WorldWideScience

Sample records for beamline front ends

  1. Alignment and commissioning of the APS beamline front ends

    International Nuclear Information System (INIS)

    Fifteen out of forty initial beamline front ends have been installed in the storage-ring tunnel at the 7-GeV Advanced Photon Source (APS). For the front-end installation, a four-step alignment process was designed and consists of (1) prealigning the front-end components with support tables in the preassembly area, (2) installing the components with tables in the storage-ring tunnel and aligning relative to the APS global telescope survey network, (3) confirming the alignment using a tooling laser alignment system, and (4) performing adjustments with the synchrotron-radiation beam during commissioning. The laser alignment system and the prealignment database have been of great importance for the expedient maintenance of front-end components. These tools are very important to a large synchrotron radiation facility, such as the APS, since they make a quick alignment setup possible and minimize alignment time inside the tunnel. This paper will present the four-step alignment process, the laser alignment system, and discuss the alignment confirmation results. copyright 1996 American Institute of Physics

  2. Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

    International Nuclear Information System (INIS)

    Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al2O3)- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

  3. Vacuum tests of a beamline front-end mock-up at the Advanced Photon Source

    International Nuclear Information System (INIS)

    A-mock-up has been constructed to test the functioning and performance of the Advanced Photon Source (APS) front ends. The mock-up consists of all components of the APS insertion-device beamline front end with a differential pumping system. Primary vacuum tests have been performed and compared with finite element vacuum calculations. Pressure distribution measurements using controlled leaks demonstrate a better than four decades of pressure difference between the two ends of the mock-up. The measured pressure profiles are consistent with results of finite element analyses of the system. The safety-control systems are also being tested. A closing time of ∼20 ms for the photon shutter and ∼7 ms for the fast closing valve have been obtained. Experiments on vacuum protection systems indicate that the front end is well protected in case of a vacuum breach

  4. Vacuum tests of a beamline front-end mock-up at the Advanced Photon Source

    International Nuclear Information System (INIS)

    A mock-up has been constructed to test the functioning and performance of the Advanced Photon Source (APS) front ends. The mock-up consists of all components of the APS insertion-device beamline front end with a differential pumping system. Primary vacuum tests have been performed and compared with finite element vacuum calculations. Pressure distribution measurements using controlled leaks demonstrate a better than four decades of pressure difference between the two ends of the mock-up. The measured pressure profiles are consistent with results of finite element analyses of the system. The safety-control systems are also being tested. A closing time of ∼20 ms for the photon shutter and ∼7 ms for the fast closing valve have been obtained. Experiments on vacuum protection systems indicate that the front end is well protected in case of a vacuum breach

  5. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  6. First photon-shutter development for APS insertion device beamline front ends

    Science.gov (United States)

    Shu, Deming; Nian, H. L. Thomas; Wang, Zhibi; Collins, Jeffrey T.; Ryding, David G.; Kuzay, Tuncer M.

    1993-02-01

    One of the most critical components on the Advanced Photon Source (APS) insertion device (ID) beamline front ends is the first photon shutter. It operates in two modes to fully intercept the high total power and high-heat-flux ID photon beam in seconds (normal mode) or in less than 100 ms (emergency fast mode). It is designed to operate in ultra high vacuum (UHV). The design incorporates a multi-channel rectangular bar, bent in a `hockey stick' configuration, with two-point suspension. The flanged end is an articulated bellows with rolling hinges. The actuation end is a spring-assisted, pneumatic fail-safe flexural pivot type. The coolant (water) channels incorporate brazed copper foam to enhance the heat transfer, a tube technology particular to the APS. The design development, and material aspects, as well as the extensive thermal and vibrational analyses in support of the design, are presented in this paper.

  7. Dynamic vacuum analysis for APS high heat flux beamline front ends using optical ray-tracing simulation methods

    International Nuclear Information System (INIS)

    The high-power and high-flux x-ray beams produced by third generation synchrotron radiation sources such as the Advanced Photon Source (APS) can cause significantly high gas desorption rates on beamline front-end components if beam missteering occurs. The effect of this gas desorption needs to be understood for dynamic vacuum analysis. To simulate beam missteering conditions, optical ray-tracing methods have been employed. The results of the ray-tracing analysis have been entered into a system-oriented vacuum program to provide dynamic vacuum calculations for determination of pumping requirements for the beamline front-ends. The APS will provide several types of synchrotron radiation sources, for example, undulators, wigglers, and bending magnets. For the purpose of this study, the wiggler source was chosen as a ''worst case'' scenario due to its high photon flux, high beam power, and relatively large beam cross section

  8. Dynamic vacuum analysis for APS high heat flux beamline front ends using optical ray-tracing simulation methods

    International Nuclear Information System (INIS)

    The high-power and high-flux x-ray beams produced by third generation synchrotron radiation sources such as the Advanced Photon Source (APS) can cause significantly high gas desorption rates on beamline front-end components if beam missteering occurs. The effect of this gas desorption needs to be understood for dynamic vacuum analysis. To simulate beam missteering conditions, optical ray-tracing methods have been employed. The results of the ray-tracing analysis have been entered into a system-oriented vacuum program to provide dynamic vacuum calculations for determination of pumping requirements for the beamline front-ends. The APS will provide several types of synchrotron radiation sources, for example, undulators, wigglers, and bending magnets. For the purpose of this study, the wiggler source was chosen as a worst case scenario due to its high photon flux, high beam power, and relatively large beam cross section

  9. Redesign and Reconstruction of the Equipment Protection Systems for the Upgrading Front Ends and Beamlines at BSRF

    International Nuclear Information System (INIS)

    The BEPC(Beijing Electron-Positron Collider) is upgraded to be BEPCII, a two-ring Electron-Positron collider. Due to the construction of the BEPCII and upgrade of the existing front ends and beamlines, all the existing EPSs(Equipment Protection Systems) have to be redesigned and reconstructed at BSRF. All the redesigned EPSs for the upgrading front ends and beamlines are a PLC- and SCADA-based equipment protection and control and monitoring system. The EPSs are used to protect BEPCII two storage rings vacuum against vacuum failures in a beamline, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. For the high-power wiggler beam lines, a fast movable mask is used to protect the blade of a fast-closing valve from damage when the fast-closing valve is triggered to close, which does not need to dump the electron beam running in BEPCII outer ring. In addition, all redesigned PLC- based EPSs are used to communicate with the same centralized monitoring computer to monitor a variety of parameters from all PLC- based EPS systems. The monitoring computer runs the SCADA (Supervisory Control And Data Acquisition) software with its own web server. Graphical HMI interfaces are used to display a few overall views of all front-end equipment operation status and the further detailed information for each EPS in a different pop-up window. On the web services, the SCADA-based centralized monitoring system provides a web browse function, etc. The design of the reconstructed systems is described in this paper

  10. Front end for high-repetition rate thin disk-pumped OPCPA beamline at ELI-beamlines

    Science.gov (United States)

    Green, Jonathan T.; Novák, Jakub; Antipenkov, Roman; Batysta, František; Zervos, Charalampos; Naylon, Jack A.; Mazanec, TomáÅ.¡; Horáček, Martin; Bakule, Pavel; Rus, Bedřich

    2015-02-01

    The ELI-Beamlines facility, currently under construction in Prague, Czech Republic, will house multiple high power laser systems with varying pulse energies, pulse durations, and repetition rates. Here we present the status of a high repetition rate beamline currently under construction with target parameters of 20 fs pulse duration, 100 mJ pulse energy, and 1 kHz repetition rate. Specifically we present the Yb:YAG thin disk lasers which are intended to pump picosecond OPCPA, synchronization between pump and signal pulses in the OPCPA, and the first stages of OPCPA.

  11. New x-ray pink-beam profile monitor system for the SPring-8 beamline front-end.

    Science.gov (United States)

    Takahashi, Sunao; Kudo, Togo; Sano, Mutsumi; Watanabe, Atsuo; Tajiri, Hiroo

    2016-08-01

    A new beam profile monitoring system for the small X-ray beam exiting from the SPring-8 front-end was developed and tested at BL13XU. This system is intended as a screen monitor and also as a position monitor even at beam currents of 100 mA by using photoluminescence of a chemical vapor deposition-grown diamond film. To cope with the challenge that the spatial distribution of the photoluminescence in the vertical direction is too flat to detect the beam centroid within a limited narrow aperture, a filter was installed that absorbs the fundamental harmonic concentrated in the beam center, which resulted in "de-flattening" of the vertical distribution. For the measurement, the filter crossed the photon beam vertically at high speed to withstand the intense heat flux of the undulator pink-beam. A transient thermal analysis, which can simulate the movement of the irradiation position with time, was conducted to determine the appropriate configuration and the required moving speed of the filter to avoid accidental melting. In a demonstration experiment, the vertically separated beam profile could be successfully observed for a 0.8 × 0.8 mm(2) beam shaped by an XY slit and with a fundamental energy of 18.48 keV. The vertical beam centroid could be detected with a resolution of less than 0.1 mm. PMID:27587104

  12. ADSL Analog Front End

    OpenAIRE

    Stojković, Nino

    2006-01-01

    In this paper the Asymmetric Digital Subscriber Line (ADSL) analog front end (AFE) designs are described and compared. AFE is the part of ADSL modems most responsible for quality signal transmission over phone wires. It can be divided into the transmitting path (TX) circuitry, the receiving path (RX) circuitry and the hybrid network and transformer. The operations and realizations of each functional block are presented. There are the D/A converter, the filter and the line driver in the TX pat...

  13. Intelligent Front Ends

    OpenAIRE

    Bundy, Alan

    1984-01-01

    An intelligent front end is a user-friendly interface to a software package, which uses Artificial Intelligence techniques to enable the user to interact with the computer using his/her own terminology rather than that demanded by the package. Several such systems exist and provide interfaces for finite element. statistical and simulation packages, and the area is an important area of growth for expert systems. In this paper we discuss the techniques required in an intelligent ...

  14. New Front End Technology

    Energy Technology Data Exchange (ETDEWEB)

    Pennington, D; Jovanovic, I; Comaskey, B J

    2001-02-01

    The next generation of Petawatt class lasers will require the development of new laser technology. Optical parametric chirped pulse amplification (OPCPA) holds a potential to increase the peak power level to >10 PW with existing grating technology through ultrashort pulses. Furthermore, by utilizing a new type of front-end system based on optical parametric amplification, pulses can be produced with substantially higher contrast than with Ti:sapphire regenerative amplifier technology. We performed extensive study of OPCPA using a single crystal-based OPA. We developed a replacement for Ti:sapphire regenerative amplifier for high peak power lasers based on OPCPA, with an output of 30 mJ, at 10 Hz repetition rate and 16.5 nm spectral bandwidth. We developed a 3D numerical model for OPCPA and we performed a theoretical study of influences of pump laser beam quality on optical parametric amplification. Our results indicate that OPCPA represents a valid replacement for Ti:sapphire in the front end of high energy short pulse lasers.

  15. SNS Front End Diagnostics

    CERN Document Server

    Doornbos, J; Oshatz, D; Ratti, A; Staples, J W

    2000-01-01

    The Front End of the Spallation Neutron Source (SNS) extends from the Ion Source (IS), through a 65 keV LEBT, a 402.5 MHz RFQ, a 2.5 MeV MEBT, ending at the entrance to the DTL. The diagnostics suite in this space includes stripline beam position and phase monitors (BPM), toroid beam current monitors (BCM), and an emittance scanner. Provision is included for beam profile measurement, either gas fluorescence, laser-based photodissociation, or a crawling wire. Mechanical and electrical design and prototyping of BPM and BCM subsystems are proceeding. Significant effort has been devoted to packaging the diagnostic devices in minimal space. Close ties are maintained to the rest of the SNS effort, to ensure long term compatibility of interfaces and in fact share some design work and construction. The data acquisition, digital processing, and control system interface needs for the BPM, BCM, and LEBT diagnostic are similar, and we are committed to using an architecture common with the rest of the SNS collaboration.

  16. Jitter-compensated Yb:YAG thin-disc laser as a pump for the broadband OPCPA front-end of the ELI-Beamlines system

    Czech Academy of Sciences Publication Activity Database

    Antipenkov, Roman; Green, Jonathan T.; Batysta, František; Naylon, Jack A.; Zervos, Charalampos; Novák, Jakub; Bakule, Pavel; Rus, Bedřich

    Bellingham: SPIE, 2014 - (Clarkson, W.; Shori, R.), "895917-1"-"895917-7". (Proceedings of SPIE. 8959). ISBN 978-0-8194-9872-4. ISSN 0277-786X. [Solid State Lasers XXIII - Technology and Devices. San Francisco (US), 02.02.2014-04.02.2014] R&D Projects: GA MŠk ED1.1.00/02.0061 Grant ostatní: ELI Beamlines(XE) CZ.1.05/1.1.00/02.0061 Institutional support: RVO:68378271 Keywords : thin-disc laser * timing jitter * OPCPA Subject RIV: BH - Optics, Masers, Lasers

  17. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  18. FRIB Front End Design Status

    CERN Document Server

    Pozdeyev, E; Machicoane, G; Morgan, G; Rao, X; Zhao, Q; Stovall, J; Vorozhtsov, S; Sun, L

    2013-01-01

    The Facility for Rare Isotope Beams (FRIB) will provide a wide range of primary ion beams for nuclear physics research with rare isotope beams. The FRIB SRF linac will be capable of accelerating medium and heavy ion beams to energies beyond 200 MeV/u with a power of 400 kW on the fragmentation target. This paper presents the status of the FRIB Front End designed to produce uranium and other medium and heavy mass ion beams at world-record intensities. The paper describes the FRIB high performance superconducting ECR ion source, the beam transport designed to transport two-charge state ion beams and prepare them for the injection in to the SRF linac, and the design of a 4-vane 80.5 MHz RFQ. The paper also describes the integration of the front end with other accelerator and experimental systems.

  19. Supporting radical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Gertsen, Frank

    2011-01-01

    An organization benefits substantially by improving front end innovation (FEI) actively and may thereby enhance the chances of developing innovations, as emphasized by several authors e.g. Reinertsen (1999), Dahl & Moreau (2002), Boeddrich (2004), Williams et al. (2007) and Vernorn et al. (2008......). Pharmaceutical innovation is unique, as it opposed to most other industries’ product development is science-driven and not customer-driven. In addition, the pharmaceutical FEI, as represented by research, lasts up to 5 years and the entire R&D process constitutes a period of 10-12 years, which is highly...... regulated by external authorities, e.g. The American Food and Drug Administration (FDA). The research aim of this paper is: to contribute to the field of FEI by studying how FEI can be actively supported within the industry specific context of the pharmaceutical industry, and through a conceptual discussion...

  20. The upgraded Tevatron front end

    International Nuclear Information System (INIS)

    We are replacing the computers which support the CAMAC crates in the Fermilab accelerator control system. We want a significant performance increase, but we still want to be able to service scores of different varieties of CAMAC cards in a manner essentially transparent to console applications software. Our new architecture is based on symmetric multiprocessing. Several processors on the same bus, each running identical software, work simultaneously at satisfying different pieces of a console's request for data. We dynamically adjust the load between the processors. We can obtain more processing power by simply plugging in more processor cards and rebooting. We describe in this paper what we believe to be the interesting architectural features of the new front-end computers. We also note how we use some of the advanced features of the MultibusTM II bus and the Intel 80386 processor design to achieve reliability and expandability of both hardware and software. (orig.)

  1. SPD very front end electronics

    International Nuclear Information System (INIS)

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  2. Front-end Combination Component Of Fixed Mask And Absorber

    International Nuclear Information System (INIS)

    A front-end combination component of fixed mask and absorber is a device that combines a fixed mask and a photon absorber in one body to save space, setup work and maintenance in the photon beamline front-end. The SPring-8 undulator absorber consists of an upper V-shaped photon absorber part and a lower rectangular beam-transfer channel part. The upper wall of the beam-transfer channel is cut in the V-shape notch as the photon absorber. The combination component design based on the absorber is adopted. The photon duct part is modified in the shape of the fixed mask. The combination component moves up and down. In the upper limit, it acts as the mask and the beam-transfer channel. In the lower limit, it acts as the photon absorber. Design details of the component and its commissioning are presented

  3. User friendly far front ends

    International Nuclear Information System (INIS)

    For years controls group hardware designers have designed microprocessor systems to accomplish specific functions such as refrigeration control. These systems often require years of software effort. The backlog of requests for even simple additions or modifications to software in embedded controllers has become overwhelming. We discuss the requirements of ''far forward'' controllers. Can we build a system that is modular enough to be configurable for specific applications without sacrificing performance? The hardware and software framework must be complete enough to isolate the end user from the peculiarities of bit and byte manipulation, but still allow system specifics to be implanted by the user. It is time to provide embedded controller systems as easy to use as workstation consoles

  4. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before. The...... processes demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and...... analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

  5. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  6. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik;

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development. This con...... market requirements....

  7. JFET-CMOS microstrip front-end

    International Nuclear Information System (INIS)

    While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper. (orig.)

  8. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  9. CDF front end electronics: The RABBIT system

    International Nuclear Information System (INIS)

    A new crate-based front end system has been built featuring low cost, compact packaging, fast readout, command capability, 16 bit digitiziation, and a high degree of redundancy. The crate can contain a variety of instrumentation modules and is designed to be placed near the detector. Remote, special purpose processors direct the data readout. Channel-by-channel pedestal subtraction and threshold comparison in the crate allow the skipping of empty channels. The system is suitable for the readout of a very large number of channels. (orig.)

  10. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  11. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  12. Front-end electronics development at BNL

    International Nuclear Information System (INIS)

    AT BNL the monolithic front-end electronics development effort is an outgrowth of work in discrete and hybrid circuits over the past 30 years. BNL's area of specialization centers on circuits for precision amplitude measurement, with signal-to-noise ratios of 100:1 and calibration to the same level of precision. Circuits are predominantly classical, continuous-time implementation of the functions now performed by hybrids, with little or no loss of performance. Included in this category are charge and current-sensitive preamplifiers, pulse shapers, sample/hold, multiplexing, and associated calibration and control circuits. Presently integration densities are limited to 16 channels per chip. Two examples are presented to illustrate the techniques needed to adopt hybrid circuits to the constraints of monolithic CMOS technology. They are programmable pulse shapes and a charge-sensitive preamp for very low detector capacitance

  13. Driving the LHCb front-end readout

    CERN Document Server

    Guzik, Z; Jost, B

    2004-01-01

    The timing and fast control (TFC) system is responsible for controlling and distributing timing, trigger and synchronous commands to the LHCb front-end (FE) electronics. It is different from the equivalent systems of the other LHC experiments in that it has to support two levels of high-rate triggers. Furthermore, the TFC mastership of a configurable ensemble of FE electronics is centralized in one module: the Readout Supervisor. A pool of optional Readout Supervisors allows mastering of all or separate combinations of subsystems in parallel by remote programming of a patch panel in the distribution network. The speed requirements and the multifunctionality of the Readout Supervisor necessitate optimal technological solutions. At the same time the logic must be modifiable to support extensions or changes in the running modes. A first prototype has been built using field-programmable gate arrays (FPGAs) for the entire logic and it has been tested successfully. This paper gives an overview of the system archite...

  14. The upgraded CDF front end electronics for calorimetry

    International Nuclear Information System (INIS)

    The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

  15. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  16. Design, fabrication, installation and commissioning of water-cooled beam viewer for undulator front-ends of Indus-2

    International Nuclear Information System (INIS)

    A water-cooled beam viewer is developed indigenously to observe the bright synchrotron light coming from recently installed undulators in Indus-2 storage ring at RRCAT, Indore. The beam viewer is installed in the undulator front-end. The frontend is a long ultra high vacuum (UHV) assembly consisting of UHV valves, shutters, vacuum pumps and beam diagnostic devices. The front-end acts as an interface between Indus-2 ring and beamline. The beam viewer uses a fluorescent sheet of Chromium doped Alumina (CHROMOX) which produces visible fluorescent light when bright synchrotron light from the undulator falls on it. This visible fluorescent light is observed through a glass window by a CCD camera. The beam viewer has been successfully tested and commissioned in Indus-2 front-end for undulator. At present, the beam viewer is operating under vacuum of 5 x 10-10 mbar in the Indus-2 undulator front-end

  17. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  18. Front-end equipment protection system at the Advanced Photon Source

    International Nuclear Information System (INIS)

    The front-end Equipment Protection System (FE-EPS) at the Advanced Photon Source (APS) is a high reliability, fail-safe single-chain interlock and control system. It consists of an Allen-Bradley PLC-5/30 processor, local and remote I/O racks, monitoring and control panels, serial communication links, and field devices. Each front end is equipped with a dedicated EPS. The system monitors a variety of sensors (e.g., vacuum, cooling water, temperature, pneumatic pressure), and controls front-end (FE) photon shutters and UHV valves. The main functions of the FE-EPS are to guard the integrity of the storage ring vacuum against vacuum excursions in the FE and beam transport line, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. The FE-EPS interfaces to six other APS interlock and control systems. Information about FE interlocks and devices is displayed on UNIX machines using the EPICS software tool kit. The system design is presented. copyright 1996 American Institute of Physics

  19. RF photonic front-end integrating with local oscillator loop.

    Science.gov (United States)

    Yu, H; Chen, M; Gao, H; Yang, S; Chen, H; Xie, S

    2014-02-24

    Broadband Radio frequency (RF) photonic front-ends are one of the vital applications of the microwave photonics. A tunable and broadband RF photonic front-end integrating with the optoelectronic oscillator (OEO) based local oscillator has been proposed and experimentally demonstrated, in which only one phase modulator (PM) is employed thanks to the characteristic of the PM. The silicon-on-insulator based narrow-bandwidth band-pass filter is introduced for signal processing. The application condition of the proposed RF photonic front-end has been discussed and the performance of the front-end has also been measured. The SFDR at a frequency of about 7.02 GHz is measured to be 88.6 dB-Hz(2/3). PMID:24663712

  20. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  1. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  2. Node for Front-End Developers

    CERN Document Server

    Means, Garann

    2012-01-01

    If you know how to use JavaScript in the browser, you already have the skills you need to put JavaScript to work on back-end servers with Node. This hands-on book shows you how to use this popular JavaScript platform to create simple server applications, communicate with the client, build dynamic pages, work with data, and tackle other tasks. Although Node has a complete library of developer-contributed modules to automate server-side development, this book will show you how to program with Node on your own, so you truly understand the platform. Discover firsthand how well Node works as a we

  3. Front-end components for SPring-8 insertion devices (finite element analysis for a heat absorber)

    International Nuclear Information System (INIS)

    SPring-8 is a third generation synchrotron facility that provides high-brilliance synchrotron radiations in the x ray region. The electron or positron beam with an energy of 8 GeV is stored up to 100 mA in the storage ring with a circumference of 1,435.95 m. Of 44 straight sections in the storage ring, 38 straight sections are available for insertion device beamlines. The insertion devices installed in the 8 GeV storage ring produce higher total power and power density compared with those in the 2-3 GeV storage rings since the total power is proportional to the square of the stored electron such or positron energy and the aperture of the radiation cone is inversely proportional to the electron or positron energy. Substantial amounts of heat power radiated from the undulator and wiggler are deposited on the components of the front-end. The heat absorber intercept the synchrotron radiation beams to protect front-end components placed downstream. In this work, the authors have studied the heat absorber in the insertion device front-end by the finite element analysis

  4. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    part and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The...... paper examines a range of such front end devices such as the ‘idea-bank’ and ‘front -end champions’, discussing how particular devices serve to configure hetero-geneous networks to in some respects facilitate, while in others, hamper, the productive engage-ment of the networks in the mobilisation of...... dealing with uncertain conditions in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other...

  5. Report of the subgroup on deadtimeless front-end electronics

    International Nuclear Information System (INIS)

    The subgroup on deadtimeless front-end electronics and data acquisition systems met for two days on June 28-29. This report summarizes some of the material presented at these discussions. It concentrates on the need for and technical obstacles to the development of high rate deadtimeless front-end electronics for silicon vertex trackers. The large yield of b bar b events at hadron colliders indicate the desirability of level 1 trigger rates of order 50-100 kHz. In order to eliminate undesirable deadtime the required front-end electronics needs to be fully pipelined and capable of supporting subsequent trigger levels without incurring any deadtime. In these discussions it has been assumed that the level 1 latency time is of order 2-4 μs

  6. Spectral Signature Analysis – BIST for RF Front-Ends

    Directory of Open Access Journals (Sweden)

    D. Lupea

    2003-01-01

    Full Text Available In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test – BIST for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC at critical building blocks.

  7. Spectral Signature Analysis - BIST for RF Front-Ends

    Science.gov (United States)

    Lupea, D.; Pursche, U.; Jentschel, H.-J.

    2003-05-01

    In this paper, the Spectral Signature Analysis is presented as a concept for an integrable self-test system (Built-In Self-Test - BIST) for RF front-ends is presented. It is based on modelling the whole RF front-end (transmitter and receiver) on system level, on generating of a Spectral Signature and of evaluating of the Signature Response. Because of using multi-carrier signal as the test signature, the concept is especially useful for tests of linearity and frequency response of front-ends. Due to the presented method of signature response evaluation, this concept can be used for Built-In Self-Correction (BISC) at critical building blocks.

  8. CERN Front-End Software Architecture for Accelerator Controls

    CERN Document Server

    Arruat, M; Guerrero, A; Jackson, S; Ludwig, M; Nougaret, J L

    2003-01-01

    To overcome the current diversity in AB front end equipment software and pave the way towards LHC for efficient development, diagnostic and maintenance in this area, the CERN Accelerator Controls group launched in April 2003 a project to develop the new CERN accelerator standard infrastructure for front end software. This development is based on the infrastructure recently born to handle the SPS beam measurement systems and extends it to handle the PS and SPS multi-cycling schemes, the future requirements needed for LHC as well as providing a good backward compatibility with the existing infrastructures. The project, approach and first deliverables are presented.

  9. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  10. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  11. A multitasking, multisinked, multiprocessor data acquisition front end

    International Nuclear Information System (INIS)

    The authors have developed a generalized data acquisition front end system which is based on MC68020 processors running a commercial real time kernel (rhoSOS), and implemented primarily in a high level language (C). This system has been attached to the back end on-line computing system at NSCL via our high performance ETHERNET protocol. Data may be simultaneously sent to any number of back end systems. Fixed fraction sampling along links to back end computing is also supported. A nonprocedural program generator simplifies the development of experiment specific code

  12. Context-aware adaptation of service front-ends

    OpenAIRE

    Caminero Gil, Francisco Javier; Patern?, Fabio; Vanderdonckt, Jean

    2012-01-01

    Ambient Intelligence implies the need for context-aware adaptation of user interfaces. This adaptation with respect to the context of use is applicable to a wide spectrum of interactive applications ranging from front ends of web services, information systems to multimedia and multimodal applications. Although the ultimate goal of this adaptation is always for the ultimate benefit of the end user, many approaches and techniques have been used to various degrees of experience and maturity that...

  13. Front End Loader Operator. Open Pit Mining Job Training Series.

    Science.gov (United States)

    Savilow, Bill

    This training outline for front end loader operators, one in a series of eight outlines, is designed primarily for company training foremen or supervisors and for trainers to use as an industry-wide guideline for heavy equipment operator training in open pit mining in British Columbia. Intended as a guide for preparation of lesson plans both for…

  14. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  15. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  16. SIROCCO IV: Front end readout processor for DELPHI Microvertex

    International Nuclear Information System (INIS)

    The SIROCCO IV is a Fastbus front end module for for DELPHI Microvertex Silicon-Strip Detector. Each Fastbus board can receive analog pulse heights from up to 2x2048 silicon strips, convert them into digital and perform extensive corrections and intelligent zero-suppression before sending the reduced data to the Fastbus data acquisition system of DELPHI. (author). 3 refs, 1 fig

  17. Thermo-mechanical optimization of Fixed Mask 2 for APS front ends

    International Nuclear Information System (INIS)

    Fixed mask 2 (FM2) is one of the critical elements on the front end of the beamlines at the Advanced Photon Source (APS) now under construction at Argonne National Laboratory (ANL). The FM2 uses an enhanced heat transfer tube developed at ANL. Due to large thermal loads on these components, inclined geometry is used in the design to spread the footprint of the x-ray beam. Even then, thermal loads are very critical. To address the thermal and thermo-mechanical issues, analytical studies have been applied to a simplified model of the FM2 tube. The maximum temperature and maximum effective stress have been parametrically studied. Results for maximum temperatures and stresses are obtained and compared with the available strength/fatigue data for the materials proposed for the fixed mask design

  18. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  19. Broadband RF front-end using microwave photonics filter.

    Science.gov (United States)

    Wang, Jingjing; Chen, Minghua; Liang, Yunhua; Chen, Hongwei; Yang, Sigang; Xie, Shizhong

    2015-01-26

    We propose and demonstrate a novel RF front-end with broadened processing bandwidth, where a tunable microwave photonic filter based on optical frequency comb (OFC) is incorporated to accomplish simultaneous down-conversion and filtering. By designing additional phase shaping and time delay controlling, the frequency tunability of the system could be enhanced. More importantly, the beating interferences generated from broadband RF input could also be suppressed, which help to break the limitation on the processing bandwidth. In our experiments, a photonics RF receiver front-end for RF input with wide bandwidth of almost 20 GHz was realized using 10-GHz-space OFC, where the center frequency of the pass band signals could be tuned continuously. PMID:25835844

  20. The front end electronics of the LHCb straw tube tracker

    International Nuclear Information System (INIS)

    The LHCb experiment is a single-arm spectrometer, designed to study B-hadron decays at the Large Hadron Collider (LHC). It is crucial to accurately and efficiently track the charged decay products with the Outer Tracker straw tube detector, in the high-density particle environment of the LHC. The Outer Tracker Front End electronics provide the precise (0.5 ns) drift-time measurement, at an average occupancy of 5% and at a 1 MHz trigger rate. The tracking procedure requires high-efficiency, while at the same time putting stringent limits on the noise level. The mass production and installation of 450 fully operational Front End boxes is completed. Quality checks have been performed at several stages, at the level of individual boards and at the global level with dedicated test systems mimicking the real detector and capable of simulating all the readout functionalities. An excellent overall threshold uniformity is achieved with low noise levels.

  1. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  2. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  3. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  4. Front-end data processing the SLD data acquisition system

    International Nuclear Information System (INIS)

    The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

  5. Terahertz antennas with silicon micromachined front-end

    OpenAIRE

    Chattopadhyay, Goutam; Reck, Theodore; Jung Kubiak, Cecile; Lee, Choonsup; Siles, Jose Vicente; Chahat, Naser; Cooper, Ken; Schlecht, Erich T.; Alonso del Pino, María; Mehdi, Imran

    2014-01-01

    Increasingly, terahertz systems are being used for multi-pixel receivers for different applications from mapping the star-forming regions of galaxies to stand-off radar imaging. Since microstrip patch antennas are too lossy and corrugated horn antenna arrays are difficult to machine at terahertz frequencies, suitable antenna array designs have been one of the key area of research for this field. Moreover, silicon micromachined waveguide housing for front-end integration is becoming very popul...

  6. Broadband beamforming compensation algorithm in CI front-end acquisition

    OpenAIRE

    Chen, Yousheng; Gong, Qin

    2013-01-01

    Background To increase the signal to noise ratio (SNR) and to suppress directional noise in front-end signal acquisition, microphone array technologies are being applied in the cochlear implant (CI). Due to size constraints, the dual microphone-based system is most suitable for actual application. However, direct application of the array technology will result in the low frequency roll-off problem, which can noticeably distort the desired signal. Methods In this paper, we theoretically analyz...

  7. Green radio despite "Dirty RF" front-end

    OpenAIRE

    Ariaudo, Myriam; Fijalkow, Inbar; Gautier, Jean-Luc; Brandon, Mathilde; Aziz, Babar; Milevsky, Borislav

    2012-01-01

    In this article, we show that the non-ideal Radio-Frequency (RF) front-ends have to be corrected in order to contribute in a Green radio development. In fact, the effects of typical RF imperfections, like nonlinearities, carrier frequency offsets, and IQ imbalances, can be compensated for, when digital correction algorithms are applied. Such algorithms enable Green applications (e.g., Orthogonal Frequency Division Multiple Access for the uplink) despite a restrictive RF imperfection, or allow...

  8. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  9. The Giga Bit Transceiver based Expandable Front-End (GEFE)—a new radiation tolerant acquisition system for beam instrumentation

    International Nuclear Information System (INIS)

    The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multi-purpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups

  10. The Giga Bit Transceiver based Expandable Front-End (GEFE)—a new radiation tolerant acquisition system for beam instrumentation

    Science.gov (United States)

    Barros Marin, M.; Boccardi, A.; Donat Godichal, C.; Gonzalez, J. L.; Lefevre, T.; Levens, T.; Szuk, B.

    2016-02-01

    The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multi-purpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups.

  11. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  12. Smart TV front-end application for cloud computing

    OpenAIRE

    Miguel Montero, Jaime

    2012-01-01

    This master project focuses on the development of a front-end applicationfor cloud computing. Traditionally, televisions have been excluded from thealways connected world. With the appearance of the smart televisions it isnow possible to connect them to the Internet. However, there still exists agap between televisions and services in the cloud.To solve the problem,we have developed a JavaScript application. This application allows the user to log into their CloudMe account from a SamsungSmar...

  13. Front-end electronics for the LZ experiment

    Science.gov (United States)

    Morad, James; LZ Collaboration

    2016-03-01

    LZ is a second generation direct dark matter detection experiment with 5.6 tonnes of liquid xenon active target, which will be instrumented as a two-phase time projection chamber (TPC). The peripheral xenon outside the active TPC (``skin'') will also be instrumented. In addition, there will be a liquid scintillator based outer veto surrounding the main cryostat. All of these systems will be read out using photomultiplier tubes. I will present the designs for front-end electronics for all these systems, which have been optimized for shaping times, gains, and low noise. Preliminary results from prototype boards will also be presented.

  14. Instrument Front-Ends at Fermilab During Run II

    CERN Document Server

    Meyer, Thomas; Voy, Duane; 10.1088/1748-0221/6/11/T11004

    2012-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  15. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2008-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

  16. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  17. Front-end electronics for the FAZIA experiment

    International Nuclear Information System (INIS)

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics

  18. Instrument front-ends at Fermilab during Run II

    International Nuclear Information System (INIS)

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  19. Instrument Front-Ends at Fermilab During Run II

    International Nuclear Information System (INIS)

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  20. APPLICATION OF OBJECT ORIENTED PROGRAMMING TECHNIQUES IN FRONT END COMPUTERS

    International Nuclear Information System (INIS)

    The Front End Computer (FEC) environment imposes special demands on software, beyond real time performance and robustness. FEC software must manage a diverse inventory of devices with individualistic timing requirements and hardware interfaces. It must implement network services which export device access to the control system at large, interpreting a uniform network communications protocol into the specific control requirements of the individual devices. Object oriented languages provide programming techniques which neatly address these challenges, and also offer benefits in terms of maintainability and flexibility. Applications are discussed which exhibit the use of inheritance, multiple inheritance and inheritance trees, and polymorphism to address the needs of FEC software

  1. An ASIC design for PMT front-end readout

    International Nuclear Information System (INIS)

    An ASIC of 5 channels is designed for PMT front-end readout, in Chartered 0.35 μm 2P4M COMS technology. Each channel integrates preamplifier, slow shaper, fast shaper and discriminator. The gain of pre-amp is adjustable and the time constant of slow shaper can be set to be 25 ns, 50 ns and 100 ns. The chip is used for experiments of dark mAtter detecting (HEGARD)[1]. The results of simulation show it has good dynamic range (14 bits), good linearity (1%) and good noise performAnce (<1/10 p.e.). (authors)

  2. Front-end electronics of the ALICE photon spectrometer

    Energy Technology Data Exchange (ETDEWEB)

    Yin Zhongbao, E-mail: zbyin@mail.ccnu.edu.c [Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Key Laboratory of Quark and Lepton Physics, Huazhong Normal University, Ministry of Education (China); Muller, Hans; Pimenta, Rui [CERN, PH Department, 1211 Geneva 23 (Switzerland); Roehrich, Dieter [Department of Physics and Technology, University of Bergen (Norway); Sibiriak, Iouri [Russian Research Center Kurchatov Institute, Moscow (Russian Federation); Skaali, Bernhard [Department of Physics, University of Oslo, Blindern 0316 (Norway); Wang Dong; Wang Yaping; Zhou Daicui [Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Key Laboratory of Quark and Lepton Physics, Huazhong Normal University, Ministry of Education (China)

    2010-11-01

    The photon spectrometer (PHOS) in the ALICE experiment at LHC is dedicated to measuring photons, {pi}{sup 0}'s and {eta}'s in a broad p{sub T} range from about 100 MeV/c to 100 GeV/c, providing the best possible energy and position resolution in order to narrow the {pi}{sup 0} and {eta} mass peaks and thus to increase the signal to background ratio. The front-end electronics (FEE) of the PHOS is thus required to cover a large dynamic range, to have a timing resolution better than {approx}2ns in order to discriminate against 1-2 GeV/c (anti-)neutrons, and to provide high p{sub T} trigger to select rare high p{sub T} events. In addition, to equalize the gains of individual detector channels, it is desired that the PHOS FEE can regulate the bias voltage of APD. In this paper, we will present the performance and status of the 32-channel low noise front-end electronics for the PHOS with a dynamic range of 14 bits. Measurements with LED pulse at laboratory and results from beam test with the first PHOS module at T10 of the CERN PS show that its performance fulfills the PHOS requirements.

  3. Front end support systems for the Advanced Photon Source

    International Nuclear Information System (INIS)

    The support system designs for the Advanced Photon Source (APS) front ends are complete and will be installed in 1994. These designs satisfy the positioning and alignment requirements of the front end components installed inside the storage ring tunnel, including the photon beam position monitors, fixed masks, photon and safety shutters, filters, windows, and differential pumps. Other components include beam transport pipes and ion pumps. The designs comprise 3-point kinematic mounts and single axis supports to satisfy various multi-direction positioning requirements from course to ultra-precise. The confined space inside the storage ring tunnel has posed engineering challenges in the design of these devices, considering some components weigh as much as 500 kg. These challenges include designing for mobility during commissioning and initial alignment, mechanical and thermal stability, and precise low profile vertical and horizontal positioning. As a result, novel stages and kinematic mounts have emerged with modular and standard designs. This paper will discuss the diverse group of support systems, including specifications and performance data of the prototypes

  4. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  5. Digital front end electronics design for the EUSO photon detector

    International Nuclear Information System (INIS)

    In this paper we will present the design status of the Digital Front End Electronic system (DFEE), that will be used for the EUSO photon detector. The DFEE is able to count the single photoelectrons coming form the detector for a given time period, store the numbers in a memory buffer and read them out after a trigger, using a serial communication line. Because of space, mass and power consumption constraints, the system will be implemented in an ASIC using a deep submicron technology. The actual design follows the original ideas of the system, though adding several new functionalities. A fully functional prototype chip has been submitted for fabrication in fall 2002. Extensive tests will be performed on it both with bench instrumentations and with the real sensor (the multi anode photomultiplier Hamamatsu R7600-M64), expecting significant results by early Summer 2003. Future work is needed to convert the design into a more robust RAD-hard technology, suitable for space applications and to include in the final die an additional circuit used to optimize the performances at high photons rates: the Analog Front End Electronics (AFEE). Moreover the base board used to house the multi anode photomultipliers is presented: it is the back-bone of the microcell and will be the basic block used to build up the EUSO focal surface

  6. Environmental surveillance of front end fuel cycle facilities

    International Nuclear Information System (INIS)

    Uranium and thorium are used as fuel for nuclear reactors. The front end of fuel cycle includes the processes through which these materials undergo, till they are ready to go into a reactor as fuel. The processes of front end fuel cycle include physical and chemical separation and purification steps. During the processing effluents are generated, which need to be taken care of, such that they are rendered environmentally benign. The Environmental Assessment Division of Bhabha Atomic Research Centre carried out environmental surveillance on a continued basis in order to ensure compliance with the regulatory norms and carries out measurements and modeling for environmental impact assessment. Uranium Corporation of India Ltd (UCIL) carried out mining and processing of uranium ore to produce Magnesium Diuranate (MDU). Environmental survey, Radiological, Industrial hygiene and safety status of UCIL operations is carried out for their operations located at Jaduguda, Bhatin, Narwapahar and Turamdit in Jharkhand state as well as their projects at KP Mouthabah in Meghalaya state, Bagjata in Jharkhand state and Tummalapalle in A.P. state. (author)

  7. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  8. Source-Constrained Recall: Front-End and Back-End Control of Retrieval Quality

    Science.gov (United States)

    Halamish, Vered; Goldsmith, Morris; Jacoby, Larry L.

    2012-01-01

    Research on the strategic regulation of memory accuracy has focused primarily on monitoring and control processes used to edit out incorrect information after it is retrieved (back-end control). Recent studies, however, suggest that rememberers also enhance accuracy by preventing the retrieval of incorrect information in the first place (front-end…

  9. 40 CFR 63.486 - Batch front-end process vent provisions.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vent provisions... Batch front-end process vent provisions. (a) Batch front-end process vents. Except as specified in paragraph (b) of this section, owners and operators of new and existing affected sources with batch...

  10. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end process vent or aggregate batch vent stream at an affected source shall submit the information...

  11. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... process vent, reduce organic HAP emissions for the batch cycle by 90 weight percent using a control device... control device as it relates to continuous front-end process vents shall be used. Furthermore,...

  12. 40 CFR 63.485 - Continuous front-end process vent provisions.

    Science.gov (United States)

    2010-07-01

    ....487(e)(2) for batch front-end process vents and aggregate batch vent streams. (p) If any gas stream... halogenated continuous front-end process vent stream was controlled by a combustion device prior to June 12... continuous front-end process vents at new and existing affected sources producing an elastomer using a...

  13. Managing Front-End Innovation through Idea Markets at Novozymes

    DEFF Research Database (Denmark)

    Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank;

    2013-01-01

    Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in which...... a relatively small number of highly motivated participants screened their colleagues' inventions through an "idea market." The idea competition fulfilled its goals of generating two ideas with high growth potential within a short time, uncovering and recombining old proposals that inventors had not...... previously been able to advance in the organization and focusing managerial attention on the selection process. The campaign is an effective tool to recombine existing knowledge that had not been utilized. The process demonstrated that asking participants to comment on proposals improves idea generation and...

  14. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  15. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2010-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  16. PMF: The front end electronic of the ALFA detector

    Energy Technology Data Exchange (ETDEWEB)

    Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

    2010-11-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  17. Software defined radio platform with wideband tunable front end

    Directory of Open Access Journals (Sweden)

    Daniel Iancu

    2015-01-01

    Full Text Available The paper presents a Software Defined Radio (SDR development platform with wideband tunable RF (Radio Frequency front end. The platform is based on the SB3500 Multicore Multithreaded Vector Processor and it is intended to be used for a wide variety of communication protocols as: Time Division Duplexing/Frequency Division Duplexing Long Term Evolution (TDD/FDD LTE, Global Positioning System (GPS, Global System for Mobile/General Packet Radio Service (GSM/GPRS, Wireless Local Area Network (WLAN, Legacy Worldwide Interoperability for Microwave Access (WiMAX. As an example, we describe briefly the implementation of the LTE TDD/FDD communication protocol. As far as we know, this is the only LTE category 1 communication protocol entirely developed and executed in software (SW, without any hardware (HW accelerators.

  18. Pion Irradiation of the APV25 Front-end Chip

    CERN Document Server

    Friedl, M; Pernicka, Manfred

    2001-01-01

    The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) at CERN will include a Silicon Strip Tracker covering a sensitive area of 206m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25um deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets (SEUs) are inevitable and affect both digital and analog circuits. Eight APV25 chips (version S1) were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

  19. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking of...... staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points to the...... importance of being aligned with the strategy and mindset of the rest of the organization. This approximate alignment will induce alternative ways to set the stage for a development spaces that is configured to perform in new ways allowing for different types of development....

  20. LANSCE Control System front-end and infrastructure hardware upgrades

    International Nuclear Information System (INIS)

    The Los Alamos Neutron Science Center (LANSCE) linear accelerator drives user facilities for isotope production, proton radiography, ultra-cold neutrons, weapons neutron research and various sciences using neutron scattering. The LANSCE Control System which is in part more than 40 years old provides control and data monitoring for most devices in the linac and for some of its associated experimental-area beam lines. In Fiscal Year 2011, the control system went through an upgrade process that affected different areas of the LANSCE Control System. We improved our network infrastructure and we converted part of our front-end control system hardware to Allen Bradley ControlsLogix 5000 and National Instruments Compact RIO programmable automation controller (PAC). In this paper, we will discuss what we have done, what we have learned about upgrading the existing control system and how this will affect our future plans. (authors)

  1. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  2. Results of the SNS front end commissioning at Berkeley Lab

    Energy Technology Data Exchange (ETDEWEB)

    Ratti, A.; Ayers, J.J.; Doolittle, L.; Greer, J.B.; Keller, R.; Lewis, S.; Lionberger, C.; Monroy, M.; Pruyn, J.; Staples, J.W.; Syversrude, D.; Thomae, R.; Virostek, S.; Aleksandrov, A.; Shea, T.; SNS Accelerator Physics Group; SNS Beam Diagnostics Collaboration

    2002-08-16

    The Front-End Systems (FES) for the Spallation Neutron Source (SNS) project comprise an rf-driven H{sup -} ion source, an electrostatic 2-lens LEBT, a 2.5 MeV RFQ, followed by a 14-quadrupole, 4-rebuncher MEBT including traveling-wave fast choppers. The nominal 2.5 MeV H{sup -} beam has a current of 38 mA at a repetition rate of 60 Hz and 1 ms pulse length, for a macro duty-factor of 6%, and is chopped at a rate of approximately 1 MHz with a mini duty-factor of 68%. The normalized rms beam emittance at the MEBT exit, matching the first tank of a 402.5 MHz Alvarez linac, is measured to be approximately 0.3 {pi} mm mrad. Diagnostic elements include wire scanners, BPMs, fast current monitors, a slit-harp emittance device and RFQ field monitoring probes. The results of the beam commissioning and the operation of the RFQ and diagnostic instrumentation are reported. The entire FES was shut down at LBNL at the end of May 2002 and will be recommissioned at ORNL prior to installation of the drift-tube linac.

  3. Results of the SNS front end commissioning at Berkeley Lab

    International Nuclear Information System (INIS)

    The Front-End Systems (FES) for the Spallation Neutron Source (SNS) project comprise an rf-driven H- ion source, an electrostatic 2-lens LEBT, a 2.5 MeV RFQ, followed by a 14-quadrupole, 4-rebuncher MEBT including traveling-wave fast choppers. The nominal 2.5 MeV H- beam has a current of 38 mA at a repetition rate of 60 Hz and 1 ms pulse length, for a macro duty-factor of 6%, and is chopped at a rate of approximately 1 MHz with a mini duty-factor of 68%. The normalized rms beam emittance at the MEBT exit, matching the first tank of a 402.5 MHz Alvarez linac, is measured to be approximately 0.3 π mm mrad. Diagnostic elements include wire scanners, BPMs, fast current monitors, a slit-harp emittance device and RFQ field monitoring probes. The results of the beam commissioning and the operation of the RFQ and diagnostic instrumentation are reported. The entire FES was shut down at LBNL at the end of May 2002 and will be recommissioned at ORNL prior to installation of the drift-tube linac

  4. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del;

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture simp...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  5. TRANSNUCLEAIRE experience in research reactor fuel transportation cycle (front end and back end)

    International Nuclear Information System (INIS)

    For 35 years TRANSNUCLEAIRE has been involved in all types of transportation for research reactors (front end and back end) and laboratories: Fresh uranium (LEU and HEU); Fresh MTR elements; Irradiated MTR and Triga elements; Sources, samples, fuels rods, etc. For the front end of Research reactors and Laboratories, each year we perform an average of 10 transportations of fresh uranium representing approximatively 1 ton of material, and an average of 30 transportations of fresh MTR fuel representing about 300-400 elements. For the back end, we are carrying out for shipments for research reactors to the USA, COGEMA La Hague reprocessing plant and between CEA sites (French Atomic Energy Commission). For example around 35 loaded casks will be transported over 1999. In the present document, a shipment of low enriched uranium to be transferred from UK Atomic Energy Agency Dounreay to CERCA Romans Plant (France) and the specific operations involved will be presented. We will also update the status of our licensed new cask TN-MTR which will be used for the transportation of irradiated MTR fuel elements this year

  6. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  7. Analog front-end prototype electronics for the LHAASO WCDA

    Science.gov (United States)

    Cong, Ma; Lei, Zhao; Yu-Xiang, Guo; Jian-Feng, Liu; Shu-Bin, Liu; Qi, An

    2016-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1%@4000 P.E. and remains better than 10%@1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than the application requirements. Supported by Knowledge Innovation Program of the Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  8. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper we illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. We also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. We outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. We also present some of the difficulties encountered in applying these networks. (author) 13 figs., 9 refs

  9. The LHCb front-end electronics and data acquisition system

    CERN Document Server

    Jost, B

    2000-01-01

    The LHCb experiment is the most recently approved of the four experiments under construction at CERN's LHC accelerator. It is a special purpose experiment designed to precisely measure the CP violation parameters in the B-B system and to study rare B-decays. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. We therefore decided to implement a four-level triggering scheme. The LHCb data acquisition (DAQ) system will have to cope with an average trigger rate of 40 kHz, after two levels of hardware triggers, and an average event size of 100 kB. Thus, an event-building network which can sustain an average bandwidth of 4 GB /s is required. A powerful software trigger farm will have to be installed to reduce the rate from 40 kHz to 100 Hz of events written for permanent storage. In this paper we will outline the general architectures of the front-end electronics and of the trigger and DAQ system and the readout protocols...

  10. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  11. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  12. Thermo-mechanical parametric studies of Fixed Mask 1 and Photon Shutter 2 for APS front ends

    International Nuclear Information System (INIS)

    Fixed Mask 1 (FM1) and Photon Shutter 2 (PS2) are two of the critical elements on the front end of the beamlines at the Advanced Photon Source (APS) now under construction at Argonne National Laboratory (ANL). FMl and PS2 use an enhanced heat transfer tube developed at ANL. Due to a high localized thermal gradient on these components, inclined geometry is used in their design to spread the footprint of the x-ray beam. Complete closed form solutions for steady state conditions have been developed for the analyses of the thermal and thermo-mechanical behavior of FMl and PS2. A modified Manson-Coffin fatigue relation is proposed to predict the predict the thermal fatigue. The maximum temperatures and maximum effective stresses have been parametrically studied. Fatigue-failure life predictions are presented for the FM1 and PS2 designs

  13. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  14. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-01-01

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions. PMID:26437404

  15. Ultra-broadband OPA of supercontinuum for ELI front end

    Czech Academy of Sciences Publication Activity Database

    Batysta, F.; Hříbek, Petr; Polívka, T.; Rus, Bedřich

    Bellingham : SPIE, 2011 - (Hein, J.; Silva, L.; Korn, G.; Gizz, L.; Edwards, C.), 80800V/1-80800V/6 ISBN 9780819486707. - (Proceedings of the SPIE. 8080). [Diode-Pumped High Energy and High Power Lasers; ELI: Ultrarelativistic Laser-Matter Interactions and Petawatt Photonics . Prague (CZ), 18.04.2011-20.04.2011] R&D Projects: GA MŠk ED1.1.00/02.0061 Grant ostatní: ELI Beamlines(XE) CZ.1.05/1.1.00/02.0061 Institutional support: RVO:68378271 Keywords : OPA * ELI * supercontinuum Subject RIV: BH - Optics, Masers, Lasers

  16. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... pressure drop. (B) If the scrubber is subject to regulations in 40 CFR parts 264 through 266 that have... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... § 63.489 Batch front-end process vents—monitoring equipment. (a) General requirements. Each owner...

  17. 40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

    Science.gov (United States)

    2010-07-01

    ... reactor for that recipe. (2) A description of, and an emission estimate for, each batch emission episode... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records...

  18. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  19. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    International Nuclear Information System (INIS)

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

  20. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2014-01-01

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing the consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I.

  1. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  2. Readout Control Specifications for the Front-End and Back-End of the LHCb Upgrade

    CERN Document Server

    Alessio, F

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run at between five and ten times the initial design luminosity. The various sub-systems in the readout architecture will need to be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. The development of a new readout control system for the upgraded LHCb readout system was investigated already in 2008. This work has evolved into a detailed system-level specification of the entire timing and readout control system . In this paper, we specify in detail the functionalities that must be supported by the Front-End and the Back-End electronics to comply with the timing requirements and the readout scheme, and the necessary control and monitoring capabilities in order to validate, commission and operate the upgraded experiment efficiently and with sufficient flexibility. The document focuses entirely on the readout control aspects of the FE and BE, and the ECS interface to t...

  3. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through a...... literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...

  4. A new approach to front-­‐end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Borga, Andrea; The ATLAS collaboration; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Ryu, Soo; Zhang, Jinlong; Anderson, John Thomas; Boterenbrood, Hendrik; Chen, Kai; Chen, Hucheng; Drake, Gary; Donszelmann, Mark; Francis, David

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

  5. Design, development, installation and commissioning of water-cooled pre-masks for undulator front-ends of Indus-2

    International Nuclear Information System (INIS)

    Recently two undulators U1 and U2 are installed in Indus-2 storage ring at RRCAT, Indore. When U1 and U2 are put in operation, a bright synchrotron radiation (SR) is produced which is transmitted through the zero degree port of the dipole vacuum chamber. In addition, a part of SR beam from the bending magnets, at the upstream and downstream of the undulator, is also overlapped with the undulator SR beam and transmitted in to the front-end through the same port. The front-end is a long ultra high vacuum (UHV) assembly consisting of water-cooled pre-mask, water-cooled shutters, UHV valves, diagnostic devices, safety shutter, vacuum pumps etc which acts as an interface between Indus-2 ring and beamline. Water-cooled pre- masks have been designed to cut a part of unwanted SR beam from the bending magnets. The pre-mask is a first active component in the undulator front-end which is also capable of absorbing high thermal load due to mis-steering of the SR beam from the undulator in the worst case scenario. The watercooled pre-mask consists of a copper block which has fixed aperture with slant faces to distribute the heat flux over a large surface area. The cooling channels are made on outer periphery of the block. The copper block is vacuum brazed with two conflat flanges of stainless steel at the two ends. The pre-mask is designed to absorb thermal load of 3 kW of synchrotron beam from undulator U1 and 2 kW of synchrotron beam from undulator U2. The thermal analysis of the pre-masks was carried out with the help of ANSYS® and the design was optimized with different cooling configurations. The main design criteria was to limit the maximum temperature of the mask less than 60 °C. This is to avoid substantial thermal outgassing from the heated portion which may deteriorate the ultra high vacuum. Pre-masks have been successfully tested, installed and commissioned with synchrotron beam in the undulator front-ends and are operating under vacuum of 5x10-10 mbar. (author)

  6. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  7. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  8. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  9. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  10. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  11. Installation and testing of the 112 boards for the front-end electronics.

    CERN Multimedia

    2006-01-01

    Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

  12. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken into...... account. The accuracy of the expressions has been verified by using Touchstone simulator. The agreement between the calculated and simulated front end performances is very good....

  13. A NEW MODIFIED TOTAL FRONT END FRAMEWORK FOR INNOVATION: NEW INSIGHTS FROM HEALTH RELATED INDUSTRIES

    OpenAIRE

    PATRICK J. TROTTER

    2011-01-01

    This paper explores the front end innovation activities in a multinational Global Healthcare Company (GHC). A questionnaire was designed and distributed to front end innovators from 20 operating companies to understand team composition, essential skill sets, and the methodology used to assess customer needs, generate ideas, and define the selection criteria used during the go/no go decision. For each category the current state and best practice (based on the views of the individual respondent...

  14. Front-end electronics of fast luminosity monitor system for BEPCII

    International Nuclear Information System (INIS)

    The front-end electronics of fast luminosity monitor system for BEPCII (Beijing Electron-Positron Collider, Phase II) was designed, constructed and tested. It mainly includes a large dynamic range high speed pre-amplifier, programmable high speed discriminators, anti-coincidence circuit, signal shaping and transferring. The test results show that the front-end electronics satisfies the requirements of 4 ns bunch-by-bunch fast luminosity monitor system for BEPCII. (authors)

  15. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  16. Ember.js front-end framework – SEO challenges and frameworks comparison

    OpenAIRE

    Shrestha, Sunil

    2015-01-01

    IWA Labs Oy, a Finnish company with extensive experience in modern information technology provides professional service in Search Engine Optimization (SEO), online marketing as well as develop mobile and web applications for its clients. In order to provide smooth and better user experience with web applications, the company has adapted front-end dedicated frameworks such as AngularJS, Backbone.js, etc. Therefore, the company is interested in Ember.js– another emerging front-end framework th...

  17. Front-End Electronics Test System Status Information (After ASDQ++ boards TEST at CERN)

    CERN Document Server

    Nobrega, R; Cernicchiaro, G

    2003-01-01

    A Front-End Electronics Test System (FEET) is being implemented in order to test the Front-end electronics (FEE), in the production line, for the LHCb Muon System. This document discusses some aspects related to the test of ASDQ++ boards. FEET presently enables 5 different tests: Connectivity, Crosstalk, Noise, Sensitivity and Rate-Method tests. The system has detected 25 channels with problems out of 640 tested channels.

  18. A low-noise CMOS front-end for TOF-PET

    OpenAIRE

    Rolo, M. D.; Alves, L. N.; Martins, E. V.; Rivetti, A.; Santos, M. B.; Varela, J

    2011-01-01

    An analogue CMOS front-end for triggering and amplification of signals produced by a silicon photomultiplier (SiPM) coupled to a LYSO scintillator is proposed. The solution is intended for time-of-flight measurement in compact Positron Emission Tomography (TOF-PET) medical imaging equipments where excellent timing resolution is required (approximate to 100 ps). A CMOS 0.13 mu m technology was used to implement such front end, and the design includes preamplification, shaping, baseline holder ...

  19. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  20. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    International Nuclear Information System (INIS)

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

  1. Design, development, and verification of the Planck Low Frequency Instrument 70 GHz Front-End and Back-End Modules

    International Nuclear Information System (INIS)

    70 GHz radiometer front-end and back-end modules for the Low Frequency Instrument of the European Space Agency's Planck Mission were built and tested. The operating principles and the design details of the mechanical structures are described along with the key InP MMIC low noise amplifiers and phase switches of the units. The units were tested in specially designed cryogenic vacuum chambers capable of producing the operating conditions required for Planck radiometers, specifically, a physical temperature of 20 K for the front-end modules, 300 K for the back-end modules and 4 K for the reference signal sources. Test results of the low noise amplifiers and phase switches, the front and back-end modules, and the combined results of both modules are discussed. At 70 GHz frequency, the system noise temperature of the front and back end is 28 K; the effective bandwidth 16 GHz, and the 1/f spectrum knee frequency is 38 mHz.The test results indicate state-of-the-art performance at 70 GHz frequency and fulfil the Planck performance requirements.

  2. Design, development, and verification of the Planck Low Frequency Instrument 70 GHz Front-End and Back-End Modules

    CERN Document Server

    Varis, J; Laaninen, M; Kilpia, V -H; Jukkala, P; Tuovinen, J; Ovaska, S; Sjoman, P; Kangaslahti, P; Gaier, T; Hoyland, R; Meinhold, P; Mennella, A; Bersanelli, M; Butler, R C; Cuttaia, F; Franceschi, E; Leonardi, R; Leutenegger, P; Malaspina, M; Mandolesi, N; Miccolis, M; Poutanen, T; Kurki-Suonio, H; Sandri, M; Stringhetti, L; Terenzi, L; Tomasi, M; Valenziano, L; 10.1088/1748-0221/4/12/T12001

    2010-01-01

    70 GHz radiometer front-end and back-end modules for the Low Frequency Instrument of the European Space Agencys Planck Mission were built and tested. The operating principles and the design details of the mechanical structures are described along with the key InP MMIC low noise amplifiers and phase switches of the units. The units were tested in specially designed cryogenic vacuum chambers capable of producing the operating conditions required for Planck radiometers, specifically, a physical temperature of 20 K for the front-end modules, 300 K for the back-end modules and 4 K for the reference signal sources. Test results of the low noise amplifiers and phase switches, the front and back-end modules, and the combined results of both modules are discussed. At 70 GHz frequency, the system noise temperature of the front and back end is 28 K; the effective bandwidth 16 GHz, and the 1/f spectrum knee frequency is 38 mHz. The test results indicate state-of-the-art performance at 70 GHz frequency and fulfil the Plan...

  3. Design of the NSLS-II Linac Front End Test Stand

    International Nuclear Information System (INIS)

    The NSLS-II operational parameters place very stringent requirements on the injection system. Among these are the charge per bunch train at low emittance that is required from the linac along with the uniformity of the charge per bunch along the train. The NSLS-II linac is a 200 MeV linac produced by Research Instruments Gmbh. Part of the strategy for understanding to operation of the injectors is to test the front end of the linac prior to its installation in the facility. The linac front end consists of a 100 kV electron gun, 500 MHz subharmonic prebuncher, focusing solenoids and a suite of diagnostics. The diagnostics in the front end need to be supplemented with an additional suite of diagnostics to fully characterize the beam. In this paper we discuss the design of a test stand to measure the various properties of the beam generated from this section. In particular, the test stand will measure the charge, transverse emittance, energy, energy spread, and bunching performance of the linac front end under all operating conditions of the front end.

  4. Attenuation of front-end reflections in an impulse radar using high-speed switching

    Science.gov (United States)

    Mazzaro, Gregory J.; Ressler, Marc A.; Smith, Gregory D.

    2011-06-01

    Pulse reflection between front-end components is a common problem for impulse radar systems. Such reflections arise because radio frequency components are rarely impedance-matched over an ultra-wide bandwidth. Any mismatch between components causes a portion of the impulse to reflect within the radar front-end. If the reflection couples into the transmit antenna, the radar emits an unintended, delayed and distorted replica of the intended radar transmission. These undesired transmissions reflect from the radar environment, produce echoes in the radar image, and generate false alarms in the vicinity of actual targets. The proposed solution for eliminating these echoes, without redesigning the transmit antenna, is to dissipate pulse reflections in a matched load before they are emitted. A high-speed switch directs the desired pulse to the antenna and redirects the undesired reflection from the antenna to a matched load. The Synchronous Impulse Reconstruction (SIRE) radar developed by the Army Research Laboratory (ARL) is the case-study. This paper reviews the current front-end design, provides a recent radar image which displays the aforementioned echoes, and describes the switch-cable-load circuit solution for eliminating the echoes. The consequences of inserting each portion of the new hardware into the radar front-end are explained. Measurements on the front-end with the high-speed switch show an attenuation of the undesired pulse transmissions of more than 18 dB and an attenuation in the desired pulse transmission of less than 3 dB.

  5. Front-End Electronics in calorimetry: from LHC to ILC

    International Nuclear Information System (INIS)

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

  6. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi;

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible for...... the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector...... gives it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors...

  7. A tunable RF Front-End with Narrowband Antennas for Mobile Devices

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Olesen, Poul; Madsen, Peter;

    2015-01-01

    In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex...... filters are replaced by tunable filters and antennas, providing a duplexer function over the air between the Tx and the Rx. A hardware system has been designed and fabricated to demonstrate the performance of this front-end architecture. Measurements demonstrate how the architecture addresses inter...

  8. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    International Nuclear Information System (INIS)

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  9. Upgrade to the front-end electronics of the BESIII muon identification system

    International Nuclear Information System (INIS)

    Resistive Plate Chambers (RPCs) built from a new type of Bakelite developed at Institute of High Energy Physics (IHEP), Chinese Academy of Sciences have been used in the BESIII Muon identification system for several years without linseed oil coating, but characteristic aging performances were observed. To adapt to the RPCs in the aging state, the front-end electronics have been upgraded by enhancing the front-end protection, improving the threshold setting circuit, and separating power supplies of the comparator and the field programmable gate array (FPGA). Improvements in system stability, front-end protection and threshold consistency have been achieved. In this paper, the system upgrade and the test results are described in detail. (authors)

  10. Front-end electronics for Micro Pattern Gas Detectors with integrated input protection against discharges

    International Nuclear Information System (INIS)

    One of the major problems that have to be addressed in the design of the front-end electronics for readout of MPGDs, is its resistance to possible random discharges inside active detector volume. This issue becomes particularly critical for the electronics built as ASICs implemented in a modern CMOS technology, for which the breakdown voltages are in the range of a few Volts, while the discharges may result in voltage spikes of even thousands Volts. The paper presents test results of input protection structures integrated with a specific design of the front-end electronics manufactured in the 350 nm CMOS process. The structures were tested using an electrical circuit to mimic discharges in the detectors for different voltage and current parameters of the sparks. Accomplished measurements showed no degradation in the front-end electronics performance even after very excessive discharge tests

  11. A front-end for silicon pixel detectors in ALICE and LHCb

    International Nuclear Information System (INIS)

    A new front-end for a pixel detector readout chip was designed. A non-standard topology was used to achieve low noise and fast return to zero of the preamplifier to be immune to pile-up of subsequent input signals. This front-end has been implemented on a pixel detector readout chip developed in a commercial 0.25 μm CMOS technology for the ALICE and LHCb experiments. This technology proved to be radiation tolerant when special layout techniques are used, and provides sufficient density for these applications. The chip is a matrix of 32 columns each containing 256 readout cells. Each readout cell comprises this front-end and digital readout circuitry, and has a static power consumption of about 60 μW

  12. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  13. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    International Nuclear Information System (INIS)

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  14. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  15. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  16. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Science.gov (United States)

    Feng, Zhou; Ting, Gao; Fei, Lan; Wei, Li; Ning, Li; Junyan, Ren

    2010-11-01

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  17. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... tendencies in formal R&D partnering relations. This paper, however, focuses on collaboration between independent companies prior to such formal agreements as joint ventures or other contractual agreements. This first phase of the innovation process is often referred to as the Fuzzy Front-End (FFE) and is...... traditionally seen as an intra-organizational process (Jongbae & David 2002;Kim & Wilemon 2002e;Qingyu & William 2001;Reid & de Brentani 2004a). As the innovation process becomes an interfirm-collaboration the management of the Fuzzy Front-End also changes and calls for new ways of collaboration. In this...

  18. Trends in the design of front-end systems for room temperature solid state detectors

    International Nuclear Information System (INIS)

    The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors

  19. Moderní Java frameworky pro front-end webových aplikací

    OpenAIRE

    Jahoda, Lukáš

    2013-01-01

    The aim of this thesis is the analysis of selected frameworks for the development of modern web applications on the Java platform focusing on the front-end. The work is complemented by well-chosen source code examples that help the reader to create one's own view of the frameworks and it can also server as a tutorial. Introductory section focuses on the trends of modern web applications, especially on the front-end. It affects themes such as support for mobile devices, AJAX or responsive desi...

  20. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  1. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    International Nuclear Information System (INIS)

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

  2. Design of a Direct-conversion Radio Receiver Front-end in CMOS Technology

    OpenAIRE

    Erixon, Mats

    2002-01-01

    In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from severa...

  3. A new approach to front-end electronics interfacing in the ATLAS experiment

    International Nuclear Information System (INIS)

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented

  4. Design and Optimization of an Analog Front-End for Biomedical Applications

    OpenAIRE

    Razzaghpour, Milad

    2011-01-01

    The state-of-the-art analog front-end of implantable biosensors is the class of current-mirror-based circuits. Despite their superior noise performance, power consumption and area, they suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In the first part of this thesis, a new analog front-end is proposed to eliminate the systematic error. The proposed topology is able to accurately copy the sensor current which will be converted i...

  5. A new approach to front-end electronics interfacing in the ATLAS experiment

    Science.gov (United States)

    Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Wu, W.; Zhang, J.

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  6. Flexible Analog Front Ends of Reconfigurable Radios Based on Sampling and Reconstruction with Internal Filtering

    Directory of Open Access Journals (Sweden)

    Poberezhskiy Gennady Y

    2005-01-01

    Full Text Available Bandpass sampling, reconstruction, and antialiasing filtering in analog front ends potentially provide the best performance of software defined radios. However, conventional techniques used for these procedures limit reconfigurability and adaptivity of the radios, complicate integrated circuit implementation, and preclude achieving potential performance. Novel sampling and reconstruction techniques with internal filtering eliminate these drawbacks and provide many additional advantages. Several ways to overcome the challenges of practical realization and implementation of these techniques are proposed and analyzed. The impact of sampling and reconstruction with internal filtering on the analog front end architectures and capabilities of software defined radios is discussed.

  7. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    CERN Document Server

    Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

    2015-01-01

    front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

  8. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    Energy Technology Data Exchange (ETDEWEB)

    Carlson, R.B.

    1992-01-01

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software.

  9. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    Energy Technology Data Exchange (ETDEWEB)

    Carlson, R.B.

    1992-05-01

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software.

  10. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    International Nuclear Information System (INIS)

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities

  11. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  12. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  13. Test stands for the Central Drift Chamber front end hybrid in the Stanford Linear Collider Detector

    Energy Technology Data Exchange (ETDEWEB)

    Lo, C.C.; Yim, A.K.

    1987-10-01

    The Central Drift Chamber (CDC) of the SLAC Linear Collider Detector (SLD) uses 1280 front end electronic hybrid modules. Each of these modules contains over 450 components and performs numerous functions. This paper describes the four test stands for production and detailed circuit characterizations of these hybrids. Descriptions and performance of some of the important functions of the test systems will be presented here.

  14. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels;

    2009-01-01

    subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AFE will enable various desired features, as for example the ability to use the front-end with antenna...

  15. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  16. Low power analog readout front-end electronics for time and energy measurements

    International Nuclear Information System (INIS)

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time tp=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC)2 shaper with the peaking time tp=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation Pdiss=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results

  17. The 025 mum front-end for the CMS pixel detector

    CERN Document Server

    Erdmann, W

    2005-01-01

    The front-end for the CMS pixel detector has been translated from the radiation hard DMILL process to a commercial 0.25 mum technology. The smaller feature size of this technology permitted a reduction of the pixel size and other improvements. First results obtained with the translated chip are discussed.

  18. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh;

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not...

  19. Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

    CERN Document Server

    Lo Presti, D; Caponetto, L

    2007-01-01

    A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  20. Low-power front-end for the optical module of a neutrino underwater telescope

    International Nuclear Information System (INIS)

    A proposal for a new system to capture signals in the Optical Module (OM) of an underwater neutrino telescope is described. It concentrates on the problem of power consumption and time precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  1. Low Power Front End for the Optical Module of a Neutrino Underwater Telescope

    CERN Document Server

    Lo Presti, D; Caponetto, L; Giorgi, F; Gabrielli, A

    2007-01-01

    A proposal for a new system to capture signals in the Optical Module (OM) of an underwater neutrino telescope is described. It concentrates on the problem of power consumption and time precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  2. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    B noise figure, 160 ns receiver recovery time and -46 dBc 3rd order IMD products. The system comprises also, a digital front-end, a digital signal generator, a microstrip antenna array and a control unit. All the subsystems were integrated, certified and functionally tested, and in May 2008 a successful...

  3. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  4. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  5. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    International Nuclear Information System (INIS)

    As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

  6. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, A.D.

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition o

  7. A differential low-voltage high gain current-mode integrated RF receiver front-end

    International Nuclear Information System (INIS)

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  8. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  9. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  10. Parameters-adjustable front-end controller in digital nuclear measurement system

    International Nuclear Information System (INIS)

    Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (Vin), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

  11. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  12. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2015-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  13. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2013-01-01

    After two years of operation of the LHC, the ATLAS Tile Calorimeter is undergoing the consolidation process of its front-end electronics. The first layer of certification of the repairs is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I. It is now possible to identify low occurrence errors due to its increased read-out bandwidth and perform more sophisticated quality checks due to its enhanced computing power. Improved results provide fast and reliable feedback to the user.

  14. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  15. Design of a hard X-ray beamline and end-station for pump and probe experiments at Pohang Accelerator Laboratory X-ray Free Electron Laser facility

    Science.gov (United States)

    Park, Jaeku; Eom, Intae; Kang, Tai-Hee; Rah, Seungyu; Nam, Ki Hyun; Park, Jaehyun; Kim, Sangsoo; Kwon, Soonam; Park, Sang Han; Kim, Kyung Sook; Hyun, Hyojung; Kim, Seung Nam; Lee, Eun Hee; Shin, Hocheol; Kim, Seonghan; Kim, Myong-jin; Shin, Hyun-Joon; Ahn, Docheon; Lim, Jun; Yu, Chung-Jong; Song, Changyong; Kim, Hyunjung; Noh, Do Young; Kang, Heung Sik; Kim, Bongsoo; Kim, Kwang-Woo; Ko, In Soo; Cho, Moo-Hyun; Kim, Sunam

    2016-02-01

    The Pohang Accelerator Laboratory X-ray Free Electron Laser project, a new worldwide-user facility to deliver ultrashort, laser-like x-ray photon pulses, will begin user operation in 2017 after one year of commissioning. Initially, it will provide two beamlines for hard and soft x-rays, respectively, and two experimental end-stations for the hard x-ray beamline will be constructed by the end of 2015. This article introduces one of the two hard x-ray end-stations, which is for hard x-ray pump-probe experiments, and primarily outlines the overall design of this end-station and its critical components. The content of this article will provide useful guidelines for the planning of experiments conducted at the new facility.

  16. Basic design of beamline and polarization control

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The basic concept of synchrotron radiation beamlines for vacuum ultraviolet and X-ray experiments has been introduced to beginning users and designers of beamlines. The beamline defined here is composed of a front end,pre-mirrors, and a monochromator with refocusing mirrors, which are connected by beam pipes, providing monochromatic light for the experiments. Firstly, time characteristics of the synchrotron radiation are briefly reviewed.Secondly, the basic technology is introduced as the fundamental knowledge required to both users and designers. The topics are photoabsorption by air and solids, front ends and beam pipes, mirrors, monochromators, and filters. Thirdly,the design consideration is described mainly for the designers. The topics are design principle, principle of ray tracing,optical machinery and control, and vacuum. Fourthly, polarization control is considered. The topics are polarizers,polarization diagnosis of beamline, and circularly-polarized light generation. Finally, a brief summary is given introducing some references for further knowledge of the users and the designers.

  17. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  18. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  19. A front-end electronics module for the PHENIX pad chamber

    International Nuclear Information System (INIS)

    The Pad Chamber (PC) is part of the Tracking System of the PHENIX detector at the RHIC accelerator of Brookhaven National Laboratory. A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The module's control functions are performed by the heap manager unit, an FPGE-based circuit on the FEM. Each FEM processes signals from 2,160 channels of front-end electronics (FEE). Data readout and formatting are performed by an additional FPGA-based circuit of the FEM. Three external systems provide initialization, timing, and data information via serial interfaces. This paper discusses the application of the heap manager, data formatter, and serial interfaces to meet the specific control and data readout needs of the Pad Chamber subsystem. Unit functions, interfaces, timing, data format, and communication rates will be discussed. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling and FPGA/Implementation and programming will be presented

  20. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  1. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  2. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    International Nuclear Information System (INIS)

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

  3. Development of an SOI analog front-end ASIC for X-ray charge coupled devices

    International Nuclear Information System (INIS)

    The FD-SOI technology is a fascinating LSI fabrication process as a possible radiation-tolerant device. In order to confirm benefits of the FD-SOI and expand application ranges in front-end electronics, we experimentally designed an analog front-end ASIC for X-ray CCD readout with the FD-SOI process. The circuit design was submitted to OKI Semiconductor Co., Ltd. via the multi-chip project as a part of the SOI pixel-detector R and D program in KEK. The ASIC contains seven readout channels using the correlated double sampling technique, and includes key circuit elements for a low-noise LSI. This paper describes the circuit design and the performance of the ASIC together with the radiation tolerance.

  4. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  5. Measurement of single event upsets in the ALICE-TPC front-end electronics

    CERN Document Server

    Mager, M; Rehman, A; Szczepankiewicz, A

    2011-01-01

    The Time Projection Chamber of the ALICE experiment at the CERN Large Hadron Collider features highly integrated on-detector read-out electronics. It is following the general trend of high energy physics experiments by placing the front-end electronics as close to the detector as possible -- only some 10 cm away from its active volume. Being located close to the beams and the interaction region, the electronics is subject to a moderate radiation load, which allowed us to use commercial off-the-shelf components. However, they needed to be selected and qualified carefully for radiation hardness and means had to be taken to protect their functionality against soft errors, i.e. single event upsets. Here we report on the first measurements of LHC induced radiation effects on ALICE front-end electronics and on how they attest to expectations.

  6. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  7. General-Purpose Front End for Real-Time Data Processing

    Science.gov (United States)

    James, Mark

    2007-01-01

    FRONTIER is a computer program that functions as a front end for any of a variety of other software of both the artificial intelligence (AI) and conventional data-processing types. As used here, front end signifies interface software needed for acquiring and preprocessing data and making the data available for analysis by the other software. FRONTIER is reusable in that it can be rapidly tailored to any such other software with minimum effort. Each component of FRONTIER is programmable and is executed in an embedded virtual machine. Each component can be reconfigured during execution. The virtual-machine implementation making FRONTIER independent of the type of computing hardware on which it is executed.

  8. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    International Nuclear Information System (INIS)

    The design and the preliminary measurements results of a multichannel, variable gain front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e - at 10 pF input capacitance

  9. A cryogenic front end for CDMA and UMTS wireless base stations

    International Nuclear Information System (INIS)

    The design and the laboratory performance of a cryogenic front end for CDMA and UMTS wireless base stations is described together with the results of a first field test at a CDMA base station in the region of Tangshan in China. The central elements of the cryogenic front ends are the cryocooler, the cryostat and the cryogenic platform mounted with up to 6 HTS pre-selection filters of high selectivity combined with the corresponding cryogenic low noise amplifiers of high dynamic range as well as the associated control electronics. Design and performance of the UMTS and CDMA filters are described and the characteristic parameters of the cryogenic low noise preamplifier are given. An analysis of the results of the first field test is discussed

  10. DSP-based Mitigation of RF Front-end Non-linearity in Cognitive Wideband Receivers

    Science.gov (United States)

    Grimm, Michael; Sharma, Rajesh K.; Hein, Matthias A.; Thomä, Reiner S.

    2012-09-01

    Software defined radios are increasingly used in modern communication systems, especially in cognitive radio. Since this technology has been commercially available, more and more practical deployments are emerging and its challenges and realistic limitations are being revealed. One of the main problems is the RF performance of the front-end over a wide bandwidth. This paper presents an analysis and mitigation of RF impairments in wideband front-ends for software defined radios, focussing on non-linear distortions in the receiver. We discuss the effects of non-linear distortions upon spectrum sensing in cognitive radio and analyse the performance of a typical wideband software-defined receiver. Digital signal processing techniques are used to alleviate non-linear distortions in the baseband signal. A feed-forward mitigation algorithm with an adaptive filter is implemented and applied to real measurement data. The results obtained show that distortions can be suppressed significantly and thus increasing the reliability of spectrum sensing.

  11. A fully integrated low-power CMOS particle detector front-end for space applications

    International Nuclear Information System (INIS)

    A fully integrated low-power complementary metal-oxide-semiconductor (CMOS) particle detector front-end (PDFE), optimized for space applications, is presented. The front-end comprises a charge sensitive amplifier and a four-stage semi-Gaussian pulse-shaping amplifier. The chip was custom synthesized with an analog synthesis environment. With a power consumption of only 10 mW and a chip area less than 1 mm2, the chip is very well suited for the stringent demands in space applications. Measurements show a peaking time of 1.2 micros and a total equivalent noise charge of less than 1000 erms-. Although a standard 0.7-microm CMOS was used, little performance degradation was observed after exposure to a total dose irradiation of 50 kRad. All tested chips fully recovered within specifications, after 24 h of annealing at room temperature

  12. SiPM and front-end electronics development for Cherenkov light detection

    CERN Document Server

    Ambrosi, G; Bissaldi, E; Ferri, A; Giordano, F; Gola, A; Ionica, M; Paoletti, R; Piemonte, C; Paternoster, G; Simone, D; Vagelli, V; Zappala, G; Zorzi, N

    2015-01-01

    The Italian Institute of Nuclear Physics (INFN) is involved in the development of a demonstrator for a SiPM-based camera for the Cherenkov Telescope Array (CTA) experiment, with a pixel size of 6$\\times$6 mm$^2$. The camera houses about two thousands electronics channels and is both light and compact. In this framework, a R&D program for the development of SiPMs suitable for Cherenkov light detection (so called NUV SiPMs) is ongoing. Different photosensors have been produced at Fondazione Bruno Kessler (FBK), with different micro-cell dimensions and fill factors, in different geometrical arrangements. At the same time, INFN is developing front-end electronics based on the waveform sampling technique optimized for the new NUV SiPM. Measurements on 1$\\times$1 mm$^2$, 3$\\times$3 mm$^2$, and 6$\\times$6 mm$^2$ NUV SiPMs coupled to the front-end electronics are presented

  13. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  14. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    CERN Document Server

    Albrecht, H

    2005-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns within a total of 256 bins. The chip also comprises a pipeline to store data from 128 events which is required for a deadtime-free trigger and data acquisition system. We report on the development, installation, and commissioning of the front-end electronics, including the grounding and noise suppression schemes, and discuss its performance in the HERA-B experiment.

  15. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Antelmi Pigosso, Daniela Cristina; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should be......Product-service systems (PSS) adoption has increased over the last years due to its potential for innovative value creation. However, the identification of ideas and opportunities in the innovation planning and the structuring of PSS projects are still incipient in organizations, following the same...... considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  16. A multi-host front end concentrator system for asynchronous consoles

    CERN Document Server

    Palandri, E M

    1974-01-01

    Describes a front end concentrator system for asynchronous time sharing consoles which has recently been put into operation at CERN. The concentrator will control up to 36 consoles at speeds up to 9600 bits per second and has the capability of dynamically connecting these consoles to several large Host processors. Features of the system include specially designed hardware and software to connect a wide range of different types of consoles in a flexible and expandable way, and the use of special purpose microcode to optimise console handling and facilitate the implementation of the system. The system runs in an HP2100 computer initially front-ending CDC 6000 series computers using the INTERCOM time sharing system. (6 refs).

  17. AMIC: an expandable integrated analog front-end for light distribution moments analysis

    OpenAIRE

    SPAGGIARI, MICHELE; Herrero Bosch, Vicente; Lerche, Christoph Werner; Aliaga Varea, Ramón José; Monzó Ferrer, José María; Gadea Gironés, Rafael

    2011-01-01

    In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a cop...

  18. A CLIMATE OF PSYCHOLOGICAL SAFETY ENHANCES THE SUCCESS OF FRONT END TEAMS

    OpenAIRE

    ANN-MARIE I. NIENABER; VERENA HOLTORF; JENS LEKER; GERHARD SCHEWE

    2015-01-01

    This paper contributes to the discussion about initiative in teams at the front end of new product development processes (innovative teams). In contrast to the general opinion presented in the literature, this study points out that unstructured innovative teams are as much initiative in developing new ideas or in finding quick solutions when compared to structured innovative teams. Therefore we analyse the relationship between teamwork quality and team initiative in structured and unstructure...

  19. Front-End Project Governance : Choice of Project Concept and Decision-Making– An International Perspective

    OpenAIRE

    Shiferaw, Asmamaw Tadege

    2013-01-01

    The demand for new investment projects is increasing; however, the preparation of a large number of those projects has had practical problems and the relevant systems and processes have been criticized. According to recent publications, a lack of problem analysis, lack of alternatives, contested information/misinformation, and many pitfalls in the decisionmaking process are among the main causes for concern. Following on from this, improving the front-end project governance processes and syst...

  20. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

    2011-02-15

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  1. Extending the Interaction Flow Modeling Language (IFML) for Model Driven Development of Mobile Applications Front End

    OpenAIRE

    Brambilla, Marco; Mauri, Andrea; Umuhoza, Eric

    2014-01-01

    Front-end design of mobile applications is a complex and multidisciplinary task, where many perspectives intersect and the user experience must be perfectly tailored to the application objectives. However, development of mobile user interactions is still largely a manual task, which yields to high risks of errors, inconsistencies and ine ciencies. In this paper we propose a model-driven approach to mobile application development based on the IFML standard. We propose an extension of the Inter...

  2. A Low-noise front-end circuit for 2D cMUT arrays

    OpenAIRE

    Güler, Ülkühan; Guler, Ulkuhan; Bozkurt, Ayhan

    2006-01-01

    cMUT technology enables 2D array design with front-end electronic integration through flip-chip bonding or cMUT-on-CMOS process. The size of a 2D array element is constrained in both dimensions due to the aperture sampling criteria, and therefore should be less than or equal to the half of the wavelength in both dimensions. Considering large parasitic capacitances introduced by the interconnections, such small transducer elements necessitate integrated low noise frontends for achieving accept...

  3. Low-noise analog front-end signal processing channel integration for pixelated semiconductor radiation detector

    OpenAIRE

    Lin, Ming-Cheng

    2012-01-01

    In the research development of the medical nuclear imaging, the low noise performance has always been a mandatory requirement in the design of the semiconductor pixelated radiation detector system in order to achieve the high detectability of the charge signal. The noise-optimized analog front-end signal processing channel composed of the charge sensitive amplifier and the pulse shaper is used extensively in processing the radiation charge signals from the pixelated semiconductor detector. Th...

  4. Front-End Project Governance: Choice of Project Concept and Decision-Making– An International Perspective

    OpenAIRE

    Shiferaw, Asmamaw Tadege

    2013-01-01

    The demand for new investment projects is increasing; however, the preparation of a large number of those projects has had practical problems and the relevant systems and processes have been criticized. According to recent publications, a lack of problem analysis, lack of alternatives, contested information/misinformation, and many pitfalls in the decisionmaking process are among the main causes for concern. Following on from this, improving the front-end project governance processes and syst...

  5. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    OpenAIRE

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels; Krozer, Viktor

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AF...

  6. Development of front-end electronics for mini-strip RPC readout

    Energy Technology Data Exchange (ETDEWEB)

    Shinde, Y. [Dipartimento Interateneo di Fisica and Sezione INFN, Via G. Amendola 173, 70126 Bari (Italy)], E-mail: yogeshmeets@gmail.com; De Robertis, G. [INFN-Sezione Di Bari Via Orabona, 4, 70125 Bari (Italy); Iaselli, G. [Dipartimento Interateneo di Fisica and Sezione INFN, Via G. Amendola 173, 70126 Bari (Italy); Loddo, F.; Pugliese, G. [INFN-Sezione Di Bari Via Orabona, 4, 70125 Bari (Italy); Tupputi, S.; Roselli, G. [Dipartimento Interateneo di Fisica and Sezione INFN, Via G. Amendola 173, 70126 Bari (Italy)

    2009-05-01

    The design and test of a single-gap resistive plate chamber instrumented with mini-strip readout is discussed. Efficiency and charge distribution are studied by means of cosmic muons using a small vertical telescope. The feasibility of inferring the position of the impinging particle is studied from the peak charge strip position. On the basis of these results a dedicated front-end VLSI is designed and prototyped.

  7. Development of front-end electronics for mini-strip RPC readout

    International Nuclear Information System (INIS)

    The design and test of a single-gap resistive plate chamber instrumented with mini-strip readout is discussed. Efficiency and charge distribution are studied by means of cosmic muons using a small vertical telescope. The feasibility of inferring the position of the impinging particle is studied from the peak charge strip position. On the basis of these results a dedicated front-end VLSI is designed and prototyped.

  8. A Dual Slope Charge Sampling Analog Front-End for a Wireless Neural Recording System

    OpenAIRE

    Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

    2014-01-01

    This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the inpu...

  9. Topology investigation of front end DC/DC converter for distributed power system

    OpenAIRE

    Yang, Bo

    2003-01-01

    Topology Investigation of Front End DC/DC Power Conversion for Distributed Power System by Bo Yang Fred C. Lee, Chairman Electrical Engineering (Abstract) With the fast advance in VLSI technology, smaller, more powerful digital system is available. It requires power supply with higher power density, lower profile and higher efficiency. PWM topologies have been widely used for this application. Unfortunately, hold up time requirement put huge penalties on the performance o...

  10. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  11. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    International Nuclear Information System (INIS)

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented

  12. Front End Design of a Multi-GeV H-minus Linac

    CERN Document Server

    Ostroumov, Peter; Romanov, Gennady; Shepard, Kenneth; William Foster, G

    2005-01-01

    The proposed 8-GeV driver at FNAL is based on ~480 independently phased SC resonators. Significant cost saving is expected by using an rf power fan out from high-power klystrons to multiple cavities. Successful development of superconducting (SC) multi-spoke resonators operating at ~345-350 MHz provides a strong basis for their application in the front end of multi-GeV linear accelerators. Such a front-end operating at 325 MHz would enable direct transition to high-gradient 1300 MHz SC TESLA-style cavities at ~400 MeV. The proposed front end consists of 5 sections: a conventional RFQ, room-temperature (RT) cross-bar H-type (CH) cavities, single-, double- and triple-spoke superconducting resonators. For several reasons which are discussed in this paper there is a large advantage in using independently phased RT CH-cavities between the RFQ and SC sections in the energy range 3-15 MeV.

  13. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  14. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  15. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    Science.gov (United States)

    Gomes, A.

    2016-02-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented.

  16. Status of the Control Sytem for the Front-End of the Spallation Neutron Source

    CERN Document Server

    Lewis, S A; Cull, P T

    2001-01-01

    The Spallation Neutron Source (SNS) is a partnership between six laboratories. To ensure a truly integrated control system, many standards have been agreed upon, including the use of EPICS as the basic toolkit. However, unique within the partnership is the requirement for Lawrence Berkeley National Lab, responsible for constructing the Front End, to operate it locally before shipping it to the Oak Ridge National Lab (ORNL) site. Thus, its control system must be finished in 2001, well before the SNS completion date of 2006. Consequently many decisions regarding interface hardware, operator screen layout, equipment types, and so forth had to be made before the other five partners had completed their designs. In some cases the Front-End has defined a standard by default; in others an upgrade to a new standard is anticipated by ORNL later. Nearly all Front-End devices have been commissioned with the EPICS control system. Of the approximately 1500 signals required, about 60% are now under daily operational use. Th...

  17. System level radiation validation studies for the CMS HCAL front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    J. Whitmore et al.

    2003-10-20

    Over a 10 year operating period, the CMS Hadron Calorimeter (HCAL) detector will be exposed to radiation fields of approximately 1 kRad of total ionizing dose (TID) and a neutron fluence of 4E11 n/cm{sup 2}. All front-end electronics must be qualified to survive this radiation environment with no degradation in performance. In addition, digital components in this environment can experience single-event upset (SEU) and single-event latchup (SEL). A measurement of these single-event effects (SEE) for all components is necessary in order to understand the level that will be encountered. System level studies of the performance of the front-end boards in a 200 MeV proton beam are presented. Limits on the latch-up immunity along with the expected SEU rate for the full front-end system have been measured. The first results from studies of the performance of the two Fermilab custom-designed chips in a radiation environment also are shown.

  18. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  19. FBI Fingerprint Image Capture System High-Speed-Front-End throughput modeling

    Energy Technology Data Exchange (ETDEWEB)

    Rathke, P.M.

    1993-09-01

    The Federal Bureau of Investigation (FBI) has undertaken a major modernization effort called the Integrated Automated Fingerprint Identification System (IAFISS). This system will provide centralized identification services using automated fingerprint, subject descriptor, mugshot, and document processing. A high-speed Fingerprint Image Capture System (FICS) is under development as part of the IAFIS program. The FICS will capture digital and microfilm images of FBI fingerprint cards for input into a central database. One FICS design supports two front-end scanning subsystems, known as the High-Speed-Front-End (HSFE) and Low-Speed-Front-End, to supply image data to a common data processing subsystem. The production rate of the HSFE is critical to meeting the FBI`s fingerprint card processing schedule. A model of the HSFE has been developed to help identify the issues driving the production rate, assist in the development of component specifications, and guide the evolution of an operations plan. A description of the model development is given, the assumptions are presented, and some HSFE throughput analysis is performed.

  20. 45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

    Science.gov (United States)

    Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

    2012-07-30

    In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W. PMID:23038384

  1. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  2. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology. PMID:25330494

  3. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  4. The influence of vehicle front-end design on pedestrian ground impact.

    Science.gov (United States)

    Crocetta, Gianmarco; Piantini, Simone; Pierini, Marco; Simms, Ciaran

    2015-06-01

    Accident data have shown that in pedestrian accidents with high-fronted vehicles (SUVs and vans) the risk of pedestrian head injuries from the contact with the ground is higher than with low-fronted vehicles (passenger cars). However, the reasons for this remain poorly understood. This paper addresses this question using multibody modelling to investigate the influence of vehicle front height and shape in pedestrian accidents on the mechanism of impact with the ground and on head ground impact speed. To this end, a set of 648 pedestrian/vehicle crash simulations was carried out using the MADYMO multibody simulation software. Impacts were simulated with six vehicle types at three impact speeds (20, 30, 40km/h) and three pedestrian types (50th % male, 5th % female, and 6-year-old child) at six different initial stance configurations, stationary and walking at 1.4m/s. Six different ground impact mechanisms, distinguished from each other by the manner in which the pedestrian impacted the ground, were identified. These configurations have statistically distinct and considerably different distributions of head-ground impact speeds. Pedestrian initial stance configuration (gait and walking speed) introduced a high variability to the head-ground impact speed. Nonetheless, the head-ground impact speed varied significantly between the different ground impact mechanisms identified and the distribution of impact mechanisms was strongly associated with vehicle type. In general, impact mechanisms for adults resulting in a head-first contact with the ground were more severe with high fronted vehicles compared to low fronted vehicles, though there is a speed dependency to these findings. With high fronted vehicles (SUVs and vans) the pedestrian was mainly pushed forward and for children this resulted in high head ground contact speeds. PMID:25813760

  5. New Order, end of illusions and the activist matrix of the first National Front

    Directory of Open Access Journals (Sweden)

    Nicolas LEBOURG

    2013-05-01

    Full Text Available Ordre nouveau was the most important French neo-fascist movement after 1945. It lasted only for four years (1969-1973 but it induced seve-ral changes shaking the radical right wing. As it was defined as a revolutionary party, ordre nouveau spread its identity onto activists on the one hand, while it also collaborated with state authorities fighting against leftists on the other hand. Following the successful italian model of the MSI, the movement oscillated between media coverage — which gave it an identity but also led to its dissolution in 1973 — and acceptance of the electoral game for which Front national had been founded. The disappearance of ordre nouveau meant the end of dreams of revolutionary right sustained by some active minorities using political violence, as well as it stood for a transition to a post-industrial radical right symbolized by the rise of Front National.

  6. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  7. Insulating electrodes: a review on biopotential front ends for dielectric skin–electrode interfaces

    International Nuclear Information System (INIS)

    Insulating electrodes, also known as capacitive electrodes, allow acquiring biopotentials without galvanic contact with the body. They operate with displacement currents instead of real charge currents, and the electrolytic electrode–skin interface is replaced by a dielectric film. The use of insulating electrodes is not the end of electrode interface problems but the beginning of new ones: coupling capacitances are of the order of pF calling for ultra-high input impedance amplifiers and careful biasing, guarding and shielding techniques. In this work, the general requirements of front ends for capacitive electrodes are presented and the different contributions to the overall noise are discussed and estimated. This analysis yields that noise bounds depend on features of the available devices as current and voltage noise, but the final noise level also depends on parasitic capacitances, requiring a careful shield and printed circuit design. When the dielectric layer is placed on the skin, the present-day amplifiers allow achieving noise levels similar to those provided by wet electrodes. Furthermore, capacitive electrode technology allows acquiring high quality ECG signals through thin clothes. A prototype front end for capacitive electrodes was built and tested. ECG signals were acquired with these electrodes in direct contact with the skin and also through cotton clothes 350 µm thick. They were compared with simultaneously acquired signals by means of wet electrodes and no significant differences were observed between both output signals

  8. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  9. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    International Nuclear Information System (INIS)

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

  10. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    International Nuclear Information System (INIS)

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2. (paper)

  11. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  12. Front end of the nuclear fuel cycle: options to reduce the risks of terrorism and proliferation

    International Nuclear Information System (INIS)

    The authors' assessment of the prospects for advanced front end technologies and fuel assurances becoming effective mechanisms for achieving nonproliferation and antiterrorism objectives is relatively pessimistic unless they are integrated with back end accommodations such as the return of spent fuel. They recommend that further examination of front end assurances be linked to that accommodation. To be sure, certain real technological improvements may postpone the day when commercial use of nuclear explosive fuels, with all their attendant terrorism and proliferation risks, is justified. Indeed, improvements in LWRs, using well-understood technology combined with advanced enrichment techniques, could reduce uranium requirements up to 45% at the beginning of the next century and up to 30% a decade earlier, provided the economic and security incentives are present. On the institutional side, existing supply conditions put little pressure on importing countries to seek long-term supply assurances. Moreover, the political obstacles to creating new international institutions or arrangements are exceedingly difficult to overcome, especially without a heightened consciousness of the growing risks of civilian explosive nuclear materials and the political will to make these risks a high priority. 2 tables

  13. High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

    Science.gov (United States)

    Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

    2010-01-01

    In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

  14. SYSTEMATIC METHOD TO GENERATE NEW IDEAS IN FUZZY FRONT END USING TRIZ

    Institute of Scientific and Technical Information of China (English)

    TAN Runhua; MA Lihui; YANG Bojun; SUN Jianguang

    2008-01-01

    The obstacle for idea generation in fuzzy front end (FFE) is difficult to apply knowledge in different fields for designers. Theory of inventive problem solving TRIZ and computer-aided innovation systems (CAIs) which are TRIZ-base software systems with a knowledge base provide a framework for knowledge application in different fields. The major methods in TRIZ are selected, which have four types. The problems to be solved for each method are summarized and mapping from the problems to the methods is given. Systematic method with eight paths to integrate the methods and problems is formed. A case study shows the idea generation in FFE using the integrated method step by step.

  15. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  16. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the...

  17. Design of an Ultra-Low Noise Analogue Front-End for Fast Voltage Pulses Measurement

    CERN Document Server

    AUTHOR|(SzGeCERN)712364; Arpaia, Pasquale; Cerqueira Bastos, Miguel; Martino, Michele

    2015-01-01

    A 15MS/s, 10 ppm repeatable acquisition system to characterize 3 μs rise-time trapezoidal voltage pulses is proposed. The system is based mainly on a low-noise, 5MHz bandwidth analog front-end. In this paper, the requirements, the concept and physical design are illustrated. Simulation results aimed at assessing the circuit performance are presented. An experimental case study on the characterization of a pulsed power supply for the klystrons modulators of the Compact Linear Collider (CLIC) under study at CERN is reported. In particular, the experimental metrological characterization of the prototype in terms of bandwidth and noise is presented.

  18. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  19. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  20. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  1. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  2. Measures of the environmental footprint of the front end of the nuclear fuel cycle

    International Nuclear Information System (INIS)

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle (FEFC) have focused primarily on energy consumption and CO2 emissions. Results have varied widely. This work builds upon reports from operating facilities and other primary data sources to build a database of front end environmental impacts. This work also addresses land transformation and water withdrawals associated with the processes of the FEFC. These processes include uranium extraction, conversion, enrichment, fuel fabrication, depleted uranium disposition, and transportation. To allow summing the impacts across processes, all impacts were normalized per tonne of natural uranium mined as well as per MWh(e) of electricity produced, a more conventional unit for measuring environmental impacts that facilitates comparison with other studies. This conversion was based on mass balances and process efficiencies associated with the current once-through LWR fuel cycle. Total energy input is calculated at 8.7 × 10−3 GJ(e)/MWh(e) of electricity and 5.9 × 10−3 GJ(t)/MWh(e) of thermal energy. It is dominated by the energy required for uranium extraction, conversion to fluoride compound for subsequent enrichment, and enrichment. An estimate of the carbon footprint is made from the direct energy consumption at 1.7 kg CO2/MWh(e). Water use is likewise dominated by requirements of uranium extraction, totaling 154 L/MWh(e). Land use is calculated at 8 × 10−3 m2/MWh(e), over 90% of which is due to uranium extraction. Quantified impacts are limited to those resulting from activities performed within the FEFC process facilities (i.e. within the plant gates). Energy embodied in material inputs such as process chemicals and fuel cladding is identified but not explicitly quantified in this study. Inclusion of indirect energy associated with embodied energy as well as construction and decommissioning of facilities could increase the FEFC energy intensity estimate by a factor

  3. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  4. Computer Aided Design of Microwave Front-End Components and Antennas for Ultrawideband Systems

    Science.gov (United States)

    Almalkawi, Mohammad J.

    This dissertation contributes to the development of novel designs, and implementation techniques for microwave front-end components and packaging employing both transmission line theory and classical circuit theory. For compact realization, all the presented components have been implemented using planar microstrip technology. Recently, there has been an increase in the demand for compact microwave front-ends which exhibit advanced functions. Under this trend, the development of multiband front-end components such as antennas with multiple band-notches, dual-band microwave filters, and high-Q reconfigurable filters play a pivotal role for more convenient and compact products. Therefore, the content of this dissertation is composed of three parts. The first part focuses on packaging as an essential process in RF/microwave integration that is used to mitigate unwanted radiations or crosstalk due to the connection traces. In printed circuit board (PCB) interconnects, crosstalk reduction has been achieved by adding a guard trace with/without vias or stitching capacitors that control the coupling between the traces. In this research, a new signal trace configuration to reduce crosstalk without adding additional components or guard traces is introduced. The second part of this dissertation considers the inherent challenges in the design of multiple-band notched ultrawideband antennas that include the integration of multilayer antennas with RF front-ends and the realization of compact size antennas. In this work, a compact UWB antenna with quad band-notched frequency characteristics was designed, fabricated, and tested demonstrating the desired performance. The third part discusses the design of single- and dual-band dual-mode filters exhibiting both symmetric and asymmetric transfer characteristics. In dual-mode filters, the numbers of resonators that determine the order of a filter are reduced by half while maintaining the performance of the actual filter order. Here, in

  5. Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

    Science.gov (United States)

    Prokop, Norman; Krasowski, Michael

    2013-01-01

    This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

  6. Digital front-end electronics for COMPASS Muon-Wall 1 detector

    International Nuclear Information System (INIS)

    The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

  7. An analog bipolar-JFET master slice array for front-end electronics design

    International Nuclear Information System (INIS)

    An analog bipolar-JFET Master Slice Array (MSA) has been designed for implementation of ICs used in nuclear physics front-end electronics. The universal conception of MSAs active and passive elements provides great functional complexity to ICs in using them. The quality of active element parameters, number and values of available resistors and capacitors made it possible to integrate a four channel amplifier-shaper-discriminator with a base line restorer into the MSA die with dimensions 2.7 mmx3.6 mm. Eight-channel ICs can be made by connection of two chips by metal wiring on a wafer

  8. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  9. The ALICE HMPID on-detector front-end and readout electronics

    CERN Document Server

    Santiard, Jean-Claude

    2004-01-01

    In the ALICE HMPID detector, Cherenkov photons are localised by measuring the charge induction on a MWPC cathode segmented into pads. Two ASICs have been developed: the Gassiplex07-3, which is an analogue 16-channels multiplexed front-end circuit dedicated to the readout of gaseous detector and the Dilogic-3, a sparse data scan digital processor. The combination of multiplexed and parallel- pipelined architecture allows to store several events between two L2 trigger and to transfer the 32-bits data words at a rate of 80 Mbytes per second through an optical data link.

  10. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  11. Design and performance Assessment of an Airborne Ice Sounding Radar Front-End

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2008-01-01

    -phase and out-of-phase power dividers with a relative bandwidth of 20% and more than 75W CW power handling, high power SPDT PIN switch with 90W CW power handling and a 70W CW High efficiency LDMOS power amplifier with ≫60% power-added efficiency. The system comprises also a digital signal generator, a...... digital front-end and a control unit. The system was functionally tested in March 2008 and had a first successful proof-of-concept campaign in Greenland in May 2008....

  12. Operation of Active Front-End Rectifier in Electric Drive under Unbalanced Voltage Supply

    Czech Academy of Sciences Publication Activity Database

    Chomát, Miroslav

    Rijeka: INTECHWEB.ORG, 2011 - (Chomát, M.), s. 195-216 ISBN 978-953-307-548-8 R&D Projects: GA ČR GA102/09/1273 Institutional research plan: CEZ:AV0Z20570509 Keywords : unbalanced voltage supply * DC-link voltage pulsations * pulse-width modulation Subject RIV: JA - Electronic s ; Optoelectronics, Electrical Engineering http://www.intechopen.com/books/electric-machines- and -drives/operation-of-active-front-end-rectifier-in-electric-drive-under-unbalanced-voltage-supply

  13. Policy, price formation, and the front end. A market-clearing model

    International Nuclear Information System (INIS)

    Demand for low enriched uranium (LEU) is met by an evolving combination of primary and secondary uranium sources and enrichment services. A market-clearing model to depict the time evolution of trade-offs between these industries under various policy and LEU demand scenarios is presented. By fixing short-run LEU demand, the model solves for the consumption of primary and secondary uranium and separative work units (SWUs) that minimizes overall front-end costs. Assuming frictionless markets at equilibrium, it projects cost minimizing tails U-235 enrichment, SWU and primary uranium prices over the next two decades by identifying producing and price-setting mines and enrichment facilities. (author)

  14. Front end ASIC for AGIPD, a high dynamic range fast detector for the European XFEL

    International Nuclear Information System (INIS)

    The Adaptive Gain Integrating Pixel Detector (AGIPD) is a hybrid pixel X-ray detector for the European-XFEL. One of the detector's important parts is the radiation tolerant front end ASIC fulfilling the European-XFEL requirements: high dynamic range—from sensitivity to single 12.5keV-photons up to 104 photons. It is implemented using the dynamic gain switching technique with three possible gains of the charge sensitive preamplifier. Each pixel can store up to 352 images in memory operated in random-access mode at ≥4.5 MHz frame rate. An external vetoing may be applied to overwrite unwanted frames

  15. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    OpenAIRE

    Valente, V.; Demosthenous, A.

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) ...

  16. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    International Nuclear Information System (INIS)

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented

  17. A front-end readout Detector Board for the OpenPET electronics system

    OpenAIRE

    Choong, W. -S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C.Q.; Wu, J.-Y.

    2015-01-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, an...

  18. T and T: a new design for a front-end time digitizer electronics

    International Nuclear Information System (INIS)

    A front-end readout electronics of new design is described. This electronics can operate in cosmic ray and extended air showers (EAS) as well as in accelerator experiments. The T and T (tracking and timing) electronics has been planned to cover large area detectors avoiding the necessity of tedious and time consuming cable calibrations. It is characterized by a 2 ns time resolution, multihits recording capability, no ambiguity in event-pulse reconstruction, daisy-chain interconnection, low power consumption and low cost. (orig.)

  19. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions. PMID:20192390

  20. Low power multi-dynamics front-end architecture for the optical module of a neutrino underwater telescope

    International Nuclear Information System (INIS)

    A proposal for a new front-end architecture intended to capture signals in the optical module of an underwater neutrino telescope is described. It concentrates on the problem of power consumption, signal reconstruction, charge and time precision.

  1. Management control systems as a tool to rationalize the intelligence gathering in the front end of innovation

    OpenAIRE

    Toivakka, Satu

    2016-01-01

    The objective of this study is to investigate how management control systems (MCS) are applied in the front end of innovation. Firstly, the focus will be to understand what kind of management controls, if any, are used in the front-end phase of innovation. Secondly, this study will clarify how these controls facilitate the intelligence gathering and the mobilization of the tacit knowledge that then leads to ideas and further to incremental innovations. The literature review explores the ...

  2. The design, test, and application of the front end in 0.3THz wireless communication systems

    Science.gov (United States)

    Wang, Hanqing; Yuan, Weiwen; Zhang, Bo; Li, Huiyuan; Zhang, Zhuo; Yang, Xiaojie; Shi, Weixun

    2015-11-01

    Designed for space application, the paper presents the design, test and application of the front end in 0.3THz wireless communication. After test and fabrication, the terahertz wireless system is completed and indicates that HD video signals have been transmitted over a distance of 14m at the data rate of 1.5Gbps. The study shows the overall course of the test and application of the front end in wireless communication.

  3. Modeling, simulation, and optimization of a front-end system for acetylene hydrogenation reactors

    Directory of Open Access Journals (Sweden)

    Gobbo R.

    2004-01-01

    Full Text Available The modeling, simulation, and dynamic optimization of an industrial reaction system for acetylene hydrogenation are discussed in the present work. The process consists of three adiabatic fixed-bed reactors, in series, with interstage cooling. These reactors are located after the compression and the caustic scrubbing sections of an ethylene plant, characterizing a front-end system; in contrast to the tail-end system where the reactors are placed after the de-ethanizer unit. The acetylene conversion and selectivity profiles for the reactors are optimized, taking into account catalyst deactivation and process constraints. A dynamic optimal temperature profile that maximizes ethylene production and meets product specifications is obtained by controlling the feed and intercoolers temperatures. An industrial acetylene hydrogenation system is used to provide the necessary data to adjust kinetics and transport parameters and to validate the approach.

  4. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  5. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  6. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  7. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    International Nuclear Information System (INIS)

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

  8. Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

    Science.gov (United States)

    Shan-Shan, Gao; Di, Jiang; Chang-Qing, Feng; Kai, Xi; Shu-Bin, Liu; Qi, An

    2016-01-01

    The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

  9. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  10. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  11. CPRF/ZTH front-end torus design and fabrication status

    International Nuclear Information System (INIS)

    Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

  12. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    International Nuclear Information System (INIS)

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors

  13. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    International Nuclear Information System (INIS)

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

  14. BORA: A front end board, with local intelligence, for the rich detector of the compass collaboration

    International Nuclear Information System (INIS)

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analogue voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analogue channel. After the analog values are digitized they are written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analogue channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC. (author)

  15. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo

    2014-11-21

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  16. Digital pulse processing and optimization of the front-end electronics for nuclear instrumentation

    International Nuclear Information System (INIS)

    This article describes an algorithm developed for the digital processing of signals provided by a high-efficiency well-type NaI(Tl) detector used to apply the 4πγ technique. In order to achieve a low-energy threshold, a new front-end electronics has been specifically designed to optimize the coupling to an analog-to-digital converter (14 bit, 125 MHz) connected to a digital development kit produced by Altera®. The digital pulse processing is based on an IIR (Infinite Impulse Response) approximation of the Gaussian filter (and its derivatives) that can be applied to the real-time processing of digitized signals. Based on measurements obtained with the photon emissions generated by an 241Am source, the energy threshold is estimated to be equal to ∼2 keV corresponding to the physical threshold of the NaI(Tl) detector. An algorithm developed for a Silicon Drift Detector used for low-energy x-ray spectrometry is also described. In that case, the digital pulse processing is specifically designed for signals provided by a reset-type preamplifier (55Fe source). - Highlights: • Digital pulse processing based on a recursive implementation of a Gaussian filter. • Optimization of the front-end electronics for the coupling to the ADC. • Improvement of detection threshold of a high-efficiency well-type NaI(Tl) detector. • Digital processing applied to a Si drift detector with reset-type preamplifier

  17. BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

    International Nuclear Information System (INIS)

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

  18. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  19. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  20. The Materials Science beamline upgrade at the Swiss Light Source.

    Science.gov (United States)

    Willmott, P R; Meister, D; Leake, S J; Lange, M; Bergamaschi, A; Böge, M; Calvi, M; Cancellieri, C; Casati, N; Cervellino, A; Chen, Q; David, C; Flechsig, U; Gozzo, F; Henrich, B; Jäggi-Spielmann, S; Jakob, B; Kalichava, I; Karvinen, P; Krempasky, J; Lüdeke, A; Lüscher, R; Maag, S; Quitmann, C; Reinle-Schmitt, M L; Schmidt, T; Schmitt, B; Streun, A; Vartiainen, I; Vitins, M; Wang, X; Wullschleger, R

    2013-09-01

    The Materials Science beamline at the Swiss Light Source has been operational since 2001. In late 2010, the original wiggler source was replaced with a novel insertion device, which allows unprecedented access to high photon energies from an undulator installed in a medium-energy storage ring. In order to best exploit the increased brilliance of this new source, the entire front-end and optics had to be redesigned. In this work, the upgrade of the beamline is described in detail. The tone is didactic, from which it is hoped the reader can adapt the concepts and ideas to his or her needs. PMID:23955029

  1. Powerloads on the front end components and the duct of the heating and diagnostic neutral beam lines at ITER

    Energy Technology Data Exchange (ETDEWEB)

    Singh, M. J.; Boilson, D.; Hemsworth, R. S.; Geli, F.; Graceffa, J.; Urbani, M.; Schunke, B.; Chareyre, J. [ITER Organisation, 13607 St. Paul-Lez-Durance Cedex (France); Dlougach, E.; Krylov, A. [RRC Kurchatov institute, 1, Kurchatov Sq, Moscow, 123182 (Russian Federation)

    2015-04-08

    The heating and current drive beam lines (HNB) at ITER are expected to deliver ∼16.7 MW power per beam line for H beams at 870 keV and D beams at 1 MeV during the H-He and the DD/DT phases of ITER operation respectively. On the other hand the diagnostic neutral beam (DNB) line shall deliver ∼2 MW power for H beams at 100 keV during both the phases. The path lengths over which the beams from the HNB and DNB beam lines need to be transported are 25.6 m and 20.7 m respectively. The transport of the beams over these path lengths results in beam losses, mainly by the direct interception of the beam with the beam line components and reionisation. The lost power is deposited on the surfaces of the various components of the beam line. In order to ensure the survival of these components over the operational life time of ITER, it is important to determine to the best possible extent the operational power loads and power densities on the various surfaces which are impacted by the beam in one way or the other during its transport. The main factors contributing to these are the divergence of the beamlets and the halo fraction in the beam, the beam aiming, the horizontal and vertical misalignment of the beam, and the gas profile along the beam path, which determines the re-ionisation loss, and the re-ionisation cross sections. The estimations have been made using a combination of the modified version of the Monte Carlo Gas Flow code (MCGF) and the BTR code. The MCGF is used to determine the gas profile in the beam line and takes into account the active gas feed into the ion source and neutraliser, the HNB-DNB cross over, the gas entering the beamline from the ITER machine, the additional gas atoms generated in the beam line due to impacting ions and the pumping speed of the cryopumps. The BTR code has been used to obtain the power loads and the power densities on the various surfaces of the front end components and the duct modules for different scenarios of ITER

  2. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0–30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  3. Wave front and phase correction for double-ended gauge block interferometry

    Science.gov (United States)

    Lassila, A.; Byman, V.

    2015-10-01

    Double-ended interferometry has several benefits over single-ended gauge block interferometry: there is no need for wringing, which wears surfaces and requires expertise, and there is improved repeatability, since there is no variation due to inconsistent wringing conditions or form errors of the gauge block surfaces. Some disadvantages of double-ended interferometry are that absolute phase change correction is needed for the gauge block and its uncertainty has a double effect on total uncertainty. In addition, elimination of the wavefront error is more complicated than with single-ended interferometry. A simple optical modification that enables double-ended interferometer (DEI) measurements with the MIKES interferometer for long gauge blocks is presented. This modification is applicable to almost any single-ended interferometer (SEI). A procedure for evaluating the wave front correction for different parts of the interferogram of DEI is explained, and a modification and software with capability for nine-point phase stepping is presented. Three independent methods for evaluation of the phase correction were studied. One of them uses integrating sphere for the surface roughness correction and literature values for the phase change due to complex refractive index of material correction. The second evaluates the phase correction from the difference between DEI and SEI results obtained with a quartz platen. The third uses differences—from separate measurements—between the results obtained with quartz or steel auxiliary platens. Only a few gauge blocks per set need testing to obtain phase correction. SEI and DEI results with different phase correction determination methods are presented and evaluated. The uncertainty estimate for gauge block calibration with DEI gives a similar standard uncertainty to that with the best SEIs, u=\\sqrt{{{≤ft(10.0~ \\text{nm}\\right)}2}+{{≤ft(118× {{10}-9}L\\right)}2}} .

  4. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  5. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  6. Testing and development of the CMS silicon tracker front-end readout electronics

    CERN Document Server

    Leaver, James D G

    2006-01-01

    The Compact Muon Solenoid (CMS) is a general purpose detector that will operate at the CERN Large Hadron Collider (LHC), a particle accelerator designed for the study of new physics at the TeV energy scale. A key component of CMS is the Silicon Tracker, which has ~9.3 million detector channels and is expected to generate over 70% of the total CMS data volume. The Tracker readout system must process data at a rate that is orders of magnitude higher than in any previous particle physics experiment. On-detector readout is performed by the APV25 front end chip. To ensure a Tracker of the highest quality and efficiency, each APV25 must be rigorously verified; a wafer probing test station has been developed for post production quality assurance. The APV25 contains internal pipelines which buffer event data pending readout. An APV Emulator has been designed to prevent APV25 buffer overflow due to random fluctuations in the Level 1 trigger rate. The first stage of the off-detector readout is performed by the Front En...

  7. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  8. Harmonic Mitigated Front End Three Level Diode Clamped High Frequency Link Inverter by Using MCI Technique

    Directory of Open Access Journals (Sweden)

    Sreedhar Madichetty

    2014-02-01

    Full Text Available In this paper it proposes a high efficient soft-switching scheme based on zero-voltage-switching (ZVS and zero-current-switching(ZCS principle operated with a simple auxiliary circuit extended range for the front-end isolated DC-AC-DC-AC high power converter with an three phase three level diode clamped multi level inverter by using Minority Charge Carrier inspired optimization technique (MCI with Total Harmonic Distortion(THD,Switching losses, Selective harmonic elimination maintaining with its fundamental as an objective function. Input to the inverter is obtained by the photo voltaic cells and with battery bank. The switching scheme is optimized by MCI technique, analyzed and executed in Matlab and implemented with a digital signal processor (DSP .Experimental results with different loads have observed and shows its effectives, robustness of the applied technique.

  9. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter; Harris, Fred

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N......-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A...... non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for...

  10. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo; Vandi, Luca; Andreani, Pietro; Castello, Rinaldo

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing a...... compact and low-power solution compatible with low-voltage technologies. A 0.13um CMOS prototype tailored to the GPS application is presented. The experimental results exhibit a noise figure of 4.8 dB, a gain of 36 dB, an IIP3 of -19 dBm with a total power consumption of only 5.4 mW from a voltage supply...

  11. Control of Beam Losses in the Front End for the Neutrino Factory

    International Nuclear Information System (INIS)

    In the Neutrino Factory and Muon Collider, muons are produced by firing high energy protons onto a target to produce pions. The pions decay to muons which are then accelerated. This method of pion production results in significant background from protons and electrons, which may result in heat deposition on superconducting materials and activation of the machine preventing manual handling. In this paper we discuss the design of a secondary particle handling system. The system comprises a solenoidal chicane that filters high momentum particles, followed by a proton absorber that reduces the energy of all particles, resulting in the rejection of low energy protons that pass through the solenoid chicane. We detail the design and optimization of the system and its integration with the rest of the muon front end.

  12. A front-end electronics module for multi-gap resistive plate chambers

    International Nuclear Information System (INIS)

    Background: The output current signal of Multi-gap Resistive Plate Chambers (MRPCs) has low amplitude and fast speed. Purpose: Its amplitude and time information should be obtained in particle Time-of-Flight (TOF) detection. Methods: A simple electronics module for the presentation of the signals from MRPCs to standard existing digitization electronics is described. The circuit is based on 'off-the-shelf' discrete components. An optimization of the values of specific components is required to match the aspects of the MRPCs for the given application. The key electronic noise control plan is also discussed. Results: This electronics module has the excellent features including low prices, convenient making, easy assembling for testing system, etc. Conclusions: This electronics module is an attractive option for the front-end signal processing in MRPCs prototype and bench or beam-testing efforts, as well as in final implementations of small-area particle TOF system with existing data acquisition systems. (authors)

  13. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  14. The NA62 LAV front-end electronics and the L0 trigger generating firmware

    CERN Document Server

    Gonnella, Francesco; Corradi, Giovanni; Kozhuharov , Venelin ; Martellotti, Silvia; Moulson, Matthew; Raggi, Mauro; Spadaro, Tommaso

    2014-01-01

    The aim of the NA62 experiment is to measure the branching ratio of the decay K + ! p + n ̄ n to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from p + p 0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is 100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed.

  15. Front-End-Electronics Communication software for multiple detectors in the ALICE experiment

    CERN Document Server

    Bablok, Sebastian; Hartung, G; Keidel, R; Kofler, C; Krawutschke, T; Lindenstruth, V; Röhrich, D

    2006-01-01

    In the ALICE experiment at CERN, the Detector Control System (DCS) employs several interacting software components to accomplish its task of ensuring the correct operation and monitoring of the experiment. This paper describes the Front-End-Electronics Communication (FeeCommunication) software and its role within the DCS. The FeeCommunication software's central task is passing configuration and monitoring data between the top level DCS process control and the field devices of several detectors within ALICE. The lowest level of the FeeCommunication software runs on the DCS boards, specialized embedded systems which are in direct contact with the field devices and are physically located within the detector. The middle and upper layers run on standard PC hardware located in the counting room or other external locations. This paper focuses on the design and implementation of the FeeCommunication software and the steps that were taken to fulfill the imposed reliability and performance requirements, specifically th...

  16. Conductive Cooling of SDD and SSD Front-End Chips for ALICE

    CERN Document Server

    Van den Brink, A; Daudo, F; Feofilov, G A; Godisov, O N; Giraudo, G; Igolkin, S N; Kuijer, P; Nooren, G J L; Swichev, A; Tosello, F

    2001-01-01

    We present analysis, technology developments and test results of the heat drain system of the SDD and SSD front-end electronics for the ALICE Inner Tracker System (ITS). Application of super thermoconductive carbon fibre thin plates provides a practical solution for the development of miniature motherboards for the FEE chips situated inside the sensitive ITS volume. Unidirectional carbon fibre motherboards of 160 -300 micron thickness ensure the mounting of the FEE chips and an efficient heat sink to the cooling arteries. Thermal conductivity up to 1.3 times better than copper is achieved while preserving a negligible multiple scattering contribution by the material (less than 0.15 percent of X/Xo).

  17. Fuzzy Decision Support for Tools Selection in the Core Front End Activities of New Product Development

    DEFF Research Database (Denmark)

    Achiche, S.; Appio, F.P.; McAloone, Tim C.;

    2013-01-01

    or analysis of the process to go from Opportunity Identification to Concept Generation; as a result, the FE process is often aborted or forced to be restarted. Koen’s Model for the FE is composed of five phases. In each of the phases, several tools can be used by designers/managers in order to......, etc. Hence, an economic evaluation of the cost of tool usage is critical, and there is furthermore a need to characterize them in terms of their influence on the FE. This paper focuses on decision support for managers/ designers in their process of assessing the cost of choosing/using tools in the...... core front end (CFE) activities identified by Koen, namely Opportunity Identification and Opportunity Analysis. This is achieved by first analyzing the influencing factors (firm context, industry context, macroenvironment) along with data collection from managers followed by the automatic construction...

  18. Performance of the front-end electronics of the ANTARES neutrino telescope

    International Nuclear Information System (INIS)

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  19. Performance of the front-end electronics of the ANTARES neutrino telescope

    Energy Technology Data Exchange (ETDEWEB)

    Aguilar, J.A. [IFIC - Instituto de Fisica Corpuscular, Edificios Investigacion de Paterna, CSIC - Universitat de Valencia, Apdo. de Correos 22085, 46071 Valencia (Spain); Al Samarai, I. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Albert, A. [GRPHE - Institut universitaire de technologie de Colmar, 34 rue du Grillenbreit BP 50568 - 68008 Colmar (France); Anghinolfi, M. [INFN - Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); Anton, G. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Anvar, S. [Direction des Sciences de la Matiere - Institut de recherche sur les lois fondamentales de l' Univers - Service d' Electronique des Detecteurs et d' Informatique, CEA Saclay, 91191 Gif-sur-Yvette Cedex (France); Ardid, M. [Institut d' Investigacio per a la Gestio Integrada de Zones Costaneres (IGIC) - Universitat Politecnica de Valencia. C/ Paranimf, 1. E-46730 Gandia (Spain); Assis Jesus, A.C.; Astraatmadja, T. [FOM Instituut voor Subatomaire Fysica Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Aubert, J.-J. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Auer, R. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Baret, B. [APC - Laboratoire AstroParticule et Cosmologie, UMR 7164 (CNRS, Universite Paris 7 Diderot, CEA, Observatoire de Paris) 10, rue Alice Domon et Leonie Duquet 75205 Paris Cedex 13 (France); Basa, S. [LAM - Laboratoire d' Astrophysique de Marseille, Pole de l' Etoile Site de Ch-Gombert, rue Frederic Joliot-Curie 38, 13388 Marseille cedex 13 (France)

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  20. Cognitive radio receiver front-ends RF/analog circuit techniques

    CERN Document Server

    Sadhu, Bodhisatwa

    2014-01-01

    This book focuses on the architecture and circuit design for cognitive radio receiver front-ends.  The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.   • Discusses in detail the circuit-level challenges that exist for cognitive radio systems; • Provides readers with a holistic understanding of RF circuits for cognitive radio systems; • Enables communications engineers and systems designers to design better cognitive radio architectures and communication protocols.

  1. A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

    Directory of Open Access Journals (Sweden)

    Eric Bharucha

    2014-11-01

    Full Text Available When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

  2. Front end electronics and first results of the ALICE V0 detector

    International Nuclear Information System (INIS)

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  3. Analog front-end measuring biopotential signal with effective offset rejection loop.

    Science.gov (United States)

    Lim, Seunghyun; Kim, Hyunho; Song, Haryong; Cho, Dong-il Dan; Ko, Hyoungho

    2015-01-01

    This paper presents an analog front-end (AFE) IC design for recording biopotential signals. The AFE employs a capacitively coupled instrumentation amplifier to achieve a low-noise and high-common mode rejection ratio (CMRR) system. A ripple reduction loop is proposed to reduce the ripple generated by the up-modulating chopper. The low frequency noise is attenuated by an input AC coupling capacitor, and is attenuated again by a DC servo loop. The proposed AFE features a differential gain of 71 dB, and a CMRR of 89 dB, at 50 Hz. Furthermore, the proposed AFE can robustly acquire biopotential signals even in the presence of an input offset and ripples. PMID:26406095

  4. Radiation Protection Aspects of the Linac Coherent Light Source Front End Enclosure

    Energy Technology Data Exchange (ETDEWEB)

    Vollaire, J.; Fasso, A.; Liu, J.C.; Mao, X.S.; Prinz, A.; Rokni, S.H.; Leitner, M.Santana; /SLAC

    2010-08-26

    The Front End Enclosure (FEE) of the Linac Coherent Light Source (LCLS) is a shielding housing located between the electron dump area and the first experimental hutch. The upstream part of the FEE hosts the commissioning diagnostics for the FEL beam. In the downstream part of the FEE, two sets of grazing incidence mirror and several collimators are used to direct the beam to one of the experimental stations and reduce the bremsstrahlung background and the hard component of the spontaneous radiation spectrum. This paper addresses the beam loss assumptions and radiation sources entering the FEE used for the design of the FEE shielding using the Monte-Carlo code FLUKA. The beam containment system prevents abnormal levels of radiations inside the FEE and ensures that the beam remains in its intended path is also described.

  5. Test bench for front end electronic of the GCT camera for the Cherenkov Telescope Array

    International Nuclear Information System (INIS)

    The Gamma Cherenkov Telescope (GCT) is a design proposed to be part of the Small Sized Telescope (SST) array of the Cherenkov Telescope Array (CTA). The GCT camera is designed to record the flashes of atmospheric Cherenkov light from gamma and cosmic ray initiated cascades, which last only a few tens of nanoseconds. The camera thus needs very fast and compact electronics, addressed by the TARGET modules, based on homonymous ASICs which provide digitation at 1 GSample/s and the first level of trigger on the analog output of the photosensors. In this paper we describe a test bench lab set up to evaluate the performance and functionality of the camera' s front end electronics with an added educational value

  6. Low noise front end ICECAL ASIC for the upgrade of the LHCb calorimeter

    International Nuclear Information System (INIS)

    A fully differential ASIC with cooled input termination is presented as a solution for the Upgrade of the Calorimeter front end electronics. The LHCb experiment needs to increase about ten times the integrated luminosity in order to study new physics. The increase in signal has to be compensated reducing the gain of the photomultipliers which implies stringent noise requirements. The proposed solution offers an active termination at the input and avoids the noise originated by the use of a resistor. The circuit is based on a two interleaved channel with a first amplifier stage, a switched integrator, and a Track-and-Hold. Two prototypes have been implemented and tested in SiGe BiCMOS 0.35um technology.

  7. Balancing research and organizational capacity building in front-end project design

    DEFF Research Database (Denmark)

    Hjortsø, Carsten Nico Portefée; Meilby, Henrik

    2013-01-01

    phase of RCB partnerships and examine how they influence the balance between performing collaborative research and developing general organizational capacity. Data collection was based on a survey (n = 25), and individual interviews and focus group discussions with 17 Danish project managers from the...... order for partnerships to comply with general governance-level recommendations, a better understanding is needed of how specific context-dependent factors influence the development and execution of projects. In this article, we aim to contribute to the understanding of factors influencing the design...... is more complex. We identify 11 specific factors influencing front-end project management related to structure, process and relationship, and we theorize about how these factors influence the choice between research and more general capacity development activities. Copyright © 2013 John Wiley & Sons...

  8. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    research and FEI to produce more valid candidates and faster for drug development. This paper explores how pharmaceutical front end innovation can be actively supported through the development and implementation of an innovation strategy. The empirical field and applied methodology is an action......, Steven & Burly, 2003, and Vernorn et al., 2008) and that innovation strategies play a central role in optimization of innovation (Clark & Wheelwright, 1995; Cottam et al., 2001; Morgan & Berthon, 2008). Innovation strategies are suggested in literature (e.g. Page, 1993; Oke, 2002; Adams et al., 2006......; Igartua, 2010) as a facilitator of innovation and may therefore also be targeted at FEI support. The pharmaceutical industry has experienced a worldwide decline in the number of applications for new molecular entities to regulatory agencies since 1997. Therefore high pressures are put on pharmaceutical...

  9. Development of a low-noise analog front-end ASIC for APD-PET detectors

    International Nuclear Information System (INIS)

    We report on the development of a front-end ASIC for high spatial resolution PET detectors with time-of-flight capability based on LYSO scintillator arrays coupled with position-sensitive avalanche photodiode (APD) arrays. The ASIC is designed based on the open-IP LSI project led by JAXA and realized in TSMC 0.35-μm CMOS technology. It consists of an 8-channel charge-sensitive amplifier, band-pass filters, differentiators, pulse-height and timing discriminators, and two-channel time-to-amplitude converters. As a result, energy resolution of 9.7% (FWHM) is obtained at 511 keV, with a time resolution below 970 ps (σ). We will also report on the current status of developing a second-version ASIC designed to have 32-channel analog circuits with improved time resolution.

  10. A digital Front-End and Readout MIcrosystem for Calorimetry at LHC, pt.1, 1990

    CERN Document Server

    Löfstedt, B; Svensson, C; Yuan, J; Hentzell, H; Sami, M; Stefanelli, F; Cattaneo, Paolo Walter; Dell'Acqua, A; Fumagalli, G; Goggi, Giorgio V; Maloberti, F; Torelli, G; Carlson, P J; Fuglesang, C; Kérek, A; Appelquist, G; Berglund, S R; Bohm, C; Yamdagni, N; CERN. Geneva. Detector Research and Development Committee

    1990-01-01

    We propose a digital approach to the front-end electronic chain for calorimetric detectors based on high speed A to D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and redundancy are also to be considered. The solutions proposed are designed to match the whole range of calorimeter performances in terms of resolution and signal speed. A system integration of a multichannel device in a multi-chip, Silicon- on-Silicon Microsystem hybrid is proposed. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of large scale integration also offers the possibility to implement detector-specific functions, as well as a high degree of programmability at both the function and the system level.

  11. Considerations on the design of front-end electronics for silicon calorimetry for the SSC

    International Nuclear Information System (INIS)

    Some considerations are described for the design of a silicon-based sampling calorimetry detector for the Superconducting Super Collider (SSC). The use of silicon as the detection medium allows fast, accurate, and fine-grained energy measurements - but for optimal performance, the front-end electronics must be matched to the detector characteristics and have the speed required by the high SSC interaction rates. The relation between the signal-to-noise rtio of the calorimeter electronics and the charge collection time, the preamplifier power dissipation, detector capacitance and leakage, charge gain, and signal shaping and sampling was studied. The electrostatic transformer connection was analyzed and found to be unusable for a tightly arranged calorimeter because of stray capacitance effects. The method of deconvolutional sampling was developed as a means for pileup correction following synchronous sampling and analog storage

  12. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    CERN Document Server

    Impiombato, D; Mineo, T; Catalano, O; Gargano, C; La Rosa, G; Russo, F; Sottile, G; Billotta, S; Bonanno, G; Garozzo, S; Grillo, A; Marano, D; Romeo, G

    2015-01-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  13. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    Energy Technology Data Exchange (ETDEWEB)

    Impiombato, D., E-mail: Domenico.Impiombato@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Giarrusso, S., E-mail: Giarrusso@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Mineo, T., E-mail: Mineo@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Catalano, O., E-mail: Catalano@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy)

    2015-09-11

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  14. CMOS front end analog signal readout chip for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    The paper presents the design of an 8-channel front-end chip for Si-strip detectors, ranging in capacitance from 1 to 30 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC3) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 250ns-2us in four fixed steps by external control. There is provision for changing gain low/high. A derivative of the chip is also developed for dosimeter application that uses small area diodes as detectors. The circuit has a power dissipation of 6 MW per channel and is designed to fabricate in 1.2um CMOS technology. The Opf noise is ∼400e. The design approach is presented and the results of simulation are shown. (author)

  15. A digital front-end and readout microsystem for calorimetry at LHC

    International Nuclear Information System (INIS)

    A digital solution to the front-end electronics for calorimetric detectors at future supercolliders is presented. The solution is based on hig speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also being considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid, is used. This solution allows a new level of integration of complex analogue and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. It also allows a high degree of programmability at both the function and the system level, and offers the possibility of customising the microsystem with detector-specific functions. (orig.)

  16. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    International Nuclear Information System (INIS)

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions

  17. An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

    Institute of Scientific and Technical Information of China (English)

    WANG Min; ZHANG Xiao; ZHANG Chun-feng; CAO Mao-yong; LI Cai-fang; KONG Hui-min; QIN Feng-ju; YAN Yu-qin

    2007-01-01

    Abstract.Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here,a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end ( AFE), while a computer ( Pentium Ⅲ ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

  18. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  19. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  20. Single event effects on the APV25 front-end chip

    CERN Document Server

    Friedl, M; Pernicka, Manfred

    2003-01-01

    The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m**2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 mum deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

  1. Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

    DEFF Research Database (Denmark)

    Song, Zhanfeng; Tian, Yanjun; Chen, Wei;

    2016-01-01

    This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...... constructed based on the desired control performance is adopted here, which is essential for the solving process of the optimizing problem. On the other hand, differently, with respect to the proposed strategy, duty cycle signals are optimized, instead of possible switching states. The determination...... of optimal duty cycles is made by predicting the effect of duty cycles on instantaneous current variations and minimizing the cost function. Due to the adoption of behavior prediction, the proposed controller inherits the excellent dynamic characteristics of predictive controllers. Moreover, the application...

  2. Understanding Managers Decision Making Process for Tools Selection in the Core Front End of Innovation

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.;

    2011-01-01

    New product development (NPD) describes the process of bringing a new product or service to the market. The Fuzzy Front End (FFE) of Innovation is the term describing the activities happening before the product development phase of NPD. In the FFE of innovation, several tools are used to facilitate...... and optimise the activities. To select these tools, managers of the product development team have to use several premises to decide upon which tool is more appropriate to which activity. This paper proposes an approach to model the decision making process of the managers. The results underline the......, and several hypotheses are tested. A preliminary version of a theoretical model depicting the decision process of managers during tools selection in the FFE is proposed. The theoretical model is built from the constructed hypotheses....

  3. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  4. Understanding Managers Decision Making Process for Tools Selection in the Core Front End of Innovation

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.; Di Minin, Alberto

    and optimise the activities. To select these tools, managers of the product development team have to use several premises to decide upon which tool is more appropriate to which activity. This paper proposes an approach to model the decision making process of the managers. The results underline the......, and several hypotheses are tested. A preliminary version of a theoretical model depicting the decision process of managers during tools selection in the FFE is proposed. The theoretical model is built from the constructed hypotheses.......New product development (NPD) describes the process of bringing a new product or service to the market. The Fuzzy Front End (FFE) of Innovation is the term describing the activities happening before the product development phase of NPD. In the FFE of innovation, several tools are used to facilitate...

  5. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  6. A VLSI ASIC front end for the optical module of the NEMO underwater neutrino detector

    International Nuclear Information System (INIS)

    The work described here has been developed in the context of the NEMO Collaboration with the aim of studying and designing a front-end electronics for the Optical Modules, which contains the telescope optical sensors, as a full-custom Very Large Scale Integration (VLSI) Application Specific Integrated Circuit (ASIC). The solution has a multitude of advantages. The most important are low power consumption and the pre-analysis and suitable reduction of data to be transferred to the shore station for acquisition. A detailed description of the chosen architecture and the design principles of the blocks, that carry out the specialized function required by this architecture, will be given. The chips produced will be described and the test measurements performed will be shown

  7. Validation of the Simulation for the CMS Endcap Muon Cathode Strip Chamber Front-end Electronics

    CERN Document Server

    Durkin, S; Terentyev, Nikolay

    2005-01-01

    The results of a validation of the ORCA simulation for the CMS Endcap Muon cathode strip chamber front-end electronics are presented. A comparison of the simulation results with test-beam and pulser calibration data is done for the cathode strip pulse shape and the cross-talk. The three types of data are compared using two methods ? fitting the pulse shapes to find the shaping times and cross-talk coefficients, and directly comparing the pulse shapes and cross-talk time dependence. The ORCA description of the pulse shape is found to be adequate, though the cross-talk modeling could be updated using recent pulser calibration data as a basis.

  8. A front-end read out chip for the OPERA scintillator tracker

    International Nuclear Information System (INIS)

    Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32-channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto-trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range [0-100] photo-electrons. In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance

  9. A low power low noise analog front end for portable healthcare system

    International Nuclear Information System (INIS)

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

  10. Indus-2 beam line front end controls using real time operating system

    International Nuclear Information System (INIS)

    Beam Line Front Ends (BLFE) are crucial interfaces between machine user beam lines and INDUS-2 synchrotron radiation source. Twenty-seven beam lines are proposed in INDUS-2 synchrotron facility out of which some are operational by now and many more are about to come. The purpose of these BLFE's is essentially to protect the machine vacuum from beam line failures and vice versa and allow a well co-ordinated and safe usage of machine by its users. For controlling these beam lines, BLFE control system is implemented. The BLFE control system is based on three-layer architecture with equipments connected ate the layer three, Layer two serves the purpose of metadata storage, layer one serves as operator console (GUI). This paper discusses the scheme and architecture of layer two and layer three implementation using RTOS OS-9. The diagnostic features incorporated in the architecture increases the system uptime by quick diagnosis of system faults. (author)

  11. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  12. An optimized analog to digital converter for WLAN analog front end

    International Nuclear Information System (INIS)

    A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multi-bit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 μm 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz. (semiconductor integrated circuits)

  13. Key differences and similarities in ways of managing and supporting radical pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2015-01-01

    facilitation of innovation management and FEI in theory and in practice across international borders. I aim to show how different aspects of Pharma and nationality affect the way innovation management and radical FEI are supported within organisations. This is examined through an in-depth case study of the......The purpose of this paper is to explore how Front End Innovation (FEI) is supported and managed among companies of different nationality within the context of pharmaceutical R&D. The present study is carried out in order to contribute to the development of a clearer understanding of active...... Danish and US based pharmaceutical company, H. Lundbeck A/S, and a comparative study including five European and American pharmaceutical companies. The findings from the study reveal a number of similarities and differences in innovation management and FEI support of radical projects and among the...

  14. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  15. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz. PMID:26736404

  16. Optimizing read-out of the NECTAr front-end electronics

    International Nuclear Information System (INIS)

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  17. Measures of the environmental footprint of the front end of the nuclear fuel cycle

    Energy Technology Data Exchange (ETDEWEB)

    E. Schneider; B. Carlsen; E. Tavrides; C. van der Hoeven; U. Phathanapirom

    2013-11-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle (FEFC) have focused primarily on energy consumption and CO2 emissions. Results have varied widely. This work builds upon reports from operating facilities and other primary data sources to build a database of front end environmental impacts. This work also addresses land transformation and water withdrawals associated with the processes of the FEFC. These processes include uranium extraction, conversion, enrichment, fuel fabrication, depleted uranium disposition, and transportation. To allow summing the impacts across processes, all impacts were normalized per tonne of natural uranium mined as well as per MWh(e) of electricity produced, a more conventional unit for measuring environmental impacts that facilitates comparison with other studies. This conversion was based on mass balances and process efficiencies associated with the current once-through LWR fuel cycle. Total energy input is calculated at 8.7 x 10- 3 GJ(e)/MWh(e) of electricity and 5.9 x 10- 3 GJ(t)/MWh(e) of thermal energy. It is dominated by the energy required for uranium extraction, conversion to fluoride compound for subsequent enrichment, and enrichment. An estimate of the carbon footprint is made from the direct energy consumption at 1.7 kg CO2/MWh(e). Water use is likewise dominated by requirements of uranium extraction, totaling 154 L/MWh(e). Land use is calculated at 8 x 10- 3 m2/MWh(e), over 90% of which is due to uranium extraction. Quantified impacts are limited to those resulting from activities performed within the FEFC process facilities (i.e. within the plant gates). Energy embodied in material inputs such as process chemicals and fuel cladding is identified but not explicitly quantified in this study. Inclusion of indirect energy associated with embodied energy as well as construction and decommissioning of facilities could increase the FEFC energy intensity estimate by a factor of up

  18. Front-End Electronics for Verification Measurements: Performance Evaluation and Viability of Advanced Tamper Indicating Measures

    International Nuclear Information System (INIS)

    The International Atomic Energy Agency (IAEA) continues to expand its use of unattended, remotely monitored measurement systems. An increasing number of systems and an expanding family of instruments create challenges in terms of deployment efficiency and the implementation of data authentication measures. A collaboration between Pacific Northwest National Laboratory (PNNL), Idaho National Laboratory (INL), and Los Alamos National Laboratory (LANL) is working to advance the IAEA's capabilities in these areas. The first objective of the project is to perform a comprehensive evaluation of a prototype front-end electronics package, as specified by the IAEA and procured from a commercial vendor. This evaluation begins with an assessment against the IAEA's original technical specifications and expands to consider the strengths and limitations over a broad range of important parameters that include: sensor types, cable types, and the spectrum of industrial electromagnetic noise that can degrade signals from remotely located detectors. A second objective of the collaboration is to explore advanced tamper-indicating (TI) measures that could help to address some of the long-standing data authentication challenges with IAEA's unattended systems. The collaboration has defined high-priority tampering scenarios to consider (e.g., replacement of sensor, intrusion into cable), and drafted preliminary requirements for advanced TI measures. The collaborators are performing independent TI investigations of different candidate approaches: active time-domain reflectometry (PNNL), passive noise analysis (INL), and pulse-by-pulse analysis and correction (LANL). The initial investigations focus on scenarios where new TI measures are retrofitted into existing IAEA UMS deployments; subsequent work will consider the integration of advanced TI methods into new IAEA UMS deployments where the detector is separated from the front-end electronics. In this paper, project progress

  19. Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

    International Nuclear Information System (INIS)

    A 2.4 GHz low-power, low-noise and highly linear receiver front-end with a low noise amplifier (LNA) and balun optimization is presented. Direct conversion architecture is employed for this front-end. The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer, and is optimized for the best noise performance of the front-end. The circuit is implemented with 0.35 μm SiGe BiCMOS technology. The front-end has three gain steps for maximization of the input dynamic range. The overall maximum gain is about 36 dB. The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode. The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes. The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm2 die size. (semiconductor integrated circuits)

  20. Low noise, low power front end electronics for pixelized TFA sensors

    CERN Document Server

    Poltorak, K; Dabrowski, W; Despeisse, M; Jarron, P; Kaplon, J; Wyrschb, N

    2009-01-01

    Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on top of the readout ASIC, TFA shows the similarity to MAP imagers, allowing, however, more sophisticated front–end circuitry to extract the signals, like in case of Hybrid Pixel technology. In this paper we present preliminary experimental results of TFA structures, obtained with 10 μm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/μm for minimum ionizing particles, therefore a low noise, high gain and very low power of the front- end are of primary importance. The developed demonstrator chip, designed in 250 nm CMOS technology, comprises an array of 64 by 64 pi...

  1. Physiological motivated transmission-lines as front end for loudness models.

    Science.gov (United States)

    Pieper, Iko; Mauermann, Manfred; Kollmeier, Birger; Ewert, Stephan D

    2016-05-01

    The perception of loudness is strongly influenced by peripheral auditory processing, which calls for a physiologically correct peripheral auditory processing stage when constructing advanced loudness models. Most loudness models, however, rather follow a functional approach: a parallel auditory filter bank combined with a compression stage, followed by spectral and temporal integration. Such classical loudness models do not allow to directly link physiological measurements like otoacoustic emissions to properties of their auditory filterbank. However, this can be achieved with physiologically motivated transmission-line models (TLMs) of the cochlea. Here two active and nonlinear TLMs were tested as the peripheral front end of a loudness model. The TLMs are followed by a simple generic back end which performs integration of basilar-membrane "excitation" across place and time to yield a loudness estimate. The proposed model approach reaches similar performance as other state-of-the-art loudness models regarding the prediction of loudness in sones, equal-loudness contours (including spectral fine structure), and loudness as a function of bandwidth. The suggested model provides a powerful tool to directly connect objective measures of basilar membrane compression, such as distortion product otoacoustic emissions, and loudness in future studies. PMID:27250182

  2. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  3. Characteristics and Disposal Categorization of Solid Radioactive Waste from the Front End of the Uranium Fuel Cycle

    International Nuclear Information System (INIS)

    The proper categorization of radioactive waste forms the basis for defining its disposal method. In particular, it is the basis for defining the disposal policy for solid radioactive waste from the front end of the uranium fuel cycle to identify scientifically its characteristics, in view of the differences in regulatory approach between artificial radioactive waste and NORM waste. The paper examines the disposal policy and practice in China and other countries for solid radioactive waste from the front end of the uranium fuel cycle and discusses the confusion in disposal of the waste as artificial radioactive waste. The radionuclide composition and characteristics of the solid radioactive waste from the front end of the uranium fuel cycle are investigated in detail and a new idea that such waste needs to be disposed of and categorized as NORM waste is proposed. (author)

  4. Upgrade of the Photon Beamline Control System on the SRS

    CERN Document Server

    Martlew, B G; Cox, G; Heath, P W; Heron, M T; Oates, A; Rawlinson, W R; Sharp, C D

    2001-01-01

    The SRS is a 2GeV synchrotron light source with 14 beamlines serving approximately 34 experimental stations. Control of the major elements of the beamlines (vacuum pumps, gauges, valves and radiation stops) is the responsibility of the main SRS Control System. As part of the long-term upgrade plan for the SRS Control System a large programme of work has been undertaken to modernize beamline control. This work included: development of Linux based PC front end computers to interface to the existing CAMAC I/O system, replacement of the user interface by graphical synoptic diagrams running on Windows NT PCs, development of an ActiveX control for parameter display/control and a cache server to reduce loading on the rest of the control system. This paper describes the major components of the project; the techniques used to manage the new PCs and discusses some of the problems encountered during development.

  5. Unified analytical expressions for calculating resonant frequencies, transimpedances, and equivalent input noise current densities of tuned receiver front ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1992-01-01

    Unified analytical expressions have been derived for calculating the resonant frequencies, transimpedance and equivalent input noise current densities of the four most widely used tuned optical receiver front ends built with FETs and p-i-n diodes. A more accurate FET model has been used to improve...... the accuracy of the analysis. The Miller capacitance has been taken into account, and its impact on the performances of the tuned front ends has been demonstrated. The accuracy of the expressions has been verified by Touchstone simulations. The agreement between the calculated and simulated...

  6. Instrumentation Developments and Beam Studies for the Fermilab Proton Improvement Plan LINAC Upgrade and New RFQ Front-End

    CERN Document Server

    Scarpine, Victor E; Karns, Pat R; Bollinger, Daniel S; Duel, Kevin L; Eddy, Nathan; Lui, Ning; Semenov, Alexei; Tomlin, Raymond E; Pellico, William A

    2014-01-01

    Fermilab is developing a Proton Improvement Plan (PIP) to increase throughput of its proton source. The plan addresses hardware modifications to increase repetition rate and improve beam loss while ensuring viable operation of the proton source through 2025. The first phase of the PIP will enable the Fermilab proton source to deliver 1.8e17 protons per hour by mid-2013. As part of this initial upgrade, Fermilab plans to install a new front-end consisting of dual H- ion sources and a 201 MHz pulsed RFQ. This paper will present beam studies measurements of this new front-end and discuss new beam instrumentation upgrades for the Fermilab linac.

  7. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  8. The Virtual Learning Commons: Supporting the Fuzzy Front End of Scientific Research with Emerging Technologies

    Science.gov (United States)

    Pennington, D. D.; Gandara, A.; Gris, I.

    2012-12-01

    The Virtual Learning Commons (VLC), funded by the National Science Foundation Office of Cyberinfrastructure CI-Team Program, is a combination of Semantic Web, mash up, and social networking tools that supports knowledge sharing and innovation across scientific disciplines in research and education communities and networks. The explosion of scientific resources (data, models, algorithms, tools, and cyberinfrastructure) challenges the ability of researchers to be aware of resources that might benefit them. Even when aware, it can be difficult to understand enough about those resources to become potential adopters or re-users. Often scientific data and emerging technologies have little documentation, especially about the context of their use. The VLC tackles this challenge by providing mechanisms for individuals and groups of researchers to organize Web resources into virtual collections, and engage each other around those collections in order to a) learn about potentially relevant resources that are available; b) design research that leverages those resources; and c) develop initial work plans. The VLC aims to support the "fuzzy front end" of innovation, where novel ideas emerge and there is the greatest potential for impact on research design. It is during the fuzzy front end that conceptual collisions across disciplines and exposure to diverse perspectives provide opportunity for creative thinking that can lead to inventive outcomes. The VLC integrates Semantic Web functionality for structuring distributed information, mash up functionality for retrieving and displaying information, and social media for discussing/rating information. We are working to provide three views of information that support researchers in different ways: 1. Innovation Marketplace: supports users as they try to understand what research is being conducted, who is conducting it, where they are located, and who they collaborate with; 2. Conceptual Mapper: supports users as they organize their

  9. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    International Nuclear Information System (INIS)

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs

  10. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  11. Design of Radio Frequency Quadrupole (RFQ) - a front end injector for accelerators at IPR

    International Nuclear Information System (INIS)

    In recent times, the Radio Frequency Quadrupole (RFQ) linear accelerator is established as a popular choice for acceleration of a high intensity ion beam from an ion source to few MeVs, due to its attractive features such as its compact size and more importantly, the simultaneous realization of the focusing and acceleration of ions by electrode tip modulation. Due to these inherent properties RFQ linacs have almost replaced the large DC accelerators, such as Cockcroft Walton accelerator used earlier in the low energy regime and have become essential component as front end injectors for high current linacs worldwide. A project on 'Development of a RFQ for accelerators' has been initiated at IPR, Gandhinagar as a part of the Indian domestic fusion program for fusion reactor matrial qualification, where the high energy accelerated ion beams from the RFQ will be used to produce the required neutron flux to fulfil the above said purpose. Design of the RFQ accelerator along with mechanical and thermal aspects will be discussed in detail in this paper

  12. Laser based beam diagnostic for the RAL Front End Test Stand (FETS)

    International Nuclear Information System (INIS)

    For the diagnostic of high power particle beams, non-destructive measurement devices provide minimum influence on the beam and avoid various problems in connection with the high power density on surfaces. An H- ion beam offers the opportunity of non destructive beam diagnostics based on the effect of photo detachment. By the interaction of light with H- ions, the additional electron can be detached and a small number of neutrals will be produced. An additional magnetic dipole field can then be used to separate the detached electrons and neutrals from the ions. Using an integral detector the spatial distribution of the beam ion density can be derived, while the use of a spatial resolving detector enables to determine the phase space distribution. To investigate the measurement principle of the latter, a test stand was set up at the IAP in Frankfurt. This system will now be adopted to the requirements of the Front End Test Stand at CCLRC/ RAL. The aim of this FETS is to demonstrate a chopped H- beam of 60mA at 3MeV and 50pps with sufficiently high beam quality. The paper will present a detailed description of the proposed set up at RAL and discuss several results of simulations and experimental data gained in Frankfurt

  13. The MYRRHA ADS Project in Belgium Enters the Front End Engineering Phase

    Science.gov (United States)

    De Bruyn, Didier; Abderrahim, Hamid Aït; Baeten, Peter; Leysen, Paul

    The MYRRHA project started in 1998 by SCK•CEN. MYRRHA is a MTR, based on the ADS concept, for material and fuel research, for studying the feasibility of transmutation of Minor Actinides and Long-Lived Fission Products arising from radioactive waste reprocessing and finally for demonstrating at a reasonable power scale the principle of the ADS. The MYRRHA design has progressed through various framework programmes of the European Commission in the context of Partitioning and Transmutation. The design has now entered into the Front End Engineering Phase (FEED) covering the period 2012-2015. The engineering company, which will handle this phase, has been selected and the works have begun in the late 2013. In the mean time we have made some refinements in both primary systems and plant layout, including reactor building design. In this paper, we present the most recent developments of the MYRRHA design in terms of reactor building and plant layout as existing today as well as a preliminary study concerning the spent fuel building of the facility. During the oral presentation we add some preliminary results of the interaction with the FEED contractor and the most recent version of the primary systems.

  14. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

  15. Thermal influences of the front-end electronics on the ALICE TPC readout chamber

    CERN Document Server

    Popescu, Sorina; Schmidt, Hans Rudolf

    2004-01-01

    The ALICE TPC detector will be operated with a gas mixture of 90% Ne and 10% CO/sub 2/ at the electric field of 400 V/cm. Recent studies favor a three-component mixture by adding about 5% N/sub 2/, which will improve the stability of the gas against discharges. These operating parameters lead to a non-saturated drift velocity for electrons but also impose that all external influences on the drift gas must be reduced to minimum. The most problematic influence is temperature variation, which can lead to local fluctuation in the gas density and therefore directly affects the drift velocity. For the Alice TPC, the aim is to have a temperature stability of 0.1 degrees C over the full drift length (2.5 m). The main heat contribution comes from the readout chambers front-end electronics and one estimates that a total of 30.2 kW must be removed. The test results discussed here give qualitative and quantitative information about the thermal behavior of the chambers for validation of the TPC cooling strategy.

  16. A front-end readout Detector Board for the OpenPET electronics system

    International Nuclear Information System (INIS)

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ''time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc

  17. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  18. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Science.gov (United States)

    Chen, Y. T.; de La Taille, C.; Suomijärvi, T.; Cao, Z.; Deligny, O.; Dulucq, F.; Ge, M. M.; Lhenry-Yvon, I.; Martin-Chassard, G.; Nguyen Trung, T.; Wanlin, E.; Xiao, G.; Yin, L. Q.; Yun Ky, B.; Zhang, L.; Zhang, H. Y.; Zhang, S. S.; Zhu, Z.

    2015-09-01

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  19. A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

    International Nuclear Information System (INIS)

    Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption. (paper)

  20. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  1. The Front-End Electronics for the HADES RPC Wall (ESTRELA-FEE)

    Science.gov (United States)

    Belver, D.; Garzón, J. A.; Gil, A.; González-Díaz, D.; Koenig, W.; Lange, S.; Marín, J.; Montes, N.; Skott, P.; Traxler, M.; Zapata, M.

    2006-08-01

    A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m 2 with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most.

  2. Front-End electronics development for the new Resistive Plate Chamber detector of HADES

    Science.gov (United States)

    Gil, A.; Belver, D.; Cabanelas, P.; Díaz, J.; Garzón, J. A.; González-Díaz, D.; Koenig, W.; Lange, J. S.; Marín, J.; Montes, N.; Skott, P.; Traxler, M.

    2007-11-01

    In this paper we present the new RPC wall, which is being installed in the HADES detector at Darmstadt GSI. It consists of time-of-flight (TOF) detectors used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The wall will contain 1024 RPC modules, covering an active area of around 7 m2, replacing the old TOFino detector at the low polar angle region. The excellent TOF and good charge resolutions of the new detector will improve the time resolution to values better than 100 ps. The Front-End electronics for the readout of the RPC signals is implemented with two types of boards to satisfy the space constraints: the Daughterboards are small boards that amplify the low level signals from the detector and provide fast discriminators for time of flight measurements, as well as an integrator for charge measurements. The Motherboard provides stable DC voltages and a stable ground, threshold DACs for the discriminators, multiplicity trigger and impedance matched paths for transfer of time window signals that contain information about time and charge. These signals are sent to a custom TDC board that label each event and send data through Ethernet to be conveniently stored.

  3. Voltage and Reactive Power Control of Front-end Speed Controlled Wind Turbine via H∞ Strategy

    Directory of Open Access Journals (Sweden)

    Haiying Dong

    2013-08-01

    Full Text Available According to the characteristics like rapidity, time variability and the uncertainty of the input mechanical torque of the front-end speed control wind turbine (FSCWT with directly grid-connected electrically excited synchronous generator (EESG, a double-loop H∞ control approach was proposed. In which, a simpilified structure of brushless excitation system was used. For the inner loop, first H∞ excitation controller was designed for realizing a fast excitation control; the second H∞ power system stabilizer (PSS was designed by solving the Riccati equation for the purpose of eliminating the oscillation and desynchronization of generator may caused by fast excitation and improving the system transient stability, which ensured the generator with stable operation in grid-connecting and effectively solved the contradiction between fast excitation and transient stability. Then the designed H∞ controllers were applied to the voltage and reactive power control system (VRCS, which realized the output voltage and reactive power control requriements by tuning the weighting functions. Simulation results show that the double-loop H∞ control approach was more effective than the single H∞ excitation control in voltage and reactive power control of FSCWT.

  4. A non-dimensional approach in solving front end, underhood flow and heat transfer problems

    International Nuclear Information System (INIS)

    A non-dimensional approach is developed to solve the front end and underhood flow problems with a cooling fan as one of the momentum sources. Typically, the fan in the vehicle is in an environment, which has high temperatures. These high temperatures have the effect of changing the density. The density variation in these cases is assumed to be a function of temperature alone. It is well known that these changes in the density affect the flow rates through the heat exchangers. The changes in the density and its effect on the flow rates if a fan model is present cannot be addressed using commercial codes unless user defined functions are written. The present method addresses how these variations can be handled using a non-dimensional approach without having to write user routines. The governing equations of flow and heat transfer are non-dimensionalized and the corresponding inputs to commercial codes found so as to enable these codes to handle the non-dimensional equations. The following sections illustrate the procedure to be used to solve these problems. (author)

  5. A non-dimensional approach in solving front end, underhood flow and heat transfer problems

    Energy Technology Data Exchange (ETDEWEB)

    Damodaran, V. [General Motors, Detroit, Michigan (United States)]. E-mail: vijay.damodran@gm.com

    2003-07-01

    A non-dimensional approach is developed to solve the front end and underhood flow problems with a cooling fan as one of the momentum sources. Typically, the fan in the vehicle is in an environment, which has high temperatures. These high temperatures have the effect of changing the density. The density variation in these cases is assumed to be a function of temperature alone. It is well known that these changes in the density affect the flow rates through the heat exchangers. The changes in the density and its effect on the flow rates if a fan model is present cannot be addressed using commercial codes unless user defined functions are written. The present method addresses how these variations can be handled using a non-dimensional approach without having to write user routines. The governing equations of flow and heat transfer are non-dimensionalized and the corresponding inputs to commercial codes found so as to enable these codes to handle the non-dimensional equations. The following sections illustrate the procedure to be used to solve these problems. (author)

  6. Progress on the upgrade of the CMS Hadron Calorimeter Front-End electronics

    Energy Technology Data Exchange (ETDEWEB)

    Anderson, Jake; Whitmore, Juliana; /Fermilab

    2011-11-01

    We present a scheme to upgrade the CMS HCAL front-end electronics in the second long shutdown to upgrade the LHC (LS2), which is expected to occur around 2018. The HCAL electronics upgrade is required to handle the major instantaneous luminosity increase (up to 5 * 10{sup 34} cm{sup -2} s{sup -1}) and an expected integrated luminosity of {approx}3000 fb{sup -1}. A key aspect of the HCAL upgrade is to read out longitudinal segmentation information to improve background rejection, energy resolution, and electron isolation at the L1 trigger. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy. The electronics are required to operate in a harsh environment and are constrained by the existing infrastructure. The proposed solutions span from chip level to system level. They include the development of a new ASIC ADC, the design and testing of higher speed transmitters to handle the increased data volume, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design, and improvements in the overall readout architecture. We will report on the progress of the designs for these upgraded systems, along with performance requirements and initial design studies.

  7. CMS hadron calorimeter front-end upgrade for SLHC phase I

    Energy Technology Data Exchange (ETDEWEB)

    Whitmore, Juliana; /Fermilab

    2009-09-01

    We present an upgrade plan for the CMS HCAL detector. The HCAL upgrade is required for the increased luminosity (3 * 10E34) of SLHC Phase I which is targeted for 2014. A key aspect of the HCAL upgrade is to add longitudinal segmentation to improve background rejection, energy resolution, and electron isolation at the L1 trigger. The increased segmentation is achieved by replacing the hybrid photodiodes (HPDs) with silicon PMTs (SIPMs). We plan to instrument each fiber of the calorimeter with an SIPM (103,000 total). We will then electrically sum outputs from selected SIPMs to form the longitudinal readout segments. In addition to having more longitudinal information, the upgrade plans include a new custom ADC with matched sensitivity and timing information. The increased data volume requires higher speed transmitters and the additional power dissipation for the readout electronics requires better thermal design, since much of the on-detector infrastructure (front-end electronics crates, cooling pipes, optical fiber plant, etc.) will remain the same. We will report on the preliminary designs for these upgraded systems, along with performance requirements and initial design studies.

  8. An analog front-end enables electrical impedance spectroscopy system on-chip for biomedical applications

    International Nuclear Information System (INIS)

    The increasing number of applications of electrical bioimpedance measurements in biomedical practice, together with continuous advances in textile technology, has encouraged several researchers to make the first attempts to develop portable, even wearable, electrical bioimpedance measurement systems. The main target of these systems is personal and home monitoring. Analog Devices has made available AD5933, a new system-on-chip fully integrated electrical impedance spectrometer, which might allow the implementation of minimum-size instrumentation for electrical bioimpedance measurements. However, AD5933 as such is not suitable for most applications of electrical bioimpedance. In this work, we present a relatively simple analog front-end that adapts AD5933 to a four-electrode strategy, allowing its use in biomedical applications for the first time. The resulting impedance measurements exhibit a very good performance in aspects like load dynamic range and accuracy. This type of minimum-size, system-on-chip-based bioimpedance measurement system would lead researchers to develop and implement light and wearable electrical bioimpedance systems for home and personal health monitoring applications, a new and huge niche for medical technology development

  9. Joint tests of ALICE TRD track matching units and front end electronics

    International Nuclear Information System (INIS)

    The Transition Radiation Detector (TRD) is one of the main detectors of the ALICE experiment at the LHC. One of its primary objectives is to trigger on high momentum electrons. Based on data from 1.2 million analog channels, event reconstruction must be performed within 6 μs to contribute to the Level-1 trigger decision. A hardware architecture has been developed to achieve the processing in the required time by means of massive parallelism. Analog data pre-processing, track segment detection and parametrization is performed by the front end electronics. Optical multi-gigabit links providing a total bandwidth of 2.7 TBit/s transfer parametrization data to the Global Tracking Unit (GTU) with tight latency requirements. The GTU reconstructs tracks from up to 20000 segments, calculates particle momenta based on track curvatures and produces the trigger contribution. In case of a Level-1 accept, compressed analog data is shipped to and buffered in the GTU for transmission to the data acquisition system. The GTU consists of 108 dedicated CompactPCI boards based on Xilinx Virtex-4 FX chips which offer integrated multi-gigabit deserializers, sufficient logic resources as well as PowerPC cores for monitoring purposes. A number of TMU prototypes were built and joint tests with the detector's first supermodule conducted at CERN. This presentation focuses on the data shipping and buffering system with its low latency requirements and summarizes the current test results. (orig.)

  10. Front-end ASICs development for W Si calorimeter at ILC (CALICE collaboration)

    Science.gov (United States)

    Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle

    2007-03-01

    An ASIC (FLC_PHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e - with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/ f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLC_PHY4), to be tested extensively in test beam at CERN in autumn 2006. FLC_PHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out.

  11. Front-end readout electronics considerations for Silicon Tracking System and Muon Chamber

    International Nuclear Information System (INIS)

    Silicon Tracking System (STS) and Muon Chamber (MUCH) are components of the Compressed Baryonic Matter (CBM) experiment at FAIR, Germany. STS will be built from 8 detector stations located in the aperture of the magnet. Each station will be built from double-sided silicon strip detectors and connected via kapton microcables to the readout electronics at the perimeter of each station. The challenging physics program of the CBM experiment requires from the detector systems very high performance. Design of the readout ASIC requires finding an optimal solution for interaction time and input charge measurements in the presence of: tight area (channel pitch: 58 μ m), noise (< 1000 e- rms), power (< 10 mW/channel), radiation hardness and speed requirements (average hit rate: 250 khit/s/channel). This paper presents the front-end electronics' analysis towards prototype STS and MUCH readout ASIC implementation in the UMC 180 nm CMOS process and in-system performance with the emphasis on preferable detector and kapton microcable parameters and input amplifiers' architecture and design

  12. A Time-Based Front End Readout System for PET & CT

    CERN Document Server

    Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

    2007-01-01

    In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

  13. Continuous-time digital front-ends for multistandard wireless transmission

    CERN Document Server

    Nuyts, Pieter A J; Dehaene, Wim

    2014-01-01

    This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components.  After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware.  As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling.  The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality.  Next, a high-level theoretical analysis of two different PWM-based architectures – baseband PWM and RF PWM – is made.  On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits.  Important design criteria are identified and diff...

  14. Replacing PS controls front end minicomputers by VME based 32-bit processors

    International Nuclear Information System (INIS)

    The PS controls have started the first phase of system rejuvenation, targeted towards the LEP Preinjector Controls. The main impact of this phase is in the architectural change, as both the front-end minicomputers and the CAMAC embedded microprocessors are replaced by microprocessor based VME crates called Device Stub Controllers (DSC). This paper discusses the different steps planned for this first phase, i.e: (1) implementing the basic set of CERN Accelerator common facilities for DSCs (error handling, system surveillance, remote boot and network access); (2) porting the equipment access software layer; (3) applying the Real-time tasks to the LynxOS operating system and I/O architecture, conforming to the real-time constraints for control and acquisition; (4) defining the number and contents of the different DSC needed, according to geographical and cpu-load constraints; (5) providing the general services outside the DSC crates (file servers, data-base services); (6) emulating the current Console programs onto the new workstations. (author)

  15. 2-GHz band man-made noise evaluation for cryogenic receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Narahashi, S; Satoh, K; Suzuki, Y [Research Laboratories, NTT DoCoMo, Inc., 3-5 Hikari-no-oka, Yokosuka, Kanagawa 239-8536 (Japan); Mimura, T [Intellectual Property Department, NTT DoCoMo, Inc., 2-11-1 Nagatacho, Chiyoda, Tokyo 100-6150 (Japan); Nojima, T [Graduate School of Information Science and Technology, Hokkaido University, Nishi 9, Kita 14, Kita, Sapporo 060-0808 (Japan)], E-mail: narahashi@nttdocomo.co.jp

    2008-02-01

    This paper presents measured results of man-made noise in urban and suburban areas in the 2-GHz band with amplitude probability distribution (APD) in order to evaluate the impact of man-made noise on an experimental cryogenic receiver front-end (CRFE). The CRFE comprises a high-temperature superconducting filter, cryogenically-cooled low-noise amplifier, and highly reliable cryostat that is very compact. The CRFE is anticipated to be an effective way to achieve efficient frequency utilization and to improve the sensitivity of mobile base station receivers. It is important to measure the characteristics of the man-made noise in typical cellular base station antenna environments and confirm their impact on the CRFE reception with APD because if man-made noise has a stronger effect than thermal noise, the CRFE would fail to offer any improvement in sensitivity. The measured results suggest that the contribution of man-made noise in the 2-GHz band can be ignored as far as the wideband code division multiple access (W-CDMA) system is concerned.

  16. 2-GHz band man-made noise evaluation for cryogenic receiver front-end

    International Nuclear Information System (INIS)

    This paper presents measured results of man-made noise in urban and suburban areas in the 2-GHz band with amplitude probability distribution (APD) in order to evaluate the impact of man-made noise on an experimental cryogenic receiver front-end (CRFE). The CRFE comprises a high-temperature superconducting filter, cryogenically-cooled low-noise amplifier, and highly reliable cryostat that is very compact. The CRFE is anticipated to be an effective way to achieve efficient frequency utilization and to improve the sensitivity of mobile base station receivers. It is important to measure the characteristics of the man-made noise in typical cellular base station antenna environments and confirm their impact on the CRFE reception with APD because if man-made noise has a stronger effect than thermal noise, the CRFE would fail to offer any improvement in sensitivity. The measured results suggest that the contribution of man-made noise in the 2-GHz band can be ignored as far as the wideband code division multiple access (W-CDMA) system is concerned

  17. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  18. An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

    CERN Document Server

    Porter, Ryan

    This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

  19. Front-end ASICs development for W-Si calorimeter at ILC

    International Nuclear Information System (INIS)

    An ASIC (FLCPHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e- with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLCPHY4), to be tested extensively in test beam at CERN in autumn 2006. FLCPHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out

  20. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  1. The dielectric-filled parabola - A new millimeter/submillimeter wavelength receiver/transmitter front end

    Science.gov (United States)

    Siegel, Peter H.; Dengler, Robert J.

    1991-01-01

    A design is presented for a semi-integrated millimeter/submillimeter wavelength receiver/transmitter front end incorporating a planar antenna and a solid-state device in an efficient feed structure which can be matched directly to high f-number optical systems. The feed system combines the simplicity and robustness of a dielectric substrate lens with the high gain of a parabolic reflector in a single structure that is termed a dielectric-filled parabola. The same fundamental unit can be configured as either a heterodyne or direct detection mode receiver, a power transmitter or a frequency multiplier by changing out the solid-state device and/or the integrated antenna. The structure can also be used with a small integrated antenna array in a multibeam or imaging arrangement. Design and fabrication details for the feed system are given. These are followed by beam pattern and impedance measurements taken on a microwave model when dipole, bow-tie, log-periodic, and log-spiral antennas are used as the integrated feed elements.

  2. Advances in Front-end Enabling Technologies for Thermal Infrared `THz Torch' Wireless Communications

    Science.gov (United States)

    Hu, Fangjing; Lucyszyn, Stepan

    2016-05-01

    The thermal (emitted) infrared frequency bands (typically 20-40 and 60-100 THz) are best known for remote sensing applications that include temperature measurement (e.g. non-contacting thermometers and thermography), night vision and surveillance (e.g. ubiquitous motion sensing and target acquisition). This unregulated part of the electromagnetic spectrum also offers commercial opportunities for the development of short-range secure communications. The `THz Torch' concept, which fundamentally exploits engineered blackbody radiation by partitioning thermally generated spectral radiance into pre-defined frequency channels, was recently demonstrated by the authors. The thermal radiation within each channel can be independently pulse-modulated, transmitted and detected, to create a robust form of short-range secure communications within the thermal infrared. In this paper, recent progress in the front-end enabling technologies associated with the THz Torch concept is reported. Fundamental limitations of this technology are discussed; possible engineering solutions for further improving the performance of such thermal-based wireless links are proposed and verified either experimentally or through numerical simulations. By exploring a raft of enabling technologies, significant enhancements to both data rate and transmission range can be expected. With good engineering solutions, the THz Torch concept can exploit nineteenth century physics with twentieth century multiplexing schemes for low-cost twenty-first century ubiquitous applications in security and defence.

  3. Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

    CERN Document Server

    Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

    1997-01-01

    We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

  4. A dual slope charge sampling analog front-end for a wireless neural recording system.

    Science.gov (United States)

    Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

    2014-01-01

    This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW. PMID:25570655

  5. DAQ system for testing RPC front-end electronics of the INO experiment

    International Nuclear Information System (INIS)

    The Resistive Plate Chamber (RPC) is the active detector element in the INO experiment. The in-house developed ANUSPARSH-III ASICs are being used as front-end electronics of the detector. The 2 m X 2 m RPC being used has 64-readout channels on X-side and 64-readout channels on Y-side. In order to test and validate the FE along with the RPC, a 64-channel DAQ system has been designed and developed. The detector parameters to be measured are noise rate, efficiency, hit pattern register and time resolution. The salient features of the DAQ system are: 64-channel LVDS receiver in FPGA, FPGA based parameter calculations and a micro controller for acquiring the processed data from FPGAs and sent through Ethernet and USB interfaces. The DAQ system consists of following parts: Two FPGAs each receiving 32 LVDS channels, FPGA firm-ware, micro controller firm-ware, Ethernet interface, embedded web server hosting data analysis software, USB interface, and Lab-windows based data analysis software. The DAQ system has been tested at TIFR with 1 m X 1 m RPC

  6. Advances in Front-end Enabling Technologies for Thermal Infrared ` THz Torch' Wireless Communications

    Science.gov (United States)

    Hu, Fangjing; Lucyszyn, Stepan

    2016-09-01

    The thermal (emitted) infrared frequency bands (typically 20-40 and 60-100 THz) are best known for remote sensing applications that include temperature measurement (e.g. non-contacting thermometers and thermography), night vision and surveillance (e.g. ubiquitous motion sensing and target acquisition). This unregulated part of the electromagnetic spectrum also offers commercial opportunities for the development of short-range secure communications. The ` THz Torch' concept, which fundamentally exploits engineered blackbody radiation by partitioning thermally generated spectral radiance into pre-defined frequency channels, was recently demonstrated by the authors. The thermal radiation within each channel can be independently pulse-modulated, transmitted and detected, to create a robust form of short-range secure communications within the thermal infrared. In this paper, recent progress in the front-end enabling technologies associated with the THz Torch concept is reported. Fundamental limitations of this technology are discussed; possible engineering solutions for further improving the performance of such thermal-based wireless links are proposed and verified either experimentally or through numerical simulations. By exploring a raft of enabling technologies, significant enhancements to both data rate and transmission range can be expected. With good engineering solutions, the THz Torch concept can exploit nineteenth century physics with twentieth century multiplexing schemes for low-cost twenty-first century ubiquitous applications in security and defence.

  7. A low power low noise analog front end for portable healthcare system

    Science.gov (United States)

    Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

    2015-10-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

  8. Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

    Directory of Open Access Journals (Sweden)

    Jimmy Nsenga

    2007-03-01

    Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

  9. Digital pulse processing and optimization of the front-end electronics for nuclear instrumentation.

    Science.gov (United States)

    Bobin, C; Bouchard, J; Thiam, C; Ménesguen, Y

    2014-05-01

    This article describes an algorithm developed for the digital processing of signals provided by a high-efficiency well-type NaI(Tl) detector used to apply the 4πγ technique. In order to achieve a low-energy threshold, a new front-end electronics has been specifically designed to optimize the coupling to an analog-to-digital converter (14 bit, 125 MHz) connected to a digital development kit produced by Altera(®). The digital pulse processing is based on an IIR (Infinite Impulse Response) approximation of the Gaussian filter (and its derivatives) that can be applied to the real-time processing of digitized signals. Based on measurements obtained with the photon emissions generated by an (241)Am source, the energy threshold is estimated to be equal to ~2 keV corresponding to the physical threshold of the NaI(Tl) detector. An algorithm developed for a Silicon Drift Detector used for low-energy x-ray spectrometry is also described. In that case, the digital pulse processing is specifically designed for signals provided by a reset-type preamplifier ((55)Fe source). PMID:24326314

  10. Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

    Directory of Open Access Journals (Sweden)

    Nsenga Jimmy

    2007-01-01

    Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

  11. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  12. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0–50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  13. A front-end readout Detector Board for the OpenPET electronics system

    Science.gov (United States)

    Choong, W.-S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C. Q.; Wu, J.-Y.

    2015-08-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ``time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.

  14. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  15. Development of a GUI Based Front End for Open Source CFD Program, OpenFOAM

    Energy Technology Data Exchange (ETDEWEB)

    Han, Samhee; Lee, Youngjin; Kim, Hyongchol; Park, Sunbyung; Kim, Hyunjik [Nuclear Safety Evaluation, Daejeon (Korea, Republic of)

    2013-05-15

    OpenFOAM is sorely lacking in user friendliness as it runs in console mode under Li nux. Run{sub F}OAM was developed to greatly simplify the task of running an OpenFOAM calculation under Windows OS. Run{sub F}OAM was written using Delphi object pascal language, and GLScene package was used for the 3D graphics. Verification of Run{sub F}OAM was carried out by performing some OpenFOAM CFD calculations provided in OpenFOAM package, and these showed that the use of Run{sub F}OAM is simple whilst providing sufficient allowances in user modifications. Run{sub F}oam, a GUI based front end program to simplify running Open Foam CFD cases, has been developed. By incorporating numerous GUI in the program, Run{sub F}oam has demonstrated that running an Open Foam case can be easily accomplished. There is a potential for further development as the Open Foam has the great advantage of being free to develop and to use. There is also a potential to couple or interface the Open Foam with the systems analysis code such as Relap5.

  16. Development of a GUI Based Front End for Open Source CFD Program, OpenFOAM

    International Nuclear Information System (INIS)

    OpenFOAM is sorely lacking in user friendliness as it runs in console mode under Li nux. RunFOAM was developed to greatly simplify the task of running an OpenFOAM calculation under Windows OS. RunFOAM was written using Delphi object pascal language, and GLScene package was used for the 3D graphics. Verification of RunFOAM was carried out by performing some OpenFOAM CFD calculations provided in OpenFOAM package, and these showed that the use of RunFOAM is simple whilst providing sufficient allowances in user modifications. RunFoam, a GUI based front end program to simplify running Open Foam CFD cases, has been developed. By incorporating numerous GUI in the program, RunFoam has demonstrated that running an Open Foam case can be easily accomplished. There is a potential for further development as the Open Foam has the great advantage of being free to develop and to use. There is also a potential to couple or interface the Open Foam with the systems analysis code such as Relap5

  17. One size does not fit all - understanding the front-end and back-ens of business model innovation

    DEFF Research Database (Denmark)

    Günzel, Franziska; Holm, Anna B.

    2013-01-01

    Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed...... understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...... production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance of...

  18. An inquiry on managers use of decision-making tools in the core front end of the innovation process

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.; Howard, Thomas J.

    2013-01-01

    This paper focuses on the Core Front End (CFE) activities of the innovation process to say, Opportunity Identification and Opportunity Analysis. In the CFE of innovation, several tools are used to facilitate and optimise decisions. To select them, managers of the product development team have to...

  19. Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

    International Nuclear Information System (INIS)

    This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about −6 dBm and −3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology. (semiconductor integrated circuits)

  20. A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Johansen, Tom K.; Zhurbenko, Vitaliy

    2013-01-01

    In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured...

  1. 40 CFR 63.490 - Batch front-end process vents-performance test methods and procedures to determine compliance.

    Science.gov (United States)

    2010-07-01

    ... interim status requirements of 40 CFR part 265, subpart O. (c) Batch front-end process vent testing and... applicable procedures of Method 301, 40 CFR part 63, appendix A. (e) Aggregate batch vent stream testing for... under 40 CFR part 270 and complies with the requirements of 40 CFR part 266, subpart H; or (ii)...

  2. A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

  3. A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

    International Nuclear Information System (INIS)

    The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

  4. Evaluation of the Ride-Through Capability of an Active-Front-End Adjustable Speed Drive under Real Grid Conditions

    DEFF Research Database (Denmark)

    Liserre, Marco; Klumpner, Christian; Blaabjerg, Frede;

    2004-01-01

    Better quality of the input currents, unity power factor and regenerative capability are not the only benefits of equipping an Adjustable Speed Drive (ASD) with an active front-end-stage. Controlling the power inflow may enable also the reduction of the dc-link energy storage, which will then lead...

  5. Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

    Science.gov (United States)

    Meng, Zhang; Zhiqun, Li; Zengqi, Wang; Chenjian, Wu; Liang, Chen

    2014-01-01

    This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

  6. A high dynamic range programmable CMOS front-end filter with a tuning range from 1850 to 2400 MHz

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Lee, Thomas H.; Bruun, Erik

    2005-01-01

    This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, -25 dBm in-band 1-d...

  7. Management of radioactive pollutants from front-end nuclear fuel cycle for clean environment - a regulatory approach

    International Nuclear Information System (INIS)

    Front end of Nuclear Fuel Cycle includes mining of low specific active material like uranium and thorium ore, milling of uranium and thorium and fabrication of nuclear fuel assemblies for Nuclear Power Plants. Diverse processes involved in the front-end nuclear fuel cycle lead to handling of wide spectrum of radionuclides. Atomic Energy Regulatory Board (AERB) is entrusted with the responsibility that discharge of the radioactive waste back into the environment does not create any undue hazard to environment and the public. Discharge limits have been prescribed by AERB for front-end fuel cycle facilities such that considering atmospheric, aquatic and terrestrial pathways; the effective dose to members of public does not exceed the yearly limit of 1 mSv. In order to comply with the regulatory limits prescribed by AERB, various treatment measures are adopted by the facilities. For release of conventional pollutants to environment, the limits are prescribed by the State Pollution Control Boards. This paper shall discuss the various treatment procedures adopted by the facilities with respect to radioactivity discharge vis-a-vis the health of the environment around the front-end nuclear fuel cycle facilities. (author)

  8. 75 FR 1179 - Passenger Equipment Safety Standards; Front End Strength of Cab Cars and Multiple-Unit Locomotives

    Science.gov (United States)

    2010-01-08

    ... Transportation (Secretary) convened a meeting of representatives from all sectors of the rail industry with the... Issues Identified for Future Rulemaking C. RSAC Overview D. Establishment of the Passenger Safety Working.... Accident History D. FRA and Industry Standards for Front End Frame Structures of Cab Cars and...

  9. 40 CFR 63.488 - Methods and procedures for batch front-end process vent group determination.

    Science.gov (United States)

    2010-07-01

    ... limit applicable to the batch front-end process vent. (D) Design analysis based on accepted chemical... maximum design production). (iii) The single highest-HAP recipe for a product means the recipe of the product with the highest total mass of HAP charged to the reactor during the production of a single...

  10. Indus-2 beamline personal safety interlocks system

    International Nuclear Information System (INIS)

    Indus-2 is a 2.5 GeV, 300 mA synchrotron radiation source and is currently operating at 2 GeV and 100 mA in the round the clock shift. Two sources of ionizing radiation at Indus-2 can pose a hazard if not properly dealt with are, Bremsstrahlung radiation and synchrotron radiation. The former is mostly generated from collision of electrons with gas molecules and consists of very high energy radiation. A hutch is a structure that houses the beamline and other experimental equipment /apparatus, which is designed to prevent personnel access to areas where there is a potential for the synchrotron beam to generate high levels of ionizing radiation. Hutches are designed to reduce the direct and scattered beam dose rates to acceptably low levels outside. Personal Safety Interlock System (PSIS) is introduced to protect people from accidental exposure to high radiation when the beamlines are in use. PSIS ensures that (1) synchrotron radiation can be allowed to enter an experimental hutch only when no one is present in the hutch and all the doors of the hutch are properly closed; (2) in case of a person entering a hutch during operation, the radiation is stopped by closing the safety shutter and (3) when radiation level in the occupied area near the beamline exceeds the permissible level, it is brought down by closing the safety shutter. The PSIS system is linked with main front-end control system of each beamline. PSIS system consist of relay modules, timers, search and scram buttons, status display panels, door limit switches with latching mechanism and audio-visual alarms. This paper describes, in detail, the design and interlock scheme of a fail-safe and reliable Personal Safety Interlock System implemented at Indus-2 beamlines. (author)

  11. Activities in front-end of uranium fuel cycle in IAEA

    International Nuclear Information System (INIS)

    The Nuclear Fuel Cycle and Materials Section (NFC and MS) in the Division of Nuclear Fuel Cycle and Waste Technology (NEFW) under the Department of Nuclear Energy (NE) of IAEA implements Major Programme 1.B. of the Agency. NFC and MS fosters development of nuclear fuel cycle options that are safe, environment-friendly, economically viable and proliferation-resistant. It promotes information exchange on exploration, mining and processing of uranium and thorium, design, manufacturing, and performance of nuclear fuels, management of spent fuel, including storage and treatment of spent fuel and recycling of plutonium and uranium fuels, and development of advanced and innovative nuclear fuels and fuel cycles through Technical Co-operation, preparation of state-of-theart technical documents, technical meetings, symposia and Coordinated Research Projects (CRP) and databases on nuclear fuels and fuel cycles. The present paper summarizes the portions of the Major Programme 1.B. of IAEA, related to the front-end of uranium fuel cycle, highlighting the activities on uranium supply and demand, exploration, production cycle and environment, the databases, and the technical documents (IAEA/TECDOC) that have been published or under preparation in these areas during the last five years. It reports on the IAEA/OECD-NEA Uranium Red Book, the IAEA database on world distribution of uranium deposits (UDEPO)and the IAEA database on nuclear fuel cycle information system (INFCIS). It discusses the environmental issues in the front-end of the uranium production cycle including mining, milling, chemical purification and long-term management of mine tails, residual materials and radioactive wastes, which are of paramount importance to the uranium industry. The Agency provides guidance on best practices in the planning, operation and closure of uranium production facilities including mine reclamation, from the perspective of changing environmental regulations in mining facilities and growing

  12. Wireless front-end with power management for an implantable cardiac microstimulator.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Hsieh, Cheng-Han; Yang, Chung-Min

    2012-02-01

    Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm², are implemented in a TSMC 0.35 μm 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues. PMID:23852742

  13. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  14. Interference Rejection in UWB LNA using Front-End Triode MOSFET

    Directory of Open Access Journals (Sweden)

    H. Rezaei

    2013-07-01

    Full Text Available In this study, an Ultra Wide Band Low Noise Amplifier (UWB LNA with new input stage for interference rejection is presented. In this scheme, a common gate front end MOS device in triode mode is used to reject in-band and out-band interferences. Furthermore, advantage of weak inversion mode of MOS device is used. While this stage has no DC power consumption, it is possible to easily reject in band and out band interferences with 12.5 and 9.2 dB, respectively. In order to increase power gain of the circuit two stages are added as an amplifier to the circuit. Also, in order to improve the Noise Figure (NF and bandwidth of the circuit, the advantages of thermal noise cancellation technique in the second stage and the series-peaking method in the output buffer are used. The circuit is design in 0.18 μm technology. Simulation results show peak gain of 17.6 dB in the low band (3.1-4.75 GHz and 15.6 dB in the high band (6.1-10.6 GHz. Minimum NF in mentioned frequency band is 3 and 2.3 dB, respectively. Hence, this circuit rejects in band and out band interferences 15.6 and 11.5 dB, respectively, while UWB LNA consumes 16 mW DC power from 1.8 V. The s11 is less than -9.6 dB over entire bandwidth since worst value of IIP3 over entire bandwidth is -14 dBm which occurs at 10.6 GHz.

  15. A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique*

    Institute of Scientific and Technical Information of China (English)

    Fan Mingjun; Ren Junyan; Shu Guanghua; Guo Yao; Li Ning; Ye Fan; Xu Jun

    2011-01-01

    A 12-Bit 40-MS/s pipelined analog-to-digital converter (ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noiseand-distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.

  16. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    Science.gov (United States)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  17. A low power front-end architecture for SiPM readout with integrated ADC and multiplexed readout

    Science.gov (United States)

    Sacco, I.; Fischer, P.; Ritzert, M.; Peric, I.

    2013-01-01

    Silicon Photo-Multiplier (SiPM) detectors are becoming widely used for optical photon and, in conjunction with suited scintillators, for gamma detection in both medical imaging and particle physics experiments. The spatial resolution can be improved by using smaller SiPMs with a corresponding increase in front-end channels density. The timing resolution of the whole system is a function of the detector parameters and of the characteristics of the front-end electronics. We present a low power front-end readout architecture which allows reading out several SiPMs though a single line in order to maximize the number of SiPMs. The design offers good timing performance and includes a simple charge digitizer in every channel. Four different single-ended channel designs have been designed, submitted for fabrication and characterized electronically and with SiPMs. The timing performance is obtained by using a low input impedance, precise threshold setting of a leading edge discriminator and a programmable input dc potential to set the SiPM HV bias on a channel per channel basis. Programmable low- and high-pass filters should allow reducing baseline fluctuations and noise. A simple ADC is implemented by first integrating the signal current and then discharging it at a constant rate until the baseline is reached again. The current consumption of the single channel is typically less than 10 mA. The time and energy information are sent out on a single wire. In order to keep as low as possible the output cabling the signals from different channels can be multiplexed on the same cable. The processing of these signals (extraction of time, ADC amplitude determination and channel number decoding) is performed by an external FPGA. The overall architecture, the front-end designs, and measurements with SiPMs are presented.

  18. 40 CFR Table 6 to Subpart U of... - Group 1 Batch Front-End Process Vents and Aggregate Batch Vent Streams-Monitoring, Recordkeeping...

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Group 1 Batch Front-End Process Vents and Aggregate Batch Vent Streams-Monitoring, Recordkeeping, and Reporting Requirements 6 Table 6 to... 6 to Subpart U of Part 63—Group 1 Batch Front-End Process Vents and Aggregate Batch Vent...

  19. Front-end Design and Implementation of HDMI%HDMI前端设计与实现

    Institute of Scientific and Technical Information of China (English)

    胡湘宏; 蔡述庭; 熊晓明; 詹瑞典

    2015-01-01

    随着高清影音时代的到来,新的高清多媒体接口技术也渐趋成熟。本文研究了高清多媒体接口的编码和解码功能,并采用硬件描述语言实现高清多媒体接口规范定义的编解码功能。首先对高清多媒体接口的整体信道传输过程进行了分析和分解,并阐述了三个数据周期传输时间及其解码方式的不同。在此基础上对编解码功能进行了模块划分,采用分层及模块复用至顶向下的设计方法。最后通过NC-Verilog仿真工具仿真验证代码功能的正确性。%The arrival of the era of high-definition multimedia, including both video images and sounds, requires new definition and realization of the interface technology. The encoding and decoding functions of high-definition multimedia interface are studied in this paper. Using the high-definition multimedia interface specification (HDMI), the front-end design of the encoding and decoding functions is implemented with the hardware description language - Verilog. First, we analyzed and decomposed the transmission process of the whole channel in the high-definition multimedia interface, and elaborated the difference of transmit time in three data periods and decoding methods. Second, based on the analysis, we divided the functions into sub-modules and adopted hierarchical and IP-reuse methodology in our implementation process. Finally, we tested the correctness of the design implementation with both functional verification and circuit simulation.

  20. Front-end electronics for PWO-based PHOS calorimeter of ALICE

    International Nuclear Information System (INIS)

    The electromagnetic Photon Spectrometer (PHOS) of ALICE consists of five modules with 56x64 PWO crystals, operated at -25 oC. Glued to each crystal are APD diodes which amplify a lightyield of 4.4 photoelectrons/MeV, followed by charge-sensitive pre-amplifiers with a charge conversion gain of ca. 1 V/pC. We describe our new 32-channel shaper/digitizer and readout electronics for gain-programmable photodiodes. These Front-End Electronics (FEE) cards are installed below the crystals in an isolated warm volume in geometrical correspondence to 2x16 crystal rows per card. With a total detector capacitance of 100 pF and a noise level of 3 MeV, the FEEs cover a 14 bit dynamic range from 5 MeV to 80 GeV. The low noise level is achieved by operating the APDs and preamplifiers at low temperature and by applying a relatively long shaping time of 1 μs. The offline timing resolution, obtained via a Gamma-2 fit is less than 2 ns. The second-order, dual-gain shapers produce semi-Gaussian output for 10 bit ADCs with embedded multi-event buffers. A Readout Control Unit (RCU) masters data readout with address-mapped access to the event-buffers and controls registers via a custom bus which interconnects up to 14 FEE cards. Programmable bias voltage controllers on the FEE cards allow for very precise gain adjustment of each individual APD. Being co-designed with the TRU trigger cards, each FEE card generates eight fast signal sums (2x2 crystals) as input to the TRU. FPGA-based algorithms generate level-0 and level-1 trigger decisions at 40 MHz and allow PHOS also to operate in self-triggered mode. Inside each PHOS module there are 112 FEE and 8 TRU cards which dissipate ca. 1 kW heat which is extracted via a water cooling system

  1. Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

    International Nuclear Information System (INIS)

    A Very-Front-End (VFE) card is an important part of the on-detector read-out electronics of the CMS (Compact Muon Solenoid) electromagnetic calorimeter that is made of ∼ 76.000 radiation hard scintillating crystals PbWO4 and operates on the Large Hadron Collider (LHC) at CERN. Almost 16.000 VFE cards that shape, amplify and digitize incoming signals from photodetectors generated by interacting particles. Since any maintenance of any part of the calorimeter is not possible during the 10-year lifetime of the experiment, the extensive screening program was employed throughout the whole manufacture process. As a part of readout electronics quality assurance program, the systems for burn-in and precise calibration of the VFE boards were developed and successfully used at IPN Lyon. In addition to functionality tests, all relevant electrical properties of each card were measured and analyzed in detail to obtain their full characterization and to build a database with all required parameters which will serve for the initial calibration of the whole calorimeter. In order to evaluate the calorimeter performance and also to deliver the most precise calibration constants, several fully equipped super-modules were extensively studied and calibrated during the test beam campaigns at CERN. As an important part of these tests, accurate studies of the electronics noise and relative gains, which are needed for measurement in high energy range, were carried out to optimize amplitude reconstruction procedure and thus improve the precision of the calorimeter energy determination. The heart of the thesis consists of the calibration of all VFE boards, including optimization of the laboratory calibration system and precise analysis of measured values to delivered desired calibration constants. The second half of the thesis is focused on the accurate evaluation and optimization of the read-out electronics in real data taking conditions. The results obtained in the laboratory at IPN Lyon

  2. Custom single-photon avalanche diode with integrated front-end for parallel photon timing applications.

    Science.gov (United States)

    Cammi, C; Panzeri, F; Gulinatti, A; Rech, I; Ghioni, M

    2012-03-01

    Emerged as a solid state alternative to photo multiplier tubes (PMTs), single-photon avalanche diodes (SPADs) are nowadays widely used in the field of single-photon timing applications. Custom technology SPADs assure remarkable performance, in particular a 10 counts/s dark count rate (DCR) at low temperature, a high photon detection efficiency (PDE) with a 50% peak at 550 nm and a 30 ps (full width at half maximum, FWHM) temporal resolution, even with large area devices, have been obtained. Over the past few years, the birth of novel techniques of analysis has led to the parallelization of the measurement systems and to a consequent increasing demand for the development of monolithic arrays of detectors. Unfortunately, the implementation of a multidimensional system is a challenging task from the electrical point of view; in particular, the avalanche current pick-up circuit, used to obtain the previously reported performance, has to be modified in order to enable high parallel temporal resolution, while minimizing the electrical crosstalk probability between channels. In the past, the problem has been solved by integrating the front-end electronics next to the photodetector, in order to reduce the parasitic capacitances and consequently the filtering action on the current signal of the SPAD, leading to an improvement of the timing jitter at higher threshold. This solution has been implemented by using standard complementary metal-oxide-semiconductor (CMOS) technologies, which, however, do not allow a complete control on the SPAD structure; for this reason the intrinsic performance of CMOS SPADs, such as DCR, PDE, and afterpulsing probability, are worse than those attainable with custom detectors. In this paper, we propose a pixel architecture, which enables the development of custom SPAD arrays in which every channel maintains the performance of the best single photodetector. The system relies on the integration of the timing signal pick-up circuit next to the

  3. Custom single-photon avalanche diode with integrated front-end for parallel photon timing applications

    Science.gov (United States)

    Cammi, C.; Panzeri, F.; Gulinatti, A.; Rech, I.; Ghioni, M.

    2012-03-01

    Emerged as a solid state alternative to photo multiplier tubes (PMTs), single-photon avalanche diodes (SPADs) are nowadays widely used in the field of single-photon timing applications. Custom technology SPADs assure remarkable performance, in particular a 10 counts/s dark count rate (DCR) at low temperature, a high photon detection efficiency (PDE) with a 50% peak at 550 nm and a 30 ps (full width at half maximum, FWHM) temporal resolution, even with large area devices, have been obtained. Over the past few years, the birth of novel techniques of analysis has led to the parallelization of the measurement systems and to a consequent increasing demand for the development of monolithic arrays of detectors. Unfortunately, the implementation of a multidimensional system is a challenging task from the electrical point of view; in particular, the avalanche current pick-up circuit, used to obtain the previously reported performance, has to be modified in order to enable high parallel temporal resolution, while minimizing the electrical crosstalk probability between channels. In the past, the problem has been solved by integrating the front-end electronics next to the photodetector, in order to reduce the parasitic capacitances and consequently the filtering action on the current signal of the SPAD, leading to an improvement of the timing jitter at higher threshold. This solution has been implemented by using standard complementary metal-oxide-semiconductor (CMOS) technologies, which, however, do not allow a complete control on the SPAD structure; for this reason the intrinsic performance of CMOS SPADs, such as DCR, PDE, and afterpulsing probability, are worse than those attainable with custom detectors. In this paper, we propose a pixel architecture, which enables the development of custom SPAD arrays in which every channel maintains the performance of the best single photodetector. The system relies on the integration of the timing signal pick-up circuit next to the

  4. Soft X-ray absorption analysis in the multi-purpose beamline BL10 at NewSUBARU (2). Cleaning of front mirrors, evaluation of optical properties, and soft X-ray absorption analysis of industrial rubber

    International Nuclear Information System (INIS)

    Optical properties of the multi-purpose beamline BL10 at NewSUBARU (NS) were evaluated after cleaning of carbon contamination on front mirrors (M0, M1). Intensity of the monochromatized beam around the CK edge was recovered with approximately 54% in a 270 - 550 eV region by the cleaning. High resolution XANES in the BK, CK, NK, TiL, and OK regions were successfully measured with a 1800 mm-1 grating. Industrial rubber samples can be analyzed from CK- and OK-XANES, then oxidation of the rubber surface by running on road was clearly observed. Hence, it is confirmed that soft X-ray absorption analysis of light-element samples can be performed in BL10/NS. (author)

  5. Development of a data management front-end for use with a LANDSAT-based information system

    Science.gov (United States)

    Turner, B. J.

    1982-01-01

    The development and implementation of a data management front-end system for use with a LANDSAT based information system that facilitates the processsing of both LANDSAT and ancillary data was examined. The final tasks, reported on here, involved; (1) the implementation of the VICAR image processing software system at Penn State and the development of a user-friendly front-end for this system; (2) the implementation of JPL-developed software based on VICAR, for mosaicking LANDSAT scenes; (3) the creation and storage of a mosiac of 1981 summer LANDSAT data for the entire state of Pennsylvania; (4) demonstrations of the defoliation assessment procedure for Perry and Centre Counties, and presentation of the results at the 1982 National Gypsy Moth Review Meeting, and (5) the training of Pennsylvania Bureau of Forestry personnel in the use of the defoliation analysis system.

  6. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    International Nuclear Information System (INIS)

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption

  7. Fuzzy Decision Support in the Early Phases of the Fuzzy Front End of Innovation in Product Development

    DEFF Research Database (Denmark)

    Achiche, Sofiane; Appio, Francesco Paolo

    2010-01-01

    The innovation process may be divided into three areas: the fuzzy front end (FFE), the new product development (NPD) process, and commercialization. Every NPD process has a FFE in which products and projects are defined. Companies tend to begin the stages of FFE without a clear definition and......, several tools can be used by designers/managers in order to improve, structure and organize their work during the FFE. However, these tools tend to be selected and used in a heuristic manner. Additionally, some tools are preferred and more effective during specific phases of the FFE; hence an economic...... evaluation of the cost of their usage is very critical and there is also a need to characterize them in terms of their influence on the FFE. This paper focuses on decision support for managers/designers in their process of assessing the cost of choosing/using tools in the core front end activities, namely...

  8. Front-end circuit for position sensitive silicon and vacuum tube photomultipliers with gain control and depth of interaction measurement

    Science.gov (United States)

    Herrero, Vicente; Colom, Ricardo; Gadea, Rafael; Lerche, Christoph W.; Cerdá, Joaquín; Sebastiá, Ángel; Benlloch, José M.

    2007-06-01

    Silicon Photomultipliers, though still under development for mass production, may be an alternative to traditional Vacuum Photomultipliers Tubes (VPMT). As a consequence, electronic front-ends initially designed for VPMT will need to be modified. In this simulation, an improved architecture is presented which is able to obtain impact position and depth of interaction of a gamma ray within a continuous scintillation crystal, using either kind of PM. A current sensitive preamplifier stage with individual gain adjustment interfaces the multi-anode PM outputs with a current division resistor network. The preamplifier stage allows to improve front-end processing delay and temporal resolution behavior as well as to increase impact position calculation resolution. Depth of interaction (DOI) is calculated from the width of the scintillation light distribution, which is related to the sum of voltages in resistor network input nodes. This operation is done by means of a high-speed current mode scheme.

  9. Skiroc : a Front-end Chip to Read Out the Imaging Silicon-Tungsten Calorimeter for ILC

    OpenAIRE

    Bouchel, M.; El Berni, M.; Fleury, J.; De La Taille, C.; Martin-Chassard, G.; Raux, L.; Wicek, F.; Bohner, G; Gay, Pascal; Lecoq, J.; Manen, S.; Royer, L.

    2007-01-01

    CALICE Collaboration EUDET Collaboration This abstract describes the new front end ASIC designed for the silicon tungsten electromagnetic calorimeter called SKIROC. This new chip embeds the main features required for the ILC final detector. Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-million-channel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range perform...

  10. A segmented hybrid photon detector with integrated auto-triggering front-end electronics for a PET scanner

    International Nuclear Information System (INIS)

    We describe the design, fabrication and test results of a segmented hybrid photon detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a positron emission tomograph. Emphasis is put on the PET-specific features of the device. The detector has been fabricated in the photocathode facility at CERN

  11. Test results of the ASIC front-end trigger prototypes for the muon barrel detector of CMS at LHC

    International Nuclear Information System (INIS)

    A sample of ASIC prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS was tested on a full size chamber prototype. Tests were performed at several incident angles on cosmic rays and at normal incidence using a muon beam. The chamber was irradiated using a 137Cs gamma source to simulate the LHC radiation environment. The performance of the tested prototypes with respect to efficiency, resolution and noise issues is reported

  12. Dynamics of internal R&D stakeholders in the Fuzzy Front-End of breakthrough engineering projects

    OpenAIRE

    Hooge, Sophie; Dalmasso, Cédric

    2015-01-01

    International audience In competitive industries, intensive innovation is a recognized necessity (Wheelwright and Clark, 1992; Le Masson et al., 2010). One success factor of breakthrough R&D projects lies in the knowledge articulation between innovation definition phases, composed of fuzzy front-end (FFE) and innovative new product development (NPD) stages (Koen et al, 2002; Cooper et al, 2001), and industrial development processes. Then, central issue for innovation projectsmanagers becom...

  13. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  14. The Climate for Creativity and Innovation in the Fuzzy Front End of Innovation : A Case Study at Arla Foods

    OpenAIRE

    Wahlström, Fanny; Jutbo, Malin

    2013-01-01

    Innovation is a key factor for economic development and growth, and firms need to continuously innovate in order to stay competitive. However, innovation is complicated in today’s markets as there are many different aspects for companies to manage. The very first phase of innovation, the fuzzy front end (FFE), is critical and this phase presents one of the greatest opportunities of improvement for the overall innovation process. Yet, the research on this phase is limited. The new product deve...

  15. Best practice project management: an analysis of the front end of the innovation process in the medical technology industry

    OpenAIRE

    Tracey Giles; Kathryn Cormican

    2014-01-01

    There are strong motivating factors for more effective project management practices at the front end of the innovation (FEI) process. Shrewd management of these pre-development activities has proven to be one of the greatest differentials for success. This study presents findings from an empirical case study analysis of a large organization operating in the medical technology industry in Ireland. We synthesized the literature to identify five critical success factors (CSFs) known to be effect...

  16. Web前端的安全防护漫谈%Web front-end Security Protection Discussion

    Institute of Scientific and Technical Information of China (English)

    王广

    2013-01-01

    With the rapid spread ofweb application services, the threats to the web application are very seriousat the same time. Recent years many famous Internetwebsite was be attacked, and most of them focused on the weak protection of web front-end. Web front-end protection has some special characteristic itself, and has been a important branch of web application security. This article introduced some root causes and major threats for web front-end security, and then investigates some principles of web front-end attack. Based on the analysis and comparison, itproposed somesecurity protection methods for the popular attacks.%  Web应用普及的同时,也导致了Web面临了越来越严重的安全威胁.近年来各大网站频繁受到攻击,其中很多攻击针对以前比较薄弱的Web前端.Web前端的安全防护具有自身的独特性,并已经成为Web应用安全的一个重要分支.首先研究了Web前端安全隐患产生的根源以及面临的主要威胁,并介绍了一些web前端攻击方式的原理.在分析和比较的基础上,针对当前主流的攻击提出一些安全防护的解决方法.

  17. Silicon-Based RFIC Multi-band Transmitter Front Ends for Ultra-Wideband Communications and Sensor Applications

    OpenAIRE

    Zhao, Jun

    2007-01-01

    Fully integrated Ultra-Wideband (UWB) RFIC transmitters are designed in Si-based technologies for applications such as wireless communications or sensor networks. UWB technology offers many unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks and frequency ...

  18. Web front-end Security Protection Discussion%Web前端的安全防护漫谈

    Institute of Scientific and Technical Information of China (English)

    王广

    2013-01-01

      Web应用普及的同时,也导致了Web面临了越来越严重的安全威胁.近年来各大网站频繁受到攻击,其中很多攻击针对以前比较薄弱的Web前端.Web前端的安全防护具有自身的独特性,并已经成为Web应用安全的一个重要分支.首先研究了Web前端安全隐患产生的根源以及面临的主要威胁,并介绍了一些web前端攻击方式的原理.在分析和比较的基础上,针对当前主流的攻击提出一些安全防护的解决方法.%With the rapid spread ofweb application services, the threats to the web application are very seriousat the same time. Recent years many famous Internetwebsite was be attacked, and most of them focused on the weak protection of web front-end. Web front-end protection has some special characteristic itself, and has been a important branch of web application security. This article introduced some root causes and major threats for web front-end security, and then investigates some principles of web front-end attack. Based on the analysis and comparison, itproposed somesecurity protection methods for the popular attacks.

  19. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  20. Design of Microwave Front-End Narrowband Filter and Limiter Components

    Science.gov (United States)

    Cross, Lee W.

    This dissertation proposes three novel bandpass filter structures to protect systems exposed to damaging levels of electromagnetic (EM) radiation from intentional and unintentional high-power microwave (HPM) sources. This is of interest because many commercial microwave communications and sensor systems are unprotected from high power levels. Novel technologies to harden front-end components must maintain existing system performance and cost. The proposed concepts all use low-cost printed circuit board (PCB) fabrication to create compact solutions that support high integration. The first proposed filter achieves size reduction of 46% using a technology that is suitable for low-loss, narrowband filters that can handle high power levels. This is accomplished by reducing a substrate-integrated waveguide (SIW) loaded evanescent-mode bandpass filter to a half-mode SIW (HMSIW) structure. Demonstrated third-order SIW and HMSIW filters have 1.7 GHz center frequency and 0.2 GHz bandwidth. Simulation and measurements of the filters utilizing combline resonators prove the underlying principles. The second proposed device combines a traditional microstrip bent hairpin filter with encapsulated gas plasma elements to create a filter-limiter: a novel narrowband filter with integral HPM limiter behavior. An equivalent circuit model is presented for the ac coupled plasma-shell components used in this dissertation, and parameter values were extracted from measured results and EM simulation. The theory of operation of the proposed filter-limiter was experimentally validated and key predictions were demonstrated including two modes of operation in the on state: a constant output power mode and constant attenuation mode at high power. A third-order filter-limiter with center frequency of 870 MHz was demonstrated. It operates passively from incident microwave energy, and can be primed with an external voltage source to reduce both limiter turn-on threshold power and output power

  1. Understanding the Front-end of Large-scale Engineering Programs

    DEFF Research Database (Denmark)

    Lucae, Sebastian; Rebentisch, Eric; Oehmen, Josef

    2014-01-01

    Large engineering programs like sociotechnical infrastructure constructions of airports, plant constructions, or the development of radically innovative, high-tech industrial products such as electric vehicles or aircraft are affected by a number of serious risks, and subsequently commonly suffer...... from large cost overruns. Significant problems in program execution can be traced back to practices performed, or more frequently not performed, in the so-called “fuzzy front end” of the program. The lack of sufficient and effective efforts in the early stages of a program can result in unstable......, unclear and incomplete requirements, unclear roles and responsibilities within the program organization, insufficient planning, and unproductive tensions between program management and systems engineering. This study intends to clarify the importance of up-front planning to improve program performance, to...

  2. Energy resolution and power consumption of Timepix detector for different detector settings and saturation of front-end electronics

    International Nuclear Information System (INIS)

    An ongoing research project in the area of radiation monitoring employing the Timepix technology from the CERN-based Medipix2 Collaboration profits greatly from optimizing the precision of the position and energy information obtained for the detected quanta. Wider applications of the Timepix technology as a radiation monitor also puts new demands on the precision and speed of the energy calibration. We compare the analog signal in pixel front-end electronics for different sources used during detector evaluation and energy calibration. We use the direct measurement of the analog signal from the pixel preamplifier and comparator to characterize pulse shape differences for different sources, e.g. internal test pulses, external test pulses, ionizing radiation, etc. and study their interchangeability. Accurate per-pixel energy calibration of the Timepix detector enables the direct measurement of the energy deposited by different types of ionizing radiation. The energy calibration process requires the application of a known charge to front-end electronics of each pixel. The small pixel size limits use of the radioactive sources. The 59.54 keV line from 241Am is commonly used as the highest point in calibration curve. The heavy ion dosimetry as encountered in the space radiation environment requires a considerable extrapolation to the energies in the MeV range. We have observed that for energies around and beyond 1 MeV the response of the Timepix's front-end electronics no longer follows the extrapolated calibration function. We have investigated this non-linearity and identified its source. We also propose both hardware and software solutions to suppress this effect. In this paper we show the impact on pixel calibration and the subsequent energy resolution for different detector settings as well as the resulting power consumptions. We discuss the parameter optimization for several different real-world applications

  3. Test results of the ASIC front-end trigger prototypes for the muon barrel detector of CMS at LHC

    CERN Document Server

    De Giorgi, M; Dosselli, U; Gasparini, F; Gasparini, U; Gonella, F; Guaita, P; Lippi, I; Meneguzzo, Anna Teresa; Passaseo, M; Pegoraro, M; Ronchese, P; Ponte-Sancho, A J; Martinelli, R; Torassa, E; Ventura, L; Zotto, P L; Zumerle, G

    1999-01-01

    A sample of ASIC prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS was tested on a full size chamber prototype. Tests were performed at several incident angles on cosmic rays and at normal incidence using a muon beam. The chamber was irradiated using a /sup 137/Cs gamma source to simulate the LHC radiation environment. The performance of the tested prototypes with respect to efficiency, resolution and noise issues is reported. (9 refs).

  4. Efficiency studies of the front-end trigger device of the muon drift tubes for the CMS detector at LHC

    International Nuclear Information System (INIS)

    Three simplified prototypes of the first-level trigger front-end device for the muon barrel drift chambers of CMS were tested on a chamber prototype. Tests were performed at several incidence angles of a muon beam and with different magnetic field configurations. The recorded drift times were also used to test a full software model reproducing the actual algorithm applied in the final ASIC being produced. The efficiency performance of this software model and of the tested prototype are presented in this paper. (orig.)

  5. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    International Nuclear Information System (INIS)

    The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception

  6. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  7. Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

    International Nuclear Information System (INIS)

    The Large Hadron Collider will be upgraded to provide instantaneous luminosity L = 5 × 1034 cm−2s−1, leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20 μs in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of pT ∼ 25 GeV, which will be of great benefit to the future physics programme of ATLAS.

  8. Performance of the front-end signal processing electronics for the drift chambers of the Stanford large detector

    International Nuclear Information System (INIS)

    This paper reports on the performance of the front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector (SLD) detector at the Stanford Linear Collider. The electronics mounted on printed circuit boards include up to 64 channels of transimpedance amplification, analog sampling, A/D conversion, and associated control circuitry. Measurements of the time resolution, gain, noise, linearity, crosstalk, and stability of the readout electronics are described and presented. The expected contribution of the electronics to the relevant drift chamber measurement resolutions (i.e., timing and charge division) is given

  9. Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

    Science.gov (United States)

    Monteil, E.; Demaria, N.; Pacher, L.; Rivetti, A.; Da Rocha Rolo, M.; Rotondo, F.; Leng, C.

    2016-03-01

    The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

  10. CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

    International Nuclear Information System (INIS)

    The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

  11. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    Loddo, Flavio

    2015-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  12. Influencing factors for sustainable design implementation in the front-end of new product development process within the Fast-Moving-Consumer-Goods sector

    OpenAIRE

    Park, Curie

    2015-01-01

    This study examines and verifies the influencing factors for sustainable design implementation in the front-end stages of New Product Development (NPD) process within the Fast-Moving-Consumer-Goods (FMCG) sector. Despite many arguments that the early consideration of sustainable design is key to successful sustainable product development, there is a paucity of research that approaches sustainable design implementation from an NPD front-end perspective. Moreover, sustainable design research...

  13. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  14. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  15. 10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

    Institute of Scientific and Technical Information of China (English)

    Fan Chao; Chen Tangsheng; Yang Lijie; Feng Ou; Jiao Shilong; Wu Yunfeng; Ye Yutang

    2009-01-01

    A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.

  16. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I2C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  17. A wideband large dynamic range and high linearity RF front-end for U-band mobile DTV

    International Nuclear Information System (INIS)

    A wideband large dynamic range and high linearity U-band RF front-end for mobile DTV is introduced, and includes a noise-cancelling low-noise amplifier (LNA), an RF programmable gain amplifier (RFPGA) and a current communicating passive mixer. The noise/distortion cancelling structure and RC post-distortion compensation are employed to improve the linearity of the LNA. An RFPGA with five stages provides large dynamic range and fine gain resolution. A simple resistor voltage network in the passive mixer decreases the gate bias voltage of the mixing transistor, and optimum linearity and symmetrical mixing is obtained at the same time. The RF front-end is implemented in a 0.25 μm CMOS process. Tests show that it achieves an IIP3 (third-order intercept point) of −17 dBm, a conversion gain of 39 dB, and a noise figure of 5.8 dB. The RFPGA achieves a dynamic range of −36.2 to 23.5 dB with a resolution of 0.32 dB. (semiconductor integrated circuits)

  18. A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

    Science.gov (United States)

    Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

    2016-05-01

    This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

  19. Development of a front-end system for chirped pulse amplification high-power Nd:glass laser

    International Nuclear Information System (INIS)

    We have developed a front-end system to generate a chirped pulse at a wavelength of 1053 nm for a 100 TW glass laser system. The front-end system consists of a passively mode-locked diode-pumped Nd:glass laser, a pulse stretcher and a Ti:Al2O3 regenerative amplifier. The passive mode-locked diode-pumped Nd:fluorophosphate glass laser produced pulses as short as 150 fs at an average power of 100 mW at 1053 nm-1061 nm at a repetition frequency of 99.98 MHz. The TEM00 Ti:Al2O3 regenerative amplifier exhibited a net gain of over 106 at 1053 nm. At long time operation, the output pulse energy is typically 4 mJ, with a power fluctuation of less than ±5% with temperature and humidity control in cavity. No significant gain narrowing was observed in the cavity, resulting in a 1.6 ns chirped pulse that was synchronized with the RF signal of GEKKO XII laser system within a few ps by controlling the oscillator cavity length with a PZT actuator. (author)

  20. Development of a front-end system for chirped pulse amplification high-power Nd:glass laser

    Energy Technology Data Exchange (ETDEWEB)

    Yoshida, Hidetsugu; Kodama, Ryosuke; Fujita, Hisanori; Kato, Yoshiaki; Mima, Kunioki [Osaka Univ., Suita (Japan). Inst. of Laser Engineering

    1999-04-01

    We have developed a front-end system to generate a chirped pulse at a wavelength of 1053 nm for a 100 TW glass laser system. The front-end system consists of a passively mode-locked diode-pumped Nd:glass laser, a pulse stretcher and a Ti:Al{sub 2}O{sub 3} regenerative amplifier. The passive mode-locked diode-pumped Nd:fluorophosphate glass laser produced pulses as short as 150 fs at an average power of 100 mW at 1053 nm-1061 nm at a repetition frequency of 99.98 MHz. The TEM{sub 00} Ti:Al{sub 2}O{sub 3} regenerative amplifier exhibited a net gain of over 10{sup 6} at 1053 nm. At long time operation, the output pulse energy is typically 4 mJ, with a power fluctuation of less than {+-}5% with temperature and humidity control in cavity. No significant gain narrowing was observed in the cavity, resulting in a 1.6 ns chirped pulse that was synchronized with the RF signal of GEKKO XII laser system within a few ps by controlling the oscillator cavity length with a PZT actuator. (author)

  1. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2015-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  2. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  3. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e− at zero farad plus 5.4 e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel

  4. Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

    International Nuclear Information System (INIS)

    A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-μm CMOS technology. The S11 of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply. (semiconductor integrated circuits)

  5. Noise-canceling and IP3 improved CMOS RF front-end for DRM/DAB/DVB-H applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Keping; Wang Zhigong; Lei Xuemei, E-mail: zgwang@seu.edu.c [Institute of RF- and OE-ICs, Southeast University, Nanjing 210096 (China)

    2010-02-15

    A CMOS RF (radio frequency) front-end for digital radio broadcasting applications is presented that contains a wideband LNA, I/Q-mixers and VGAs, supporting other various wireless communication standards in the ultra-wide frequency band from 200 kHz to 2 GHz as well. Improvement of the NF (noise figure) and IP3 (third-order intermodulation distortion) is attained without significant degradation of other performances like voltage gain and power consumption. The NF is minimized by noise-canceling technology, and the IP3 is improved by using differential multiple gate transistors (DMGTR). The dB-in-linear VGA (variable gain amplifier) exploits a single PMOS to achieve exponential gain control. The circuit is fabricated in 0.18-{mu}m CMOS technology. The S{sub 11} of the RF front-end is lower than -11.4 dB over the whole band of 200 kHz-2 GHz. The variable gain range is 12-42 dB at 0.25 GHz and 4-36 dB at 2 GHz. The DSB NF at maximum gain is 3.1-6.1 dB. The IIP3 at middle gain is -4.7 to 0.2 dBm. It consumes a DC power of only 36 mW at 1.8 V supply. (semiconductor integrated circuits)

  6. A hearing aid on-chip system based on accuracy optimized front- and back-end blocks

    International Nuclear Information System (INIS)

    A hearing aid on-chip system based on accuracy optimized front- and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front- and back-end blocks, respectively, so as to alleviate the nonlinearity distortion caused by the output swing. By using the technique, the accuracy of the whole hearing aid system can be significantly improved. The prototype chip has been designed with a 0.13 μm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 Ω loudspeaker with a normalized output level of 300 mVp-p, the total harmonic distortion reached about −60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 μVrms. (semiconductor integrated circuits)

  7. Experimental validation of a method for performance monitoring of the front-end permeators in the TEP system of ITER

    International Nuclear Information System (INIS)

    The reference process for the Tokamak Exhaust Processing (TEP) system of ITER is called CAPER and comprises three different, consecutive steps to recover hydrogen isotopes at highest purity for direct transfer to the cryogenic isotope separation system (ISS). The CAPER process was developed at the Tritium Laboratory Karlsruhe (TLK) and employs a palladium/silver permeator battery as the 1st step to separate more than 95% of the un-burnt deuterium/tritium fuel from impurities like helium, hydrocarbons and water. These so-called front-end permeators have a capacity of about 80 mol h-1/1 m2 effective surface area if operated under conditions currently specified for ITER. The front-end permeators of ITER should all the time be operated such that coking of the permeation membranes by hydrocarbon cracking is avoided, since this process lead to a reduction of the effective surface area and therefore to a reduction of the performance of the component. At TLK a method to measure the actual performance of a technical permeator has been developed. This method has been successfully tested with the experimental facility for the demonstration of the CAPER process at TLK and appears feasible for the TEP system of ITER

  8. A 0.5-V multi-channel low-noise readout front-end for portable EEG acquisition.

    Science.gov (United States)

    Wen-Yen Huang; Yu-Wei Cheng; Kea-Tiong Tang

    2015-08-01

    This article presents a low-noise readout front-end suitable for Electroencephalogram (EEG) acquisition. The chip includes 8-channel fully-differential instrumentation amplifiers, utilizing chopper stabilization technique for reducing the flicker noise, each amplifier with a small Gm-C low-pass filter, a programmable gain amplifier, and a 10-bit successive approximation register (SAR) ADC with a detect logic for DAC switching. The chip is fabricated with the TSMC 90nm CMOS process. The low-noise readout front-end has simulated frequency response from 0.57 Hz to 213 Hz, programmable gain from 54.4 dB to 87.6 dB, integrated input-referred noise of 0.358 μVrms within EEG bandwidth, a noise efficiency factor (NEF) of 2.43, and a power efficiency factor (PEF) of 2.95. The overall system consumes 32.08 μW under 0.5-V supply. PMID:26736392

  9. Development of C-Band RF Front-end of Precision Coherent Mono-pulse C-Band Radar

    Directory of Open Access Journals (Sweden)

    Arun Kumar Ray

    2014-07-01

    Full Text Available A compact, robust and high performance front-end of a radar receiver is designed and demonstrated in this paper. The important parameters like noise figure, sensitivity, selectivity, dynamic range and tracking range are superior to that of the existing systems and facilitate online monitoring of the above important parameters. The gain and phase matching facility are incorporated. The local oscillator is integrated within the module which in turn reduces the losses as compare with the existing local oscillator, placed in the instrumentation cabin. The frequency, amplitude, delay between skin and transponder frequency can be controlled remotely by computer program. Therefore, the mixed mode operation (skin and transponder of radar receiver is possible. Moreover, the SPDT switch is integrated in the same module for RF simulation to facilitate the three channel mono-pulse receiver calibration, receiver health monitoring and range calibration of precision coherent mono-pulse C-band radar. The components used are monolithic microwave integrated circuit based technologies with superior specifications, makes the total module miniaturized and reduced the hardware complications. The total power consumption is much less and improves the overall performance than the existing front-end.Defence Science Journal, Vol. 64, No. 4, July 2014, pp. 358-365, DOI:http://dx.doi.org/10.14429/dsj.64.4245 

  10. Use of object-oriented techniques in a beam-line control system

    International Nuclear Information System (INIS)

    The authors describe the use of object-oriented programming in the control and data-acquisition system for the upgraded CERN neutrino beam-line. C++ in conjunction with Posix threads running under Lynx-OS have been used in several front-end PCs. These communicate using Remote Procedure Calls over ethernet with a workstation running the commercial supervisory package, FactoryLink

  11. The Design and Evaluation of a Front-End User Interface for Energy Researchers.

    Science.gov (United States)

    Borgman, Christine L.; And Others

    1989-01-01

    Reports on the Online Access to Knowledge (OAK) Project, which developed software to support end user access to a Department of Energy database based on the skill levels and needs of energy researchers. The discussion covers issues in development, evaluation, and the study of user behavior in designing an interface tailored to a special…

  12. Microphone front-ends for spatial sound analysis and synthesis with Directional Audio Coding

    OpenAIRE

    Ahonen, Jukka

    2013-01-01

    A large number of professional and domestic audio applications utilize spatial soundreproduction. In addition to the conventional applications, such as the surround sound inmovie and home theaters, spatial sound is also applied for telecommunication purposes. Forinstance in teleconferencing, sound emanated by talkers can be captured with multiplemicrophones at one end and reproduced spatially distributed with multiple loudspeakers at theother. This has benefit over a typical monophonic reprodu...

  13. Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

    Science.gov (United States)

    Kureba, C. O.; Govender, M.; Hofsajer, I.; Ruan, X.; Sandrock, C.; Spoor, M.

    2015-10-01

    The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade.

  14. Inelastic X-ray Scattering Beamline Collaborative Development Team Final Report

    International Nuclear Information System (INIS)

    This is the final report for the project to create a beam line for inelastic x-ray scattering at the Advanced Photon Source. The facility is complete and operating well, with spectrometers for both high resolution and medium resolution measurements. With the advent of third generation synchrotron sources, inelastic x-ray scattering (IXS) has become a valuable technique to probe the electronic and vibrational states of a wide variety of systems of interest in physics, chemistry, and biology. IXS is a weak probe, and experimental setups are complex and require well-optimized spectrometers which need a dedicated beamline to function efficiently. This project was the result of a proposal to provide a world-class, user friendly beamline for IXS at the Advanced Photon Source. The IXS Collaborative Development Team (IXS-CDT) was formed from groups at the national laboratories and a number of different universities. The beamline was designed from the front end to the experimental stations. Two different experimental stations were provided, one for medium resolution inelastic x-ray scattering (MERIX) and a spectrometer for high resolution inelastic x-ray scattering (HERIX). Funding for this project came from several sources as well as the DOE. The beamline is complete with both spectrometers operating well. The facility is now open to the general user community and there has been a tremendous demand to take advantage of the beamline's capabilities. A large number of different experiments have already been carried out on the beamline. A detailed description of the beamline has been given in the final design report (FDR) for the beamline from which much of the material in this report came. The first part of this report contains a general overview of the project with more technical details given later.

  15. Performance Trade-Off Analysis Comparing Different Front-End Configurations for a Digital X-ray Imager.

    Science.gov (United States)

    Kuhls-Gilcrist, Andrew; Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2010-10-30

    Performance of indirect digital x-ray imagers is typically limited by the front-end components. Present x-ray-to-light converting phosphors significantly reduce detector resolution due to stochastic blurring and k-fluorescent x-ray reabsorption. Thinner phosphors improve resolution at the cost of lowering quantum detection efficiency (QDE) and increasing Swank noise. Magnifying fiber optic tapers (FOTs) are commonly used to increase the field-of-view of small sensor imagers, such as CMOS, CCD, or electron-multiplying CCD (EMCCD) based detectors, which results in a reduction in detector sensitivity and further reduces the MTF. We investigate performance trade-offs for different front-end configurations coupled to an EMCCD sensor with 8 μm pixels. Six different columnar structured CsI(Tl) scintillators with thicknesses of 100, 200, 350, 500, and 1000 μm type high-light (HL) and a 350 μm type high-resolution (HR) (Hamamatsu) and four different FOTs with magnification ratios (M) of 1, 2.5, 3.3, and 4 were studied using the RQA5 x-ray spectrum. The relative signal of the different scintillators largely followed the relative QDE, indicating their light output per absorbed x-ray was similar, with the type HR CsI emitting 57% of the type HL. The efficiency of the FOTs was inversely proportional to M(2) with the M = 1 FOT transmitting 87% of the incident light. At 5 (10) cycles/mm, the CsI MTF was 0.38 (0.22), 0.33 (0.17), 0.37 (0.19), 0.23 (0.09), 0.19 (0.08), and 0.09 (0.03) for the 100, 200, 350HR, 350, 500, and 1000 μm CsI, respectively and the FOT MTF was 0.89 (0.84), 0.80 (0.72), 0.70 (0.60), and 0.69 (0.37) for M = 1, 2.5, 3.3, and 4, respectively. The 1000, 500, and 350HR μm CsI had the highest DQE for low, medium, and high spatial frequency ranges of 0 to 1.6, 1.6 to 4.5, and 4.5 to 10 cycles/mm, respectively. Larger FOT M resulted in a reduction in DQE. Quantifying performance of different front-end configurations will enable optimal selection of components

  16. New Synchrotron Radiation Center beamlines at Aladdin

    International Nuclear Information System (INIS)

    In the past year, the Synchrotron Radiation Center (SRC) staff has installed five new beamlines at SRC. Three of these beamlines are ''public'' beamlines operated by SRC for experiments selected from peer-reviewed proposals. Fifty to seventy-five percent of the experimental time on the other two beamlines is managed by the SRC as a consequence of the SRC being a partner in participating research teams (PRTs). These new beamlines bring the number of VUV and soft x-ray research beamlines installed on Aladdin to 17 as of August 1988. Including two storage ring optical diagnostic ports, there will be 20 ports in use on Aladdin by the end of 1988

  17. Controller design and implementation of a three-phase Active Front End using SiC based MOSFETs

    DEFF Research Database (Denmark)

    Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

    2015-01-01

    The design and implementation of a three phase Active Front End for power factor correction purposes using fast switching SiC based MOSFETs is presented. Possible applications are within the drives- and renewable energy sector. The controller is designed and implemented in the synchronous rotating...... factor correction for an active rectifier in comparison to a passive rectifier. The SiC based power switches thereby offer the possibility of using high switching frequencies leading to a reduction in filter size - here a simple L filter. The controller is able to validate the simulation results...... reference frame. Besides the theoretical modelling the controller is optimized through simulations and implemented on a low cost DSP processor using a visual programming language - here MATLAB/SIMULINK - with automatic code generation for embedded targets. The paper illustrates the advantages of power...

  18. A Front-End electronics board for single photo-electron timing and charge from MaPMT

    International Nuclear Information System (INIS)

    A Front-End (FE) design based on commercial operational amplifiers has been developed to read-out signals from a Multianode PhotoMultiplier Tube (MaPMT). The overall design has been optimised for single photo-electron signal from the Hamamatsu H8500. The signal is collected by a current sensitive preamplifier and then it is fed into both a ECL fast discriminator and a shaper for analog output readout in differential mode. The analog signal and the digital gates are then registered on VME ADC and TDC modules respectively. Performances in terms of linearity, gain and timing resolution will be discussed, presenting results obtained on a test bench with differentiated step voltage inputs and also with a prototype electronic board plugged into the H8500 PMT illuminated by a picosecond laser

  19. A low noise front end electronics for micro-channel plate detector with wedge and strip anode

    Science.gov (United States)

    Hu, K.; Li, F.; Liang, F.; Chen, L.; Jin, G.

    2016-03-01

    A low noise Front End Electronics (FEE) for two-dimensional position sensitive Micro-Channel Plate (MCP) detector has been developed. The MCP detector is based on Wedge and Strip Anode (WSA) with induction readout mode. The WSA has three electrodes, the wedge electrode, the strip electrode, and the zigzag electrode. Then, three readout channels are designed in the Printed Circuit Board (PCB). The FEE is calibrated by a pulse generator from Agilent. We also give an analysis of the charge loss from the CSA. The noise levels of the three channels are less than 1 fC RMS at the shaping time of 200 ns. The experimental result shows that the position resolution of the MCP detector coupled with the designed PCB can reach up to 110 μm.

  20. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    International Nuclear Information System (INIS)

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.