WorldWideScience

Sample records for beamline front ends

  1. Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

    International Nuclear Information System (INIS)

    Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al2O3)- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

  2. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  3. First photon-shutter development for APS insertion device beamline front ends

    Science.gov (United States)

    Shu, Deming; Nian, H. L. Thomas; Wang, Zhibi; Collins, Jeffrey T.; Ryding, David G.; Kuzay, Tuncer M.

    1993-02-01

    One of the most critical components on the Advanced Photon Source (APS) insertion device (ID) beamline front ends is the first photon shutter. It operates in two modes to fully intercept the high total power and high-heat-flux ID photon beam in seconds (normal mode) or in less than 100 ms (emergency fast mode). It is designed to operate in ultra high vacuum (UHV). The design incorporates a multi-channel rectangular bar, bent in a `hockey stick' configuration, with two-point suspension. The flanged end is an articulated bellows with rolling hinges. The actuation end is a spring-assisted, pneumatic fail-safe flexural pivot type. The coolant (water) channels incorporate brazed copper foam to enhance the heat transfer, a tube technology particular to the APS. The design development, and material aspects, as well as the extensive thermal and vibrational analyses in support of the design, are presented in this paper.

  4. New x-ray pink-beam profile monitor system for the SPring-8 beamline front-end.

    Science.gov (United States)

    Takahashi, Sunao; Kudo, Togo; Sano, Mutsumi; Watanabe, Atsuo; Tajiri, Hiroo

    2016-08-01

    A new beam profile monitoring system for the small X-ray beam exiting from the SPring-8 front-end was developed and tested at BL13XU. This system is intended as a screen monitor and also as a position monitor even at beam currents of 100 mA by using photoluminescence of a chemical vapor deposition-grown diamond film. To cope with the challenge that the spatial distribution of the photoluminescence in the vertical direction is too flat to detect the beam centroid within a limited narrow aperture, a filter was installed that absorbs the fundamental harmonic concentrated in the beam center, which resulted in "de-flattening" of the vertical distribution. For the measurement, the filter crossed the photon beam vertically at high speed to withstand the intense heat flux of the undulator pink-beam. A transient thermal analysis, which can simulate the movement of the irradiation position with time, was conducted to determine the appropriate configuration and the required moving speed of the filter to avoid accidental melting. In a demonstration experiment, the vertically separated beam profile could be successfully observed for a 0.8 × 0.8 mm(2) beam shaped by an XY slit and with a fundamental energy of 18.48 keV. The vertical beam centroid could be detected with a resolution of less than 0.1 mm. PMID:27587104

  5. Intelligent Front Ends

    OpenAIRE

    Bundy, Alan

    1984-01-01

    An intelligent front end is a user-friendly interface to a software package, which uses Artificial Intelligence techniques to enable the user to interact with the computer using his/her own terminology rather than that demanded by the package. Several such systems exist and provide interfaces for finite element. statistical and simulation packages, and the area is an important area of growth for expert systems. In this paper we discuss the techniques required in an intelligent ...

  6. SNS Front End Diagnostics

    CERN Document Server

    Doornbos, J; Oshatz, D; Ratti, A; Staples, J W

    2000-01-01

    The Front End of the Spallation Neutron Source (SNS) extends from the Ion Source (IS), through a 65 keV LEBT, a 402.5 MHz RFQ, a 2.5 MeV MEBT, ending at the entrance to the DTL. The diagnostics suite in this space includes stripline beam position and phase monitors (BPM), toroid beam current monitors (BCM), and an emittance scanner. Provision is included for beam profile measurement, either gas fluorescence, laser-based photodissociation, or a crawling wire. Mechanical and electrical design and prototyping of BPM and BCM subsystems are proceeding. Significant effort has been devoted to packaging the diagnostic devices in minimal space. Close ties are maintained to the rest of the SNS effort, to ensure long term compatibility of interfaces and in fact share some design work and construction. The data acquisition, digital processing, and control system interface needs for the BPM, BCM, and LEBT diagnostic are similar, and we are committed to using an architecture common with the rest of the SNS collaboration.

  7. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  8. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  9. SPD very front end electronics

    International Nuclear Information System (INIS)

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  10. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik;

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  11. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  12. The front end electronics for LHCb calorimeters

    CERN Document Server

    Beigbeder-Beau, C; Breton, D; Cacéres, T; Callot, O; Cros, P; Delcourt, B; Jean-Marie, B; Lefrançois, J; Hrisoho, A T; Tocut, V; Truong, K D; Videau, I

    1999-01-01

    The electronics for the electromagnetic and hadronic calorimeters of LHCb is under design. The 32 channel-9U front-end board offers the complete front-end and readout electronics for every channel including original shaping, 12bit-40MHz ADC, digital filtering and latency for level 0 and level 1 triggers. The clipped PM input signal is integrated during 25ns, but also delayed then subtracted to itself 25ns later which allows performant pile up independence. This board also includes the first processing levels of the L0 calorimeter trigger. A 16 channel-6U prototype board has been designed and used at CERN in test beam in 1999.

  13. JFET-CMOS microstrip front-end

    International Nuclear Information System (INIS)

    While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper. (orig.)

  14. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  15. CDF front end electronics: The RABBIT system

    International Nuclear Information System (INIS)

    A new crate-based front end system has been built featuring low cost, compact packaging, fast readout, command capability, 16 bit digitiziation, and a high degree of redundancy. The crate can contain a variety of instrumentation modules and is designed to be placed near the detector. Remote, special purpose processors direct the data readout. Channel-by-channel pedestal subtraction and threshold comparison in the crate allow the skipping of empty channels. The system is suitable for the readout of a very large number of channels. (orig.)

  16. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  17. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  18. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  19. The upgraded CDF front end electronics for calorimetry

    International Nuclear Information System (INIS)

    The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

  20. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  1. Design, fabrication, installation and commissioning of water-cooled beam viewer for undulator front-ends of Indus-2

    International Nuclear Information System (INIS)

    A water-cooled beam viewer is developed indigenously to observe the bright synchrotron light coming from recently installed undulators in Indus-2 storage ring at RRCAT, Indore. The beam viewer is installed in the undulator front-end. The frontend is a long ultra high vacuum (UHV) assembly consisting of UHV valves, shutters, vacuum pumps and beam diagnostic devices. The front-end acts as an interface between Indus-2 ring and beamline. The beam viewer uses a fluorescent sheet of Chromium doped Alumina (CHROMOX) which produces visible fluorescent light when bright synchrotron light from the undulator falls on it. This visible fluorescent light is observed through a glass window by a CCD camera. The beam viewer has been successfully tested and commissioned in Indus-2 front-end for undulator. At present, the beam viewer is operating under vacuum of 5 x 10-10 mbar in the Indus-2 undulator front-end

  2. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  3. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  4. Front-end equipment protection system at the Advanced Photon Source

    International Nuclear Information System (INIS)

    The front-end Equipment Protection System (FE-EPS) at the Advanced Photon Source (APS) is a high reliability, fail-safe single-chain interlock and control system. It consists of an Allen-Bradley PLC-5/30 processor, local and remote I/O racks, monitoring and control panels, serial communication links, and field devices. Each front end is equipped with a dedicated EPS. The system monitors a variety of sensors (e.g., vacuum, cooling water, temperature, pneumatic pressure), and controls front-end (FE) photon shutters and UHV valves. The main functions of the FE-EPS are to guard the integrity of the storage ring vacuum against vacuum excursions in the FE and beam transport line, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. The FE-EPS interfaces to six other APS interlock and control systems. Information about FE interlocks and devices is displayed on UNIX machines using the EPICS software tool kit. The system design is presented. copyright 1996 American Institute of Physics

  5. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...... for solutions. Management is actively involved in this process, in many different ways. Among the implications from this analysis is that the managers' role in the FFE is multifaceted and each controversy seems to require different skills and competencies....

  6. RF photonic front-end integrating with local oscillator loop.

    Science.gov (United States)

    Yu, H; Chen, M; Gao, H; Yang, S; Chen, H; Xie, S

    2014-02-24

    Broadband Radio frequency (RF) photonic front-ends are one of the vital applications of the microwave photonics. A tunable and broadband RF photonic front-end integrating with the optoelectronic oscillator (OEO) based local oscillator has been proposed and experimentally demonstrated, in which only one phase modulator (PM) is employed thanks to the characteristic of the PM. The silicon-on-insulator based narrow-bandwidth band-pass filter is introduced for signal processing. The application condition of the proposed RF photonic front-end has been discussed and the performance of the front-end has also been measured. The SFDR at a frequency of about 7.02 GHz is measured to be 88.6 dB-Hz(2/3). PMID:24663712

  7. Idea management in support of pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

  8. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  9. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  10. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  11. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  12. Node for Front-End Developers

    CERN Document Server

    Means, Garann

    2012-01-01

    If you know how to use JavaScript in the browser, you already have the skills you need to put JavaScript to work on back-end servers with Node. This hands-on book shows you how to use this popular JavaScript platform to create simple server applications, communicate with the client, build dynamic pages, work with data, and tackle other tasks. Although Node has a complete library of developer-contributed modules to automate server-side development, this book will show you how to program with Node on your own, so you truly understand the platform. Discover firsthand how well Node works as a we

  13. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other devices such as representations of users......This paper addresses Front End Innovation as an object for the management and staging of innovation processes. We examine the role which devices play in the managing of Front End Innovation, with inspiration from Science and Technology Studies (STS). The paper contributes to a new understanding...... and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The paper examines...

  14. HINS Linac front end focusing system R&D

    Energy Technology Data Exchange (ETDEWEB)

    Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

    2008-08-01

    This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

  15. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  16. The front-end electronics for LHCb calorimeters

    CERN Document Server

    Beigbeder-Beau, C; Breton, D; Cacéres, T; Callot, O; Cros, P; Delcourt, B; De Vivie de Régie, J B; Falleau, I; Hrisoho, A; Jeanmarie, B; Lefrançois, J; Tocut, V; Truong, K D; Videau, I

    2000-01-01

    The electronics for the electromagnetic and hadronic calorimeters of LHCb is under design. The 32 channel-9U front-end board offers the complete front-end and readout electronics for every channel including original shaping, 12bit-40MHz ADC, digital filtering and latency for level 0 and level 1 triggers. The clipped PM input signal is integrated during 25ns, but also delayed then subtracted to itself 25ns later which allows performant pile up independence. This board also includes the first processing levels of the L0 calorimeter trigger. A 16 channel-6U prototype board has been designed and used at CERN in test beam in 1999.

  17. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  18. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  19. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  20. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  1. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  2. The control system for the CMS tracker front-end

    CERN Document Server

    Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

    2002-01-01

    The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

  3. A Life Cycle Assessment of a Magnesium Automotive Front End

    Energy Technology Data Exchange (ETDEWEB)

    Das, Sujit [ORNL; Dubreuil, Alain [Natural Resources Canada; Bushi, Lindita [GreenhouseGasMeasurement.com; Tharumarajah, Ambalavanar [CSIRO/CAST-CRC

    2009-01-01

    The Magnesium Front End Research and Development (MFERD) project under the sponsorship of Canada, China and USA aims to develop key technologies and a knowledge base for increased use of magnesium in automobile. The goal of this life cycle assessment (LCA) study is to compare the energy and potential environmental impacts of advanced magnesium based front end parts of a North America built 2007 GM-Cadillac CTS with the standard carbon steel based design. This LCA uses the 'cradle-to-grave' approach by including primary material production, semi-fabrication production, autoparts manufacturing and assembly, transportation, use phase and end-of-life processing of autoparts. This LCA study was done in compliance with international standards ISO 14040:2006 and ISO 14044:2006. Furthermore, the LCA results for aluminum based front end autopart are presented. While weight savings result in reductions in energy use and carbon dioxide emissions during the use of the car, the impacts of fabrication and recycling of lightweight materials are substantial in regard to steel. Pathways for improving sustainability of magnesium use in automobiles through material management and technology improvements including recycling are also discussed.

  4. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  5. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  6. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  7. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  8. Broadband RF front-end using microwave photonics filter.

    Science.gov (United States)

    Wang, Jingjing; Chen, Minghua; Liang, Yunhua; Chen, Hongwei; Yang, Sigang; Xie, Shizhong

    2015-01-26

    We propose and demonstrate a novel RF front-end with broadened processing bandwidth, where a tunable microwave photonic filter based on optical frequency comb (OFC) is incorporated to accomplish simultaneous down-conversion and filtering. By designing additional phase shaping and time delay controlling, the frequency tunability of the system could be enhanced. More importantly, the beating interferences generated from broadband RF input could also be suppressed, which help to break the limitation on the processing bandwidth. In our experiments, a photonics RF receiver front-end for RF input with wide bandwidth of almost 20 GHz was realized using 10-GHz-space OFC, where the center frequency of the pass band signals could be tuned continuously. PMID:25835844

  9. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...

  10. Holographic Optical Receiver Front End for Wireless Infrared Indoor Communications

    Science.gov (United States)

    Jivkova, S.; Kavehrad, M.

    2001-06-01

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver s small size, light weight, and low cost make the receiver front end a promising candidate for a user s portable equipment in broadband indoor wireless multimedia access.

  11. The Giga Bit Transceiver based Expandable Front-End (GEFE)—a new radiation tolerant acquisition system for beam instrumentation

    Science.gov (United States)

    Barros Marin, M.; Boccardi, A.; Donat Godichal, C.; Gonzalez, J. L.; Lefevre, T.; Levens, T.; Szuk, B.

    2016-02-01

    The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multi-purpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups.

  12. The Giga Bit Transceiver based Expandable Front-End (GEFE)—a new radiation tolerant acquisition system for beam instrumentation

    International Nuclear Information System (INIS)

    The Giga Bit Transceiver based Expandable Front-End (GEFE) is a multi-purpose FPGA-based radiation tolerant card. It is foreseen to be the new standard FMC carrier for digital front-end applications in the CERN BE-BI group. Its intended use ranges from fast data acquisition systems to slow control installed close to the beamlines, in a radioactive environment exposed to total ionizing doses of up to 750 Gy. This paper introduces the architecture of the GEFE, its features as well as examples of its application in different setups

  13. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  14. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2008-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

  15. Front-end electronics for the FAZIA experiment

    International Nuclear Information System (INIS)

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics

  16. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  17. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  18. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  19. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  20. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  1. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  2. Source-Constrained Recall: Front-End and Back-End Control of Retrieval Quality

    Science.gov (United States)

    Halamish, Vered; Goldsmith, Morris; Jacoby, Larry L.

    2012-01-01

    Research on the strategic regulation of memory accuracy has focused primarily on monitoring and control processes used to edit out incorrect information after it is retrieved (back-end control). Recent studies, however, suggest that rememberers also enhance accuracy by preventing the retrieval of incorrect information in the first place (front-end…

  3. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end process vent or aggregate batch vent stream at an affected source shall submit the information...

  4. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... assumes that the batch unit operation is operating at the maximum design capacity of the EPPU for 12... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process...

  5. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2010-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  6. PMF: The front end electronic of the ALFA detector

    Energy Technology Data Exchange (ETDEWEB)

    Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

    2010-11-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  7. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  8. Software defined radio platform with wideband tunable front end

    Directory of Open Access Journals (Sweden)

    Daniel Iancu

    2015-01-01

    Full Text Available The paper presents a Software Defined Radio (SDR development platform with wideband tunable RF (Radio Frequency front end. The platform is based on the SB3500 Multicore Multithreaded Vector Processor and it is intended to be used for a wide variety of communication protocols as: Time Division Duplexing/Frequency Division Duplexing Long Term Evolution (TDD/FDD LTE, Global Positioning System (GPS, Global System for Mobile/General Packet Radio Service (GSM/GPRS, Wireless Local Area Network (WLAN, Legacy Worldwide Interoperability for Microwave Access (WiMAX. As an example, we describe briefly the implementation of the LTE TDD/FDD communication protocol. As far as we know, this is the only LTE category 1 communication protocol entirely developed and executed in software (SW, without any hardware (HW accelerators.

  9. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  10. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  11. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  12. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  13. Pion Irradiation of the APV25 Front-end Chip

    CERN Document Server

    Friedl, M; Pernicka, Manfred

    2001-01-01

    The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) at CERN will include a Silicon Strip Tracker covering a sensitive area of 206m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25um deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets (SEUs) are inevitable and affect both digital and analog circuits. Eight APV25 chips (version S1) were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

  14. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  15. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  16. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  17. Front End CAMAC Controller for SLAC Control System

    CERN Document Server

    Browne, M J; Siskind, E J

    2001-01-01

    Most of the devices in the SLAC control system are accessed via interface modules in ~450 CAMAC crates. Low-cost controllers in these crates communicate via a SLAC-proprietary bit-serial protocol with 77 satellite control computers ("micros") within the accelerator complex. A proposed upgrade replaces the existing Multibus-I implementation of the micro hardware with commercial-off-the-shelf ("COTS") personal computers. For increased reliability and ease of maintenance, these micros will move from their current electrically noisy and environmentally challenging sites to the control center's computer room, with only a stand-alone portion of each micro's CAMAC interface remaining in the micro's original location. This paper describes the hardware/software architecture of that intelligent front-end CAMAC controller and the accompanying fiber optic link board that connects it to the PC-based micro's PCI bus. Emphasis is placed on the hardware/software techniques employed to minimize real-time latency for pulse-to-...

  18. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  19. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  20. Receiver front end for optical free space communications

    Science.gov (United States)

    Hildebrand, Ulrich

    1994-09-01

    The Receiver Front End (RFE) is the optical receiver of ESA's Semiconductor Laser Intersatellite Link Experiment (SILEX). Optical free space communication between satellites is characterized by narrow beams and therefore by demanding requirements for pointing accuracy. This applies for the steering of the laser beam in transmission, for the pointing of the receiver's field of view (FOV), and for the alignment between transmitted and received beams. The RFE housing, the optical system, the lens and detector's mounting have to be designed to meet the stringent requirements for angular stability. This paper concentrates on the mechanical and thermal aspects which strongly influence the performance. Thermal expansion effects are of major concern when keeping the optical axis stable. All materials have been matched to the thermal expansion characteristics of the hybrid circuit which contains the detector. Assuming only homogeneous temperature changes during life, no stress or angular deviations have to be expected. The relative changes of dimensions in any direction stays equal at different temperatures. The verification of opto-mechanical performance requires sophisticated measurement tools. Measurements have to be performed in order to determine the lateral stability of lens and detector. A dedicated autocollimator was developed which measures the angular stability of the optical axis after vibration, thermo-vacuum test and under temperature changes. It also serves as a test transmitter. Measurement accuracies of 5 (mu) rad have been achieved. For the measurements the RFE is mounted onto a test fixture. A reference mirror on the fixture is the stable reference which has to be more stable than the equipment itself.

  1. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  2. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... pressure drop. (B) If the scrubber is subject to regulations in 40 CFR parts 264 through 266 that have... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... § 63.489 Batch front-end process vents—monitoring equipment. (a) General requirements. Each owner...

  3. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  4. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  5. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  6. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    International Nuclear Information System (INIS)

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

  7. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2014-01-01

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing the consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I.

  8. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  9. A new approach to front-­‐end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Borga, Andrea; The ATLAS collaboration; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Ryu, Soo; Zhang, Jinlong; Anderson, John Thomas; Boterenbrood, Hendrik; Chen, Kai; Chen, Hucheng; Drake, Gary; Donszelmann, Mark; Francis, David

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

  10. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  11. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  12. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  13. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

  14. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  15. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  16. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  17. A NEW MODIFIED TOTAL FRONT END FRAMEWORK FOR INNOVATION: NEW INSIGHTS FROM HEALTH RELATED INDUSTRIES

    OpenAIRE

    PATRICK J. TROTTER

    2011-01-01

    This paper explores the front end innovation activities in a multinational Global Healthcare Company (GHC). A questionnaire was designed and distributed to front end innovators from 20 operating companies to understand team composition, essential skill sets, and the methodology used to assess customer needs, generate ideas, and define the selection criteria used during the go/no go decision. For each category the current state and best practice (based on the views of the individual respondent...

  18. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  19. Front-End Electronics Test System Status Information (After ASDQ++ boards TEST at CERN)

    CERN Document Server

    Nobrega, R; Cernicchiaro, G

    2003-01-01

    A Front-End Electronics Test System (FEET) is being implemented in order to test the Front-end electronics (FEE), in the production line, for the LHCb Muon System. This document discusses some aspects related to the test of ASDQ++ boards. FEET presently enables 5 different tests: Connectivity, Crosstalk, Noise, Sensitivity and Rate-Method tests. The system has detected 25 channels with problems out of 640 tested channels.

  20. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  1. Ember.js front-end framework – SEO challenges and frameworks comparison

    OpenAIRE

    Shrestha, Sunil

    2015-01-01

    IWA Labs Oy, a Finnish company with extensive experience in modern information technology provides professional service in Search Engine Optimization (SEO), online marketing as well as develop mobile and web applications for its clients. In order to provide smooth and better user experience with web applications, the company has adapted front-end dedicated frameworks such as AngularJS, Backbone.js, etc. Therefore, the company is interested in Ember.js– another emerging front-end framework th...

  2. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    International Nuclear Information System (INIS)

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

  3. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  4. The Materials Science beamline upgrade at the Swiss Light Source

    Energy Technology Data Exchange (ETDEWEB)

    Willmott, P. R., E-mail: philip.willmott@psi.ch; Meister, D.; Leake, S. J.; Lange, M.; Bergamaschi, A. [Swiss Light Source, Paul Scherrer Institut, CH-5232 Villigen (Switzerland); and others

    2013-07-16

    The wiggler X-ray source of the Materials Science beamline at the Swiss Light Source has been replaced with a 14 mm-period cryogenically cooled in-vacuum undulator. In order to best exploit the increased brilliance of this new source, the entire front-end and optics have been redesigned. The Materials Science beamline at the Swiss Light Source has been operational since 2001. In late 2010, the original wiggler source was replaced with a novel insertion device, which allows unprecedented access to high photon energies from an undulator installed in a medium-energy storage ring. In order to best exploit the increased brilliance of this new source, the entire front-end and optics had to be redesigned. In this work, the upgrade of the beamline is described in detail. The tone is didactic, from which it is hoped the reader can adapt the concepts and ideas to his or her needs.

  5. Basic design of beamline and polarization control

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The basic concept of synchrotron radiation beamlines for vacuum ultraviolet and X-ray experiments has been introduced to beginning users and designers of beamlines. The beamline defined here is composed of a front end,pre-mirrors, and a monochromator with refocusing mirrors, which are connected by beam pipes, providing monochromatic light for the experiments. Firstly, time characteristics of the synchrotron radiation are briefly reviewed.Secondly, the basic technology is introduced as the fundamental knowledge required to both users and designers. The topics are photoabsorption by air and solids, front ends and beam pipes, mirrors, monochromators, and filters. Thirdly,the design consideration is described mainly for the designers. The topics are design principle, principle of ray tracing,optical machinery and control, and vacuum. Fourthly, polarization control is considered. The topics are polarizers,polarization diagnosis of beamline, and circularly-polarized light generation. Finally, a brief summary is given introducing some references for further knowledge of the users and the designers.

  6. Attenuation of front-end reflections in an impulse radar using high-speed switching

    Science.gov (United States)

    Mazzaro, Gregory J.; Ressler, Marc A.; Smith, Gregory D.

    2011-06-01

    Pulse reflection between front-end components is a common problem for impulse radar systems. Such reflections arise because radio frequency components are rarely impedance-matched over an ultra-wide bandwidth. Any mismatch between components causes a portion of the impulse to reflect within the radar front-end. If the reflection couples into the transmit antenna, the radar emits an unintended, delayed and distorted replica of the intended radar transmission. These undesired transmissions reflect from the radar environment, produce echoes in the radar image, and generate false alarms in the vicinity of actual targets. The proposed solution for eliminating these echoes, without redesigning the transmit antenna, is to dissipate pulse reflections in a matched load before they are emitted. A high-speed switch directs the desired pulse to the antenna and redirects the undesired reflection from the antenna to a matched load. The Synchronous Impulse Reconstruction (SIRE) radar developed by the Army Research Laboratory (ARL) is the case-study. This paper reviews the current front-end design, provides a recent radar image which displays the aforementioned echoes, and describes the switch-cable-load circuit solution for eliminating the echoes. The consequences of inserting each portion of the new hardware into the radar front-end are explained. Measurements on the front-end with the high-speed switch show an attenuation of the undesired pulse transmissions of more than 18 dB and an attenuation in the desired pulse transmission of less than 3 dB.

  7. Prediction and control of front-end curvature in hot finish rolling process

    Directory of Open Access Journals (Sweden)

    Kyunghun Lee

    2015-11-01

    Full Text Available The purpose of this study is to predict the front-end curvature in hot strip finishing mills and to prevent it by controlling the rolling conditions. A theoretical model based on the slab method is developed for predicting the front-end curvature by taking into account the entrance angle of the strip, the friction condition and the back tension. To validate the developed theoretical model, the theoretically obtained curvature value is compared with the results of finite element analysis. Consequently, it is shown that the calculation results of the theoretical model are in good agreement with the measured results of the finite element analysis. Furthermore, a curvature control model based on geometrical and mathematical approaches that can reduce the front-end curvature by the control of the roll speed ratio of the upper to lower rolls is proposed. The proposed curvature control model is verified by finite element analysis, and it is shown that the front-end curvature can be reduced considerably using the proposed model. Therefore, it is concluded that the proposed control model for reducing the front-end curvature in a hot strip finishing mill can be used to improve the quality of the rolled product.

  8. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  9. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Science.gov (United States)

    Feng, Zhou; Ting, Gao; Fei, Lan; Wei, Li; Ning, Li; Junyan, Ren

    2010-11-01

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  10. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  11. Front-end electronics for Micro Pattern Gas Detectors with integrated input protection against discharges

    International Nuclear Information System (INIS)

    One of the major problems that have to be addressed in the design of the front-end electronics for readout of MPGDs, is its resistance to possible random discharges inside active detector volume. This issue becomes particularly critical for the electronics built as ASICs implemented in a modern CMOS technology, for which the breakdown voltages are in the range of a few Volts, while the discharges may result in voltage spikes of even thousands Volts. The paper presents test results of input protection structures integrated with a specific design of the front-end electronics manufactured in the 350 nm CMOS process. The structures were tested using an electrical circuit to mimic discharges in the detectors for different voltage and current parameters of the sparks. Accomplished measurements showed no degradation in the front-end electronics performance even after very excessive discharge tests

  12. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  13. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  14. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi;

    2012-01-01

    for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives......This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

  15. LabVIEW interface with Tango control system for a multi-technique X-ray spectrometry IAEA beamline end-station at Elettra Sincrotrone Trieste

    Science.gov (United States)

    Wrobel, P. M.; Bogovac, M.; Sghaier, H.; Leani, J. J.; Migliori, A.; Padilla-Alvarez, R.; Czyzycki, M.; Osan, J.; Kaiser, R. B.; Karydas, A. G.

    2016-10-01

    A new synchrotron beamline end-station for multipurpose X-ray spectrometry applications has been recently commissioned and it is currently accessible by end-users at the XRF beamline of Elettra Sincrotrone Trieste. The end-station consists of an ultra-high vacuum chamber that includes as main instrument a seven-axis motorized manipulator for sample and detectors positioning, different kinds of X-ray detectors and optical cameras. The beamline end-station allows performing measurements in different X-ray spectrometry techniques such as Microscopic X-Ray Fluorescence analysis (μXRF), Total Reflection X-Ray Fluorescence analysis (TXRF), Grazing Incidence/Exit X-Ray Fluorescence analysis (GI-XRF/GE-XRF), X-Ray Reflectometry (XRR), and X-Ray Absorption Spectroscopy (XAS). A LabVIEW Graphical User Interface (GUI) bound with Tango control system consisted of many custom made software modules is utilized as a user-friendly tool for control of the entire end-station hardware components. The present work describes this advanced Tango and LabVIEW software platform that utilizes in an optimal synergistic manner the merits and functionality of these well-established programming and equipment control tools.

  16. Design of a Direct-conversion Radio Receiver Front-end in CMOS Technology

    OpenAIRE

    Erixon, Mats

    2002-01-01

    In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from severa...

  17. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  18. Design and Optimization of an Analog Front-End for Biomedical Applications

    OpenAIRE

    Razzaghpour, Milad

    2011-01-01

    The state-of-the-art analog front-end of implantable biosensors is the class of current-mirror-based circuits. Despite their superior noise performance, power consumption and area, they suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In the first part of this thesis, a new analog front-end is proposed to eliminate the systematic error. The proposed topology is able to accurately copy the sensor current which will be converted i...

  19. Flexible Analog Front Ends of Reconfigurable Radios Based on Sampling and Reconstruction with Internal Filtering

    Directory of Open Access Journals (Sweden)

    Poberezhskiy Gennady Y

    2005-01-01

    Full Text Available Bandpass sampling, reconstruction, and antialiasing filtering in analog front ends potentially provide the best performance of software defined radios. However, conventional techniques used for these procedures limit reconfigurability and adaptivity of the radios, complicate integrated circuit implementation, and preclude achieving potential performance. Novel sampling and reconstruction techniques with internal filtering eliminate these drawbacks and provide many additional advantages. Several ways to overcome the challenges of practical realization and implementation of these techniques are proposed and analyzed. The impact of sampling and reconstruction with internal filtering on the analog front end architectures and capabilities of software defined radios is discussed.

  20. Implementation of a 66 MHz analog memory as a front end for LHC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Munday, D.J.; Parker, M.A. (Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE (United Kingdom)); Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Gros, J.; Jarron, P.; Heijne, E.H.M.; Meddeler, G.; Pollet, L.; Santiard, J.C.; Verweij, H. (CERN, CH-1211 Geneva 23 (Switzerland)); Goessling, C.; Lisowsky, B. (Institut fuer Physik, Universitaet Dortmund, D-4600 Dortmund (Germany)); Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; La Marra, D.; Wu, X. (DPNC, Geneva University, CH-1211, Geneva 4 (Switzerland)); Moorhead, G. (School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia)); Weidberg, A. (Department of Nuclear Physics, Oxford University, Oxford (United Kingdom)); Campbell, D.; Murray, P.; Seller, P.; Stevens, R. (Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)); Beuville, E.; Rouger, M.; Teiger, J. (Centre d' Etudes Nucleaires de Saclay, F-91191 Gif-sur-Yvette (France))

    1992-02-05

    We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

  1. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  2. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    International Nuclear Information System (INIS)

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities

  3. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken...

  4. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter;

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified...

  5. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  6. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; Van Engelen, Jo; Achterkamp, Madolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to supp

  7. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study aim

  8. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  9. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels;

    2009-01-01

    subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AFE will enable various desired features, as for example the ability to use the front-end with antenna...

  10. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  11. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  12. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  13. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, A.D.

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition o

  14. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh;

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which...

  15. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  16. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  17. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  18. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  19. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  20. Commissioning and operation of the FNAL front end injection line and ion sources

    Science.gov (United States)

    Karns, Patrick R.

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  1. Low power analog readout front-end electronics for time and energy measurements

    International Nuclear Information System (INIS)

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time tp=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC)2 shaper with the peaking time tp=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation Pdiss=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results

  2. Parameters-adjustable front-end controller in digital nuclear measurement system

    International Nuclear Information System (INIS)

    Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (Vin), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

  3. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  4. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2015-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  5. FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

    1989-05-01

    The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.

  6. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2013-01-01

    After two years of operation of the LHC, the ATLAS Tile Calorimeter is undergoing the consolidation process of its front-end electronics. The first layer of certification of the repairs is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I. It is now possible to identify low occurrence errors due to its increased read-out bandwidth and perform more sophisticated quality checks due to its enhanced computing power. Improved results provide fast and reliable feedback to the user.

  7. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  8. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  9. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  10. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    CERN Document Server

    Albrecht, H

    2005-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns within a total of 256 bins. The chip also comprises a pipeline to store data from 128 events which is required for a deadtime-free trigger and data acquisition system. We report on the development, installation, and commissioning of the front-end electronics, including the grounding and noise suppression schemes, and discuss its performance in the HERA-B experiment.

  11. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  12. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  13. Development of a front end controller/heap manager for PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Allen, M.D.; Musrock, M.S.; Walker, J.W.; Britton, C.L. Jr.; Wintenberg, A.L.; Young, G.R.

    1996-12-31

    A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

  14. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  15. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  16. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  17. A MEMS-Based Power-Scalable Hearing Aid Analog Front End.

    Science.gov (United States)

    Deligoz, I; Naqvi, S R; Copani, T; Kiaei, S; Bakkaloglu, B; Sang-Soo Je; Junseok Chae

    2011-06-01

    A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.

  18. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  19. SiPM and front-end electronics development for Cherenkov light detection

    CERN Document Server

    Ambrosi, G; Bissaldi, E; Ferri, A; Giordano, F; Gola, A; Ionica, M; Paoletti, R; Piemonte, C; Paternoster, G; Simone, D; Vagelli, V; Zappala, G; Zorzi, N

    2015-01-01

    The Italian Institute of Nuclear Physics (INFN) is involved in the development of a demonstrator for a SiPM-based camera for the Cherenkov Telescope Array (CTA) experiment, with a pixel size of 6$\\times$6 mm$^2$. The camera houses about two thousands electronics channels and is both light and compact. In this framework, a R&D program for the development of SiPMs suitable for Cherenkov light detection (so called NUV SiPMs) is ongoing. Different photosensors have been produced at Fondazione Bruno Kessler (FBK), with different micro-cell dimensions and fill factors, in different geometrical arrangements. At the same time, INFN is developing front-end electronics based on the waveform sampling technique optimized for the new NUV SiPM. Measurements on 1$\\times$1 mm$^2$, 3$\\times$3 mm$^2$, and 6$\\times$6 mm$^2$ NUV SiPMs coupled to the front-end electronics are presented

  20. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del;

    2015-01-01

    simplifies this by making few fully frequency tunable Tx and Rx chains that each cover multiple bands. Three implementations of antenna systems for the proposed architecture are shown and discussed. They all consist of separate Rx and Tx antennas with more than 25 dB of isolation in between. Combined......This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture...... with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...

  1. Common front end systems for Space Shuttle and Space Station control centers at Johnson Space Center

    Science.gov (United States)

    Uljon, Linda; Muratore, John

    1993-03-01

    In the beginning of the fiscal year 1992, the development organizations of Johnson Space Center (JSC) were poised to begin two major projects: the Space Station Control Center and the refurbishment of the telemetry processing area of the Space Shuttle Mission Control Center. A study team established that a common front end concept could be used and could reduce development costs for both projects. A standard processor was defined to support most of the front end functions of both control centers and supports a consolidation of control positions which effectively reduces operations cost. This paper defines that common concept and describes the progress that has been made in development of the Consolidated Communications Facility (CCF) during the past year.

  2. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  3. General-Purpose Front End for Real-Time Data Processing

    Science.gov (United States)

    James, Mark

    2007-01-01

    FRONTIER is a computer program that functions as a front end for any of a variety of other software of both the artificial intelligence (AI) and conventional data-processing types. As used here, front end signifies interface software needed for acquiring and preprocessing data and making the data available for analysis by the other software. FRONTIER is reusable in that it can be rapidly tailored to any such other software with minimum effort. Each component of FRONTIER is programmable and is executed in an embedded virtual machine. Each component can be reconfigured during execution. The virtual-machine implementation making FRONTIER independent of the type of computing hardware on which it is executed.

  4. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  5. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... are: • What are the objectives of measurement in radical design? and • What are the most crucial future challenges related with the selection of the relevant measurement objectives? Based on the theoretical part of this paper, our framework of the Balanced Design Front-End Model (BDFEM) for measuring...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

  6. Topology investigation of front end DC/DC converter for distributed power system

    OpenAIRE

    Yang, Bo

    2003-01-01

    Topology Investigation of Front End DC/DC Power Conversion for Distributed Power System by Bo Yang Fred C. Lee, Chairman Electrical Engineering (Abstract) With the fast advance in VLSI technology, smaller, more powerful digital system is available. It requires power supply with higher power density, lower profile and higher efficiency. PWM topologies have been widely used for this application. Unfortunately, hold up time requirement put huge penalties on the performance o...

  7. Modification of a Tractor Dynamic Model Considering the Rotatable Front End

    OpenAIRE

    Li, Zhen; Mitsuoka, Muneshi; Inoue, Eiji; OKAYASU, Takashi; Hirai, Yasumaru; Zhu, Zhongxiang

    2015-01-01

    A mathematical model for tractor dynamics was expanded by considering the rotatable tractor front end. The fundamental shortcoming of the simplified model was revealed by the loss of contact of the tire with a rigid horizontal surface in an obstacle–passing case. Further shortcom–ings of the simplified model arise from aspects of the motion and vibration characteristics. The improved model provides a better and more realistic representation of the tire–ground contact condition and is applicab...

  8. A Low-noise front-end circuit for 2D cMUT arrays

    OpenAIRE

    Güler, Ülkühan; Guler, Ulkuhan; Bozkurt, Ayhan

    2006-01-01

    cMUT technology enables 2D array design with front-end electronic integration through flip-chip bonding or cMUT-on-CMOS process. The size of a 2D array element is constrained in both dimensions due to the aperture sampling criteria, and therefore should be less than or equal to the half of the wavelength in both dimensions. Considering large parasitic capacitances introduced by the interconnections, such small transducer elements necessitate integrated low noise frontends for achieving accept...

  9. A front-end automation tool supporting design, verification and reuse of SOC

    Institute of Scientific and Technical Information of China (English)

    严晓浪; 余龙理; 王界兵

    2004-01-01

    This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

  10. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    OpenAIRE

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels; Krozer, Viktor

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AF...

  11. Advances in Digital Front-End and Software RF Processing: Part II

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    In the first editorial of this two-part special issue, we pointed out that one of the biggest trends in wireless broadband, radar, sonar, and broadcasting technology is software RF processing and digital front-end [1]. Thistrend encompasses signal processing algorithms and integrated circuit design and includes digital pre-distortion (DPD), conversions between digital and analog signals, digita up-conversion (DUC), digital down-conversion (DDC), DC offset,

  12. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

    2011-02-15

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  13. A CLIMATE OF PSYCHOLOGICAL SAFETY ENHANCES THE SUCCESS OF FRONT END TEAMS

    OpenAIRE

    ANN-MARIE I. NIENABER; VERENA HOLTORF; JENS LEKER; GERHARD SCHEWE

    2015-01-01

    This paper contributes to the discussion about initiative in teams at the front end of new product development processes (innovative teams). In contrast to the general opinion presented in the literature, this study points out that unstructured innovative teams are as much initiative in developing new ideas or in finding quick solutions when compared to structured innovative teams. Therefore we analyse the relationship between teamwork quality and team initiative in structured and unstructure...

  14. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology. PMID:25330494

  15. Status of the Control Sytem for the Front-End of the Spallation Neutron Source

    CERN Document Server

    Lewis, S A; Cull, P T

    2001-01-01

    The Spallation Neutron Source (SNS) is a partnership between six laboratories. To ensure a truly integrated control system, many standards have been agreed upon, including the use of EPICS as the basic toolkit. However, unique within the partnership is the requirement for Lawrence Berkeley National Lab, responsible for constructing the Front End, to operate it locally before shipping it to the Oak Ridge National Lab (ORNL) site. Thus, its control system must be finished in 2001, well before the SNS completion date of 2006. Consequently many decisions regarding interface hardware, operator screen layout, equipment types, and so forth had to be made before the other five partners had completed their designs. In some cases the Front-End has defined a standard by default; in others an upgrade to a new standard is anticipated by ORNL later. Nearly all Front-End devices have been commissioned with the EPICS control system. Of the approximately 1500 signals required, about 60% are now under daily operational use. Th...

  16. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  17. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  18. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    International Nuclear Information System (INIS)

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  20. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  1. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  2. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  3. 45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

    Science.gov (United States)

    Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

    2012-07-30

    In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W. PMID:23038384

  4. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  5. Implementing method of optimum front-end conditioner based on Butterworth filter

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The front-end conditioner is an essential part of digital systems of nuclear spectrometer, which functions in two ways: (1) prevents saturation of the subsequent ADC; (2) limits the bandwidth of frequency to realize anti-aliasing. To realize the above-mentioned functions, an optimum front-end conditioner for a resistive feedback charge-sensitive preamplifier is designed. In the conditioner, the pole-zero compensation (P/Z compensation) technique was used to effectively filter signals from the preamplifier. The Butterworth filter was improved after the pole-zero position was optimally set up to shape the wave of output, which tallied with the whole system. The front-end conditioner can resolve the aberration of waveform of nuclear signals in a regular Butterworth filter. Compared with the traditional triple-pole filtering circuitry, the circuitry of this conditioner is more compact and flexible.Moreover, its output waveform is more symmetrical and the signal-to-noise ratio (SNR) is higher. The improvement in the resolution of spectrometer is also significant.

  6. Front End Design of a Multi-GeV H-minus Linac

    CERN Document Server

    Ostroumov, Peter; Romanov, Gennady; Shepard, Kenneth; William Foster, G

    2005-01-01

    The proposed 8-GeV driver at FNAL is based on ~480 independently phased SC resonators. Significant cost saving is expected by using an rf power fan out from high-power klystrons to multiple cavities. Successful development of superconducting (SC) multi-spoke resonators operating at ~345-350 MHz provides a strong basis for their application in the front end of multi-GeV linear accelerators. Such a front-end operating at 325 MHz would enable direct transition to high-gradient 1300 MHz SC TESLA-style cavities at ~400 MeV. The proposed front end consists of 5 sections: a conventional RFQ, room-temperature (RT) cross-bar H-type (CH) cavities, single-, double- and triple-spoke superconducting resonators. For several reasons which are discussed in this paper there is a large advantage in using independently phased RT CH-cavities between the RFQ and SC sections in the energy range 3-15 MeV.

  7. FBI Fingerprint Image Capture System High-Speed-Front-End throughput modeling

    Energy Technology Data Exchange (ETDEWEB)

    Rathke, P.M.

    1993-09-01

    The Federal Bureau of Investigation (FBI) has undertaken a major modernization effort called the Integrated Automated Fingerprint Identification System (IAFISS). This system will provide centralized identification services using automated fingerprint, subject descriptor, mugshot, and document processing. A high-speed Fingerprint Image Capture System (FICS) is under development as part of the IAFIS program. The FICS will capture digital and microfilm images of FBI fingerprint cards for input into a central database. One FICS design supports two front-end scanning subsystems, known as the High-Speed-Front-End (HSFE) and Low-Speed-Front-End, to supply image data to a common data processing subsystem. The production rate of the HSFE is critical to meeting the FBI`s fingerprint card processing schedule. A model of the HSFE has been developed to help identify the issues driving the production rate, assist in the development of component specifications, and guide the evolution of an operations plan. A description of the model development is given, the assumptions are presented, and some HSFE throughput analysis is performed.

  8. All Fiber Technology for High-Energy Petawatt Front End Laser Systems

    Energy Technology Data Exchange (ETDEWEB)

    Dawson, J W; Liao, Z M; Jovanovic, I; Wattellier, B; Beach, R; Payne, S A; Barty, C P J

    2003-09-05

    We are developing an all fiber front end for the next generation high-energy petawatt (HEPW) laser at Lawrence Livermore National Laboratory (LLNL). The ultimate goal of the LLNL HEPW effort is to generate 5-kJ pulses capable of compression to 5ps at 1053nm, enabling advanced x-ray backlighters and possible demonstration of fast ignition. We discuss the front-end of the laser design from the fiber master oscillator, which generates the mode-locked 20nm bandwidth initial pulses through the 10mJ output of the large flattened mode (LFM) fiber amplifier. Development of an all fiber front end requires technological breakthroughs in the key areas of the master oscillator and fiber amplification. Chirped pulse amplification in optical fibers has been demonstrated to 1mJ. Further increase is limited by the onset of stimulated Raman scattering (SRS). We have recently demonstrated a new flattened mode fiber technology, which reduces peak power for a given energy and thus the onset of SRS. Controlled experiments with 1st generation fibers yielded 0.5mJ of energy while significantly increasing the point at which nonlinear optical effects degrade the amplified pulse. In this paper we will discuss our efforts to extend this work to greater than 20mJ using our large flattened mode fiber amplifier.

  9. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    Institute of Scientific and Technical Information of China (English)

    Mehmood A wan; Yannick Le Moullec; Peter Koch; Fred Harris

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filterbank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resamp/ing in SDR front-ends. These modes are (i) maximally decimated, (ii) Under-decimated, (iii) over-decimated, and combined up- and down-sampling with (iv) single stride length, and (v) multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

  10. New Order, end of illusions and the activist matrix of the first National Front

    Directory of Open Access Journals (Sweden)

    Nicolas LEBOURG

    2013-05-01

    Full Text Available Ordre nouveau was the most important French neo-fascist movement after 1945. It lasted only for four years (1969-1973 but it induced seve-ral changes shaking the radical right wing. As it was defined as a revolutionary party, ordre nouveau spread its identity onto activists on the one hand, while it also collaborated with state authorities fighting against leftists on the other hand. Following the successful italian model of the MSI, the movement oscillated between media coverage — which gave it an identity but also led to its dissolution in 1973 — and acceptance of the electoral game for which Front national had been founded. The disappearance of ordre nouveau meant the end of dreams of revolutionary right sustained by some active minorities using political violence, as well as it stood for a transition to a post-industrial radical right symbolized by the rise of Front National.

  11. Understanding the Front-end of Large-scale Engineering Programs

    DEFF Research Database (Denmark)

    Lucae, Sebastian; Rebentisch, Eric; Oehmen, Josef

    2014-01-01

    Large engineering programs like sociotechnical infrastructure constructions of airports, plant constructions, or the development of radically innovative, high-tech industrial products such as electric vehicles or aircraft are affected by a number of serious risks, and subsequently commonly suffer......, unclear and incomplete requirements, unclear roles and responsibilities within the program organization, insufficient planning, and unproductive tensions between program management and systems engineering. This study intends to clarify the importance of up-front planning to improve program performance......, to propose a model for the front-end of large-scale engineering programs based on a review of existing, suitable models in literature and to better understand the complexity drivers that are impeding reliable planning and common planning mistakes made in large-scale engineering programs....

  12. Front- and back-end process characterization by SIMS to achieve electrically matched devices

    Science.gov (United States)

    Budri, Thanas; Kouzminov, Dimitry

    2004-06-01

    Application of SIMS metrology in high volume wafer manufacturing allows comparison of important physical characteristics of devices and can address changes in the process during early stages of process flow, thus improving production yields and cycles. In the current paper, we investigate the correlation between wafer-level SIMS characterization and electrical characteristics of devices in a wide spectrum of front- and back-end applications: high precision SIMS analysis for implanter recipe development and monitoring is a technique that has provided major contributions to achieve electrically matched devices. SIMS analysis is also used widely on gate material selection and characterization. As SiGe/SiGeC is taking precedence over III-V materials for rf applications due to processing simplicity, SIMS analytical technique provides major metrology support on process targeting and development. The SIMS analytical technique has earned its reputation and is wide used as metrology solution on front-end semiconductor processing. Fluorine SIMS analysis investigation in TiN, W and its relation with increased via resistance and voids on the nucleation is an example of SIMS analysis application for back-end process support.

  13. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  14. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  15. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  16. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    International Nuclear Information System (INIS)

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2. (paper)

  17. High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

    Science.gov (United States)

    Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

    2010-01-01

    In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

  18. A front-end readout Detector Board for the OpenPET electronics system

    OpenAIRE

    Choong, W. -S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C.Q.; Wu, J.-Y.

    2015-01-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, an...

  19. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  20. Front-End Electronics for the Dark Energy Survey Camera (DECam)

    Science.gov (United States)

    Shaw, Theresa M.; Huffman, D.; Kozlovsky, M.; Olsen, J.; Stuermer, W.; Barcelo, M.; Cardiel, L.; Castilla, J.; DeVicente, J.; Martinez, G.; Moore, P.; Schmidt, R.

    2006-12-01

    The front-end electronics design for the Dark Energy Survey Camera (DECam) is based on the MONSOON Image Acquisition System that was developed by the National Optical Astronomy Observatory (NOAO). MONSOON systems are currently being used to test and characterize CCDs. The Dark Energy Survey group both in the U.S. and Spain will produce custom versions of these systems for use in the production readout that will better match the requirements of a large focal plane of 70+ CCDs and the tight space constraints of a prime focus instrument. The customization of the MONSOON boards and the electronics path will be presented.

  1. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  2. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    OpenAIRE

    Valente, V.; Demosthenous, A.

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) ...

  3. THz semiconductor-based front-end receiver technology for space applications

    Science.gov (United States)

    Mehdi, Imran; Siegel, Peter

    2004-01-01

    Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

  4. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  5. Balancing research and organizational capacity building in front-end project design

    DEFF Research Database (Denmark)

    Hjortsø, Carsten Nico Portefée; Meilby, Henrik

    2013-01-01

    phase of RCB partnerships and examine how they influence the balance between performing collaborative research and developing general organizational capacity. Data collection was based on a survey (n = 25), and individual interviews and focus group discussions with 17 Danish project managers from...... is more complex. We identify 11 specific factors influencing front-end project management related to structure, process and relationship, and we theorize about how these factors influence the choice between research and more general capacity development activities. Copyright © 2013 John Wiley & Sons, Ltd...

  6. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    Product-service systems (PSS) adoption has increased over the last years due to its potential for innovative value creation. However, the identification of ideas and opportunities in the innovation planning and the structuring of PSS projects are still incipient in organizations, following the same...... be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  7. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions. PMID:20192390

  8. Design of an Ultra-Low Noise Analogue Front-End for Fast Voltage Pulses Measurement

    CERN Document Server

    AUTHOR|(SzGeCERN)712364; Arpaia, Pasquale; Cerqueira Bastos, Miguel; Martino, Michele

    2015-01-01

    A 15MS/s, 10 ppm repeatable acquisition system to characterize 3 μs rise-time trapezoidal voltage pulses is proposed. The system is based mainly on a low-noise, 5MHz bandwidth analog front-end. In this paper, the requirements, the concept and physical design are illustrated. Simulation results aimed at assessing the circuit performance are presented. An experimental case study on the characterization of a pulsed power supply for the klystrons modulators of the Compact Linear Collider (CLIC) under study at CERN is reported. In particular, the experimental metrological characterization of the prototype in terms of bandwidth and noise is presented.

  9. SYSTEMATIC METHOD TO GENERATE NEW IDEAS IN FUZZY FRONT END USING TRIZ

    Institute of Scientific and Technical Information of China (English)

    TAN Runhua; MA Lihui; YANG Bojun; SUN Jianguang

    2008-01-01

    The obstacle for idea generation in fuzzy front end (FFE) is difficult to apply knowledge in different fields for designers. Theory of inventive problem solving TRIZ and computer-aided innovation systems (CAIs) which are TRIZ-base software systems with a knowledge base provide a framework for knowledge application in different fields. The major methods in TRIZ are selected, which have four types. The problems to be solved for each method are summarized and mapping from the problems to the methods is given. Systematic method with eight paths to integrate the methods and problems is formed. A case study shows the idea generation in FFE using the integrated method step by step.

  10. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  11. Computer Aided Design of Microwave Front-End Components and Antennas for Ultrawideband Systems

    Science.gov (United States)

    Almalkawi, Mohammad J.

    This dissertation contributes to the development of novel designs, and implementation techniques for microwave front-end components and packaging employing both transmission line theory and classical circuit theory. For compact realization, all the presented components have been implemented using planar microstrip technology. Recently, there has been an increase in the demand for compact microwave front-ends which exhibit advanced functions. Under this trend, the development of multiband front-end components such as antennas with multiple band-notches, dual-band microwave filters, and high-Q reconfigurable filters play a pivotal role for more convenient and compact products. Therefore, the content of this dissertation is composed of three parts. The first part focuses on packaging as an essential process in RF/microwave integration that is used to mitigate unwanted radiations or crosstalk due to the connection traces. In printed circuit board (PCB) interconnects, crosstalk reduction has been achieved by adding a guard trace with/without vias or stitching capacitors that control the coupling between the traces. In this research, a new signal trace configuration to reduce crosstalk without adding additional components or guard traces is introduced. The second part of this dissertation considers the inherent challenges in the design of multiple-band notched ultrawideband antennas that include the integration of multilayer antennas with RF front-ends and the realization of compact size antennas. In this work, a compact UWB antenna with quad band-notched frequency characteristics was designed, fabricated, and tested demonstrating the desired performance. The third part discusses the design of single- and dual-band dual-mode filters exhibiting both symmetric and asymmetric transfer characteristics. In dual-mode filters, the numbers of resonators that determine the order of a filter are reduced by half while maintaining the performance of the actual filter order. Here, in

  12. How can HR practices support front-end innovation and increase the innovativeness of companies?

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Andersen, Torben

    2014-01-01

    This theoretical review is investigating how selected HR practices can help overcome the challenges companies face in establishing a basis for continuous innovation and thereby economic performance. In particular, the front end of innovation is being emphasised as a key element in companies......' innovativeness. If HR is to support these activities, focus should be on broader issues such as team-based organising, founded on a questioning attitude and a management style with a high level of empowerment. In addition, traditional HR themes such as recruitment, training and development have...

  13. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  14. Policy, price formation, and the front end. A market-clearing model

    International Nuclear Information System (INIS)

    Demand for low enriched uranium (LEU) is met by an evolving combination of primary and secondary uranium sources and enrichment services. A market-clearing model to depict the time evolution of trade-offs between these industries under various policy and LEU demand scenarios is presented. By fixing short-run LEU demand, the model solves for the consumption of primary and secondary uranium and separative work units (SWUs) that minimizes overall front-end costs. Assuming frictionless markets at equilibrium, it projects cost minimizing tails U-235 enrichment, SWU and primary uranium prices over the next two decades by identifying producing and price-setting mines and enrichment facilities. (author)

  15. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  16. An analog bipolar-JFET master slice array for front-end electronics design

    International Nuclear Information System (INIS)

    An analog bipolar-JFET Master Slice Array (MSA) has been designed for implementation of ICs used in nuclear physics front-end electronics. The universal conception of MSAs active and passive elements provides great functional complexity to ICs in using them. The quality of active element parameters, number and values of available resistors and capacitors made it possible to integrate a four channel amplifier-shaper-discriminator with a base line restorer into the MSA die with dimensions 2.7 mmx3.6 mm. Eight-channel ICs can be made by connection of two chips by metal wiring on a wafer

  17. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  18. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  19. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    International Nuclear Information System (INIS)

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented

  20. Management control systems as a tool to rationalize the intelligence gathering in the front end of innovation

    OpenAIRE

    Toivakka, Satu

    2016-01-01

    The objective of this study is to investigate how management control systems (MCS) are applied in the front end of innovation. Firstly, the focus will be to understand what kind of management controls, if any, are used in the front-end phase of innovation. Secondly, this study will clarify how these controls facilitate the intelligence gathering and the mobilization of the tacit knowledge that then leads to ideas and further to incremental innovations. The literature review explores the ...

  1. Modeling, simulation, and optimization of a front-end system for acetylene hydrogenation reactors

    Directory of Open Access Journals (Sweden)

    Gobbo R.

    2004-01-01

    Full Text Available The modeling, simulation, and dynamic optimization of an industrial reaction system for acetylene hydrogenation are discussed in the present work. The process consists of three adiabatic fixed-bed reactors, in series, with interstage cooling. These reactors are located after the compression and the caustic scrubbing sections of an ethylene plant, characterizing a front-end system; in contrast to the tail-end system where the reactors are placed after the de-ethanizer unit. The acetylene conversion and selectivity profiles for the reactors are optimized, taking into account catalyst deactivation and process constraints. A dynamic optimal temperature profile that maximizes ethylene production and meets product specifications is obtained by controlling the feed and intercoolers temperatures. An industrial acetylene hydrogenation system is used to provide the necessary data to adjust kinetics and transport parameters and to validate the approach.

  2. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  3. Multi-channel front-end board for SiPM readout

    Science.gov (United States)

    Auger, M.; Ereditato, A.; Goeldi, D.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Weber, M. S.

    2016-10-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias for the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The signal-to-noise ratio of 12 is attained for the first photo-electron peak. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  4. Indus-2 beamline personal safety interlocks system

    International Nuclear Information System (INIS)

    Indus-2 is a 2.5 GeV, 300 mA synchrotron radiation source and is currently operating at 2 GeV and 100 mA in the round the clock shift. Two sources of ionizing radiation at Indus-2 can pose a hazard if not properly dealt with are, Bremsstrahlung radiation and synchrotron radiation. The former is mostly generated from collision of electrons with gas molecules and consists of very high energy radiation. A hutch is a structure that houses the beamline and other experimental equipment /apparatus, which is designed to prevent personnel access to areas where there is a potential for the synchrotron beam to generate high levels of ionizing radiation. Hutches are designed to reduce the direct and scattered beam dose rates to acceptably low levels outside. Personal Safety Interlock System (PSIS) is introduced to protect people from accidental exposure to high radiation when the beamlines are in use. PSIS ensures that (1) synchrotron radiation can be allowed to enter an experimental hutch only when no one is present in the hutch and all the doors of the hutch are properly closed; (2) in case of a person entering a hutch during operation, the radiation is stopped by closing the safety shutter and (3) when radiation level in the occupied area near the beamline exceeds the permissible level, it is brought down by closing the safety shutter. The PSIS system is linked with main front-end control system of each beamline. PSIS system consist of relay modules, timers, search and scram buttons, status display panels, door limit switches with latching mechanism and audio-visual alarms. This paper describes, in detail, the design and interlock scheme of a fail-safe and reliable Personal Safety Interlock System implemented at Indus-2 beamlines. (author)

  5. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  6. CPRF/ZTH front-end torus design and fabrication status

    International Nuclear Information System (INIS)

    Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

  7. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  8. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  9. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  10. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  11. Towards a smart Holter system with high performance analogue front-end and enhanced digital processing.

    Science.gov (United States)

    Du, Leilei; Yan, Yan; Wu, Wenxian; Mei, Qiujun; Luo, Yu; Li, Yang; Wang, Lei

    2013-01-01

    Multiple-lead dynamic ECG recorders (Holter) play an important role in the earlier detection of various cardiovascular diseases. In this paper, we present the first several steps towards a 12-lead Holter system with high-performance AFE (Analogue Front-End) and enhanced digital processing. The system incorporates an analogue front-end chip (ADS1298 from TI), which has not yet been widely used in most commercial Holter products. A highly-efficient data management module was designated to handle the data exchange between the ADS1298 and the microprocessor (STM32L151 from ST electronics). Furthermore, the system employs a Field Programmable Gate Array (Spartan-3E from Xilinx) module, on which a dedicated real-time 227-step FIR filter was executed to improve the overall filtering performance, since the ADS1298 has no high-pass filtering capability and only allows limited low-pass filtering. The Spartan-3E FPGA is also capable of offering further on-board computational ability for a smarter Holter. The results indicate that all functional blocks work as intended. In the future, we will conduct clinical trials and compare our system with other state-of-the-arts.

  12. Status report on front end electronics for the EUSO photon detector

    Energy Technology Data Exchange (ETDEWEB)

    Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P

    2002-12-01

    In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

  13. BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

    International Nuclear Information System (INIS)

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

  14. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    International Nuclear Information System (INIS)

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

  15. Implementation of re-configurable Digital front end module of MIMO-OFDM module using NCO

    Directory of Open Access Journals (Sweden)

    Veena M.B.

    2011-09-01

    Full Text Available This paper focuses on FPGA implementation of Reconfigurable Digital Front end MIMO-OFDM module. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. Unlike the conventional OFDM based systems, the Numerically Controlled Oscillators (NCO is used for mapping modulated data onto the sub carriers. The use of NCO in the MIMO-OFDM system reduces the resource utilization of the design on FPGA along with reduced power consumption. The major modules that were designed, which constitute the digital front end module, are Quadrature Phase Shift Keying (QPSK modulator/demodulator, 16-Quadrature Amplitude Modulation (QAM modulator/demodulator and NCOs. Each of the modules was tested for their functionality by developing corresponding test benches. In order to achieve real time reconfigurability of the proposed architecture, the proposed approach is realized on FPGAs optimizing area, power and speed. Reconfigurability of the proposed approach is dependent upon user requirement. Hence the proposed approach can support future generation communication technologies that are based on MIMO-OFDM.

  16. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  17. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  18. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0–30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  19. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  20. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  1. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  2. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C. J.; Müller, W. F. J.

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  3. An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

    Institute of Scientific and Technical Information of China (English)

    WANG Min; ZHANG Xiao; ZHANG Chun-feng; CAO Mao-yong; LI Cai-fang; KONG Hui-min; QIN Feng-ju; YAN Yu-qin

    2007-01-01

    Abstract.Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here,a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end ( AFE), while a computer ( Pentium Ⅲ ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

  4. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  5. FEC-CCS A common Front-End Controller card for the CMS detector electronics

    CERN Document Server

    Kloukinas, Kostas; Drouhin, F; Ljuslin, C; Marchioro, A; Murer, E; Paillard, C; Vlasov, E

    2007-01-01

    The FEC-CCS is a custom made 9U VME64x card for the CMS Off-Detector electronics. The FEC-CCS card is responsible for distributing the fast timing signals and the slow control data, through optical links, to the Front-End system. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS detectors namely the Tracker, ECAL, Preshower, PIXELs, RPCs and TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enable the common utilization by most of the CMS detectors. Results from the integration tests with the detector electronics subsystems and performance measurements will be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.

  6. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  7. The NA62 LAV front-end electronics and the L0 trigger generating firmware

    CERN Document Server

    Gonnella, Francesco; Corradi, Giovanni; Kozhuharov , Venelin ; Martellotti, Silvia; Moulson, Matthew; Raggi, Mauro; Spadaro, Tommaso

    2014-01-01

    The aim of the NA62 experiment is to measure the branching ratio of the decay K + ! p + n ̄ n to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from p + p 0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is 100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed.

  8. Front-End-Electronics Communication software for multiple detectors in the ALICE experiment

    CERN Document Server

    Bablok, Sebastian; Hartung, G; Keidel, R; Kofler, C; Krawutschke, T; Lindenstruth, V; Röhrich, D

    2006-01-01

    In the ALICE experiment at CERN, the Detector Control System (DCS) employs several interacting software components to accomplish its task of ensuring the correct operation and monitoring of the experiment. This paper describes the Front-End-Electronics Communication (FeeCommunication) software and its role within the DCS. The FeeCommunication software's central task is passing configuration and monitoring data between the top level DCS process control and the field devices of several detectors within ALICE. The lowest level of the FeeCommunication software runs on the DCS boards, specialized embedded systems which are in direct contact with the field devices and are physically located within the detector. The middle and upper layers run on standard PC hardware located in the counting room or other external locations. This paper focuses on the design and implementation of the FeeCommunication software and the steps that were taken to fulfill the imposed reliability and performance requirements, specifically th...

  9. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  10. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  11. A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

    Directory of Open Access Journals (Sweden)

    Eric Bharucha

    2014-11-01

    Full Text Available When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

  12. Front-end signal analysis of the transverse feedback system for SSRF

    Institute of Scientific and Technical Information of China (English)

    HAN Lifeng; YUAN Renxian; YU Luyang; YE Kairong

    2008-01-01

    Multi-bunch instabilities degrade beam quality through increased beam emittance, energy spread and even cause beam loss. A feedback system is used to suppress multi-bunch instabilities associated with resistive wall of the beam ducts, cavity-like structures, and trapped ions. A digital TFS (Transverse Feedback System) is in construction at the SSRF (Shanghai Synchrotron Radiation Facility), which is based on the latest generation of FPGA (Field Programmable Gate Array) processor. Before we get such FPGA digital board, investigation and simulation of the front-end were done in the first place. The signal flow was analyzed by SystemView. Construction and optimization of the entire system is our next goal.

  13. Indus-2 beam line front end controls using real time operating system

    International Nuclear Information System (INIS)

    Beam Line Front Ends (BLFE) are crucial interfaces between machine user beam lines and INDUS-2 synchrotron radiation source. Twenty-seven beam lines are proposed in INDUS-2 synchrotron facility out of which some are operational by now and many more are about to come. The purpose of these BLFE's is essentially to protect the machine vacuum from beam line failures and vice versa and allow a well co-ordinated and safe usage of machine by its users. For controlling these beam lines, BLFE control system is implemented. The BLFE control system is based on three-layer architecture with equipments connected ate the layer three, Layer two serves the purpose of metadata storage, layer one serves as operator console (GUI). This paper discusses the scheme and architecture of layer two and layer three implementation using RTOS OS-9. The diagnostic features incorporated in the architecture increases the system uptime by quick diagnosis of system faults. (author)

  14. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Acqua, A.; Hansen, M.; Lofstedt, B.; Vanuxem, J.P. (CERN, Geneva (Switzerland)); Svensson, C.; Yuan, J. (Univ. of Linkoeping (Sweden). Dept. of Physics and Measurement Technology); Hentzell, H. (Univ. of Linkoeping (Sweden). Center for Industrial Microelectronics and Materials Technology); Alippi, C.; Breveglieri, L.; Dadda, L.; Piuri, V.; Salice, F.; Sami, M.; Stefanelli, R. (Sezione INFN, Pavia, Milano (Italy). Dept. di Ellettronica); Cattaneo, P.; Fumagalli, G.; Goggi, V.G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Fisica Nucleare); Brigati, S.; Gatti, U.; Maloberti, F.; Torelli, G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Electronica); Carlson, P.; Fuglesang, C.; Kerek, A. (Manne Siegbahn Inst. of Physics, Stockholm (Sweden)); Appelquist, G.; Berglund, S.; Bohm, C.; Yamdagni, N. (Univ. of Stockholm (Sweden)); Sundblad, R. (SiCon AB, Linkoeping (Sweden))

    1993-08-01

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.

  15. Performance of the front-end electronics of the ANTARES neutrino telescope

    International Nuclear Information System (INIS)

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  16. Performance of the front-end electronics of the ANTARES neutrino telescope

    Energy Technology Data Exchange (ETDEWEB)

    Aguilar, J.A. [IFIC - Instituto de Fisica Corpuscular, Edificios Investigacion de Paterna, CSIC - Universitat de Valencia, Apdo. de Correos 22085, 46071 Valencia (Spain); Al Samarai, I. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Albert, A. [GRPHE - Institut universitaire de technologie de Colmar, 34 rue du Grillenbreit BP 50568 - 68008 Colmar (France); Anghinolfi, M. [INFN - Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); Anton, G. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Anvar, S. [Direction des Sciences de la Matiere - Institut de recherche sur les lois fondamentales de l' Univers - Service d' Electronique des Detecteurs et d' Informatique, CEA Saclay, 91191 Gif-sur-Yvette Cedex (France); Ardid, M. [Institut d' Investigacio per a la Gestio Integrada de Zones Costaneres (IGIC) - Universitat Politecnica de Valencia. C/ Paranimf, 1. E-46730 Gandia (Spain); Assis Jesus, A.C.; Astraatmadja, T. [FOM Instituut voor Subatomaire Fysica Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Aubert, J.-J. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Auer, R. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Baret, B. [APC - Laboratoire AstroParticule et Cosmologie, UMR 7164 (CNRS, Universite Paris 7 Diderot, CEA, Observatoire de Paris) 10, rue Alice Domon et Leonie Duquet 75205 Paris Cedex 13 (France); Basa, S. [LAM - Laboratoire d' Astrophysique de Marseille, Pole de l' Etoile Site de Ch-Gombert, rue Frederic Joliot-Curie 38, 13388 Marseille cedex 13 (France)

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  17. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  18. Harmonic Mitigated Front End Three Level Diode Clamped High Frequency Link Inverter by Using MCI Technique

    Directory of Open Access Journals (Sweden)

    Sreedhar Madichetty

    2014-02-01

    Full Text Available In this paper it proposes a high efficient soft-switching scheme based on zero-voltage-switching (ZVS and zero-current-switching(ZCS principle operated with a simple auxiliary circuit extended range for the front-end isolated DC-AC-DC-AC high power converter with an three phase three level diode clamped multi level inverter by using Minority Charge Carrier inspired optimization technique (MCI with Total Harmonic Distortion(THD,Switching losses, Selective harmonic elimination maintaining with its fundamental as an objective function. Input to the inverter is obtained by the photo voltaic cells and with battery bank. The switching scheme is optimized by MCI technique, analyzed and executed in Matlab and implemented with a digital signal processor (DSP .Experimental results with different loads have observed and shows its effectives, robustness of the applied technique.

  19. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  20. Cognitive radio receiver front-ends RF/analog circuit techniques

    CERN Document Server

    Sadhu, Bodhisatwa

    2014-01-01

    This book focuses on the architecture and circuit design for cognitive radio receiver front-ends.  The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.   • Discusses in detail the circuit-level challenges that exist for cognitive radio systems; • Provides readers with a holistic understanding of RF circuits for cognitive radio systems; • Enables communications engineers and systems designers to design better cognitive radio architectures and communication protocols.

  1. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    CERN Document Server

    Impiombato, D; Mineo, T; Catalano, O; Gargano, C; La Rosa, G; Russo, F; Sottile, G; Billotta, S; Bonanno, G; Garozzo, S; Grillo, A; Marano, D; Romeo, G

    2015-01-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  2. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    Energy Technology Data Exchange (ETDEWEB)

    Impiombato, D., E-mail: Domenico.Impiombato@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Giarrusso, S., E-mail: Giarrusso@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Mineo, T., E-mail: Mineo@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Catalano, O., E-mail: Catalano@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy)

    2015-09-11

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  3. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    Science.gov (United States)

    Impiombato, D.; Giarrusso, S.; Mineo, T.; Catalano, O.; Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G.; Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G.

    2015-09-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  4. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  5. Study of the performance of ATLAS prototype detectors using analogue LHC front-end electronics

    CERN Document Server

    Riedler, P; Kaplon, J; Weilhammer, Peter

    2002-01-01

    The silicon strip detectors in the ATLAS experiment at LHC will be exposed to very high hadron fluences. In order to study the radiation damage effects ATLAS prototype detectors and small test detectors were irradiated to a fluence of 3 * 10/sup 14/ 24 GeV protons/cm/sup 2/. After irradiation, the detectors were annealed at 25 degrees C to simulate the damage foreseen after 10 years of ATLAS operation. The detectors were then connected to the SCT32A analogue front-end chips and tested with a /sup 106/Ru source. The performance of the irradiated detectors was compared to non-irradiated detectors from the same batch. The charge collection efficiency is discussed taking into account the electronic response of the readout chip and the ballistic deficit. (10 refs).

  6. A front-end electronics module for multi-gap resistive plate chambers

    International Nuclear Information System (INIS)

    Background: The output current signal of Multi-gap Resistive Plate Chambers (MRPCs) has low amplitude and fast speed. Purpose: Its amplitude and time information should be obtained in particle Time-of-Flight (TOF) detection. Methods: A simple electronics module for the presentation of the signals from MRPCs to standard existing digitization electronics is described. The circuit is based on 'off-the-shelf' discrete components. An optimization of the values of specific components is required to match the aspects of the MRPCs for the given application. The key electronic noise control plan is also discussed. Results: This electronics module has the excellent features including low prices, convenient making, easy assembling for testing system, etc. Conclusions: This electronics module is an attractive option for the front-end signal processing in MRPCs prototype and bench or beam-testing efforts, as well as in final implementations of small-area particle TOF system with existing data acquisition systems. (authors)

  7. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  8. System considerations and RF front-end design for integration of satellite navigation and mobile standards

    Directory of Open Access Journals (Sweden)

    A. Miskiewicz

    2009-05-01

    Full Text Available The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF, and 1dB compression point (P1dB of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

  9. Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

    CERN Document Server

    Cooper, B; The ATLAS collaboration

    2012-01-01

    Around 2021 the Large Hadron Collider will be upgraded to provide instantaneous luminosities 5x10^34, leading to excessive rates from the ATLAS Level-1 trigger. We describe a double-buffer front-end architecture for the ATLAS tracker replacement which should enable tracking information to be used in the Level-1 decision. This will allow Level-1 rates to be controlled whilst preserving high efficiency for single lepton triggers at relatively low transverse momentum thresholds pT ~25 GeV, enabling ATLAS to remain sensitive to physics at the electroweak scale. In particular, a potential hardware solution for the communication between the upgraded silicon barrel strip detectors and the external processing within this architecture will be described, and discrete event simulations used to demonstrate that this fits within the tight latency constraints.

  10. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  11. A low power low noise analog front end for portable healthcare system

    International Nuclear Information System (INIS)

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

  12. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    % relative bandwidth. The transmitter uses two amplifiers combined in parallel to generate more than >128 W peak power, with system >60% PAE and 47 dB in-band to out-of-band signal ratio. The four channel receiver features digitally controlled variable gain to achieve more than 100 dB dynamic range, 2.4 d......B noise figure, 160 ns receiver recovery time and -46 dBc 3rd order IMD products. The system comprises also, a digital front-end, a digital signal generator, a microstrip antenna array and a control unit. All the subsystems were integrated, certified and functionally tested, and in May 2008 a successful...

  13. A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

    Science.gov (United States)

    Singh, Harjit; Loach, James; Poon, Alan

    2012-10-01

    One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.

  14. Single event effects on the APV25 front-end chip

    CERN Document Server

    Friedl, M; Pernicka, Manfred

    2003-01-01

    The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider at CERN will include a Silicon Strip Tracker covering a sensitive area of 206 m**2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25 mum deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets are inevitable. Moreover, localized ionization can also produce fake signals in the analog circuitry. Eight APV25 chips were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

  15. An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

    Institute of Scientific and Technical Information of China (English)

    LIU Dong-sheng; ZOU Xue-cheng; YANG Qiu-ping; XIONG Ting-wen

    2006-01-01

    The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) transponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD)protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

  16. Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications

    Science.gov (United States)

    Venkatesan, Jaikrishna; Mysoor, Narayan R.; Hashemi, Hassein; Aflatouni, Firooz

    2010-01-01

    A fully integrated, front-end Ka-band monolithic microwave integrated circuit (MMIC) was developed that houses an LNA (low noise amplifier) stage, a down-conversion stage, and output buffer amplifiers. The MMIC design employs a two-step quadrature down-conversion architecture, illustrated in the figure, which results in improved quality of the down-converted IF quadrature signals. This is due to the improved sensitivity of this architecture to amplitude and phase mismatches in the quadrature down-conversion process. Current sharing results in reduced power consumption, while 3D-coupled inductors reduce the chip area. Improved noise figure is expected over previous SiGe-based, frontend designs

  17. Design and performance Assessment of an Airborne Ice Sounding Radar Front-End

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2008-01-01

    The paper describes the design and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design features newly developed components at a centre frequency of 435 MHz, such as, antenna 20% bandwidth at RL ≪ 13 dB, compact high power in......-phase and out-of-phase power dividers with a relative bandwidth of 20% and more than 75W CW power handling, high power SPDT PIN switch with 90W CW power handling and a 70W CW High efficiency LDMOS power amplifier with ≫60% power-added efficiency. The system comprises also a digital signal generator, a digital...

  18. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    ; Igartua, 2010) as a facilitator of innovation and may therefore also be targeted at FEI support. The pharmaceutical industry has experienced a worldwide decline in the number of applications for new molecular entities to regulatory agencies since 1997. Therefore high pressures are put on pharmaceutical...... research and FEI to produce more valid candidates and faster for drug development. This paper explores how pharmaceutical front end innovation can be actively supported through the development and implementation of an innovation strategy. The empirical field and applied methodology is an action......-oriented longitudinal case study of a Danish pharmaceutical company. The findings and key learnings from the study are presented as propositions of how innovation strategies can be applied to actively facilitate FEI and with measurable results....

  19. Key differences and similarities in ways of managing and supporting radical pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2015-01-01

    The purpose of this paper is to explore how Front End Innovation (FEI) is supported and managed among companies of different nationality within the context of pharmaceutical R&D. The present study is carried out in order to contribute to the development of a clearer understanding of active...... of the Danish and US based pharmaceutical company, H. Lundbeck A/S, and a comparative study including five European and American pharmaceutical companies. The findings from the study reveal a number of similarities and differences in innovation management and FEI support of radical projects and among...... the different nationalities. This presents propositions of important aspects to consider in facilitation of radical FEI in general and in multinational pharmaceutical companies. In addition, proposals are made for a global study of innovation management and FEI support including Chinese and other Asian...

  20. Front-End Electronics for Verification Measurements: Performance Evaluation and Viability of Advanced Tamper Indicating Measures

    International Nuclear Information System (INIS)

    The International Atomic Energy Agency (IAEA) continues to expand its use of unattended, remotely monitored measurement systems. An increasing number of systems and an expanding family of instruments create challenges in terms of deployment efficiency and the implementation of data authentication measures. A collaboration between Pacific Northwest National Laboratory (PNNL), Idaho National Laboratory (INL), and Los Alamos National Laboratory (LANL) is working to advance the IAEA's capabilities in these areas. The first objective of the project is to perform a comprehensive evaluation of a prototype front-end electronics package, as specified by the IAEA and procured from a commercial vendor. This evaluation begins with an assessment against the IAEA's original technical specifications and expands to consider the strengths and limitations over a broad range of important parameters that include: sensor types, cable types, and the spectrum of industrial electromagnetic noise that can degrade signals from remotely located detectors. A second objective of the collaboration is to explore advanced tamper-indicating (TI) measures that could help to address some of the long-standing data authentication challenges with IAEA's unattended systems. The collaboration has defined high-priority tampering scenarios to consider (e.g., replacement of sensor, intrusion into cable), and drafted preliminary requirements for advanced TI measures. The collaborators are performing independent TI investigations of different candidate approaches: active time-domain reflectometry (PNNL), passive noise analysis (INL), and pulse-by-pulse analysis and correction (LANL). The initial investigations focus on scenarios where new TI measures are retrofitted into existing IAEA UMS deployments; subsequent work will consider the integration of advanced TI methods into new IAEA UMS deployments where the detector is separated from the front-end electronics. In this paper, project progress

  1. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  2. Design and optimization of a 2.4 GHz RF front-end with an on-chip balun

    Institute of Scientific and Technical Information of China (English)

    Xu Hua; Wang Lei; Shi Yin; Dai Fa Foster

    2011-01-01

    A 2.4 GHz low-power,low-noise and highly linear receiver front-end with a low noise amplifier (LNA)and balun optimization is presented.Direct conversion architecture is employed for this front-end.The on-chip balun is designed for single-to-differential conversion between the LNA and the down-conversion mixer,and is optimized for the best noise performance of the front-end.The circuit is implemented with 0.35μm SiGe BiCMOS technology.The front-end has three gain steps for maximization of the input dynamic range.The overall maximum gain is about 36 dB.The double-sideband noise figure is 3.8 dB in high gain mode and the input referred third-order intercept point is 12.5 dBm in low gain mode.The down-conversion mixer has a tunable parallel R-C load at the output and an emitter follower is used as the output stage for testing purposes.The total front-end dissipation is 33 mW under a 2.85 V supply and occupies a 0.66 mm2 die size.

  3. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  4. Low noise, low power front end electronics for pixelized TFA sensors

    CERN Document Server

    Poltorak, K; Dabrowski, W; Despeisse, M; Jarron, P; Kaplon, J; Wyrschb, N

    2009-01-01

    Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on top of the readout ASIC, TFA shows the similarity to MAP imagers, allowing, however, more sophisticated front–end circuitry to extract the signals, like in case of Hybrid Pixel technology. In this paper we present preliminary experimental results of TFA structures, obtained with 10 μm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/μm for minimum ionizing particles, therefore a low noise, high gain and very low power of the front- end are of primary importance. The developed demonstrator chip, designed in 250 nm CMOS technology, comprises an array of 64 by 64 pi...

  5. Characteristics and Disposal Categorization of Solid Radioactive Waste from the Front End of the Uranium Fuel Cycle

    International Nuclear Information System (INIS)

    The proper categorization of radioactive waste forms the basis for defining its disposal method. In particular, it is the basis for defining the disposal policy for solid radioactive waste from the front end of the uranium fuel cycle to identify scientifically its characteristics, in view of the differences in regulatory approach between artificial radioactive waste and NORM waste. The paper examines the disposal policy and practice in China and other countries for solid radioactive waste from the front end of the uranium fuel cycle and discusses the confusion in disposal of the waste as artificial radioactive waste. The radionuclide composition and characteristics of the solid radioactive waste from the front end of the uranium fuel cycle are investigated in detail and a new idea that such waste needs to be disposed of and categorized as NORM waste is proposed. (author)

  6. Instrumentation Developments and Beam Studies for the Fermilab Proton Improvement Plan LINAC Upgrade and New RFQ Front-End

    CERN Document Server

    Scarpine, Victor E; Karns, Pat R; Bollinger, Daniel S; Duel, Kevin L; Eddy, Nathan; Lui, Ning; Semenov, Alexei; Tomlin, Raymond E; Pellico, William A

    2014-01-01

    Fermilab is developing a Proton Improvement Plan (PIP) to increase throughput of its proton source. The plan addresses hardware modifications to increase repetition rate and improve beam loss while ensuring viable operation of the proton source through 2025. The first phase of the PIP will enable the Fermilab proton source to deliver 1.8e17 protons per hour by mid-2013. As part of this initial upgrade, Fermilab plans to install a new front-end consisting of dual H- ion sources and a 201 MHz pulsed RFQ. This paper will present beam studies measurements of this new front-end and discuss new beam instrumentation upgrades for the Fermilab linac.

  7. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  8. The Virtual Learning Commons: Supporting the Fuzzy Front End of Scientific Research with Emerging Technologies

    Science.gov (United States)

    Pennington, D. D.; Gandara, A.; Gris, I.

    2012-12-01

    The Virtual Learning Commons (VLC), funded by the National Science Foundation Office of Cyberinfrastructure CI-Team Program, is a combination of Semantic Web, mash up, and social networking tools that supports knowledge sharing and innovation across scientific disciplines in research and education communities and networks. The explosion of scientific resources (data, models, algorithms, tools, and cyberinfrastructure) challenges the ability of researchers to be aware of resources that might benefit them. Even when aware, it can be difficult to understand enough about those resources to become potential adopters or re-users. Often scientific data and emerging technologies have little documentation, especially about the context of their use. The VLC tackles this challenge by providing mechanisms for individuals and groups of researchers to organize Web resources into virtual collections, and engage each other around those collections in order to a) learn about potentially relevant resources that are available; b) design research that leverages those resources; and c) develop initial work plans. The VLC aims to support the "fuzzy front end" of innovation, where novel ideas emerge and there is the greatest potential for impact on research design. It is during the fuzzy front end that conceptual collisions across disciplines and exposure to diverse perspectives provide opportunity for creative thinking that can lead to inventive outcomes. The VLC integrates Semantic Web functionality for structuring distributed information, mash up functionality for retrieving and displaying information, and social media for discussing/rating information. We are working to provide three views of information that support researchers in different ways: 1. Innovation Marketplace: supports users as they try to understand what research is being conducted, who is conducting it, where they are located, and who they collaborate with; 2. Conceptual Mapper: supports users as they organize their

  9. Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

    Directory of Open Access Journals (Sweden)

    Jimmy Nsenga

    2007-03-01

    Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

  10. Digital pulse processing and optimization of the front-end electronics for nuclear instrumentation.

    Science.gov (United States)

    Bobin, C; Bouchard, J; Thiam, C; Ménesguen, Y

    2014-05-01

    This article describes an algorithm developed for the digital processing of signals provided by a high-efficiency well-type NaI(Tl) detector used to apply the 4πγ technique. In order to achieve a low-energy threshold, a new front-end electronics has been specifically designed to optimize the coupling to an analog-to-digital converter (14 bit, 125 MHz) connected to a digital development kit produced by Altera(®). The digital pulse processing is based on an IIR (Infinite Impulse Response) approximation of the Gaussian filter (and its derivatives) that can be applied to the real-time processing of digitized signals. Based on measurements obtained with the photon emissions generated by an (241)Am source, the energy threshold is estimated to be equal to ~2 keV corresponding to the physical threshold of the NaI(Tl) detector. An algorithm developed for a Silicon Drift Detector used for low-energy x-ray spectrometry is also described. In that case, the digital pulse processing is specifically designed for signals provided by a reset-type preamplifier ((55)Fe source). PMID:24326314

  11. Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

    Directory of Open Access Journals (Sweden)

    Nsenga Jimmy

    2007-01-01

    Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

  12. An analogue front-end ASIC prototype designed for PMT signal readout

    Science.gov (United States)

    Liu, Jian-Feng; Zhao, Lei; Yu, Li; Liang, Yu; Qin, Jia-Jun; Yang, Yun-Fan; Wu, Wei-Hao; Liu, Shu-Bin; An, Qi

    2016-06-01

    The Water Cherenkov Detector Array (WCDA) is one of the core detectors in the Large High Altitude Air Shower Observatory (LHAASO), and it consists of 3600 photomultiplier tubes (PMTs). Both high resolution time and charge measurement are required over a large dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated using Global Foundry 0.35 μm CMOS technology is designed to read out the PMT signal in the WCDA. This ASIC employs leading edge discrimination and an (RC)4 shaping structure. Combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge resolution is better than 10% at 1 P.E. and better than 1% with large input signals (300 P.E. to 4000 P.E.). Besides, this ASIC has a good channel-to-channel isolation of more than 84 dB and the temperature dependency of charge measurement is less than 5% in the range 0–50°C. Supported by Knowledge Innovation Program of Chinese Academy of Sciences (KJCX2-YW-N27), National Natural Science Foundation of China (11175174) and CAS Center for Excellence in Particle Physics (CCEPP)

  13. A front-end readout Detector Board for the OpenPET electronics system

    Science.gov (United States)

    Choong, W.-S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C. Q.; Wu, J.-Y.

    2015-08-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ``time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc.

  14. A low power low noise analog front end for portable healthcare system

    Science.gov (United States)

    Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

    2015-10-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

  15. The MYRRHA ADS Project in Belgium Enters the Front End Engineering Phase

    Science.gov (United States)

    De Bruyn, Didier; Abderrahim, Hamid Aït; Baeten, Peter; Leysen, Paul

    The MYRRHA project started in 1998 by SCK•CEN. MYRRHA is a MTR, based on the ADS concept, for material and fuel research, for studying the feasibility of transmutation of Minor Actinides and Long-Lived Fission Products arising from radioactive waste reprocessing and finally for demonstrating at a reasonable power scale the principle of the ADS. The MYRRHA design has progressed through various framework programmes of the European Commission in the context of Partitioning and Transmutation. The design has now entered into the Front End Engineering Phase (FEED) covering the period 2012-2015. The engineering company, which will handle this phase, has been selected and the works have begun in the late 2013. In the mean time we have made some refinements in both primary systems and plant layout, including reactor building design. In this paper, we present the most recent developments of the MYRRHA design in terms of reactor building and plant layout as existing today as well as a preliminary study concerning the spent fuel building of the facility. During the oral presentation we add some preliminary results of the interaction with the FEED contractor and the most recent version of the primary systems.

  16. The front-end electronics of the LSPE-SWIPE experiment

    Science.gov (United States)

    Fontanelli, F.; Biasotti, M.; Bevilacqua, A.; Siccardi, F.

    2016-07-01

    The SWIPE detector of the Ballon Borne Mission LSPE (see e.g. the contribution of P. de Bernardis et al. in this conference) intends to measure the primordial 'B-mode' polarization of the Cosmic Microwave Background (CMB). For this scope microwave telescopes need sensitive cryogenic bolometers with an overall equivalent noise temperature in the nK range. The detector is a spiderweb bolometer based on transition edge sensor and followed by a SQUID to perform the signal readout. This contribution will concentrate on the design, description and first tests on the front-end electronics which processes the squid output (and controls it). The squid output is first amplified by a very low noise preamplifier based on a discrete JFET input differential architecture followed by a low noise CMOS operational amplifier. Equivalent input noise density is 0.6 nV/Hz and bandwidth extends up to at least 2 MHz. Both devices (JFET and CMOS amplifier) have been tested at liquid nitrogen. The second part of the contribution will discuss design and results of the control electronics, both the flux locked loop for the squid and the slow control chain to monitor and set up the system will be reviewed.

  17. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    International Nuclear Information System (INIS)

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs

  18. A front-end readout Detector Board for the OpenPET electronics system

    International Nuclear Information System (INIS)

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, and high-performance OpenPET electronics system. The analog signals from the different types of detectors used in medical imaging share similar characteristics, which allows for a common analog signal processing. The OpenPET electronics processes the analog signals with Detector Boards. Here we report on the development of a 16-channel Detector Board. Each signal is digitized by a continuously sampled analog-to-digital converter (ADC), which is processed by a field programmable gate array (FPGA) to extract pulse height information. A leading edge discriminator creates a timing edge that is ''time stamped'' by a time-to-digital converter (TDC) implemented inside the FPGA . This digital information from each channel is sent to an FPGA that services 16 analog channels, and then information from multiple channels is processed by this FPGA to perform logic for crystal lookup, DOI calculation, calibration, etc

  19. Advances in Front-end Enabling Technologies for Thermal Infrared `THz Torch' Wireless Communications

    Science.gov (United States)

    Hu, Fangjing; Lucyszyn, Stepan

    2016-05-01

    The thermal (emitted) infrared frequency bands (typically 20-40 and 60-100 THz) are best known for remote sensing applications that include temperature measurement (e.g. non-contacting thermometers and thermography), night vision and surveillance (e.g. ubiquitous motion sensing and target acquisition). This unregulated part of the electromagnetic spectrum also offers commercial opportunities for the development of short-range secure communications. The `THz Torch' concept, which fundamentally exploits engineered blackbody radiation by partitioning thermally generated spectral radiance into pre-defined frequency channels, was recently demonstrated by the authors. The thermal radiation within each channel can be independently pulse-modulated, transmitted and detected, to create a robust form of short-range secure communications within the thermal infrared. In this paper, recent progress in the front-end enabling technologies associated with the THz Torch concept is reported. Fundamental limitations of this technology are discussed; possible engineering solutions for further improving the performance of such thermal-based wireless links are proposed and verified either experimentally or through numerical simulations. By exploring a raft of enabling technologies, significant enhancements to both data rate and transmission range can be expected. With good engineering solutions, the THz Torch concept can exploit nineteenth century physics with twentieth century multiplexing schemes for low-cost twenty-first century ubiquitous applications in security and defence.

  20. Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

    CERN Document Server

    Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

    1997-01-01

    We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

  1. An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

    CERN Document Server

    Porter, Ryan

    This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

  2. A non-dimensional approach in solving front end, underhood flow and heat transfer problems

    International Nuclear Information System (INIS)

    A non-dimensional approach is developed to solve the front end and underhood flow problems with a cooling fan as one of the momentum sources. Typically, the fan in the vehicle is in an environment, which has high temperatures. These high temperatures have the effect of changing the density. The density variation in these cases is assumed to be a function of temperature alone. It is well known that these changes in the density affect the flow rates through the heat exchangers. The changes in the density and its effect on the flow rates if a fan model is present cannot be addressed using commercial codes unless user defined functions are written. The present method addresses how these variations can be handled using a non-dimensional approach without having to write user routines. The governing equations of flow and heat transfer are non-dimensionalized and the corresponding inputs to commercial codes found so as to enable these codes to handle the non-dimensional equations. The following sections illustrate the procedure to be used to solve these problems. (author)

  3. A non-dimensional approach in solving front end, underhood flow and heat transfer problems

    Energy Technology Data Exchange (ETDEWEB)

    Damodaran, V. [General Motors, Detroit, Michigan (United States)]. E-mail: vijay.damodran@gm.com

    2003-07-01

    A non-dimensional approach is developed to solve the front end and underhood flow problems with a cooling fan as one of the momentum sources. Typically, the fan in the vehicle is in an environment, which has high temperatures. These high temperatures have the effect of changing the density. The density variation in these cases is assumed to be a function of temperature alone. It is well known that these changes in the density affect the flow rates through the heat exchangers. The changes in the density and its effect on the flow rates if a fan model is present cannot be addressed using commercial codes unless user defined functions are written. The present method addresses how these variations can be handled using a non-dimensional approach without having to write user routines. The governing equations of flow and heat transfer are non-dimensionalized and the corresponding inputs to commercial codes found so as to enable these codes to handle the non-dimensional equations. The following sections illustrate the procedure to be used to solve these problems. (author)

  4. The Front-End Electronics for the HADES RPC Wall (ESTRELA-FEE)

    Science.gov (United States)

    Belver, D.; Garzón, J. A.; Gil, A.; González-Díaz, D.; Koenig, W.; Lange, S.; Marín, J.; Montes, N.; Skott, P.; Traxler, M.; Zapata, M.

    2006-08-01

    A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m 2 with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most.

  5. Front-End electronics development for the new Resistive Plate Chamber detector of HADES

    Science.gov (United States)

    Gil, A.; Belver, D.; Cabanelas, P.; Díaz, J.; Garzón, J. A.; González-Díaz, D.; Koenig, W.; Lange, J. S.; Marín, J.; Montes, N.; Skott, P.; Traxler, M.

    2007-11-01

    In this paper we present the new RPC wall, which is being installed in the HADES detector at Darmstadt GSI. It consists of time-of-flight (TOF) detectors used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The wall will contain 1024 RPC modules, covering an active area of around 7 m2, replacing the old TOFino detector at the low polar angle region. The excellent TOF and good charge resolutions of the new detector will improve the time resolution to values better than 100 ps. The Front-End electronics for the readout of the RPC signals is implemented with two types of boards to satisfy the space constraints: the Daughterboards are small boards that amplify the low level signals from the detector and provide fast discriminators for time of flight measurements, as well as an integrator for charge measurements. The Motherboard provides stable DC voltages and a stable ground, threshold DACs for the discriminators, multiplicity trigger and impedance matched paths for transfer of time window signals that contain information about time and charge. These signals are sent to a custom TDC board that label each event and send data through Ethernet to be conveniently stored.

  6. A novel pseudo resistor structure for biomedical front-end amplifiers.

    Science.gov (United States)

    Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

    2015-08-01

    This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

  7. Advances in Front-end Enabling Technologies for Thermal Infrared ` THz Torch' Wireless Communications

    Science.gov (United States)

    Hu, Fangjing; Lucyszyn, Stepan

    2016-09-01

    The thermal (emitted) infrared frequency bands (typically 20-40 and 60-100 THz) are best known for remote sensing applications that include temperature measurement (e.g. non-contacting thermometers and thermography), night vision and surveillance (e.g. ubiquitous motion sensing and target acquisition). This unregulated part of the electromagnetic spectrum also offers commercial opportunities for the development of short-range secure communications. The ` THz Torch' concept, which fundamentally exploits engineered blackbody radiation by partitioning thermally generated spectral radiance into pre-defined frequency channels, was recently demonstrated by the authors. The thermal radiation within each channel can be independently pulse-modulated, transmitted and detected, to create a robust form of short-range secure communications within the thermal infrared. In this paper, recent progress in the front-end enabling technologies associated with the THz Torch concept is reported. Fundamental limitations of this technology are discussed; possible engineering solutions for further improving the performance of such thermal-based wireless links are proposed and verified either experimentally or through numerical simulations. By exploring a raft of enabling technologies, significant enhancements to both data rate and transmission range can be expected. With good engineering solutions, the THz Torch concept can exploit nineteenth century physics with twentieth century multiplexing schemes for low-cost twenty-first century ubiquitous applications in security and defence.

  8. A Time-Based Front End Readout System for PET & CT

    CERN Document Server

    Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

    2007-01-01

    In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

  9. Development of a GUI Based Front End for Open Source CFD Program, OpenFOAM

    Energy Technology Data Exchange (ETDEWEB)

    Han, Samhee; Lee, Youngjin; Kim, Hyongchol; Park, Sunbyung; Kim, Hyunjik [Nuclear Safety Evaluation, Daejeon (Korea, Republic of)

    2013-05-15

    OpenFOAM is sorely lacking in user friendliness as it runs in console mode under Li nux. Run{sub F}OAM was developed to greatly simplify the task of running an OpenFOAM calculation under Windows OS. Run{sub F}OAM was written using Delphi object pascal language, and GLScene package was used for the 3D graphics. Verification of Run{sub F}OAM was carried out by performing some OpenFOAM CFD calculations provided in OpenFOAM package, and these showed that the use of Run{sub F}OAM is simple whilst providing sufficient allowances in user modifications. Run{sub F}oam, a GUI based front end program to simplify running Open Foam CFD cases, has been developed. By incorporating numerous GUI in the program, Run{sub F}oam has demonstrated that running an Open Foam case can be easily accomplished. There is a potential for further development as the Open Foam has the great advantage of being free to develop and to use. There is also a potential to couple or interface the Open Foam with the systems analysis code such as Relap5.

  10. Development of a GUI Based Front End for Open Source CFD Program, OpenFOAM

    International Nuclear Information System (INIS)

    OpenFOAM is sorely lacking in user friendliness as it runs in console mode under Li nux. RunFOAM was developed to greatly simplify the task of running an OpenFOAM calculation under Windows OS. RunFOAM was written using Delphi object pascal language, and GLScene package was used for the 3D graphics. Verification of RunFOAM was carried out by performing some OpenFOAM CFD calculations provided in OpenFOAM package, and these showed that the use of RunFOAM is simple whilst providing sufficient allowances in user modifications. RunFoam, a GUI based front end program to simplify running Open Foam CFD cases, has been developed. By incorporating numerous GUI in the program, RunFoam has demonstrated that running an Open Foam case can be easily accomplished. There is a potential for further development as the Open Foam has the great advantage of being free to develop and to use. There is also a potential to couple or interface the Open Foam with the systems analysis code such as Relap5

  11. An Analogue Front-End ASIC Prototype Designed For PMT Signal Readout

    CERN Document Server

    Liu, Jianfeng; Yu, Li; Liang, Yu; Qin, Jiajun; Yang, Yunfang; Wu, Weihao; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) is designed for high energy gamma ray and cosmic ray detection. A Water Cherenkov Detector Array which is sensitive to gamma ray showers above a few hundred GeV is proposed to survey gamma ray sources. The WCDA consists of 3600 PhotoMultiplier Tubes (PMT) which collect the Cherenkov light produced by the shower particles in water. Both high precision time and charge measurement are required over a large dynamic range from 1 photo electron (P.E.) to 4000 P.E. Prototype of an analogue front-end Application Specific Integrated Circuit (ASIC) fabricated in Chartered 0.35 {\\mu}m CMOS technology is designed to read out PMT signal in the WCDA. This ASIC employs leading edge discrimination and RC4 shaping structure; combined with the following Time-to-Digital Converter (TDC) and Analog-to-Digital Converter (ADC), both the arrival time and charge of the PMT signal can be measured. Initial test results indicate that time resolution is better than 350 ps and charge...

  12. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  13. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  14. The dielectric-filled parabola - A new millimeter/submillimeter wavelength receiver/transmitter front end

    Science.gov (United States)

    Siegel, Peter H.; Dengler, Robert J.

    1991-01-01

    A design is presented for a semi-integrated millimeter/submillimeter wavelength receiver/transmitter front end incorporating a planar antenna and a solid-state device in an efficient feed structure which can be matched directly to high f-number optical systems. The feed system combines the simplicity and robustness of a dielectric substrate lens with the high gain of a parabolic reflector in a single structure that is termed a dielectric-filled parabola. The same fundamental unit can be configured as either a heterodyne or direct detection mode receiver, a power transmitter or a frequency multiplier by changing out the solid-state device and/or the integrated antenna. The structure can also be used with a small integrated antenna array in a multibeam or imaging arrangement. Design and fabrication details for the feed system are given. These are followed by beam pattern and impedance measurements taken on a microwave model when dipole, bow-tie, log-periodic, and log-spiral antennas are used as the integrated feed elements.

  15. An analog front-end enables electrical impedance spectroscopy system on-chip for biomedical applications

    International Nuclear Information System (INIS)

    The increasing number of applications of electrical bioimpedance measurements in biomedical practice, together with continuous advances in textile technology, has encouraged several researchers to make the first attempts to develop portable, even wearable, electrical bioimpedance measurement systems. The main target of these systems is personal and home monitoring. Analog Devices has made available AD5933, a new system-on-chip fully integrated electrical impedance spectrometer, which might allow the implementation of minimum-size instrumentation for electrical bioimpedance measurements. However, AD5933 as such is not suitable for most applications of electrical bioimpedance. In this work, we present a relatively simple analog front-end that adapts AD5933 to a four-electrode strategy, allowing its use in biomedical applications for the first time. The resulting impedance measurements exhibit a very good performance in aspects like load dynamic range and accuracy. This type of minimum-size, system-on-chip-based bioimpedance measurement system would lead researchers to develop and implement light and wearable electrical bioimpedance systems for home and personal health monitoring applications, a new and huge niche for medical technology development

  16. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

  17. The front-end readout electronics for the bar PANDA Focussing-Lightguide Disc DIRC

    Science.gov (United States)

    Cowie, E.; Föhl, K.; Glazier, D.; Hill, G.; Hoek, M.; Kaiser, R.; Keri, T.; Murray, M.; Rosner, G.; Seitz, B.

    2009-11-01

    One of the key detectors of the upcoming bar PANDA experiment for particle identification will be the Focussing-Lightguide Disc DIRC, based on a novel detector technique. It will use a fused silica disc as a solid radiator to generate Cherenkov light by the passing of charged particles. These photons will be transported by total-internal-reflection to the rim, where LiF crystals will be used to perform dispersion corrections. Focussing lightguides will map propagation angles to spatial positions on the surface of photon detectors. Fast single photon detection devices will be used to measure azimuthal angles and spatial positions, which can be used to reconstruct kinematic properties of the passing particles. The expected average interaction rate of 20 MHz yields a photon detection rate of 1.3 MHz, as it is foreseen to use 128 MCP-PMT, each with 32 channels, for continuous readout. Moderate timing resolution of 300 ps improves signal from noise separation. The readout design requirements for the Focussing-Lightguide Disc DIRC will be introduced. The current candidate for implementation of the front-end readout electronic system will be described and several alternative readout scenarios will be discussed. Finally, a summary and an outlook for further developments and tests will be given.

  18. Continuous-time digital front-ends for multistandard wireless transmission

    CERN Document Server

    Nuyts, Pieter A J; Dehaene, Wim

    2014-01-01

    This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components.  After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware.  As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling.  The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality.  Next, a high-level theoretical analysis of two different PWM-based architectures – baseband PWM and RF PWM – is made.  On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits.  Important design criteria are identified and diff...

  19. Upgrade Design of TileCal Front-end Readout Electronics and Radiation Hardness Studies

    CERN Document Server

    Anderson, K; The ATLAS collaboration; Drake, G; Eriksson, D; Muschter, S; Oreglia, M; Pilcher, J; Price, L; Tang, F

    2011-01-01

    The ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of hadrons and taus produced in LHC collisions. The TileCal consists of "tiles" of plastic scintillator dispersed in a fine-grained steel matrix . Optical fibers from the tiles are sent to ~10,000 photomultiplier tubes (PMT) and associated readout electronics. The TileCal front-end analog readout electronics process the signals from ~10,000 PMTs. Signals from each PMT are shaped with a 7-pole passive LC shaper and split it to two channels amplified by a pair of clamping amplifiers with a gain ratio of 32. Incorporated with two 40Msps 12-bit ADCs, the readout electronics provide a combined dynamic range of 17-bits. With this dynamic range, the readout system is capable of measuring the energy deposition in the calorimeter cells from ~220MeV to 1.3TeV with the least signal-to-noise ratio of greater than 20. The digitized data from each PMT are transmitted off-detector optically, where the data are further processed with ded...

  20. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  1. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    Cassina, L

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  2. Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

    Science.gov (United States)

    Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

    2012-07-01

    There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

  3. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved

  4. Front-end ASICs development for W-Si calorimeter at ILC

    International Nuclear Information System (INIS)

    An ASIC (FLCPHY3) has been developed to read out the test-beam prototype of the future international linear collider (ILC) tungsten-silicon calorimeter. It consists of 18 channels low-noise charge preamplifiers, bi-gain CRRC2 180 ns shapers, 12-bit track-and-hold, and a 5 MHz output multiplexer. It covers a dynamic range of 14 bits with a noise of 3500 e- with the 70 pF detector and a linearity at the per-mil level. The chip dissipates 6 mW/channel and 1000 chips have been produced in AMS 0.8 μm BiCMOS technology in 2003. One channel has recently been migrated into 0.35 μm, improving the series noise by 20% and the 1/f noise by two. Besides, a power pulsing feature has been added in order to exploit the 1% duty cycle of the accelerator. This feature is a key parameter for ILC, as it is mandatory to embed the front-end inside the detector, without spoiling the Moliere radius with cooling pipes. Preliminary results indicate a good behavior in pulsing mode and several hundred channels have been produced of the recent version including this feature (FLCPHY4), to be tested extensively in test beam at CERN in autumn 2006. FLCPHY4 also includes a 12-bit ADC in order to take a step to the final version, which will send digital data out

  5. A single active nanoelectromechanical tuning fork front-end radio-frequency receiver

    International Nuclear Information System (INIS)

    Nanoelectromechanical systems (NEMS) offer the potential to revolutionize fundamental methods employed for signal processing in today’s telecommunication systems, owing to their spectral purity and the prospect of integration with existing technology. In this work we present a novel, front-end receiver topology based on a single device silicon nanoelectromechanical mixer-filter. The operation is demonstrated by using the signal amplification in a field effect transistor (FET) merged into a tuning fork resonator. The combination of both a transistor and a mechanical element into a hybrid unit enables on-chip functionality and performance previously unachievable in silicon. Signal mixing, filtering and demodulation are experimentally demonstrated at very high frequencies ( > 100 MHz), maintaining a high quality factor of Q = 800 and stable operation at near ambient pressure (0.1 atm) and room temperature (T = 300 K). The results show that, ultimately miniaturized, silicon NEMS can be utilized to realize multi-band, single-chip receiver systems based on NEMS mixer-filter arrays with reduced system complexity and power consumption. (paper)

  6. DAQ system for testing RPC front-end electronics of the INO experiment

    International Nuclear Information System (INIS)

    The Resistive Plate Chamber (RPC) is the active detector element in the INO experiment. The in-house developed ANUSPARSH-III ASICs are being used as front-end electronics of the detector. The 2 m X 2 m RPC being used has 64-readout channels on X-side and 64-readout channels on Y-side. In order to test and validate the FE along with the RPC, a 64-channel DAQ system has been designed and developed. The detector parameters to be measured are noise rate, efficiency, hit pattern register and time resolution. The salient features of the DAQ system are: 64-channel LVDS receiver in FPGA, FPGA based parameter calculations and a micro controller for acquiring the processed data from FPGAs and sent through Ethernet and USB interfaces. The DAQ system consists of following parts: Two FPGAs each receiving 32 LVDS channels, FPGA firm-ware, micro controller firm-ware, Ethernet interface, embedded web server hosting data analysis software, USB interface, and Lab-windows based data analysis software. The DAQ system has been tested at TIFR with 1 m X 1 m RPC

  7. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  8. One size does not fit all - understanding the front-end and back-ens of business model innovation

    DEFF Research Database (Denmark)

    Günzel, Franziska; Holm, Anna B.

    2013-01-01

    Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed...... understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...... production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance...

  9. A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

  10. An inquiry on managers use of decision-making tools in the core front end of the innovation process

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.;

    2013-01-01

    This paper focuses on the Core Front End (CFE) activities of the innovation process to say, Opportunity Identification and Opportunity Analysis. In the CFE of innovation, several tools are used to facilitate and optimise decisions. To select them, managers of the product development team have......, difficulty in usage, frequency of usage and estimate investment for using them. Also, interesting cross-case patterns emerge....

  11. Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

    International Nuclear Information System (INIS)

    This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about −6 dBm and −3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology. (semiconductor integrated circuits)

  12. 40 CFR 63.490 - Batch front-end process vents-performance test methods and procedures to determine compliance.

    Science.gov (United States)

    2010-07-01

    ... interim status requirements of 40 CFR part 265, subpart O. (c) Batch front-end process vent testing and... applicable procedures of Method 301, 40 CFR part 63, appendix A. (e) Aggregate batch vent stream testing for... under 40 CFR part 270 and complies with the requirements of 40 CFR part 266, subpart H; or (ii)...

  13. Interfirm collaboration in the fuzzy front-end of the innovation process - Exploring new forms of collaboration

    DEFF Research Database (Denmark)

    Bergenholtz, Carsten; Jørgensen, Jacob Høj; Goduscheit, Rene Chester;

    The objective of this paper is to elaborate on the differentiating characteristics between intra-firm and inter-firm innovation projects in the Fuzzy Front-End (FFE) of the innovation process. Focus is on management methods of the collaboration and the CEO-commitment to the project. The main point...

  14. Unified analytical expressions for calculating resonant frequencies, transimpedances, and equivalent input noise current densities of tuned receiver front ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1992-01-01

    Unified analytical expressions have been derived for calculating the resonant frequencies, transimpedance and equivalent input noise current densities of the four most widely used tuned optical receiver front ends built with FETs and p-i-n diodes. A more accurate FET model has been used to improve...

  15. Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

    Science.gov (United States)

    Meng, Zhang; Zhiqun, Li; Zengqi, Wang; Chenjian, Wu; Liang, Chen

    2014-01-01

    This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about -6 dBm and -3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology.

  16. Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter;

    2012-01-01

    In this paper, we describe resource-efficient hardware architectures for software-defined radio (SDR) front-ends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time...

  17. 75 FR 1179 - Passenger Equipment Safety Standards; Front End Strength of Cab Cars and Multiple-Unit Locomotives

    Science.gov (United States)

    2010-01-08

    ... Transportation (Secretary) convened a meeting of representatives from all sectors of the rail industry with the... Issues Identified for Future Rulemaking C. RSAC Overview D. Establishment of the Passenger Safety Working.... Accident History D. FRA and Industry Standards for Front End Frame Structures of Cab Cars and...

  18. Inter-firm collaboration in the Fuzzy Front-End of the innovation process - Exploring New Forms of Collaboration

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholz, Carsten;

    2007-01-01

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated ...

  19. A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Johansen, Tom K.; Zhurbenko, Vitaliy

    2013-01-01

    In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured...

  20. 40 CFR 63.488 - Methods and procedures for batch front-end process vent group determination.

    Science.gov (United States)

    2010-07-01

    ... limit applicable to the batch front-end process vent. (D) Design analysis based on accepted chemical... maximum design production). (iii) The single highest-HAP recipe for a product means the recipe of the product with the highest total mass of HAP charged to the reactor during the production of a single...

  1. Management of radioactive pollutants from front-end nuclear fuel cycle for clean environment - a regulatory approach

    International Nuclear Information System (INIS)

    Front end of Nuclear Fuel Cycle includes mining of low specific active material like uranium and thorium ore, milling of uranium and thorium and fabrication of nuclear fuel assemblies for Nuclear Power Plants. Diverse processes involved in the front-end nuclear fuel cycle lead to handling of wide spectrum of radionuclides. Atomic Energy Regulatory Board (AERB) is entrusted with the responsibility that discharge of the radioactive waste back into the environment does not create any undue hazard to environment and the public. Discharge limits have been prescribed by AERB for front-end fuel cycle facilities such that considering atmospheric, aquatic and terrestrial pathways; the effective dose to members of public does not exceed the yearly limit of 1 mSv. In order to comply with the regulatory limits prescribed by AERB, various treatment measures are adopted by the facilities. For release of conventional pollutants to environment, the limits are prescribed by the State Pollution Control Boards. This paper shall discuss the various treatment procedures adopted by the facilities with respect to radioactivity discharge vis-a-vis the health of the environment around the front-end nuclear fuel cycle facilities. (author)

  2. Play it forward: A Game-based tool for Sustainable Product and Business Model Innovation in the Fuzzy Front End

    NARCIS (Netherlands)

    Dewulf, K.R.

    2010-01-01

    Dealing with sustainability in the fuzzy front end of innovation is complex and often hard. There are a number of tools available to guide designers, engineers and managers in the design process after the specifications of the product or service are already set, but methods supporting goal finding f

  3. A high dynamic range programmable CMOS front-end filter with a tuning range from 1850 to 2400 MHz

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Lee, Thomas H.; Bruun, Erik

    2005-01-01

    This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, -25 dBm in-band 1-d...

  4. An integrated interface circuit with a capacitance-to-voltage converter as front-end for grounded capacitive sensors

    NARCIS (Netherlands)

    Heidary, A.; Meijer, G.C.M.

    2009-01-01

    This paper presents the analysis and design of an integrated interface for grounded capacitive sensors. To reduce the effects of parasitic cable capacitances, a feedforward technique has been applied. In combination with the use of a special front-end amplifier this yields high immunity for a parasi

  5. A 12-bit 40-MS/s SHA-less pipelined ADC using a front-end RC matching technique*

    Institute of Scientific and Technical Information of China (English)

    Fan Mingjun; Ren Junyan; Shu Guanghua; Guo Yao; Li Ning; Ye Fan; Xu Jun

    2011-01-01

    A 12-Bit 40-MS/s pipelined analog-to-digital converter (ADC) incorporates a front-end RC constant matching technique and a set of front-end timing with different duty cycle that are beneficial for enhancing linearity in SHA-less architecture without tedious verification in back-end layout simulation. Employing SHA-less, opampsharing and low-power opamps for low dissipation and low cost, designed in 0.13-μm CMOS technology, the prototype digitizes a 10.2-MHz input with 78.2-dB of spurious free dynamic range, 60.5-dB of signal-to-noiseand-distortion ratio, and -75.5-dB of total harmonic distortion (the first 5 harmonics included) while consuming 15.6-mW from a 1.2-V supply.

  6. A 14-bit 40-MHz analog front end for CCD application

    Science.gov (United States)

    Jingyu, Wang; Zhangming, Zhu; Shubin, Liu

    2016-06-01

    A 14-bit, 40-MHz analog front end (AFE) for CCD scanners is analyzed and designed. The proposed system incorporates a digitally controlled wideband variable gain amplifier (VGA) with nearly 42 dB gain range, a correlated double sampler (CDS) with programmable gain functionality, a 14-bit analog-to-digital converter and a programmable timing core. To achieve the maximum dynamic range, the VGA proposed here can linearly amplify the input signal in a gain range from -1.08 to 41.06 dB in 6.02 dB step with a constant bandwidth. A novel CDS takes image information out of noise, and further amplifies the signal accurately in a gain range from 0 to 18 dB in 0.035 dB step. A 14-bit ADC is adopted to quantify the analog signal with optimization in power and linearity. An internal timing core can provide flexible timing for CCD arrays, CDS and ADC. The proposed AFE was fabricated in SMIC 0.18 μm CMOS process. The whole circuit occupied an active area of 2.8 × 4.8 mm2 and consumed 360 mW. When the frequency of input signal is 6.069 MHz, and the sampling frequency is 40 MHz, the signal to noise and distortion (SNDR) is 70.3 dB, the effective number of bits is 11.39 bit. Project supported by the National Natural Science Foundation of China (Nos. 61234002, 61322405, 61306044, 61376033), the National High-Tech Program of China (No. 2013AA014103), and the Opening Project of Science and Technology on Reliability Physics and Application Technology of Electronic Component Laboratory (No. ZHD201302).

  7. MEMS-based redundancy ring for low-noise millimeter-wave front-end

    Science.gov (United States)

    Pons, Patrick; Dubuc, David; Flourens, Federic; Saddaoui, Mohammad; Melle, Samuel; Tackacs, Alex; Tao, Junwu; Aubert, Herve; Boukabache, Ali; Paillot, T.; Blondy, Pierre; Vendier, Olivier; Grenier, Katia M.; Plana, Robert

    2004-08-01

    This paper reports on the investigation of the potentialities of the MEMS technologies to develop innovative microsystem for millimetre wave communication essentially for space applications. One main issue deals with the robustness and the reliability of the equipment as it may difficult to replace or to repair them when a satellite has been launched. One solution deals with the development of redundancy rings that are making the front end more robust. Usually, the architecture of such system involves waveguide or diode technologies, which present severe limitations in term of weight, volume and insertion loss. The concept considered in this paper is to replace some key elements of such system by MEMS based devices (Micromachined transmission lines, switches) in order to optimize both the weight and the microwave performance of the module. A specific technological process has been developed consisting in the fabrication of the devices on a dielectric membrane on air suspended in order to improve the insertion loss and the isolation. To prove the concept, building blocks have been already fabricated and measured (i.e micromachined transmission and filter featuring very low insertion loss, single pole double through circuits to address the appropriate path of the redundancy ring). We have to outline that MEMS technology have allowed a simplification of the architecture and a different system partitioning which gives more degree of freedom for the system designer. Furthermore, it has been conducted an exhaustive reliability study in order to identify the failure mechanisms. Again, from the results obtained, we have proposed an original topology for the SPDT circuit that takes into account the reliability behaviour of the MEMS devices and that allow to prevent most of the failure mechanisms reported so far (mainly related to the dielectric charging effect). Finally, the active device (millimetre wave low noise amplifier) will be reported on the MEMS based chip using

  8. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy.

    Science.gov (United States)

    Valente, Virgilio; Demosthenous, Andreas

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) channels suitable for both bipolar and tetrapolar electrical impedance spectroscopy (EIS) analysis. Each VR channel occupies an area of 0.48 mm 2 , is capable of an operational bandwidth of 8 MHz and a linear gain in the range between -6 dB and 42 dB. The gain of the CR channel can be set to 10 kΩ, 50 kΩ or 100 kΩ and is capable of 80-dB dynamic range, with a very linear response for input currents between 10 nA and 100 μ A. Each CR channel occupies an area of 0.21 mm 2 . The chip consumes between 530 μ A and 690 μ A per channel and operates from a 1.8-V supply. The chip was used to measure the impedance of capacitive interdigitated electrodes in saline solution. Measurements show close matching with results obtained using a commercial impedance analyser. The chip will be part of a fully flexible and configurable fully-integrated dual-mode EIS system for impedance sensors and bioimpedance analysis. PMID:27463721

  9. Interference Rejection in UWB LNA using Front-End Triode MOSFET

    Directory of Open Access Journals (Sweden)

    H. Rezaei

    2013-07-01

    Full Text Available In this study, an Ultra Wide Band Low Noise Amplifier (UWB LNA with new input stage for interference rejection is presented. In this scheme, a common gate front end MOS device in triode mode is used to reject in-band and out-band interferences. Furthermore, advantage of weak inversion mode of MOS device is used. While this stage has no DC power consumption, it is possible to easily reject in band and out band interferences with 12.5 and 9.2 dB, respectively. In order to increase power gain of the circuit two stages are added as an amplifier to the circuit. Also, in order to improve the Noise Figure (NF and bandwidth of the circuit, the advantages of thermal noise cancellation technique in the second stage and the series-peaking method in the output buffer are used. The circuit is design in 0.18 μm technology. Simulation results show peak gain of 17.6 dB in the low band (3.1-4.75 GHz and 15.6 dB in the high band (6.1-10.6 GHz. Minimum NF in mentioned frequency band is 3 and 2.3 dB, respectively. Hence, this circuit rejects in band and out band interferences 15.6 and 11.5 dB, respectively, while UWB LNA consumes 16 mW DC power from 1.8 V. The s11 is less than -9.6 dB over entire bandwidth since worst value of IIP3 over entire bandwidth is -14 dBm which occurs at 10.6 GHz.

  10. Integrated high-voltage inductive power and data-recovery front end dedicated to implantable devices.

    Science.gov (United States)

    Mounaim, F; Sawan, M

    2011-06-01

    In near-field electromagnetic links, the inductive voltage is usually much larger than the compliance of low-voltage integrated-circuit (IC) technologies used for the implementation of implantable devices. Thus most integrated power-recovery approaches limit the induced signal to low voltages with inefficient shunt regulation or voltage clipping. In this paper, we propose using high-voltage (HV) complementary metal-oxide semiconductor technology to fully integrate the inductive power and data-recovery front end while adopting a step-down approach where the inductive voltage is left free up to 20 or 50 V. The advantage is that excessive inductive power will translate to an additional charge that can be stored in a capacitor, instead of shunting to ground excessive current with voltage limiters. We report the design of two consecutive HV custom ICs-IC1 and IC2-fabricated in DALSA semiconductor C08G and C08E technologies, respectively, with a total silicon area (including pads) of 4 and 9 mm(2), respectively. Both ICs include HV rectification and regulation; however, IC2 includes two enhanced rectifier designs, a voltage-doubler, and a bridge rectifier, as well as data recovery. Postlayout simulations show that both IC2 rectifiers achieve more than 90% power efficiency at a 1-mA load and provide enough room for 12-V regulation at a 3-mA load and a maximum-available inductive power of 50 mW only. Successful measurement results show that HV regulators provide a stable 3.3- to 12-V supply from an unregulated input up to 50 or 20 V for IC1 and IC2, respectively, with performance that matches simulation results. PMID:23851479

  11. Vacuum upgrade and enhanced performances of the double imaging electron/ion coincidence end-station at the vacuum ultraviolet beamline DESIRS

    Science.gov (United States)

    Tang, Xiaofeng; Garcia, Gustavo A.; Gil, Jean-François; Nahon, Laurent

    2015-12-01

    We report here the recent upgrade of the SAPHIRS permanent photoionization end-station at the DESIRS vacuum ultraviolet beamline of synchrotron SOLEIL, whose performances have been enhanced by installing an additional double-skimmer differential chamber. The smaller molecular beam profile obtained at the interaction region has increased the mass resolution of the double imaging photoelectron photoion coincidence (i2PEPICO) spectrometer, DELICIOUS III, installed in the photoionization chamber of the SAPHIRS endstation, by a factor of two, to M/ΔM ˜ 1700 (FWHM). The electron kinetic energy resolution offered by the velocity map imaging (VMI) part of the spectrometer has been improved down to 2.8% (ΔE/E) as we show on the N2 photoionization case in the double skimmer configuration. As a representative example of the overall state-of-the-art i2PEPICO performances, experimental results of the dissociation of state-selected O2+ (B 2 ∑ g - , v+ = 0-6) molecular ions performed at the fixed photon energy of hν = 21.1 eV are presented.

  12. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    Science.gov (United States)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  13. A low power front-end architecture for SiPM readout with integrated ADC and multiplexed readout

    Science.gov (United States)

    Sacco, I.; Fischer, P.; Ritzert, M.; Peric, I.

    2013-01-01

    Silicon Photo-Multiplier (SiPM) detectors are becoming widely used for optical photon and, in conjunction with suited scintillators, for gamma detection in both medical imaging and particle physics experiments. The spatial resolution can be improved by using smaller SiPMs with a corresponding increase in front-end channels density. The timing resolution of the whole system is a function of the detector parameters and of the characteristics of the front-end electronics. We present a low power front-end readout architecture which allows reading out several SiPMs though a single line in order to maximize the number of SiPMs. The design offers good timing performance and includes a simple charge digitizer in every channel. Four different single-ended channel designs have been designed, submitted for fabrication and characterized electronically and with SiPMs. The timing performance is obtained by using a low input impedance, precise threshold setting of a leading edge discriminator and a programmable input dc potential to set the SiPM HV bias on a channel per channel basis. Programmable low- and high-pass filters should allow reducing baseline fluctuations and noise. A simple ADC is implemented by first integrating the signal current and then discharging it at a constant rate until the baseline is reached again. The current consumption of the single channel is typically less than 10 mA. The time and energy information are sent out on a single wire. In order to keep as low as possible the output cabling the signals from different channels can be multiplexed on the same cable. The processing of these signals (extraction of time, ADC amplitude determination and channel number decoding) is performed by an external FPGA. The overall architecture, the front-end designs, and measurements with SiPMs are presented.

  14. 40 CFR Table 6 to Subpart U of... - Group 1 Batch Front-End Process Vents and Aggregate Batch Vent Streams-Monitoring, Recordkeeping...

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Group 1 Batch Front-End Process Vents and Aggregate Batch Vent Streams-Monitoring, Recordkeeping, and Reporting Requirements 6 Table 6 to... 6 to Subpart U of Part 63—Group 1 Batch Front-End Process Vents and Aggregate Batch Vent...

  15. Front-end electronics for PWO-based PHOS calorimeter of ALICE

    International Nuclear Information System (INIS)

    The electromagnetic Photon Spectrometer (PHOS) of ALICE consists of five modules with 56x64 PWO crystals, operated at -25 oC. Glued to each crystal are APD diodes which amplify a lightyield of 4.4 photoelectrons/MeV, followed by charge-sensitive pre-amplifiers with a charge conversion gain of ca. 1 V/pC. We describe our new 32-channel shaper/digitizer and readout electronics for gain-programmable photodiodes. These Front-End Electronics (FEE) cards are installed below the crystals in an isolated warm volume in geometrical correspondence to 2x16 crystal rows per card. With a total detector capacitance of 100 pF and a noise level of 3 MeV, the FEEs cover a 14 bit dynamic range from 5 MeV to 80 GeV. The low noise level is achieved by operating the APDs and preamplifiers at low temperature and by applying a relatively long shaping time of 1 μs. The offline timing resolution, obtained via a Gamma-2 fit is less than 2 ns. The second-order, dual-gain shapers produce semi-Gaussian output for 10 bit ADCs with embedded multi-event buffers. A Readout Control Unit (RCU) masters data readout with address-mapped access to the event-buffers and controls registers via a custom bus which interconnects up to 14 FEE cards. Programmable bias voltage controllers on the FEE cards allow for very precise gain adjustment of each individual APD. Being co-designed with the TRU trigger cards, each FEE card generates eight fast signal sums (2x2 crystals) as input to the TRU. FPGA-based algorithms generate level-0 and level-1 trigger decisions at 40 MHz and allow PHOS also to operate in self-triggered mode. Inside each PHOS module there are 112 FEE and 8 TRU cards which dissipate ca. 1 kW heat which is extracted via a water cooling system

  16. Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

    International Nuclear Information System (INIS)

    A Very-Front-End (VFE) card is an important part of the on-detector read-out electronics of the CMS (Compact Muon Solenoid) electromagnetic calorimeter that is made of ∼ 76.000 radiation hard scintillating crystals PbWO4 and operates on the Large Hadron Collider (LHC) at CERN. Almost 16.000 VFE cards that shape, amplify and digitize incoming signals from photodetectors generated by interacting particles. Since any maintenance of any part of the calorimeter is not possible during the 10-year lifetime of the experiment, the extensive screening program was employed throughout the whole manufacture process. As a part of readout electronics quality assurance program, the systems for burn-in and precise calibration of the VFE boards were developed and successfully used at IPN Lyon. In addition to functionality tests, all relevant electrical properties of each card were measured and analyzed in detail to obtain their full characterization and to build a database with all required parameters which will serve for the initial calibration of the whole calorimeter. In order to evaluate the calorimeter performance and also to deliver the most precise calibration constants, several fully equipped super-modules were extensively studied and calibrated during the test beam campaigns at CERN. As an important part of these tests, accurate studies of the electronics noise and relative gains, which are needed for measurement in high energy range, were carried out to optimize amplitude reconstruction procedure and thus improve the precision of the calorimeter energy determination. The heart of the thesis consists of the calibration of all VFE boards, including optimization of the laboratory calibration system and precise analysis of measured values to delivered desired calibration constants. The second half of the thesis is focused on the accurate evaluation and optimization of the read-out electronics in real data taking conditions. The results obtained in the laboratory at IPN Lyon

  17. Front-end Design and Implementation of HDMI%HDMI前端设计与实现

    Institute of Scientific and Technical Information of China (English)

    胡湘宏; 蔡述庭; 熊晓明; 詹瑞典

    2015-01-01

    随着高清影音时代的到来,新的高清多媒体接口技术也渐趋成熟。本文研究了高清多媒体接口的编码和解码功能,并采用硬件描述语言实现高清多媒体接口规范定义的编解码功能。首先对高清多媒体接口的整体信道传输过程进行了分析和分解,并阐述了三个数据周期传输时间及其解码方式的不同。在此基础上对编解码功能进行了模块划分,采用分层及模块复用至顶向下的设计方法。最后通过NC-Verilog仿真工具仿真验证代码功能的正确性。%The arrival of the era of high-definition multimedia, including both video images and sounds, requires new definition and realization of the interface technology. The encoding and decoding functions of high-definition multimedia interface are studied in this paper. Using the high-definition multimedia interface specification (HDMI), the front-end design of the encoding and decoding functions is implemented with the hardware description language - Verilog. First, we analyzed and decomposed the transmission process of the whole channel in the high-definition multimedia interface, and elaborated the difference of transmit time in three data periods and decoding methods. Second, based on the analysis, we divided the functions into sub-modules and adopted hierarchical and IP-reuse methodology in our implementation process. Finally, we tested the correctness of the design implementation with both functional verification and circuit simulation.

  18. Evaluation of the Ride-Through Capability of an Active-Front-End Adjustable Speed Drive under Real Grid Conditions

    DEFF Research Database (Denmark)

    Liserre, Marco; Klumpner, Christian; Blaabjerg, Frede;

    2004-01-01

    Better quality of the input currents, unity power factor and regenerative capability are not the only benefits of equipping an Adjustable Speed Drive (ASD) with an active front-end-stage. Controlling the power inflow may enable also the reduction of the dc-link energy storage, which will then lead...... to the replacement of the electrolytic capacitors with film capacitors, which have lower energy density meaning that the volume is similar, but will increase the ASD lifetime. In these circumstances, operation under unbalanced and distorted supply voltage as well as high dynamic operation of the ASD makes...... the control task more challenging. The aim of this paper is to investigate the ride-through capability of an ASD with active front-end under real grid conditions and in view of the minimum dc-link storage. Experiments validate the theoretical analysis....

  19. Front-end electronics for CsI based charged particle array for the study of reaction dynamics

    Energy Technology Data Exchange (ETDEWEB)

    Jhingan, Akhil, E-mail: akhil@iuac.res.in [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Sugathan, P. [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Kaur, Gurpreet; Kapoor, K. [Department of Physics, Panjab University, Chandigarh 160014 (India); Saneesh, N.; Banerjee, T. [Inter University Accelerator Centre, P.O. Box 10502, New Delhi 110067 (India); Singh, Hardev [Department of Physics, Kurukshetra University, Kurukshetra 136119 (India); Kumar, A.; Behera, B.R. [Department of Physics, Panjab University, Chandigarh 160014 (India); Nayak, B.K. [Nuclear Physics Division, Bhabha Atomic Research Centre, Mumbai 400085 (India)

    2015-06-21

    The characteristics and performance of a new detector system based on CsI(TI) scintillators, and its front-end electronics are presented. The detector system has been developed for the detection of light charged particles to investigate fusion–fission dynamics, and will also serve as ancillary detector for an array of neutron detectors. CsI scintillators are read by photo-diodes. The main feature of the array is its compact and simple high density front-end electronics which includes custom developed low noise charge sensitive preamplifiers (with very low power consumption for operation inside vacuum), NIM differential drivers, and commercially available Mesytec amplifiers with two different time constants for particle identification using a ballistic deficit technique.

  20. A 7-13 GHz low-noise tuned optical front-end amplifier for heterodyne transmission system application

    DEFF Research Database (Denmark)

    Ebskamp, Frank; Schiellerup, Gert; Høgdal, Morten

    1991-01-01

    The authors present a 7-13 GHz low-noise bandpass tuned optical front-end amplifier, showing 46±1 dBΩ transimpedance, and a noise spectral density of about 12 pA/√Hz. This is the first time such a flat response and such low noise were obtained simultaneously at these frequencies, without any...... further equalization. A new lay-out technique enabled close monitoring of each manufacturing step, and excellent agreement between the measurements and simulations was observed. The front-end was used in an optical 2.5 Gb/s coherent CPFSK continuous phase frequency shift keying system experiment......, resulting in a sensitivity of -41.7 dBm at a bit error rate of 10-9...

  1. Development of a data management front-end for use with a LANDSAT-based information system

    Science.gov (United States)

    Turner, B. J.

    1982-01-01

    The development and implementation of a data management front-end system for use with a LANDSAT based information system that facilitates the processsing of both LANDSAT and ancillary data was examined. The final tasks, reported on here, involved; (1) the implementation of the VICAR image processing software system at Penn State and the development of a user-friendly front-end for this system; (2) the implementation of JPL-developed software based on VICAR, for mosaicking LANDSAT scenes; (3) the creation and storage of a mosiac of 1981 summer LANDSAT data for the entire state of Pennsylvania; (4) demonstrations of the defoliation assessment procedure for Perry and Centre Counties, and presentation of the results at the 1982 National Gypsy Moth Review Meeting, and (5) the training of Pennsylvania Bureau of Forestry personnel in the use of the defoliation analysis system.

  2. Low power analog front-end electronics in deep submicrometer CMOS technology based on gain enhancement techniques

    International Nuclear Information System (INIS)

    This paper evaluates the design of front-end electronics in modern technologies to be used in a new generation of heavy ion detectors—HYDE (FAIR, Germany)—proposing novel architectures to achieve high gain in a low voltage environment. As conventional topologies of operational amplifiers in modern CMOS processes show limitations in terms of gain, novel approaches must be raised. The work addresses the design using transistors with channel length of no more than double the feature size and a supply voltage as low as 1.2 V. A front-end system has been fabricated in a 90 nm process including gain boosting techniques based on regulated cascode circuits. The analog channel has been optimized to match a detector capacitance of 5 pF and exhibits a good performance in terms of gain, speed, linearity and power consumption

  3. Inelastic X-ray Scattering Beamline Collaborative Development Team Final Report

    International Nuclear Information System (INIS)

    This is the final report for the project to create a beam line for inelastic x-ray scattering at the Advanced Photon Source. The facility is complete and operating well, with spectrometers for both high resolution and medium resolution measurements. With the advent of third generation synchrotron sources, inelastic x-ray scattering (IXS) has become a valuable technique to probe the electronic and vibrational states of a wide variety of systems of interest in physics, chemistry, and biology. IXS is a weak probe, and experimental setups are complex and require well-optimized spectrometers which need a dedicated beamline to function efficiently. This project was the result of a proposal to provide a world-class, user friendly beamline for IXS at the Advanced Photon Source. The IXS Collaborative Development Team (IXS-CDT) was formed from groups at the national laboratories and a number of different universities. The beamline was designed from the front end to the experimental stations. Two different experimental stations were provided, one for medium resolution inelastic x-ray scattering (MERIX) and a spectrometer for high resolution inelastic x-ray scattering (HERIX). Funding for this project came from several sources as well as the DOE. The beamline is complete with both spectrometers operating well. The facility is now open to the general user community and there has been a tremendous demand to take advantage of the beamline's capabilities. A large number of different experiments have already been carried out on the beamline. A detailed description of the beamline has been given in the final design report (FDR) for the beamline from which much of the material in this report came. The first part of this report contains a general overview of the project with more technical details given later.

  4. Skiroc : a Front-end Chip to Read Out the Imaging Silicon-Tungsten Calorimeter for ILC

    OpenAIRE

    Bouchel, M.; El Berni, M.; Fleury, J.; De La Taille, C.; Martin-Chassard, G.; Raux, L.; Wicek, F.; Bohner, G; Gay, Pascal; Lecoq, J.; Manen, S.; Royer, L.

    2007-01-01

    CALICE Collaboration EUDET Collaboration This abstract describes the new front end ASIC designed for the silicon tungsten electromagnetic calorimeter called SKIROC. This new chip embeds the main features required for the ILC final detector. Integration and low-power consumption of the read-out ASIC for the International Linear Collider (ILC) 82-million-channel W-Si calorimeter must reach an unprecedented level as it will be embedded inside the detector. Uniformity and dynamic range perform...

  5. A segmented hybrid photon detector with integrated auto-triggering front-end electronics for a PET scanner

    International Nuclear Information System (INIS)

    We describe the design, fabrication and test results of a segmented hybrid photon detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a positron emission tomograph. Emphasis is put on the PET-specific features of the device. The detector has been fabricated in the photocathode facility at CERN

  6. Web前端的安全防护漫谈%Web front-end Security Protection Discussion

    Institute of Scientific and Technical Information of China (English)

    王广

    2013-01-01

    With the rapid spread ofweb application services, the threats to the web application are very seriousat the same time. Recent years many famous Internetwebsite was be attacked, and most of them focused on the weak protection of web front-end. Web front-end protection has some special characteristic itself, and has been a important branch of web application security. This article introduced some root causes and major threats for web front-end security, and then investigates some principles of web front-end attack. Based on the analysis and comparison, itproposed somesecurity protection methods for the popular attacks.%  Web应用普及的同时,也导致了Web面临了越来越严重的安全威胁.近年来各大网站频繁受到攻击,其中很多攻击针对以前比较薄弱的Web前端.Web前端的安全防护具有自身的独特性,并已经成为Web应用安全的一个重要分支.首先研究了Web前端安全隐患产生的根源以及面临的主要威胁,并介绍了一些web前端攻击方式的原理.在分析和比较的基础上,针对当前主流的攻击提出一些安全防护的解决方法.

  7. Dynamics of internal R&D stakeholders in the Fuzzy Front-End of breakthrough engineering projects

    OpenAIRE

    Hooge, Sophie; Dalmasso, Cédric

    2015-01-01

    International audience In competitive industries, intensive innovation is a recognized necessity (Wheelwright and Clark, 1992; Le Masson et al., 2010). One success factor of breakthrough R&D projects lies in the knowledge articulation between innovation definition phases, composed of fuzzy front-end (FFE) and innovative new product development (NPD) stages (Koen et al, 2002; Cooper et al, 2001), and industrial development processes. Then, central issue for innovation projectsmanagers becom...

  8. Silicon-Based RFIC Multi-band Transmitter Front Ends for Ultra-Wideband Communications and Sensor Applications

    OpenAIRE

    Zhao, Jun

    2007-01-01

    Fully integrated Ultra-Wideband (UWB) RFIC transmitters are designed in Si-based technologies for applications such as wireless communications or sensor networks. UWB technology offers many unique features such as broad bandwidth, low power, accurate position location capabilities, etc. This research focuses on the RFIC front-end hardware design issues for proposed UWB transmitters. Two different methods of multiband frequency generation ----- using switched capacitor VCO tanks and frequency ...

  9. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  10. Web front-end Security Protection Discussion%Web前端的安全防护漫谈

    Institute of Scientific and Technical Information of China (English)

    王广

    2013-01-01

      Web应用普及的同时,也导致了Web面临了越来越严重的安全威胁.近年来各大网站频繁受到攻击,其中很多攻击针对以前比较薄弱的Web前端.Web前端的安全防护具有自身的独特性,并已经成为Web应用安全的一个重要分支.首先研究了Web前端安全隐患产生的根源以及面临的主要威胁,并介绍了一些web前端攻击方式的原理.在分析和比较的基础上,针对当前主流的攻击提出一些安全防护的解决方法.%With the rapid spread ofweb application services, the threats to the web application are very seriousat the same time. Recent years many famous Internetwebsite was be attacked, and most of them focused on the weak protection of web front-end. Web front-end protection has some special characteristic itself, and has been a important branch of web application security. This article introduced some root causes and major threats for web front-end security, and then investigates some principles of web front-end attack. Based on the analysis and comparison, itproposed somesecurity protection methods for the popular attacks.

  11. Workshop on physics at the first muon collider and front-end of a muon collider: A brief summary

    Energy Technology Data Exchange (ETDEWEB)

    Geer, S.

    1998-02-01

    In November 1997 a workshop was held at Fermilab to explore the physics potential of the first muon collider, and the physics potential of the accelerator complex at the `front-end` of the collider. An extensive physics program emerged from the workshop. This paper attempts to summarize this physics program and to identify the main conclusions from the workshop. 14 refs., 1 fig., 5 tabs.

  12. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  13. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with X-ray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  14. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  15. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  16. Controller design and implementation of a three-phase Active Front End using SiC based MOSFETs

    DEFF Research Database (Denmark)

    Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

    2015-01-01

    The design and implementation of a three phase Active Front End for power factor correction purposes using fast switching SiC based MOSFETs is presented. Possible applications are within the drives- and renewable energy sector. The controller is designed and implemented in the synchronous rotating...... reference frame. Besides the theoretical modelling the controller is optimized through simulations and implemented on a low cost DSP processor using a visual programming language - here MATLAB/SIMULINK - with automatic code generation for embedded targets. The paper illustrates the advantages of power...

  17. Low noise 4-channel front end ASIC with on-chip DLL for the upgrade of the LHCb Calorimeter

    Science.gov (United States)

    Picatoste, E.; Bigbeder-Beau, C.; Duarte, O.; Garrido, L.; Gascon, D.; Grauges, E.; Lefrançois, J.; Machefert, F.; Mauricio, J.; Vilasis, X.

    2015-04-01

    An integrated circuit for the Upgrade of the LHCb Calorimeter front end electronics is presented. It includes four analog channels, a Delay Locked Loop (DLL) for signal phase synchronization for all channels and an SPI communication protocol based interface. The analog circuit is based on two fully differential interleaved channels with a switched integrator to avoid dead time and it incorporates dedicated solutions to achieve low noise, linearity and spill-over specifications. The included DLL is capable of shifting the phase of the LHC clock (25 ns) in steps of 1 ns. The selected technology is AMS SiGe BiCMOS 0.35 um.

  18. Collaboration with Customers in Network-Based Innovation Processes - Network and relations in the Fuzzy Front-End

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj

    Abstract There is a general tendency that product life cycles get shortened and there is an increased customer demand for individualized products. These trends put pressure on companies to continuously bring new products to the market (Cooper & Kleinschmidt 1987a)   Further it is a tendency...... by Eric von Hippel to a network innovation perspective and discusses the different concepts as a method when identifying industrial customers for network based innovation. This is done in order to provide insights in how the Fuzzy Front-End of network based innovation can become more efficient.  ...

  19. Building Blocks for a 24 GHz Phased-Array Front-End in CMOS Technology for Smart Streetlights

    OpenAIRE

    Wang, Ban; Tasselli, Gabriele; Botteron, Cyril; Farine, Pierre-André

    2014-01-01

    According to a recent European Union report, lighting represents a significant share of electricity costs and the goal of reducing lighting power consumption by 20% demands the coupling of light-emitting diode (LED) lights with smart sensors and communication networks. In this context, this paper proposes the integration of these three elements into a smart streetlight, incorporating a 24 GHz phased-array (Ph-A) front-end (FE). The main building blocks of this Ph-A FE integrated in a low cost...

  20. Design of a Constant Fraction Discriminator for the VFAT3 front-end ASIC of the CMS GEM detector

    CERN Document Server

    Loddo, Flavio

    2015-01-01

    In this work the design of a Constant Fraction Discriminator (CFD) to be used in the VFAT3 chip, currently under design for the read-out of the Triple-Gem detectors of the CMS experiment, is described. Simulations show that it is possible to extend the front-end shaping time in order to fully integrate the GEM detector signal charge whilst maintaining optimal timing resolution using the CFD technique. A prototype chip containing 8 CFDs was implemented in 130 nm CMOS technology to prove the effectiveness of the proposed architecture before its integration in the VFAT3 chip. The CFD design and test results will be shown.

  1. Utilizing a Novel Approach at the Fuzzy Front-End of New Product Development: A Case Study in a Flexible Fabric Supercapacitor

    OpenAIRE

    Gwo-Tsuen Jou; Benjamin J. C. Yuan

    2016-01-01

    The fuzzy front-end plays a most crucial part in new product development (NPD), leading to the success of product development and product launch in the market. This study proposes a novel method, TTRI_MP, by combining Crawford and Di Benedetto’s model and Cooper’s model, to strengthen the management of the fuzzy front-end. The proposed method comprises four stages: market exploration and technology forecasting, idea generation and segmentation, portfolio analysis and technology roadmapping (T...

  2. A hearing aid on-chip system based on accuracy optimized front- and back-end blocks

    International Nuclear Information System (INIS)

    A hearing aid on-chip system based on accuracy optimized front- and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front- and back-end blocks, respectively, so as to alleviate the nonlinearity distortion caused by the output swing. By using the technique, the accuracy of the whole hearing aid system can be significantly improved. The prototype chip has been designed with a 0.13 μm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 Ω loudspeaker with a normalized output level of 300 mVp-p, the total harmonic distortion reached about −60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 μVrms. (semiconductor integrated circuits)

  3. A hearing aid on-chip system based on accuracy optimized front- and back-end blocks

    Science.gov (United States)

    Fanyang, Li; Hao, Jiang

    2014-03-01

    A hearing aid on-chip system based on accuracy optimized front- and back-end blocks is presented for enhancing the signal processing accuracy of the hearing aid. Compared with the conventional system, the accuracy optimized system is characterized by the dual feedback network and the gain compensation technique used in the front- and back-end blocks, respectively, so as to alleviate the nonlinearity distortion caused by the output swing. By using the technique, the accuracy of the whole hearing aid system can be significantly improved. The prototype chip has been designed with a 0.13 μm standard CMOS process and tested with 1 V supply voltage. The measurement results show that, for driving a 16 Ω loudspeaker with a normalized output level of 300 mVp-p, the total harmonic distortion reached about -60 dB, achieving at least three times reduction compared to the previously reported works. In addition, the typical input referred noise is only about 5 μVrms.

  4. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Liu, H., E-mail: newhui.cn@gmail.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Gan, B., E-mail: shadow524@163.com [Institute of Microelectronics, School of Computer S and T, Northwestern Polytechnical University, Xi’an (China); Hu, Y., E-mail: Yann.Hu@ires.in2p3.fr [Institut Pluridisciplinaire Hubert Curien, IN2P3/CNRS/UDS, Strasbourg (France)

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e{sup −} to 180,000e{sup −}, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e{sup −} at zero farad plus 5.4 e{sup −} per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  5. A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

    Science.gov (United States)

    Liu, Wei; Wei, Tingcun; Li, Bo; Yang, Lifeng; Xue, Feifei; Hu, Yongcai

    2016-05-01

    This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of -1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm2. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

  6. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    Science.gov (United States)

    Gao, W.; Liu, H.; Gan, B.; Hu, Y.

    2014-05-01

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e- to 180,000e-, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e- at zero farad plus 5.4 e- per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel.

  7. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  8. Single Event Effect Hardness for the Front-end ASICs Applied in BGO Calorimeter of DAMPE Satellite

    CERN Document Server

    Gao, Shan-Shan; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray study with a primary scientific goal of indirect search of dark matter particles. As a crucial sub-detector, BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effect (SEE) a probable threat to reliability. In order to evaluate the SEE sensitivity of the chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration regist...

  9. Characteristics of a multichannel low-noise front-end ASIC for CZT-based small animal PET imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design and characteristics of a novel low-noise front-end readout application-specific integrated circuit dedicated to CdZnTe (CZT) detectors for a small animal PET imaging system. A low-noise readout method based on the charge integration and the delayed peak detection is proposed. An eight-channel front-end readout prototype chip is designed and implemented in a 0.35 μm CMOS process. The die size is 2.3 mm ×2.3 mm. The prototype chip is tested in different methods including electronic test, energy spectrum test and irradiation test. The input range of the ASIC is from 2000e− to 180,000e−, reflecting the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 mV/fC at the shaping time of 1 μs. The best test result of the equivalent noise charge (ENC) is 58.9 e− at zero farad plus 5.4 e− per picofarad. The nonlinearity and the crosstalk are less than 3% and less than 2%, respectively, at the room temperature. The static power dissipation is about 3 mW/channel

  10. Development of C-Band RF Front-end of Precision Coherent Mono-pulse C-Band Radar

    Directory of Open Access Journals (Sweden)

    Arun Kumar Ray

    2014-07-01

    Full Text Available A compact, robust and high performance front-end of a radar receiver is designed and demonstrated in this paper. The important parameters like noise figure, sensitivity, selectivity, dynamic range and tracking range are superior to that of the existing systems and facilitate online monitoring of the above important parameters. The gain and phase matching facility are incorporated. The local oscillator is integrated within the module which in turn reduces the losses as compare with the existing local oscillator, placed in the instrumentation cabin. The frequency, amplitude, delay between skin and transponder frequency can be controlled remotely by computer program. Therefore, the mixed mode operation (skin and transponder of radar receiver is possible. Moreover, the SPDT switch is integrated in the same module for RF simulation to facilitate the three channel mono-pulse receiver calibration, receiver health monitoring and range calibration of precision coherent mono-pulse C-band radar. The components used are monolithic microwave integrated circuit based technologies with superior specifications, makes the total module miniaturized and reduced the hardware complications. The total power consumption is much less and improves the overall performance than the existing front-end.Defence Science Journal, Vol. 64, No. 4, July 2014, pp. 358-365, DOI:http://dx.doi.org/10.14429/dsj.64.4245 

  11. Inductorless Ultra-Wide Band Front-End Chip Design with Noise Cancellation Technology for Wireless Communication Applications 10

    Institute of Scientific and Technical Information of China (English)

    Jhin-fang HUANG; Ming-chun HSU; Ron-yi LIU

    2010-01-01

    An inductorless Ultra-Wide Band (UWB) receiver front-end chip design used in wireless communications for the frequency band of 3.1~4.8 GHz is presented. This homodyne receiver mainly consists of a differential Low Noise Amplifier (LNA) circuit followed by a down-converting mixer. The proposed LNA circuit with a noise canceling resistor is connected to the CMOS device's body to reduce the substrate thermal noise. Simulation and measurement results show that the chip can reduce the front-end Noise Figure (NF) about 0.5dB and achieve the Conversion Gain (CG) of 19.44~21.57 dB and double-sideband NF less than 7.8 dB. Also, the input third-order intercept point (IIP3) is -11 dBm, and the input second-order intercept point (IIP2) is 49 dBm. Fabricated in TSMC 0.18 μm CMOS technology, this chip occupies only 0.167 mm2 and dissipates power 59.2 mW.

  12. 10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

    Institute of Scientific and Technical Information of China (English)

    Fan Chao; Chen Tangsheng; Yang Lijie; Feng Ou; Jiao Shilong; Wu Yunfeng; Ye Yutang

    2009-01-01

    A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.

  13. Development and applications of rectangular box-type explosively bonded structures for high-heat-load beamline components

    Science.gov (United States)

    Shu, D.; Chang, J.; Kuzay, T. M.; Brasher, D. G.

    2001-07-01

    Explosive bonding technology is a good choice to join dissimilar materials, such as 304L stainless steel and GlidCop AL-15, and is used extensively in making the advanced photon source (APS) high-heat-load beamline and front-end components. It is a bonding method in which the controlled energy of a detonating explosive is used to create a metallurgical bond between two or more similar or dissimilar materials. In recent years, special explosive bonding units with rectangular box-type joints were developed for the APS new high-heat-load beamline components. Based on this new technique, the box form of the component could be built in two halves first, then welded together. Therefore, beamline designers have more freedom to optimize the cooling surface geometry.

  14. Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

    Science.gov (United States)

    Kureba, C. O.; Govender, M.; Hofsajer, I.; Ruan, X.; Sandrock, C.; Spoor, M.

    2015-10-01

    The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade.

  15. Performance Trade-Off Analysis Comparing Different Front-End Configurations for a Digital X-ray Imager.

    Science.gov (United States)

    Kuhls-Gilcrist, Andrew; Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2010-10-30

    Performance of indirect digital x-ray imagers is typically limited by the front-end components. Present x-ray-to-light converting phosphors significantly reduce detector resolution due to stochastic blurring and k-fluorescent x-ray reabsorption. Thinner phosphors improve resolution at the cost of lowering quantum detection efficiency (QDE) and increasing Swank noise. Magnifying fiber optic tapers (FOTs) are commonly used to increase the field-of-view of small sensor imagers, such as CMOS, CCD, or electron-multiplying CCD (EMCCD) based detectors, which results in a reduction in detector sensitivity and further reduces the MTF. We investigate performance trade-offs for different front-end configurations coupled to an EMCCD sensor with 8 μm pixels. Six different columnar structured CsI(Tl) scintillators with thicknesses of 100, 200, 350, 500, and 1000 μm type high-light (HL) and a 350 μm type high-resolution (HR) (Hamamatsu) and four different FOTs with magnification ratios (M) of 1, 2.5, 3.3, and 4 were studied using the RQA5 x-ray spectrum. The relative signal of the different scintillators largely followed the relative QDE, indicating their light output per absorbed x-ray was similar, with the type HR CsI emitting 57% of the type HL. The efficiency of the FOTs was inversely proportional to M(2) with the M = 1 FOT transmitting 87% of the incident light. At 5 (10) cycles/mm, the CsI MTF was 0.38 (0.22), 0.33 (0.17), 0.37 (0.19), 0.23 (0.09), 0.19 (0.08), and 0.09 (0.03) for the 100, 200, 350HR, 350, 500, and 1000 μm CsI, respectively and the FOT MTF was 0.89 (0.84), 0.80 (0.72), 0.70 (0.60), and 0.69 (0.37) for M = 1, 2.5, 3.3, and 4, respectively. The 1000, 500, and 350HR μm CsI had the highest DQE for low, medium, and high spatial frequency ranges of 0 to 1.6, 1.6 to 4.5, and 4.5 to 10 cycles/mm, respectively. Larger FOT M resulted in a reduction in DQE. Quantifying performance of different front-end configurations will enable optimal selection of components

  16. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    -end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have...

  17. Practical Limits in the Sensitivity-Linearity Trade-off for Radio Telescope Front Ends in the HF and VHF-low Bands

    CERN Document Server

    Tillman, R H; Brendler, J

    2016-01-01

    Radio telescope front ends must have simultaneously low noise and sufficiently-high linearity to accommodate interfering signals. Typically these are opposing design goals. For modern radio telescopes operating in the HF (3-30 MHz) and VHF-low (30-88 MHz) bands, the problem is more nuanced in that front end noise temperature may be a relatively small component of the system temperature, and increased linearity may be required due to the particular interference problems associated with this spectrum. In this paper we present an analysis of the sensitivity-linearity trade off at these frequencies, applicable to existing commercially-available monolithic microwave integrated circuit (MMIC) amplifiers in single-ended, differential, and parallelized configurations. This analysis and associated findings should be useful in the design and upgrade of front ends for low frequency radio telescopes. The analysis is demonstrated explicitly for one of the better-performing amplifiers encountered in this study, the Mini-Ci...

  18. A low noise front end electronics for micro-channel plate detector with wedge and strip anode

    International Nuclear Information System (INIS)

    A low noise Front End Electronics (FEE) for two-dimensional position sensitive Micro-Channel Plate (MCP) detector has been developed. The MCP detector is based on Wedge and Strip Anode (WSA) with induction readout mode. The WSA has three electrodes, the wedge electrode, the strip electrode, and the zigzag electrode. Then, three readout channels are designed in the Printed Circuit Board (PCB). The FEE is calibrated by a pulse generator from Agilent. We also give an analysis of the charge loss from the CSA. The noise levels of the three channels are less than 1 fC RMS at the shaping time of 200 ns. The experimental result shows that the position resolution of the MCP detector coupled with the designed PCB can reach up to 110 μm

  19. Influence Of Tools Input/Output Requirements On Managers Core Front End Activities In New Product Development

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; Minin, Alberto Di;

    2011-01-01

    The object of analysis of this explorative research is the Fuzzy Front End of Innovation in Product Development, described by those activities going from the opportunity identification to the concept definition. Business scholars have shown that confusion in terms of goals and different ideas about...... and use of such tools and the ways that new product development processes can change accordingly. The starting hypothesis that we test here, using 5 case studies in Italy and Denmark, is that managers have to fully understand the needed input requirements and be aware of potential of such tools, in order...... development process is carried-out. First results show that managers have a low/very low awareness of tools’ inputs/outputs requirements. This gives life to the problem according to which managers cannot select appropriate tools if they do not know their basic characteristics, challenging the opportunity...

  20. Exploiting jump-resonance hysteresis in silicon auditory front-ends for extracting speaker discriminative formant trajectories.

    Science.gov (United States)

    Aono, Kenji; Shaga, Ravi K; Chakrabartty, Shantanu

    2013-08-01

    Jump-resonance is a phenomenon observed in non-linear circuits where the amplitude of the output signal exhibits an abrupt jump when the frequency of the input signal is varied. For [Formula: see text] filters used in the design of analog auditory front-ends (AFEs), jump-resonance is generally considered to be undesirable and several techniques have been proposed in literature to avoid or alleviate this artifact. In this paper we explore the use of jump-resonance based hysteresis in [Formula: see text] band-pass filters for encoding speech formant trajectories. Using prototypes of silicon AFEs fabricated in a 0.5 μm CMOS process, we demonstrate the benefits of the proposed approach for extracting speaker discriminative features. These benefits are validated using speaker recognition experiments where consistent improvements in equal-error-rates (EERs) are achieved using the jump-resonance based features as compared to conventional features.

  1. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  2. A low noise front end electronics for micro-channel plate detector with wedge and strip anode

    Science.gov (United States)

    Hu, K.; Li, F.; Liang, F.; Chen, L.; Jin, G.

    2016-03-01

    A low noise Front End Electronics (FEE) for two-dimensional position sensitive Micro-Channel Plate (MCP) detector has been developed. The MCP detector is based on Wedge and Strip Anode (WSA) with induction readout mode. The WSA has three electrodes, the wedge electrode, the strip electrode, and the zigzag electrode. Then, three readout channels are designed in the Printed Circuit Board (PCB). The FEE is calibrated by a pulse generator from Agilent. We also give an analysis of the charge loss from the CSA. The noise levels of the three channels are less than 1 fC RMS at the shaping time of 200 ns. The experimental result shows that the position resolution of the MCP detector coupled with the designed PCB can reach up to 110 μm.

  3. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Science.gov (United States)

    Fischer, P.; Comes, G.; Krüger, H.

    1999-07-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized.

  4. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    Energy Technology Data Exchange (ETDEWEB)

    Fischer, P. E-mail: fischerp@physik.uni-bonn.de; Comes, G.; Krueger, H

    1999-07-11

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  5. MEPHISTO - a 128-channel front end chip with real time data sparsification and multi-hit capability

    CERN Document Server

    Fischer, P; Krüger, H

    1999-01-01

    The MEPHISTO chip uses a novel binary architecture to achieve a high speed readout for multichannel detectors, like silicon strip detectors or MSGCs. The architecture is an alternative to existing designs with raw data pipelines as are commonly used in particle physics applications. The chip receives 128 digital input signals from an analog front end chip at a rate of up to 80 MHz. The hit pattern is sparsified in real time and only the addresses and interaction times of hits are stored temporarily in FIFOs. Multiple hits per event are possible. A trigger selects interesting events for readout. All other hits are automatically discarded. Untriggered readout at high rates is also possible. The occupied chip area depends on the average data rate which can be very small in many applications. Very compact designs with up to ten times less first level storage can therefore be realized. (author)

  6. Fuzzy Decision Support in the Early Phases of the Fuzzy Front End of Innovation in Product Development

    DEFF Research Database (Denmark)

    Achiche, Sofiane; Appio, Francesco Paolo

    2010-01-01

    The innovation process may be divided into three areas: the fuzzy front end (FFE), the new product development (NPD) process, and commercialization. Every NPD process has a FFE in which products and projects are defined. Companies tend to begin the stages of FFE without a clear definition...... and analysis of the process to go from opportunity identification to concepts, and often they even abort the process or start over. Koen’s Model for the FFE is composed of 5 different phases, the first two being Opportunity Identification and Opportunity Analysis, which are the focus of this paper. Furthermore....... The decision support focuses upon the estimate investment needed for the use of tools during the 2 phases cited above. The generation of FDSMs is carried out automatically using a specialized genetic algorithm applied to learning data obtained from 5 experienced managers from 5 different companies...

  7. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 During the first year of the IBL operation in 2015 a significant increase of the LV current of the front-end chip and the detuning of its parameters (threshold and time-over- threshold) have been observed in relation to the received TID. In this talk , the TID effects in the FE-I4 chip are reported based on studies performed in the laboratory using X-ray and proton irradiation sources for various temperature and irradiation intensity conditions. Based on these results, an operation guideline of the IBL detector is presented.

  8. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    Energy Technology Data Exchange (ETDEWEB)

    Bagliesi, M.G., E-mail: mg.bagliesi@pi.infn.it [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Avanzini, C. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy); Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S. [Department of Physics, University of Siena and INFN, Via Roma 56, 53100 Siena (Italy); Morsani, F. [INFN Sezione di Pisa, Edificio C-Polo Fibonacci Largo Bruno Pontecorvo 3, 56127 Pisa (Italy)

    2011-06-15

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  9. Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The Large Hadron Collider will be upgraded to provide instantaneous luminosity $L=5\\times10^{34}\\,\\mbox{cm}^{-2}\\mbox{s}^{-1}$, leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20$\\,\\mu$s in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of $p_{T}\\sim25\\,$GeV, which will be of great benefit to the future physics programme of ATLAS

  10. Web前端开发技术研究%Research on Web Front-End Development Technology

    Institute of Scientific and Technical Information of China (English)

    魏娜

    2011-01-01

    Expounds the Web front-end development related technologies, focusing on development technology and standards based on the Web browser programming, including HTML/XHTML, CSS, DOM, JavaScript, cross browser development, Firefox extension and Web site design and maintenance%阐述Web前端开发相关技术等.主要聚焦于基于Web浏览器编程的前端开发技术和标准,内容包括HTML/XHTML、层叠样式表(CSS)、文档对象模型(DOM),JavaScript、跨浏览器开发、Firefox扩展开发以及Web站点设计与维护等。

  11. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm3, the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  12. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    International Nuclear Information System (INIS)

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  13. Visualization for Hyper-Heuristics. Front-End Graphical User Interface

    Energy Technology Data Exchange (ETDEWEB)

    Kroenung, Lauren [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2015-03-01

    Modern society is faced with ever more complex problems, many of which can be formulated as generate-and-test optimization problems. General-purpose optimization algorithms are not well suited for real-world scenarios where many instances of the same problem class need to be repeatedly and efficiently solved because they are not targeted to a particular scenario. Hyper-heuristics automate the design of algorithms to create a custom algorithm for a particular scenario. While such automated design has great advantages, it can often be difficult to understand exactly how a design was derived and why it should be trusted. This project aims to address these issues of usability by creating an easy-to-use graphical user interface (GUI) for hyper-heuristics to support practitioners, as well as scientific visualization of the produced automated designs. My contributions to this project are exhibited in the user-facing portion of the developed system and the detailed scientific visualizations created from back-end data.

  14. A multifunctional switched-capacitor programmable gain amplifier for high-definition video analog front-ends

    Science.gov (United States)

    Hong, Zhang; Jie, Zhang; Mudan, Zhang; Xue, Li; Jun, Cheng

    2015-03-01

    A multifunctional programmable gain amplifier (PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends (AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter (ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter (DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18-μm process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of -220 to 220 mV while consuming 10.1 mA from a 1.8 V power supply. Project supported by the National Natural Science Foundation of China (No. 61106027), and the Science and Technology Project of Shanxi Province (No. 2014K05-14).

  15. A multifunctional switched-capacitor programmable gain amplifier for high-definition video analog front-ends

    International Nuclear Information System (INIS)

    A multifunctional programmable gain amplifier (PGA) that provides gain and offset adjusting abilities for high-definition video analog front-ends (AFE) is presented. With a switched-capacitor structure, the PGA also acts as a sample and holder of the analog-to-digital converter (ADC) in the AFE to reduce the power consumption and chip area of the whole AFE. Furthermore, the PGA converts the single-ended video signal into differential signal for the following ADC to reject common-mode noise and interferences. The 9-bit digital-to-analog converter (DAC) for gain and offset adjusting is embedded into the switched capacitor networks of the PGA. A video AFE integrated circuit based on the proposed PGA is fabricated in a 0.18-μm process. Simulation and measurement results show that the PGA achieves a gain control range of 0.90 to 2.34 and an offset control range of −220 to 220 mV while consuming 10.1 mA from a 1.8 V power supply. (paper)

  16. Diagnostic X-Multi-Axis Beamline

    Energy Technology Data Exchange (ETDEWEB)

    Paul, A C

    2000-04-05

    Tomographic reconstruction of explosive events require time resolved multipal lines of sight. Considered here is a four (or eight) line of sight beam layout for a nominal 20 MeV 2000 Ampere 2 microsecond electron beam for generation of x-rays 0.9 to 5 meters from a given point, the ''firing point''. The requirement of a millimeter spatial x-ray source requires that the electron beam be delivered to the converter targets with sub-millimeter precision independent of small variations in beam energy and initial conditions. The 2 usec electron beam pulse allows for four bursts in each line, separated in time by about 500 microseconds. Each burst is divided by a electro-magnetic kicker into four (or eight) pulses, one for each beamline. The arrival time of the four (or eight) beam pulses at the x-ray target can be adjusted by the kicker timing and the sequence that the beams of each burst are switched into the different beamlines. There exists a simple conceptual path from a four beamline to a eight beamline upgrade. The eight line beamline is built up from seven unique types of sub-systems or ''blocks''. The beamline consists of 22 of these functional blocks and contains a total of 455 individual magnets, figure 1. The 22 blocks are inter-connected by a total of 30 straight line inter-block sections (IBS). Beamlines 1-4 are built from 12 blocks with conceptual layout structure shown in figure 2. Beamlines 5-8 are built with an additional 10 blocks with conceptual layout structure shown in figure 3. This beamline can be thought of as looking like a lollipop consisting of a 42 meter long stick leading to a 60 by 70 meter rectangular candy blob consisting of the eight lines of sight. The accelerator providing the electron beam is at the end of the stick and the firing point is at the center of the blob. The design allows for a two stage implementation. Beamlines 1-3 can be installed to provide a tomographic azimuthal resolution of 45

  17. 数字电视前端系统的 IP 化改造%IP Transformation of Digital TV Front-end Systems

    Institute of Scientific and Technical Information of China (English)

    张琪信

    2014-01-01

    With the development of IP technology , traditional digital TV ASI architecture gradually transits to the architecture of IP , to meet the technical requirement of the new business'development .This paper de-scribes the advantages of IP front-end system, and expounds the IP reform of traditional ASI front-end and the guarantee to broadcast's security of front-end IP.%随着IP技术的发展,数字电视前端传统的ASI架构逐渐向IP化架构过渡,以满足新业务拓展的技术要求。介绍数字电视前端系统IP化的优势,重点阐述传统ASI前端的IP化改造方案以及IP前端的播出安全保障措施。

  18. Front-end chip for Silicon Photomultiplier detectors with pico-second Time-of-Flight resolution

    Science.gov (United States)

    Stankova, V.; Briggl, K.; Chen, H.; Gil, A.; Harion, T.; Munwes, Y.; Shen, W.; Schultz-Coulon, H.-C.

    2016-07-01

    A mixed-mode readout Application Specific Integrated Circuit (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM) for medical imaging and particle physics applications. The STiC3 is a 64-channel chip, with fully differential analog front-end for cross-talk and electronic noise immunity. The time and charge information from the SiPM signals are encrypted into two time stamps generated by integrated Time to Digital Converter (TDC) modules with 50 ps time binning. The TDC data is stored in an internal memory and transferred to a PC via a 160 MBit/s serial link using an 8/10 bit encoding. The chip provides an input bias tuning in a range of 0-900 mV to compensate the breakdown voltage variation of individual SiPMs. The TDC jitter together with the digital part is around 37 ps. A Coincidence Time Resolution (CTR) of 213.6 ps FWHM has been obtained with 3.1 × 3.1 × 15m2 LYSO:Ce scintillator crystals and Hamamatsu SiPM matrices (S12643-050CN(X)). Characterization measurements with the chip and its integration into the external plate of the EndoTOFPET-US prototype are presented.

  19. Analog Circuit Design Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

    CERN Document Server

    Roermund, Arthur; Baschirotto, Andrea

    2012-01-01

    The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design.  Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of Low-Voltage Low-Power Data Converters - Chaired by Prof. Anderea Baschirotto, University of Milan-Bicocca Short Range Wireless Front-Ends - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology Power management and DC-DC - Chaired by Prof. M. Steyaert, Katholieke University Leuven Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

  20. Design of a Modular Multilevel Converter as an Active Front-End for a magnet supply application

    CERN Document Server

    Panagiotis, Asimakopoulos; Massimo, Bongiorno

    2015-01-01

    The aim of this work is to describe the general design procedure of a Modular Multilevel Converter (MMC) applied as an Active Front-End (AFE) for a magnet supply for beam accelerators. The dimensioning criteria for the converter and the dc-link capacitance are presented and the grid transformer requirements are set. Considering the converter design, the arm inductance calculation is based on the specifications for the arm-current ripple and the DC-link fault tolerance, but, also, on the limitation of the second harmonic and the second-order LC resonance of the arm current. The module capacitance value is evaluated by focusing on the required switching dynamics and the capacitor-voltage ripple according to a newly proposed graphical method. The loading of each semiconductor in the half bridge is calculated via simulation, indicating the unsymmetrical current distribution. It is concluded that the current distribution for each semiconductor depends on the mode of operation of the converter. The different criter...

  1. Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

    Science.gov (United States)

    Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

    2003-04-01

    This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

  2. Analysis of RF Front-End Performance of Reconfigurable Antennas with RF Switches in the Far Field

    Directory of Open Access Journals (Sweden)

    Insu Yeom

    2014-01-01

    Full Text Available The RF front-end performances in the far-field condition of reconfigurable antennas employing two commonly used RF switching devices (PIN diodes and RF-MEMS switches were compared. Two types of antennas (monopole and slot representing general direct/coupled feed types were used for the reconfigurable antennas to compare the excited RF power to the RF switches by the reconfigurable antenna types. For the switching operation of the antennas, a biasing circuit was designed and embedded in the same antenna board, which included a battery to emphasize the antenna’s adaptability to mobile devices. The measurement results of each reconfigurable antenna (radiation patterns and return losses are presented in this study. The receiving power of the reference antenna was measured by varying the transmitting power of the reconfigurable antennas in the far-field condition. The receiving power was analyzed using the “Friis transmission equation” and compared for two switching elements. Based on the results of these measurements and comparisons, we discuss what constitutes an appropriate switch device and antenna type for reconfigurable antennas of mobile devices in the far-field condition.

  3. Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

    Science.gov (United States)

    Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

    2009-05-01

    A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

  4. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  5. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  6. LHCb: Dynamically Adaptive Header Generator and Front-End Source Emulator for a 100 Gbps FPGA Based DAQ

    CERN Multimedia

    Srikanth, S

    2014-01-01

    The proposed upgrade for the LHCb experiment envisages a system of 500 Data sources each generating data at 100 Gbps, the acquisition and processing of which is a big challenge even for the current state of the art FPGAs. This requires an FPGA DAQ module that not only handles the data generated by the experiment but also is versatile enough to dynamically adapt to potential inadequacies of other components like the network and PCs. Such a module needs to maintain real time operation while at the same time maintaining system stability and overall data integrity. This also creates a need for a Front-end source Emulator capable of generating the various data patterns, that acts as a testbed to validate the functionality and performance of the Header Generator. The rest of the abstract briefly describes these modules and their implementation. The Header Generator is used to packetize the streaming data from the detectors before it is sent to the PCs for further processing. This is achieved by continuously scannin...

  7. A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends

    DEFF Research Database (Denmark)

    Fard, Ali; Andreani, Pietro

    2005-01-01

    A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO...... structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when...... consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz....

  8. A 410 μW, 70 dB SNR high performance analog front-end for portable audio application

    International Nuclear Information System (INIS)

    This paper describes an analog front-end (AFE) intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier (PGA) and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW. (semiconductor integrated circuits)

  9. An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

    International Nuclear Information System (INIS)

    We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

  10. AUTOMOTIVE DIESEL MAINTENANCE 1. UNIT XIX, I--ENGINE TUNE-UP--CUMMINS DIESEL ENGINE, II--FRONT END SUSPENSION AND AXLES.

    Science.gov (United States)

    Minnesota State Dept. of Education, St. Paul. Div. of Vocational and Technical Education.

    THIS MODULE OF A 30-MODULE COURSE IS DESIGNED TO DEVELOP AN UNDERSTANDING OF DIESEL ENGINE TUNE-UP PROCEDURES AND THE DESIGN OF FRONT END SUSPENSION AND AXLES USED ON DIESEL ENGINE EQUIPMENT. TOPICS ARE (1) PRE-TUNE-UP CHECKS, (2) TIMING THE ENGINE, (3) INJECTOR PLUNGER AND VALVE ADJUSTMENTS, (4) FUEL PUMP ADJUSTMENTS ON THE ENGINE (PTR AND PTG),…

  11. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  12. Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications

    Institute of Scientific and Technical Information of China (English)

    胡嵩; 李伟男; 黄煜梅; 洪志良

    2012-01-01

    A fully integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented.It supports SAW-less operation for WCDMA.To improve the linearity in terms of both IP3 and IP2,the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization,current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs.A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO.In addition,a constant-gm biasing with an on-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance.This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13 μm CMOS.The measurement results show that owing to this high-linearity RF front-end,the receiver achieves -6 dBm IIP3 and better than +60 dBm IIP2 for all modes and bands.

  13. Beamline for Schools 2016

    CERN Multimedia

    2016-01-01

    Two teams of high-school students from the UK and Poland had the opportunity to conduct their own experiments at a fully equipped CERN beamline. Two teams of high-school students from the UK and Poland had the opportunity to conduct their own experiments at a fully equipped CERN beamline, after winning the Beamline for Schools competition. The teams, ‘Pyramid Hunters’ from Poland and ‘Relatively Special’ from the United Kingdom, spent 10 days at CERN conducting the experiments they had dreamt up in their winning proposals. The Beamline for Schools competition gives high-school students the chance to run an experiment on a fully equipped CERN beamline, in the same way researchers do at the Large Hadron Collider and other CERN facilities every day. 

  14. WNA's worldwide overview on front-end nuclear fuel cycle growth and health, safety and environmental issues

    International Nuclear Information System (INIS)

    Full text: This paper presents the WNA's worldwide nuclear industry overview on the anticipated growth of the front-end nuclear fuel cycle from uranium mining to conversion and enrichment, and on the related key health, safety and environmental issues (or key HSE issues) and challenges. This paper subsequently puts an emphasis on uranium mining in new producing countries with insufficiently developed regulatory regimes that pose greater HSE concerns. It describes the new WNA policy on uranium mining: Sustaining Global Best Practices in Uranium Mining and Processing - Principles for Managing Radiation, Health and Safety and the Environment, which is an outgrowth of an IAEA cooperation project that closely involved industry and governmental experts in uranium mining from around the world. Given the expansion of nuclear power, world uranium production must grow quickly to meet increasing demand. Production in the major uranium producing countries, such as Canada and Australia, will be expanded, but the most key increases are likely to come from Kazakhstan. In situ leaching (ISL) is expected to represent a greater share of uranium production. Conventional mining is expected to remain dominant. Uranium production is also likely to start in some new countries, mainly in Africa. Conversion facilities will be expanded to cope with rising demand. The most significant feature in enrichment will be the gradual replacement of the older gas diffusion facilities (France and United States) by heavy investment in gas centrifuge facilities. Elsewhere, both Western Europe and Russia will likely expand their existing centrifuge capacities. Investors in the SILEX laser enrichment technology will try to commercialise it within the next five years. No key HSE issues are foreseen for the global expansion of conversion and enrichment. The upgrade of existing plants and new plants are expected to deliver greater HSE performance. One of the most notable improvements arises from the much

  15. Design of millimeter-wave MEMS-based reconfigurable front-end circuits using the standard CMOS technology

    International Nuclear Information System (INIS)

    This paper describes the designs of three reconfigurable CMOS-MEMS front-end components for V-/W-band applications. The suspended MEMS structure is released through post-CMOS micromachining. To achieve circuit reconfigurability, dual-state and multi-state fishbone-beam-drive actuators are proposed herein. The reconfigurable bandstop is fabricated in a 0.35 µm CMOS process with the chip size of 0.765 × 0.98 mm2, showing that the stop-band frequency can be switched from 60 to 50 GHz with 40 V actuation voltage. The measured isolation is better than 38 dB at 60 GHz and 34 dB at 50 GHz, respectively. The bandpass filter-integrated single-pole single-throw switch, using the 0.18 µm CMOS process, demonstrates that insertion loss and return loss are better than 6.2 and 15 dB from 88 to 100 GHz in the on-state, and isolation is better than 21 dB in the off-state with an actuation voltage of 51 V. The chip size is 0.7 × 1.04 mm2. The third component is a reconfigurable slot antenna fabricated in a 0.18 µm CMOS process with the chip size of 1.2 × 1.2 mm2. By utilizing the multi-state actuators, the frequencies of this antenna can be switched to 43, 47, 50.5, 54, 57.5 GHz with return loss better than 20 dB. Those circuits demonstrate good RF performance and are relatively compact by employing several size miniaturizing techniques, thereby enabling a great potential for the future single-chip transceiver.

  16. An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

    Science.gov (United States)

    Edward, Alexander; Chan, Pak Kwong

    This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

  17. 7-GeV advanced photon source beamline initiative: Conceptual design report

    International Nuclear Information System (INIS)

    The DOE is building a new generation 6-7 GeV Synchrotron Radiation Source known as the Advanced Photon Source (APS) at Argonne National Laboratory. This facility, to be completed in FY 1996, can provide 70 x-ray sources of unprecedented brightness to meet the research needs of virtually all scientific disciplines and numerous technologies. The technological research capability of the APS in the areas of energy, communications and health will enable a new partnership between the DOE and US industry. Current funding for the APS will complete the current phase of construction so that scientists can begin their applications in FY 1996. Comprehensive utilization of the unique properties of APS beams will enable cutting-edge research not currently possible. It is now appropriate to plan to construct additional radiation sources and beamline standard components to meet the excess demands of the APS users. In this APS Beamline Initiative, 2.5-m-long insertion-device x-ray sources will be built on four straight sections of the APS storage ring, and an additional four bending-magnet sources will also be put in use. The front ends for these eight x-ray sources will be built to contain and safeguard access to these bright x-ray beams. In addition, funds will be provided to build standard beamline components to meet scientific and technological research demands of the Collaborative Access Teams. The Conceptual Design Report (CDR) for the APS Beamline Initiative describes the scope of all the above technical and conventional construction and provides a detailed cost and schedule for these activities. The document also describes the preconstruction R ampersand D plans for the Beamline Initiative activities and provides the cost estimates for the required R ampersand D

  18. 7-GeV advanced photon source beamline initiative: Conceptual design report

    Energy Technology Data Exchange (ETDEWEB)

    1993-05-01

    The DOE is building a new generation 6-7 GeV Synchrotron Radiation Source known as the Advanced Photon Source (APS) at Argonne National Laboratory. This facility, to be completed in FY 1996, can provide 70 x-ray sources of unprecedented brightness to meet the research needs of virtually all scientific disciplines and numerous technologies. The technological research capability of the APS in the areas of energy, communications and health will enable a new partnership between the DOE and US industry. Current funding for the APS will complete the current phase of construction so that scientists can begin their applications in FY 1996. Comprehensive utilization of the unique properties of APS beams will enable cutting-edge research not currently possible. It is now appropriate to plan to construct additional radiation sources and beamline standard components to meet the excess demands of the APS users. In this APS Beamline Initiative, 2.5-m-long insertion-device x-ray sources will be built on four straight sections of the APS storage ring, and an additional four bending-magnet sources will also be put in use. The front ends for these eight x-ray sources will be built to contain and safeguard access to these bright x-ray beams. In addition, funds will be provided to build standard beamline components to meet scientific and technological research demands of the Collaborative Access Teams. The Conceptual Design Report (CDR) for the APS Beamline Initiative describes the scope of all the above technical and conventional construction and provides a detailed cost and schedule for these activities. The document also describes the preconstruction R&D plans for the Beamline Initiative activities and provides the cost estimates for the required R&D.

  19. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  20. A 5.4mW GPS CMOS quadrature front-end based on a single-stage LNA-mixer-VCO

    DEFF Research Database (Denmark)

    Liscidini, Amtonio; Mazzanti, Andrea; Tonietto, Riccardo;

    2006-01-01

    A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm.......A GPS RF front-end combines the LNA, mixer, and VCO in a single stage and can operate from a 1.2V supply. The chip is implemented in a 0.13um CMOS process and occupies 1.5mm2 active area. It consumes 5.4mW with a 4.8dB NF, 36dB gain, and a P1dB of -31dBm....

  1. Demonstration of a double chirped-pulse-amplification front-end system to improve the temporal contrast at a sub-petawatt laser

    Science.gov (United States)

    Xie, Na; Zhou, Kainan; Huang, Wanqing; Wang, Xiaodong; Sun, Li; Guo, Yi; Li, Qing

    2012-02-01

    The temporal contrast is an important factor affecting the application of ultra-intense and ultra-short lasers. In this paper, we develop a double chirped-pulse-amplification (CPA) front-end system with an intermediate nonlinear temporal pulse filter to improve the temporal contrast at a sub-petawatt Ti:sapphire laser facility, i.e. the super intense laser for experiment on the extremes (SILEX-I). The temporal pulse filter employs cross-polarized wave (XPW) generation to suppress the amplified spontaneous emission (ASE). The design output energy is 320 mJ for the front-end system. The experimental results show that the output energy of the double CPA system is 360 mJ. The ASE pedestal is suppressed significantly and the temporal contrast is improved by around three orders of magnitude.

  2. Characterization of EASIROC as front-end for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

    Energy Technology Data Exchange (ETDEWEB)

    Impiombato, D., E-mail: Domenico.Impiombato@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Giarrusso, S., E-mail: Giarrusso@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Mineo, T., E-mail: Mineo@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Belluso, M.; Billotta, S.; Bonanno, G. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy); Catalano, O. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Grillo, A. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy); La Rosa, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Marano, D. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy); Sottile, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy)

    2013-11-21

    The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (<1%). Our results show that it is suitable as front-end chip for the camera prototype, although, specific modifications are necessary to adopt the device in the final version of the telescope.

  3. Characterization of EASIROC as Front-End for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

    CERN Document Server

    Impiombato, D; Mineo, T; Belluso, M; Billotta, S; Bonanno, G; Catalano, O; Grillo, A; La Rosa, G; Marano, D; Sottile, G

    2013-01-01

    The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (<1%). Our results show that it is suitable as front-end chip for the camera prototype, although, specific modifications are necessary to adopt the device in the final version of the telescope.

  4. Characterization of EASIROC as front-end for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

    Science.gov (United States)

    Impiombato, D.; Giarrusso, S.; Mineo, T.; Belluso, M.; Billotta, S.; Bonanno, G.; Catalano, O.; Grillo, A.; La Rosa, G.; Marano, D.; Sottile, G.

    2013-11-01

    The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (<1%). Our results show that it is suitable as front-end chip for the camera prototype, although, specific modifications are necessary to adopt the device in the final version of the telescope.

  5. The beamlines of ELETTRA and their application to structural biology.

    Science.gov (United States)

    Zanini, F; Lausi, A; Savoia, A

    1999-01-01

    Protein crystallographers are nowadays regular users of synchrotron radiation (SR) facilities for several applications. The goal of majority of users is simply to extract more accurate, higher resolution data from existing crystals; they use monochromatic radiation and the rotation method, in order to get a complete survey of the reciprocal space in a short time. In fact the brilliance of SR is essential, due to the weak scattering power of the samples, and because of their sensibility to radiation damage. Over the last few years, however, a general increase of interest for measurements at multiple wavelengths, which exploit the anomalous dispersion for the phase problem (multiwavelength anomalous diffraction--MAD), has generated the need of intense tuneable sources. For these applications, the emphasis is on accurate measurements of the small differences between the intensities of Bragg reflections at various energies across the absorption edge of an element present in the sample. The macromolecular diffraction beamline at ELETTRA, which is now running routinely since spring 1995, has been designed to provide a high flux--highly collimated tuneable X-rays source in the spectral range between 4 and 25 keV. The radiation source is the 57-pole wiggler, which delivers a very intense radiation up to 25 keV, and is shared and used simultaneously with the small angle X-ray scattering (SAXS) beamline. The front-end filter system has a cut-off energy at about 4 keV. The beamline optics consists of a pseudo-channel-cut double-crystal monochromator followed by a double focusing toroidal mirror. The tunability and the stability of the monochromator allows the user to perform MAD experiments, and for this purpose, a fluorescence probe for the exact calibration of the absorption edge is available on-line. The experimental station is based on an imaging plate area detector from MarResearch, with a sensible area of 345 mm in diameter. A cooled N2-stream is available to cool the

  6. 射频前端强电磁脉冲前门耦合研究%Research on High Power EMP Coupling into RF Front-End Through Front-Door

    Institute of Scientific and Technical Information of China (English)

    李名杰; 谭志良; 耿利飞

    2013-01-01

    针对强电磁脉冲能量经天线进入射频前端的威胁,给出强电磁脉冲环境的评估方法,通过分析天线-射频前端工作原理,提出全频带脉冲耦合能量的理论计算公式.并以中馈天线-短波电台为例,用电磁仿真软件CST实现了天线仿真与前端电路仿真的有机连接,得出前门耦合数据及其影响因素,此仿真方案也为更深入分析耦合效应、验证防护技术提供了良好平台.最后根据仿真为前门防护提出若干意见.%Aiming at the serious threat of high power EMP energy by coupling into RF front-end through antenna,an assessment method of high power EMP environment is presented.Then the theoretical formula of full-band coupling energy is deduced after analyzing coupling mechanism of antenna connected with RF front-end.Taking center-fed antenna connected with shortwave radio as an example,software compute simulation technology (CST) is adopted to achieve the valid association between antenna simulation and circuit simulation and obtain the coupling data and the factors affecting front-door coupling.The simulation program provides an effective platform for further analysis of the coupling effect and validation of protection technology.Finally,some views about front-door protection are proposed.

  7. Measurement of the front-end dead-time of the LHCb muon detector and evaluation of its contribution to the muon detection inefficiency

    CERN Document Server

    AUTHOR|(CDS)2078645; Archilli, F; Auriemma, G; Baldini, W; Bencivenni, G; Bizzeti, A; Bocci, V; Bondar, N; Bonivento, W; Bochin, B; Bozzi, C; Brundu, D; Cadeddu, S; Campana, P; Carboni, G; Cardini, A; Carletti, M; Casu, L; Chubykin, A; Ciambrone, P; Dané, E; De Simone, P; Falabella, A; Felici, G; Fiore, M; Fontana, M; Fresch, P; Furfaro, E; Graziani, G; Kashchuk, A; Kotriakhova, S; Lai, A; Lanfranchi, G; Loi, A; Maev, O; Manca, G; Martellotti, G; Neustroev, P; Oldeman, R G C; Palutan, M; Passaleva, G; Penso, G; Pinci, D; Polycarpo, E; Saitta, B; Santacesaria, R; Santimaria, M; Santovetti, E; Saputi, A; Sarti, A; Satriano, C; Satta, A; Schmidt, B; Schneider, T; Sciascia, B; Sciubba, A; Siddi, B G; Tellarini, G; Vacca, C; Vazquez-Gomez, R; Vecchi, S; Veltri, M; Vorobyev, A

    2016-01-01

    A method is described which allows to deduce the dead-time of the front-end electronics of the LHCb muon detector from a series of measurements performed at different luminosities at a bunch-crossing rate of 20 MHz. The measured values of the dead-time range from 70 ns to 100 ns. These results allow to estimate the performance of the muon detector at the future bunch-crossing rate of 40 MHz and at higher luminosity.

  8. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii

    2013-07-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

  9. The Project-x Injector Experiment: A Novel High Performance Front-end For A Future High Power Proton Facility At Fermilab

    CERN Document Server

    Nagaitsev, S; Johnson, D; Kaducak, M; Kephart, R; Lebedev, V; Mishra, S; Shemyakin, A; Solyak, N; Stanek, R; Yakovlev, V; Ostroumov, P; Li, D; Singh, P; Pande, M; Malhotra, S

    2014-01-01

    A multi-MW proton facility, Project X, has been proposed and is currently under development at Fermilab. We are carrying out a program of research and development aimed at integrated systems testing of critical components comprising the front end of Project X. This program, known as the Project X Injector Experiment (PXIE), is being undertaken as a key component of the larger Project X R&D program. The successful completion of this program will validate the concept for the Project X front end, thereby minimizing a primary technical risk element within Project X. PXIE is currently under construction at Fermilab and will be completed over the period FY12-17. PXIE will include an H- ion source, a CW 2.1-MeV RFQ and two superconductive RF (SRF) cryomodules providing up to 25 MeV energy gain at an average beam current of 1 mA (upgradable to 2 mA). Successful systems testing will also demonstrate the viability of novel front end technologies that are expected find applications beyond Project X.

  10. THE PROJECT-X INJECTOR EXPERIMENT: A NOVEL HIGH PERFORMANCE FRONT-END FOR A FUTURE HIGH POWER PROTON FACILITY AT FERMILAB

    Energy Technology Data Exchange (ETDEWEB)

    Nagaitsev, S.; et al,

    2013-09-25

    A multi-MW proton facility, Project X, has been proposed and is currently under development at Fermilab. We are carrying out a program of research and development aimed at integrated systems testing of critical components comprising the front end of Project X. This program, known as the Project X Injector Experiment (PXIE), is being undertaken as a key component of the larger Project X R&D program. The successful completion of this program will validate the concept for the Project X front end, thereby minimizing a primary technical risk element within Project X. PXIE is currently under construction at Fermilab and will be completed over the period FY12-17. PXIE will include an H* ion source, a CW 2.1-MeV RFQ and two superconductive RF (SRF) cryomodules providing up to 25 MeV energy gain at an average beam current of 1 mA (upgradable to 2 mA). Successful systems testing will also demonstrate the viability of novel front end technologies that are expected find applications beyond Project X.

  11. Development and tests of a new prototype detector for the XAFS beamline at Elettra Synchrotron in Trieste

    CERN Document Server

    Fabiani, S; Baldazzi, G; Bellutti, P; Bertuccio, G; Bruschi, M; Bufon, J; Carrato, S; Castoldi, A; Cautero, G; Ciano, S; Cicuttin, A; Crespo, M L; Santos, M Dos; Gandola, M; Giacomini, G; Giuressi, D; Guazzoni, C; Menk, R H; Niemela, J; Olivi, L; Picciotto, A; Piemonte, C; Rashevskaya, I; Rachevski, A; Rignanese, L P; Sbrizzi, A; Schillani, S; Vacchi, A; Garcia, V Villaverde; Zampa, G; Zampa, N; Zorzi, N

    2016-01-01

    The XAFS beamline at Elettra Synchrotron in Trieste combines X-ray absorption spectroscopy and X-ray diffraction to provide chemically specific structural information of materials. It operates in the energy range 2.4-27 keV by using a silicon double reflection Bragg monochromator. The fluorescence measurement is performed in place of the absorption spectroscopy when the sample transparency is too low for transmission measurements or the element to study is too diluted in the sample. We report on the development and on the preliminary tests of a new prototype detector based on Silicon Drift Detectors technology and the SIRIO ultra low noise front-end ASIC. The new system will be able to reduce drastically the time needed to perform fluorescence measurements, while keeping a short dead time and maintaining an adequate energy resolution to perform spectroscopy. The custom-made silicon sensor and the electronics are designed specifically for the beamline requirements.

  12. The SLS optics beamline

    Energy Technology Data Exchange (ETDEWEB)

    Flechsig, U.; Abela, R.; Betemps, R.; Blumer, H.; Frank, K.; Jaggi, A.; MacDowell A.A.; Padmore, H.A.; Schonherr, V.; Ulrich, J.; Walther, H.; Zelenika, S.; Zumbach, C.

    2006-05-20

    A multipurpose beamline for tests and developments in the field of x-ray optics and synchrotron radiation instrumentation in general is under construction at the Swiss Light Source (SLS) bending magnet X05DA. The beamline uses a newly developed UHV compatible, 100 mm thick, brazed CVD diamond vacuum window. The very compact cryogenically cooled channel cut Si(111) monochromator and bendable 1:1 toroidal focusing mirror at 7:75 m from the source point are installed inside the shielding tunnel. The beamline covers a photon energy range of about 6 to 17 keV.We expect 5x1011 photons=s within a 100 mu m spot and a resolving power of 1300. The monochromator and focusing mirror can be retracted independently for unfocused monochromatic and focused ''white'' light operation respectively.

  13. A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

    Institute of Scientific and Technical Information of China (English)

    Wang Xiaoyu; Yang Haigang; Li Fanyang; Yin Tao; Liu Fei

    2012-01-01

    A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented.The circuit consists of a current-mode AGC (automatic gain control) and a current-mode adaptive filter.Compared with its conventional voltage-mode counterparts,the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic.The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss.The continuous gain should meet the requirement of any input amplitude level,while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL (sound pressure level).Furthermore,the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility.These features can accommodate users whose ears have different pain thresholds.Taking advantage of the current-mode technique,the MOS transistors work in the subthreshold region so that the quiescent current is small.Moreover,the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain.Therefore,the objective of low voltage and low power (48 μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35 μm (VToN + |Vrop|≈ 1.35 V).The THD is below -45 dB.The fabricated chip only occupies the area of 1 × 0.5 mm2 and 1 × 1 mm2.

  14. Thermal neutron beamline monitor

    International Nuclear Information System (INIS)

    A detector has been developed which has characteristics that make it suitable for use as a neutron beamline monitor on the Spallation Neutron Source. Efficiency has been reduced to 10-4, pulse pair resolution is 50 nSecs and it presents minimal obstruction to the neutron beam. (author)

  15. Front-end vision and multi-scale image analysis multi-scale computer vision theory and applications, written in Mathematica

    CERN Document Server

    Romeny, Bart M Haar

    2008-01-01

    Front-End Vision and Multi-Scale Image Analysis is a tutorial in multi-scale methods for computer vision and image processing. It builds on the cross fertilization between human visual perception and multi-scale computer vision (`scale-space') theory and applications. The multi-scale strategies recognized in the first stages of the human visual system are carefully examined, and taken as inspiration for the many geometric methods discussed. All chapters are written in Mathematica, a spectacular high-level language for symbolic and numerical manipulations. The book presents a new and effective

  16. The Structure of Digital TV Front End System in Single IP Architecture%纯IP架构数字电视前端系统的结松

    Institute of Scientific and Technical Information of China (English)

    刘东明

    2012-01-01

    随着三网融合的不断推进,组建纯IP架构的数字电视网络系统成为不可阻挡的潮流。而数字电视前端系统是广播电视网向IP网络整合的关键部分。对于新建电视台网、新建居民小区以及将要从模拟电视升级到数字电视的城市与地区来说,数字电视前端系统完全可以跨越“IP/QAM调制+HFC网络”的中间架构,直接升级到纯IP架构。这样做的好处是不但顺应了技术发展的趋势,而且将大量节约投资成本,简化系统维护,便于系统升级。主要探讨如何构建纯IP架构的数字电视前端系统,包括前端设备、主干网建设以及用户端结构等方面的内容。%With the continuous development of the Network convergence (Radio and television network, Tele- communication network,internet) , setting up digital TV network system of the framework in single IP architec- ture is becoming an irresistible trend. The front end system of Digital TV system is the key part of the Network convergence from radio and television network to IP network. For the newly build TV networks,the new resi- dential quarters,the cities and districts to upgrade from analog TV to digital TV, the front end system of digital TV can beyond the transitional structure of "IP/QA Modulation + HFC networks", and direct upgrade the system in single IP architecture. This solution not only following the trend of technology development, but also can saving a lot of investment cost, simplifying system maintenance, and convenient for upgrading the system. This paper mainly discusses how to construct the system of digital TV front end in single IP architecture, inclu- ding the contents of the front end devices ,backbone network construction and the user terminal structure.

  17. CARIOCA : A Fast Binary Front-End Implemented in 0.25Pm CMOS using a Novel Current-Mode Technique for the LHCb Muon Detector

    CERN Multimedia

    2000-01-01

    The CARIOCA front-end is an amplifier discriminator chip, using 0.25mm CMOS technology, developed with a very fast and low noise preamplifier. This prototype was designed to have input impedance below 10W. Measurements showed a peaking time of 14ns and noise of 450e- at zero input capacitance, with a noise slope of 37.4 e-/pF. The sensitivity of 8mV/fC remains almost unchanged up to a detector capacitance of 120pF.

  18. Front-end technologies for robust ASR in reverberant environments—spectral enhancement-based dereverberation and auditory modulation filterbank features

    Science.gov (United States)

    Xiong, Feifei; Meyer, Bernd T.; Moritz, Niko; Rehr, Robert; Anemüller, Jörn; Gerkmann, Timo; Doclo, Simon; Goetze, Stefan

    2015-12-01

    This paper presents extended techniques aiming at the improvement of automatic speech recognition (ASR) in single-channel scenarios in the context of the REVERB (REverberant Voice Enhancement and Recognition Benchmark) challenge. The focus is laid on the development and analysis of ASR front-end technologies covering speech enhancement and feature extraction. Speech enhancement is performed using a joint noise reduction and dereverberation system in the spectral domain based on estimates of the noise and late reverberation power spectral densities (PSDs). To obtain reliable estimates of the PSDs—even in acoustic conditions with positive direct-to-reverberation energy ratios (DRRs)—we adopt the statistical model of the room impulse response explicitly incorporating DRRs, as well in combination with a novel proposed joint estimator for the reverberation time T 60 and the DRR. The feature extraction approach is inspired by processing strategies of the auditory system, where an amplitude modulation filterbank is applied to extract the temporal modulation information. These techniques were shown to improve the REVERB baseline in our previous work. Here, we investigate if similar improvements are obtained when using a state-of-the-art ASR framework, and to what extent the results depend on the specific architecture of the back-end. Apart from conventional Gaussian mixture model (GMM)-hidden Markov model (HMM) back-ends, we consider subspace GMM (SGMM)-HMMs as well as deep neural networks in a hybrid system. The speech enhancement algorithm is found to be helpful in almost all conditions, with the exception of deep learning systems in matched training-test conditions. The auditory feature type improves the baseline for all system architectures. The relative word error rate reduction achieved by combining our front-end techniques with current back-ends is 52.7% on average with the REVERB evaluation test set compared to our original REVERB result.

  19. A 16 GHz silicon-based monolithic balanced photodetector with on-chip capacitors for 25 Gbaud front-end receivers.

    Science.gov (United States)

    Hai, Mohammed Shafiqul; Sakib, Meer Nazmus; Liboiron-Ladouceur, Odile

    2013-12-30

    In this paper, a Germanium-on-Silicon balanced photodetector (BPD) with integrated biasing capacitors is demonstrated for highly compact monolithic 100 Gb/s coherent receivers or 25 Gbaud front-end receivers for differential or quadrature phase shift keying. The balanced photodetector has a bandwidth of approximately 16.2 GHz at a reverse bias of -4.5 V. The balanced photodetector exhibits a common mode rejection ratio (CMRR) of 30 dB. For balanced detection of return-to-zero (RZ) differential phase shift keying (DPSK) signal, the photodetector has a sensitivity of -6.95 dBm at the BER of 10(-12). For non-return-to-zero (NRZ) on off keying (OOK) signal, the measured BER is 1.0 × 10(-12) for a received power of -1.65 dBm at 25 Gb/s and 9.9 × 10(-5) for -0.34 dBm at 30 Gb/s. The total footprint area of the monolithic front-end receiver is less than 1 mm(2). The BPD is packaged onto a ceramic substrate with two DC and one RF connectors exhibits a bandwidth of 15.9 GHz.

  20. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

    International Nuclear Information System (INIS)

    This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 μm 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 fJ/conversion-step. (semiconductor integrated circuits)

  1. Utilizing a Novel Approach at the Fuzzy Front-End of New Product Development: A Case Study in a Flexible Fabric Supercapacitor

    Directory of Open Access Journals (Sweden)

    Gwo-Tsuen Jou

    2016-08-01

    Full Text Available The fuzzy front-end plays a most crucial part in new product development (NPD, leading to the success of product development and product launch in the market. This study proposes a novel method, TTRI_MP, by combining Crawford and Di Benedetto’s model and Cooper’s model, to strengthen the management of the fuzzy front-end. The proposed method comprises four stages: market exploration and technology forecasting, idea generation and segmentation, portfolio analysis and technology roadmapping (TRM. In the first stage, SWOT was utilized to identify the key strategic areas, and the technology readiness level (TRL was adopted to position the level of developed technologies. In the second stage, the business concepts were required to go through the viability test and customers, collaborators, competitors and company (4C. In the third stage, the Strategic Position Analysis (SPAN and Financial Analysis (FAN developed by IBM were employed in the portfolio analysis to screen out potential NPD projects. In the last stage, the selected NPD projects were linked with their functions and technologies in the TRM chart. The method was successfully implemented by a research team working on a flexible fabric supercapacitor at the Taiwan Textile Research Institute (TTRI.

  2. A single-pole nine-throw antenna switch using radio-frequency microelectromechanical systems technology for broadband multi-mode and multi-band front-ends

    International Nuclear Information System (INIS)

    In this paper, a generic single-pole nine-throw (SP9T) switch is demonstrated using radio-frequency (RF) microelectromechanical systems (MEMS) technology for broadband multi-mode and multi-band front-ends. In order to improve uniformity and yield required for complex switches, 'stress-free' single-crystalline-silicon series dc-contact MEMS switches have been employed instead of metal membrane switches. When tested according to the third-generation partnership project (3GPP) specifications, the antenna switch in this work shows loss, isolation and linearity characteristics better than the conventional semiconductor switches. Measured results showed insertion losses for all nine paths less than 0.5 dB and 2 dB from dc to 2.17 GHz and 21.6 GHz, respectively. Isolations for all input–output and output–output ports are higher than 49 dB at 2.17 GHz. Nonlinearities generated by the MEMS switch were well below the measurement limit of our system setup. The broadband RF performance, together with excellent linearity characteristics, makes this type of MEMS switch a promising candidate for an antenna switch for multi-band and multi-mode front-end applications

  3. A 55-dB SNDR, 2.2-mW double chopper-stabilized analog front-end for a thermopile sensor

    International Nuclear Information System (INIS)

    A double chopper-stabilized analog front-end (DCS-AFE) circuit for a thermopile sensor is presented, which includes a closed-loop front-end amplifier and a 2nd-order 1 bit quantization sigma—delta modulator. The amplifier with a closed-loop structure ensures the gain stability against the temperature. Moreover, by adopting the chopper-stabilized technique both for the amplifier and 2nd-order 1-bit quantization sigma—delta modulator, the low-frequency 1/f noise and offset is reduced and high resolution is achieved. The AFE is implemented in the SMIC 0.18 μm 1P6M CMOS process. The measurement results show that in a 3.3 V power supply, 1 Hz input frequency and 3KHz clock frequency, the peak signal-to-noise and distortion ratio (SNDR) is 55.4 dB, the effective number of bits (ENOB) is 8.92 bit, and in the range of −20 to 85 degrees, the detection resolution is 0.2 degree. (semiconductor integrated circuits)

  4. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

    Institute of Scientific and Technical Information of China (English)

    Chen Huabin; Xiang Jixuan; Xue Xiangyan; Chen Chixiao; Ye Fan; Xu Jun; Ren Junyan

    2014-01-01

    This paper presents an analog front end for a power line communication system,including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter,a positive feedback programmable gain amplifier,a 9.8 ppm/℃ bandgap reference and on-chip low-output voltage regulators.A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements.Implemented in the GSMC 0.13μm 1.5 V/12 V dual-gate 4P6M e-flash process,the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW,in which 1.1 mW cost by the SAR ADC.Measured at 500 kHz input,the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively,achieving a figure of merit of 350 fJ/conversion-step.

  5. An analog front end with a 12-bit 3.2-MS/s SAR ADC for a power line communication system

    Science.gov (United States)

    Huabin, Chen; Jixuan, Xiang; Xiangyan, Xue; Chixiao, Chen; Fan, Ye; Jun, Xu; Junyan, Ren

    2014-11-01

    This paper presents an analog front end for a power line communication system, including a 12-bit 3.2-MS/s energy-efficient successive approximation register analog-to-digital converter, a positive feedback programmable gain amplifier, a 9.8 ppm/°C bandgap reference and on-chip low-output voltage regulators. A two segment capacitive array structure (6 MSB 5 LSB) composed by split capacitors is designed for the SAR core to save area cost and release reference voltage accuracy requirements. Implemented in the GSMC 0.13 μm 1.5 V/12 V dual-gate 4P6M e-flash process, the analog front end occupies an area of 0.457 mm2 and consumes power of 18.8 mW, in which 1.1 mW cost by the SAR ADC. Measured at 500 kHz input, the spurious-free dynamic range and signal-to-noise plus distortion ratio of the ADC are 71.57 dB and 60.60 dB respectively, achieving a figure of merit of 350 fJ/conversion-step.

  6. Transformation and Implementation of Digital Television Front End Backup System——A Case Study of Digital Television Front End Backup System Transformation in Nanning%数字电视前端备份系统的改造与实现——南宁市数字电视前端备份系统改造案例研究

    Institute of Scientific and Technical Information of China (English)

    焦冬秀; 周思伊

    2011-01-01

    市县级数字电视前端备份系统的建设要充分考虑当地实际情况和成本投入,以安全可靠和经济实用为基本原则.以南宁市数字电视前端机房的备份系统改造为例,并结合目前国内其他市县数字电视前端备份平台建设情况进行分析研究,对基层广电网络的建设和运维具有一定的指导和借鉴作用.%Construction of digital television front end backup system in small cities and counties takes into account the local reality and cost input, so the basic design principle is secure, reliable, economical and practical. Taking backup system transformation of digital television front end machine room in Nanning as example, and combine with the analyses of other cities and counties digital television front end backup system platform construction situations, this paper plays a role in grassroots radio and television network construction, operation and maintenance.

  7. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

    Energy Technology Data Exchange (ETDEWEB)

    Knopf, Jan

    2009-07-08

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  8. Smart x-ray beam position monitor system using artificial intelligence methods for the advanced photon source insertion-device beamlines

    International Nuclear Information System (INIS)

    At the Advanced Photon Source (APS), each insertion device (ID) beamline front-end has two XBPMs to monitor the X-ray beam position for both that vertical and horizontal directions. Performance challenges for a conventional photoemission type X-ray beam position monitor (XBPM) during operations are contamination of the signal from the neighboring bending magnet sources and the sensitivity of the XBPM to the insertion device (ID) gap variations. Problems are exacerbated because users change the ID gap during their operations, and hence the percentage level of the contamination in the front end XBPM signals varies. A smart XBPM system with a high speed digital signal processor has been built at the Advanced Photon Source for the ID beamline front ends. The new version of the software, which uses an artificial intelligence method, provides a self learning and self-calibration capability to the smart XBPM system. The structure of and recent test results with the system are presented in this paper

  9. Beamline for schools

    CERN Multimedia

    2015-01-01

    This video is about BL4S Snapshot 22 Sep 2015 12:02:47From 10–20 September, winners of the Beamline for Schools competition visited CERN to perform their experiments. Two teams of high-school students – “Accelerating Africa” from South Africa and “Leo4G” from Italy – were chosen from a total of 119 teams, adding up to 1050 high-school students. “When we were told we’d won we never believed it. People’s parents thought we were lying,” says Michael Copeland from Accelerating Africa. The two teams shared a fully equipped accelerator beamline and conducted their experiment just like other researchers at CERN.

  10. Front-end Evaluation as Part of a Comprehensive Approach to Inform the Development of a New Climate Exhibit at NCAR

    Science.gov (United States)

    Ristvey, J. D., Jr.; Brinkworth, C.; Hatheway, B.; Williams, V.

    2015-12-01

    In an era of discord in public views of climate change, communicating atmospheric and related sciences to the public at a large research facility like the National Center for Atmospheric Research (NCAR) can be a daunting challenge yet one that is filled with many possibilities. The University Corporation for Atmospheric Research (UCAR) Center for Science Education (SciEd) is responsible for education and outreach activities at UCAR, including the exhibits program. Over 90,000 people visit the NCAR Mesa Lab each year to enjoy a number of exhibits that showcase our community's research. The current climate exhibit is twelve years old, and with advances in our understanding of climate science and exhibit design, SciEd staff are developing a new exhibit that is as cutting edge as the research conducted at NCAR. Based on listening sessions with NCAR scientists, the following big ideas for the exhibit emerged: How the climate system works The climate system is changing How scientists study our climate Regional impacts Solutions The goal of the new climate exhibit is to reach people using a variety of learning styles, including offerings for visitors who learn by doing, as well as providing informative text and images (Hatheway, 2014). Developers and evaluators are working together to conduct front-end, formative, and summative evaluations to understand of the needs of our visitors and collect ongoing data to inform development. The purpose of the front-end evaluation, conducted in the summer of 2014 was to develop informed data-driven strategies to move forward with exhibit design. The evaluation results to be shared in this session include: The demographics and behaviors of visitors Trends in visitors' experiences Visitor input on exhibit design (Williams and Tarsi, 2014). In this presentation, we will share the results, significance, and application of the front-end evaluation as part of a comprehensive approach to study both how we convey information about climate

  11. Integration of market pull and technology push in the corporate front end and innovation management - Insights from the German software industry

    DEFF Research Database (Denmark)

    Brem, Alexander; Voigt, K.-I.

    2009-01-01

    a conceptual framework. Additionally, the most common front end innovation models will be introduced. Finally, the authors will introduce how a technology-based service company is managing the connection of these two alternatives. A special focus will be laid on the accordant methods in order to search...... for current market needs and new related technologies. The selected case study will focus on one of Germany’s biggest and most successful software development and information technology service providers. Based on interviews, document analysis, and practical applications, an advanced conceptual framework...... managers may use the results as a conceptual mirror, especially regarding the influencing factors of innovation impulses and the use of interdisciplinary teams (with people from inside and outside the company) to accomplish successful corporate technology and innovation management....

  12. Diseño de un Front-end analógico LV-LP para medir impedancia torácica

    OpenAIRE

    Quispe Bonilla, Max David

    2014-01-01

    En este trabajo presentamos el diseño de un nuevo Front-end analógico (AFE) para medir señales de impedancia cardiográfica, ventilación pulmonar y señales electrocardiográficas (ECG). También se da un breve resumen de los algoritmos desarrollados para detectar las ondas y picos más importantes de las señales ICG, métodos usados para hallar el volumen sistólico y demás parámetros cardiacos de gran importancia. Por último, se discuten los resultados de algunas pruebas comparativas realizadas a ...

  13. Transient Stability Analysis of Grid-connected Wind Turbines with Front-end Speed Control via Information Entropy Energy Function Method

    Directory of Open Access Journals (Sweden)

    Hongwei Li

    2013-07-01

    Full Text Available According to the characteristics like time-consuming and can not be quantitatively analyzed of time domain simulation in power system transient stability analysis, a direct method using information entropy combined with transient energy function method is proposed in this paper to analyze the transient stability of wind power system equiped with front-end speed controlled wind turbines (FSCWT with synchronous generators. In which, the system kinetic energy and potential energy are used as information source to makeup information entropy function, then, a theoretical analysis of system transient stability is conducted. Based on this, simulations are carried out in IEEE 5-machine 14-bus system compared with the time domain’s, which verified the consistency of information entropy energy function (IEEF method and time domain analysis. Results show that it is more intuitively and effectively to use IEEF method for wind power system transient analysis equiped with FSCWT.

  14. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  15. HTML 5在 WEB 前端开发中的应用研究%Research on Application of HTML 5 in Web Front -end Development

    Institute of Scientific and Technical Information of China (English)

    台雯

    2016-01-01

    HTML5 has become the mainstream of the Web front -end development technology , and it has many new features compared with the previous version .This paper introduces the concept of HTML5 technology ,and some of the commonly used methods and techniques for responsive Web design based on HTML5 ,offline Web application development ,embedded audio ,video ,graphics and anima‐tion .%HTML5已成为目前主流的Web前端开发技术,与以往版本相比它具有许多新特性。本文主要介绍了HTML5技术的概念,以及基于HTML5进行响应式Web设计、Web离线程序开发、音频视频嵌入、绘图和动画实现的一些常用方法和技巧。

  16. Use of phase information with a stepper motor to control frequency for tuning system of the Front End Test Stand Radio Frequency Quadrupole at Rutherford Appleton Laboratory

    Energy Technology Data Exchange (ETDEWEB)

    Alsari, S., E-mail: s.alsari@imperial.ac.uk; Aslaninejad, M.; Pozimski, J.

    2015-03-01

    For the Front End Test Stand (FETS) linear accelerator project at the Rutherford Appleton Laboratory in the UK, a 4 m, 4 vanes Radio Frequency Quadrupole (RFQ) with a resonant frequency of 324 MHz has been designed. The RF power feeding the RFQ gives rise to the temperature increase in the RFQ, which in turn, results in shifting the resonant frequency of the RFQ. The frequency shift and the stability in the RFQ frequency can be maintained based on the reflected power or signal phase information. We have, however, investigated restoration of the RFQ nominal frequency based on the RF signal phases driving a stepper motor. The concept and the system set-up and electronics are described in detail. Results of the measurements indicating the full restoration of the RFQ nominal frequency based on the RF signal phases and stepper motor are presented. Moreover, measured sensitivity of tuner with respect to its position is given.

  17. Use of phase information with a stepper motor to control frequency for tuning system of the Front End Test Stand Radio Frequency Quadrupole at Rutherford Appleton Laboratory

    International Nuclear Information System (INIS)

    For the Front End Test Stand (FETS) linear accelerator project at the Rutherford Appleton Laboratory in the UK, a 4 m, 4 vanes Radio Frequency Quadrupole (RFQ) with a resonant frequency of 324 MHz has been designed. The RF power feeding the RFQ gives rise to the temperature increase in the RFQ, which in turn, results in shifting the resonant frequency of the RFQ. The frequency shift and the stability in the RFQ frequency can be maintained based on the reflected power or signal phase information. We have, however, investigated restoration of the RFQ nominal frequency based on the RF signal phases driving a stepper motor. The concept and the system set-up and electronics are described in detail. Results of the measurements indicating the full restoration of the RFQ nominal frequency based on the RF signal phases and stepper motor are presented. Moreover, measured sensitivity of tuner with respect to its position is given

  18. APS beamline standard components handbook

    International Nuclear Information System (INIS)

    It is clear that most Advanced Photon Source (APS) Collaborative Access Team (CAT) members would like to concentrate on designing specialized equipment related to their scientific programs rather than on routine or standard beamline components. Thus, an effort is in progress at the APS to identify standard and modular components of APS beamlines. Identifying standard components is a nontrivial task because these components should support diverse beamline objectives. To assist with this effort, the APS has obtained advice and help from a Beamline Standardization and Modularization Committee consisting of experts in beamline design, construction, and operation. The staff of the Experimental Facilities Division identified various components thought to be standard items for beamlines, regardless of the specific scientific objective of a particular beamline. A generic beamline layout formed the basis for this identification. This layout is based on a double-crystal monochromator as the first optical element, with the possibility of other elements to follow. Pre-engineering designs were then made of the identified standard components. The Beamline Standardization and Modularization Committee has reviewed these designs and provided very useful input regarding the specifications of these components. We realize that there will be other configurations that may require special or modified components. This Handbook in its current version (1.1) contains descriptions, specifications, and pre-engineering design drawings of these standard components. In the future, the APS plans to add engineering drawings of identified standard beamline components. Use of standard components should result in major cost reductions for CATs in the areas of beamline design and construction

  19. Photophysics beamline at Indus-1

    CERN Document Server

    Meenakshi-Raja-Rao, P; Raja-Sekhar, B N; Padmanabhan, S; Shastri, A; Bhattacharya, S; Roy, A P

    2001-01-01

    The first Indian synchrotron radiation source, Indus-1 has been commissioned recently at the Centre for Advanced Technology, Indore. Using the soft X-ray and VUV radiation from this 450 MeV storage ring, a variety of atomic, molecular and condensed matter physics experiments are planned. Several beamlines are being set up for this purpose. One of these beamlines, the Photophysics beamline is a medium resolution beamline meant for photoabsorption, fluorescence and reflectivity experiments in the wavelength region 500-2000 A (6-25 eV). It is currently being installed at the Indus-1 storage ring. Details of the optical and mechanical design, fabrication and testing of this beamline are discussed.

  20. The TDCpix Readout ASIC: A 75 ps Resolution Timing Front-End for the Gigatrackerof theNA62 Experiment

    Science.gov (United States)

    Rinella, G. Aglieri; Fiorini, M.; Jarron, P.; Kaplon, J.; Kluge, A.; Martin, E.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    NA62 is an experiment under development at the CERN Super Proton Synchrotron, aiming at measuring ultra rare kaon decays. The Gigatracker (GTK) detector shall combine on-beam tracking of individual particles with a time resolution of 150 ps rms. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm2 fora total rateof about 0.75 GHz.Ahybrid siliconpixel detectoris beingdevelopedto meet these requirements. The pixel chip for the Gigatracker (TDCpix) is under design. The TDCpix chip will feature 1800 square pixels of 300×300 μm2 arranged in a matrix of 45 rows × 40 columns. Bump-bonded to a silicon pixel sensor it shall perform time stamping of particle hits with a timing accuracybetter than 200 ps rms and a detection efficiencyabove 99%. The chosen architecture provides full separation of the sensitive analog amplifiers of the pixel matrix from the noisy digital circuits of the TDCs and of the readout blocks. Discriminated hit signals from each pixel are transmitted to the end of column region. An array ofTime to Digital Converters (TDC) is implemented at the bottom of the pixel array. The TDCs are based on time tagging the events with the fine time codes generated by Delay Locked Loops (DLL) and have a nominal time bin of ˜100 ps. Time stamps and time-over-threshold are recorded for each discriminated hit and the correction of the discriminator's time-walk is performed off-detector. Data are continuously transmitted on four 2.4 Gb/s serial output links. Adescription of the on-going design of the final TDCpix is given in this paper. Design choices and some technical implementation details are presented. Aprototype ASIC including thekeycomponents of this architecture has been manufactured. The achievement of specification figures such as a time resolution of the processing chain of 75 ps rms as well as charged particle time stampingwitha resolutionbetterthan200psrmswere demonstratedexperimentally.Asummaryoftheseresultsisalso presented in

  1. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  2. Design of the Taiwan contract bending-magnet beamline at SPring-8

    International Nuclear Information System (INIS)

    The BL12B2 beamline at SPring-8 is a Taiwan contract bending magnet beamline designed for multiple applications. This beamline is able to provide different operational modes of white beam and monochromatic photons of energies from 5 to 70 keV. The end stations under construction include a micro-beam station, a MAD protein crystallography station, a high-resolution X-ray scattering/diffraction station, and an EXAFS station. This beamline has been installed and will be ready for user operation in the spring of 2001

  3. A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

    Science.gov (United States)

    Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

    2016-03-01

    The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

  4. A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

    International Nuclear Information System (INIS)

    The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

  5. 10 years of protein crystallography at AR-NW12A beamline

    International Nuclear Information System (INIS)

    The exponential growth of protein crystallography can be observed in the continuously increasing demand for synchrotron beam time, both from academic and industrial users. Nowadays, the screening of a profusion of sample crystals for more and more projects is being implemented by taking advantage of fully automated procedures at every level of the experiments. The insertion device AR-NW12A beamline is one of the five macromolecular crystallography (MX) beamlines at the Photon Factory (PF). Currently the oldest MX beamline operational at the High Energy Accelerator Research Organization (KEK), the end-station was launched in 2001 as part of an upgrade of the PF Advanced Ring. Since its commissioning, AR-NW12A has been operating as a high-throughput beamline, slowly evolving to a multipurpose end-station for MX experiments. The development of the beamline took place about a decade ago, in parallel with a drastic development of protein crystallography and more general synchrotron technology. To keep the beamline up-to-date and competitive with other MX stations in Japan and worldwide, new features have been constantly added, with the goal of user friendliness of the various beamline optics and other instruments. Here we describe the evolution of AR-NW12A for its tenth anniversary. We also discuss the plans for upgrades for AR-NW12A, the future objectives in terms of the beamline developments, and especially the strong desire to open the beamline to a larger user community.

  6. Development of a low-power, low-cost front end electronics module for large scale distributed neutrino detectors

    Energy Technology Data Exchange (ETDEWEB)

    James J. Beatty

    2008-03-08

    using standard PCB fabrication techniques. We have determined that to achieve best performance the circuits should be built on a low loss-tangent RF substrate. We are working in cooperation with our colleagues in condensed matter who also have a need for this capability to purchase the equipment for in-house fabrication of prototype quantities of these circuits. We plan to continue the work on these filtersusing internal funds, and produce and characterize the performance of prototypes. We also participated in deployment of a prototype detector station near McMurdo Station, Antarctica in collaboration with colleagues at UCLA and UC-Irvine. The prototype station includes a single-board computer, GPS receiver, ADC board, and Iridium satellite modem powered by an omnidirectional solar array. We operated this station in the austral summer of 2006-2007, and used the Iridium SMS mode to transmit the status of the station until the end of the daylight season.

  7. Supporting radical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Gertsen, Frank

    2011-01-01

    ). Pharmaceutical innovation is unique, as it opposed to most other industries’ product development is science-driven and not customer-driven. In addition, the pharmaceutical FEI, as represented by research, lasts up to 5 years and the entire R&D process constitutes a period of 10-12 years, which is highly...... regulated by external authorities, e.g. The American Food and Drug Administration (FDA). The research aim of this paper is: to contribute to the field of FEI by studying how FEI can be actively supported within the industry specific context of the pharmaceutical industry, and through a conceptual discussion...... of FEI, pharmaceutical FEI and radical innovation. Based on this understanding, empirical research through exploratory and inductive case studies is analyzed. The value added and the contribution of this article to the existing FEI literature is in the study of the theoretical fields of research...

  8. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W., E-mail: gaowu@nwpu.edu.cn; Gan, B.; Li, X.; Wei, T.; Gao, D.; Hu, Y.

    2015-04-21

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e{sup −} at zero farad plus 10 e{sup −} per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source {sup 241}Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  9. A CMOS front-end for MPPC-based detectors aimed to TOF applications with fast discriminator, adjustable arming threshold and constant-fraction functionality

    International Nuclear Information System (INIS)

    We have designed and realized a Front-End chip for MPPC in standard CMOS 0.35μm technology. The channel presents a low input impedance in order to reduce as much as possible the recovery time of the sensor. This is achieved using the current domain for processing signals through the current conveyors (CCII) as building blocks of the channel. A current feed-back with low-pass filter has also been used to realize a sensitive improvement of the correction of the pile-up problem, in case of high repetition rate events. An independent arming threshold is available for each channel, providing the selection of the event through the peak level (proportional to the number of simultaneously hit pixels) reached by the signal. A constant-fraction functionality is present in order to reduce the well know time-walk problem. The delay in the correspondent branch is obtained by using an additional CCII block. The digital output of the discriminator channel has adjustable time width. The pilot chip is made up of five channels. All the values of the independent thresholds are stored in 10−bit registers as well as the values of the trigger output width and the main polarization current of the CCII blocks. All the registers are writable from a standard three-wire SPI. These features make the chip fully self-consistent. In this work we present and discuss the simulation results together with the preliminary test performed

  10. 高校图书馆网站页面的前端设计探讨%Discussion on the university library website front-end design

    Institute of Scientific and Technical Information of China (English)

    韩晶

    2014-01-01

    高校图书馆网站的设计应从读者的角度出发,以服务于广大高校师生教学科研为目的。本文指出了对于高校图书馆网站进行前端设计的必要性,并且介绍了高校图书馆网站设计特点。进而提出了针对图书馆网站设计特点所采用的设计方法,并进行了简单的举例说明。%With the consideration of the readers, the University Library website is designed to serve the purposes for teaching and researching. This article points out the necessity of the University Library website front-end design and introduces the main features of the University Library website design. Furthermore, based on the characteristics of the library website design, the design method are provided and illustrated with simple examples.

  11. Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

    CERN Document Server

    AUTHOR|(CDS)2068589; Rohrich, Dieter

    2008-01-01

    The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

  12. Development of a compact radiation-hardened low-noise front-end readout ASIC for CZT-based hard X-ray imager

    International Nuclear Information System (INIS)

    In this paper, we present the development and performances of a radiation-hardened front-end readout application-specific integrated circuit (ASIC) dedicated to CZT detectors for a hard X-ray imager in space applications. The readout channel consists of a charge sensitive amplifier (CSA), a CR-RC shaper, a fast shaper, a discriminator and a driving buffer. With the additional digital filtering, the readout channel can achieve very low noise performances and low power dissipation. An eight-channel prototype ASIC is designed and fabricated in 0.35 μm CMOS process. The energy range of the detected X-rays is evaluated as 1.45 keV to 281 keV. The gain is larger than 100 mV/fC. The equivalent noise charge (ENC) of the ASIC is 53 e− at zero farad plus 10 e− per picofarad. The power dissipation is less than 4.4 mW/channel. Through the measurement with a CZT detector, the energy resolution is less than 3.45 keV (FWHM) under the irradiation of the radioactive source 241Am. The radiation effect experiments indicate that the proposed ASIC can resist the total ionization dose (TID) irradiation of higher than 200 krad (Si)

  13. SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

    2009-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  14. Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mercado Perez, Jorge

    2008-11-10

    Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

  15. Design of a 12-bit 1 MS/s SAR-ADC for front-end readout of 32-channel CZT detector imaging system

    Energy Technology Data Exchange (ETDEWEB)

    Liu, Wei, E-mail: liouwei930@sina.com [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun; Li, Bo; Guo, Panjie [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

    2015-06-21

    A 12-bit 1MS/s SAR-ADC for the front-end readout of a 32-channel CZT detector imaging system is presented. In order to improve the performances of the ADC, several techniques are proposed. First, a novel offset cancellation method for comparator is proposed, in which no any capacitor is introduced in the signal pathway, thus it has faster operation speed than traditional one. Second, the architecture of unit capacitor array is adopted in the charge-redistribution DAC to reduce the capacitor mismatch. Third, the radiation-hardened ability is enhanced through circuit and layout design. The prototype chip was fabricated using a TSMC 0.35 um 2P4M CMOS process. At a 3.3/5 V power supply, the proposed SAR-ADC achieves 67.64 dB SINAD at 1MS/s, consumes 10 mW power and occupies a core area of 1180×1080 um{sup 2}.

  16. Towards the development of a wearable Electrical Impedance Tomography system: A study about the suitability of a low power bioimpedance front-end.

    Science.gov (United States)

    Menolotto, Matteo; Rossi, Stefano; Dario, Paolo; Della Torre, Luigi

    2015-01-01

    Wearable systems for remote monitoring of physiological parameter are ready to evolve towards wearable imaging systems. The Electrical Impedance Tomography (EIT) allows the non-invasive investigation of the internal body structure. The characteristics of this low-resolution and low-cost technique match perfectly with the concept of a wearable imaging device. On the other hand low power consumption, which is a mandatory requirement for wearable systems, is not usually discussed for standard EIT applications. In this work a previously developed low power architecture for a wearable bioimpedance sensor is applied to EIT acquisition and reconstruction, to evaluate the impact on the image of the limited signal to noise ratio (SNR), caused by low power design. Some anatomical models of the chest, with increasing geometric complexity, were developed, in order to evaluate and calibrate, through simulations, the parameters of the reconstruction algorithms provided by Electrical Impedance Diffuse Optical Reconstruction Software (EIDORS) project. The simulation results were compared with experimental measurements taken with our bioimpedance device on a phantom reproducing chest tissues properties. The comparison was both qualitative and quantitative through the application of suitable figures of merit; in this way the impact of the noise of the low power front-end on the image quality was assessed. The comparison between simulation and measurement results demonstrated that, despite the limited SNR, the device is accurate enough to be used for the development of an EIT based imaging wearable system. PMID:26736956

  17. Design of the Front End Electronics for the Infrared Camera of JEM-EUSO, and manufacturing and verification of the prototype model

    CERN Document Server

    Maroto, Oscar; Carbonell, Jordi; Tomàs, Albert; Reyes, Marcos; Joven, Enrique; Martín, Yolanda; Ríos, J A Morales de los; Del Peral, Luis; Frías, M D Rodríguez

    2015-01-01

    The Japanese Experiment Module (JEM) Extreme Universe Space Observatory (EUSO) will be launched and attached to the Japanese module of the International Space Station (ISS). Its aim is to observe UV photon tracks produced by ultra-high energy cosmic rays developing in the atmosphere and producing extensive air showers. The key element of the instrument is a very wide-field, very fast, large-lense telescope that can detect extreme energy particles with energy above $10^{19}$ eV. The Atmospheric Monitoring System (AMS), comprising, among others, the Infrared Camera (IRCAM), which is the Spanish contribution, plays a fundamental role in the understanding of the atmospheric conditions in the Field of View (FoV) of the telescope. It is used to detect the temperature of clouds and to obtain the cloud coverage and cloud top altitude during the observation period of the JEM-EUSO main instrument. SENER is responsible for the preliminary design of the Front End Electronics (FEE) of the Infrared Camera, based on an unco...

  18. The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

    Science.gov (United States)

    Aguilar, J. A.; Bilnik, W.; Borkowski, J.; Cadoux, F.; Christov, A.; della Volpe, D.; Favre, Y.; Heller, M.; Kasperek, J.; Lyard, E.; Marszałek, A.; Moderski, R.; Montaruli, T.; Porcelli, A.; Prandini, E.; Rajda, P.; Rameez, M.; Schioppa, E.; Troyano Pujadas, I.; Ziȩtara, K.; Błocki, J.; Bogacz, L.; Bulik, T.; Curyło, M.; Dyrda, M.; Frankowski, A.; Grudniki, Ł.; Grudzińska, M.; Idźkowski, B.; Jamrozy, M.; Janiak, M.; Lalik, K.; Mach, E.; Mandat, D.; Michałowski, J.; Neronov, A.; Niemiec, J.; Ostrowski, M.; Paśsko, P.; Pech, M.; Schovanek, P.; Seweryn, K.; Skowron, K.; Sliusar, V.; Sowiński, M.; Stawarz, Ł.; Stodulska, M.; Stodulski, M.; Toscano, S.; Walter, R.; Wiȩcek, M.; Zagdański, A.; Żychowski, P.

    2016-09-01

    The single mirror Small Size Telescope (SST-1M) is one of the proposed designs for the smallest type of telescopes, SSTs that will compose the Cherenkov Telescope Array (CTA). The SST-1M camera will use Silicon PhotoMultipliers (SiPM) which are nowadays commonly used in High Energy Physics experiments and many imaging applications. However the unique pixel shape and size have required a dedicated development by the University of Geneva and Hamamatsu. The resulting sensor has a surface of ∼94 mm2 and a total capacitance of ∼3.4 nF. These unique characteristics, combined with the stringent requirements of the CTA project on timing and charge resolution have led the University of Geneva to develop custom front-end electronics. The preamplifier stage has been tailored in order to optimize the signal shape using measurement campaigns and electronic simulation of the sensor. A dedicated trans-impedance pre-amplifier topology is used resulting in a power consumption of 400 mW per pixel and a pulse width control electronics was designed to provide the bias voltage with 6.7 mV precision and to correct for temperature variation with a forward feedback compensation with 0.17 °C resolution. It is fully configurable and can be monitored using CANbus interface. The architecture and the characterization of the various elements are presented.

  19. Development of a front-end analog circuit for multi-channel SiPM readout and performance verification for various PET detector designs

    International Nuclear Information System (INIS)

    Silicon photomultipliers (SiPMs) are outstanding photosensors for the development of compact imaging devices and hybrid imaging systems such as positron emission tomography (PET)/ magnetic resonance (MR) scanners because of their small size and MR compatibility. The wide use of this sensor for various types of scintillation detector modules is being accelerated by recent developments in tileable multichannel SiPM arrays. In this work, we present the development of a front-end readout module for multi-channel SiPMs. This readout module is easily extendable to yield a wider detection area by the use of a resistive charge division network (RCN). We applied this readout module to various PET detectors designed for use in small animal PET/MR, optical fiber PET/MR, and double layer depth of interaction (DOI) PET. The basic characteristics of these detector modules were also investigated. The results demonstrate that the PET block detectors developed using the readout module and tileable multi-channel SiPMs had reasonable performance

  20. Development of a front-end analog circuit for multi-channel SiPM readout and performance verification for various PET detector designs

    Energy Technology Data Exchange (ETDEWEB)

    Ko, Guen Bae; Yoon, Hyun Suk [Department of Nuclear Medicine, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Department of Biomedical Sciences, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Institute of Radiation Medicine, Medical Research Center, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Kwon, Sun Il [Department of Nuclear Medicine, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Interdisciplinary Program in Radiation Applied Life Science, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Institute of Radiation Medicine, Medical Research Center, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Lee, Chan Mi [Department of Nuclear Medicine, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Department of Biomedical Sciences, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Institute of Radiation Medicine, Medical Research Center, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Ito, Mikiko [Department of Nuclear Medicine, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Institute of Radiation Medicine, Medical Research Center, Seoul National University, 103 Daehak-ro, Jongro-gu, Seoul 110-799 (Korea, Republic of); Hong, Seong Jong [Department of Radiological Science, Eulji University, 212 Yangji-dong, Sujeong-gu, Seongnam-si, Gyeonggi-do, 461-713 (Korea, Republic of); and others

    2013-03-01

    Silicon photomultipliers (SiPMs) are outstanding photosensors for the development of compact imaging devices and hybrid imaging systems such as positron emission tomography (PET)/ magnetic resonance (MR) scanners because of their small size and MR compatibility. The wide use of this sensor for various types of scintillation detector modules is being accelerated by recent developments in tileable multichannel SiPM arrays. In this work, we present the development of a front-end readout module for multi-channel SiPMs. This readout module is easily extendable to yield a wider detection area by the use of a resistive charge division network (RCN). We applied this readout module to various PET detectors designed for use in small animal PET/MR, optical fiber PET/MR, and double layer depth of interaction (DOI) PET. The basic characteristics of these detector modules were also investigated. The results demonstrate that the PET block detectors developed using the readout module and tileable multi-channel SiPMs had reasonable performance.