Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

Energy Technology Data Exchange (ETDEWEB)

Loechner, S.

2006-07-26

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Development, optimisation and characterisation of a radiation hard mixed-signal readout chip for LHCb

International Nuclear Information System (INIS)

Loechner, S.

2006-01-01

The Beetle chip is a radiation hard, 128 channel pipelined readout chip for silicon strip detectors. The front-end consists of a charge-sensitive preamplifier followed by a CR-RC pulse shaper. The analogue pipeline memory is implemented as a switched capacitor array with a maximum latency of 4us. The 128 analogue channels are multiplexed and transmitted off chip in 900ns via four current output drivers. Beside the pipelined readout path, the Beetle provides a fast discrimination of the front-end pulse. Within this doctoral thesis parts of the radiation hard Beetle readout chip for the LHCb experiment have been developed. The overall chip performances like noise, power consumption, input charge rates have been optimised as well as the elimination of failures so that the Beetle fulfils the requirements of the experiment. Furthermore the characterisation of the chip was a major part of this thesis. Beside the detailed measurement of the chip performance, several irradiation tests and an Single Event Upset (SEU) test were performed. A long-time measurement with a silicon strip detector was also part of this work as well as the development and test of a first mass production test setup. The Beetle chip showed no functional failure and only slight degradation in the analogue performance under irradiation of up to 130Mrad total dose. The Beetle chip fulfils all requirements of the vertex detector (VELO), the trigger tracker (TT) and the inner tracker (IT) and is ready for the start of LHCb end of 2007. (orig.)

Readout electronic for multichannel detectors

CERN Document Server

Kulibaba, V I; Naumov, S V

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) sup 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc.

Readout electronic for multichannel detectors

International Nuclear Information System (INIS)

Kulibaba, V.I.; Maslov, N.I.; Naumov, S.V.

2001-01-01

Readout electronics based on the 128-channel chip 'Viking' (IDE AS inc., Norway) is considered. The chip 'Viking' integrates 128 low noise charge-sensitive preamplifiers with tunable CR-(RC) 2 shapers,analog memory and multiplexed readout to one output. All modules of readout electronics were designed and produced in KIPT taking into account the published recommendations of IDE AS inc

Spectroscopy study of imaging devices based on silicon Pixel Array Detector coupled to VATAGP7 read-out chips

International Nuclear Information System (INIS)

Linhart, V; Lacasta, C; Llosa, G; Stankova, V; Burdette, D; Chessi, E; Cochran, E; Honscheid, K; Kagan, H; Weilhammer, P; Cindro, V; Grosicar, B; Mikuz, M; Studen, A; Zontar, D; Clinthorne, N H

2011-01-01

Spectroscopic and timing response studies have been conducted on a detector module consisting of a silicon Pixel Array Detector bonded on two VATAGP7 read-out chips manufactured by Gamma-Medica Ideas using laboratory gamma sources and the internal calibration facilities (the calibration system of the read-out chips). The performed tests have proven that the chips have (i) non-linear calibration curves which can be approximated by power functions, (ii) capability to measure the energy of photons with energy resolution better than 2 keV (exact range and resolution depend on experimental setup), (iii) the internal calibration facility which provides 6 out of 16 available internal calibration charges within our region of interest (spanning the Compton edge of 511 keV photons). The peaks induced by the internal calibration facility are suitable for a fit of the calibration curves. However, they are not suitable for measurements of equivalent noise charge because their full width at half maximum varies with their amplitude. These facts indicate that the VATAGP7 chips are useful and precise tools for a wide variety of spectroscopic devices. We have also explored time walk of the module and peaking time of the spectroscopy signals provided by the chips. We have observed that (iv) the time walk is caused partly by the peaking time of the signals provided by the fast shaper of the chips and partly by the timing uncertainty related to the varying position of the photon interaction, (v) the peaking time of the spectroscopy signals provided by the chips increases with increasing pulse height.

Radiation effects on the Viking-2 preamplifier-readout chip

International Nuclear Information System (INIS)

Fallot-Burghardt, W.; Hawblitzel, C.; Hofmann, W.; Knoepfle, K.T.; Seeger, M.; Brenner, R.; Nygaard, E.; Rudge, A.; Toker, O.; Weilhammer, P.; Yoshioka, K.

1994-01-01

We have studied the radiation sensitivity of the Viking-2 VLSI circuit which has been designed for the readout of silicon strip detectors and manufactured at Mietec in 1.5 μm CMOS technology. Both biased and unbiased chips have been irradiated with a 137 Cs γ source up to a total dose of 2 kGy (200 krad) after which all tested chips were still fully functional. We report the characteristic changes of device parameters with dose, including equivalent noise charge for different capacitive loads, and determine transistor threshold shifts and change of mobilities. ((orig.))

Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

International Nuclear Information System (INIS)

Trimpl, M.

2005-12-01

The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

Design of a current based readout chip and development of a DEPFET pixel prototype system for the ILC vertex detector

Energy Technology Data Exchange (ETDEWEB)

Trimpl, M.

2005-12-15

The future TeV-scale linear collider ILC (International Linear Collider) offers a large variety of precision measurements complementary to the discovery potential of the LHC (Large Hadron Collider). To fully exploit its physics potential, a vertex detector with unprecedented performance is needed. One proposed technology for the ILC vertex detector is the DEPFET active pixel sensor. The DEPFET sensor offers particle detection with in-pixel amplification by incorporating a field effect transistor into a fully depleted high-ohmic silicon substrate. The device provides an excellent signal-to-noise ratio and a good spatial resolution at the same time. To establish a very fast readout of a DEPFET pixel matrix with row rates of 20 MHz and more, the 128 channel CURO II ASIC has been designed and fabricated. The architecture of the chip is completely based on current mode techniques (SI) perfectly adapted to the current signal of the sensor. For the ILC vertex detector a prototype system with a 64 x 128 DEPFET pixel matrix read out by the CURO II chip has been developed. The design issues and the standalone performance of the readout chip as well as first results with the prototype system will be presented. (orig.)

Performance of a Fast Binary Readout CMOS Active Pixel Sensor Chip Designed for Charged Particle Detection

Science.gov (United States)

Deerli, Yavuz; Besanon, Marc; Besson, Auguste; Claus, Gilles; Deptuch, Grzegorz; Dulinski, Wojciech; Fourches, Nicolas; Goffe, Mathieu; Himmi, Abdelkader; Li, Yan; Lutz, Pierre; Orsini, Fabienne; Szelezniak, Michal

2006-12-01

We report on the performance of the MIMOSA8 (HiMAPS1) chip. The chip is a 128times32 pixels array where 24 columns have discriminated binary outputs and eight columns analog test outputs. Offset correction techniques are used extensively in this chip to overcome process related mismatches. The array is divided in four blocks of pixels with different conversion factors and is controlled by a serially programmable sequencer. MIMOSA8 is a representative of the CMOS sensors development option considered as a promising candidate for the Vertex Detector of the future International Linear Collider (ILC). The readout technique, implemented on the chip, combines high spatial resolution capabilities with high processing readout speed. Data acquisition, providing control of the chip and signal buffering and linked to a VME system, was made on the eight analog outputs. Analog data, without and with a 55Fe X-ray source, were acquired and processed using off-line analysis software. From the reconstruction of pixel clusters, built around a central pixel, we deduce that the charge spread is limited to the closest 25 pixels and almost all the available charge is collected. The position of the total charge collection peak (and subsequently the charge-to-voltage conversion factor) stays unaffected when the clock frequency is increased even up to 150 MHz (13.6 mus readout time per frame). The discriminators, placed in the readout chain, have proved to be fully functional. Beam tests have been made with high energy electrons at DESY (Germany) to study detection efficiency. The results prove that MIMOSA8 is the first and fastest successful monolithic active pixel sensor with on-chip signal discrimination for detection of MIPs

A self-adjusting delay circuit for pixel read-out chips

International Nuclear Information System (INIS)

Raith, B.

1997-01-01

A simple concept for automatic adjustment of important VLSI-circuit properties was proposed in (Fischer and Joens, Nucl. Instr. and. Meth.). As an application, a self-adjusting monoflop is reviewed, and detailed measurements are discussed regarding a possible implementation in the LHC 1 read-out chip for the ATLAS experiment (ATLAS Internal Note, 1995). (orig.)

Programmable System-on-Chip (PSoC) Embedded Readout Designs for Liquid Helium Level Sensors.

Science.gov (United States)

Parasakthi, C; Gireesan, K; Usha Rani, R; Sheela, O K; Janawadkar, M P

2014-08-01

This article reports the development of programmable system-on-chip (PSoC)-based embedded readout designs for liquid helium level sensors using resistive liquid vapor discriminators. The system has been built for the measurement of liquid helium level in a concave-bottomed, helmet-shaped, fiber-reinforced plastic cryostat for magnetoencephalography. This design incorporates three carbon resistors as cost-effective sensors, which are mounted at desired heights inside the cryostat and were used to infer the liquid helium level by measuring their temperature-dependent resistance. Localized electrical heating of the carbon resistors was used to discriminate whether the resistor is immersed in liquid helium or its vapor by exploiting the difference in the heat transfer rates in the two environments. This report describes a single PSoC chip for the design and development of a constant current source to drive the three carbon resistors, a multiplexer to route the sensor outputs to the analog-to-digital converter (ADC), a buffer to avoid loading of the sensors, an ADC for digitizing the data, and a display using liquid crystal display cum light-emitting diode modules. The level sensor readout designed with a single PSoC chip enables cost-effective and reliable measurement system design. © 2014 Society for Laboratory Automation and Screening.

Integration of the Omega-3 readout chip into a high energy physics experimental data acquisition system

International Nuclear Information System (INIS)

Beker, H.; Chesi, E.; Martinengo, P.

1997-01-01

The Omega-3 readout chip is presented in detail elsewhere in the same proceedings. We here describe the integration of the chip into present and future experiments describing both hardware and software aspects. We cover preliminary tests in the laboratory and on the beam. The WA97 experiment has already used a pixel telescope in the past and intends to upgrade to the Omega-3 chip. A newly proposed experiment at CERN studying strangeness production in heavy ion collisions also plans to use a similar telescope. Finally, we give an outlook on the ongoing developments in the pixel readout architecture in the context of ALICE, the heavy ion experiment at the LHC collider. (orig.)

LSST camera readout chip ASPIC: test tools

Science.gov (United States)

Antilogus, P.; Bailly, Ph; Jeglot, J.; Juramy, C.; Lebbolo, H.; Martin, D.; Moniez, M.; Tocut, V.; Wicek, F.

2012-02-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

LSST camera readout chip ASPIC: test tools

International Nuclear Information System (INIS)

Antilogus, P; Bailly, Ph; Juramy, C; Lebbolo, H; Martin, D; Jeglot, J; Moniez, M; Tocut, V; Wicek, F

2012-01-01

The LSST camera will have more than 3000 video-processing channels. The readout of this large focal plane requires a very compact readout chain. The correlated ''Double Sampling technique'', which is generally used for the signal readout of CCDs, is also adopted for this application and implemented with the so called ''Dual Slope integrator'' method. We have designed and implemented an ASIC for LSST: the Analog Signal Processing asIC (ASPIC). The goal is to amplify the signal close to the output, in order to maximize signal to noise ratio, and to send differential outputs to the digitization. Others requirements are that each chip should process the output of half a CCD, that is 8 channels and should operate at 173 K. A specific Back End board has been designed especially for lab test purposes. It manages the clock signals, digitizes the analog differentials outputs of ASPIC and stores data into a memory. It contains 8 ADCs (18 bits), 512 kwords memory and an USB interface. An FPGA manages all signals from/to all components on board and generates the timing sequence for ASPIC. Its firmware is written in Verilog and VHDL languages. Internals registers permit to define various tests parameters of the ASPIC. A Labview GUI allows to load or update these registers and to check a proper operation. Several series of tests, including linearity, noise and crosstalk, have been performed over the past year to characterize the ASPIC at room and cold temperature. At present, the ASPIC, Back-End board and CCD detectors are being integrated to perform a characterization of the whole readout chain.

A Fastbus-based silicon strip readout system

International Nuclear Information System (INIS)

Neoustroev, P.; Stepanov, V.; Svoiski, M.; Uvarov, L.; Matthew, P.; Russ, J.; Cooper, P.

1995-01-01

The readout system we describe here is built specifically to work with the LBL-designed SVX chip. It is typical of systems using a master sequencer module to direct the trigger and readout cycles of the sparse data source and to push data into a digitization and storage module. (orig.)

Performance of the CAMEX64 silicon strip readout chip

International Nuclear Information System (INIS)

Yarema, R.J.

1989-06-01

The CAMEX64 is a 64 channel full custom CMOS chip designed specifically for the readout of silicon strip detectors. CAMEX which stands for CMOS Multichannel Analog MultiplEXer for Silicon Strip Detectors was designed by members of the Franhofer Institute for Microelectronic Circuits and Systems and the Max Planck Institute for Physics and Astrophysics. Each CAMEX channel has a switched capacitor charge sensitive amplifier with 4 sampling capacitors and a multiplexing scheme for reading out each of the channels on an analog bus. The device uses multiple sampling capacitors to filter and reduce input noise. Filtering is controlled through sampling techniques using external clocks. The device operates in a double correlated sampling mode and therefore cannot separate detector leakage current from a charge input. Normal operation of this device is similar to all other silicon readout chips designed and built thus far in that there is a data acquisition cycle during which charge is simultaneously accepted on all channels for a short period of time from a detector array, followed by a readout cycle where that charge or hit information is read out. This device works especially well for colliding beam experiments where the time of charge arrival is accurately known. However it can be used in fixed target or asynchronous mode where the time of charge arrival is not well known. In the asynchronous mode it appears that gain is somewhat dependent on the time interval required to decide whether or not to accept charge input information and thus the maximum signal to noise performance found with the synchronous mode may not be achieved in the asynchronous mode. 18 figs., 5 tabs

A prototype pixel readout chip for asynchronous detection applications

International Nuclear Information System (INIS)

Raymond, D.M.; Hall, G.; Lewis, A.J.; Sharp, P.H.

1991-01-01

A two-dimensional array of amplifier cells has been fabricated as a prototype readout system for a matching array of silicon diode detectors. Each cell contains a preamplifier, shaping amplifier, comparator and analogue signal storage in an area of 300 μmx320 μm using 3 μm CMOS technology. Full size chips will be bump bonded to pixel detector arrays. Low noise and asynchronous operation are novel design features. With noise levels of less than 250 rms electrons for input capacitances up to 600 fF, pixel detectors will be suitable for autoradiography, synchrotron X-ray and high energy particle detection applications. The design of the prototype chip is presented and future developments and prospects for applications are discussed. (orig.)

Frequency multiplexing for readout of spin qubits

Energy Technology Data Exchange (ETDEWEB)

Hornibrook, J. M.; Colless, J. I.; Mahoney, A. C.; Croot, X. G.; Blanvillain, S.; Reilly, D. J., E-mail: david.reilly@sydney.edu.au [ARC Centre of Excellence for Engineered Quantum Systems, School of Physics, University of Sydney, Sydney, NSW 2006 (Australia); Lu, H.; Gossard, A. C. [Materials Department, University of California, Santa Barbara, California 93106 (United States)

2014-03-10

We demonstrate a low loss, chip-level frequency multiplexing scheme for readout of scaled-up spin qubit devices. By integrating separate bias tees and resonator circuits on-chip for each readout channel, we realise dispersive gate-sensing in combination with charge detection based on two radio frequency quantum point contacts. We apply this approach to perform multiplexed readout of a double quantum dot in the few-electron regime and further demonstrate operation of a 10-channel multiplexing device. Limitations for scaling spin qubit readout to large numbers of multiplexed channels are discussed.

A One-Dimensional Magnetic Chip with a Hybrid Magnetosensor and a Readout Circuit

Directory of Open Access Journals (Sweden)

Guo-Ming Sung

2018-01-01

Full Text Available This work presents a one-dimensional magnetic chip composed of a hybrid magnetosensor and a readout circuit, which were fabricated with 0.18 μm 1P6M CMOS technology. The proposed magnetosensor includes a polysilicon cross-shaped Hall plate and two separated metal-oxide semiconductor field-effect transistors (MOSFETs to sense the magnetic induction perpendicular to the chip surface. The readout circuit, which comprises a current-to-voltage converter, a low-pass filter, and an instrumentation amplifier, is designed to amplify the output Hall voltage with a gain of 43 dB. Furthermore, a SPICE macro model is proposed to predict the sensor’s performance in advance and to ensure sufficient comprehension of the magnetic mechanism of the proposed magnetosensor. Both simulated and measured results verify the correctness and flexibility of the proposed SPICE macro model. Measurements reveal that the maximum output Hall voltage VH, the optimum current-related magnetosensitivity SRI, the optimum voltage-related magnetosensitivity SRV, the averaged nonlinearity error NLE, and the relative bias current Ibias are 4.381 mV, 520.5 V/A·T, 40.04 V/V·T, 7.19%, and 200 μA, respectively, for the proposed 1-D magnetic chip with a readout circuit of 43 dB. The averaged NLE is small at high magnetic inductions of ±30 mT, whereas it is large at low magnetic inductions of ±30 G.

Radiation induced effects in the \\\\ATLAS Insertable B-Layer readout chip

CERN Document Server

The ATLAS collaboration

2017-01-01

The ATLAS Insertable B-Layer is the innermost pixel barrel layer of the ATLAS detector installed in 2014. During the first year of $pp$ collisions at $\\sqrt{s} = 13~{\\rm TeV}$ in 2015, an unusual increase was observed in the low voltage currents of the readout chips. This increase was found to be due to radiation damage to the chips. The dependence of the current on the total ionising dose and temperature has been studied using X-ray and proton beam sources, and will be presented in this note together with its possible parametrisation and operation guidelines for the detector.

Development of telescope readout system based on FELIX for testbeam experiments

CERN Document Server

Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

2017-01-01

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

MAROC, a generic photomultiplier readout chip

Science.gov (United States)

Blin, S.; Barrillon, P.; de La Taille, C.

2010-12-01

The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ~ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ~ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

Development of a Timepix3 readout system based on the Merlin readout system

International Nuclear Information System (INIS)

Crevatin, G.; Carrato, S.; Horswell, I.; Omar, D.; Tartoni, N.; Cautero, G.

2015-01-01

Timepix3 chip is a new ASIC specifically designed to readout hybrid pixel detectors. The main purpose of Timepix3 is to measure the time of arrival of events. This characteristic can be exploited very effectively to develop detectors for time resolved experiments at synchrotron radiation facilities. In order to investigate how the ASIC can be applied to synchrotron experiments the Merlin readout system, developed at Diamond for the Medipix3 ASIC, has been adapted to readout the Timepix3 ASIC. The first tests of the ASIC with pulse injection and with alpha particles show that its behaviour is consistent with its nominal characteristics

A multi-chip data acquisition system based on a heterogeneous system-on-chip platform

CERN Document Server

Fiergolski, Adrian

2017-01-01

The Control and Readout Inner tracking BOard (CaRIBOu) is a versatile readout system targeting a multitude of detector prototypes. It profits from the heterogeneous platform of the Zynq System-on-Chip (SoC) and integrates in a monolithic device front-end FPGA resources with a back-end software running on a hard-core ARM-based processor. The user-friendly Linux terminal with the pre-installed DAQ software is combined with the efficiency and throughput of a system fully implemented in the FPGA fabric. The paper presents the design of the SoC-based DAQ system and its building blocks. It also shows examples of the achieved functionality for the CLICpix2 readout ASIC.

MAROC, a generic photomultiplier readout chip

Energy Technology Data Exchange (ETDEWEB)

Blin, S; Barrillon, P; La Taille, C de, E-mail: blin@lal.in2p3.f [CNRS/IN2p3/LAL-OMEGA, Universite Paris Sud, Bat.200, 91898 Orsay (France)

2010-12-15

The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( {approx} 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: {approx} 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

MAROC, a generic photomultiplier readout chip

International Nuclear Information System (INIS)

Blin, S; Barrillon, P; La Taille, C de

2010-01-01

The MAROC ASICs family is dedicated to the readout of 64-channel Multi Anode PMT and similar detectors. Its main roles are to correct the gain spread of MAPMT channels thanks to an individual variable gain preamplifier and to discriminate the input signals (from 50fC i.e 1/3 photo-electron) in order to produce 64 trigger outputs. A multiplexed analog charge output is also available with a dynamic range around 10 pe ( ∼ 1.6 pC) and a 12 bit Wilkinson ADC is embedded. Three versions of this chip have been submitted. MAROC 2 is the production version for the ATLAS luminometer and MAROC3 is a version with lower dissipation and significant improvements concerning the charge (30 pe: ∼ 5 pC) and trigger (discrimination from 10fC). This third version showed very good characteristics that are presented here.

Evaluation of the x-ray response of a position-sensitive microstrip detector with an integrated readout chip

International Nuclear Information System (INIS)

Rossington, C.; Jaklevic, J.; Haber, C.; Spieler, H.; Reid, J.

1990-08-01

The performance of an SVX silicon microstrip detector and its compatible integrated readout chip have been evaluated in response to Rh Kα x-rays (average energy 20.5 keV). The energy and spatial discrimination capabilities, efficient data management and fast readout rates make it an attractive alternative to the CCD and PDA detectors now being offered for x-ray position sensitive diffraction and EXAFS work. The SVX system was designed for high energy physics applications and thus further development of the existing system is required to optimize it for use in practical x-ray experiments. For optimum energy resolution the system noise must be decreased to its previously demonstrated low levels of 2 keV FWHM at 60 keV or less, and the data handling rate of the computer must be increased. New readout chips are now available that offer the potential of better performance. 15 refs., 7 figs

Yarr: A PCIe based readout system for semiconductor tracking systems

Energy Technology Data Exchange (ETDEWEB)

Heim, Timon [Bergische Universitaet Wuppertal, Wuppertal (Germany); CERN, Geneva (Switzerland); Maettig, Peter [Bergische Universitaet Wuppertal, Wuppertal (Germany); Pernegger, Heinz [CERN, Geneva (Switzerland)

2015-07-01

The Yarr readout system is a novel DAQ concept, using an FPGA board connected via PCIe to a computer, to read out semiconductor tracking systems. The system uses the FPGA as a reconfigurable IO interface which, in conjunction with the very high speed of the PCIe bus, enables a focus of processing the data stream coming from the pixel detector in software. Modern computer system could potentially make the need of custom signal processing hardware in readout systems obsolete and the Yarr readout system showcases this for FE-I4 chips, which are state-of-the-art readout chips used in the ATLAS Pixel Insertable B-Layer and developed for tracking in high multiplicity environments. The underlying concept of the Yarr readout system tries to move intelligence from hardware into the software without the loss of performance, which is made possible by modern multi-core processors. The FPGA board firmware acts like a buffer and does no further processing of the data stream, enabling rapid integration of new hardware due to minimal firmware minimisation.

Indium phosphide-based monolithically integrated PIN waveguide photodiode readout for resonant cantilever sensors

Energy Technology Data Exchange (ETDEWEB)

Siwak, N. P. [Department of Electrical and Computer Engineering, Institute for Systems Research, University of Maryland, College Park, Maryland 20742 (United States); Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740 (United States); Fan, X. Z.; Ghodssi, R. [Department of Electrical and Computer Engineering, Institute for Systems Research, University of Maryland, College Park, Maryland 20742 (United States); Kanakaraju, S.; Richardson, C. J. K. [Laboratory for the Physical Sciences, 8050 Greenmead Drive, College Park, Maryland 20740 (United States)

2014-10-06

An integrated photodiode displacement readout scheme for a microelectromechanical cantilever waveguide resonator sensing platform is presented. III-V semiconductors are used to enable the monolithic integration of passive waveguides with active optical components. This work builds upon previously demonstrated results by measuring the displacement of cantilever waveguide resonators with on-chip waveguide PIN photodiodes. The on-chip integration of the readout provides an additional 70% improvement in mass sensitivity compared to off-chip photodetector designs due to measurement stability and minimized coupling loss. In addition to increased measurement stability, reduced packaging complexity is achieved due to the simplicity of the readout design. We have fabricated cantilever waveguides with integrated photodetectors and experimentally characterized these cantilever sensors with monolithically integrated PIN photodiodes.

Development of Micromegas-like gaseous detectors using a pixel readout chip as collecting anode

International Nuclear Information System (INIS)

Chefdeville, M.

2009-01-01

This thesis reports on the fabrication and test of a new gaseous detector with a very large number of readout channels. This detector is intended for measuring the tracks of charged particles with an unprecedented sensitivity to single electrons of almost 100 %. It combines a metal grid for signal amplification called the Micromegas with a pixel readout chip as signal collecting anode and is dubbed GridPix. GridPix is a potential candidate for a sub-detector at a future electron linear collider (ILC) foreseen to work in parallel with the LHC around 2020--2030. The tracking capability of GridPix is best exploited if the Micromegas is integrated on the pixel chip. This integrated grid is called InGrid and is precisely fabricated by wafer post-processing. The various steps of the fabrication process and the measurements of its gain, energy resolution and ion back-flow property are reported in this document. Studies of the response of the complete detector formed by an InGrid and a TimePix pixel chip to X-rays and cosmic particles are also presented. In particular, the efficiency for detecting single electrons and the point resolution in the pixel plane are measured. Implications for a GridPix detector at ILC are discussed. (author)

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

International Nuclear Information System (INIS)

Flouzat, C.; Değerli, Y.; Guilloux, F.; Orsini, F.; Venault, P.

2015-01-01

In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R and D program has been performed on the design of MAPS in the 0.18 μ m CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 μ m CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision

Zero suppression logic of the ALICE muon forward tracker pixel chip prototype PIXAM and associated readout electronics development

Science.gov (United States)

Flouzat, C.; Değerli, Y.; Guilloux, F.; Orsini, F.; Venault, P.

2015-05-01

In the framework of the ALICE experiment upgrade at HL-LHC, a new forward tracking detector, the Muon Forward Tracker (MFT), is foreseen to overcome the intrinsic limitations of the present Muon Spectrometer and will perform new measurements of general interest for the whole ALICE physics. To fulfill the new detector requirements, CMOS Monolithic Active Pixel Sensors (MAPS) provide an attractive trade-off between readout speed, spatial resolution, radiation hardness, granularity, power consumption and material budget. This technology has been chosen to equip the Muon Forward Tracker and also the vertex detector: the Inner Tracking System (ITS). Since few years, an intensive R&D program has been performed on the design of MAPS in the 0.18 μ m CMOS Image Sensor (CIS) process. In order to avoid pile up effects in the experiment, the classical rolling shutter readout system of MAPS has been improved to overcome the readout speed limitation. A zero suppression algorithm, based on a 3 by 3 cluster finding (position and data), has been chosen for the MFT. This algorithm allows adequate data compression for the sensor. This paper presents the large size prototype PIXAM, which represents 1/3 of the final chip, and will focus specially on the zero suppression block architecture. This chip is designed and under fabrication in the 0.18 μ m CIS process. Finally, the readout electronics principle to send out the compressed data flow is also presented taking into account the cluster occupancy per MFT plane for a single central Pb-Pb collision.

Flip chip assembly of thinned chips for hybrid pixel detector applications

International Nuclear Information System (INIS)

Fritzsch, T; Zoschke, K; Rothermund, M; Oppermann, H; Woehrmann, M; Ehrmann, O; Lang, K D; Huegging, F

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump deposition process the glass-readout chip stack is diced in one step. Finally the glass carrier chip is released by laser illumination after flip chip assembly of the readout chip onto sensor tile. The results of the flip chip assembly process development for the ATLAS IBL upgrade are described more in detail. The new ATLAS FEI4B chip with a size of 20 × 19 mm 2 is flip chip bonded with a thickness of only 150 μm, but the capability of this technology has been demonstrated on hybrid modules with a reduced readout chip thickness of down to 50 μm which is a major step for ultra-thin electronic systems

Results of FE65-P2 Pixel Readout Test Chip for High Luminosity LHC Upgrades

CERN Document Server

AUTHOR|(SzGeCERN)394193

2016-01-01

A pixel readout test chip called FE65-P2 has been fabricated on 65 nm CMOS technology. FE65-P2 contains a matrix of 64 x 64 pixels on 50 micron by 50 micron pitch, designed to read out a bump bonded sensor. The goals of FE65-P2 are to demonstrate excellent analog performance isolated from digital activity well enough to achieve 500 electron stable threshold, be radiation hard to at least 500 Mrad, and prove the novel concept of isolated analog front ends embedded in a flat digital design, dubbed “analog islands in a digital sea”. Experience from FE65-P2 and hybrid assemblies will be applied to the design for a large format readout chip, called RD53A, to be produced in a wafer run in early 2017 by the RD53 collaboration. We review the case for 65 nm technology and report on threshold stability test results for the FE65-P2.

Optimised cantilever biosensor with piezoresistive read-out

DEFF Research Database (Denmark)

Rasmussen, Peter; Thaysen, J.; Hansen, Ole

2003-01-01

We present a cantilever-based biochemical sensor with piezoresistive read-out which has been optimised for measuring surface stress. The resistors and the electrical wiring on the chip are encapsulated in low-pressure chemical vapor deposition (LPCVD) silicon nitride, so that the chip is well sui...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)696050; Garelli, N.; Herbst, R.T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A.J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Bartoldus, R.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambe...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

ATLAS CSC Collaboration; The ATLAS collaboration

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgrade during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chamber...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

AUTHOR|(SzGeCERN)664042

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thr...

A New ATLAS Muon CSC Readout System with System on Chip Technology on ATCA Platform

CERN Document Server

Claus, Richard; The ATLAS collaboration

2015-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf thro...

The readout system of the new H1 silicon detectors

International Nuclear Information System (INIS)

Buerger, J.; Hansen, K.; Lange, W.; Prell, S.; Zimmermann, W.; Henschel, H.; Haynes, W.J.; Noyes, G.W.; Joensson, L.; Gabathuler, K.; Horisberger, R.; Wagener, M.; Eichler, R.; Erdmann, W.; Niggli, H.; Pitzl, D.

1995-03-01

The H1 detector at HERA at DESY undergoes presently a major upgrade. In this context silicon strip detectors have been installed at beginning of 1995. The high bunch crossing frequency of HERA (10.4 MHz) demands a novel readout architecture which includes pipelining, signal processing and data reduction at a very early stage. The front end readout is hierarchically organized. The detector elements are read out by the APC chip which contains an analog pipeline and performs first background subtraction. Up to five readout chips are controlled by a Decoder Chip. The readout processor module (OnSiRoC) operates the detectors, controls the Decoder Chips and performs a first level data reduction. The paper describes the readout architecture of the H1 Silicon Detectors and performance data of the complete readout chain. (orig.)

In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

CERN Multimedia

Saba, A

2006-01-01

2 ladders are connected via a multi layer aluminium polyimide flexible cable with a multi chip module containing several custom designed ASICs. The production of the flexible cable was developed and carrier out at CERN. It provides signal and data lines as well as power to the individual readout chipswith a total thickness of only 220 microns. In the photograph, one can see the interconnection from one readout chip to the flexible cable realized with ultrasonic wire bonds (25 microns).

The FE-I4 Pixel Readout Chip and the IBL Module

Energy Technology Data Exchange (ETDEWEB)

Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

2012-05-01

FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

Fast readout of the COMPASS RICH CsI-MWPC chambers

CERN Document Server

Abbon, P; Deschampbs, H; Kunne, F; Gerasimov, S; Ketzer, B; Konorov, I; Kravtchuk, N; Magnon, A; Neyret, D; Panebianco, S; Paul, S; Rebourgeard, P; Tessaroto, F

2006-01-01

A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with “slow” signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ∼3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5–6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficien...

Readout of the upgraded ALICE-ITS

Science.gov (United States)

Szczepankiewicz, A.; ALICE Collaboration

2016-07-01

The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb-Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

Readout of the upgraded ALICE-ITS

International Nuclear Information System (INIS)

Szczepankiewicz, A.

2016-01-01

The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb–Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

Readout of the upgraded ALICE-ITS

Energy Technology Data Exchange (ETDEWEB)

Szczepankiewicz, A., E-mail: Adam.Szczepankiewicz@cern.ch [CERN, Geneva (Switzerland); Institute of Computer Science, Warsaw University of Technology, Warsaw (Poland)

2016-07-11

The ALICE experiment will undergo a major upgrade during the second long shutdown of the CERN LHC. As part of this program, the present Inner Tracking System (ITS), which employs different layers of hybrid pixels, silicon drift and strip detectors, will be replaced by a completely new tracker composed of seven layers of monolithic active pixel sensors. The upgraded ITS will have more than twelve billion pixels in total, producing 300 Gbit/s of data when tracking 50 kHz Pb–Pb events. Two families of pixel chips realized with the TowerJazz CMOS imaging process have been developed as candidate sensors: the ALPIDE, which uses a proprietary readout and sparsification mechanism and the MISTRAL-O, based on a proven rolling shutter architecture. Both chips can operate in continuous mode, with the ALPIDE also supporting triggered operations. As the communication IP blocks are shared among the two chip families, it has been possible to develop a common Readout Electronics. All the sensor components (analog stages, state machines, buffers, FIFOs, etc.) have been modelled in a system level simulation, which has been extensively used to optimize both the sensor and the whole readout chain design in an iterative process. This contribution covers the progress of the R&D efforts and the overall expected performance of the ALICE-ITS readout system.

Latest generation of ASICs for photodetector readout

Science.gov (United States)

Seguin-Moreau, N.

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

Latest generation of ASICs for photodetector readout

Energy Technology Data Exchange (ETDEWEB)

Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

2013-08-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

Latest generation of ASICs for photodetector readout

International Nuclear Information System (INIS)

Seguin-Moreau, N.

2013-01-01

The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

Analyses of test beam data for the ATLAS upgrade readout chip (ABC130)

Energy Technology Data Exchange (ETDEWEB)

Peschke, Richard [DESY, Hamburg (Germany); Collaboration: ATLAS-Collaboration

2015-07-01

As part of the ATLAS phase II upgrade it is planned to replace the current tracker with an all silicon tracker. The outer part of the new tracker will consist of silicon strip detectors. For the readout of the strip detector a new Analog to Binary Converter chip (ABC130) was designed. The chip is processed in the 130 nm technology. In laboratory measurements the preamplifier of the new ABC130 showed a significant lower gain than expected. From the measurements in the laboratory it was not possible to distinguish if the malfunction is in the preamplifier or in the test circuit. Therefore an unbiased test was mandatory. Among other measurements, one was a test beam campaign at the Stanford Linear Accelerator Collider (SLAC). The result of measurement is shown in the presentation.

Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

Energy Technology Data Exchange (ETDEWEB)

Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

2015-07-01

The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

A readout system for position sensitive measurements of X-ray using silicon strip detectors

CERN Document Server

Dabrowski, W; Grybos, P; Idzik, M; Kudlaty, J

2000-01-01

In this paper we describe the development of a readout system for X-ray measurements using silicon strip detectors. The limitation concerning the inherent spatial resolution of silicon strip detectors has been evaluated by Monte Carlo simulation and the results are discussed. The developed readout system is based on the binary readout architecture and consists of two ASICs: RX32 front-end chip comprising 32 channels of preamplifiers, shapers and discriminators, and COUNT32 counter chip comprising 32 20-bit asynchronous counters and the readout logic. This work focuses on the design and performance of the front-end chip. The RX32 chip has been optimised for a low detector capacitance, in the range of 1-3 pF, and high counting rate applications. It can be used with DC coupled detectors allowing the leakage current up to a few nA per strip. For the prototype chip manufactured in a CMOS process all basic parameters have been evaluated by electronic measurements. The noise below 140 el rms has been achieved for a ...

A Zinc Oxide Nanorod Ammonia Microsensor Integrated with a Readout Circuit on-a-Chip

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2011-11-01

Full Text Available A zinc oxide nanorod ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process was investigated. The structure of the ammonia sensor is composed of a sensitive film and polysilicon electrodes. The ammonia sensor requires a post-process to etch the sacrificial layer, and to coat the sensitive film on the polysilicon electrodes. The sensitive film that is prepared by a hydrothermal method is made of zinc oxide. The sensor resistance changes when the sensitive film adsorbs or desorbs ammonia gas. The readout circuit is used to convert the sensor resistance into the voltage output. Experiments show that the ammonia sensor has a sensitivity of about 1.5 mV/ppm at room temperature.

Fast readout of the COMPASS RICH CsI-MWPC photon chambers

International Nuclear Information System (INIS)

Abbon, P.; Delagnes, E.; Deschamps, H.; Kunne, F.; Gerasimov, S.; Ketzer, B.; Konorov, I.; Kravtchuk, N.; Magnon, A.; Neyret, D.; Panebianco, S.; Paul, S.; Rebourgeard, P.; Tessaroto, F.

2006-01-01

A new readout system for CsI-coated MWPCs, used in the COMPASS RICH detector, has been proposed and tested in nominal high-rate conditions. It is based on the APV25-S1 analog sampling chip, and will replace the Gassiplex chip readout used up to now. The APV chip, originally designed for silicon microstrip detectors, is shown to perform well even with 'slow' signals from a MWPC, keeping a signal-to-noise ratio of 9. For every trigger the system reads three consecutive in-time samples, thus allowing to extract information on the signal shape and its timing. The effective time window is reduced from ∼3 μs for the Gassiplex to below 400 ns for the APV25-S1 chip, reducing pile-up events at high particle rate. A significant improvement of the signal-to-background ratio by a factor 5-6 with respect to the original readout has been measured in the central region of the RICH detector. Due to its pipelined architecture, the new readout system also considerably reduces the dead time per event, allowing efficient data taking at higher trigger rate

Flip chip assembly of thinned chips for hybrid pixel detector applications

CERN Document Server

Fritzsch, T; Woehrmann, M; Rothermund, M; Huegging, F; Ehrmann, O; Oppermann, H; Lang, K.D

2014-01-01

There is a steady trend to ultra-thin microelectronic devices. Especially for future particle detector systems a reduced readout chip thickness is required to limit the loss of tracking precision due to scattering. The reduction of silicon thickness is performed at wafer level in a two-step thinning process. To minimize the risk of wafer breakage the thinned wafer needs to be handled by a carrier during the whole process chain of wafer bumping. Another key process is the flip chip assembly of thinned readout chips onto thin sensor tiles. Besides the prevention of silicon breakage the minimization of chip warpage is one additional task for a high yield and reliable flip chip process. A new technology using glass carrier wafer will be described in detail. The main advantage of this technology is the combination of a carrier support during wafer processing and the chip support during flip chip assembly. For that a glass wafer is glue-bonded onto the backside of the thinned readout chip wafer. After the bump depo...

Image processing system design for microcantilever-based optical readout infrared arrays

Science.gov (United States)

Tong, Qiang; Dong, Liquan; Zhao, Yuejin; Gong, Cheng; Liu, Xiaohua; Yu, Xiaomei; Yang, Lei; Liu, Weiyu

2012-12-01

Compared with the traditional infrared imaging technology, the new type of optical-readout uncooled infrared imaging technology based on MEMS has many advantages, such as low cost, small size, producing simple. In addition, the theory proves that the technology's high thermal detection sensitivity. So it has a very broad application prospects in the field of high performance infrared detection. The paper mainly focuses on an image capturing and processing system in the new type of optical-readout uncooled infrared imaging technology based on MEMS. The image capturing and processing system consists of software and hardware. We build our image processing core hardware platform based on TI's high performance DSP chip which is the TMS320DM642, and then design our image capturing board based on the MT9P031. MT9P031 is Micron's company high frame rate, low power consumption CMOS chip. Last we use Intel's company network transceiver devices-LXT971A to design the network output board. The software system is built on the real-time operating system DSP/BIOS. We design our video capture driver program based on TI's class-mini driver and network output program based on the NDK kit for image capturing and processing and transmitting. The experiment shows that the system has the advantages of high capturing resolution and fast processing speed. The speed of the network transmission is up to 100Mbps.

Intensity-based readout of resonant-waveguide grating biosensors: Systems and nanostructures

Science.gov (United States)

Paulsen, Moritz; Jahns, Sabrina; Gerken, Martina

2017-09-01

Resonant waveguide gratings (RWG) - also called photonic crystal slabs (PCS) - have been established as reliable optical transducers for label-free biochemical assays as well as for cell-based assays. Current readout systems are based on mechanical scanning and spectrometric measurements with system sizes suitable for laboratory equipment. Here, we review recent progress in compact intensity-based readout systems for point-of-care (POC) applications. We briefly introduce PCSs as sensitive optical transducers and introduce different approaches for intensity-based readout systems. Photometric measurements have been realized with a simple combination of a light source and a photodetector. Recently a 96-channel, intensity-based readout system for both biochemical interaction analyses as well as cellular assays was presented employing the intensity change of a near cut-off mode. As an alternative for multiparametric detection, a camera system for imaging detection has been implemented. A portable, camera-based system of size 13 cm × 4.9 cm × 3.5 cm with six detection areas on an RWG surface area of 11 mm × 7 mm has been demonstrated for the parallel detection of six protein binding kinetics. The signal-to-noise ratio of this system corresponds to a limit of detection of 168 M (24 ng/ml). To further improve the signal-to-noise ratio advanced nanostructure designs are investigated for RWGs. Here, results on multiperiodic and deterministic aperiodic nanostructures are presented. These advanced nanostructures allow for the design of the number and wavelengths of the RWG resonances. In the context of intensity-based readout systems they are particularly interesting for the realization of multi-LED systems. These recent trends suggest that compact point-of-care systems employing disposable test chips with RWG functional areas may reach market in the near future.

Test and improvement of readout system based on APV25 chip for GEM detector

International Nuclear Information System (INIS)

Hu Shouyang; Jian Siyu; Zhou Jing; Shan Chao; Li Xinglong; Li Xia; Li Xiaomei; Zhou Yi

2014-01-01

Gas electron multiplier (GEM) is the most promising position sensitive gas detector. The new generation of readout electronics system includes APV25 front-end card, multi-purpose digitizer (MPD), VME controller and Linux-based acquisition software DAQ. The construction and preliminary test of this readout system were finished, and the ideal data with the system working frequency of 40 MHz and 20 MHz were obtained. The long time running test shows that the system has a very good time-stable ability. Through optimizing the software configuration and improving hardware quality, the noise level was reduced, and the signal noise ratio was improved. (authors)

A Medipix3 readout system based on the National Instruments FlexRIO card and using the LabVIEW programming environment

Science.gov (United States)

Horswell, I.; Gimenez, E. N.; Marchal, J.; Tartoni, N.

2011-01-01

Hybrid silicon photon-counting detectors are becoming standard equipment for many synchrotron applications. The latest in the Medipix family of read-out chips designed as part of the Medipix Collaboration at CERN is the Medipix3, which while maintaining the same pixel size as its predecessor, offers increased functionality and operating modes. The active area of the Medipix3 chip is approx 14mm × 14mm (containing 256 × 256 pixels) which is not large enough for many detector applications, this results in the need to tile many sensors and chips. As a first step on the road to develop such a detector, it was decided to build a prototype single chip readout system to gain the necessary experience in operating a Medipix3 chip. To provide a flexible learning and development tool it was decided to build an interface based on the recently released FlexRIOTM system from National Instruments and to use the LabVIEWTM graphical programming environment. This system and the achieved performance are described in this paper.

A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

Energy Technology Data Exchange (ETDEWEB)

Irmler, C., E-mail: christian.irmler@oeaw.ac.at [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Bergauer, T.; Frankenberger, A.; Friedl, M.; Gfall, I. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria); Higuchi, T. [University of Tokyo, Kavli Institute for Physics and Mathematics of the Universe, 5-1-5 Kashiwanoha, Kashiwa, Chiba 277-8583 (Japan); Ishikawa, A. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Joo, C. [Seoul National University, High Energy Physics Laboratory, 25-107 Shinlim-dong, Kwanak-gu, Seoul 151-742 (Korea, Republic of); Kah, D.H.; Kang, K.H. [Kyungpook National University, Department of Physics, 1370 Sankyuk Dong, Buk Gu, Daegu 702-701 (Korea, Republic of); Rao, K.K. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Kato, E. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Mohanty, G.B. [Tata Institute of Fundamental Research, Experimental High Energy Physics Group, Homi Bhabha Road, Mumbai 400 005 (India); Negishi, K. [Tohoku University, Department of Physics, Aoba Aramaki Aoba-ku, Sendai 980-8578 (Japan); Onuki, Y.; Shimizu, N. [University of Tokyo, Department of Physics, 7-3-1 Hongo, Bunkyo-ku, Tokyo 113-0033 (Japan); Tsuboyama, T. [KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Valentan, M. [HEPHY Vienna – Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, A-1050 Vienna (Austria)

2013-12-21

B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure. In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor. This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO{sub 2} system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder. We present the concept and the assembly procedure of the Origami chip-on-sensor modules.

A Low Mass On-Chip Readout Scheme for Double-Sided Silicon Strip Detectors

International Nuclear Information System (INIS)

Irmler, C.; Bergauer, T.; Frankenberger, A.; Friedl, M.; Gfall, I.; Higuchi, T.; Ishikawa, A.; Joo, C.; Kah, D.H.; Kang, K.H.; Rao, K.K.; Kato, E.; Mohanty, G.B.; Negishi, K.; Onuki, Y.; Shimizu, N.; Tsuboyama, T.; Valentan, M.

2013-01-01

B-factories like the KEKB in Tsukuba, Japan, operate at relatively low energies and thus require detectors with very low material budget in order to minimize multiple scattering. On the other hand, front-end chips with short shaping time like the APV25 have to be placed as close to the sensor strips as possible to reduce the capacitive load, which mainly determines the noise figure. In order to achieve both – minimal material budget and low noise – we developed a readout scheme for double-sided silicon detectors, where the APV25 chips are placed on a flexible circuit, which is glued onto the top side of the sensor. The bottom-side strips are connected by two flexible circuits, which are bent around the edge of the sensor. This so-called “Origami” design will be utilized to build the Silicon Vertex Detector of the Belle II experiment, which will consist of four layers made from ladders with up to five double-sided silicon strip sensors in a row. Each ladder will be supported by two ribs made of a carbon fiber and Airex foam core sandwich. The heat dissipated by the front-end chips will be removed by a highly efficient two-phase CO 2 system. Thanks to the Origami concept, all APV25 chips are aligned in a row and thus can be cooled by a single thin cooling pipe per ladder. We present the concept and the assembly procedure of the Origami chip-on-sensor modules

An optical fiber-based flexible readout system for micro-pattern gas detectors

Science.gov (United States)

Li, C.; Feng, C. Q.; Zhu, D. Y.; Liu, S. B.; An, Q.

2018-04-01

This paper presents an optical fiber-based readout system that is intended to provide a general purpose multi-channel readout solution for various Micro-Pattern Gas Detectors (MPGDs). The proposed readout system is composed of several front-end cards (FECs) and a data collection module (DCM). The FEC exploits the capability of an existing 64-channel generic TPC readout ASIC chip, named AGET, to implement 256 channels readout. AGET offers FEC a large flexibility in gain range (4 options from 120 fC to 10 pC), peaking time (16 options from 50 ns to 1 us) and sampling freqency (100 MHz max.). The DCM contains multiple 1 Gbps optical fiber serial link interfaces that allow the system scaling up to 1536 channels with 6 FECs and 1 DCM. Further scaling up is possible through cascading of multiple DCMs, by configuring one DCM as a master while other DCMs in slave mode. This design offers a rapid readout solution for different application senario. Tests indicate that the nonlinearity of each channel is less than 1%, and the equivalent input noise charge is typically around 0.7 fC in RMS (root mean square), with a noise slope of about 0.01 fC/pF. The system level trigger rate limit is about 700 Hz in all channel readout mode. When in hit channel readout mode, supposing that typically 10 percent of channels are fired, trigger rate can go up to about 7 kHz. This system has been tested with Micromegas detector and GEM detector, confirming its capability in MPGD readout. Details of hardware and FPGA firmware design, as well as system performances, are described in the paper.

The PASTA chip. A free-running readout ASIC for silicon strip sensors in PANDA

Energy Technology Data Exchange (ETDEWEB)

Goerres, Andre; Stockmanns, Tobias; Ritman, James [Forschungszentrum Juelich GmbH, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2015-07-01

The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using anti pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does an event selection based on the complete raw data of the detector. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. All this has to be done with a very low power design (<4 mW/ch) on a small footprint with less than 21 mm{sup 2} and 60 μm input pitch for 64 channels per chip. Therefore, a simple, time-based readout approach with two independent thresholds is chosen. In this talk, the conceptual design of the full front-end and some aspects of the digital part are presented.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Science.gov (United States)

Claus, R.; ATLAS Collaboration

2016-07-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

International Nuclear Information System (INIS)

Claus, R.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Science.gov (United States)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R. T.; Huffer, M.; Iakovidis, G.; Iordanidou, K.; Kwan, K.; Kocian, M.; Lankford, A. J.; Moschovakos, P.; Nelson, A.; Ntekas, K.; Ruckman, L.; Russell, J.; Schernau, M.; Schlenker, S.; Su, D.; Valderanis, C.; Wittgen, M.; Yildiz, S. C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2.

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

International Nuclear Information System (INIS)

Bartoldus, R.; Claus, R.; Garelli, N.; Herbst, R.T.; Huffer, M.; Kocian, M.; Ruckman, L.; Russell, J.; Su, D.; Wittgen, M.; Iakovidis, G.; Iordanidou, K.; Moschovakos, P.; Ntekas, K.; Kwan, K.; Lankford, A.J.; Nelson, A.; Schernau, M.; Schlenker, S.; Valderanis, C.

2016-01-01

The ATLAS muon Cathode Strip Chamber (CSC) backend readout system has been upgraded during the LHC 2013-2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run-2 luminosity. The readout design is based on the Reconfigurable Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the Advanced Telecommunication Computing Architecture (ATCA) platform. The RCE design is based on the new System on Chip XILINX ZYNQ series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources. Together with auxiliary memories, all these components form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the ZYNQ for high speed input and output fiberoptic links and TTC allowed the full system of 320 input links from the 32 chambers to be processed by 6 COBs in one ATCA shelf. The full system was installed in September 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning for LHC Run 2

A new ATLAS muon CSC readout system with system on chip technology on ATCA platform

Energy Technology Data Exchange (ETDEWEB)

Claus, R., E-mail: claus@slac.stanford.edu

2016-07-11

The ATLAS muon Cathode Strip Chamber (CSC) back-end readout system has been upgraded during the LHC 2013–2015 shutdown to be able to handle the higher Level-1 trigger rate of 100 kHz and the higher occupancy at Run 2 luminosity. The readout design is based on the Reconfiguration Cluster Element (RCE) concept for high bandwidth generic DAQ implemented on the ATCA platform. The RCE design is based on the new System on Chip Xilinx Zynq series with a processor-centric architecture with ARM processor embedded in FPGA fabric and high speed I/O resources together with auxiliary memories to form a versatile DAQ building block that can host applications tapping into both software and firmware resources. The Cluster on Board (COB) ATCA carrier hosts RCE mezzanines and an embedded Fulcrum network switch to form an online DAQ processing cluster. More compact firmware solutions on the Zynq for G-link, S-link and TTC allowed the full system of 320 G-links from the 32 chambers to be processed by 6 COBs in one ATCA shelf through software waveform feature extraction to output 32 S-links. The full system was installed in Sept. 2014. We will present the RCE/COB design concept, the firmware and software processing architecture, and the experience from the intense commissioning towards LHC Run 2.

Strip detectors read-out system user's guide

International Nuclear Information System (INIS)

Claus, G.; Dulinski, W.; Lounis, A.

1996-01-01

The Strip Detector Read-out System consists of two VME modules: SDR-Flash and SDR-seq completed by a fast logic SDR-Trig stand alone card. The system is a self-consistent, cost effective and easy use solution for the read-out of analog multiplexed signals coming from some of the front-end electronics chips (Viking/VA chips family, Premus 128 etc...) currently used together with solid (silicon) or gas microstrip detectors. (author)

Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

Energy Technology Data Exchange (ETDEWEB)

Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

2000-03-01

New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

LHC1: a semiconductor pixel detector readout chip with internal, tunable delay providing a binary pattern of selected events

International Nuclear Information System (INIS)

Heijne, E.H.M.; Antinori, F.; Barberis, D.

1996-01-01

The Omega3/LHC1 pixel detector readout chip comprises a matrix of 128 x 16 readout cells of 50 μm x 500 μm and peripheral functions with 4 distinct modes of initialization and operation, together more than 800 000 transistors. Each cell contains a complete chain of amplifier, discriminator with adjustable threshold and fast-OR output, a globally adjustable delay with local fine-tuning, coincidence logic and memory. Every cell can be individually addressed for electrical test and masking. First results have been obtained from electrical tests of a chip without detector as well as from source measurements. The electronic noise without detector is ∼100 e - rms. The lowest threshold setting is close to 2000 e - and non-uniformity has been measured to be better than 450 e - rms at 5000 e - threshold. A timewalk of <10 ns and a precision of <6 ns rms on a delay of 2 μs have been measured. The results may be improved by further optimization. (orig.)

A novel readout integrated circuit for ferroelectric FPA detector

Science.gov (United States)

Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

2017-11-01

Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

Microcontroller based four-channel current readout unit for beam slit monitor

International Nuclear Information System (INIS)

Holikatti, A.C.; Puntambekar, T.A.; Pithawa, C.K.

2009-01-01

This paper describes the design and development of a microcontroller based four-channel current readout unit for Beam Slit Monitor (BSM) installed in Transport Line-1 of Indus Accelerator Complex. BSM is a diagnostic device consisting of two horizontal and two vertical blades, which can be moved independently in to the beam pipe to cut the beam transversely. The readout unit employs switched integrators with reset, hold and select switches and timing and control unit. It integrates the current output of the four blades of BSM and produces an output corresponding to the beam charge intercepted by the blade. The integrator outputs are then multiplexed and digitized using 12-bit ADC. Acquired digital data from ADC is stored into on-chip RAM of the microcontroller. The readout sequence is synchronized with the Microtron beam-timing signal. The timing of integration, hold and reset cycles is controlled by the microcontroller. The unit is connected on a serial link to the host computer in main control room. This unit has been integrated with the BSM system and is being used to obtain the electron beam profile. (author)

A fast and reliable readout method for quantitative analysis of surface-enhanced Raman scattering nanoprobes on chip surface

Energy Technology Data Exchange (ETDEWEB)

Chang, Hyejin; Jeong, Sinyoung; Ko, Eunbyeol; Jeong, Dae Hong, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Chemistry Education, Seoul National University, Seoul 151-742 (Korea, Republic of); Kang, Homan [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Yoon-Sik, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Interdisciplinary Program in Nano-Science and Technology, Seoul National University, Seoul 151-742 (Korea, Republic of); School of Chemical and Biological Engineering, Seoul National University, Seoul 151-742 (Korea, Republic of); Lee, Ho-Young, E-mail: yslee@snu.ac.kr, E-mail: debobkr@gmail.com, E-mail: jeongdh@snu.ac.kr [Department of Nuclear Medicine, Seoul National University Bundang Hospital, Seongnam 463-707 (Korea, Republic of)

2015-05-15

Surface-enhanced Raman scattering techniques have been widely used for bioanalysis due to its high sensitivity and multiplex capacity. However, the point-scanning method using a micro-Raman system, which is the most common method in the literature, has a disadvantage of extremely long measurement time for on-chip immunoassay adopting a large chip area of approximately 1-mm scale and confocal beam point of ca. 1-μm size. Alternative methods such as sampled spot scan with high confocality and large-area scan method with enlarged field of view and low confocality have been utilized in order to minimize the measurement time practically. In this study, we analyzed the two methods in respect of signal-to-noise ratio and sampling-led signal fluctuations to obtain insights into a fast and reliable readout strategy. On this basis, we proposed a methodology for fast and reliable quantitative measurement of the whole chip area. The proposed method adopted a raster scan covering a full area of 100 μm × 100 μm region as a proof-of-concept experiment while accumulating signals in the CCD detector for single spectrum per frame. One single scan with 10 s over 100 μm × 100 μm area yielded much higher sensitivity compared to sampled spot scanning measurements and no signal fluctuations attributed to sampled spot scan. This readout method is able to serve as one of key technologies that will bring quantitative multiplexed detection and analysis into practice.

Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

CERN Document Server

Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

2009-01-01

In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

LHCb - SALT, a dedicated readout chip for strip detectors in the LHCb Upgrade experiment

CERN Multimedia

Swientek, Krzysztof Piotr

2015-01-01

Silicon strip detectors in the upgraded Tracker of LHCb experiment will require a new readout 128-channel ASIC called SALT. It will extract and digitise analogue signals from the sensor, perform digital processing and transmit serial output data. SALT is designed in CMOS 130 nm process and uses a novel architecture comprising of analogue front-end and ultra-low power ($<$0.5 mW) fast (40 MSps) sampling 6-bit ADC in each channel. A prototype of first 8-channel version of SALT chip, comprising all important functionalities, was submitted. Its design and possibly first tests results will be presented.

Effect of gamma irradiation on leakage current in CMOS read-out chips for the ATLAS upgrade silicon strip tracker at the HL-LHC

CERN Document Server

Stucci, Stefania Antonia; Lynn, Dave; Kierstead, James; Kuczewski, Philip; van Nieuwenhuizen, Gerrit J; Rosin, Guy; Tricoli, Alessandro

2017-01-01

The increase of the leakage current of NMOS transistors in detector readout chips in certain 130 nm CMOS technologies during exposure to ionising radiation needs special consideration in the design of detector systems, as this can result in a large increase of the supply current and power dissipation. As part of the R&D; program for the upgrade of the ATLAS inner detector tracker for the High Luminosity upgrade of the LHC at CERN, a dedicated set of irradiations have been carried out with the $^60$Co gamma-ray source at the Brookhaven National Laboratory. Measurements will be presented that characterise the increase in the digital leakage current in the 130 nm-technology ABC130 readout chips. The variation of the current as a function of time and total ionising dose has been studied under various conditions of dose rate, temperature and power applied to the chip. The range of variation of dose rates and temperatures has been set to be close to those expected at the High Luminosity LHC, i.e. in the range 0...

FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

2004-01-01

A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

MEMS capacitive pressure sensor monolithically integrated with CMOS readout circuit by using post CMOS processes

Science.gov (United States)

Jang, Munseon; Yun, Kwang-Seok

2017-12-01

In this paper, we presents a MEMS pressure sensor integrated with a readout circuit on a chip for an on-chip signal processing. The capacitive pressure sensor is formed on a CMOS chip by using a post-CMOS MEMS processes. The proposed device consists of a sensing capacitor that is square in shape, a reference capacitor and a readout circuitry based on a switched-capacitor scheme to detect capacitance change at various environmental pressures. The readout circuit was implemented by using a commercial 0.35 μm CMOS process with 2 polysilicon and 4 metal layers. Then, the pressure sensor was formed by wet etching of metal 2 layer through via hole structures. Experimental results show that the MEMS pressure sensor has a sensitivity of 11 mV/100 kPa at the pressure range of 100-400 kPa.

Study of multi-channel readout ASIC and its discrete module for particle detector

International Nuclear Information System (INIS)

Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

2013-01-01

Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2009-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2007-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

Implementation of the Timepix ASIC in the Scalable Readout System

Energy Technology Data Exchange (ETDEWEB)

Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

2016-09-11

We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

GOSSIPO-4: Evaluation of a Novel PLL-Based TDC-Technique for the Readout of GridPix-Detectors

CERN Document Server

Brezina, C; Zappon, F; Van Beuzekom, M; Campbell, M; Desch, K; Van der Graaf, H; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Zivkovic, V

2014-01-01

The direct readout of Micro-Pattern Gaseous Detectors (MPGDs) with bare pixel chips introduces the need for a new generation of readout electronics featuring a high spatial granularity as well as a highly accurate time measurement in each pixel. GOSSIPO-4, fabricated in a 130 nm CMOS technology, is a demonstrator ASIC investigating the potential of a new TDC-concept that is based on a chip-wide 40 MHz clock which is complemented by an additional 640 MHz clock. The latter is created upon demand by local oscillators distributed across the pixel matrix. PLL tuning of the local oscillators allows for automatic compensation of frequency fluctuations caused by process parameter, supply voltage and temperature variations. The developed PLL locks within s and achieves a duty cycle of 50.75% with a time interval error of only 23.4 ps. Mean DNL and INL of the TDC are less than 20% of the time bin size of 1.56 ns under all anticipated conditions.

Evaluation of 320x240 pixel LEC GaAs Schottky barrier X-ray imaging arrays, hybridized to CMOS readout circuit based on charge integration

CERN Document Server

Irsigler, R; Alverbro, J; Borglind, J; Froejdh, C; Helander, P; Manolopoulos, S; O'Shea, V; Smith, K

1999-01-01

320x240 pixels GaAs Schottky barrier detector arrays were fabricated, hybridized to silicon readout circuits, and subsequently evaluated. The detector chip was based on semi-insulating LEC GaAs material. The square shaped pixel detector elements were of the Schottky barrier type and had a pitch of 38 mu m. The GaAs wafers were thinned down prior to the fabrication of the ohmic back contact. After dicing, the chips were indium bump, flip-chip bonded to CMOS readout circuits based on charge integration, and finally evaluated. A bias voltage between 50 and 100 V was sufficient to operate the detector. Results on I-V characteristics, noise behaviour and response to X-ray radiation are presented. Images of various objects and slit patterns were acquired by using a standard dental imaging X-ray source. The work done was a part of the XIMAGE project financed by the European Community (Brite-Euram). (author)

FE-I4 pixel chip characterization with USBpix3 test system

Energy Technology Data Exchange (ETDEWEB)

Filimonov, Viacheslav; Gonella, Laura; Hemperek, Tomasz; Huegging, Fabian; Janssen, Jens; Krueger, Hans; Pohl, David-Leon; Wermes, Norbert [University of Bonn, Bonn (Germany)

2015-07-01

The USBpix readout system is a small and light weighting test system for the ATLAS pixel readout chips. It is widely used to operate and characterize FE-I4 pixel modules in lab and test beam environments. For multi-chip modules the resources on the Multi-IO board, that is the central control unit of the readout system, are coming to their limits, which makes the simultaneous readout of more than one chip at a time challenging. Therefore an upgrade of the current USBpix system has been developed. The upgraded system is called USBpix3 - the main focus of the talk. Characterization of single chip FE-I4 modules was performed with USBpix3 prototype (digital, analog, threshold and source scans; tuning). PyBAR (Bonn ATLAS Readout in Python scripting language) was used as readout software. PyBAR consists of FEI4 DAQ and Data Analysis Libraries in Python. The presentation describes the USBpix3 system, results of FE-I4 modules characterization and preparation for the multi-chip module and multi-module readout with USBpix3.

A compact readout system for multi-pixel hybrid photodiodes

International Nuclear Information System (INIS)

Datema, C.P.; Meng, L.J.; Ramsden, D.

1999-01-01

Although the first Multi-pixel Hybrid Photodiode (M-HPD) was developed in the early 1990s by Delft Electronic Products, the main obstacle to its application has been the lack of availability of a compact read-out system. A fast, parallel readout system has been constructed for use with the earlier 25-pixel tube with High-energy Physics applications in mind. The excellent properties of the recently developed multi-pixel hybrid photodiodes (M-HPD) will be easier to exploit following the development of the new hybrid read-out circuits described in this paper. This system will enable all of the required read-out functions to be accommodate on a single board into which the M-HPD is plugged. The design and performance of a versatile system is described in which a trigger-signal, derived from the common-side of the silicon anode in the M-HPD, is used to trigger the readout of the 60-anode pixels in the M-HPD. The multi-channel amplifier section is based on the use of a new, commercial VLSI chip, whilst the read-out sequencer uses a chip of its own design. The common anode signal is processed by a fast amplifier and discriminator to provide a trigger signal when a single event is detected. In the prototype version, the serial analogue output data-stream is processed using a PC-mounted, high speed ADC. Results obtained using the new read-out system in a compact gamma-camera and with a small muon tracking-chamber demonstrate the low-noise performance of the system. The application of this read-out system in other position-sensitive or multi-anode photomultiplier tube applications are also described

The RD53 Collaboration's SystemVerilog-UVM Simulation Framework and its General Applicability to Design of Advanced Pixel Readout Chips

CERN Document Server

Marconi, S.; Placidi, P.; Christiansen, J.; Hemperek, T.

2014-01-01

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger late...

Design and realisation of integrated circuits for the readout of pixel sensors in high-energy physics and biomedical imaging

Energy Technology Data Exchange (ETDEWEB)

Peric, I.

2004-08-01

Radiation tolerant pixel-readout chip for the ATLAS pixel detector has been designed, implemented in a deep-submicron CMOS technology and successfully tested. The chip contains readout-channels with complex analog and digital circuits. Chip for steering of the DEPFET active-pixel matrix has been implemented in a high-voltage CMOS technology. The chip contains channels which generate fast sequences of high-voltage signals. Detector containing this chip has been successfully tested. Pixel-readout test chip for an X-ray imaging pixel sensor has been designed, implemented in a CMOS technology and tested. Pixel-readout channels are able to simultaneously count the signals generated by passage of individual photons and to sum the total charge generated during exposure time. (orig.)

Cobalt Oxide Nanosheet and CNT Micro Carbon Monoxide Sensor Integrated with Readout Circuit on Chip

Directory of Open Access Journals (Sweden)

Ching-Liang Dai

2010-03-01

Full Text Available The study presents a micro carbon monoxide (CO sensor integrated with a readout circuit-on-a-chip manufactured by the commercial 0.35 μm complementary metal oxide semiconductor (CMOS process and a post-process. The sensing film of the sensor is a composite cobalt oxide nanosheet and carbon nanotube (CoOOH/CNT film that is prepared by a precipitation-oxidation method. The structure of the CO sensor is composed of a polysilicon resistor and a sensing film. The sensor, which is of a resistive type, changes its resistance when the sensing film adsorbs or desorbs CO gas. The readout circuit is used to convert the sensor resistance into the voltage output. The post-processing of the sensor includes etching the sacrificial layers and coating the sensing film. The advantages of the sensor include room temperature operation, short response/recovery times and easy post-processing. Experimental results show that the sensitivity of the CO sensor is about 0.19 mV/ppm, and the response and recovery times are 23 s and 34 s for 200 ppm CO, respectively.

Investigation of image distortion due to MCP electronic readout misalignment and correction via customized GUI application

Science.gov (United States)

Vitucci, G.; Minniti, T.; Tremsin, A. S.; Kockelmann, W.; Gorini, G.

2018-04-01

The MCP-based neutron counting detector is a novel device that allows high spatial resolution and time-resolved neutron radiography and tomography with epithermal, thermal and cold neutrons. Time resolution is possible by the high readout speeds of ~ 1200 frames/sec, allowing high resolution event counting with relatively high rates without spatial resolution degradation due to event overlaps. The electronic readout is based on a Timepix sensor, a CMOS pixel readout chip developed at CERN. Currently, a geometry of a quad Timepix detector is used with an active format of 28 × 28 mm2 limited by the size of the Timepix quad (2 × 2 chips) readout. Measurements of a set of high-precision micrometers test samples have been performed at the Imaging and Materials Science & Engineering (IMAT) beamline operating at the ISIS spallation neutron source (U.K.). The aim of these experiments was the full characterization of the chip misalignment and of the gaps between each pad in the quad Timepix sensor. Such misalignment causes distortions of the recorded shape of the sample analyzed. We present in this work a post-processing image procedure that considers and corrects these effects. Results of the correction will be discussed and the efficacy of this method evaluated.

Study of preamplifier, shaper and peak detector in readout ASIC for particle detector

International Nuclear Information System (INIS)

Wang Ke; Zhang Shengjun; Fan Lei; Li Xian

2014-01-01

Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout system and ASICs have been designed in China now. This project designed a multi-channel readout ASIC for general detector. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured, results will be reported in time. (authors)

Status of readout integrated circuits for radiation detector

International Nuclear Information System (INIS)

Moon, B. S.; Hong, S. B.; Cheng, J. E. and others

2001-09-01

In this report, we describe the current status of readout integrated circuits developed for radiation detectors, along with new technologies being applied to this field. The current status of ASCIC chip development related to the readout electronics is also included in this report. Major sources of this report are from product catalogs and web sites of the related industries. In the field of semiconductor process technology in Korea, the current status of the multi-project wafer(MPW) of IDEC, the multi-project chip(MPC) of ISRC and other domestic semiconductor process industries is described. In the case of other countries, the status of the MPW of MOSIS in USA and the MPW of EUROPRACTICE in Europe is studied. This report also describes the technologies and products of readout integrated circuits of industries worldwide

Data readout system utilizing photonic integrated circuit

Energy Technology Data Exchange (ETDEWEB)

Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

2013-10-11

We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

CERN Document Server

Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

2012-01-01

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

High-speed readout of high-Z pixel detectors with the LAMBDA detector

International Nuclear Information System (INIS)

Pennicard, D.; Smoljanin, S.; Sheviakov, I.; Xia, Q.; Rothkirch, A.; Yu, Y.; Struth, B.; Hirsemann, H.; Graafsma, H.

2014-01-01

High-frame-rate X-ray pixel detectors make it possible to perform time-resolved experiments at synchrotron beamlines, and to make better use of these sources by shortening experiment times. LAMBDA is a photon-counting hybrid pixel detector based on the Medipix3 chip, designed to combine a small pixel size of 55 μm, a large tileable module design, high speed, and compatibility with ''high-Z'' sensors for hard X-ray detection. This technical paper focuses on LAMBDA's high-speed-readout functionality, which allows a frame rate of 2000 frames per second with no deadtime between successive images. This takes advantage of the Medipix3 chip's ''continuous read-write'' function and highly parallelised readout. The readout electronics serialise this data and send it back to a server PC over two 10 Gigabit Ethernet links. The server PC controls the detector and receives, processes and stores the data using software designed for the Tango control system. As a demonstration of high-speed readout of a high-Z sensor, a GaAs LAMBDA detector was used to make a high-speed X-ray video of a computer fan

Characterization of Ni/SnPb-TiW/Pt Flip Chip Interconnections in Silicon Pixel Detector Modules

CERN Document Server

Karadzhinova, Aneliya; Härkönen, Jaakko; Luukka, Panja-riina; Mäenpää, Teppo; Tuominen, Eija; Haeggstrom, Edward; Kalliopuska, Juha; Vahanen, Sami; Kassamakov, Ivan

2014-01-01

In contemporary high energy physics experiments, silicon detectors are essential for recording the trajectory of new particles generated by multiple simultaneous collisions. Modern particle tracking systems may feature 100 million channels, or pixels, which need to be individually connected to read-out chains. Silicon pixel detectors are typically connected to readout chips by flip-chip bonding using solder bumps. High-quality electro-mechanical flip-chip interconnects minimizes the number of dead read-out channels in the particle tracking system. Furthermore, the detector modules must endure handling during installation and withstand heat generation and cooling during operation. Silicon pixel detector modules were constructed by flip-chip bonding 16 readout chips to a single sensor. Eutectic SnPb solder bumps were deposited on the readout chips and the sensor chips were coated with TiW/Pt thin film UBM (under bump metallization). The modules were assembled at Advacam Ltd, Finland. We studied the uniformity o...

The rad-hard readout system of the BaBar silicon vertex tracker

Science.gov (United States)

Re, V.; DeWitt, J.; Dow, S.; Frey, A.; Johnson, R. P.; Kroeger, W.; Kipnis, I.; Leona, A.; Luo, L.; Mandelli, E.; Manfredi, P. F.; Nyman, M.; Pedrali-Noy, M.; Poplevin, P.; Perazzo, A.; Roe, N.; Spencer, N.

1998-02-01

This paper discusses the behaviour of a prototype rad-hard version of the chip developed for the readout of the BaBar silicon vertex tracker. A previous version of the chip, implemented in the 0.8 μm HP rad-soft version has been thoroughly tested in the recent times. It featured outstanding noise characteristics and showed that the specifications assumed as target for the tracker readout were met to a very good extent. The next step was the realization of a chip prototype in the rad-hard process that will be employed in the actual chip production. Such a prototype is structurally and functionally identical to its rad-soft predecessor. However, the process parameters being different, and not fully mastered at the time of design, some deviations in the behaviour were to be expected. The reasons for such deviations have been identified and some of them were removed by acting on the points that were left accessible on the chip. Other required small circuit modifications that will not affect the production schedule. The tests done so far on the rad-hard chip have shown that the noise behaviour is very close to that of the rad-soft version, that is fully adequate for the vertex detector readout.

Pad readout for gas detectors using 128-channel integrated preamplifiers

International Nuclear Information System (INIS)

Fischer, P.; Drees, A.; Glassel, P.

1988-01-01

A novel two-dimensional readout scheme for gas detectors is presented which uses small metal pads with 2.54 mm pitch as an anode. The pads are read out via 128-channel VLSI low-noise preamplifier/multiplexer chips. These chips are mounted on 2.8x2.8 cm/sup 2/ modules which are directly plugged onto the detector backplane, daisy-chained with jumpers and read out sequentially. The readout has been successfully tested with a low-pressure, two-step, TMAE-filled UV-RICH detector prototype. A single electron efficiently of >90% was observed at moderate chamber gains (<10/sup 6/). The method offers high electronic amplification, low noise, and high readout speed with a very flexible and compact design, suited for space-limited applications

Chip cleaning and regeneration for electrochemical sensor arrays

Energy Technology Data Exchange (ETDEWEB)

Bhalla, Vijayender [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Carrara, Sandro, E-mail: sandro.carrara@epfl.c [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy); Stagni, Claudio [Department DEIS, University of Bologna, viale Risorgimento 2, 40136 Bologna (Italy); Samori, Bruno [Biochemistry Department ' G.Moruzzi' , University of Bologna, Via Irnerio 48, 40126 Bologna (Italy)

2010-04-02

Sensing systems based on electrochemical detection have generated great interest because electronic readout may replace conventional optical readout in microarray. Moreover, they offer the possibility to avoid labelling for target molecules. A typical electrochemical array consists of many sensing sites. An ideal micro-fabricated sensor-chip should have the same measured values for all the equivalent sensing sites (or spots). To achieve high reliability in electrochemical measurements, high quality in functionalization of the electrodes surface is essential. Molecular probes are often immobilized by using alkanethiols onto gold electrodes. Applying effective cleaning methods on the chip is a fundamental requirement for the formation of densely-packed and stable self-assembly monolayers. However, the available well-known techniques for chip cleaning may not be so reliable. Furthermore, it could be necessary to recycle the chip for reuse. Also in this case, an effective recycling technique is required to re-obtain well cleaned sensing surfaces on the chip. This paper presents experimental results on the efficacy and efficiency of the available techniques for initial cleaning and further recycling of micro-fabricated chips. Piranha, plasma, reductive and oxidative cleaning methods were applied and the obtained results were critically compared. Some interesting results were attained by using commonly considered cleaning methodologies. This study outlines oxidative electrochemical cleaning and recycling as the more efficient cleaning procedure for electrochemical based sensor arrays.

Emulation and Calibration of the SALT Read-out Chip for the Upstream Tracker for Modernised LHCb Detector

CERN Document Server

Dendek, Adam

2015-01-01

The LHCb is one of the four major experiments currently operating at CERN. The main reason for constructing the LHCb forward spectrometer was a precise measurement of the CP violation in heavy quarks section as well as search for a New Physics. To obtain interesting results, the LHCb is mainly focused on study of B meson decays. Unfortunately, due to the present data acquisition architecture, the LHCb experiment is statistically limited for collecting such events. This fact led the LHCb Collaboration to decide to perform far-reaching upgrade. Key part of this upgrade will be replacement of the TT detector. To perform this action, it was requited to design new tracking detector with entirely new front-end electronics. This detector will be called the Upstream Tracker (UT) and the read-out chip — SALT. This note presents an overall discussion on SALT chip. In particular, the emulation process of the SALT data preformed via the software written by the author.

First considerations for a readout system for the ILD TPC with the Timepix3

Energy Technology Data Exchange (ETDEWEB)

Schiffer, Tobias [Universitaet Bonn (Germany); Collaboration: LCTPC-Deutschland-Collaboration

2016-07-01

For the planned International Linear Collider (ILC) two detectors are proposed. One of them, the International Large Detector (ILD) uses a Time Projektion Chamber (TPC) as the main tracking device. As a readout system for this TPC, pixel chips are one of the considered options. An integrated Micromegas stage is foreseen as gas amplification stage, which is built directly on top of the chip. Since first tests of a Pixel-TPC with 160 Timepix ASICs showed promising results, one is interested in developing a detector using the Timepix3 ASIC. It has several advantages, first of all its feature to measure ToT and a ToA at the same time and its significantly increased readout rate. For this purpose a readout system needs to be developed which fulfils the requirements of the Timpix3 ASIC and also has a high scalability. The main challenges are the high speed readout with a clock of up to 640 MHz and the reliability of the system. Also, the data driven as well as the frame-based readout of the Timepix3 needs to be considered for the implementation. The main goal is to provide a fast and parallel readout of several million channels. An overview and the status of the planning is given. Also, the development challenges are discussed.

An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

International Nuclear Information System (INIS)

Fiorini, C.; Porro, M.

2006-01-01

We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

A Low Noise CMOS Readout Based on a Polymer-Coated SAW Array for Miniature Electronic Nose

Directory of Open Access Journals (Sweden)

Cheng-Chun Wu

2016-10-01

Full Text Available An electronic nose (E-Nose is one of the applications for surface acoustic wave (SAW sensors. In this paper, we present a low-noise complementary metal–oxide–semiconductor (CMOS readout application-specific integrated circuit (ASIC based on an SAW sensor array for achieving a miniature E-Nose. The center frequency of the SAW sensors was measured to be approximately 114 MHz. Because of interference between the sensors, we designed a low-noise CMOS frequency readout circuit to enable the SAW sensor to obtain frequency variation. The proposed circuit was fabricated in Taiwan Semiconductor Manufacturing Company (TSMC 0.18 μm 1P6M CMOS process technology. The total chip size was nearly 1203 × 1203 μm2. The chip was operated at a supply voltage of 1 V for a digital circuit and 1.8 V for an analog circuit. The least measurable difference between frequencies was 4 Hz. The detection limit of the system, when estimated using methanol and ethanol, was 0.1 ppm. Their linearity was in the range of 0.1 to 26,000 ppm. The power consumption levels of the analog and digital circuits were 1.742 mW and 761 μW, respectively.

An inverter-based capacitive trans-impedance amplifier readout with offset cancellation and temporal noise reduction for IR focal plane array

Science.gov (United States)

Chen, Hsin-Han; Hsieh, Chih-Cheng

2013-09-01

This paper presents a readout integrated circuit (ROIC) with inverter-based capacitive trans-impedance amplifier (CTIA) and pseudo-multiple sampling technique for infrared focal plane array (IRFPA). The proposed inverter-based CTIA with a coupling capacitor [1], executing auto-zeroing technique to cancel out the varied offset voltage from process variation, is used to substitute differential amplifier in conventional CTIA. The tunable detector bias is applied from a global external bias before exposure. This scheme not only retains stable detector bias voltage and signal injection efficiency, but also reduces the pixel area as well. Pseudo-multiple sampling technique [2] is adopted to reduce the temporal noise of readout circuit. The noise reduction performance is comparable to the conventional multiple sampling operation without need of longer readout time proportional to the number of samples. A CMOS image sensor chip with 55×65 pixel array has been fabricated in 0.18um CMOS technology. It achieves a 12um×12um pixel size, a frame rate of 72 fps, a power-per-pixel of 0.66uW/pixel, and a readout temporal noise of 1.06mVrms (16 times of pseudo-multiple sampling), respectively.

The Retinal Readout System: a status report A Status Report

CERN Document Server

Litke, A M

1999-01-01

The 'Retinal Readout System' is being developed to study the language the eye uses to send information about the visual world to the brain. Its architecture is based on that of silicon microstrip detectors. An array of 512 microscopic electrodes picks up the signals generated by the output neurons of live retinal tissue in response to a dynamic image focused on the input neurons. These signals are amplified, filtered and multiplexed by a set of eight custom-designed VLSI readout chips, and digitized and recorded by a data acquisition system. This report describes the goals, design, and status of the system. (author)

The RD53 collaboration's SystemVerilog-UVM simulation framework and its general applicability to design of advanced pixel readout chips

International Nuclear Information System (INIS)

Marconi, S; Christiansen, J; Conti, E; Placidi, P; Hemperek, T

2014-01-01

The foreseen Phase 2 pixel upgrades at the LHC have very challenging requirements for the design of hybrid pixel readout chips. A versatile pixel simulation platform is as an essential development tool for the design, verification and optimization of both the system architecture and the pixel chip building blocks (Intellectual Properties, IPs). This work is focused on the implemented simulation and verification environment named VEPIX53, built using the SystemVerilog language and the Universal Verification Methodology (UVM) class library in the framework of the RD53 Collaboration. The environment supports pixel chips at different levels of description: its reusable components feature the generation of different classes of parameterized input hits to the pixel matrix, monitoring of pixel chip inputs and outputs, conformity checks between predicted and actual outputs and collection of statistics on system performance. The environment has been tested performing a study of shared architectures of the trigger latency buffering section of pixel chips. A fully shared architecture and a distributed one have been described at behavioral level and simulated; the resulting memory occupancy statistics and hit loss rates have subsequently been compared

Simulation of digital pixel readout chip architectures with the RD53 SystemVerilog-UVM verification environment using Monte Carlo physics data

International Nuclear Information System (INIS)

Conti, E.; Marconi, S.; Christiansen, J.; Placidi, P.; Hemperek, T.

2016-01-01

The simulation and verification framework developed by the RD53 collaboration is a powerful tool for global architecture optimization and design verification of next generation hybrid pixel readout chips. In this paper the framework is used for studying digital pixel chip architectures at behavioral level. This is carried out by simulating a dedicated, highly parameterized pixel chip description, which makes it possible to investigate different grouping strategies between pixels and different latency buffering and arbitration schemes. The pixel hit information used as simulation input can be either generated internally in the framework or imported from external Monte Carlo detector simulation data. The latter have been provided by both the CMS and ATLAS experiments, featuring HL-LHC operating conditions and the specifications related to the Phase 2 upgrade. Pixel regions and double columns were simulated using such Monte Carlo data as inputs: the performance of different latency buffering architectures was compared and the compliance of different link speeds with the expected column data rate was verified

Evaluation of mixed-signal noise effects in photon-counting X-ray image sensor readout circuits

International Nuclear Information System (INIS)

Lundgren, Jan; Abdalla, Suliman; O'Nils, Mattias; Oelmann, Bengt

2006-01-01

In readout electronics for photon-counting pixel detectors, the tight integration between analog and digital blocks causes the readout electronics to be sensitive to on-chip noise coupling. This noise coupling can result in faulty luminance values in grayscale X-ray images, or as color distortions in a color X-ray imaging system. An exploration of simulating noise coupling in readout circuits is presented which enables the discovery of sensitive blocks at as early a stage as possible, in order to avoid costly design iterations. The photon-counting readout system has been simulated for noise coupling in order to highlight the existing problems of noise coupling in X-ray imaging systems. The simulation results suggest that on-chip noise coupling should be considered and simulated in future readout electronics systems for X-ray detectors

A 240-channel thick film multi-chip module for readout of silicon drift detectors

International Nuclear Information System (INIS)

Lynn, D.; Bellwied, R.; Beuttenmueller, R.; Caines, H.; Chen, W.; DiMassimo, D.; Dyke, H.; Elliott, D.; Grau, M.; Hoffmann, G.W.; Humanic, T.; Jensen, P.; Kleinfelder, S.A.; Kotov, I.; Kraner, H.W.; Kuczewski, P.; Leonhardt, B.; Li, Z.; Liaw, C.J.; LoCurto, G.; Middelkamp, P.; Minor, R.; Mazeh, N.; Nehmeh, S.; O'Conner, P.; Ott, G.; Pandey, S.U.; Pruneau, C.; Pinelli, D.; Radeka, V.; Rescia, S.; Rykov, V.; Schambach, J.; Sedlmeir, J.; Sheen, J.; Soja, B.; Stephani, D.; Sugarbaker, E.; Takahashi, J.; Wilson, K.

2000-01-01

We have developed a thick film multi-chip module for readout of silicon drift (or low capacitance ∼200 fF) detectors. Main elements of the module include a custom 16-channel NPN-BJT preamplifier-shaper (PASA) and a custom 16-channel CMOS Switched Capacitor Array (SCA). The primary design criteria of the module were the minimizations of the power (12 mW/channel), noise (ENC=490 e - rms), size (20.5 mmx63 mm), and radiation length (1.4%). We will discuss various aspects of the PASA design, with emphasis on the preamplifier feedback network. The SCA is a modification of an integrated circuit that has been previously described [1]; its design features specific to its application in the SVT (Silicon Vertex Tracker in the STAR experiment at RHIC) will be discussed. The 240-channel multi-chip module is a circuit with five metal layers fabricated in thick film technology on a beryllia substrate and contains 35 custom and commercial integrated circuits. It has been recently integrated with silicon drift detectors in both a prototype system assembly for the SVT and a silicon drift array for the E896 experiment at the Alternating Gradient Synchrotron at the Brookhaven National Laboratory. We will discuss features of the module's design and fabrication, report the test results, and emphasize its performance both on the bench and under experimental conditions

Readout electronics development for the ATLAS silicon tracker

International Nuclear Information System (INIS)

Borer, K.; Beringer, J.; Anghinolfi, F.; Aspell, P.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Bonino, R.; Clark, A.G.; Kambara, H.; La Marra, D.; Leger, A.; Wu, X.; Richeux, J.P.; Taylor, G.N.; Fedotov, M.; Kuper, E.; Velikzhanin, Yu.; Campbell, D.; Murray, P.; Seller, P.

1995-01-01

We present the status of the development of the readout electronics for the large area silicon tracker of the ATLAS experiment at the LHC, carried out by the CERN RD2 project. Our basic readout concept is to integrate a fast amplifier, analog memory, sparse data scan circuit and analog-to-digital convertor (ADC) on a single VLSI chip. This architecture will provide full analog information of charged particle hits associated unambiguously to one LHC beam crossing, which is expected to be at a frequency of 40 MHz. The expected low occupancy of the ATLAS inner silicon detectors allows us to use a low speed (5 MHz) on-chip ADC with a multiplexing scheme. The functionality of the fast amplifier and analog memory have been demonstrated with various prototype chips. Most recently we have successfully tested improved versions of the amplifier and the analog memory. A piecewise linear ADC has been fabricated and performed satisfactorily up to 5 MHz. A new chip including amplifier, analog memory, memory controller, ADC, and data buffer has been designed and submitted for fabrication and will be tested on a prototype of the ATLAS silicon tracker module with realistic electrical and mechanical constraints. (orig.)

Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

International Nuclear Information System (INIS)

Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

2017-01-01

We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

Science.gov (United States)

Kremastiotis, I.

2017-12-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128×128 square pixels with 25μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (~20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ~20 ns for a power consumption of 5μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (~20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using future assemblies with the readout chip.

Test beam results of the first CMS double-sided strip module prototypes using the CBC2 read-out chip

Energy Technology Data Exchange (ETDEWEB)

Harb, Ali, E-mail: ali.harb@desy.de; Mussgiller, Andreas; Hauk, Johannes

2017-02-11

The CMS Binary Chip (CBC) is a prototype version of the front-end read-out ASIC to be used in the silicon strip modules of the CMS outer tracking detector during the high luminosity phase of the LHC. The CBC is produced in 130 nm CMOS technology and bump-bonded to the hybrid of a double layer silicon strip module, the so-called 2S-p{sub T} module. It has 254 input channels and is designed to provide on-board trigger information to the first level trigger system of CMS, with the capability of cluster-width discrimination and high-p{sub T} track identification. In November 2013 the first 2S-p{sub T} module prototypes equipped with the CBC chips were put to test at the DESY-II test beam facility. Data were collected exploiting a beam of positrons with an energy ranging from 2 to 4 GeV. In this paper the test setup and the results are presented.

Readout scheme for the Baby-MIND detector

CERN Document Server

Noah, Etam; Cadoux, F; Favre, Y; Martinez, B; Nicola, L; Parsa, S; Rayner, M; Antonova, M; Fedotov, S; Izmaylov, A; Kleymenova, A; Khabibullin, M; Khotyantsev, A; Kudenko, Y; Likhacheva, V; Mefodiev, A; Mineev, O; Ovsiannikova, T; Shaykhiev, A; Suvorov, S; Yershov, N; Tsenov, R

2016-01-01

A readout scheme has been designed for the plastic scintillator bars of the Baby-MIND detector modules. This spectrometer will measure momentum and identify the charge of 1 GeV/c muons with magnetized iron plates interleaved with detector modules. One challenge the detector aims to address is that of keeping high charge identification efficiencies for momenta below 1 GeV/c where multiple scattering in the iron plates degrades momentum resolution. A front-end board has been developed, with 3 CITIROC readout chips per board and up to 96 channels. Hamamatsu MPPCs type S12571-025C photosensors were chosen for readout of wavelength shifting fibers embedded in plastic scintillators. Procurement of the MPPCs has been carried out to instrument 3000 channels in total. Design choices and first results of this readout scheme are presented.

SPIDR, a general-purpose readout system for pixel ASICs

International Nuclear Information System (INIS)

Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

2017-01-01

The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

International Nuclear Information System (INIS)

Alemi, M.; Campbell, M.; Gys, T.; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K.

2000-01-01

We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface

First operation of a hybrid photon detector prototype with electrostatic cross-focussing and integrated silicon pixel readout

Energy Technology Data Exchange (ETDEWEB)

Alemi, M.; Campbell, M.; Gys, T. E-mail: thierry.gys@cern.ch; Mikulec, B.; Piedigrossi, D.; Puertolas, D.; Rosso, E.; Schomaker, R.; Snoeys, W.; Wyllie, K

2000-07-11

We report on the first operation of a hybrid photon detector prototype with integrated silicon pixel readout for the ring imaging Cherenkov detectors of the LHCb experiment. The photon detector is based on a cross-focussed image intensifier tube geometry where the image is de-magnified by a factor of 4. The anode consists of a silicon pixel array, bump-bonded to a binary readout chip with matching pixel electronics. The prototype has been characterized using a low-intensity light-emitting diode operated in pulsed mode. Its performance in terms of single-photoelectron detection efficiency and imaging properties is presented. A model of photoelectron detection is proposed, and is shown to be in good agreement with the experimental data. It includes an estimate of the charge signal generated in the silicon detector, and the combined effects of the comparator threshold spread of the pixel readout chip, charge sharing at the pixel boundaries and back-scattering of the photoelectrons at the silicon detector surface.

Front-end electronics and readout system for the ILD TPC

CERN Document Server

Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

2015-01-01

A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

International Nuclear Information System (INIS)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P.L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C.A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.

2015-01-01

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

Energy Technology Data Exchange (ETDEWEB)

Yang, P., E-mail: yangping0710@126.com [Central China Normal University, Wuhan (China); Aglieri, G.; Cavicchioli, C. [CERN, 1210 Geneva 23 (Switzerland); Chalmet, P.L. [MIND, Archamps (France); Chanlek, N. [Suranaree University of Technology, Nakhon Ratchasima (Thailand); Collu, A. [University of Cagliari, Cagliari (Italy); INFN (Italy); Gao, C. [Central China Normal University, Wuhan (China); Hillemanns, H.; Junique, A. [CERN, 1210 Geneva 23 (Switzerland); Kofarago, M. [CERN, 1210 Geneva 23 (Switzerland); University of Utrecht, Utrecht (Netherlands); Keil, M.; Kugathasan, T. [CERN, 1210 Geneva 23 (Switzerland); Kim, D. [Dongguk and Yonsei University, Seoul (Korea, Republic of); Kim, J. [Pusan National University, Busan (Korea, Republic of); Lattuca, A. [University of Torino, Torino (Italy); INFN (Italy); Marin Tobon, C.A. [CERN, 1210 Geneva 23 (Switzerland); Marras, D. [University of Cagliari, Cagliari (Italy); INFN (Italy); Mager, M.; Martinengo, P. [CERN, 1210 Geneva 23 (Switzerland); Mazza, G. [University of Torino, Torino (Italy); INFN (Italy); and others

2015-06-11

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

Low-power priority Address-Encoder and Reset-Decoder data-driven readout for Monolithic Active Pixel Sensors for tracker system

Science.gov (United States)

Yang, P.; Aglieri, G.; Cavicchioli, C.; Chalmet, P. L.; Chanlek, N.; Collu, A.; Gao, C.; Hillemanns, H.; Junique, A.; Kofarago, M.; Keil, M.; Kugathasan, T.; Kim, D.; Kim, J.; Lattuca, A.; Marin Tobon, C. A.; Marras, D.; Mager, M.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Puggioni, C.; Rousset, J.; Reidt, F.; Riedler, P.; Snoeys, W.; Siddhanta, S.; Usai, G.; van Hoorne, J. W.; Yi, J.

2015-06-01

Active Pixel Sensors used in High Energy Particle Physics require low power consumption to reduce the detector material budget, low integration time to reduce the possibilities of pile-up and fast readout to improve the detector data capability. To satisfy these requirements, a novel Address-Encoder and Reset-Decoder (AERD) asynchronous circuit for a fast readout of a pixel matrix has been developed. The AERD data-driven readout architecture operates the address encoding and reset decoding based on an arbitration tree, and allows us to readout only the hit pixels. Compared to the traditional readout structure of the rolling shutter scheme in Monolithic Active Pixel Sensors (MAPS), AERD can achieve a low readout time and a low power consumption especially for low hit occupancies. The readout is controlled at the chip periphery with a signal synchronous with the clock, allows a good digital and analogue signal separation in the matrix and a reduction of the power consumption. The AERD circuit has been implemented in the TowerJazz 180 nm CMOS Imaging Sensor (CIS) process with full complementary CMOS logic in the pixel. It works at 10 MHz with a matrix height of 15 mm. The energy consumed to read out one pixel is around 72 pJ. A scheme to boost the readout speed to 40 MHz is also discussed. The sensor chip equipped with AERD has been produced and characterised. Test results including electrical beam measurement are presented.

The AMS silicon tracker readout, performance results with minimum ionizing particles

CERN Document Server

Alpat, B; Battiston, R; Bourquin, Maurice; Burger, W J; Extermann, Pierre; Chang, Y H; Hou, S R; Pauluzzi, M; Produit, N; Qiu, S; Rapin, D; Ribordy, R; Toker, O; Wu, S X

2000-01-01

First results for the AMS silicon tracker readout performance are presented. Small 20.0*20.0*0.300 mm/sup 3/ silicon microstrip detectors were installed in a 50 GeV electron beam at CERN. The detector readout consisted of prototypes of the tracker data reduction card equipped with a 12-bit ADC and the tracker frontend hybrid with VA_hdr readout chips. The system performance is assessed in terms of signal-to-noise, position resolution, and efficiency. (13 refs).

arXiv The MuPix System-on-Chip for the Mu3e Experiment

CERN Document Server

Augustin, Heiko

2017-02-11

Mu3e is a novel experiment searching for charged lepton flavor violation in the rare decay $\\mu^+ \\rightarrow e^+e^-e^+$. Decay vertex position, decay time and particle momenta have to be precisely measured in order to reject both accidental and physics background. A silicon pixel tracker based on $50\\,\\mu$m thin high voltage monolithic active pixel sensors (HV-MAPS) in a 1 T solenoidal magnetic field provides precise vertex and momentum information. The MuPix chip combines pixel sensor cells with integrated analog electronics and a periphery with a complete digital readout. The MuPix7 is the first HV-MAPS prototype implementing all functionalities of the final sensor including a readout state machine and high speed serialization with 1.25 Gbit/s data output, allowing for a streaming readout in parallel to the data taking. The observed efficiency of the MuPix7 chip including the full readout system is $\\geq99\\%$ in a high rate test beam.

TARGET: A multi-channel digitizer chip for very-high-energy gamma-ray telescopes

Energy Technology Data Exchange (ETDEWEB)

Bechtol, K.; Funk, S.; /Stanford U., HEPL /KIPAC, Menlo Park; Okumura, A.; /JAXA, Sagamihara /Stanford U., HEPL /KIPAC, Menlo Park; Ruckman, L.; /Hawaii U.; Simons, A.; Tajima, H.; Vandenbroucke, J.; /Stanford U., HEPL /KIPAC, Menlo Park; Varner, G.; /Hawaii U.

2011-08-11

The next-generation very-high-energy (VHE) gamma-ray observatory, the Cherenkov Telescope Array, will feature dozens of imaging atmospheric Cherenkov telescopes (IACTs), each with thousands of pixels of photosensors. To be affordable and reliable, reading out such a mega-channel array requires event recording technology that is highly integrated and modular, with a low cost per channel. We present the design and performance of a chip targeted to this application: the TeV Array Readout with GSa/s sampling and Event Trigger (TARGET). This application-specific integrated circuit (ASIC) has 16 parallel input channels, a 4096-sample buffer for each channel, adjustable input termination, self-trigger functionality, and tight window-selected readout. We report the performance of TARGET in terms of sampling frequency, power consumption, dynamic range, current-mode gain, analog bandwidth, and cross talk. The large number of channels per chip allows a low cost per channel ($10 to $20 including front-end and back-end electronics but not including photosensors) to be achieved with a TARGET-based IACT readout system. In addition to basic performance parameters of the TARGET chip itself, we present a camera module prototype as well as a second-generation chip (TARGET 2), both of which have been produced.

The ALICE Time of Flight Readout System AFRO

CERN Document Server

Kluge, A

1999-01-01

The ALICE Time of Flight Detector system comprises more than 100.000 channels and covers an area of more than 100 m2. The timing resolution should be better than 150 ps. This combination of requirements poses a major challenge to the readout system. All detector timing measurements are referenced to a unique start signal t0. This signal is generated at the time an event occurs. Timing measurements are performed using a multichannel TDC chip which requires a 40 MHz reference clock signal. The general concept of the readout system is based on a modular architecture. Detector cells are combined to modules of 1024 channels. Each of these modules can be read out and calibrated independently from each other. By distributing a reference signal, a timing relationship between the modules is established. This reference signal can either be the start signal t0 or the TDC-reference clock. The readout architecture is divided into three steps; the TDC controller, the module controller, and the time of flight controller. Th...

Performance of 20:1 multiplexer for large area charge readouts in directional dark matter TPC detectors

Science.gov (United States)

Ezeribe, A. C.; Robinson, M.; Robinson, N.; Scarff, A.; Spooner, N. J. C.; Yuriev, L.

2018-02-01

More target mass is required in current TPC based directional dark matter detectors for improved detector sensitivity. This can be achieved by scaling up the detector volumes, but this results in the need for more analogue signal channels. A possible solution to reducing the overall cost of the charge readout electronics is to multiplex the signal readout channels. Here, we present a multiplexer system in expanded mode based on LMH6574 chips produced by Texas Instruments, originally designed for video processing. The setup has a capability of reducing the number of readouts in such TPC detectors by a factor of 20. Results indicate that the important charge distribution asymmetry along an ionization track is retained after multiplexed signals are demultiplexed.

Medipix3 array high performance read-out board for synchrotron research

International Nuclear Information System (INIS)

Tartoni, N.; Horswell, I. C.; Marchal, J.; Gimenez, E. N.; Fearn, R. D.; Silfhout, R. G. van

2010-01-01

The Medipix3 ASIC is one of the most advanced chip that is presently available to build photon counting area detectors. The capabilities of the chip include adjacent pixels charge summing circuitry to sort out the distortion due to charge sharing, simultaneous counting and read-out that enables frames to be acquired without dead time, the colour mode of operation that enables up to eight energy bands to be acquired. In order to fully exploit the capabilities of the Medipix3 chip in synchrotron research, a high performance electronic board capable of driving large arrays of chips is necessary. We propose a parallel read-out board of Medipix3 chip arrays with a scalable architecture that allows driving the Medipix3 chip in all of its modes of operation. The board functions include the control of the chip arrays, data formatting and data compression, the management of the communications with the data storage devices, and operation in various trigger modes. In addition to this the board will have some 'intelligence' embedded. This will add some very important features to the final detector such as pattern recognition, capability of variable frame duration as a function of the photon flux, feedback to other equipment and real time calculations of data relevant to experiments such as the autocorrelation function.

A micromachined surface stress sensor with electronic readout

NARCIS (Netherlands)

Carlen, Edwin; Weinberg, M.S.; Zapata, A.M.; Borenstein, J.T.

2008-01-01

A micromachined surface stress sensor has been fabricated and integrated off chip with a low-noise, differential capacitance, electronic readout circuit. The differential capacitance signal is modulated with a high frequency carrier signal, and the output signal is synchronously demodulated and

Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

International Nuclear Information System (INIS)

Braga, D; Hall, G; Pesaresi, M; Raymond, M; Jones, L; Murray, P; Prydderch, M

2014-01-01

The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version

Development of pixel readout integrated circuits for extreme rate and radiation

CERN Multimedia

Liberali, V; Rizzi, A; Re, V; Minuti, M; Pangaud, P; Barbero, M B; Pacher, L; Kluit, R; Hinchliffe, I; Manghisoni, M; Giubilato, P; Faccio, F; Pernegger, H; Krueger, H; Gensolen, F D; Bilei, G M; Da rocha rolo, M D; Prydderch, M L; Fanucci, L; Grillo, A A; Bellazzini, R; Palomo pinto, F R; Michelis, S; Huegging, F G; Kishishita, T; Marchiori, G; Christian, D C; Kaestli, H C; Meier, B; Andreazza, A; Key-charriere, M; Linssen, L; Dannheim, D; Conti, E; Hemperek, T; Menouni, M; Fougeron, D; Genat, J; Bomben, M; Marzocca, C; Demaria, N; Mazza, G; Van bakel, N A; Palla, F; Grippo, M T; Magazzu, G; Ratti, L; Abbaneo, D; Crescioli, F; Deptuch, G W; Neue, G; De robertis, G; Passeri, D; Placidi, P; Gromov, V; Morsani, F; Paccagnella, A; Christiansen, J; Dho, E; Wermes, N; Rymaszewski, P; Rozanov, A; Wang, A; Lipton, R J; Havranek, M; Neviani, A; Marconi, S; Karagounis, M; Godiot, S; Calderini, G; Seidel, S C; Horisberger, R P; Garcia-sciveres, M A; Stabile, A; Beccherle, R; Bacchetta, N

The present hybrid pixel detectors in operation at the LHC represent a major achievement. They deployed a new technology on an unprecedented scale and their success firmly established pixel tracking as indispensable for future HEP experiments. However, extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. We propose a new RD collaboration specifically focused on the development of pixel readout Integrated Circuits (IC). The IC challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm$^{2}$), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. We propose a collaboration to design the next generation of hybrid pixel readout chips to enable the ATLAS and CMS Phase 2 pixel upgrades. This does not imply that ATLAS and CMS must use the same exact pixel readout chip, as most of the dev...

The universal read-out controller for CBM at FAIR

Energy Technology Data Exchange (ETDEWEB)

Manz, Sebastian; Abel, Norbert; Gebelein, Jano [Kirchhoff-Institut fuer Physik, Heidelberg (Germany); Collaboration: CBM-Collaboration

2011-07-01

Since 2007 we design and develop the firmware for the read-out controller (ROC) for data acquisition of the CBM detector at FAIR. While our first implementation solely focused on the nXYTER chip, today we are also designing and implementing readout logic for the GET4 chip which is supposed to be part of the time of flight (TOF) detector. Furthermore, we fully support both Ethernet and Optical transport as two transparent solutions. This addresses the different requirements of a laboratory setup and the final detector setup respectively. The usage of a strict modularization of the Read Out Controller firmware enables us to provide an Universal ROC where front-end specific logic and transport logic can be combined in a very flexible way. Fault tolerance techniques are only required for some of those modules and hence are only implemented there.

A TDC integrated circuit for drift chamber readout

International Nuclear Information System (INIS)

Passaseo, M.; Petrolo, E.; Veneziano, S.

1995-01-01

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

A TDC integrated circuit for drift chamber readout

Energy Technology Data Exchange (ETDEWEB)

Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

1995-12-11

A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

RD Collaboration Proposal: Development of pixel readout integrated circuits for extreme rate and radiation

CERN Document Server

Chistiansen, J (CERN)

2013-01-01

This proposal describes a new RD collaboration to develop the next genrration of hybrid pixel readout chips for use in ATLAS and CMS PHase 2 upgrades. extrapolation of hybrid pixel technology to the HL-LHC presents major challenges on several fronts. Challenges include: smaller pixels to resolve tracks in boosted jets, much higher hit rates (1-2 GHz/cm2 ), unprecedented radiation tolerance (10 MGy), much higher output bandwidth, and large IC format with low power consumption in order to instrument large areas while keeping the material budget low. This collaboration is specifically focused on design of hybrid pixel readout chips, and not on more general chip design or on other aspects of hybrid pixel technology. Participants include 7 institutes on ATLAS and 7 on CMS, plus 2 on both experiments.

Simulations of busy probabilities in the ALPIDE chip and the upgraded ALICE ITS detector

CERN Document Server

Nesbo, Simon Voigt; Bonora, Matthias; Giubilato, Piero; Helstrup, Haavard; Hristozkov, Svetlomir; Aglieri Rinella, Gianluca; Röhrich, Dieter; Schambach, Joachim; Shahoyan, Ruben; Ullaland, Kjetil

2017-01-01

For the Long Shutdown 2 (LS2) upgrade of the ITS detector in the ALICE experiment at the LHC, a novel pixel detector chip, the ALPIDE chip, has been developed. In the event of busy ALPIDE chips in the ITS detector, the readout electronics may need to take appropriate action to minimize loss of data. This paper presents a lightweight, statistical simulation model for the ALPIDE chip and the up- graded ITS detector, developed using the SystemC framework. The purpose of the model is to quantify the probability of a busy condition and the data taking efficiency of the ALPIDE chips under various conditions, and to apply this knowledge during the development of the readout electronics and firmware.

Development of pixel readout integrated circuits for extreme rate and radiation

CERN Document Server

Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

2013-01-01

Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

Characterisation of capacitively coupled HV/HR-CMOS sensor chips for the CLIC vertex detector

CERN Document Server

AUTHOR|(SzGeCERN)756402

2017-01-01

The capacitive coupling between an active sensor and a readout ASIC has been considered in the framework of the CLIC vertex detector study. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is a High-Voltage CMOS sensor chip produced in a commercial 180 nm HV-CMOS process for this purpose. The sensor was designed to be connected to the CLICpix2 readout chip. It therefore matches the dimensions of the readout chip, featuring a matrix of 128 × 128 square pixels with 25 μm pitch. The sensor chip has been produced with the standard value for the substrate resistivity (∼ 20 Ωcm) and it has been characterised in standalone testing mode, before receiving and testing capacitively coupled assemblies. The standalone measurement results show a rise time of ∼ 20 ns for a power consumption of 5 μW/pixel. Production of the C3PD HV-CMOS sensor chip with higher substrate resistivity wafers (∼ 20, 80, 200 and 1000 Ωcm) is foreseen. The expected benefits of the higher substrate resistivity will be studied using...

Study and optimization of the spatial resolution for detectors with binary readout

Energy Technology Data Exchange (ETDEWEB)

Yonamine, R., E-mail: ryo.yonamine@ulb.ac.be; Maerschalk, T.; Lentdecker, G. De

2016-09-11

Using simulations and analytical approaches, we have studied single hit resolutions obtained with a binary readout, which is often proposed for high granularity detectors to reduce the generated data volume. Our simulations considering several parameters (e.g. strip pitch) show that the detector geometry and an electronics parameter of the binary readout chips could be optimized for binary readout to offer an equivalent spatial resolution to the one with an analog readout. To understand the behavior as a function of simulation parameters, we developed analytical models that reproduce simulation results with a few parameters. The models can be used to optimize detector designs and operation conditions with regard to the spatial resolution.

The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

Directory of Open Access Journals (Sweden)

Trong-Hieu Tran

2016-09-01

Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

Prototype readout system for a multi Mpixels UV single-photon imaging detector capable of space flight operation

Science.gov (United States)

Seljak, A.; Cumming, H. S.; Varner, G.; Vallerga, J.; Raffanti, R.; Virta, V.

2018-02-01

Our collaboration works on the development of a large aperture, high resolution, UV single-photon imaging detector, funded through NASA's Strategic Astrophysics Technology (SAT) program. The detector uses a microchannel plate for charge multiplication, and orthogonal cross strip (XS) anodes for charge readout. Our target is to make an advancement in the technology readiness level (TRL), which enables real scale prototypes to be tested for future NASA missions. The baseline detector has an aperture of 50×50 mm and requires 160 low-noise charge-sensitive channels, in order to extrapolate the incoming photon position with a spatial resolution of about 20 μm FWHM. Technologies involving space flight require highly integrated electronic systems operating at very low power. We have designed two ASICs which enable the construction of such readout system. First, a charge sensitive amplifier (CSAv3) ASIC provides an equivalent noise charge (ENC) of around 600 e-, and a baseline gain of 10 mV/fC. The second, a Giga Sample per Second (GSPS) ASIC, called HalfGRAPH, is a 12-bit analog to digital converter. Its architecture is based on waveform sampling capacitor arrays and has about 8 μs of analog storage memory per channel. Both chips encapsulate 16 measurement channels. Using these chips, a small scale prototype readout system has been constructed on a FPGA Mezzanine Board (FMC), equipped with 32 measurement channels for system evaluation. We describe the construction of HalfGRAPH ASIC, detector's readout system concept and obtained results from the prototype system. As part of the space flight qualification, these chips were irradiated with a Cobalt gamma-ray source, to verify functional operation under ionizing radiation exposure.

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

MEMS acceleration sensor with remote optical readout for continuous power generator monitoring

Directory of Open Access Journals (Sweden)

Tormen Maurizio

2015-01-01

Full Text Available Miniaturized accelerometers with remote optical readout are required devices for the continuous monitoring of vibrations inside power generators. In turbo and hydro generators, end-winding vibrations are present during operation causing in the long term undesirable out-of-service repairs. Continuous monitoring of these vibrations is therefore mandatory. The high electromagnetic fields in the generators impose the use of devices immune to electromagnetic interferences. In this paper a MEMS based accelerometer with remote optical readout is presented. Advantages of the proposed device are the use of a differential optical signal to reject the common mode signal and noise, the reduced number of steps for the MEMS chip fabrication and for the system assembly, and the reduced package volume.

Design and implementation of a nanosecond time-stamping readout system-on-chip for photo-detectors

International Nuclear Information System (INIS)

Anvar, Shebli; Château, Frédéric; Le Provost, Hervé; Louis, Frédéric; Manolopoulos, Konstantinos; Moudden, Yassir; Vallage, Bertrand; Zonca, Eric

2014-01-01

A readout system suitable for a large number of synchronized photo-detection units has been designed. Each unit embeds a specifically designed fully integrated communicating system based on Xilinx FPGA SoC technology. It runs the VxWorks real-time OS and a custom data acquisition software designed within the Ice middleware framework, resulting in a highly flexible, controllable and scalable distributed application. Clock distribution and delay calibration over customized fixed latency gigabit Ethernet links enable synchronous time-stamping of events with nanosecond precision. The implementation of this readout system on several data-collecting units as well as its performances are described

Central FPGA-based Destination and Load Control in the LHCb MHz Event Readout

CERN Document Server

Jacobsson, Richard

2012-01-01

The readout strategy of the LHCb experiment [1] is based on complete event readout at 1 MHz [2]. Over 300 sub-detector readout boards transmit event fragments at 1 MHz over a commercial 70 Gigabyte/s switching network to a distributed event building and trigger processing farm with 1470 individual multi-core computer nodes [3]. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a powerful non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. A high-speed FPGA-based central master module controls the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load balancing and trigger rate regulation as a function of the global farm load. It also ...

Development of radiation hard readout electronics for LHCb

CERN Document Server

Sexauer, Edgar; Lindenstruth, Volker

2001-01-01

The experiment LHCb is under development at CERN and aims to measure CP-violation in the B-Meson system at very high precision. The experiment makes use of a vertex detector that is equipped with silicon microstrip detectors. A chip suitable for the readout of this detector has been developed in a working group at the ASIC-laboratory Heidelberg. This readout chip 'Beetle-1.0' contains 128 analog input stages of a charge sensitive preamplifier, a pulse shaper and a buffer. The analog signal is fed into a comparator, from which a fast trigger signal can be derived. The following pipeline, realized as an array of gate capacitances, can be used to either store the analog output of the input amplifiers or to store the digital comparator output. External trigger signals mark events that have to be read out and the according pipeline location is stored in a derandomizing buffer. Pending events are read out from the pipeline via a charge-sensitive, resetable amplifier and an analog multiplexer, which serializes the s...

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

Energy Technology Data Exchange (ETDEWEB)

Rovati, L; Bonaiuti, M [Dipartimento di Ingegneria dell' Informazione, Universita di Modena e Reggio Emilia, Modena (Italy); Bettarini, S [Dipartimento di Fisica, Universita di Pisa and INFN Pisa, Pisa (Italy); Bosisio, L [Dipartimento di Fisica, Universita di Trieste and INFN Trieste, Trieste (Italy); Dalla Betta, G-F; Tyzhnevyi, V [Dipartimento di Ingegneria e Scienza dell' Informazione, Universita di Trento e INFN Trento, Trento (Italy); Verzellesi, G [Dipartimento di Scienze e Metodi dell' Ingegneria, Universita di Modena e Reggio Emilia and INFN Trento, Reggio Emilia (Italy); Zorzi, N, E-mail: giovanni.verzellesi@unimore.i [Fondazione Bruno Kessler (FBK), Trento (Italy)

2009-11-15

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

Alpha-particle detection based on the BJT detector and simple, IC-based readout electronics

International Nuclear Information System (INIS)

Rovati, L; Bonaiuti, M; Bettarini, S; Bosisio, L; Dalla Betta, G-F; Tyzhnevyi, V; Verzellesi, G; Zorzi, N

2009-01-01

In this paper we propose a portable instrument for alpha-particle detection based on a previously-developed BJT detector and a simple, IC-based readout electronics. Experimental tests of the BJT detector and readout electronics are reported. Numerical simulations are adopted to predict the performance enhancement achievable with optimized BJT detectors.

Investigation of the readout electronics of DELPHI surround muon chamber

International Nuclear Information System (INIS)

Khovanskij, N.; Krumshtejn, Z.; Ol'shevskij, A.; Sadovskij, A.; Sedykh, Yu.; Molnar, J.; Sicho, P.; Tomsa, Z.

1995-01-01

The characteristics of the readout electronics of the DELPHI surround muon chambers with various AMPLEX chips (AMPLEX 16 and AMPLEX-SICAL) are presented. This electronics is studied in a cosmic rays test of the real surround muon chamber model. 4 refs., 6 figs., 1 tab

A custom readout electronics for the BESIII CGEM detector

International Nuclear Information System (INIS)

Rolo, M. Da Rocha; Alexeev, M.; Amoroso, A.; Bianchi, F.; Cossio, F.; Mori, F. De; Destefanis, M.; Ferroli, R. Baldini; Chai, J.Y.; Bertani, M.; Calcaterra, A.; Capodiferro, M.; Cerioni, S.; Bettoni, D.; Canale, N.; Carassiti, V.; Chiozzi, S.; Cibinetto, G.; Ramusino, A. Cotta; Bugalho, R.

2017-01-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM

A custom readout electronics for the BESIII CGEM detector

Science.gov (United States)

Da Rocha Rolo, M.; Alexeev, M.; Amoroso, A.; Baldini Ferroli, R.; Bertani, M.; Bettoni, D.; Bianchi, F.; Bugalho, R.; Calcaterra, A.; Canale, N.; Capodiferro, M.; Carassiti, V.; Cerioni, S.; Chai, J. Y.; Chiozzi, S.; Cibinetto, G.; Cossio, F.; Cotta Ramusino, A.; De Mori, F.; Destefanis, M.; Di Francesco, A.; Dong, J.; Evangelisti, F.; Farinelli, R.; Fava, L.; Felici, G.; Fioravanti, E.; Garzia, I.; Gatta, M.; Greco, M.; Lavezzi, L.; Leng, C. Y.; Li, H.; Maggiora, M.; Malaguti, R.; Marcello, S.; Marciniewski, P.; Melchiorri, M.; Mezzadri, G.; Mignone, M.; Morello, G.; Pacetti, S.; Patteri, P.; Pellegrino, J.; Pelosi, A.; Rivetti, A.; Savrié, M.; Scodeggio, M.; Soldani, E.; Sosio, S.; Spataro, S.; Tskhadadze, E.; Varela, J.; Verma, S.; Wheadon, R.; Yan, L.

2017-07-01

For the upgrade of the inner tracker of the BESIII spectrometer, planned for 2018, a lightweight tracker based on an innovative Cylindrical Gas Electron Multiplier (CGEM) detector is now under development. The analogue readout of the CGEM enables the use of a charge centroid algorithm to improve the spatial resolution to better than 130 μm while loosening the pitch strip to 650 μm, which allows to reduce the total number of channels to about 10 000. The channels are readout by 160 dedicated integrated 64-channel front-end ASICs, providing a time and charge measurement and featuring a fully-digital output. The energy measurement is extracted either from the time-over-threshold (ToT) or the 10-bit digitisation of the peak amplitude of the signal. The time of the event is generated by quad-buffered low-power TDCs, allowing for rates in excess of 60 kHz per channel. The TDCs are based on analogue interpolation techniques and produce a time stamp (or two, if working in ToT mode) of the event with a time resolution better than 50 ps. The front-end noise, based on a CSA and a two-stage complex conjugated pole shapers, dominate the channel intrinsic time jitter, which is less than 5 ns r.m.s. The time information of the hit can be used to reconstruct the track path, operating the detector as a small TPC and hence improving the position resolution when the distribution of the cloud, due to large incident angle or magnetic field, is very broad. Event data is collected by an off-detector motherboard, where each GEM-ROC readout card handles 4 ASIC carrier FEBs (512 channels). Configuration upload and data readout between the off-detector electronics and the VME-based data collector cards are managed by bi-directional fibre optical links. This paper covers the design of a custom front-end electronics for the readout of the new inner tracker of the BESIII experiment, addressing the relevant design aspects of the detector electronics and the front-end ASIC for the CGEM readout

Development of an external readout electronics for a hybrid photon detector

CERN Document Server

Uyttenhove, Simon; Tichon, Jacques; Garcia, Salvador

The pixel hybrid photon detectors currently installed in the LHCb Cherenkov system encapsulate readout electronics in the vacuum tube envelope. The LHCb upgrade and the new trigger system will require their replacement with new photon detectors. The baseline photon detector candidate is the multi-anode photomultiplier. A hybrid photon detector with external readout electronics has been proposed as a backup option. This master thesis covers a R & D phase to investigate this latter concept. Extensive studies of the initial electronics system underlined the noise contributions from the Beetle chip used as front-end readout ASIC and from the ceramic carrier of the photon detector. New front-end electronic boards have been developed and made fully compatible with the existing LHCb-RICH infrastructure. With this compact readout system, Cherenkov photons have been successfully detected in a real particle beam environment. The proof-of-concept of a hybrid photon detector with external readout electronics was val...

The NA62 Gigatracker: Detector properties and pixel read-out architectures

International Nuclear Information System (INIS)

Fiorini, M.; Carassiti, V.; Ceccucci, A.; Cortina, E.; Cotta Ramusino, A.; Dellacasa, G.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Martoiu, S.; Mazza, G.; Noy, M.; Petrucci, F.; Riedler, P.; Rivetti, A.; Tiuraniemi, S.

2010-01-01

The beam spectrometer of the NA62 experiment, named Gigatracker, has to perform single track reconstruction with unprecedented time resolution (150 ps rms) in a harsh radiation environment. To meet these requirements, and in order to reduce material budget to a minimum, three hybrid silicon pixel detector stations will be installed in vacuum. An adequate strategy to compensate for the discriminator time-walk must be implemented and R and D investigating two different options is ongoing. Two read-out chip prototypes have been designed in order to compare their performance: one approach is based on the use of a constant-fraction discriminator followed by an on-pixel TDC, while the other one is based on the use of a time-over-threshold circuit followed by a TDC shared by a group of pixels. This paper describes the Gigatracker system, presents the global architectures of both read-out ASICs and reviews the current status of the R and D project.

Temporal Noise Analysis of Charge-Domain Sampling Readout Circuits for CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Xiaoliang Ge

2018-02-01

Full Text Available This paper presents a temporal noise analysis of charge-domain sampling readout circuits for Complementary Metal-Oxide Semiconductor (CMOS image sensors. In order to address the trade-off between the low input-referred noise and high dynamic range, a Gm-cell-based pixel together with a charge-domain correlated-double sampling (CDS technique has been proposed to provide a way to efficiently embed a tunable conversion gain along the read-out path. Such readout topology, however, operates in a non-stationery large-signal behavior, and the statistical properties of its temporal noise are a function of time. Conventional noise analysis methods for CMOS image sensors are based on steady-state signal models, and therefore cannot be readily applied for Gm-cell-based pixels. In this paper, we develop analysis models for both thermal noise and flicker noise in Gm-cell-based pixels by employing the time-domain linear analysis approach and the non-stationary noise analysis theory, which help to quantitatively evaluate the temporal noise characteristic of Gm-cell-based pixels. Both models were numerically computed in MATLAB using design parameters of a prototype chip, and compared with both simulation and experimental results. The good agreement between the theoretical and measurement results verifies the effectiveness of the proposed noise analysis models.

FPGA-based upgrade of the read-out electronics for the low energy polarimeter at the cooler synchrotron

Energy Technology Data Exchange (ETDEWEB)

Hempelmann, Nils [Institut fuer Kernphysik, Forschungszentrum Juelich (Germany); Collaboration: JEDI-Collaboration

2015-07-01

The Cooler Synchrotron (COSY) is a storage ring used for experiments with polarized proton and deuteron beams. The low energy polarimeter is used to determine the vector and tensor polarization of the beam before injection at kinetic energies up to 45 MeV for protons and 75 MeV for deuterons. The polarimeter uses scintillators to measure the energy of both outgoing particles of a scattering reaction and the time between their detection. The present read-out electronics consists of analog NIM modules and is limited in terms of time resolution and the capability for online data analysis. The read-out electronics will be replaced with a a new system based on analog pulse sampling and an FPGA chip for logic operations. The new system will be able to measure the time at which particles arrive to a precision better than 50 ps, facilitating better background reduction using coincidence measurement. In addition to measuring the beam polarization, the system will be used to precisely determine the vector and tensor analyzing powers for deuteron scattering off carbon at a kinetic energy of 75 MeV.

Development of X-ray CCD camera system with high readout rate using ASIC

International Nuclear Information System (INIS)

Nakajima, Hiroshi; Matsuura, Daisuke; Anabuki, Naohisa; Miyata, Emi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi

2009-01-01

We report on the development of an X-ray charge-coupled device (CCD) camera system with high readout rate using application-specific integrated circuit (ASIC) and Camera Link standard. The distinctive ΔΣ type analog-to-digital converter is introduced into the chip to achieve effective noise shaping and to obtain a high resolution with relatively simple circuits. The unit test proved moderately low equivalent input noise of 70μV with a high readout pixel rate of 625 kHz, while the entire chip consumes only 100 mW. The Camera Link standard was applied for the connectivity between the camera system and frame grabbers. In the initial test of the whole system, we adopted a P-channel CCD with a thick depletion layer developed for X-ray CCD camera onboard the next Japanese X-ray astronomical satellite. The characteristic X-rays from 109 Cd were successfully read out resulting in the energy resolution of 379(±7)eV (FWHM) at 22.1 keV, that is, ΔE/E=1.7% with a readout rate of 44 kHz.

A fast integrated readout system for a cathode pad photon detector

Energy Technology Data Exchange (ETDEWEB)

French, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Lovell, M. (Rutherford Appleton Lab., Chilton (United Kingdom)); Chesi, E. (CERN, ECP Div., Geneva (Switzerland)); Racz, A. (CERN, ECP Div., Geneva (Switzerland)); Seguinot, J. (Coll. de France, Paris (France)); Ypsilantis, T. (Coll. de France, Paris (France)); Arnold, R. (CRN, Louis Pasteur Univ., Strasbourg (France)); Guyonnet, J.L. (CRN, Louis Pasteur Univ., Strasbourg (France)); Egger, J. (Paul Scherrer Inst., Villigen (Switzerland)); Gabathuler, K. (Paul Scherrer Inst., Villigen (Switzerland))

1994-04-01

A fast integrated electronic chain is presented to read out the cathode pad array of a multiwire photon detector for a fast RICH counter. Two VLSI circuits have been designed and produced. An analog eight channel, low noise, fast, bipolar, current preamplifier and discriminator chip serves as front-end electronics. It has an rms equivalent noise current of 10 nA (2000 e[sup -]), 50 MHz bandwidth with 10 mW of power consumption per channel. Two analogue chips are coupled to a digital 16 channels CMOS readout chip, operating at 20 MHz, that provides a pipelined delay of 1.3 [mu]s and zero suppression with a power consumption of about 6 mW per channel. Readout of a 4000 pad sector requires 3-4 [mu]s depending on the number of hit pads. The full RICH counter is made up of many of such sectors (the prototype has three fully equipped sectors), read out in parallel. The minimum time to separate successive hits on the same pad is about 70 ns. The time skew of the full chain is about 15 ns. (orig.)

Feasibility study to use an SRAM-based FPGA in the readout electronics of the upgraded LHCb outer tracker detector

International Nuclear Information System (INIS)

Faerber, Christian

2014-01-01

This thesis presents a study of the feasibility to use SRAM-based FPGAs as central component of the upgraded LHCb Outer Tracker readout electronics. The FPGA should contain the functionality of a TDC and should provide fast data links using multi-GBit/s transceivers. The TDC core that was developed provides 5 bit time measurements for 32 channels with a bin size of 780 ps. The TDC has the required time resolution of better than 1 ns. This was achieved by manually placing every logic element of the TDC channels and with an iterative procedure feeding timing measurements back to the Place and Route step of the router software. A transceiver and TDC card, and an adapter board for the existing readout electronics was developed. Both boards were used successfully to read out drift times from an Outer Tracker straw-tube module in a cosmic setup. To qualify the proposed electronics for the expected radiation levels an irradiation test with 22 MeV protons and two FPGA boards was performed up to a total ionization dose of 30 Mrad. Both chips sustained the irradiation expected for the full life time of the upgraded LHCb detector of up to 30 krad. After an irradiation dose of 150 krad the first deteriorations of the performance of the chips were observed. The proton cross section for configuration bit flips was determined to be 1.6.10 16 cm 2 per bit. The measured error rate scaled to the upgrade environment would correspond to a manageable firmware error rate.

Qualification method for a 1 MGy-tolerant front-end chip designed in 65 nm CMOS for the read-out of remotely operated sensors and actuators during maintenance in ITER

Energy Technology Data Exchange (ETDEWEB)

Verbeeck, Jens, E-mail: jens.verbeeck@esat.kuleuven.be [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Cao, Ying [KU Leuven (KUL), Div. LRD-MAGyICS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Van Uffelen, Marco; Casellas, Laura Mont; Damiani, Carlo; Morales, Emilio Ruiz; Santana, Roberto Ranz [Fusion for Energy (F4E), c/Josep, no. 2, Torres Diagonal Litoral, Ed. B3, 08019 Barcelona (Spain); Meek, Richard; Haist, Bernhard [Oxford Technologies Ltd. (OTL), 7 Nuffield Way, Abingdon OX14 1RL (United Kingdom); Hamilton, David [ITER Organisation (IO), Route de Vinon-sur-Verdon, CS 90 046, 13067 St. Paul les Durance Cedex (France); Steyaert, Michiel [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); Leroux, Paul [KU Leuven, ESAT-MICAS, Kasteelpark Arenberg 10, 3001 Heverlee (Belgium); KU Leuven, ESAT, Advanced Integrated Sensing Lab (AdvISe), Kleinhoefstraat 4, 2440 Geel (Belgium)

2015-10-15

This paper describes the radiation qualification procedure for a 1 MGy-tolerant Application Specific Integrated Circuit (ASIC) developed in 65 nm CMOS technology. The chip is intended for the read-out of electrical signals of sensors and actuators during maintenance in ITER. First the general working principle of the ASIC is shown. The developed IC allows to read-out, condition and digitize multiple low bandwidth (<10 kHz) sensors. In addition the IC is able to multiplex the digitized sensor signals. To comply with ITER-relevant constraints an adapted radiation qualification procedure has been proposed. The radiation-qualification procedure describes the test criteria and test conditions of the developed ASICs, which are also compared with COTS alternatives, to meet the stringent qualification procedures for electronics exposed to radiation in ITER.

Electronics and readout of a large area silicon detector for LHC

International Nuclear Information System (INIS)

Borer, K.; Munday, D.J.; Parker, M.A.; Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Jarron, P.; Heijne, E.H.M.; Santiard, J.C.; Scampoli, P.; Verweij, H.; Goessling, C.; Lisowski, B.; Reichold, A.; Spiwoks, R.; Tsesmelis, E.; Benslama, K.; Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; Wu, X.; Fretwurst, E.; Lindstroem, G.; Schultz, T.; Bardos, R.A.; Gorfine, G.W.; Moorhead, G.F.; Taylor, G.N.; Tovey, S.N.; Bibby, J.H.; Hawkings, R.J.; Kundu, N.; Weidberg, A.; Campbell, D.; Murray, P.; Seller, P.; Teiger, J.

1994-01-01

The purpose of the RD2 project is to evaluate the feasibility of a silicon tracker and/or preshower detector for LHC. Irradiation studies with doses equivalent to those expected at LHC have been performed to determine the behavior of operational parameters such as leakage current, depletion voltage and charge collection during the life of the detector. The development of fast, dense, low power and low cost signal processing electronics is one of the major activities of the collaboration. We describe the first fully functional integrated analog memory chip with asynchronous read and write operations and level 1 trigger capture capabilities. A complete test beam system using this analog memory chip at 66 MHz has been successfully operated with RD2 prototype silicon detectors during various test runs. The flexibility of the electronics and readout have allowed us to easily interface our set-up to other data acquisition systems. Mechanical studies are in progress to design a silicon tracking detector with several million channels that may be operated at low (0-10 C) temperature, while maintaining the required geometrical precision. Prototype readout boards for such a detector are being developed and simulation studies are being performed to optimize the readout architecture. (orig.)

An FPGA-based sampling-ADC readout for the crystal barrel calorimeter

Energy Technology Data Exchange (ETDEWEB)

Muellers, Johannes [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Marciniewski, Pawel [Angstroemlaboratoriet, Uppsala (Sweden); Collaboration: CBELSA/TAPS-Collaboration

2015-07-01

The CBELSA/TAPS experiment at the electron accelerator ELSA (Bonn) investigates the photoproduction of mesons off protons and neutrons. Presently the readout of the CsI(Tl)-crystals of the Crystal Barrel calorimeter is being upgraded from a PIN-diode readout to an APD readout to create a fast signal for first-level-triggering. This will increase the trigger efficiency especially for final states with only neutral particles substantially. To increase the possible data readout rate, which is currently limited by the digitization stage (LeCroy QDC 1885F) to ∼ 2 kHz, the implementation of a new Sampling-ADC (SADC) readout is being prepared. Based on the 64-channel PANDA-SADC, the CB-SADC design was modified and adapted to the needs of the CBELSA/TAPS experiment. It offers 64 channels in one NIM module, together with modular analog or FPGA-based digital shaping. The data transfer will be realized by two standard gigabit links. Using an FPGA together with SADCs provides a multitude of possibilities for online feature extraction, such as the determination of the energy deposited in the crystal, TDC capabilities and pile-up detection and recovery.

Design of a CMOS integrated on-chip oscilloscope for spin wave characterization

Directory of Open Access Journals (Sweden)

Eugen Egel

2017-05-01

Full Text Available Spin waves can perform some optically-inspired computing algorithms, e.g. the Fourier transform, directly than it is done with the CMOS logic. This article describes a new approach for on-chip characterization of spin wave based devices. The readout circuitry for the spin waves is simulated with 65-nm CMOS technology models. Commonly used circuits for Radio Frequency (RF receivers are implemented to detect a sinusoidal ultra-wideband (5-50 GHz signal with an amplitude of at least 15 μV picked up by a loop antenna. First, the RF signal is amplified by a Low Noise Amplifier (LNA. Then, it is down-converted by a mixer to Intermediate Frequency (IF. Finally, an Operational Amplifier (OpAmp brings the IF signal to higher voltages (50-300 mV. The estimated power consumption and the required area of the readout circuit is approximately 55.5 mW and 0.168 mm2, respectively. The proposed On-Chip Oscilloscope (OCO is highly suitable for on-chip spin wave characterization regarding the frequency, amplitude change and phase information. It offers an integrated low power alternative to current spin wave detecting systems.

Performance of the gamma-ray camera based on GSO(Ce) scintillator array and PSPMT with the ASIC readout system

International Nuclear Information System (INIS)

Ueno, Kazuki; Hattori, Kaori; Ida, Chihiro; Iwaki, Satoru; Kabuki, Shigeto; Kubo, Hidetoshi; Kurosawa, Shunsuke; Miuchi, Kentaro; Nagayoshi, Tsutomu; Nishimura, Hironobu; Orito, Reiko; Takada, Atsushi; Tanimori, Toru

2008-01-01

We have studied the performance of a readout system with ASIC chips for a gamma-ray camera based on a 64-channel multi-anode PSPMT (Hamamatsu flat-panel H8500) coupled to a GSO(Ce) scintillator array. The GSO array consists of 8x8 pixels of 6x6x13 mm 3 with the same pixel pitch as the anode of the H8500. This camera is intended to serve as an absorber of an electron tracking Compton gamma-ray camera that measures gamma rays up to ∼1 MeV. Because we need a readout system with low power consumption for a balloon-borne experiment, we adopted a 32-channel ASIC chip, IDEAS VA32 H DR11, which has one of the widest dynamic range among commercial chips. However, in the case of using a GSO(Ce) crystal and the H8500, the dynamic range of VA32 H DR11 is narrow, and therefore the H8500 has to be operated with a low gain of about 10 5 . If the H8500 is operated with a low gain, the camera has a narrow incident-energy dynamic range from 100 to 700 keV, and a bad energy resolution of 13.0% (FWHM) at 662 keV. We have therefore developed an attenuator board in order to operate the H8500 with the typical gain of 10 6 , which can measure up to ∼1 MeV gamma ray. The board makes the variation of the anode gain uniform and widens the dynamic range of the H8500. The system using the new attenuator board has a good uniformity of min:max∼1:1.6, an incident-energy dynamic range from 30 to 900 keV, a position resolution of less than 6 mm, and a typical energy resolution of 10.6% (FWHM) at 662 keV with a low power consumption of about 1.7 W/64ch

A time projection chamber with GEM-based readout

Energy Technology Data Exchange (ETDEWEB)

Attié, David [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); Behnke, Ties [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); Bellerive, Alain [Carleton University, Department of Physics, 1125 Colonel By Drive, Ottawa, ON, Canada K1S 5B6 (Canada); Bezshyyko, Oleg [Taras Shevchenko National University of Kyiv, 64/13, Volodymyrska Street, City of Kyiv 01601 (Ukraine); Bhattacharya, Deb Sankar [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); now at Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); Bhattacharya, Purba [Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); now at National Institute of Science Education and Research (NISER) Bhubaneswar, P.O. Jatni, Khurda 752050, Odisha (India); Bhattacharya, Sudeb [Saha Institute of Nuclear Physics, 1/AF, Sector 1, Bidhan Nagar, Kolkata 700064 (India); Caiazza, Stefano [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); now at Johannes Gutenberg Universität Mainz, Institut für Physik, 55099 Mainz (Germany); Colas, Paul [CEA Saclay, IRFU, F-91191 Gif-sur-Yvette (France); Lentdecker, Gilles De [Inter University ULB-VUB, Av. Fr. Roosevelt 50, B1050 Bruxelles (Belgium); Dehmelt, Klaus [Deutsches Elektronen-Synchrotron DESY, A Research Centre of the Helmholtz Association, Notkestrasse 85, 22607 Hamburg (Hamburg site) (Germany); now at State University of New York at Stony Brook, Department of Physics and Astronomy, Stony Brook, NY 11794-3800 (United States); Desch, Klaus [Universität Bonn, Physikalisches Institut, Nußallee 12, 53115 Bonn (Germany); and others

2017-06-01

For the International Large Detector concept at the planned International Linear Collider, the use of time projection chambers (TPC) with micro-pattern gas detector readout as the main tracking detector is investigated. In this paper, results from a prototype TPC, placed in a 1 T solenoidal field and read out with three independent Gas Electron Multiplier (GEM) based readout modules, are reported. The TPC was exposed to a 6 GeV electron beam at the DESY II synchrotron. The efficiency for reconstructing hits, the measurement of the drift velocity, the space point resolution and the control of field inhomogeneities are presented.

Transparent Nanopore Cavity Arrays Enable Highly Parallelized Optical Studies of Single Membrane Proteins on Chip.

Science.gov (United States)

Diederichs, Tim; Nguyen, Quoc Hung; Urban, Michael; Tampé, Robert; Tornow, Marc

2018-06-13

Membrane proteins involved in transport processes are key targets for pharmaceutical research and industry. Despite continuous improvements and new developments in the field of electrical readouts for the analysis of transport kinetics, a well-suited methodology for high-throughput characterization of single transporters with nonionic substrates and slow turnover rates is still lacking. Here, we report on a novel architecture of silicon chips with embedded nanopore microcavities, based on a silicon-on-insulator technology for high-throughput optical readouts. Arrays containing more than 14 000 inverted-pyramidal cavities of 50 femtoliter volumes and 80 nm circular pore openings were constructed via high-resolution electron-beam lithography in combination with reactive ion etching and anisotropic wet etching. These cavities feature both, an optically transparent bottom and top cap. Atomic force microscopy analysis reveals an overall extremely smooth chip surface, particularly in the vicinity of the nanopores, which exhibits well-defined edges. Our unprecedented transparent chip design provides parallel and independent fluorescent readout of both cavities and buffer reservoir for unbiased single-transporter recordings. Spreading of large unilamellar vesicles with efficiencies up to 96% created nanopore-supported lipid bilayers, which are stable for more than 1 day. A high lipid mobility in the supported membrane was determined by fluorescent recovery after photobleaching. Flux kinetics of α-hemolysin were characterized at single-pore resolution with a rate constant of 0.96 ± 0.06 × 10 -3 s -1 . Here, we deliver an ideal chip platform for pharmaceutical research, which features high parallelism and throughput, synergistically combined with single-transporter resolution.

Development of high performance readout ASICs for silicon photomultipliers (SiPMs)

International Nuclear Information System (INIS)

Shen, Wei

2012-01-01

Silicon Photomultipliers (SiPMs) are novel kind of solid state photon detectors with extremely high photon detection resolution. They are composed of hundreds or thousands of avalanche photon diode pixels connected in parallel. These avalanche photon diodes are operated in Geiger Mode. SiPMs have the same magnitude of multiplication gain compared to the conventional photomultipliers (PMTs). Moreover, they have a lot of advantages such as compactness, relatively low bias voltage and magnetic field immunity etc. Special readout electronics are required to preserve the high performance of the detector. KLauS and STiC are two CMOS ASIC chips designed in particular for SiPMs. KLauS is used for SiPM charge readout applications. Since SiPMs have a much larger detector capacitance compared to other solid state photon detectors such as PIN diodes and APDs, a few special techniques are used inside the chip to make sure a descent signal to noise ratio for pixel charge signal can be obtained. STiC is a chip dedicated to SiPM time-of-flight applications. High bandwidth and low jitter design schemes are mandatory for such applications where time jitter less than tens of picoseconds is required. Design schemes and error analysis as well as measurement results are presented in the thesis.

3 ns single-shot read-out in a quantum dot-based memory structure

International Nuclear Information System (INIS)

Nowozin, T.; Bimberg, D.; Beckel, A.; Lorke, A.; Geller, M.

2014-01-01

Fast read-out of two to six charges per dot from the ground and first excited state in a quantum dot (QD)-based memory is demonstrated using a two-dimensional electron gas. Single-shot measurements on modulation-doped field-effect transistor structures with embedded InAs/GaAs QDs show read-out times as short as 3 ns. At low temperature (T = 4.2 K) this read-out time is still limited by the parasitics of the setup and the device structure. Faster read-out times and a larger read-out signal are expected for an improved setup and device structure

Silicon μ-strip detectors with SVX chip readout

International Nuclear Information System (INIS)

Brueckner, W.; Dropmann, F.; Godbersen, M.; Konorov, I.; Koenigsmann, K.; Newsom, C.; Paul, S.; Povh, B.; Russ, J.; Timm, S.; Vorwalter, K.; Werding, R.

1994-01-01

A new silicon strip detector has been designed and constructed for a fixed target experiment at CERN. The system of about 30 000 channels is equipped with SVX chips and read out via a double buffer into Fastbus memory. Construction and performance during the actual data taking run are discussed. ((orig.))

Monitoring the CMS strip tracker readout system

International Nuclear Information System (INIS)

Mersi, S; Bainbridge, R; Cripps, N; Fulcher, J; Wingham, M; Baulieu, G; Bel, S; Delaere, C; Drouhin, F; Mirabito, L; Cole, J; Giassi, A; Gross, L; Hahn, K; Nikolic, M; Tkaczyk, S

2008-01-01

The CMS Silicon Strip Tracker at the LHC comprises a sensitive area of approximately 200 m 2 and 10 million readout channels. Its data acquisition system is based around a custom analogue front-end chip. Both the control and the readout of the front-end electronics are performed by off-detector VME boards in the counting room, which digitise the raw event data and perform zero-suppression and formatting. The data acquisition system uses the CMS online software framework to configure, control and monitor the hardware components and steer the data acquisition. The first data analysis is performed online within the official CMS reconstruction framework, which provides many services, such as distributed analysis, access to geometry and conditions data, and a Data Quality Monitoring tool based on the online physics reconstruction. The data acquisition monitoring of the Strip Tracker uses both the data acquisition and the reconstruction software frameworks in order to provide real-time feedback to shifters on the operational state of the detector, archiving for later analysis and possibly trigger automatic recovery actions in case of errors. Here we review the proposed architecture of the monitoring system and we describe its software components, which are already in place, the various monitoring streams available, and our experiences of operating and monitoring a large-scale system

Design and prototyping of a readout aggregation ASIC

Energy Technology Data Exchange (ETDEWEB)

Lemke, Frank; Schatral, Sven; Bruening, Ulrich [ZITI, Universitaet Heidelberg (Germany); Som, Indranil; Bhattacharyya, Tarun [Indian Institute of Technology, Kharagpur (India); Collaboration: CBM-Collaboration

2015-07-01

In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

Science.gov (United States)

Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

2018-03-01

Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

Performance of the new amplifier-shaper-discriminator chip for the ATLAS MDT chambers at the HL-LHC

CERN Document Server

INSPIRE-00218480

2016-01-01

The Phase-II Upgrade of the ATLAS Muon Detector requires new electronics for the readout of the MDT drift tubes. The first processing stage, the Amplifier-Shaper-Discriminator (ASD), determines the performance of the readout for crucial parameters like time resolution, gain uniformity, efficiency and noise rejection. An 8-channel ASD chip, using the IBM 130 nm CMOS 8RF-DM technology, has been designed, produced and tested. The area of the chip is 2.2 x 2.9 square mm size. We present results of detailed measurements as well as a comparision with simulation results of the chip behaviour at three different levels of detail.

A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Directory of Open Access Journals (Sweden)

Ming-Zhi Yang

2013-03-01

Full Text Available The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm.

Central FPGA-based destination and load control in the LHCb MHz event readout

International Nuclear Information System (INIS)

Jacobsson, R.

2012-01-01

The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

Central FPGA-based destination and load control in the LHCb MHz event readout

Science.gov (United States)

Jacobsson, R.

2012-10-01

The readout strategy of the LHCb experiment is based on complete event readout at 1 MHz. A set of 320 sub-detector readout boards transmit event fragments at total rate of 24.6 MHz at a bandwidth usage of up to 70 GB/s over a commercial switching network based on Gigabit Ethernet to a distributed event building and high-level trigger processing farm with 1470 individual multi-core computer nodes. In the original specifications, the readout was based on a pure push protocol. This paper describes the proposal, implementation, and experience of a non-conventional mixture of a push and a pull protocol, akin to credit-based flow control. An FPGA-based central master module, partly operating at the LHC bunch clock frequency of 40.08 MHz and partly at a double clock speed, is in charge of the entire trigger and readout control from the front-end electronics up to the high-level trigger farm. One FPGA is dedicated to controlling the event fragment packing in the readout boards, the assignment of the farm node destination for each event, and controls the farm load based on an asynchronous pull mechanism from each farm node. This dynamic readout scheme relies on generic event requests and the concept of node credit allowing load control and trigger rate regulation as a function of the global farm load. It also allows the vital task of fast central monitoring and automatic recovery in-flight of failing nodes while maintaining dead-time and event loss at a minimum. This paper demonstrates the strength and suitability of implementing this real-time task for a very large distributed system in an FPGA where no random delays are introduced, and where extreme reliability and accurate event accounting are fundamental requirements. It was in use during the entire commissioning phase of LHCb and has been in faultless operation during the first two years of physics luminosity data taking.

Pulseshape characteristics of a 300 $\\mu$m PR03 R-measuring VELO sensor read out with a Beetle1.3 chip

CERN Document Server

Palacios, A; Buytaert, J; Borel, J; Collins, P; Eckstein, D; Eklund, L; Ferro-Luzzi, M; Jans, E; Ketel, T; Petrie, D; Pivk, M; Tobin, M

2005-01-01

The signal-to-noise, overspill and undershoot characteristics of a VELO module equipped with Beetle1.3 read-out chips have been measured using 120 GeV pions from the SPS test beam facility at CERN. The module consists of a PR03 n-on-n 300 $\\mu$m R measuring prototype sensor and a fully populated K03 hybrid. Results are presented for a single Beetle1.3 chip with a variety of chip parameter settings controlling the pre-amplifier and shaper currents and feedback voltages, with the objective of establishing the performance of the module and understanding its dependence on the read-out chip settings.

Electronic readout for THGEM detectors based on FPGA TDCs

Energy Technology Data Exchange (ETDEWEB)

Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

2013-07-01

In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

Performance of the ALIBAVA portable readout system with irradiated and non-irradiated microstrip silicon sensors

International Nuclear Information System (INIS)

Marco-Hernadez, R.

2009-01-01

A readout system for microstrip silicon sensors has been developed as a result of collaboration among the University of Liverpool, the CNM of Barcelona and the IFIC of Valencia. The name of this collaboration is ALIBAVA and it is integrated in the RD50 Collaboration. This system is able to measure the collected charge in one or two microstrip silicon sensors by reading out all the channels of the sensor(s), up to 256, as an analogue measurement. The system uses two Beetle chips to read out the detector(s). The Beetle chip is an analogue pipelined readout chip used in the LHCb experiment. The system can operate either with non-irradiated and irradiated sensors as well as with n-type and p-type microstrip silicon sensors. Heavily irradiated sensors will be used at the SLHC, so this system is being to research the performance of microstrip silicon sensors in conditions as similar as possible to the SLHC operating conditions. The system has two main parts: a hardware part and a software part. The hardware part acquires the sensor signals either from external trigger inputs, in case of a radioactive source setup is used, or from a synchronised trigger output generated by the system, if a laser setup is used. This acquired data is sent by USB to be stored in a PC for a further processing. The hardware is a dual board based system. The daughterboard is a small board intended for containing two Beetle readout chips as well as fan-ins and detector support to interface the sensors. The motherboard is intended to process the data, to control the whole hardware and to communicate with the software by USB. The software controls the system and processes the data acquired from the sensors in order to store it in an adequate format file. The main characteristics of the system will be described. Results of measurements acquired with n-type and p-type irradiated and non-irradiated detectors using both the laser and the radioactive source setup will be also presented and discussed

General-purpose readout electronics for white neutron source at China Spallation Neutron Source.

Science.gov (United States)

Wang, Q; Cao, P; Qi, X; Yu, T; Ji, X; Xie, L; An, Q

2018-01-01

The under-construction White Neutron Source (WNS) at China Spallation Neutron Source is a facility for accurate measurements of neutron-induced cross section. Seven spectrometers are planned at WNS. As the physical objectives of each spectrometer are different, the requirements for readout electronics are not the same. In order to simplify the development of the readout electronics, this paper presents a general method for detector signal readout. This method has advantages of expansibility and flexibility, which makes it adaptable to most detectors at WNS. In the WNS general-purpose readout electronics, signals from any kinds of detectors are conditioned by a dedicated signal conditioning module corresponding to this detector, and then digitized by a common waveform digitizer with high speed and high precision (1 GSPS at 12-bit) to obtain the full waveform data. The waveform digitizer uses a field programmable gate array chip to process the data stream and trigger information in real time. PXI Express platform is used to support the functionalities of data readout, clock distribution, and trigger information exchange between digitizers and trigger modules. Test results show that the performance of the WNS general-purpose readout electronics can meet the requirements of the WNS spectrometers.

Merlin: a fast versatile readout system for Medipix3

International Nuclear Information System (INIS)

Plackett, R; Horswell, I; Gimenez, E N; Marchal, J; Omar, D; Tartoni, N

2013-01-01

This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in 'pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

Merlin: a fast versatile readout system for Medipix3

Science.gov (United States)

Plackett, R.; Horswell, I.; Gimenez, E. N.; Marchal, J.; Omar, D.; Tartoni, N.

2013-01-01

This contribution reports on the development of a new high rate readout system for the Medipix3 hybrid pixel ASIC developed by the Detector Group at Diamond Light Source. It details the current functionality of the system and initial results from tests on Diamond's B16 beamline. The Merlin system is based on a National Instruments PXI/FlexRIO system running a Xilinx Virtex5 FPGA. It is capable of recording Medipix3 256 by 256 by 12 bit data frames at over 1 kHz in bursts of 1200 frames and running at over 100 Hz continuously to disk or over a TCP/IP link. It is compatible with the standard Medipix3 single chipboards developed at CERN and is capable of driving them over cable lengths of up to 10 m depending on the data rate required. In addition to a standalone graphical interface, a system of remote TCP/IP control and data transfer has been developed to allow easy integration with third party control systems and scripting languages. Two Merlin systems are being deployed on the B16 and I16 beamlines at Diamond and the system has been integrated with the EPICS/GDA control systems used. Results from trigger synchronisation, fast burst and high rate tests made on B16 in March are reported and demonstrate an encouraging reliability and timing accuracy. In addition to normal high resolution imaging applications of Medipix3, the results indicate the system could profitably be used in `pump and probe' style experiments, where a very accurate, high frame rate is especially beneficial. In addition to these two systems, Merlin is being used by the Detector Group to test the Excalibur 16 chip hybrid modules, and by the LHCb VELO Pixel Upgrade group in their forthcoming testbeams. Additionally the contribution looks forward to further developments and improvements in the system, including full rate quad chip readout capability, multi-FPGA support, long distance optical communication and further functionality enhancements built on the capabilities of the Medipix3 chips.

Progress on TSV technology for Medipix3RX chip

Science.gov (United States)

Sarajlić, M.; Pennicard, D.; Smoljanin, S.; Fritzsch, T.; Zoschke, K.; Graafsma, H.

2017-12-01

The progress of Through Silicon Via (TSV) technology for Medipix3RX chip done at DESY is presented here. The goal of this development is to replace the wire bonds in X-ray detectors with TSVs, in order to reduce the dead area between detectors. We obtained the first working chips assembled together with Si based sensors for X-ray detection. The 3D integration technology, including TSV, Re-distribution layer deposition, bump bonding to the Si sensor and bump bonding to the carrier PCB, was done by Fraunhofer Institute IZM in Berlin. After assembly, the module was successfully tested by recording background radiation and making X-ray images of small objects. The active area of the Medipix3RX chip is 14.1 mm×14.1 mm or 256×256 pixels. During TSV processing, the Medipix3RX chip was thinned from 775 μm original thickness, to 130 μm. The diameter of the vias is 40 μm, and the pitch between the vias is 120 μm. A liner filling approach was used to contact the TSV with the RDL on the backside of the Medipix3RX readout chip.

5A Zirconium Dioxide Ammonia Microsensor Integrated with a Readout Circuit Manufactured Using the 0.18 μm CMOS Process

Science.gov (United States)

Lin, Guan-Ming; Dai, Ching-Liang; Yang, Ming-Zhi

2013-01-01

The study presents an ammonia microsensor integrated with a readout circuit on-a-chip fabricated using the commercial 0.18 μm complementary metal oxide semiconductor (CMOS) process. The integrated sensor chip consists of a heater, an ammonia sensor and a readout circuit. The ammonia sensor is constructed by a sensitive film and the interdigitated electrodes. The sensitive film is zirconium dioxide that is coated on the interdigitated electrodes. The heater is used to provide a working temperature to the sensitive film. A post-process is employed to remove the sacrificial layer and to coat zirconium dioxide on the sensor. When the sensitive film adsorbs or desorbs ammonia gas, the sensor produces a change in resistance. The readout circuit converts the resistance variation of the sensor into the output voltage. The experiments show that the integrated ammonia sensor has a sensitivity of 4.1 mV/ppm. PMID:23503294

Studies for an upgrade of ALICE Inner Tracking System: Pixel chip characterization

Directory of Open Access Journals (Sweden)

Park Jonghan

2017-01-01

Full Text Available Inner Tracking System (ITS of ALICE is used for vertex determination and tracking. Future heavy-ion program at the LHC aims to run with high luminosity. To address this challenge, upgrade program of ITS is underway, which aims at better position resolution (factor of 3, high detection efficiency (>99%, high-rate readout capabilities (100 kHz for Pb-Pb and moderate radiation hardness (> 700 krad. The new ITS will be composed with 7 layers of silicon pixel chip based on Monolithic Active Pixel Sensor (MAPS technology. The characterization test of various version of prototype chips at different phases of development has been performed. This contribution will provide the main characterization results obtained from the measurements performed at laboratories and using test beam for finalizing the pixel chip specification.

On-chip concentration of bacteria using a 3D dielectrophoretic chip and subsequent laser-based DNA extraction in the same chip

International Nuclear Information System (INIS)

Cho, Yoon-Kyoung; Kim, Tae-hyeong; Lee, Jeong-Gun

2010-01-01

We report the on-chip concentration of bacteria using a dielectrophoretic (DEP) chip with 3D electrodes and subsequent laser-based DNA extraction in the same chip. The DEP chip has a set of interdigitated Au post electrodes with 50 µm height to generate a network of non-uniform electric fields for the efficient trapping by DEP. The metal post array was fabricated by photolithography and subsequent Ni and Au electroplating. Three model bacteria samples (Escherichia coli, Staphylococcus epidermidis, Streptococcus mutans) were tested and over 80-fold concentrations were achieved within 2 min. Subsequently, on-chip DNA extraction from the concentrated bacteria in the 3D DEP chip was performed by laser irradiation using the laser-irradiated magnetic bead system (LIMBS) in the same chip. The extracted DNA was analyzed with silicon chip-based real-time polymerase chain reaction (PCR). The total process of on-chip bacteria concentration and the subsequent DNA extraction can be completed within 10 min including the manual operation time.

CdTe layer structures for X-ray and gamma-ray detection directly grown on the Medipix readout-chip by MBE

Science.gov (United States)

Vogt, A.; Schütt, S.; Frei, K.; Fiederle, M.

2017-11-01

This work investigates the potential of CdTe semiconducting layers used for radiation detection directly deposited on the Medipix readout-chip by MBE. Due to the high Z-number of CdTe and the low electron-hole pair creation energy a thin layer suffices for satisfying photon absorption. The deposition takes place in a modified MBE system enabling growth rates up to 10 μm/h while the UHV conditions allow the required high purity for detector applications. CdTe sensor layers deposited on silicon substrates show resistivities up to 5.8 × 108 Ω cm and a preferred (1 1 1) orientation. However, the resistivity increases with higher growth temperature and the orientation gets more random. Additionally, the deposition of a back contact layer sequence in one process simplifies the complex production of an efficient contact on CdTe with aligned work functions. UPS measurements verify a decrease of the work function of 0.62 eV induced by Te doping of the CdTe.

The front-end chip of the SuperB SVT detector

International Nuclear Information System (INIS)

Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.

2013-01-01

The asymmetric e + e − collider SuperB is designed to deliver a high luminosity, greater than 10 36 cm −2 s −1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

Wideband pulse amplifiers for the NECTAr chip

International Nuclear Information System (INIS)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J-F.; Naumann, C.L.; Nayman, P.; Ribó, M.

2012-01-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1–3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Wideband pulse amplifiers for the NECTAr chip

Science.gov (United States)

Sanuy, A.; Delagnes, E.; Gascon, D.; Sieiro, X.; Bolmont, J.; Corona, P.; Feinstein, F.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribó, M.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.; Vorobiov, S.

2012-12-01

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Initial beam test results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Adolphsen, C.; Litke, A.; Schwarz, A.

1986-01-01

Silicon detectors with 256 strips, having a pitch of 25 μm, and connected to two 128 channel NMOS VLSI chips each (Microplex), have been tested in relativistic charged particle beams at CERN and at the Stanford Linear Accelerator Center. The readout chips have an input channel pitch of 47.5 μm and a single multiplexed output which provides voltages proportional to the integrated charge from each strip. The most probable signal height from minimum ionizing tracks was 15 times the rms noise in any single channel. Two-track traversals with a separation of 100 μm were cleanly resolved

Multimedia-Based Chip Design Education.

Science.gov (United States)

Catalkaya, Tamer; Golze, Ulrich

This paper focuses on multimedia computer-based training programs on chip design. Their development must be fast and economical, in order to be affordable by technical university institutions. The self-produced teaching program Illusion, which demonstrates a monitor controller as an example of a small but complete chip design, was implemented to…

Test vehicles for CMS HGCAL readout ASIC

CERN Document Server

Thienpont, Damien

2017-01-01

This paper presents first measurement results of two test vehicles ASIC embedding some building blocks for the future CMS High Granularity CALorimeter (HGCAL) read-out ASIC. They were fabricated in CMOS 130 nm, in order to first design the Analog and Mixed-Signal blocks before going to a complete and complex chip. Such a circuit needs to achieve low noise high dynamic range charge measurement and 20 ps resolution timing capability. The results show good analog performance but with higher noise levels compared to simulations. We present the results of the preamplifiers, shapers and ADCs.

First implementation of the MEPHISTO binary readout architecture for strip detectors

International Nuclear Information System (INIS)

Fischer, P.

2001-01-01

Today's front-end readout chips for multi-channel silicon strip detectors use pipeline-like structures for temporary storage of hit information until arrival of a trigger signal. This approach leads to large-area chips when long trigger latencies are necessary. The MEPHISTO architecture uses a different concept. Hit strips are identified in real time and only the relevant binary hit information is stored in FIFOs. For the typical occupancies in LHC detectors of ∼1 hit per clock cycle this architecture requires less than half the chip area of a typical binary pipeline. This reduces the system cost considerably. At a lower data rate, operation with very long trigger latencies or even without any trigger is possible due to the real-time data sparsification. The Mephisto II architecture is presented and the expected performance is discussed

A novel integrated circuit for semiconductor radiation detectors with sparse readout

International Nuclear Information System (INIS)

Zhang Yacong; Chen Zhognjian; Lu Wengao; Zhao Baoying; Ji Lijiu

2008-01-01

A novel fully integrated CMOS readout circuit for semiconductor radiation detector with sparse readout is presented. The new sparse scheme is: when one channel is being read out, the trigger signal from other channels is delayed and then processed. Therefore, the dead time is reduced and so is the error rate. Besides sparse readout, sequential readout is also allowed, which means the analog voltages and addresses of all the channels are read out sequentially once there is a channel triggered. The circuit comprises Charge Sensitive Amplifier (CSA), pulse shaper, peak detect and hold circuit, and digital logic. A test chip of four channels designed in a 0.5 μ DPTM CMOS technology has been taped out. The results of post simulation indicate that the gain is 79.3 mV/fC with a linearity of 99.92%. The power dissipation is 4 mW per channel. Theory analysis and calculation shows that the error probability is approximately 2.5%, which means a reduction of about 37% is obtained compared with the traditional scanning scheme, assuming a 16-channel system with a particle rate of 100 k/s per channel. (authors)

Architecture of a modular, multichannel readout system for dense electrochemical biosensor microarrays

International Nuclear Information System (INIS)

Ramfos, Ioannis; Birbas, Alexios; Blionas, Spyridon

2015-01-01

The architecture of a modular, multichannel readout system for dense electrochemical microarrays, targeting Lab-on-a-Chip applications, is presented. This approach promotes efficient component reusability through a hybrid multiplexing methodology, maintaining high levels of sampling performance and accuracy. Two readout modes are offered, which can be dynamically interchanged following signal profiling, to cater for both rapid signal transitions and weak current responses. Additionally, functional extensions to the described architecture are discussed, which provide the system with multi-biasing capabilities. A prototype integrated circuit of the proposed architecture’s analog core and a supporting board were implemented to verify the working principles. The system was evaluated using standard loads, as well as electrochemical sensor arrays. Through a range of operating conditions and loads, the prototype exhibited a highly linear response and accurately delivered the readout of input signals with fast transitions and wide dynamic ranges. (paper)

Rework of flip chip bonded radiation pixel detectors

International Nuclear Information System (INIS)

Vaehaenen, S.; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S.

2008-01-01

In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process

Rework of flip chip bonded radiation pixel detectors

Energy Technology Data Exchange (ETDEWEB)

Vaehaenen, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)], E-mail: sami.vahanen@vtt.fi; Heikkinen, H.; Pohjonen, H.; Salonen, J.; Savolainen-Pulli, S. [VTT MEMS and Micropackaging, Espoo 02150 (Finland)

2008-06-11

In this paper, some practical aspects of reworking flip chip hybridized pixel detectors are discussed. As flip chip technology has been advancing in terms of placement accuracy and reliability, large-area hybrid pixel detectors have been developed. The area requirements are usually fulfilled by placing several readout chips (ROCs) on single sensor chip. However, as the number of ROCs increases, the probability of failure in the hybridization process and the ROC operation also increases. Because high accuracy flip chip bonding takes time, a significant part of the price of a pixel detector comes from the flip chip assembly process itself. As large-area detector substrates are expensive, and many flip chip placements are required, the price of an assembled detector can become very high. In a typical case, there is just one bad ROC (out of several) on a faulty detector to be replaced. Considering the high price of pixel detectors and the fact that reworking faulty ROCs does not take much longer than the original placement, it is worthwhile to investigate the feasibility of a rework process.

Integrated optical readout for miniaturization of cantilever-based sensor system

DEFF Research Database (Denmark)

Nordström, Maria; Zauner, Dan; Calleja, Montserrat

2007-01-01

The authors present the fabrication and characterization of an integrated optical readout scheme based on single-mode waveguides for cantilever-based sensors. The cantilever bending is read out by monitoring changes in the optical intensity of light transmitted through the cantilever that also acts...

Development and characterisation of a radiation hard readout chip for the LHCb outer tracker detector

International Nuclear Information System (INIS)

Stange, U.

2005-01-01

The reconstruction of charged particle tracks in the Outer Tracker detector of the LHCb experiment requires to measure the drift times of the straw tubes. A Time to Digital Converter (TDC) chip has been developed for this task. The chip integrates into the LHCb data acquisition schema and fulfils the requirements of the detector. The OTIS chip is manufactured in a commercial 0.25 μm CMOS process. A 32-channel TDC core drives the drift time measurement (25 ns measurement range, 390 ps nominal resolution) without introducing dead times. The resulting drift times are buffered until a trigger decision arrives after the fixed latency of 4 μs. In case of a trigger accept signal, the digital control core processes and transmits the corresponding data to the following data acquisition stage. Drift time measurement and data processing are independent from the detector occupancy. The digital control core of the OTIS chip has been developed within this doctoral thesis. It has been integrated into the TDC chip together with other constituents of the chip. Several test chips and prototype versions of the TDC chip have been characterised. The present version of the chip OTIS1.2 fulfils all requirements and is ready for mass production. (Orig.)

Cantilever-based sensor with integrated optical read-out using single mode waveguides

DEFF Research Database (Denmark)

Nordström, Maria; Zauner, Dan; Calleja, Montserrat

2007-01-01

This work presents the design, fabrication and mechanical characterisation of an integrated optical read-out scheme for cantilever-based biosensors. A cantilever can be used as a biosensor by monitoring its bending caused by the surface stress generated due to chemical reactions occurring on its...... surface. Here, we present a novel integrated optical read-out scheme based on single-mode waveguides that enables the fabrication of a compact system. The complete system is fabricated in the polymer SU-8. This manuscript shows the principle of operation and the design well as the fabrication...

White noise of Nb-based microwave superconducting quantum interference device multiplexers with NbN coplanar resonators for readout of transition edge sensors

Science.gov (United States)

Kohjiro, Satoshi; Hirayama, Fuminori; Yamamori, Hirotake; Nagasawa, Shuichi; Fukuda, Daiji; Hidaka, Mutsuo

2014-06-01

White noise of dissipationless microwave radio frequency superconducting quantum interference device (RF-SQUID) multiplexers has been experimentally studied to evaluate their readout performance for transition edge sensor (TES) photon counters ranging from near infrared to gamma ray. The characterization has been carried out at 4 K, first to avoid the low-frequency fluctuations present at around 0.1 K, and second, for a feasibility study of readout operation at 4 K for extended applications. To increase the resonant Q at 4 K and maintain low noise SQUID operation, multiplexer chips consisting of niobium nitride (NbN)-based coplanar-waveguide resonators and niobium (Nb)-based RF-SQUIDs have been developed. This hybrid multiplexer exhibited 1 × 104 ≤ Q ≤ 2 × 104 and the square root of spectral density of current noise referred to the SQUID input √SI = 31 pA/√Hz. The former and the latter are factor-of-five and seven improvements from our previous results on Nb-based resonators, respectively. Two-directional readout on the complex plane of the transmission component of scattering matrix S21 enables us to distinguish the flux noise from noise originating from other sources, such as the cryogenic high electron mobility transistor (HEMT) amplifier. Systematic noise measurements with various microwave readout powers PMR make it possible to distinguish the contribution of noise sources within the system as follows: (1) The achieved √SI is dominated by the Nyquist noise from a resistor at 4 K in parallel to the SQUID input coil which is present to prevent microwave leakage to the TES. (2) The next dominant source is either the HEMT-amplifier noise (for small values of PMR) or the quantization noise due to the resolution of 300-K electronics (for large values of PMR). By a decrease of these noise levels to a degree that is achievable by current technology, we predict that the microwave RF-SQUID multiplexer can exhibit √SI ≤ 5 pA/√Hz, i.e., close to √SI of

White noise of Nb-based microwave superconducting quantum interference device multiplexers with NbN coplanar resonators for readout of transition edge sensors

International Nuclear Information System (INIS)

Kohjiro, Satoshi; Hirayama, Fuminori; Yamamori, Hirotake; Nagasawa, Shuichi; Fukuda, Daiji; Hidaka, Mutsuo

2014-01-01

White noise of dissipationless microwave radio frequency superconducting quantum interference device (RF-SQUID) multiplexers has been experimentally studied to evaluate their readout performance for transition edge sensor (TES) photon counters ranging from near infrared to gamma ray. The characterization has been carried out at 4 K, first to avoid the low-frequency fluctuations present at around 0.1 K, and second, for a feasibility study of readout operation at 4 K for extended applications. To increase the resonant Q at 4 K and maintain low noise SQUID operation, multiplexer chips consisting of niobium nitride (NbN)-based coplanar-waveguide resonators and niobium (Nb)-based RF-SQUIDs have been developed. This hybrid multiplexer exhibited 1 × 10 4  ≤ Q ≤ 2 × 10 4 and the square root of spectral density of current noise referred to the SQUID input √S I  = 31 pA/√Hz. The former and the latter are factor-of-five and seven improvements from our previous results on Nb-based resonators, respectively. Two-directional readout on the complex plane of the transmission component of scattering matrix S 21 enables us to distinguish the flux noise from noise originating from other sources, such as the cryogenic high electron mobility transistor (HEMT) amplifier. Systematic noise measurements with various microwave readout powers P MR make it possible to distinguish the contribution of noise sources within the system as follows: (1) The achieved √S I is dominated by the Nyquist noise from a resistor at 4 K in parallel to the SQUID input coil which is present to prevent microwave leakage to the TES. (2) The next dominant source is either the HEMT-amplifier noise (for small values of P MR ) or the quantization noise due to the resolution of 300-K electronics (for large values of P MR ). By a decrease of these noise levels to a degree that is achievable by current technology, we predict that the microwave RF-SQUID multiplexer can exhibit �

Progress in the development of the DTMROC time measurement chip for the ATLAS transition radiation tracker (TRT)

CERN Document Server

Alexander, C; Dressnandt, N; Ekenberg, T; Farthouat, Philippe; Keener, P T; Lam, N; La Marra, D; Mann, J; Newcomer, F M; Ryzhov, V; Söderberg, M; Szczygiel, R; Van Berg, R; Williams, H H

2001-01-01

A 16-channel digital time-measurement readout chip (DTMROC) has been fabricated in the TEMIC/DM1LL left bracket 1 right bracket BI- CMOS radiation-hard process for the Large Hadron Collider's (LHC) Transition Radiation Tracker (ATLAS/TRT) at CERN left bracket 2 right bracket . The chip receives discriminated straw-drift-tube signals from bipolar amplifier-shaper-discriminator chips (ASDBLR). measures the arrival time in 3.125 ns increments ( plus or minus 1 ns), and stores the data in a pipeline for 3.3mus. A trigger signal (L1A) causes the data to be tagged with a time stamp and stored for readout- Up to 13 events may be stored in an on-chip buffer while data is being clocked out in a 40 MHz serial stream. The chip has been designed to function after exposure to 1x10**1**4 protons/cm**2 and 1 Mrad total dose. System beam-tests have demonstrated measurement of track positions with a resolution of 165mum and 85% efficiency at rates up to 18MHz. 6 Refs.

Wideband pulse amplifiers for the NECTAr chip

Energy Technology Data Exchange (ETDEWEB)

Sanuy, A., E-mail: asanuy@ecm.ub.es [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Delagnes, E. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Gascon, D. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Sieiro, X. [Departament d' Electronica, Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, CC072, bat. 13, place Eugene Bataillon, 34095 Montpellier (France); Glicenstein, J-F. [IRFU/DSM/CEA, CE-Saclay, Bat. 141 SEN Saclay, F-91191, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Barre 12-22, 1er etage, 4 place Jussieu, 75252 Paris (France); Ribo, M. [Dept. AM i Dept. ECM, Institut de Ciencies del Cosmos (ICC), Universitat de Barcelona. Marti i Franques 1, E08028, Barcelona (Spain); and others

2012-12-11

The NECTAr collaboration's FE option for the camera of the CTA is a 16 bits and 1-3 GS/s sampling chip based on analog memories including most of the readout functions. This works describes the input amplifiers of the NECTAr ASIC. A fully differential wideband amplifier, with voltage gain up to 20 V/V and a BW of 400 MHz. As it is impossible to design a fully differential OpAmp with an 8 GHz GBW product in a 0.35 CMOS technology, an alternative implementation based on HF linearized transconductors is explored. The output buffer is a class AB miller operational amplifier, with special non-linear current boost.

Design of a readout ASIC for gas detectors with self-amplification

International Nuclear Information System (INIS)

Deng Zhi; Liu Yinong

2009-01-01

A readout ASIC has been designed for gas detectors with self-amplification such as GEM and RPC. It provides amplification and shaping of the detector signals and buffers them to the free running ADCs. The charge gain and the shaping time can be adjusted. The programmability of gain and shaping time is very convenient for studying detector performance under different gas gain and also expands the application range of the chip. The ENC increases as charge gain decreases below 10 mV/fC because the noise from the shaper becomes significant. The chip is designed in Chartered 0.35μm 2P4M CMOS process. Detailed design and simulation results are described in the paper. (authors)

GOSSIP: A vertex detector combining a thin gas layer as signal generator with a CMOS readout pixel array

Energy Technology Data Exchange (ETDEWEB)

Campbell, M. [CERN/MediPix Consortium, Geneva (Switzerland); Heijne, E.H.M. [CERN/MediPix Consortium, Geneva (Switzerland); Llopart, X. [CERN/MediPix Consortium, Geneva (Switzerland); Colas, P. [DAPNIA, CEA Saclay, 91191 Gif sur Yvette Cedex (France); Giganon, A. [DAPNIA, CEA Saclay, 91191 Gif sur Yvette Cedex (France); Giomataris, Y. [DAPNIA, CEA Saclay, 91191 Gif sur Yvette Cedex (France); Chefdeville, M. [NIKHEF, Amsterdam (Netherlands); Colijn, A.P. [NIKHEF, Amsterdam (Netherlands); Fornaini, A. [NIKHEF, Amsterdam (Netherlands); Graaf, H. van der [NIKHEF, Amsterdam (Netherlands)]. E-mail: vdgraaf@nikhef.nl; Kluit, P. [NIKHEF, Amsterdam (Netherlands); Timmermans, J. [NIKHEF, Amsterdam (Netherlands); Visschers, J.L. [NIKHEF, Amsterdam (Netherlands); Schmitz, J. [University of Twente/MESA (Netherlands)

2006-05-01

A small TPC has been read out by means of a Medipix2 chip as direct anode. A Micromegas foil was placed 50{mu}m above the chip, and electron multiplication occurred in the gap. With a He/isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90%. With this new readout technology for gas-filled detectors we recorded many image frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as {delta}-rays. With a gas layer thickness of only 1mm, the device could be applied as vertex detector, outperforming all Si-based detectors.

GOSSIP: A vertex detector combining a thin gas layer as signal generator with a CMOS readout pixel array

International Nuclear Information System (INIS)

Campbell, M.; Heijne, E.H.M.; Llopart, X.; Colas, P.; Giganon, A.; Giomataris, Y.; Chefdeville, M.; Colijn, A.P.; Fornaini, A.; Graaf, H. van der; Kluit, P.; Timmermans, J.; Visschers, J.L.; Schmitz, J.

2006-01-01

A small TPC has been read out by means of a Medipix2 chip as direct anode. A Micromegas foil was placed 50μm above the chip, and electron multiplication occurred in the gap. With a He/isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90%. With this new readout technology for gas-filled detectors we recorded many image frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as δ-rays. With a gas layer thickness of only 1mm, the device could be applied as vertex detector, outperforming all Si-based detectors

GOSSIP: A vertex detector combining a thin gas layer as signal generator with a CMOS readout pixel array

Science.gov (United States)

Campbell, M.; Heijne, E. H. M.; Llopart, X.; Colas, P.; Giganon, A.; Giomataris, Y.; Chefdeville, M.; Colijn, A. P.; Fornaini, A.; van der Graaf, H.; Kluit, P.; Timmermans, J.; Visschers, J. L.; Schmitz, J.

2006-05-01

A small TPC has been read out by means of a Medipix2 chip as direct anode. A Micromegas foil was placed 50 μm above the chip, and electron multiplication occurred in the gap. With a He/isobutane 80/20 mixture, gas multiplication factors up to tens of thousands were achieved, resulting in an efficiency for detecting single electrons of better than 90%. With this new readout technology for gas-filled detectors we recorded many image frames containing 2D images with tracks from cosmic muons. Along these tracks, electron clusters were observed, as well as δ-rays. With a gas layer thickness of only 1 mm, the device could be applied as vertex detector, outperforming all Si-based detectors.

Dedicated multichannel readout ASIC coupled with single crystal diamond for dosimeter application

International Nuclear Information System (INIS)

Fabbri, A; Notaristefani, F De; Galasso, M; Cencelli, V Orsolini; Falco, M D; Marinelli, M; Tortora, L; Verona, C; Rinati, G Verona

2013-01-01

This paper reports on the tests of a low-noise, multi-channel readout integrated circuit used as a readout electronic front-end for a diamond multi-pixel dosimeter. The system is developed for dose distribution measurement in radiotherapy applications. The first 10-channel prototype chip was designed and fabricated in a 0.18 um CMOS process. Every channel includes a charge integrator with a 10 pF capacitor and a double slope A/D converter. The diamond multi-pixel detector, based on CVD synthetic single crystal diamond Schottky diodes, is made by a 3 × 3 sensor matrix. The overall device has been tested under irradiation with 6 MeV radio therapeutic photon beams at the Policlinico ''Tor Vergata'' (PTV) hospital. Measurements show a 20 fA RMS leakage current from the front-end input stage and a negligible dark current from the diamond detector, a stable temporal response and a good linear behaviour as a function of both dose and dose rate. These characteristics were common to each tested channel.

The PASTA chip - A free-running readout ASIC for silicon strip sensors in PANDA

Energy Technology Data Exchange (ETDEWEB)

Goerres, Andre; Stockmanns, Tobias; Ritman, James [Institut fuer Kernphysik, Forschungszentrum Juelich, Juelich (Germany); Rivetti, Angelo [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The PANDA experiment is a multi purpose detector, investigating hadron physics in the charm quark mass regime. It is one of the main experiments at the future FAIR accelerator facility, using pp annihilations from a 1.5-15 GeV/c anti-proton beam. Because of the broad physics spectrum and the similarity of event and background signals, PANDA does not rely on a hardware-level trigger decision. The innermost of PANDA's sub-systems is the Micro Vertex Detector (MVD), consisting of silicon pixel and strip sensors. The latter will be read out by a specialized, free-running readout front-end called PANDA Strip ASIC (PASTA). It has to face a high event rate of up to 40 kHz/ch in an radiation-intense environment. To fulfill the MVD's requirements, it has to give accurate timing information to incoming events (<10 ns) and determine the collected charge with an 8-bit precision. The design has to meet cooling and placing restrictions, leading to a very low power consumption (<4 mW/ch) and limited dimensions. Therefore, a simple, time-based readout approach is chosen. In this talk, the conceptual design of the front-end is presented.

An Automatic Baseline Regulation in a Highly Integrated Receiver Chip for JUNO

Science.gov (United States)

Muralidharan, P.; Zambanini, A.; Karagounis, M.; Grewing, C.; Liebau, D.; Nielinger, D.; Robens, M.; Kruth, A.; Peters, C.; Parkalian, N.; Yegin, U.; van Waasen, S.

2017-09-01

This paper describes the data processing unit and an automatic baseline regulation of a highly integrated readout chip (Vulcan) for JUNO. The chip collects data continuously at 1 Gsamples/sec. The Primary data processing which is performed in the integrated circuit can aid to reduce the memory and data processing efforts in the subsequent stages. In addition, a baseline regulator compensating a shift in the baseline is described.

60 GHz wireless data transfer for tracker readout systems—first studies and results

International Nuclear Information System (INIS)

Dittmeier, S.; Berger, N.; Schöning, A.; Soltveit, H.K.; Wiedner, D.

2014-01-01

To allow highly granular trackers to contribute to first level trigger decisions or event filtering, a fast readout system with very high bandwidth is required. Space, power and material constraints, however, pose severe limitations on the maximum available bandwidth of electrical or optical data transfers. A new approach for the implementation of a fast readout system is the application of a wireless data transfer at a carrier frequency of 60 GHz. The available bandwidth of several GHz allows for data rates of multiple Gbps per link. 60 GHz transceiver chips can be produced with a small form factor and a high integration level. A prototype transceiver currently under development at the University of Heidelberg is briefly described in this paper. To allow easy and fast future testing of the chip's functionality, a bit error rate test has been developed with a commercially available transceiver. Crosstalk might be a big issue for a wireless readout system with many links in a tracking detector. Direct crosstalk can be avoided by using directive antennas, linearly polarized waves and frequency channeling. Reflections from tracking modules can be reduced by applying an absorbing material like graphite foam. Properties of different materials typically used in tracking detectors and graphite foam in the 60 GHz frequency range are presented. For data transmission tests, links using commercially available 60 GHz transmitters and receivers are used. Studies regarding crosstalk and the applicability of graphite foam, Kapton horn antennas and polarized waves are shown

The GOTTHARD charge integrating readout detector: design and characterization

International Nuclear Information System (INIS)

Mozzanica, A; Bergamaschi, A; Dinapoli, R; Greiffenberg, D; Henrich, B; Johnson, I; Valeria, R; Schmitt, B; Xintian, S; Graafsma, H; Lohmann, M

2012-01-01

A charge integrating readout ASIC (Application Specific Integrated Circuit) for silicon strip sensors has been developed at PSI in collaboration with DESY. The goal of the project is to provide a charge integrating readout system able to cope with the pulsed beam of XFEL machines and at the same time to retain the high dynamic range and single photon resolution performances typical for photon counting systems. The ASIC, designed in IBM 130 nm CMOS technology, takes advantage of its three gain stages with automatic stage selection to achieve a dynamic range of 10000 12 keV photons and a noise better than 300 e.n.c.. The 4 analog outputs of the ASIC are optimized for speed, allowing frame rates higher than 1 MHz, without compromises on linearity and noise performances. This work presents the design features of the ASIC, and reports the characterization results of the chip itself.

First results from a silicon-strip detector with VLSI readout

International Nuclear Information System (INIS)

Anzivino, G.; Horisberger, R.; Hubbeling, L.; Hyams, B.; Parker, S.; Breakstone, A.; Litke, A.M.; Walker, J.T.; Bingefors, N.

1986-01-01

A 256-strip silicon detector with 25 μm strip pitch, connected to two 128-channel NMOS VLSI chips (Microplex), has been tested using straight-through tracks from a ruthenium beta source. The readout channels have a pitch of 47.5 μm. A single multiplexed output provides voltages proportional to the integrated charge from each strip. The most probable signal height from the beta traversals is approximately 14 times the rms noise in any single channel. (orig.)

LHCb: Radiation tolerance tests of SRAM-based FPGAs for the possible usage in the readout electronics for the LHCb experiment

CERN Multimedia

Faerber, C; Wiedner, D; Leveringzon, B; Ekelhof, R

2013-01-01

This paper describes radiation studies of SRAM-based FPGAs as a central component of the electronics for a possible upgrade of the LHCb Outer Tracker readout electronics to a frequency of 40 MHz. Two Arria GX FPGAs were irradiated with 20 MeV protons to radiation doses of up to 7 Mrad. During and between the irradiation periods the different FPGA currents, the package temperature, the firmware error rate, the PLL stability, and the stability of a 32 channel TDC implemented on the FPGA were monitored. Results on the radiation tolerance of the FPGA and the measured firmware error rates will be presented. The Arria GX FPGA fulfils the radiation tolerance required for the LHCb upgrade (30 krad) and an expected firmware error rate of 10$^{-6}$ Hz makes the chip viable for the LHCb Upgrade.

A novel high electrode count spike recording array using an 81,920 pixel transimpedance amplifier-based imaging chip.

Science.gov (United States)

Johnson, Lee J; Cohen, Ethan; Ilg, Doug; Klein, Richard; Skeath, Perry; Scribner, Dean A

2012-04-15

Microelectrode recording arrays of 60-100 electrodes are commonly used to record neuronal biopotentials, and these have aided our understanding of brain function, development and pathology. However, higher density microelectrode recording arrays of larger area are needed to study neuronal function over broader brain regions such as in cerebral cortex or hippocampal slices. Here, we present a novel design of a high electrode count picocurrent imaging array (PIA), based on an 81,920 pixel Indigo ISC9809 readout integrated circuit camera chip. While originally developed for interfacing to infrared photodetector arrays, we have adapted the chip for neuron recording by bonding it to microwire glass resulting in an array with an inter-electrode pixel spacing of 30 μm. In a high density electrode array, the ability to selectively record neural regions at high speed and with good signal to noise ratio are both functionally important. A critical feature of our PIA is that each pixel contains a dedicated low noise transimpedance amplifier (∼0.32 pA rms) which allows recording high signal to noise ratio biocurrents comparable to single electrode voltage amplifier recordings. Using selective sampling of 256 pixel subarray regions, we recorded the extracellular biocurrents of rabbit retinal ganglion cell spikes at sampling rates up to 7.2 kHz. Full array local electroretinogram currents could also be recorded at frame rates up to 100 Hz. A PIA with a full complement of 4 readout circuits would span 1cm and could acquire simultaneous data from selected regions of 1024 electrodes at sampling rates up to 9.3 kHz. Published by Elsevier B.V.

OSL signal of IC chips from mobile phones for dose assessment in accidental dosimetry

International Nuclear Information System (INIS)

Mrozik, A.; Marczewska, B.; Bilski, P.; Książek, M.

2017-01-01

The rapid assessment of the radiation dose is very important for the prediction of biological effects after unintended exposition. The materials for use as dosimeters in accidental dosimetry should be everyday objects which are usually placed near the human body, for example mobile phones. IC (Integrated Circuit) chip is one of several electronic components of mobile phones which give a luminescent signal. The measurements of samples from different mobile phones and smartphones were conducted by optically stimulated luminescence (OSL) and thermoluminescence (TL) methods. The OSL measurement was performed in two ways: with readouts at room temperature and at 100 °C. This work is focused on determination of OSL dose response of IC chips, minimum detectable dose (MDD), OSL signal stability in the time after the exposition, its repeatability and sensitivity to light. Several tests of the assessment of unknown doses were also conducted. The readouts at 100 °C indicate the reducing of the fading of OSL signal in the first hours after irradiation in comparison with room temperature readouts. The obtained results showed relatively good dosimetric properties of IC chips: their high sensitivity to the ionizing radiation, linear dose response up to 10 Gy and a good reproducibility of OSL signal which can allow the dose recovery of doses less than 2 Gy in 14 days after an incident with the accuracy better than 25%. The fading is a drawback of IC chips and the fading factor should be considered when calculating the dose. - Highlights: • IC chips from smartphones demonstrated high potential for accidental dosimetry. • Minimum detectable dose was estimated as a value of 50 mGy. • Samples showed linear dose response for the dose range from 0.05 Gy up to 10 Gy.

Conditional Dispersive Readout of a CMOS Single-Electron Memory Cell

Science.gov (United States)

Schaal, S.; Barraud, S.; Morton, J. J. L.; Gonzalez-Zalba, M. F.

2018-05-01

Quantum computers require interfaces with classical electronics for efficient qubit control, measurement, and fast data processing. Fabricating the qubit and the classical control layer using the same technology is appealing because it will facilitate the integration process, improving feedback speeds and offering potential solutions to wiring and layout challenges. Integrating classical and quantum devices monolithically, using complementary metal-oxide-semiconductor (CMOS) processes, enables the processor to profit from the most mature industrial technology for the fabrication of large-scale circuits. We demonstrate a CMOS single-electron memory cell composed of a single quantum dot and a transistor that locks charge on the quantum-dot gate. The single-electron memory cell is conditionally read out by gate-based dispersive sensing using a lumped-element L C resonator. The control field-effect transistor (FET) and quantum dot are fabricated on the same chip using fully depleted silicon-on-insulator technology. We obtain a charge sensitivity of δ q =95 ×10-6e Hz-1 /2 when the quantum-dot readout is enabled by the control FET, comparable to results without the control FET. Additionally, we observe a single-electron retention time on the order of a second when storing a single-electron charge on the quantum dot at millikelvin temperatures. These results demonstrate first steps towards time-based multiplexing of gate-based dispersive readout in CMOS quantum devices opening the path for the development of an all-silicon quantum-classical processor.

Experimental characterization of the 192 channel Clear-PEM frontend ASIC coupled to a multi-pixel APD readout of LYSO:Ce crystals

International Nuclear Information System (INIS)

Albuquerque, Edgar; Bexiga, Vasco; Bugalho, Ricardo; Carrico, Bruno; Ferreira, Claudia S.; Ferreira, Miguel; Godinho, Joaquim; Goncalves, Fernando; Leong, Carlos; Lousa, Pedro; Machado, Pedro; Moura, Rui; Neves, Pedro; Ortigao, Catarina; Piedade, Fernando; Pinheiro, Joao F.; Rego, Joel; Rivetti, Angelo; Rodrigues, Pedro; Silva, Jose C.

2009-01-01

In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC), which incorporates 192 low-noise charge pre-amplifiers, shapers, analog memory cells and digital control blocks. Pulses are continuously stored in memory cells at clock frequency. Channels above a common threshold voltage are readout for digitization by off-chip free-sampling ADCs. The ASIC has a size of 7.3x9.8mm 2 and was implemented in a AMS 0.35μm CMOS technology. In this paper the experimental characterization of the Clear-PEM frontend ASIC, reading out multi-pixel APDs coupled to LYSO:Ce crystal matrices, is presented. The chips were mounted on a custom test board connected to six APD arrays and to the data acquisition system. Six 32-pixel LYSO:Ce crystal matrices coupled on both sides to APD arrays were readout by two test boards. All 384 channels were operational. The chip power consumption is 660 mW (3.4 mW per channel). A very stable behavior of the chip was observed, with an estimated ENC of 1200-1300e - at APD gain 100. The inter-channel noise dispersion and mean baseline variation is less than 8% and 0.5%, respectively. The spread in the gain between different channels is found to be 1.5%. Energy resolution of 16.5% at 511 keV and 12.8% at 662 keV has been measured. Timing measurements between the two APDs that readout the same crystal is extracted and compared with detailed Monte Carlo simulations. At 511 keV the measured single photon time RMS resolution is 1.30 ns, in very good agreement with the expected value of 1.34 ns.

Nanophotonic lab-on-a-chip platforms including novel bimodal interferometers, microfluidics and grating couplers.

Science.gov (United States)

Duval, Daphné; González-Guerrero, Ana Belén; Dante, Stefania; Osmond, Johann; Monge, Rosa; Fernández, Luis J; Zinoviev, Kirill E; Domínguez, Carlos; Lechuga, Laura M

2012-05-08

One of the main limitations for achieving truly lab-on-a-chip (LOC) devices for point-of-care diagnosis is the incorporation of the "on-chip" detection. Indeed, most of the state-of-the-art LOC devices usually require complex read-out instrumentation, losing the main advantages of portability and simplicity. In this context, we present our last advances towards the achievement of a portable and label-free LOC platform with highly sensitive "on-chip" detection by using nanophotonic biosensors. Bimodal waveguide interferometers fabricated by standard silicon processes have been integrated with sub-micronic grating couplers for efficient light in-coupling, showing a phase resolution of 6.6 × 10(-4)× 2π rad and a limit of detection of 3.3 × 10(-7) refractive index unit (RIU) in bulk. A 3D network of SU-8 polymer microfluidics monolithically assembled at the wafer-level was included, ensuring perfect sealing and compact packaging. To overcome some of the drawbacks inherent to interferometric read-outs, a novel all-optical wavelength modulation system has been implemented, providing a linear response and a direct read-out of the phase variation. Sensitivity, specificity and reproducibility of the wavelength modulated BiMW sensor has been demonstrated through the label-free immunodetection of the human hormone hTSH at picomolar level using a reliable biofunctionalization process.

Rapid Newcastle Disease Virus Detection Based on Loop-Mediated Isothermal Amplification and Optomagnetic Readout

DEFF Research Database (Denmark)

Tian, Bo; Ma, Jing; Zardán Gómez de la Torre, Teresa

2016-01-01

Rapid and sensitive diagnostic methods based on isothermal amplification are ideal substitutes for PCR in out-of-lab settings. However, there are bottlenecks in terms of establishing low-cost and user-friendly readout methods for isothermal amplification schemes. Combining the high amplification...... efficiency of loop-mediated isothermal amplification (LAMP) with an optomagnetic nanoparticle-based readout system, we demonstrate ultrasensitive and rapid detection of Newcastle disease virus RNA. Biotinylated amplicons of LAMP and reverse transcription LAMP (RT-LAMP) bind to streptavidin-coated magnetic...... nanoparticles (MNPs) resulting in a dramatical increase in the hydrodynamic size of the MNPs. This increase was measured by an optomagnetic readout system and provided quantitative information on the amount of LAMP target sequence. Our assay resulted in a limit of detection of 10 aM of target sequence...

Triroc: A Multi-Channel SiPM Read-Out ASIC for PET/PET-ToF Application

Science.gov (United States)

Ahmad, Salleh; Fleury, Julien; de la Taille, Christophe; Seguin-Moreau, Nathalie; Dulucq, Frederic; Martin-Chassard, Gisele; Callier, Stephane; Thienpont, Damien; Raux, Ludovic

2015-06-01

Triroc is the latest addition to SiPM readout ASICs family developed at Weeroc, a start-up company from the Omega microelectronics group of IN2P3/CNRS. This chip is developed under the framework TRIMAGE European project which is aimed for building a cost effective tri-modal PET/MR/EEG brain scan. To ensure the flexibility and compatibility with any SiPM in the market, the ASIC is designed to be capable of accepting negative and positive polarity input signals. This 64-channel ASIC, is suitable for SiPM readout which requires high accuracy timing and charge measurements. Targeted applications would be PET prototyping with time-of-flight capability. Main features of Triroc includes high dynamic range ADC up to 2500 photoelectrons and TDC fine time binning of 40 ps. Triroc requires very minimal external components which means it is a good contender for compact multichannel PET prototyping. Triroc is designed by using AMS 0.35 μm SiGe technology and it was submitted in March 2014. The detail design of this chip will be presented.

submitter Development of the readout for the IBL upgrade project of the ATLAS Pixel Detector

CERN Document Server

Krieger, Nina

The LHC luminosity is upgraded in several phases until 2022. The resulting higher occupancy degrades the detector performance of the current Pixel Detector. To provide a good performance during the LHC luminosity upgrade, a fourth pixel layer is inserted into the existing ATLAS Pixel Detector. A new FE-I4 readout chip and a new data acquisition chain are required to cope with the higher track rate and the resulting increased bandwidth. Among others, this includes a new readout board: the IBL ROD. One component of this board is the DSP which creates commands for the FE-I4 chip and has to be upgraded as well. In this thesis, the first tests of the IBL ROD prototype are presented. A correct communication of the DSP to its external memory is verified. Moreover, the implementations for an IBL DSP code are described and tested. This includes the first configuration of the FE-I4 with an IBL ROD. In addition, a working communication with the Histogrammer SDRAM and the Input FIFO on the IBL ROD are demonstrated.

On-chip integration of a superconducting microwave circulator and a Josephson parametric amplifier

Science.gov (United States)

Rosenthal, Eric I.; Chapman, Benjamin J.; Moores, Bradley A.; Kerckhoff, Joseph; Malnou, Maxime; Palken, D. A.; Mates, J. A. B.; Hilton, G. C.; Vale, L. R.; Ullom, J. N.; Lehnert, K. W.

Recent progress in microwave amplification based on parametric processes in superconducting circuits has revolutionized the measurement of feeble microwave signals. These devices, which operate near the quantum limit, are routinely used in ultralow temperature cryostats to: readout superconducting qubits, search for axionic dark matter, and characterize astrophysical sensors. However, these amplifiers often require ferrite circulators to separate incoming and outgoing traveling waves. For this reason, measurement efficiency and scalability are limited. In order to facilitate the routing of quantum signals we have created a superconducting, on-chip microwave circulator without permanent magnets. We integrate our circulator on-chip with a Josephson parametric amplifier for the purpose of near quantum-limited directional amplification. In this talk I will present a design overview and preliminary measurements.

A High-Speed, Event-Driven, Active Pixel Sensor Readout for Photon-Counting Microchannel Plate Detectors

Science.gov (United States)

Kimble, Randy A.; Pain, Bedabrata; Norton, Timothy J.; Haas, J. Patrick; Oegerle, William R. (Technical Monitor)

2002-01-01

Silicon array readouts for microchannel plate intensifiers offer several attractive features. In this class of detector, the electron cloud output of the MCP intensifier is converted to visible light by a phosphor; that light is then fiber-optically coupled to the silicon array. In photon-counting mode, the resulting light splashes on the silicon array are recognized and centroided to fractional pixel accuracy by off-chip electronics. This process can result in very high (MCP-limited) spatial resolution while operating at a modest MCP gain (desirable for dynamic range and long term stability). The principal limitation of intensified CCD systems of this type is their severely limited local dynamic range, as accurate photon counting is achieved only if there are not overlapping event splashes within the frame time of the device. This problem can be ameliorated somewhat by processing events only in pre-selected windows of interest of by using an addressable charge injection device (CID) for the readout array. We are currently pursuing the development of an intriguing alternative readout concept based on using an event-driven CMOS Active Pixel Sensor. APS technology permits the incorporation of discriminator circuitry within each pixel. When coupled with suitable CMOS logic outside the array area, the discriminator circuitry can be used to trigger the readout of small sub-array windows only when and where an event splash has been detected, completely eliminating the local dynamic range problem, while achieving a high global count rate capability and maintaining high spatial resolution. We elaborate on this concept and present our progress toward implementing an event-driven APS readout.

Design and standalone characterisation of a capacitively coupled HV-CMOS sensor chip for the CLIC vertex detector

Science.gov (United States)

Kremastiotis, I.; Ballabriga, R.; Campbell, M.; Dannheim, D.; Fiergolski, A.; Hynds, D.; Kulis, S.; Peric, I.

2017-09-01

The concept of capacitive coupling between sensors and readout chips is under study for the vertex detector at the proposed high-energy CLIC electron positron collider. The CLICpix Capacitively Coupled Pixel Detector (C3PD) is an active High-Voltage CMOS sensor, designed to be capacitively coupled to the CLICpix2 readout chip. The chip is implemented in a commercial 180 nm HV-CMOS process and contains a matrix of 128×128 square pixels with 25μm pitch. First prototypes have been produced with a standard resistivity of ~20 Ωcm for the substrate and tested in standalone mode. The results show a rise time of ~20 ns, charge gain of 190 mV/ke- and ~40 e- RMS noise for a power consumption of 4.8μW/pixel. The main design aspects, as well as standalone measurement results, are presented.

Test of a PCIe based readout option for PANDA

Energy Technology Data Exchange (ETDEWEB)

Reiter, Simon; Lange, Soeren; Kuehn, Wolfgang [Justus-Liebig-Universitaet Giessen (Germany); Engel, Heiko [Goethe-Universitaet Frankfurt (Germany); Collaboration: PANDA-Collaboration

2016-07-01

The future PANDA detector will achieve an event rate at about 20 MHz resulting in a high data load of up to 200 GB/s. The data acquisition system will be based on a triggerless readout concept, leading to the requirement of large data bandwidths. The data reduction will be guaranteed on the first level by an array of FPGAs running a full on-line reconstruction followed by the second level of a CPU/GPU cluster to achieve a reduction factor more than 1000. The C-RORC (Common Readout Receiver Card), originally developed for ALICE, provides on the one hand 12 optical links with 6.25 Gbps each, and on the other hand a PCIe interface with up to 40 Gbps. The receiver card has been installed and tested, and the firmware has been adjusted for the Panda data format. Test results are presented.

Design and Measurement of a Low-Noise 64-Channels Front-End Readout ASIC for CdZnTe Detectors

Energy Technology Data Exchange (ETDEWEB)

Gan, Bo; Wei, Tingcun; Gao, Wu; Liu, Hui; Hu, Yann [School of Computer Science and Technology, Northwestern Polytechnical University, Xi' an (China)

2015-07-01

Cadmium zinc telluride (CdZnTe) detectors, as one of the principal detectors for the next-generation X-ray and γ-ray imagers, have high energy resolution and supporting electrode patterning in the radiation environment at room-temperature. In the present, a number of internationally renowned research institutions and universities are actively using these detector systems to carry out researches of energy spectrum analysis, medical imaging, materials characterization, high-energy physics, nuclear plant monitoring, and astrophysics. As the most important part of the readout system for the CdZnTe detector, the front-end readout application specific integrated circuit (ASIC) would have an important impact on the performances of the whole detector system. In order to ensure the small signal to noise ratio (SNR) and sufficient range of the output signal, it is necessary to design a front-end readout ASIC with very low noise and very high dynamic range. In addition, radiation hardness should be considered when the detectors are utilized in the space applications and high energy physics experiments. In this paper, we present measurements and performances of a novel multi-channel radiation-hardness low-noise front-end readout ASIC for CdZnTe detectors. The readout circuits in each channel consist of charge sensitive amplifier, leakage current compensation circuit (LCC), CR-RC shaper, S-K filter, inverse proportional amplifier, peak detect and hold circuit (PDH), discriminator and trigger logic, time sequence control circuit and driving buffer. All of 64 readout channels' outputs enter corresponding inputs of a 64 channel multiplexer. The output of the mux goes directly out of the chip via the output buffer. The 64-channel readout ASIC is implemented using the TSMC 0.35 μm mixed-signal CMOS technology. The die size of the prototype chip is 2.7 mm x 8 mm. At room temperature, the equivalent noise level of a typical channel reaches 66 e{sup -} (rms) at zero farad for a

Perspective: Fabrication of integrated organ-on-a-chip via bioprinting.

Science.gov (United States)

Yang, Qingzhen; Lian, Qin; Xu, Feng

2017-05-01

Organ-on-a-chip has emerged as a powerful platform with widespread applications in biomedical engineering, such as pathology studies and drug screening. However, the fabrication of organ-on-a-chip is still a challenging task due to its complexity. For an integrated organ-on-a-chip, it may contain four key elements, i.e., a microfluidic chip, live cells/microtissues that are cultured in this chip, components for stimulus loading to mature the microtissues, and sensors for results readout. Recently, bioprinting has been used for fabricating organ-on-a-chip as it enables the printing of multiple materials, including biocompatible materials and even live cells in a programmable manner with a high spatial resolution. Besides, all four elements for organ-on-a-chip could be printed in a single continuous procedure on one printer; in other words, the fabrication process is assembly free. In this paper, we discuss the recent advances of organ-on-a-chip fabrication by bioprinting. Light is shed on the printing strategies, materials, and biocompatibility. In addition, some specific bioprinted organs-on-chips are analyzed in detail. Because the bioprinted organ-on-a-chip is still in its early stage, significant efforts are still needed. Thus, the challenges presented together with possible solutions and future trends are also discussed.

Design and Characterization of 64K Pixels Chips Working in Single Photon Processing Mode

CERN Document Server

Llopart Cudie, Xavier; Campbell, M

2007-01-01

Progress in CMOS technology and in fine pitch bump bonding has made possible the development of high granularity single photon counting detectors for X-ray imaging. This thesis studies the design and characterization of three pulse processing chips with 65536 square pixels of 55 µm x 55 µm designed in a commercial 0.25 µm 6-metal CMOS technology. The 3 chips share the same architecture and dimensions and are named Medipix2, Mpix2MXR20 and Timepix. The Medipix2 chip is a pixel detector readout chip consisting of 256 x 256 identical elements, each working in single photon counting mode for positive or negative input charge signals. The preamplifier feedback provides compensation for detector leakage current on a pixel by pixel basis. Two identical pulse height discriminators are used to define an energy window. Every event falling inside the energy window is counted with a 13 bit pseudo-random counter. The counter logic, based in a shift register, also behaves as the input/output register for the pixel. Each...

Performance of an optical readout GEM-based TPC

International Nuclear Information System (INIS)

Margato, L.M.S.; Fraga, F.A.F.; Fetal, S.T.G.; Fraga, M.M.F.R.; Balau, E.F.S.; Blanco, A.; Marques, R. Ferreira; Policarpo, A.J.P.L

2004-01-01

We report on the operation of a GEM-based small TPC using an optical readout. The detector was operated with a mixture of Ar+CF 4 using 5.48 MeV alpha particles obtained from a 241 Am source and the GEM scintillation was concurrently read by a CCD camera and a photomultiplier. Precision collimators were used to define the track orientation. Qualitative results on the accuracy of the track angle, length and charge deposition measurements are presented

Optimized readout configuration for PIXE spectrometers based on Silicon Drift Detectors: Architecture and performance

International Nuclear Information System (INIS)

Alberti, R.; Grassi, N.; Guazzoni, C.; Klatka, T.

2009-01-01

An optimized readout configuration based on a charge preamplifier with pulsed-reset has been designed for Silicon Drift Detectors (SDDs) to be used in Particle Induced X-ray Emission (PIXE) measurements. The customized readout electronics is able to manage the large pulses originated by the protons backscattered from the target material that would otherwise cause significant degradation of X-ray spectra and marked increase in dead time. In this way, the excellent performance of SDDs can be exploited in high-quality proton-induced spectroscopy of low- and medium-energy X-rays. This paper describes the designed readout architecture and the performance characterization carried out in a PIXE setup with MeV proton beams.

Design of a 40-nm CMOS integrated on-chip oscilloscope for 5-50 GHz spin wave characterization

Science.gov (United States)

Egel, Eugen; Csaba, György; Dietz, Andreas; Breitkreutz-von Gamm, Stephan; Russer, Johannes; Russer, Peter; Kreupl, Franz; Becherer, Markus

2018-05-01

Spin wave (SW) devices are receiving growing attention in research as a strong candidate for low power applications in the beyond-CMOS era. All SW applications would require an efficient, low power, on-chip read-out circuitry. Thus, we provide a concept for an on-chip oscilloscope (OCO) allowing parallel detection of the SWs at different frequencies. The readout system is designed in 40-nm CMOS technology and is capable of SW device characterization. First, the SWs are picked up by near field loop antennas, placed below yttrium iron garnet (YIG) film, and amplified by a low noise amplifier (LNA). Second, a mixer down-converts the radio frequency (RF) signal of 5 - 50 GHz to lower intermediate frequencies (IF) around 10 - 50 MHz. Finally, the IF signal can be digitized and analyzed regarding the frequency, amplitude and phase variation of the SWs. The power consumption and chip area of the whole OCO are estimated to 166.4 mW and 1.31 mm2, respectively.

An asynchronous data-driven readout prototype for CEPC vertex detector

Science.gov (United States)

Yang, Ping; Sun, Xiangming; Huang, Guangming; Xiao, Le; Gao, Chaosong; Huang, Xing; Zhou, Wei; Ren, Weiping; Li, Yashu; Liu, Jianchao; You, Bihui; Zhang, Li

2017-12-01

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 μm. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.

A camac based data acquisition system for flat-panel image array readout

International Nuclear Information System (INIS)

Morton, E.J.; Antonuk, L.E.; Berry, J.E.; Huang, W.; Mody, P.; Yorkston, J.; Longo, M.J.

1993-01-01

A readout system has been developed to facilitate the digitization and subsequent display of image data from two-dimensional, pixellated, flat-panel, amorphous silicon imaging arrays. These arrays have been designed specifically for medical x-ray imaging applications. The readout system is based on hardware and software developed for various experiments at CERN and Fermi National Accelerator Laboratory. Additional analog signal processing and digital control electronics were constructed specifically for this application. The authors report on the form of the resulting data acquisition system, discuss aspects of its performance, and consider the compromises which were involved in its design

Development of a small-scale protope of the GOSSIPO-2 chip in 0.13 um CMOS technology

CERN Document Server

Kluit, R; Gromov, V

2007-01-01

The GOSSIP (Gas On Slimmed Silicon Pixel) detector is a proposed alternative for silicon based pixel detectors. The Gossip Prototype (GOSSIPO) chip is being developed to serve as a prototype read-out chip for such a gas-filled detector. Thanks to the very low capacitance at the preamplifier input, the front-end of the chip demonstrates low-noise performance in combination with a fast peaking time and low analog power dissipation. Measurement of the drift time of every primary electron in the gas volume enables 3D reconstruction of the particle tracks. For this purpose a Time-to- Digital converter must be placed in each pixel. A small-scale prototype of the GOSSIP chip has been developed in the 0.13 μm CMOS technology. The prototype includes a 16 by 16 pixel array where each pixel is equipped with a front-end circuit, threshold DAC, and a 4-bit TDC. The chip is available for testing in May 2007 and after initial tests it will be postprocessed to build a prototype detector. This paper describes the detector de...

Enhancements to a Superconducting Quantum Interference Device (SQUID) Multiplexer Readout and Control System

Science.gov (United States)

Forgione, J.; Benford, D. J.; Buchanan, E. D.; Moseley, S. H.; Rebar, J.; Shafer, R. A.

2004-01-01

Far-infrared detector arrays such as the 16x32 superconducting bolometer array for the SAFIRE instrument (flying on the SOFIA airborne observatory) require systems of readout and control electronics to provide translation between a user-driven, digital PC and the cold, analog world of the cryogenic detector. In 2001, the National Institute of Standards and Technology (NIST) developed their Mark III electronics for purposes of control and readout of their 1x32 SQUID Multiplexer chips. We at NASA s Goddard Space Flight Center acquired a Mark 111 system and subsequently designed upgrades to suit our and our collaborators purposes. We developed an arbitrary, programmable multiplexing system that allows the user to cycle through rows in a SQUID array in an infinite number of combinations. We provided hooks in the Mark III system to allow readout of signals from outside the Mark 111 system, such as telescope status information. Finally, we augmented the heart of the system with a new feedback algorithm implementation, flexible diagnostic tools, and informative telemetry.

The ALTRO Chip A 16-channel A/D Converter and Digital Processor for Gas Detectors

CERN Document Server

Esteve-Bosch, R; Mota, B; Musa, L

2003-01-01

The ALTRO (ALICE TPC Read Out) chip is a mixed-signal integrated circuit designed to be one of the building blocks of the readout electronics for gas detectors. Originally conceived and optimised for the Time Projection Chamber (TPC) of the ALICE experiment at the CERN LHC, its architecture and programmability makes it suitable for the readout of a wider class of gas detectors. In one single chip, the analogue signals from 16 channels are digitised, processed, compressed and stored in a multi-acquisition memory. The Analogue-to- Digital converters embedded in the chip have a 10-bit dynamic range and a maximum sampling rate in the range of 20 to 40MHz. After digitisation, a pipelined hardwired Processor is able to remove from the input signal a wide range of systematic and non-systematic perturbations, related to the non-ideal behaviour of the detector, temperature variation of the electronics, environmental noise, etc. Moreover, the Processor is able to suppress the signal tail within 1mus after the pulse pea...

Origami chip-on-sensor design: progress and new developments

International Nuclear Information System (INIS)

Irmler, C; Bergauer, T; Frankenberger, A; Friedl, M; Gfall, I; Valentan, M; Ishikawa, A; Kato, E; Negishi, K; Kameswara, R; Mohanty, G; Onuki, Y; Shimizu, N; Tsuboyama, T

2013-01-01

The Belle II silicon vertex detector will consist of four layers of double-sided silicon strip detectors, arranged in ladders. Each sensor will be read out individually by utilizing the Origami chip-on-sensor concept, where the APV25 chips are placed on flexible circuits, glued on top of the sensors. Beside a best compromise between low material budget and sufficient SNR, this concept allows efficient CO 2 cooling of the readout chips by a single, thin cooling pipe per ladder. Recently, we assembled a module consisting of two consecutive 6'' double-sided silicon strip detectors, both read out by Origami flexes. Such a compound of Origami modules is required for the ladders of the outer Belle II SVD layers. Consequently, it is intended to verify the scalability of the assembly procedure, the performance of combined Origami flexes as well as the efficiency of the CO 2 cooling system for a higher number of APV25 chips.

Time over threshold readout method of SiPM based small animal PET detector

International Nuclear Information System (INIS)

Valastyan, I.; Gal, J.; Hegyesi, G.; Kalinka, G.; Nagy, F.; Kiraly, B.; Imrek, J.; Molnar, J.

2012-01-01

Complete text of publication follows. The aim of the work was to design a readout concept for silicon photomultiplier (SiPM) sensor array used in small animal PET scanner. The detector module consist of LYSO 35x35 scintillation crystals, 324 SiPM sensors (arranged in 2x2 blocks and those quads in a 9x9 configuration) and FPGA based readout electronics. The dimensions of the SiPM matrix are area: 48x48 mm 2 and the size of one SiPM sensor is 1.95x2.2 mm 2 . Due to the high dark current of the SiPM, conventional Anger based readout method does not provide sufficient crystal position maps. Digitizing the 324 SiPM channels is a straightforward way to obtain proper crystal position maps. However handling hundreds of analogue input channels and the required DSP resources cause large racks of data acquisition electronics. Therefore coding of the readout channels is required. Proposed readout method: The coding of the 324 SiPMs consists two steps: Step 1) Reduction of the channels from 324 to 36: Row column readout, SiPMs are connected to each other in column by column and row-by row, thus the required channels are 36. The dark current of 18 connected SiPMs is small in off for identifying pulses coming from scintillating events. Step 2) Reduction of the 18 rows and columns to 4 channels: Comparators were connected to each rows and columns, and the level was set above the level of dark noise. Therefore only few comparators are active when scintillation light enters in the tile. The output of the comparator rows and columns are divided to two parts using resistor chains. Then the outputs of the resistor chains are digitized by a 4 channel ADC. However instead of the Anger method, time over threshold (ToT) was used. Figure 1 shows the readout concept of the SiPM matrix. In order to validate the new method and optimize the front-end electronics of the detector, the analogue signals were digitized before the comparators using a CAEN DT5740 32 channel digitizer, then the

Readout of micromechanical cantilever sensor arrays by Fabry-Perot interferometry

International Nuclear Information System (INIS)

Wehrmeister, Jana; Fuss, Achim; Saurenbach, Frank; Berger, Ruediger; Helm, Mark

2007-01-01

The increasing use of micromechanical cantilevers in sensing applications causes a need for reliable readout techniques of micromechanical cantilever sensor (MCS) bending. Current optical beam deflection techniques suffer from drawbacks such as artifacts due to changes in the refraction index upon exchange of media. Here, an adaptation of the Fabry-Perot interferometer is presented that allows simultaneous determination of MCS bending and changes in the refraction index of media. Calibration of the instrument with liquids of known refraction index provides an avenue to direct measurement of bending with nanometer precision. Versatile construction of flow cells in combination with alignment features for substrate chips allows simultaneous measurement of two MCS situated either on the same, or on two different support chips. The performance of the instrument is demonstrate in several sensing applications, including adsorption experiments of alkanethioles on MCS gold surfaces, and measurement of humidity changes in air

Design of the ANTARES LCM-DAQ board test bench using a FPGA-based system-on-chip approach

Energy Technology Data Exchange (ETDEWEB)

Anvar, S. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France); Kestener, P. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)]. E-mail: pierre.kestener@cea.fr; Le Provost, H. [CEA Saclay, DAPNIA/SEDI, 91191 Gif-sur-Yvette Cedex (France)

2006-11-15

The System-on-Chip (SoC) approach consists in using state-of-the-art FPGA devices with embedded RISC processor cores, high-speed differential LVDS links and ready-to-use multi-gigabit transceivers allowing development of compact systems with substantial number of IO channels. Required performances are obtained through a subtle separation of tasks between closely cooperating programmable hardware logic and user-friendly software environment. We report about our experience in using the SoC approach for designing the production test bench of the off-shore readout system for the ANTARES neutrino experiment.

A free-running, time-based readout method for particle detectors

International Nuclear Information System (INIS)

Goerres, A; Ritman, J; Stockmanns, T; Bugalho, R; Francesco, A Di; Gastón, C; Gonçalves, F; Rolo, M D; Silva, J C da; Silva, R; Varela, J; Veckalns, V; Mazza, G; Mignone, M; Pietro, V Di; Riccardi, A; Rivetti, A; Wheadon, R

2014-01-01

For the EndoTOFPET-US experiment, the TOFPET ASIC has been developed as a front-end chip to read out data from silicon photomultipliers (SiPM) [1]. It introduces a time of flight information into the measurement of a PET scanner and hence reduces radiation exposure of the patient [2]. The chip is designed to work with a high event rate up to 100 kHz and a time resolution of 50 ps LSB. Using two threshold levels, it can measure the leading edge of the event pulse precisely while successfully suppressing dark counts from the SiPM. This also enables a time over threshold determination, leading to a charge measurement of the signal's pulse. The same, time-based concept is chosen for the PASTA chip used in the PANDA experiment. This high-energy particle detector contains sub-systems for specific measurement goals. The innermost of these is the Micro Vertex Detector, a silicon-based tracking system. The PASTA chip's approach is much like the TOFPET ASIC with some differences. The most significant ones are a changed amplifying part for different input signals as well as protection for radiation effects of the high-radiation environment. Apart from that, the simple and general concept combined with a small area and low power consumption support the choice for using this approach

A free-running, time-based readout method for particle detectors

Science.gov (United States)

Goerres, A.; Bugalho, R.; Di Francesco, A.; Gastón, C.; Gonçalves, F.; Mazza, G.; Mignone, M.; Di Pietro, V.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; da Silva, J. C.; Silva, R.; Stockmanns, T.; Varela, J.; Veckalns, V.; Wheadon, R.

2014-03-01

For the EndoTOFPET-US experiment, the TOFPET ASIC has been developed as a front-end chip to read out data from silicon photomultipliers (SiPM) [1]. It introduces a time of flight information into the measurement of a PET scanner and hence reduces radiation exposure of the patient [2]. The chip is designed to work with a high event rate up to 100 kHz and a time resolution of 50 ps LSB. Using two threshold levels, it can measure the leading edge of the event pulse precisely while successfully suppressing dark counts from the SiPM. This also enables a time over threshold determination, leading to a charge measurement of the signal's pulse. The same, time-based concept is chosen for the PASTA chip used in the PANDA experiment. This high-energy particle detector contains sub-systems for specific measurement goals. The innermost of these is the Micro Vertex Detector, a silicon-based tracking system. The PASTA chip's approach is much like the TOFPET ASIC with some differences. The most significant ones are a changed amplifying part for different input signals as well as protection for radiation effects of the high-radiation environment. Apart from that, the simple and general concept combined with a small area and low power consumption support the choice for using this approach.

Reliable and redundant FPGA based read-out design in the ATLAS TileCal Demonstrator

CERN Document Server

Åkerstedt, Henrik; The ATLAS collaboration; Drake, Gary; Anderson, Kelby; Bohm, Christian; Oreglia, Mark; Tang, Fukun

2015-01-01

The Tile Calorimeter at ATLAS is a hadron calorimeter based on steel plates and scintillating tiles read out by PMTs. The current read-out system uses standard ADCs and custom ASICs to digitize and temporarily store the data on the detector. However, only a subset of the data is actually read out to the counting room. The on-detector electronics will be replaced around 2023. To achieve the required reliability the upgraded system will be highly redundant. Here the ASICs will be replaced with Kintex-7 FPGAs from Xilinx. This, in addition to the use of multiple 10 Gbps optical read-out links, will allow a full read-out of all detector data. Due to the higher radiation levels expected when the beam luminosity is increased, opportunities for repairs will be less frequent. The circuitry and firmware must therefore be designed for sufficiently high reliability using redundancy and radiation tolerant components. Within a year, a hybrid demonstrator including the new read-out system will be installed in one slice of ...

Characterization of the column-based priority logic readout of Topmetal-II− CMOS pixel direct charge sensor

International Nuclear Information System (INIS)

An, M.; Zhang, W.; Xiao, L.; Gao, C.; Chen, C.; Huang, G.; Ji, R.; Liu, J.; Pei, H.; Sun, X.; Wang, K.; Yang, P.; Zhou, W.; Han, M.; Mei, Y.; Li, X.; Sun, Q.

2017-01-01

We present the detailed study of the digital readout of Topmetal-II - CMOS pixel direct charge sensor. Topmetal-II - is an integrated sensor with an array of 72×72 pixels each capable of directly collecting external charge through exposed metal electrodes in the topmost metal layer. In addition to the time-shared multiplexing readout of the analog output from Charge Sensitive Amplifiers in each pixel, hits are also generated through comparators in each pixel with individually adjustable thresholds. The hits are read out via a column-based priority logic structure, retaining both hit location and time information. The in-array column-based priority logic features with a full clock-less circuitry hence there is no continuously running clock distributed in the pixel and matrix logic. These characteristics enable its use as the charge readout device in future Time Projection Chambers without gaseous gain mechanism, which has unique advantages in low background and low rate-density experiments. We studied the detailed working behavior and performance of this readout, and demonstrated its functional validity and potential in imaging applications.

The Design of High Performance, Low Power Triple-Track Magnetic Sensor Chip

Directory of Open Access Journals (Sweden)

Junning Chen

2013-07-01

Full Text Available This paper presents a design of a high performance and low power consumption triple-track magnetic sensor chip which was fabricated in TSMC 0.35 μm CMOS process. This chip is able to simultaneously sense, decode and read out the information stored in triple-track magnetic cards. A reference voltage generating circuit, a low-cost filter circuit, a power-on reset circuit, an RC oscillator, and a pre-decoding circuit are utilized as the basic modules. The triple-track magnetic sensor chip has four states, i.e., reset, sleep, swiping card and data read-out. In sleep state, the internal RC oscillator is closed, which means that the digital part does not operate to optimize energy consumption. In order to improve decoding accuracy and expand the sensing range of the signal, two kinds of circuit are put forward, naming offset correction circuit, and tracking circuit. With these two circuits, the sensing function of this chip can be more efficiently and accurately. We simulated these circuit modules with TSMC technology library. The results showed that these modules worked well within wide range input signal. Based on these results, the layout and tape-out were carried out. The measurement results showed that the chip do function well within a wide swipe speed range, which achieved the design target.

Test of the CMS microstrip silicon tracker readout and control system

CERN Document Server

Zghiche, A

2001-01-01

The Microstrip Silicon tracker of the CMS detector is designed to provide robust particle tracking and vertex reconstruction within a strong magnetic field in the high luminosity environment of the LHC. The Tracker readout system employs Front-End Driver cards to digitize and buffer the analogue data arriving via optical links from on detector pipeline chips. The control chain of the front-end electronic is built to operate via optical fibers in order to shield the communications from the outside noise. Components close to the final design have been assembled to be tested in the X5 beam area at CERN where a dedicated 25 ns temporal structure beam has been made available by the SPS. This paper describes the hardware and the software developed for readout and control of data acquired by the front-end electronics operating at 40 MHz, Some preliminary results of the tests performed in the 25 ns beam are also given. (8 refs).

Power distribution and substrate noise coupling investigations on the behavioral level for photon counting imaging readout circuits

International Nuclear Information System (INIS)

Lundgren, Jan; Abdalla, Suliman; O'Nils, Mattias; Oelmann, Bengt

2007-01-01

In modern mixed-signal system design, there are increasing problems associated with noise coupling caused by switching digital parts to sensitive analog parts. As a consequence, there is a growing necessity to understand these problems. In order to avoid costly design iterations, noise coupling simulations should be initiated as early as possible in the design chain. The problems associated with on-chip noise coupling have been discovered in photon counting pixel detector readout systems, where the level of integration of analog and digital circuits is very high on a very small area, and it would appear that these problems will continue to increase for future system designs in this field. This paper deals with the functionality of utilizing behavioral level models for simulating noise coupling in these readout systems. The methods and models are described and simulation results are shown for a photon counting pixel detector readout system

A Reconfigurable Readout Integrated Circuit for Heterogeneous Display-Based Multi-Sensor Systems

Directory of Open Access Journals (Sweden)

Kyeonghwan Park

2017-04-01

Full Text Available This paper presents a reconfigurable multi-sensor interface and its readout integrated circuit (ROIC for display-based multi-sensor systems, which builds up multi-sensor functions by utilizing touch screen panels. In addition to inherent touch detection, physiological and environmental sensor interfaces are incorporated. The reconfigurable feature is effectively implemented by proposing two basis readout topologies of amplifier-based and oscillator-based circuits. For noise-immune design against various noises from inherent human-touch operations, an alternate-sampling error-correction scheme is proposed and integrated inside the ROIC, achieving a 12-bit resolution of successive approximation register (SAR of analog-to-digital conversion without additional calibrations. A ROIC prototype that includes the whole proposed functions and data converters was fabricated in a 0.18 μm complementary metal oxide semiconductor (CMOS process, and its feasibility was experimentally verified to support multiple heterogeneous sensing functions of touch, electrocardiogram, body impedance, and environmental sensors.

The CMS silicon strip tracker and its electronic readout

International Nuclear Information System (INIS)

Friedl, M.

2001-05-01

The Large Hadron Collider (LHC) at CERN (Geneva, CH) will be the world's biggest accelerator machine when operation starts in 2006. One of its four detector experiments is the Compact Muon Solenoid (CMS), consisting of a large-scale silicon tracker and electromagnetic and hadron calorimeters, all embedded in a solenoidal magnetic field of 4 T, and a muon system surrounding the magnet coil. The Silicon Strip Tracker has a sensitive area of 206m 2 with 10 million analog channels which are read out at the collider frequency of 40 MHz. The building blocks of the CMS Tracker are the silicon sensors, APV amplifier ASICs, supporting front-end ASICs, analog and digital optical links as well as data processors and control units in the back-end. Radiation tolerance, readout speed and the huge data volume are challenging requirements. The charge collection in silicon detectors was modeled, which is discussed as well as the concepts of readout amplifiers with respect to the LHC requirements, including the deconvolution method of fast pulse shaping, electronic noise constraints and radiation effects. Moreover, extensive measurements on prototype components of the CMS Tracker and different versions of the APV chip in particular were performed. There was a significant contribution to the construction of several detector modules, characterized them in particle beam tests and quantified radiation induced effects on the APV chip and on silicon detectors. In addition, a prototype of the analog optical link and the analog performance of the back-end digitization unit were evaluated. The results are very encouraging, demonstrating the feasibility of the CMS Silicon Strip Tracker system and motivating progress towards the construction phase. (author)

Performance study of large area encoding readout MRPC

Science.gov (United States)

Chen, X. L.; Wang, Y.; Chen, G.; Han, D.; Wang, X.; Zeng, M.; Zeng, Z.; Zhao, Z.; Guo, B.

2018-02-01

Muon tomography system built by the 2-D readout high spatial resolution Multi-gap Resistive Plate Chamber (MRPC) detector is a project of Tsinghua University. An encoding readout method based on the fine-fine configuration has been used to minimize the number of the readout electronic channels resulting in reducing the complexity and the cost of the system. In this paper, we provide a systematic comparison of the MRPC detector performance with and without fine-fine encoding readout. Our results suggest that the application of the fine-fine encoding readout leads us to achieve a detecting system with slightly worse spatial resolution but dramatically reduce the number of electronic channels.

Opto-electronic DNA chip-based integrated card for clinical diagnostics.

Science.gov (United States)

Marchand, Gilles; Broyer, Patrick; Lanet, Véronique; Delattre, Cyril; Foucault, Frédéric; Menou, Lionel; Calvas, Bernard; Roller, Denis; Ginot, Frédéric; Campagnolo, Raymond; Mallard, Frédéric

2008-02-01

Clinical diagnostics is one of the most promising applications for microfluidic lab-on-a-chip or lab-on-card systems. DNA chips, which provide multiparametric data, are privileged tools for genomic analysis. However, automation of molecular biology protocol and use of these DNA chips in fully integrated systems remains a great challenge. Simplicity of chip and/or card/instrument interfaces is amongst the most critical issues to be addressed. Indeed, current detection systems for DNA chip reading are often complex, expensive, bulky and even limited in terms of sensitivity or accuracy. Furthermore, for liquid handling in the lab-on-cards, many devices use complex and bulky systems, either to directly manipulate fluids, or to ensure pneumatic or mechanical control of integrated valves. All these drawbacks prevent or limit the use of DNA-chip-based integrated systems, for point-of-care testing or as a routine diagnostics tool. We present here a DNA-chip-based protocol integration on a plastic card for clinical diagnostics applications including: (1) an opto-electronic DNA-chip, (2) fluid handling using electrically activated embedded pyrotechnic microvalves with closing/opening functions. We demonstrate both fluidic and electric packaging of the optoelectronic DNA chip without major alteration of its electronical and biological functionalities, and fluid control using novel electrically activable pyrotechnic microvalves. Finally, we suggest a complete design of a card dedicated to automation of a complex biological protocol with a fully electrical fluid handling and DNA chip reading.

Evaluation of local radiation damage in silicon sensor via charge collection mapping with the Timepix read-out chip

International Nuclear Information System (INIS)

Platkevic, M; Jakubek, J; Jakubek, M; Pospisil, S; Zemlicka, J; Havranek, V; Semian, V

2013-01-01

Studies of radiation hardness of silicon sensors are standardly performed with single-pad detectors evaluating their global electrical properties. In this work we introduce a technique to visualize and determine the spatial distribution of radiation damage across the area of a semiconductor sensor. The sensor properties such as charge collection efficiency and charge diffusion were evaluated locally at many points of the sensor creating 2D maps. For this purpose we used a silicon sensor bump bonded to the pixelated Timepix read-out chip. This device, operated in Time-over-threshold (TOT) mode, allows for the direct energy measurement in each pixel. Selected regions of the sensor were intentionally damaged by defined doses (up to 10 12 particles/cm 2 ) of energetic protons (of 2.5 and 4 MeV). The extent of the damage was measured in terms of the detector response to the same ions. This procedure was performed either on-line during irradiation or off-line after it. The response of the detector to each single particle was analyzed determining the charge collection efficiency and lateral charge diffusion. We evaluated the changes of these parameters as a function of radiation dose. These features are related to the local properties such as the spatial homogeneity of the sensor. The effect of radiation damage was also independently investigated measuring local changes of signal response to γ, and X rays and alpha particles.

ADVANCED READOUT ELECTRONICS FOR MULTIELEMENT CdZnTe SENSORS

International Nuclear Information System (INIS)

DE GERONIMO, G.; O CONNOR, P.; KANDASAMY, A.; GROSHOLZ, J.

2002-01-01

A generation of high performance front-end and read-out ASICs customized for highly segmented CdZnTe sensors is presented. The ASICs, developed in a multi-year effort at Brookhaven National Laboratory, are targeted to a wide range of applications including medical, safeguards/security, industrial, research, and spectroscopy. The front-end multichannel ASICs provide high accuracy low noise preamplification and filtering of signals, with versions for small and large area CdZnTe elements. They implement a high order unipolar or bipolar shaper, an innovative low noise continuous reset system with self-adapting capability to the wide range of detector leakage currents, a new system for stabilizing the output baseline and high output driving capability. The general-purpose versions include programmable gain and peaking time. The read-out multichannel ASICs provide fully data driven high accuracy amplitude and time measurements, multiplexing and time domain derandomization of the shaped pulses. They implement a fast arbitration scheme and an array of innovative two-phase offset-free rail-to-rail analog peak detectors for buffering and absorption of input rate fluctuations, thus greatly relaxing the rate requirement on the external ADC. Pulse amplitude, hit timing, pulse risetime, and channel address per processed pulse are available at the output in correspondence of an external readout request. Prototype chips have been fabricated in 0.5 and 0.35 (micro)m CMOS and tested. Design concepts and experimental results are discussed

An FPGA-based Sampling-ADC readout for the crystal barrel calorimeter

Energy Technology Data Exchange (ETDEWEB)

Muellers, Johannes [Helmholtz-Institut fuer Strahlen- und Kernphysik, Bonn (Germany); Marciniewski, Pawel [Angstroemlaboratoriet, Uppsala (Sweden); Collaboration: CBELSA/TAPS-Collaboration

2016-07-01

The CBELSA/TAPS experiment at the electron accelerator ELSA (Bonn) investigates the photoproduction of mesons off protons and neutrons. The Crystal Barrel Calorimeter has been upgraded replacing its photodiode readout by APDs, which allows the integration of the calorimeter into the first level trigger. Since the possible DAQ rate is currently limited by the digitization stage (LeCroy QDC1885F) to ∼ 2 kHz, the implementation of a new Sampling-ADC (SADC) readout is the second important step in the upgrade of the detector system. Based on the 64-channel PANDA-SADC, the design was modified, adapting it to the needs of the CBELSA/TAPS experiment. The CB-SADC offers 64 channels in one NIM module with up to 14 bit rate at 125 MHz, accompanied by a modular analog input stage and power supply. Data processing and reduction are realized with Kintex7 FPGAs. Readout is possible via gigabit ethernet links. Using an FPGA provides a multitude of possibilities for online feature extraction, such as the determination of the energy deposited in the crystal, TDC capabilities and pile-up detection and recovery. The SADC development is discussed, and first measurements performed in comparison to the presently used LeCroy QDC are presented.

A 10 MHz micropower CMOS front end for direct readout of pixel detectors

International Nuclear Information System (INIS)

Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

1990-01-01

In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

The SVX3D integrated circuit for dead-timeless silicon strip readout

Energy Technology Data Exchange (ETDEWEB)

Garcia-Sciveres, M. E-mail: mgs@lbl.gov; Milgrome, O.; Zimmerman, T.; Volobouev, I.; Ely, R.P.; Connolly, A.; Fish, D.; Affolder, T.; Sill, A

1999-10-01

The revision D of the SVX3 readout IC has been fabricated in the Honeywell radiation-hard 0.8 {mu}m bulk CMOS process, for instrumenting 712,704 silicon strips in the upgrade to the Collider Detector at Fermilab. This final revision incorporates new features and changes to the original architecture that were added to meet the goal of dead-timeless operation. This paper describes the features central to dead-timeless operation, and presents test data for un-irradiated and irradiated SVX3D chips. (author)

Flip-chip bonded optoelectronic integration based on ultrathin silicon (UTSi) CMOS

Science.gov (United States)

Hong, Sunkwang; Ho, Tawei; Zhang, Liping; Sawchuk, Alexander A.

2003-06-01

We describe the design and test of flip-chip bonded optoelectronic CMOS devices based on Peregrine Semiconductor's 0.5 micron Ultra-Thin Silicon on sapphire (UTSi) technology. The UTSi process eliminates the substrate leakage that typically results in crosstalk and reduces parasitic capacitance to the substrate, providing many benefits compared to bulk silicon CMOS. The low-loss synthetic sapphire substrate is optically transparent and has a coefficient of thermal expansion suitable for flip-chip bonding of vertical cavity surface emitting lasers (VCSELs) and detectors. We have designed two different UTSi CMOS chips. One contains a flip-chip bonded 1 x 4 photodiode array, a receiver array, a double edge triggered D-flip flop-based 2047-pattern pseudo random bit stream (PRBS) generator and a quadrature-phase LC-voltage controlled oscillator (VCO). The other chip contains a flip-chip bonded 1 x 4 VCSEL array, a driver array based on high-speed low-voltage differential signals (LVDS) and a full-balanced differential LC-VCO. Each VCSEL driver and receiver has individual input and bias voltage adjustments. Each UTSi chip is mounted on different printed circuit boards (PCBs) which have holes with about 1 mm radius for optical output and input paths through the sapphire substrate. We discuss preliminary testing of these chips.

A Low-Power Integrated Humidity CMOS Sensor by Printing-on-Chip Technology

Directory of Open Access Journals (Sweden)

Chang-Hung Lee

2014-05-01

Full Text Available A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

A low-power integrated humidity CMOS sensor by printing-on-chip technology.

Science.gov (United States)

Lee, Chang-Hung; Chuang, Wen-Yu; Cowan, Melissa A; Wu, Wen-Jung; Lin, Chih-Ting

2014-05-23

A low-power, wide-dynamic-range integrated humidity sensing chip is implemented using a printable polymer sensing material with an on-chip pulse-width-modulation interface circuit. By using the inkjet printing technique, poly(3,4-ethylene-dioxythiophene)/polystyrene sulfonate that has humidity sensing features can be printed onto the top metal layer of a 0.35 μm CMOS IC. The developed printing-on-chip humidity sensor achieves a heterogeneous three dimensional sensor system-on-chip architecture. The humidity sensing of the implemented printing-on-chip sensor system is experimentally tested. The sensor shows a sensitivity of 0.98% to humidity in the atmosphere. The maximum dynamic range of the readout circuit is 9.8 MΩ, which can be further tuned by the frequency of input signal to fit the requirement of the resistance of printed sensor. The power consumption keeps only 154 μW. This printing-on-chip sensor provides a practical solution to fulfill an ultra-small integrated sensor for the applications in miniaturized sensing systems.

Highly efficient router-based readout algorithm for single-photon-avalanche-diode imagers for time-correlated experiments

Science.gov (United States)

Cominelli, A.; Acconcia, G.; Caldi, F.; Peronio, P.; Ghioni, M.; Rech, I.

2018-02-01

Time-Correlated Single Photon Counting (TCSPC) is a powerful tool that permits to record extremely fast optical signals with a precision down to few picoseconds. On the other hand, it is recognized as a relatively slow technique, especially when a large time-resolved image is acquired exploiting a single acquisition channel and a scanning system. During the last years, much effort has been made towards the parallelization of many acquisition and conversion chains. In particular, the exploitation of Single-Photon Avalanche Diodes in standard CMOS technology has paved the way to the integration of thousands of independent channels on the same chip. Unfortunately, the presence of a large number of detectors can give rise to a huge rate of events, which can easily lead to the saturation of the transfer rate toward the elaboration unit. As a result, a smart readout approach is needed to guarantee an efficient exploitation of the limited transfer bandwidth. We recently introduced a novel readout architecture, aimed at maximizing the counting efficiency of the system in typical TCSPC measurements. It features a limited number of high-performance converters, which are shared with a much larger array, while a smart routing logic provides a dynamic multiplexing between the two parts. Here we propose a novel routing algorithm, which exploits standard digital gates distributed among a large 32x32 array to ensure a dynamic connection between detectors and external time-measurement circuits.

Prototype detection unit for the CHIPS experiment

Science.gov (United States)

Pfützner, Maciej M.

2017-09-01

CHIPS (CHerenkov detectors In mine PitS) is an R&D project aiming to develop novel cost-effective neutrino detectors, focused on measuring the CP-violating neutrino mixing phase (δ CP). A single detector module, containing an enclosed volume of purified water, would be submerged in an existing lake, located in a neutrino beam. A staged approach is proposed with first detectors deployed in a flooded mine pit in Northern Minnesota, 7 mrad off-axis from the existing NuMI beam. A small proof-of-principle model (CHIPS-M) has already been tested and the first stage of a fully functional 10 kt module (CHIPS-10) is planned for 2018. One of the instruments submerged on board of CHIPS-M in autumn 2015 was a prototype detection unit, constructed at Nikhef. The unit contains hardware borrowed from the KM3NeT experiment, including 16 3 inch photomultiplier tubes and readout electronics. In addition to testing the mechanical design and data acquisition, the detector was used to record a large sample of cosmic ray muon events. The collected data is valuable for characterising the cosmic muon background and validating a Monte Carlo simulation used to optimise future designs. This paper introduces the CHIPS project, describes the design of the prototype unit, and presents the results of a preliminary data analysis.

Development of a cylindrical tracking detector with multichannel scintillation fibers and pixelated photon detector readout

Energy Technology Data Exchange (ETDEWEB)

Akazawa, Y.; Miwa, K.; Honda, R.; Shiozaki, T.; Chiga, N.

2015-07-01

We are developing a cylindrical tracking detector for a Σp scattering experiment in J-PARC with scintillation fibers and the Pixelated Photon Detector (PPD) readout, which is called as cylindrical fiber tracker (CFT), in order to reconstruct trajectories of charged particles emitted inside CFT. CFT works not only as a tracking detector but also a particle identification detector from energy deposits. A prototype CFT consisting of two straight layers and one spiral layer was constructed. About 1100 scintillation fibers with a diameter of 0.75 mm (Kuraray SCSF-78 M) were used. Each fiber signal was read by Multi-Pixel Photon Counter (MPPC, HPK S10362-11-050P, 1×1 mm{sup 2}, 400 pixels) fiber by fiber. MPPCs were handled with Extended Analogue Silicon Photomultipliers Integrated ReadOut Chip (EASIROC) boards, which were developed for the readout of a large number of MPPCs. The energy resolution of one layer was 28% for a 70 MeV proton where the energy deposit in fibers was 0.7 MeV.

CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

CERN Document Server

Prydderch, Mark Lyndon; Bell, Stephen Jean-marc; Key-Charriere, M; Jones, Lawrence; Auzinger, Georg; Borg, Johan; Hall, Geoffrey; Pesaresi, Mark Franco; Raymond, David Mark; Uchida, Kirika; Goldstein, Joel; Seif El Nasr, Sarah

2018-01-01

The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips. On-chip logic identifies first level trigger primitives from high transverse-momentum tracks by selecting correlated hits in the two sensors. Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing. Results and performance are reported.

Manipulating Neutral Atoms in Chip-Based Magnetic Traps

Science.gov (United States)

Aveline, David; Thompson, Robert; Lundblad, Nathan; Maleki, Lute; Yu, Nan; Kohel, James

2009-01-01

Several techniques for manipulating neutral atoms (more precisely, ultracold clouds of neutral atoms) in chip-based magnetic traps and atomic waveguides have been demonstrated. Such traps and waveguides are promising components of future quantum sensors that would offer sensitivities much greater than those of conventional sensors. Potential applications include gyroscopy and basic research in physical phenomena that involve gravitational and/or electromagnetic fields. The developed techniques make it possible to control atoms with greater versatility and dexterity than were previously possible and, hence, can be expected to contribute to the value of chip-based magnetic traps and atomic waveguides. The basic principle of these techniques is to control gradient magnetic fields with suitable timing so as to alter a trap to exert position-, velocity-, and/or time-dependent forces on atoms in the trap to obtain desired effects. The trap magnetic fields are generated by controlled electric currents flowing in both macroscopic off-chip electromagnet coils and microscopic wires on the surface of the chip. The methods are best explained in terms of examples. Rather than simply allowing atoms to expand freely into an atomic waveguide, one can give them a controllable push by switching on an externally generated or a chip-based gradient magnetic field. This push can increase the speed of the atoms, typically from about 5 to about 20 cm/s. Applying a non-linear magnetic-field gradient exerts different forces on atoms in different positions a phenomenon that one can exploit by introducing a delay between releasing atoms into the waveguide and turning on the magnetic field.

PADI ASIC for straw tube read-out

Energy Technology Data Exchange (ETDEWEB)

Pietraszko, Jerzy; Traeger, Michael; Fruehauf, Jochen; Schmidt, Christian [GSI, Darmstadt (Germany); Ciobanu, Mircea [ISS, Bucharest (Romania); Collaboration: CBM-Collaboration

2016-07-01

A prototype of the CBM MUCH straw tube detector consisting of six individual straws of 6mm inner diameter and 220 mm length filled with Ar/CO{sub 2} gas mixture has been tested at the COSY accelerator in Juelich. The straw tubes were connected to the FEET-PADI6-HDa PCB equipped with PADI-6 fast amplifier/discriminator ASIC. As a reference counter in this measurement the scCVD diamond detector has been used delivering excellent timing, time resolution below 100 ps (sigma), and very precise position information, below 50 μm. The demonstrated position resolution of about 160 μm of the straw tube read out with PADI-6 ASIC confirms the capability of the PADI chip and puts this development as a very attractive readout option for straw tubes and wire chambers.

Measurement of extremely low level dose with LiF(Mg,Cu,P) TL chips

International Nuclear Information System (INIS)

Zha Ziying; Wang Shoushan; Wu Fang; Chen Guolong; Li Yuanfang; Zhu Jianhuan

1986-01-01

This paper presents some of the dosimetric characteristics of newly developed LiF(Mg,Cu,P) TL chips with high signal-to-noise ratio for measurement at the 10 -7 to 10 -4 Gy dose level. Measuring techniques and optimum procedures for annealing and readout are also presented. (author)

The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

CERN Document Server

Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

2013-01-01

The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

International Nuclear Information System (INIS)

Heuvelmans, S; Boerrigter, M

2011-01-01

Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

A pixel read-out architecture implementing a two-stage token ring, zero suppression and compression

Energy Technology Data Exchange (ETDEWEB)

Heuvelmans, S; Boerrigter, M, E-mail: sander.heuvelmans@bruco.nl [Bruco integrated circuits BV, Oostermaat 2, 7623 CS (Netherlands)

2011-01-15

Increasing luminosity in high energy physics experiments leads to new challenges in the design of data acquisition systems for pixel detectors. With the upgrade of the LHCb experiment, the data processing will be changed; hit data from every collision will be transported off the pixel chip, without any trigger selection. A read-out architecture is proposed which is able to obtain low hit data loss on limited silicon area by using the logic beneath the pixels as a data buffer. Zero suppression and redundancy reduction ensure that the data rate off chip is minimized. A C++ model has been created for simulation of functionality and data loss, and for system development. A VHDL implementation has been derived from this model.

On-Chip Microwave Quantum Hall Circulator

Directory of Open Access Journals (Sweden)

A. C. Mahoney

2017-01-01

Full Text Available Circulators are nonreciprocal circuit elements that are integral to technologies including radar systems, microwave communication transceivers, and the readout of quantum information devices. Their nonreciprocity arises from the interference of microwaves over the centimeter scale of the signal wavelength, in the presence of bulky magnetic media that breaks time-reversal symmetry. Here, we realize a completely passive on-chip microwave circulator with size 1/1000th the wavelength by exploiting the chiral, “slow-light” response of a two-dimensional electron gas in the quantum Hall regime. For an integrated GaAs device with 330  μm diameter and about 1-GHz center frequency, a nonreciprocity of 25 dB is observed over a 50-MHz bandwidth. Furthermore, the nonreciprocity can be dynamically tuned by varying the voltage at the port, an aspect that may enable reconfigurable passive routing of microwave signals on chip.

Solid state silicon based condenser microphone for hearing aid, has transducer chip and IC chip between intermediate chip and openings on both sides of intermediate chip, to allow sound towards diaphragm

DEFF Research Database (Denmark)

2000-01-01

towards diaphragm. Surface of the chip (2) has electrical conductors (14) to connect chip with IC chip (3). USE - For use in miniature electroacoustic devices such as hearing aid. ADVANTAGE - Since sound inlet is covered by filter, dust, moisture and other impurities do not obstruct interior and sound...... inlet of microphone. External electrical connection can be made economically reliable and the thermal stress is avoided with the small size solid state silicon based condenser microphone....

Integrated potentiometric detector for use in chip-based flow cells

Science.gov (United States)

Tantra; Manz

2000-07-01

A new kind of potentiometric chip sensor for ion-selective electrodes (ISE) based on a solvent polymeric membrane is described. The chip sensor is designed to trap the organic cocktail inside the chip and to permit sample solution to flow past the membrane. The design allows the sensor to overcome technical problems of ruggedness and would therefore be ideal for industrial processes. The sensor performance for a Ba2+-ISE membrane based on a Vogtle ionophore showed electrochemical behavior similar to that observed in conventional electrodes and microelectrode arrangements.

FASTBUS readout system for the CDF DAQ upgrade

International Nuclear Information System (INIS)

Andresen, J.; Areti, H.; Black, D.

1993-11-01

The Data Acquisition System (DAQ) at the Collider Detector at Fermilab is currently being upgraded to handle a minimum of 100 events/sec for an aggregate bandwidth that is at least 25 Mbytes/sec. The DAQ System is based on a commercial switching network that has interfaces to VME bus. The modules that readout the front end crates (FASTBUS and RABBIT) have to deliver the data to the VME bus based host adapters of the switch. This paper describes a readout system that has the required bandwidth while keeping the experiment dead time due to the readout to a minimum

A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

Science.gov (United States)

Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

2010-12-01

We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64×64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

Energy Technology Data Exchange (ETDEWEB)

Schanz, T., E-mail: schanz@astro.uni-tuebingen.d [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany); Tenzer, C., E-mail: tenzer@astro.uni-tuebingen.d [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany); Maier, D.; Kendziorra, E.; Santangelo, A. [Kepler Center for Astro- and Particlephysics, Institut fuer Astronomie und Astrophysik Tuebingen, Sand 1, 72076 Tuebingen (Germany)

2010-12-11

We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64x64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

A fast one-chip event-preprocessor and sequencer for the Simbol-X Low Energy Detector

International Nuclear Information System (INIS)

Schanz, T.; Tenzer, C.; Maier, D.; Kendziorra, E.; Santangelo, A.

2010-01-01

We present an FPGA-based digital camera electronics consisting of an Event-Preprocessor (EPP) for on-board data preprocessing and a related Sequencer (SEQ) to generate the necessary signals to control the readout of the detector. The device has been originally designed for the Simbol-X low energy detector (LED). The EPP operates on 64x64 pixel images and has a real-time processing capability of more than 8000 frames per second. The already working releases of the EPP and the SEQ are now combined into one Digital-Camera-Controller-Chip (D3C).

Characterization of a DAQ system for the readout of a SiPM based shashlik calorimeter

International Nuclear Information System (INIS)

Berra, A.; Bonvicini, V.; Bosisio, L.; Lietti, D.; Penzo, A.; Prest, M.; Rabaioli, S.; Rashevskaya, I.; Vallazza, E.

2014-01-01

Silicon PhotoMultipliers (SiPMs) are a recently developed type of silicon photodetector characterized by high gain and insensitivity to magnetic fields, which make them a suitable detector for the next generation high energy and space physics experiments. This paper presents the performance of a readout system for SiPMs based on the MAROC3 ASIC. The ASIC consists of 64 channels working in parallel, each one with a variable gain pre-amplifier, a tunable slow shaper with a sample and hold circuit for the analog readout and a tunable fast shaper for the digital one. In the tests described in this paper, only the analog part of the ASIC has been used. A frontend board based on the MAROC3 ASIC has been tested at CERN coupled to a scintillator-lead shashlik calorimeter, readout with 36 large area SiPMs. The performance of the system has been characterized in terms of linearity and energy resolution on the CERN PS-T9 and SPS-H2 beamlines, using different configurations of the ASIC parameters

High-Tc dc-SQUID gradiometers in flip-chip configuration

International Nuclear Information System (INIS)

Peiselt, K; Schmidl, F; Linzen, S; Anton, A S; Huebner, U; Seidel, P

2003-01-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-T c superconductor YBa 2 Cu 3 O 7-x (YBCO). For the flip-chip antenna, a 40 mm x 10 mm SrTiO 3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm x 10 mm SrTiO 3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm -1 Hz -1/2 in the white noise region and of 310 fT cm -1 Hz -1/2 at 1 Hz in the unshielded laboratory environment

High-Tc dc-SQUID gradiometers in flip-chip configuration

Science.gov (United States)

Peiselt, K.; Schmidl, F.; Linzen, S.; Anton, A. S.; Hübner, U.; Seidel, P.

2003-12-01

We describe a new design of a gradiometric flip-chip antenna, which is inductively coupled to a dc-SQUID gradiometer. Both components are patterned out of thin films of the high-Tc superconductor YBa2Cu3O7-x (YBCO). For the flip-chip antenna, a 40 mm × 10 mm SrTiO3 single crystalline substrate is used, while the gradiometer sensors are prepared on 10 mm × 10 mm SrTiO3 bicrystal substrates. Special attention is paid to the inductive coupling between the flip-chip antenna and the read-out gradiometer antenna. We investigate different designs of coupling loops in order to optimize the coupling inductance between both components of the sensor. With optimized coupling the sensor achieves a field-gradient resolution of 12 fT cm-1 Hz-1/2 in the white noise region and of 310 fT cm-1 Hz-1/2 at 1 Hz in the unshielded laboratory environment.

SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

International Nuclear Information System (INIS)

Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

2013-06-01

In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

Pixel detector readout electronics with two-level discriminator scheme

International Nuclear Information System (INIS)

Pengg, F.

1998-01-01

In preparation for a silicon pixel detector with more than 3,000 readout channels per chip for operation at the future large hadron collider (LHC) at CERN the analog front end of the readout electronics has been designed and measured on several test-arrays with 16 by 4 cells. They are implemented in the HP 0.8 microm process but compatible with the design rules of the radiation hard Honeywell 0.8 microm bulk process. Each cell contains bump bonding pad, preamplifier, discriminator and control logic for masking and testing within a layout area of only 50 microm by 140 microm. A new two-level discriminator scheme has been implemented to cope with the problems of time-walk and interpixel cross-coupling. The measured gain of the preamplifier is 900 mV for a minimum ionizing particle (MIP, about 24,000 e - for a 300 microm thick Si-detector) with a return to baseline within 750 ns for a 1 MIP input signal. The full readout chain (without detector) shows an equivalent noise charge to 60e - r.m.s. The time-walk, a function of the separation between the two threshold levels, is measured to be 22 ns at a separation of 1,500 e - , which is adequate for the 40 MHz beam-crossing frequency at the LHC. The interpixel cross-coupling, measured with a 40fF coupling capacitance, is less than 3%. A single cell consumes 35 microW at 3.5 V supply voltage

FASTBUS Readout Controller card for high speed data acquisition

International Nuclear Information System (INIS)

Zimmermann, S.

1991-10-01

This article describes a FASTBUS Readout Controller (FRC) for high speed data acquisition in FASTBUS based systems. The controller has two main interfaces: to FASTBUS and to a Readout Port. The FASTBUS interface performs FASTBUS master and slave operations at a maximum transfer rate exceeding 40 MBytes/s. The Readout Port can be adapted for a variety of protocols. Currently, it will be interfaced to a VME bus based processor with a VSB port. The on-board LR33000 embedded processor controls the readout, executing a list of operations download into its memory. It scans the FASTBUS modules and stores the data in a triple port DRAM (TPDRAM), through one of the Serial Access Memory (SAM) ports of the (TPDRAM). Later, it transfers this data to the readout port using the other SAM. The FRC also supports serial communication via RS232 and Ethernet interfaces. This device is intended for use in the data acquisition system at the Collider Detector at Fermilab. 5 refs., 3 figs

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology

Directory of Open Access Journals (Sweden)

Preethi Padmanabhan

2018-02-01

Full Text Available Gallium nitride (GaN and its alloys are becoming preferred materials for ultraviolet (UV detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs, implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology.

Science.gov (United States)

Padmanabhan, Preethi; Hancock, Bruce; Nikzad, Shouleh; Bell, L Douglas; Kroep, Kees; Charbon, Edoardo

2018-02-03

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e - , obtaining avalanche gains up to 10³. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology.

Toward a reduced-wire readout system for ultrasound imaging.

Science.gov (United States)

Lim, Jaemyung; Arkan, Evren F; Degertekin, F Levent; Ghovanloo, Maysam

2014-01-01

We present a system-on-a-chip (SoC) for use in high-frequency capacitive micromachined ultrasonic transducer (CMUT) imaging systems. This SoC consists of trans-impedance amplifiers (TIA), delay locked loop (DLL) based clock multiplier, quadrature sampler, and pulse width modulator (PWM). The SoC down converts RF echo signal to baseband by quadrature sampling which facilitates modulation. To send data through a 1.6 m wire in the catheter which has limited bandwidth and is vulnerable to noise, the SoC creates a pseudo-digital PWM signal which can be used for back telemetry or wireless readout of the RF data. In this implementation, using a 0.35-μm std. CMOS process, the TIA and single-to-differential (STD) converter had 45 MHz bandwidth, the quadrature sampler had 10.1 dB conversion gain, and the PWM had 5-bit ENoB. Preliminary results verified front-end functionality, and the power consumption of a TIA, STD, quadrature sampler, PWM, and clock multiplier was 26 mW from a 3 V supply.

Read-out concepts for FPGA-based sub-systems within the CBM detector

Energy Technology Data Exchange (ETDEWEB)

Michel, Jan [Goethe-Universitaet Frankfurt (Germany); Collaboration: CBM-Collaboration

2015-07-01

The Compressed Baryonic Matter experiment (CBM) to be built at FAIR consists of several individual sub-detectors. Some are based on custom ASICs as front-ends. Others employ FPGA based modules where extensive slow control features can be implemented to ease the recording of data and to allow for fast detection of any kind of error condition. Being designed as a free-running data acquisition, the demands also include a synchronized read-out, i.e. distribution of a common clock signal to all modules. To reduce the complexity of wiring, this is to be done sharing the same optical fibers as the data transport. During the past years, TrbNet has been designed and is used in various experiments, initially for the HADES experiment at FAIR. This protocol can now serve as a platform for the CBM read-out. In several steps, synchronous links with deterministic latency, as well as a free-streaming data transport can be included. At the same time, modifications to improve bandwidth and provide compatibility to the CERN GBTx links used for ASIC based sub-systems are to be developed. This contribution shows the planned steps as well as the current status of development.

A multichannel front end ASIC for PMT readout in LHAASO WCDA

Science.gov (United States)

Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

2018-01-01

Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

DNA Nanobiosensors: An Outlook on Signal Readout Strategies

Directory of Open Access Journals (Sweden)

Arun Richard Chandrasekaran

2017-01-01

Full Text Available A suite of functionalities and structural versatility makes DNA an apt material for biosensing applications. DNA-based biosensors are cost-effective and sensitive and have the potential to be used as point-of-care diagnostic tools. Along with robustness and biocompatibility, these sensors also provide multiple readout strategies. Depending on the functionality of DNA-based biosensors, a variety of output strategies have been reported: fluorescence- and FRET-based readout, nanoparticle-based colorimetry, spectroscopy-based techniques, electrochemical signaling, gel electrophoresis, and atomic force microscopy.

The TOTEM DAQ based on the Scalable Readout System (SRS)

Science.gov (United States)

Quinto, Michele; Cafagna, Francesco S.; Fiergolski, Adrian; Radicioni, Emilio

2018-02-01

The TOTEM (TOTal cross section, Elastic scattering and diffraction dissociation Measurement at the LHC) experiment at LHC, has been designed to measure the total proton-proton cross-section and study the elastic and diffractive scattering at the LHC energies. In order to cope with the increased machine luminosity and the higher statistic required by the extension of the TOTEM physics program, approved for the LHC's Run Two phase, the previous VME based data acquisition system has been replaced with a new one based on the Scalable Readout System. The system features an aggregated data throughput of 2GB / s towards the online storage system. This makes it possible to sustain a maximum trigger rate of ˜ 24kHz, to be compared with the 1KHz rate of the previous system. The trigger rate is further improved by implementing zero-suppression and second-level hardware algorithms in the Scalable Readout System. The new system fulfils the requirements for an increased efficiency, providing higher bandwidth, and increasing the purity of the data recorded. Moreover full compatibility has been guaranteed with the legacy front-end hardware, as well as with the DAQ interface of the CMS experiment and with the LHC's Timing, Trigger and Control distribution system. In this contribution we describe in detail the architecture of full system and its performance measured during the commissioning phase at the LHC Interaction Point.

Novel readout method for molecular diagnostic assays based on optical measurements of magnetic nanobead dynamics.

Science.gov (United States)

Donolato, Marco; Antunes, Paula; Bejhed, Rebecca S; Zardán Gómez de la Torre, Teresa; Østerberg, Frederik W; Strömberg, Mattias; Nilsson, Mats; Strømme, Maria; Svedlindh, Peter; Hansen, Mikkel F; Vavassori, Paolo

2015-02-03

We demonstrate detection of DNA coils formed from a Vibrio cholerae DNA target at picomolar concentrations using a novel optomagnetic approach exploiting the dynamic behavior and optical anisotropy of magnetic nanobead (MNB) assemblies. We establish that the complex second harmonic optical transmission spectra of MNB suspensions measured upon application of a weak uniaxial AC magnetic field correlate well with the rotation dynamics of the individual MNBs. Adding a target analyte to the solution leads to the formation of permanent MNB clusters, namely, to the suppression of the dynamic MNB behavior. We prove that the optical transmission spectra are highly sensitive to the formation of permanent MNB clusters and, thereby to the target analyte concentration. As a specific clinically relevant diagnostic case, we detect DNA coils formed via padlock probe recognition and isothermal rolling circle amplification and benchmark against a commercial equipment. The results demonstrate the fast optomagnetic readout of rolling circle products from bacterial DNA utilizing the dynamic properties of MNBs in a miniaturized and low-cost platform requiring only a transparent window in the chip.

Further studies of the stability of LiF:Mg,Cu,P (GR-200) at maximum readout temperatures between 240oC and 280oC

International Nuclear Information System (INIS)

Oster, L.; Horowitz, Y.S.; Horowitz, A.

1996-01-01

It has recently been shown that LiF:Mg,Cu,P (GR-200) can be read out to temperatures as high as 270 o C for 12 s with negligible loss in sensitivity. In the present work the long-term sensitivity of GR-200 was studied at readout temperatures between 240 o C and 280 o C. The idea was that the readout temperatures above 240 o C might initiate reaction processes which influence the sensitivity only after long-term storage. No difference was found in the behaviour of GR-200 chips with 80 accumulated readouts to 240 o C or 270 o C and after storage of up to four months. Slight losses in sensitivity of 4% for 240 o C and 10% for 270 o C are observed after 80 readouts during four months storage. However, at a maximum readout temperature of 280 o C, a 33% loss in sensitivity after 80 cycles is observed. In conclusion it is found that GR-200 can be read out at temperatures as high as 270 o C with negligible loss in sensitivity (less than 0.1% per readout following an initialisation procedure of 1 readout) and acceptable residual signal (0.6%). (author)

Beam test performance of the APV5 chip

International Nuclear Information System (INIS)

De Fez-Laso, M.D.M.; Gill, K.; MacEvoy, B.; Millmore, M.; Potts, A.; Raymond, M.

1996-01-01

The performance of the latest prototype of the radiation hard front end chip to be used by the CMS collaboration for analogue readout of the microstrip tracker has been evaluated with a silicon microstrip detector in a beam at CERN. The circuit, developed by the RD20 collaboration, consists of 128 channels of amplifier, pipeline memory, analogue signal processor and a serial multiplexer. As a result of these studies improvements in the circuit design have been devised which will be implemented in the next version. (orig.)

A readout buffer prototype for ATLAS high-level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2001-01-01

Readout buffers are critical components in the dataflow chain of the ATLAS trigger/data-acquisition system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several readout buffers are grouped to form a readout buffer complex that acts as a data server for the high-level trigger selection algorithms and for the final data-collection system. This paper describes a functional prototype of a readout buffer based on a custom-made PCI mezzanine card that is designed to accept input data at up to 160 MB /s, to store up to 8 MB of data, and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel 1960 processor and complex programmable logic devices. We present the integration of several of these cards in a readout buffer complex. We measure various performance figures and discuss to which extent these can fulfil ATLAS needs. (5 refs).

Timing and Readout Contorl in the LHCb Upgraded Readout System

CERN Document Server

Alessio, Federico

2016-01-01

In 2019, the LHCb experiment at CERN will undergo a major upgrade where its detectors electronics and entire readout system will be changed to read-out events at the full LHC rate of 40 MHz. In this paper, the new timing, trigger and readout control system for such upgrade is reviewed. Particular attention is given to the distribution of the clock, timing and synchronization information across the entire readout system using generic FTTH technology like Passive Optical Networks. Moreover the system will be responsible to generically control the Front-End electronics by transmitting configuration data and receiving monitoring data, offloading the software control system from the heavy task of manipulating complex protocols of thousands of Front-End electronics devices. The way in which this was implemented is here reviewed with a description of results from first implementations of the system, including usages in test-benches, implementation of techniques for timing distribution and latency control."

GaN-based integrated photonics chip with suspended LED and waveguide

Science.gov (United States)

Li, Xin; Wang, Yongjin; Hane, Kazuhiro; Shi, Zheng; Yan, Jiang

2018-05-01

We propose a GaN-based integrated photonics chip with suspended LED and straight waveguide with different geometric parameters. The integrated photonics chip is prepared by double-side process. Light transmission performance of the integrated chip verse current is quantitatively analyzed by capturing light transmitted to waveguide tip and BPM (beam propagation method) simulation. Reduction of the waveguide width from 8 μm to 4 μm results in an over linear reduction of the light output power while a doubling of the length from 250 μm to 500 μm only results in under linear decrease of the output power. Free-space data transmission with 80 Mbps random binary sequence of the integrated chip is capable of achieving high speed data transmission via visible light. This study provides a potential approach for GaN-based integrated photonics chip as micro light source and passive optical device in VLC (visible light communication).

Design of analog front-ends for the RD53 demonstrator chip

CERN Document Server

Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

2017-01-01

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

[Evaluation of Image Quality of Readout Segmented EPI with Readout Partial Fourier Technique].

Science.gov (United States)

Yoshimura, Yuuki; Suzuki, Daisuke; Miyahara, Kanae

Readout segmented EPI (readout segmentation of long variable echo-trains: RESOLVE) segmented k-space in the readout direction. By using the partial Fourier method in the readout direction, the imaging time was shortened. However, the influence on image quality due to insufficient data sampling is concerned. The setting of the partial Fourier method in the readout direction in each segment was changed. Then, we examined signal-to-noise ratio (SNR), contrast-to-noise ratio (CNR), and distortion ratio for changes in image quality due to differences in data sampling. As the number of sampling segments decreased, SNR and CNR showed a low value. In addition, the distortion ratio did not change. The image quality of minimum sampling segments is greatly different from full data sampling, and caution is required when using it.

A real-time data transmission method based on Linux for physical experimental readout systems

International Nuclear Information System (INIS)

Cao Ping; Song Kezhu; Yang Junfeng

2012-01-01

In a typical physical experimental instrument, such as a fusion or particle physical application, the readout system generally implements an interface between the data acquisition (DAQ) system and the front-end electronics (FEE). The key task of a readout system is to read, pack, and forward the data from the FEE to the back-end data concentration center in real time. To guarantee real-time performance, the VxWorks operating system (OS) is widely used in readout systems. However, VxWorks is not an open-source OS, which gives it has many disadvantages. With the development of multi-core processor and new scheduling algorithm, Linux OS exhibits performance in real-time applications similar to that of VxWorks. It has been successfully used even for some hard real-time systems. Discussions and evaluations of real-time Linux solutions for a possible replacement of VxWorks arise naturally. In this paper, a real-time transmission method based on Linux is introduced. To reduce the number of transfer cycles for large amounts of data, a large block of contiguous memory buffer for DMA transfer is allocated by modifying the Linux Kernel (version 2.6) source code slightly. To increase the throughput for network transmission, the user software is designed into formation of parallelism. To achieve high performance in real-time data transfer from hardware to software, mapping techniques must be used to avoid unnecessary data copying. A simplified readout system is implemented with 4 readout modules in a PXI crate. This system can support up to 48 MB/s data throughput from the front-end hardware to the back-end concentration center through a Gigabit Ethernet connection. There are no restrictions on the use of this method, hardware or software, which means that it can be easily migrated to other interrupt related applications.

A CMOS 130nm Evaluation digitzer chip for silicon strips readout

CERN Document Server

Da Silva, W; Dhellot, M; Fougeron, D; Genat, J F; Hermel, R; Huppert, J f; Kapusta, F; Lebbolo, H; Pham, T H; Rossel, F; Savoy-navarro, A; Sefri, R; Vilalte

2007-01-01

A CMOS 130nm evaluation chip intended to read Silicon strip detectors at the ILC has been designed and successfully tested. Optimized for a detector capacitance of 10 pF, it includes four channels of charge integration, pulse shaping, a 16-deep analogue sampler triggered on input analogue sums, and parallel analogue to digital conversion. Tests results of the full chain are reported, demonstrating the behaviour and performance of the full sampling process and analogue to digital conversion. Each channel dissipates less than one milli-Watt static power.

Lab-on-a-Chip Based Protein Crystallization

Science.gov (United States)

vanderWoerd, Mark J.; Brasseur, Michael M.; Spearing, Scott F.; Whitaker, Ann F. (Technical Monitor)

2001-01-01

We are developing a novel technique with which we will grow protein crystals in very small volumes, utilizing chip-based, microfluidic ("LabChip") technology. This development, which is a collaborative effort between NASA's Marshall Space Flight Center and Caliper Technologies Corporation, promises a breakthrough in the field of protein crystal growth. Our initial results obtained from two model proteins, Lysozyme and Thaumatin, show that it is feasible to dispense and adequately mix protein and precipitant solutions on a nano-liter scale. The mixtures have shown crystal growth in volumes in the range of 10 nanoliters to 5 microliters. In addition, large diffraction quality crystals were obtained by this method. X-ray data from these crystals were shown to be of excellent quality. Our future efforts will include the further development of protein crystal growth with LabChip(trademark) technology for more complex systems. We will initially address the batch growth method, followed by the vapor diffusion method and the liquid-liquid diffusion method. The culmination of these chip developments is to lead to an on orbit protein crystallization facility on the International Space Station. Structural biologists will be invited to utilize the on orbit Iterative Biological Crystallization facility to grow high quality macromolecular crystals in microgravity.

chipPCR: an R package to pre-process raw data of amplification curves.

Science.gov (United States)

Rödiger, Stefan; Burdukiewicz, Michał; Schierack, Peter

2015-09-01

Both the quantitative real-time polymerase chain reaction (qPCR) and quantitative isothermal amplification (qIA) are standard methods for nucleic acid quantification. Numerous real-time read-out technologies have been developed. Despite the continuous interest in amplification-based techniques, there are only few tools for pre-processing of amplification data. However, a transparent tool for precise control of raw data is indispensable in several scenarios, for example, during the development of new instruments. chipPCR is an R: package for the pre-processing and quality analysis of raw data of amplification curves. The package takes advantage of R: 's S4 object model and offers an extensible environment. chipPCR contains tools for raw data exploration: normalization, baselining, imputation of missing values, a powerful wrapper for amplification curve smoothing and a function to detect the start and end of an amplification curve. The capabilities of the software are enhanced by the implementation of algorithms unavailable in R: , such as a 5-point stencil for derivative interpolation. Simulation tools, statistical tests, plots for data quality management, amplification efficiency/quantification cycle calculation, and datasets from qPCR and qIA experiments are part of the package. Core functionalities are integrated in GUIs (web-based and standalone shiny applications), thus streamlining analysis and report generation. http://cran.r-project.org/web/packages/chipPCR. Source code: https://github.com/michbur/chipPCR. stefan.roediger@b-tu.de Supplementary data are available at Bioinformatics online. © The Author 2015. Published by Oxford University Press. All rights reserved. For Permissions, please e-mail: journals.permissions@oup.com.

BJT detector with FPGA-based read-out for alpha particle monitoring

International Nuclear Information System (INIS)

Tyzhnevyi, V; Dalla Betta, G-F; Rovati, L; Verzellesi, G; Zorzi, N

2011-01-01

In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an α-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

BJT detector with FPGA-based read-out for alpha particle monitoring

Energy Technology Data Exchange (ETDEWEB)

Tyzhnevyi, V; Dalla Betta, G-F [Universita di Trento, via Sommarive, 14, 38123 Trento (Italy); Rovati, L [Universita di Modena e Reggio Emilia, via Vignolese 905, 41125 Modena (Italy); Verzellesi, G [Universita di Modena e Reggio Emilia, via Amendola 2, Pad. Morselli, 42100 Reggio Emilia (Italy); Zorzi, N, E-mail: tyzhnevyi@disi.unitn.it [Fondazione Bruno Kessler, via Sommarive, 18, 38123 Trento (Italy)

2011-01-15

In this work we introduce a new prototype of readout electronics (ALPHADET), which was designed for an {alpha}-particle detection system based on a bipolar junction transistor (BJT) detector. The system uses an FPGA, which provides many advantages at the stage of prototyping and testing the detector. The main design and electrical features of the board are discussed in this paper, along with selected results from the characterization of ALPHADET coupled to BJT detectors.

Laser Power Measurement Using Commercial MEMS Pressure Sensor along with PSoC Embedded Read-out

Directory of Open Access Journals (Sweden)

J. Jayapandian

2011-06-01

Full Text Available Solid-state, gas, semiconductor and other types of lasers are extensively employed in industry for producing laser beams used in such wide ranging fields as machining, medicine and communications. In such applications, it is necessary to be able to accurately measure the power of the laser beam that is emitted by the laser. This paper describes a novel design technique which uses the diaphragm of a commercial MEMS pressure sensor as a target surface on which laser beam impinge, transfer heat and causes change in piezo resistance. The measured change in resistance was proportional to the intensity of laser beam in the range of 0 to 300 mW. The ratio metric embedded read-out design using a single chip programmable system on chip (PSoC has been used to acquire the resistance.

A Hybrid Readout Solution for GaN-Based Detectors Using CMOS Technology †

Science.gov (United States)

Hancock, Bruce; Nikzad, Shouleh; Bell, L. Douglas; Kroep, Kees; Charbon, Edoardo

2018-01-01

Gallium nitride (GaN) and its alloys are becoming preferred materials for ultraviolet (UV) detectors due to their wide bandgap and tailorable out-of-band cutoff from 3.4 eV to 6.2 eV. GaN based avalanche photodiodes (APDs) are particularly suitable for their high photon sensitivity and quantum efficiency in the UV region and for their inherent insensitivity to visible wavelengths. Challenges exist however for practical utilization. With growing interests in such photodetectors, hybrid readout solutions are becoming prevalent with CMOS technology being adopted for its maturity, scalability, and reliability. In this paper, we describe our approach to combine GaN APDs with a CMOS readout circuit, comprising of a linear array of 1 × 8 capacitive transimpedance amplifiers (CTIAs), implemented in a 0.35 µm high voltage CMOS technology. Further, we present a simple, yet sustainable circuit technique to allow operation of APDs under high reverse biases, up to ≈80 V with verified measurement results. The readout offers a conversion gain of 0.43 µV/e−, obtaining avalanche gains up to 103. Several parameters of the CTIA are discussed followed by a perspective on possible hybridization, exploiting the advantages of a 3D-stacked technology. PMID:29401655

Developing an optimum protocol for thermoluminescence dosimetry with gr-200 chips using Taguchi method

International Nuclear Information System (INIS)

Sadeghi, Maryam; Faghihi, Reza; Sina, Sedigheh

2017-01-01

Thermoluminescence dosimetry (TLD) is a powerful technique with wide applications in personal, environmental and clinical dosimetry. The optimum annealing, storage and reading protocols are very effective in accuracy of TLD response. The purpose of this study is to obtain an optimum protocol for GR-200; LiF: Mg, Cu, P, by optimizing the effective parameters, to increase the reliability of the TLD response using Taguchi method. Taguchi method has been used in this study for optimization of annealing, storage and reading protocols of the TLDs. A number of 108 GR-200 chips were divided into 27 groups, each containing four chips. The TLDs were exposed to three different doses, and stored, annealed and read out by different procedures as suggested by Taguchi Method. By comparing the signal-to-noise ratios the optimum dosimetry procedure was obtained. According to the results, the optimum values for annealing temperature (de.C), Annealing Time (s), Annealing to Exposure time (d), Exposure to Readout time (d), Pre-heat Temperature (de.C), Pre-heat Time (s), Heating Rate (de.C/s), Maximum Temperature of Readout (de.C), readout time (s) and Storage Temperature (de.C) are 240, 90, 1, 2, 50, 0, 15, 240, 13 and -20, respectively. Using the optimum protocol, an efficient glow curve with low residual signals can be achieved. Using optimum protocol obtained by Taguchi method, the dosimetry can be effectively performed with great accuracy. (authors)

The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

Energy Technology Data Exchange (ETDEWEB)

Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

2013-12-21

The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

A 130 nm ASIC prototype for the NA62 Gigatracker readout

Energy Technology Data Exchange (ETDEWEB)

Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

2011-09-11

One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

First performance results of the ALICE TPC Readout Control Unit 2

OpenAIRE

Zhao, Chengxin; Alme, Johan; Alt, Torsten; Appelshäuser, Harald; Bratrud, Lars Karlot Stubberud; Castro, Andrew; Costa, Filippo; David, Ernö; Gunji, Tako; Kirsch, S; Kiss, Tivadar; Langøy, Rune; Lien, Jørgen; Lippmann, C; Oskarsson, Anders

2016-01-01

- This paper presents the first performance results of the ALICE TPC Readout Control Unit 2 (RCU2). With the upgraded hardware typology and the new readout scheme in FPGA design, the RCU2 is designed to achieve twice the readout speed of the present Readout Control Unit. Design choices such as using the flash-based Microsemi Smartfusion2 FPGA and applying mitigation techniques in interfaces and FPGA design ensure a high degree of radiation tolerance. This paper presents the system level ir...

LHCb: A new Readout Control system for the LHCb Upgrade

CERN Multimedia

Alessio, F

2012-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and the first hardware implementation of a new Readout Control system for the LHCb upgrade. The system is based on FPGAs and bi-directional links for the control of the entire readout architecture. First results on the validation of the system are also given.

Read-out and calibration of a tile calorimeter for ATLAS

International Nuclear Information System (INIS)

Tardell, S.

1997-06-01

The read-out and calibration of scintillating tiles hadronic calorimeter for ATLAS is discussed. Tests with prototypes of FERMI, a system of read-out electronics based on a dynamic range compressor reducing the dynamic range from 16 to 10 bits and a 40 MHz 10 bits sampling ADC, are presented. In comparison with a standard charge integrating read-out improvements in the resolution of 1% in the constant term are obtained

FPGA-based upgrade of the read-out electronics for the low energy polarimeter at COSY/Juelich

Energy Technology Data Exchange (ETDEWEB)

Hempelmann, Nils [Institut fuer Kernphysik, Forschungszentrum Juelich (Germany); Collaboration: JEDI-Collaboration

2016-07-01

The Cooler Synchrotron (COSY) is a facility for cooled polarized beams at the Forschungszentrum in Juelich. The Low Energy Polarimeter (LEP) is the polarimeter in the injection beam line of COSY. The beam polarization is measured using scattering off carbon and polyethylene (CH2) targets. The outgoing particles are detected using twelve plastic scintillators installed in groups of three to the left, to the right, above, and below the beam. The LEP is the routine tool for beam set-up, but its performance was limited by the old read-out electronics consisting of analog NIM modules. A new system using analog pulse sampling and an FPGA chip for signal processing was installed and tested. The ejectile particles were identified by relative time of flight measurement using a signal from the RF amplifier of the cyclotron used for acceleration as a reference. The new system is able to measure the time at which a particle arrives to an accuracy in the order of 50 ps. The presentation includes a review of available systems and a report about measurements in May and December 2015.

SiPM based readout system for PbWO4 crystals

Science.gov (United States)

Berra, A.; Bolognini, D.; Bonfanti, S.; Bonvicini, V.; Lietti, D.; Penzo, A.; Prest, M.; Stoppani, L.; Vallazza, E.

2013-08-01

Silicon PhotoMultipliers (SiPMs) consist of a matrix of small passively quenched silicon avalanche photodiodes operated in limited Geiger-mode (GM-APDs) and read out in parallel from a common output node. Each pixel (with a typical size in the 20-100 μm range) gives the same current response when hit by a photon; the SiPM output signal is the sum of the signals of all the pixels, which depends on the light intensity. The main advantages of SiPMs with respect to photomultiplier tubes (PMTs) are essentially the small dimensions, the insensitivity to magnetic fields and a low bias voltage. This contribution presents the performance of a SiPM based readout system for crystal calorimeters developed in the framework of the FACTOR/TWICE collaboration. The SiPM used for the test is a new device produced by FBK-irst which consists in a matrix of four sensors embedded in the same silicon substrate, called QUAD. The SiPM has been coupled to a lead tungstate crystal, an early-prototype version of the crystals developed for the electromagnetic calorimeter of the CMS experiment. New tests are foreseen using a complete module consisting of nine crystals, each one readout by two QUADs.

SiPM based readout system for PbWO4 crystals

International Nuclear Information System (INIS)

Berra, A.; Bolognini, D.; Bonfanti, S.; Bonvicini, V.; Lietti, D.; Penzo, A.; Prest, M.; Stoppani, L.; Vallazza, E.

2013-01-01

Silicon PhotoMultipliers (SiPMs) consist of a matrix of small passively quenched silicon avalanche photodiodes operated in limited Geiger-mode (GM-APDs) and read out in parallel from a common output node. Each pixel (with a typical size in the 20–100 μm range) gives the same current response when hit by a photon; the SiPM output signal is the sum of the signals of all the pixels, which depends on the light intensity. The main advantages of SiPMs with respect to photomultiplier tubes (PMTs) are essentially the small dimensions, the insensitivity to magnetic fields and a low bias voltage. This contribution presents the performance of a SiPM based readout system for crystal calorimeters developed in the framework of the FACTOR/TWICE collaboration. The SiPM used for the test is a new device produced by FBK-irst which consists in a matrix of four sensors embedded in the same silicon substrate, called QUAD. The SiPM has been coupled to a lead tungstate crystal, an early-prototype version of the crystals developed for the electromagnetic calorimeter of the CMS experiment. New tests are foreseen using a complete module consisting of nine crystals, each one readout by two QUADs

Noise Reduction Effect of Multiple-Sampling-Based Signal-Readout Circuits for Ultra-Low Noise CMOS Image Sensors

Directory of Open Access Journals (Sweden)

Shoji Kawahito

2016-11-01

Full Text Available This paper discusses the noise reduction effect of multiple-sampling-based signal readout circuits for implementing ultra-low-noise image sensors. The correlated multiple sampling (CMS technique has recently become an important technology for high-gain column readout circuits in low-noise CMOS image sensors (CISs. This paper reveals how the column CMS circuits, together with a pixel having a high-conversion-gain charge detector and low-noise transistor, realizes deep sub-electron read noise levels based on the analysis of noise components in the signal readout chain from a pixel to the column analog-to-digital converter (ADC. The noise measurement results of experimental CISs are compared with the noise analysis and the effect of noise reduction to the sampling number is discussed at the deep sub-electron level. Images taken with three CMS gains of two, 16, and 128 show distinct advantage of image contrast for the gain of 128 (noise(median: 0.29 e−rms when compared with the CMS gain of two (2.4 e−rms, or 16 (1.1 e−rms.

Rutherford X-ray spectrometer readout

International Nuclear Information System (INIS)

Bateman, J.E.

1978-07-01

Rutherford electronic X-ray spectrometer readout is based on the combination of two established techniques (a) the detection and location of soft X-rays by means of multichannel electron multiplier arrays (MCP's), and (b) the electronic readout of charge distributions (generally in multi-wire proportional counters) by means of the delay line techniques. In order for the latter device to function well a charge signal of approximately 10 6 electrons must be available to the delay line wand. This is achieved in the present device by means of two cascaded MCP's which can produce electron gains up to approximately 10 8 , and so operate the delay line from the single electron pulses generated at the front face of an MCP by a soft X-ray. The delay line readout technique was chosen because of its simplicity (both in terms of the necessary hardware and the associated electronics), robustness, and ease of implementation. In order to achieve the target spatial resolution of 50 μm (fwhm) or 20 μm (standard deviation) it was necessary to adapt the charge collection system so that the readout takes place from a length of delay line 200 mm long. The general layout of the system and the functions of the electronic circuits are described. Performance testing, setting up procedures and trouble shooting of the system are discussed. (U.K.)

Front-end electronics for the readout of CdZnTe sensors

CERN Document Server

Moraes, D; Rudge, A

2006-01-01

The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.

A CMOS micromachined capacitive tactile sensor with integrated readout circuits and compensation of process variations.

Science.gov (United States)

Tsai, Tsung-Heng; Tsai, Hao-Cheng; Wu, Tien-Keng

2014-10-01

This paper presents a capacitive tactile sensor fabricated in a standard CMOS process. Both of the sensor and readout circuits are integrated on a single chip by a TSMC 0.35 μm CMOS MEMS technology. In order to improve the sensitivity, a T-shaped protrusion is proposed and implemented. This sensor comprises the metal layer and the dielectric layer without extra thin film deposition, and can be completed with few post-processing steps. By a nano-indenter, the measured spring constant of the T-shaped structure is 2.19 kNewton/m. Fully differential correlated double sampling capacitor-to-voltage converter (CDS-CVC) and reference capacitor correction are utilized to compensate process variations and improve the accuracy of the readout circuits. The measured displacement-to-voltage transductance is 7.15 mV/nm, and the sensitivity is 3.26 mV/μNewton. The overall power dissipation is 132.8 μW.

A read-out buffer prototype for ATLAS high level triggers

CERN Document Server

Calvet, D; Huet, M; Le Dû, P; Mandjavidze, I D; Mur, M

2000-01-01

Read-Out Buffers are critical components in the dataflow chain of the ATLAS Trigger/DAQ system. At up to 75 kHz, after each Level-1 trigger accept signal, these devices receive and store digitized data from groups of front-end electronic channels. Several Read-Out Buffers are grouped to form a Read-Out Buffer Complex that acts as a data server for the High Level Triggers selection algorithms and for the final data collection system. This paper describes a functional prototype of a Read-Out Buffer based on a custom made PCI mezzanine card that is designed to accept input data at up to 160 MB/s, to store up to 8 MB of data and to distribute data chunks at the desired request rate. We describe the hardware of the card that is based on an Intel I960 processor and CPLDs. We present the integration of several of these cards in a Read-Out Buffer Complex. We measure various performance figures and we discuss to which extent these can fulfill ATLAS needs. 5 Refs.

CBC2: A CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

Energy Technology Data Exchange (ETDEWEB)

Hall, G., E-mail: g.hall@imperial.ac.uk [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Pesaresi, M.; Raymond, M. [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Braga, D.; Jones, L.; Murray, P.; Prydderch, M. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 OQX (United Kingdom); Abbaneo, D.; Blanchot, G.; Honma, A.; Kovacs, M.; Vasey, F. [CERN, CH-1211, Geneva (Switzerland)

2014-11-21

The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130 nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

FAIR: A new fast trigger and readout bus system

International Nuclear Information System (INIS)

Ordine, A.; Boiano, A.; Zaghi, A.

1998-01-01

FAIR (FAst Intercrate Readout) is a synchronous ECL bus system dedicated to readout. It is based on a new trigger and readout hardware level protocol and on a new control system that learns how to setup and control modules. The hardware protocol along with the data structure allow both readout and event building at the same time at the rate of 22 ns/longword (1.44 Gbit/s) without the need of CPUs. It performs trigger management and full pipelining by using a multilevel FIFO structure. FAIR provides for a multi-crate front-end environment and uses an embedded serial network to accomplish front-end control and setup. The data transfer measured performances and the control system are presented in some detail

On-ground characterization of the Euclid's CCD273-based readout chain

Science.gov (United States)

Szafraniec, Magdalena; Azzollini, R.; Cropper, M.; Pottinger, S.; Khalil, A.; Hailey, M.; Hu, D.; Plana, C.; Cutts, A.; Hunt, T.; Kohley, R.; Walton, D.; Theobald, C.; Sharples, R.; Schmoll, J.; Ferrando, P.

2016-07-01

Euclid is a medium class European Space Agency mission scheduled for launch in 2020. The goal of the survey is to examine the nature of Dark Matter and Dark Energy in the Universe. One of the cosmological probes used to analyze Euclid's data, the weak lensing technique, measures the distortions of galaxy shapes and this requires very accurate knowledge of the system point spread function (PSF). Therefore, to ensure that the galaxy shape is not affected, the detector chain of the telescope's VISible Instrument (VIS) needs to meet specific performance performance requirements. Each of the 12 VIS readout chains consisting of 3 CCDs, readout electronics (ROE) and a power supply unit (RPSU) will undergo a rigorous on-ground testing to ensure that these requirements are met. This paper reports on the current status of the warm and cold testing of the VIS Engineering Model readout chain. Additionally, an early insight to the commissioning of the Flight Model calibration facility and program is provided.

Novel gas-based detection techniques

International Nuclear Information System (INIS)

Graaf, Harry van der

2009-01-01

This year we celebrate the 100th birthday of gaseous detectors: Hans Geiger operated the first gas-filled counter in Manchester in 1908. The thin wires, essential for obtaining gas amplification, have been replaced by Micro Pattern Gas Detectors (MPGDs): Micromegas (1995) and GEM (1996). In the GridPix detector, each of the grid holes of a MPGD is equipped with its own electronic readout channel in the form of an active pixel in suitable pixel CMOS chips. By means of MEMS technology, the grid has been integrated with the chip, forming a monolithic readout device for gas volumes. By applying a protection layer made of hydrogenated amorphous silicon, the chips can be made spark proof. New protection layers have been made of silicon nitride. The use of gas as detection material for trackers is compared to Si, and the issue of chamber aging is addressed. New developments are set out: the development of Micro Channel Plates, integrated on pixel chips, the development of electron emission foil, and the realization of TimePix-2: a general-purpose pixel chip with time and amplitude measurement, per pixel, of charge signals.

Comparing interferometry techniques for multi-degree of freedom test mass readout

International Nuclear Information System (INIS)

Isleif, Katharina-Sophie; Gerberding, Oliver; Mehmet, Moritz; Schwarze, Thomas S; Heinzel, Gerhard; Danzmann, Karsten

2016-01-01

Laser interferometric readout systems with 1pm/Hz precision over long time scales have successfully been developed for LISA and LISA Pathfinder. Future gravitational physics experiments, for example in the fields of gravitational wave detection and geodesy, will potentially require similar levels of displacement and tilt readouts of multiple test masses in multiple degrees of freedom. In this article we compare currently available classic interferometry schemes with new techniques using phase modulations and complex readout algorithms. Based on a simple example we show that the new techniques have great potential to simplify interferometric readouts. (paper)

Chip based electroanalytical systems for cell analysis

DEFF Research Database (Denmark)

Spegel, C.; Heiskanen, A.; Skjolding, L.H.D.

2008-01-01

' measurements of processes related to living cells, i.e., systems without lysing the cells. The focus is on chip based amperometric and impedimetric cell analysis systems where measurements utilizing solely carbon fiber microelectrodes (CFME) and other nonchip electrode formats, such as CFME for exocytosis...

A 3x1 integrated pyroelectric sensor based on VDF/TrFE copolymer

NARCIS (Netherlands)

Setiadi, D.; Setiadi, D.; Sarro, P.M.; Regtien, Paulus P.L.

1996-01-01

This paper presents an integrated pyroelectric sensor based on a vinylidene fluoride¿trifluoroethylene (VDF/TrFE) copolymer. A silicon substrate that contains field-effect transistor (FET) readout electronics is coated with the VDF/TrFE copolymer film using a spin-coating technique. On-chip poling

A study of SEU-tolerant latches for the RD53A chip

CERN Document Server

Fougeron, Denis

2018-01-01

The RD53 collaboration was established to develop the next generation of pixel readout chips needed by ATLAS and CMS at the HL-LHC and requiring extreme rate and radiation tolerance. The 65 nm CMOS process has been adopted in order to satisfy the high level of integration requirement. However, the SEU immunity should be carefully considered for a deep submicron process like the 65 nm. Indeed, the device dimensions are small and the capacitance of the storage nodes becomes very low. A chip prototype including different SEU tolerant structures was designed in a 65 nm technology. Several proton irradiation tests were carried out in order to estimate the SEU tolerance of the proposed structures and the level of improvement comparing with a standard architecture.

Environmental sensors based on micromachined cantilevers with integrated read-out

DEFF Research Database (Denmark)

Boisen, Anja; Thaysen, Jacob; Jensenius, Henriette

2000-01-01

-out facilitates measurements in liquid. The probe has been successfully implemented in gaseous as well as in liquid experiments. For example, the probe has been used as an accurate and minute thermal sensor and as a humidity sensor. In liquid, the probe has been used to detect the presence of alcohol in water. (C......An AFM probe with integrated piezoresistive read-out has been developed and applied as a cantilever-based environmental sensor. The probe has a built-in reference cantilever, which makes it possible to subtract background drift directly in the measurement. Moreover, the integrated read...

Design and Verification of Digital Architecture of 65K Pixel Readout Chip for High-Energy Physics

CERN Document Server

Poikela, Tuomas; Paakkulainen, J

2010-01-01

The feasibility to design and implement a front-end ASIC for the upgrade of the VELO detector of LHCb experiment at CERN using IBM’s 130nm standard CMOS process and a standard cell library is studied in this thesis. The proposed architecture is a design to cope with high data rates and continuous data taking. The architecture is designed to operate without any external trigger to record every hit signal the ASIC receives from a sensor chip, and then to transmit the information to the next level of electronics, for example to FPGAs. This thesis focuses on design, implementation and functional verification of the digital electronics of the active pixel area. The area requirements are dictated by the geometry of pixels (55$mu$m x 55$mu$m), power requirements (20W/module) by restricted cooling capabilities of the module consisting of 10 chips and output bandwidth requirements by data rate (< 10 Gbit/s) produced by a particle flux passing through the chip. The design work was carried out using transaction...

Characterizing Rat PNS Electrophysiological Response to Electrical Stimulation Using in vitro Chip-Based Human Investigational Platform (iCHIP)

Energy Technology Data Exchange (ETDEWEB)

Khani, Joshua [Georgetown Univ., Washington, DC (United States); Prescod, Lindsay [Georgetown Univ., Washington, DC (United States); Enright, Heather [Georgetown Univ., Washington, DC (United States); Felix, Sarah [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Osburn, Joanne [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Wheeler, Elizabeth [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States); Kulp, Kris [Lawrence Livermore National Lab. (LLNL), Livermore, CA (United States)

2015-08-18

Ex vivo systems and organ-on-a-chip technology offer an unprecedented approach to modeling the inner workings of the human body. The ultimate goal of LLNL’s in vitro Chip-based Human Investigational Platform (iCHIP) is to integrate multiple organ tissue cultures using microfluidic channels, multi-electrode arrays (MEA), and other biosensors in order to effectively simulate and study the responses and interactions of the major organs to chemical and physical stimulation. In this study, we focused on the peripheral nervous system (PNS) component of the iCHIP system. Specifically we sought to expound on prior research investigating the electrophysiological response of rat dorsal root ganglion cells (rDRGs) to chemical exposures, such as capsaicin. Our aim was to establish a protocol for electrical stimulation using the iCHIP device that would reliably elicit a characteristic response in rDRGs. By varying the parameters for both the stimulation properties – amplitude, phase width, phase shape, and stimulation/ return configuration – and the culture conditions – day in vitro and neural cell types - we were able to make several key observations and uncover a potential convention with a minimal number of devices tested. Future work will seek to establish a standard protocol for human DRGs in the iCHIP which will afford a portable, rapid method for determining the effects of toxins and novel therapeutics on the PNS.

Tests of UFXC32k chip with CdTe pixel detector

Science.gov (United States)

Maj, P.; Taguchi, T.; Nakaye, Y.

2018-02-01

The paper presents the performance of the UFXC32K—a hybrid pixel detector readout chip working with CdTe detectors. The UFXC32K has a pixel pitch of 75 μm and can cope with both input signal polarities. This functionality allows operating with widely used silicon sensors collecting holes and CdTe sensors collecting electrons. This article describes the chip focusing on solving the issues connected to high-Z sensor material, namely high leakage currents, slow charge collection time and thick material resulting in increased charge-sharring effects. The measurements were conducted with higher X-ray energies including 17.4 keV from molybdenum. Conclusions drawn inside the paper show the UFXC32K's usability for CdTe sensors in high X-ray energy applications.

Developing an Optimum Protocol for Thermoluminescence Dosimetry with GR-200 Chips using Taguchi Method.

Science.gov (United States)

Sadeghi, Maryam; Faghihi, Reza; Sina, Sedigheh

2017-06-15

Thermoluminescence dosimetry (TLD) is a powerful technique with wide applications in personal, environmental and clinical dosimetry. The optimum annealing, storage and reading protocols are very effective in accuracy of TLD response. The purpose of this study is to obtain an optimum protocol for GR-200; LiF: Mg, Cu, P, by optimizing the effective parameters, to increase the reliability of the TLD response using Taguchi method. Taguchi method has been used in this study for optimization of annealing, storage and reading protocols of the TLDs. A number of 108 GR-200 chips were divided into 27 groups, each containing four chips. The TLDs were exposed to three different doses, and stored, annealed and read out by different procedures as suggested by Taguchi Method. By comparing the signal-to-noise ratios the optimum dosimetry procedure was obtained. According to the results, the optimum values for annealing temperature (°C), Annealing Time (s), Annealing to Exposure time (d), Exposure to Readout time (d), Pre-heat Temperature (°C), Pre-heat Time (s), Heating Rate (°C/s), Maximum Temperature of Readout (°C), readout time (s) and Storage Temperature (°C) are 240, 90, 1, 2, 50, 0, 15, 240, 13 and -20, respectively. Using the optimum protocol, an efficient glow curve with low residual signals can be achieved. Using optimum protocol obtained by Taguchi method, the dosimetry can be effectively performed with great accuracy. © The Author 2016. Published by Oxford University Press. All rights reserved. For Permissions, please email: journals.permissions@oup.com.

Development of a versatile readout and test system and characterization of a capacitively coupled active pixel sensor

Energy Technology Data Exchange (ETDEWEB)

Janssen, Jens; Gonella, Laura; Hemperek, Tomasz; Hirono, Toko; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Institute of Physics, University of Bonn, Bonn (Germany); Peric, Ivan [Karlsruher Institut fuer Technologie, Karlsruhe (Germany); Collaboration: ATLAS-Collaboration

2015-07-01

With the availability of high voltage and high resistivity CMOS processes, active pixel sensors are becoming increasingly interesting for radiation detection in high energy physics experiments. Although the pixel signal-to-noise ratio and the sensor radiation tolerance were improved, active pixel sensors cannot yet compete with state-of-the-art hybrid pixel detector in a high radiation environment. Hence, active pixel sensors are possible candidates for the outer tracking detector in HEP experiments where production cost plays a role. The investigation of numerous prototyping steps and different technologies is still ongoing and requires a versatile test and readout system, which will be presented in this talk. A capacitively coupled active pixel sensor fabricated in AMS 180 nm high voltage CMOS process is investigated. The sensor is designed to be glued to existing front-end pixel readout chips. Results from the characterization are presented in this talk.

Self-corrected chip-based dual-comb spectrometer.

Science.gov (United States)

Hébert, Nicolas Bourbeau; Genest, Jérôme; Deschênes, Jean-Daniel; Bergeron, Hugo; Chen, George Y; Khurmi, Champak; Lancaster, David G

2017-04-03

We present a dual-comb spectrometer based on two passively mode-locked waveguide lasers integrated in a single Er-doped ZBLAN chip. This original design yields two free-running frequency combs having a high level of mutual stability. We developed in parallel a self-correction algorithm that compensates residual relative fluctuations and yields mode-resolved spectra without the help of any reference laser or control system. Fluctuations are extracted directly from the interferograms using the concept of ambiguity function, which leads to a significant simplification of the instrument that will greatly ease its widespread adoption and commercial deployment. Comparison with a correction algorithm relying on a single-frequency laser indicates discrepancies of only 50 attoseconds on optical timings. The capacities of this instrument are finally demonstrated with the acquisition of a high-resolution molecular spectrum covering 20 nm. This new chip-based multi-laser platform is ideal for the development of high-repetition-rate, compact and fieldable comb spectrometers in the near- and mid-infrared.

The NA60 experiment readout architecture

CERN Document Server

Floris, M; Usai, G L; David, A; Rosinsky, P; Ohnishi, H

2004-01-01

The NA60 experiment was designed to identify signatures of a new state of matter, the Quark Gluon Plasma, in heavy-ion collisions at the CERN Super Proton Synchroton. The apparatus is composed of four main detectors: a muon spectrometer (MS), a zero degree calorimeter (ZDC), a silicon vertex telescope (VT), and a silicon microstrip beam tracker (BT). The readout of the whole experiment is based on a PCI architecture. The basic unit is a general purpose PCI card, interfaced to the different subdetectors via custom mezzanine cards. This allowed us to successfully implement several completely different readout protocols (from the VME like protocol of the MS to the custom protocol of the pixel telescope). The system was fully tested with proton and ion beams, and several million events were collected in 2002 and 2003. This paper presents the readout architecture of NA60, with particular emphasis on the PCI layer common to all the subdetectors. (16 refs).

Application of the DRS chip for fast waveform digitizing

Energy Technology Data Exchange (ETDEWEB)

Ritt, Stefan, E-mail: stefan.ritt@psi.c [PSI, CH-5232 Villigen (Switzerland); Dinapoli, Roberto; Hartmann, Ueli [PSI, CH-5232 Villigen (Switzerland)

2010-11-01

The high demands of modern experiments in fast waveform digitizing led to the development of a whole family of switched capacitor arrays (SCA), called the Domino Ring Sampler (DRS). The most recent version, DRS4, is produced in a radiation hard 0.25 {mu}m CMOS process, and is capable of digitizing 9 differential input channels at sampling rates of up to 6 Giga-samples per second (GSPS) with an analogue bandwidth of 950 MHz (-3 dB). The channel depth can be configured between 1024 and 8192 cells, and the signal-to-noise ratio allows a resolution equivalent to more than 11 bits. Using an interleaved sampling technique, sampling rates up to 48 GSPS are possible. Compared with the previous versions, the DRS4 chip contains several improvements such as an on-chip PLL for sampling-frequency stabilization and various mechanisms to reduce the read out dead-time. The high bandwidth, low power consumption and short readout time make this chip attractive for many experiments, replacing traditional ADCs and TDCs. This includes time-of-flight detectors, cosmic gamma ray observatories, PET scanners and industrial applications.

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity.

Science.gov (United States)

Kafi, Md Abdul; Cho, Hyeon-Yeol; Choi, Jeong Woo

2015-07-02

Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD) or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C), C(RGD)₄ ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot) or three dimensional (rod or pillar) like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD), graphene oxide (GO) and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

Neural Cell Chip Based Electrochemical Detection of Nanotoxicity

Directory of Open Access Journals (Sweden)

Md. Abdul Kafi

2015-07-01

Full Text Available Development of a rapid, sensitive and cost-effective method for toxicity assessment of commonly used nanoparticles is urgently needed for the sustainable development of nanotechnology. A neural cell with high sensitivity and conductivity has become a potential candidate for a cell chip to investigate toxicity of environmental influences. A neural cell immobilized on a conductive surface has become a potential tool for the assessment of nanotoxicity based on electrochemical methods. The effective electrochemical monitoring largely depends on the adequate attachment of a neural cell on the chip surfaces. Recently, establishment of integrin receptor specific ligand molecules arginine-glycine-aspartic acid (RGD or its several modifications RGD-Multi Armed Peptide terminated with cysteine (RGD-MAP-C, C(RGD4 ensure farm attachment of neural cell on the electrode surfaces either in their two dimensional (dot or three dimensional (rod or pillar like nano-scale arrangement. A three dimensional RGD modified electrode surface has been proven to be more suitable for cell adhesion, proliferation, differentiation as well as electrochemical measurement. This review discusses fabrication as well as electrochemical measurements of neural cell chip with particular emphasis on their use for nanotoxicity assessments sequentially since inception to date. Successful monitoring of quantum dot (QD, graphene oxide (GO and cosmetic compound toxicity using the newly developed neural cell chip were discussed here as a case study. This review recommended that a neural cell chip established on a nanostructured ligand modified conductive surface can be a potential tool for the toxicity assessments of newly developed nanomaterials prior to their use on biology or biomedical technologies.

Multi-path interferometric Josephson directional amplifier for qubit readout

Science.gov (United States)

Abdo, Baleegh; Bronn, Nicholas T.; Jinka, Oblesh; Olivadese, Salvatore; Brink, Markus; Chow, Jerry M.

2018-04-01

We realize and characterize a quantum-limited, directional Josephson amplifier suitable for qubit readout. The device consists of two nondegenerate, three-wave-mixing amplifiers that are coupled together in an interferometric scheme, embedded in a printed circuit board. Nonreciprocity is generated by applying a phase gradient between the same-frequency pumps feeding the device, which plays the role of the magnetic field in a Faraday medium. Directional amplification and reflection-gain elimination are induced via wave interference between multiple paths in the system. We measure and discuss the main figures of merit of the device and show that the experimental results are in good agreement with theory. An improved version of this directional amplifier is expected to eliminate the need for bulky, off-chip isolation stages that generally separate quantum systems and preamplifiers in high-fidelity, quantum-nondemolition measurement setups.

Miniature silicon electronic biological assay chip and applications for rapid battlefield diagnostics

Science.gov (United States)

Cunningham, Brian T.; Regan, Robert A.; Clapp, Christopher; Hildebrant, Eric; Weinberg, Marc S.; Williams, John

1999-07-01

Assessing the medical condition of battlefield personnel requires the development of rapid, portable biological diagnostic assays for a wide variety of antigens and enzymes. Ideally, such an assay would be inexpensive, small, and require no added reagents while maintaining the sensitivity and accuracy of laboratory-based assays. In this work, a microelectromechanical (MEMS) based biological assay sensor is presented which is expected to meet the above requirements. The sensor is a thin silicon membrane resonator (SMR) which registers a decrease in resonant frequency when mass is adsorbed onto its surface. By coating the sensor surface with a monolayer of antibody, for example, we have detected the corresponding antigen with a detection resolution of 0.25 ng/ml in phosphate buffer solution. Micromachining techniques are being used to integrate many (64 elements on the first test chip) identical SMR sensors into a single silicon chip which would be capable of simultaneously performing a wide variety of biomedical assays. The sensors require only a small printed circuit board and 8V power supply to operate and provide a readout. The presentation will describe the operation of the SMR sensor, the fabrication of the sensor array, and initial test results using commercially available animal immunoglobulins in laboratory-prepared test solutions.

Cold front-end electronics and Ethernet-based DAQ systems for large LAr TPC readout

CERN Document Server

D.Autiero,; B.Carlus,; Y.Declais,; S.Gardien,; C.Girerd,; J.Marteau; H.Mathez

2010-01-01

Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detectors implies severe constraints on their readout and DAQ system. We are carrying on a R&D in electronics on a complete readout chain including an ASIC located close to the collecting planes in the argon gas phase and a DAQ system based on smart Ethernet sensors implemented in a µTCA standard. The choice of the latter standard is motivated by the similarity in the constraints with those existing in Network Telecommunication Industry. We also developed a synchronization scheme developed from the IEEE1588 standard integrated by the use of the recovered clock from the Gigabit link

Silicon-Chip-Based Optical Frequency Combs

Science.gov (United States)

2015-10-26

fiber-based polarization controllers and a polarization beam splitter , and the output power is monitored with a sensitive photodiode. We use a...a single CW laser beam coupled to a microresonators can produce stabilized, octave-spanning combs through highly cascaded four-wave mixing (FWM...resonator designs , the resonator and the coupling waveguide are monolithically integrated. Thus, the entire on-chip configuration of CMOS-compatible

The IBL Readout System

CERN Document Server

Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Kugel, A; Maettig, P; Morettini, P; Polini, A; Schroer, N

2010-01-01

The first upgrade for the ATLAS pixel detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer having new electronics assembled an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth and also compatible with the existing system to be integrated into it. The talk will describe the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

The IBL Readout System

CERN Document Server

Dopke, J; Flick, T; Gabrielli, A; Kugel, A; Maettig, P; Morettini, P; Polini, A; Schroer, N

2011-01-01

The first upgrade for the ATLAS Pixel Detector will be an additional layer, which is called IBL (Insertable B-Layer). To readout this new layer, having new electronics, an update of the readout electronics is necessary. The aim is to develop a system which is capable to read out at a higher bandwidth, but also compatible with the existing system to be integrated into it. This paper will describe the necessary development to reach a new readout system, concentrating on the requirements of a newly designed Back of Crate card as the optical interface in the counting room.

A missing factor in chip-based patch clamp assay: gigaseal

International Nuclear Information System (INIS)

Ong, W-L; Yobas, L; Ong, W-Y

2006-01-01

The 'gold' standard in the study of ionic currents across biological membranes is the Patch Clamp method. However, this is a slow, labor and skill intensive process. High throughput patch clamp devices are mainly chip-based. A major challenge in these miniaturized devices is the low rate of 'Gigaseal' formation which is critical in the study of Single Channel effect. In a conventional patch clamp, a pipette moves and patches a fixed cell (cell-adhered patch) which is grown on the bottom of a Petri dish. In the chip-based case, the cells are in suspension and move towards the fixed patch clamp sites (cell-suspended patch). In this study, using the proven conventional patch clamp setup, we investigated the effect of the differences in the cell configurations between the convention patch clamp and cell-based patch clamp. It is shown that adhered cells (as used in the conventional setup) have a much higher rate of gigaseal formation as compared to the cells in suspension (as used in chip-based devices). We postulate that the arrangement of the cytoskeleton within the cell plays a major part in the formation of the gigaseal

Building a large-area GEM-based readout chamber for the upgrade of the ALICE TPC

CERN Document Server

Gasik, Piotr

2017-01-01

A large Time Projection Chamber (TPC) is the main device for tracking and charged-particle identification in the ALICE experiment at the CERN LHC. After the second long shutdown in 2019-2020, the LHC will deliver Pb beams colliding at an interaction rate up to 50 kHz, which is about a factor of 100 above the present read-out rate of the TPC. To fully exploit the LHC potential the TPC will be upgraded based on the Gas Electron Multiplier (GEM) technology. A prototype of an ALICE TPC Outer Read-Out Chamber (OROC) was equipped with twelve large-size GEM foils as amplification stage to demonstrate the feasibility of replacing the current Multi Wire Proportional Chambers with the new technology. With a total area of $\\sim$0.76 m$^2$ it is the largest GEM-based detector built to date. The GEM OROC was installed within a test field cage and commissioned with radioactive sources.

Building a large-area GEM-based readout chamber for the upgrade of the ALICE TPC

Energy Technology Data Exchange (ETDEWEB)

Gasik, P. [Physik Department E62, Technische Universität München, Garching (Germany); Excellence Cluster ‘Origin and Structure of the Universe’, Garching (Germany)

2017-02-11

A large Time Projection Chamber (TPC) is the main device for tracking and charged-particle identification in the ALICE experiment at the CERN LHC. After the second long shutdown in 2019–2020, the LHC will deliver Pb beams colliding at an interaction rate up to 50 kHz, which is about a factor of 100 above the present read-out rate of the TPC. To fully exploit the LHC potential the TPC will be upgraded based on the Gas Electron Multiplier (GEM) technology. A prototype of an ALICE TPC Outer Read-Out Chamber (OROC) was equipped with twelve large-size GEM foils as amplification stage to demonstrate the feasibility of replacing the current Multi Wire Proportional Chambers with the new technology. With a total area of ∼0.76 m{sup 2} it is the largest GEM-based detector built to date. The GEM OROC was installed within a test field cage and commissioned with radioactive sources.

Building a large-area GEM-based readout chamber for the upgrade of the ALICE TPC

International Nuclear Information System (INIS)

Gasik, P.

2017-01-01

A large Time Projection Chamber (TPC) is the main device for tracking and charged-particle identification in the ALICE experiment at the CERN LHC. After the second long shutdown in 2019–2020, the LHC will deliver Pb beams colliding at an interaction rate up to 50 kHz, which is about a factor of 100 above the present read-out rate of the TPC. To fully exploit the LHC potential the TPC will be upgraded based on the Gas Electron Multiplier (GEM) technology. A prototype of an ALICE TPC Outer Read-Out Chamber (OROC) was equipped with twelve large-size GEM foils as amplification stage to demonstrate the feasibility of replacing the current Multi Wire Proportional Chambers with the new technology. With a total area of ∼0.76 m 2 it is the largest GEM-based detector built to date. The GEM OROC was installed within a test field cage and commissioned with radioactive sources.

SU-8 as a material for lab-on-a-chip-based mass spectrometry.

Science.gov (United States)

Arscott, Steve

2014-10-07

This short review focuses on the application of SU-8 for the microchip-based approach to the miniaturization of mass spectrometry. Chip-based mass spectrometry will make the technology commonplace and bring benefits such as lower costs and autonomy. The chip-based miniaturization of mass spectrometry necessitates the use of new materials which are compatible with top-down fabrication involving both planar and non-planar processes. In this context, SU-8 is a very versatile epoxy-based, negative tone resist which is sensitive to ultraviolet radiation, X-rays and electron beam exposure. It has a very wide thickness range, from nanometres to millimetres, enabling the formation of mechanically rigid, very high aspect ratio, vertical, narrow width structures required to form microfluidic slots and channels for laboratory-on-a-chip design. It is also relatively chemically resistant and biologically compatible in terms of the liquid solutions used for mass spectrometry. This review looks at the impact and potential of SU-8 on the different parts of chip-based mass spectrometry - pre-treatment, ionization processes, and ion sorting and detection.

Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

Energy Technology Data Exchange (ETDEWEB)

Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

2011-02-01

The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

International Nuclear Information System (INIS)

Thil, Ch.; Baron, A.Q.R.; Fajardo, P.; Fischer, P.; Graafsma, H.; Rueffer, R.

2011-01-01

The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm 2 active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280μmx280μm size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

An AES chip with DPA resistance using hardware-based random order execution

International Nuclear Information System (INIS)

Yu Bo; Li Xiangyu; Chen Cong; Sun Yihe; Wu Liji; Zhang Xiangmin

2012-01-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm 2 . A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance. (semiconductor integrated circuits)

An AES chip with DPA resistance using hardware-based random order execution

Science.gov (United States)

Bo, Yu; Xiangyu, Li; Cong, Chen; Yihe, Sun; Liji, Wu; Xiangmin, Zhang

2012-06-01

This paper presents an AES (advanced encryption standard) chip that combats differential power analysis (DPA) side-channel attack through hardware-based random order execution. Both decryption and encryption procedures of an AES are implemented on the chip. A fine-grained dataflow architecture is proposed, which dynamically exploits intrinsic byte-level independence in the algorithm. A novel circuit called an HMF (Hold-Match-Fetch) unit is proposed for random control, which randomly sets execution orders for concurrent operations. The AES chip was manufactured in SMIC 0.18 μm technology. The average energy for encrypting one group of plain texts (128 bits secrete keys) is 19 nJ. The core area is 0.43 mm2. A sophisticated experimental setup was built to test the DPA resistance. Measurement-based experimental results show that one byte of a secret key cannot be disclosed from our chip under random mode after 64000 power traces were used in the DPA attack. Compared with the corresponding fixed order execution, the hardware based random order execution is improved by at least 21 times the DPA resistance.

On-chip plasmon-induced transparency based on plasmonic coupled nanocavities.

Science.gov (United States)

Zhu, Yu; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

2014-01-17

On-chip plasmon-induced transparency offers the possibility of realization of ultrahigh-speed information processing chips. Unfortunately, little experimental progress has been made to date because it is difficult to obtain on-chip plasmon-induced transparency using only a single meta-molecule in plasmonic circuits. Here, we report a simple and efficient strategy to realize on-chip plasmon-induced transparency in a nanoscale U-shaped plasmonic waveguide side-coupled nanocavity pair. High tunability in the transparency window is achieved by covering the pair with different organic polymer layers. It is possible to realize ultrafast all-optical tunability based on pump light-induced refractive index change of a graphene cover layer. Compared with previous reports, the overall feature size of the plasmonic nanostructure is reduced by more than three orders of magnitude, while ultrahigh tunability of the transparency window is maintained. This work also provides a superior platform for the study of the various physical effects and phenomena of nonlinear optics and quantum optics.

Ceramic thermal wind sensor based on advanced direct chip attaching package

International Nuclear Information System (INIS)

Zhou Lin; Qin Ming; Chen Shengqi; Chen Bei

2014-01-01

An advanced direct chip attaching packaged two-dimensional ceramic thermal wind sensor is studied. The thermal wind sensor chip is fabricated by metal lift-off processes on the ceramic substrate. An advanced direct chip attaching (DCA) packaging is adopted and this new packaged method simplifies the processes of packaging further. Simulations of the advanced DCA packaged sensor based on computational fluid dynamics (CFD) model show the sensor can detect wind speed and direction effectively. The wind tunnel testing results show the advanced DCA packaged sensor can detect the wind direction from 0° to 360° and wind speed from 0 to 20 m/s with the error less than 0.5 m/s. The nonlinear fitting based least square method in Matlab is used to analyze the performance of the sensor. (semiconductor devices)

SiPM based readout system for PbWO{sub 4} crystals

Energy Technology Data Exchange (ETDEWEB)

Berra, A., E-mail: alessandro.berra@gmail.com [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11-22100 Como (Italy); Bolognini, D.; Bonfanti, S. [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11-22100 Como (Italy); Bonvicini, V. [INFN sezione di Trieste (Italy); Lietti, D. [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11-22100 Como (Italy); Penzo, A. [INFN sezione di Trieste (Italy); Prest, M.; Stoppani, L. [Università degli Studi dell' Insubria e INFN sezione di Milano Bicocca, Via Valleggio, 11-22100 Como (Italy); Vallazza, E. [INFN sezione di Trieste (Italy)

2013-08-01

Silicon PhotoMultipliers (SiPMs) consist of a matrix of small passively quenched silicon avalanche photodiodes operated in limited Geiger-mode (GM-APDs) and read out in parallel from a common output node. Each pixel (with a typical size in the 20–100 μm range) gives the same current response when hit by a photon; the SiPM output signal is the sum of the signals of all the pixels, which depends on the light intensity. The main advantages of SiPMs with respect to photomultiplier tubes (PMTs) are essentially the small dimensions, the insensitivity to magnetic fields and a low bias voltage. This contribution presents the performance of a SiPM based readout system for crystal calorimeters developed in the framework of the FACTOR/TWICE collaboration. The SiPM used for the test is a new device produced by FBK-irst which consists in a matrix of four sensors embedded in the same silicon substrate, called QUAD. The SiPM has been coupled to a lead tungstate crystal, an early-prototype version of the crystals developed for the electromagnetic calorimeter of the CMS experiment. New tests are foreseen using a complete module consisting of nine crystals, each one readout by two QUADs.

LHCb: Fast Readout Control for the upgraded readout architecture of the LHCb experiment at CERN

CERN Multimedia

Alessio, F

2013-01-01

The LHCb experiment at CERN has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity with an upgraded LHCb detector. As a consequence, the various LHCb sub-systems in the readout architecture will be upgraded to cope with higher sub-detector occupancies, higher rate, and higher readout load. The new architecture, new functionalities, and the first hardware implementation of a new LHCb Readout Control system (commonly referred to as S-TFC) for the upgraded LHCb experiment is here presented. Our attention is focused in describing solutions for the distribution of clock and timing information to control the entire upgraded readout architecture by profiting of a bidirectional optical network and powerful FPGAs, including a real-time mechanism to synchronize the entire system. Solutions and implementations are presented, together with first results on the simulation and the validation of the system.

Microfluidics on liquid handling stations (μF-on-LHS): an industry compatible chip interface between microfluidics and automated liquid handling stations.

Science.gov (United States)

Waldbaur, Ansgar; Kittelmann, Jörg; Radtke, Carsten P; Hubbuch, Jürgen; Rapp, Bastian E

2013-06-21

We describe a generic microfluidic interface design that allows the connection of microfluidic chips to established industrial liquid handling stations (LHS). A molding tool has been designed that allows fabrication of low-cost disposable polydimethylsiloxane (PDMS) chips with interfaces that provide convenient and reversible connection of the microfluidic chip to industrial LHS. The concept allows complete freedom of design for the microfluidic chip itself. In this setup all peripheral fluidic components (such as valves and pumps) usually required for microfluidic experiments are provided by the LHS. Experiments (including readout) can be carried out fully automated using the hardware and software provided by LHS manufacturer. Our approach uses a chip interface that is compatible with widely used and industrially established LHS which is a significant advancement towards near-industrial experimental design in microfluidics and will greatly facilitate the acceptance and translation of microfluidics technology in industry.

Readout ASIC for ILC-FPCCD vertex detector

International Nuclear Information System (INIS)

Takubo, Yosuke; Miyamoto, Akiya; Ikeda, Hirokazu; Yamamoto, Hitoshi; Itagaki, Kennosuke; Nagamine, Tadashi; Sugimoto, Yasuhiro

2010-01-01

The concept of FPCCD (Fine Pixel CCD) whose pixel size is 5x5μm 2 has been proposed as vertex detector at ILC. Since FPCCD has 128 x20,000 pixels in one readout channel, its readout poses a considerable challenge. We have developed a prototype of readout ASIC to readout the large number of pixels during the inter-train gap of the ILC beam. In this paper, we report the design and performance of the readout ASIC.

On-chip nanofluidic integration of acoustic sensors towards high Q in liquid

Science.gov (United States)

Liang, Ji; Liu, Zifeng; Zhang, Hongxiang; Liu, Bohua; Zhang, Menglun; Zhang, Hao; Pang, Wei

2017-11-01

This paper reports an on-chip acoustic sensor comprising a piston-mode film bulk acoustic resonator and a monolithically integrated nanochannel. The resonator with the channel exhibits a resonance frequency (f) of 2.5 GHz and a quality (Q) factor of 436 in deionized water. The f × Q product is as high as 1.1 × 1012, which is the highest among all the acoustic wave sensors in the liquid phase. The sensor consumes 2 pl liquid volume and thus greatly saves the precious assays in biomedical testing. The Q factor is investigated, and real-time viscosity tests of glucose solution are demonstrated. The highly miniaturized and integrated sensor is capable to be arrayed with readout-circuitry, which opens an avenue for portable applications and lab-on-chip systems.

A volumetric meter chip for point-of-care quantitative detection of bovine catalase for food safety control

International Nuclear Information System (INIS)

Cui, Xingye; Hu, Jie; Choi, Jane Ru; Huang, Yalin; Wang, Xuemin; Lu, Tian Jian; Xu, Feng

2016-01-01

A volumetric meter chip was developed for quantitative point-of-care (POC) analysis of bovine catalase, a bioindicator of bovine mastitis, in milk samples. The meter chip displays multiplexed quantitative results by presenting the distance of ink bar advancement that is detectable by the naked eye. The meter chip comprises a poly(methyl methacrylate) (PMMA) layer, a double-sided adhesive (DSA) layer and a glass slide layer fabricated by the laser-etching method, which is typically simple, rapid (∼3 min per chip), and cost effective (∼$0.2 per chip). Specially designed “U shape” reaction cells are covered by an adhesive tape that serves as an on-off switch, enabling the simple operation of the assay. As a proof of concept, we employed the developed meter chip for the quantification of bovine catalase in raw milk samples to detect catalase concentrations as low as 20 μg/mL. The meter chip has great potential to detect various target analytes for a wide range of POC applications. - Highlights: • The meter chip is a standalone point-of-care diagnostic tool with visible readouts of quantification results. • A fast and low cost fabrication protocol (~3 min and ~$0.2 per chip) of meter chip was proposed. • The chip may hold the potential for rapid scaning of bovine mastitis in cattle farms for food safety control.

A volumetric meter chip for point-of-care quantitative detection of bovine catalase for food safety control

Energy Technology Data Exchange (ETDEWEB)

Cui, Xingye; Hu, Jie; Choi, Jane Ru; Huang, Yalin; Wang, Xuemin [The Key Laboratory of Biomedical Information Engineering of Ministry of Education, School of Life Science and Technology, Xi' an Jiaotong University, Xi' an, 710049 (China); Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China); Lu, Tian Jian, E-mail: tjlu@mail.xjtu.edu.cn [Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China); Xu, Feng, E-mail: fengxu@mail.xjtu.edu.cn [The Key Laboratory of Biomedical Information Engineering of Ministry of Education, School of Life Science and Technology, Xi' an Jiaotong University, Xi' an, 710049 (China); Bioinspired Engineering and Biomechanics Center (BEBC), Xi' an Jiaotong University, Xi' an, 710049 (China)

2016-09-07

A volumetric meter chip was developed for quantitative point-of-care (POC) analysis of bovine catalase, a bioindicator of bovine mastitis, in milk samples. The meter chip displays multiplexed quantitative results by presenting the distance of ink bar advancement that is detectable by the naked eye. The meter chip comprises a poly(methyl methacrylate) (PMMA) layer, a double-sided adhesive (DSA) layer and a glass slide layer fabricated by the laser-etching method, which is typically simple, rapid (∼3 min per chip), and cost effective (∼$0.2 per chip). Specially designed “U shape” reaction cells are covered by an adhesive tape that serves as an on-off switch, enabling the simple operation of the assay. As a proof of concept, we employed the developed meter chip for the quantification of bovine catalase in raw milk samples to detect catalase concentrations as low as 20 μg/mL. The meter chip has great potential to detect various target analytes for a wide range of POC applications. - Highlights: • The meter chip is a standalone point-of-care diagnostic tool with visible readouts of quantification results. • A fast and low cost fabrication protocol (~3 min and ~$0.2 per chip) of meter chip was proposed. • The chip may hold the potential for rapid scaning of bovine mastitis in cattle farms for food safety control.

Manufacture of a Polyaniline Nanofiber Ammonia Sensor Integrated with a Readout Circuit Using the CMOS-MEMS Technique

Directory of Open Access Journals (Sweden)

Chyan-Chyi Wu

2009-02-01

Full Text Available This study presents the fabrication of a polyaniline nanofiber ammonia sensor integrated with a readout circuit on a chip using the commercial 0.35 mm complementary metal oxide semiconductor (CMOS process and a post-process. The micro ammonia sensor consists of a sensing resistor and an ammonia sensing film. Polyaniline prepared by a chemical polymerization method was adopted as the ammonia sensing film. The fabrication of the ammonia sensor needs a post-process to etch the sacrificial layers and to expose the sensing resistor, and then the ammonia sensing film is coated on the sensing resistor. The ammonia sensor, which is of resistive type, changes its resistance when the sensing film adsorbs or desorbs ammonia gas. A readout circuit is employed to convert the resistance of the ammonia sensor into the voltage output. Experimental results show that the sensitivity of the ammonia sensor is about 0.88 mV/ppm at room temperature

Design of fundamental building blocks for fast binary readout CMOS sensors used in high-energy physics experiments

Energy Technology Data Exchange (ETDEWEB)

Degerli, Yavuz [CEA Saclay, IRFU/SEDI, 91191 Gif-sur-Yvette Cedex (France)], E-mail: degerli@cea.fr

2009-04-21

In this paper, design details of key building blocks for fast binary readout CMOS monolithic active pixel sensors developed for charged particle detection are presented. Firstly, an all-NMOS pixel architecture with in-pixel amplification and reset noise suppression which allows fast readout is presented. This pixel achieves high charge-to-voltage conversion factors (CVF) using a few number of transistors inside the pixel. It uses a pre-amplifying stage close to the detector and a simple double sampling (DS) circuitry to store the reset level of the detector. The DS removes the offset mismatches of amplifiers and the reset noise of the detector. Offset mismatches of the source follower are also corrected by a second column-level DS stage. The second important building block of these sensors, a low-power auto-zeroed column-level discriminator, is also presented. These two blocks transform the charge of the impinging particle into binary data. Finally, some experimental results obtained on CMOS chips designed using these blocks are presented.

Four-channel readout ASIC for silicon pad detectors

International Nuclear Information System (INIS)

Baturitsky, M.A.; Zamiatin, N.I.

2000-01-01

A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e - +18e - /pF at 30 ns peaking time for detector capacitance up to C d =400 pF. Rise time is 8 ns at input capacitance C d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

Pulse mode actuation-readout system based on MEMS resonator for liquid sensing

DEFF Research Database (Denmark)

Tang, Meng; Cagliani, Alberto; Davis, Zachary James

2014-01-01

A MEMS (Micro-Electro-Mechanical Systems) bulk disk resonator is applied for mass sensing under its dynamic mode. The classical readout circuitry involves sophisticated feedback loop and feedthrough compensation. We propose a simple straightforward non-loop pulse mode actuation and capacitive...... readout scheme. In order to verify its feasibility in liquid bio-chemical sensing environment, an experimental measurement is conducted with humidity sensing application. The measured resonant frequency changes 60kHz of 67.7MHz with a humidity change of 0~80%....

Embedded Processor Based Automatic Temperature Control of VLSI Chips

Directory of Open Access Journals (Sweden)

Narasimha Murthy Yayavaram

2009-01-01

Full Text Available This paper presents embedded processor based automatic temperature control of VLSI chips, using temperature sensor LM35 and ARM processor LPC2378. Due to the very high packing density, VLSI chips get heated very soon and if not cooled properly, the performance is very much affected. In the present work, the sensor which is kept very near proximity to the IC will sense the temperature and the speed of the fan arranged near to the IC is controlled based on the PWM signal generated by the ARM processor. A buzzer is also provided with the hardware, to indicate either the failure of the fan or overheating of the IC. The entire process is achieved by developing a suitable embedded C program.

18k Channels single photon counting readout circuit for hybrid pixel detector

International Nuclear Information System (INIS)

Maj, P.; Grybos, P.; Szczygiel, R.; Zoladz, M.; Sakumura, T.; Tsuji, Y.

2013-01-01

We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm×20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96×192 pixels with 100 μm×100 μm pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 μW/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 μV/e − and the equivalent noise charge is 168 e − rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

18k Channels single photon counting readout circuit for hybrid pixel detector

Energy Technology Data Exchange (ETDEWEB)

Maj, P., E-mail: piotr.maj@agh.edu.pl [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Grybos, P.; Szczygiel, R.; Zoladz, M. [AGH University of Science and Technology, Department of Measurements and Electronics, Al. Mickiewicza 30, 30-059 Krakow (Poland); Sakumura, T.; Tsuji, Y. [X-ray Analysis Division, Rigaku Corporation, Matsubara, Akishima, Tokyo 196-8666 (Japan)

2013-01-01

We have performed measurements of an integrated circuit named PXD18k designed for hybrid pixel semiconductor detectors used in X-ray imaging applications. The PXD18k integrated circuit, fabricated in CMOS 180 nm technology, has dimensions of 9.64 mm Multiplication-Sign 20 mm and contains approximately 26 million transistors. The core of the IC is a matrix of 96 Multiplication-Sign 192 pixels with 100 {mu}m Multiplication-Sign 100 {mu}m pixel size. Each pixel works in a single photon counting mode. A single pixel contains two charge sensitive amplifiers with Krummenacher feedback scheme, two shapers, two discriminators (with independent thresholds A and B) and two 16-bit ripple counters. The data are read out via eight low voltage differential signaling (LVDS) outputs with 100 Mbps rate. The power consumption is dominated by analog blocks and it is about 23 {mu}W/pixel. The effective peaking time at the discriminator input is 30 ns and is mainly determined by the time constants of the charge sensitive amplifier (CSA). The gain is equal to 42.5 {mu}V/e{sup -} and the equivalent noise charge is 168 e{sup -} rms (with bump-bonded silicon pixel detector). Thanks to the use of trim DACs in each pixel, the effective threshold spread at the discriminator input is only 1.79 mV. The dead time of the front end electronics for a standard setting is 172 ns (paralyzable model). In the standard readout mode (when the data collection time is separated from the time necessary to readout data from the chip) the PXD18k IC works with two energy thresholds per pixel. The PXD18k can also be operated in the continuous readout mode (with a zero dead time) where one can select the number of bits readout from each pixel to optimize the PXD18k frame rate. For example, for reading out 16 bits/pixel the frame rate is 2.7 kHz and for 4 bits/pixel it rises to 7.1 kHz.

A new readout control system for the LHCb upgrade at CERN

International Nuclear Information System (INIS)

Alessio, F; Jacobsson, R

2012-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire readout architecture will be upgraded in order to cope with higher sub-detector occupancies, higher rate and higher network load. In this paper, we describe the architecture, functionalities and a first hardware implementation of a new fast Readout Control system for the LHCb upgrade, which will be entirely based on FPGAs and bi-directional links. We also outline the real-time implementations of the new Readout Control system, together with solutions on how to handle the synchronous distribution of timing and synchronous information to the complex upgraded LHCb readout architecture. One section will also be dedicated to the control and usage of the newly developed CERN GBT chipset to transmit fast and slow control commands to the upgraded LHCb Front-End electronics. At the end, we outline the plans for the deployment of the system in the global LHCb upgrade readout architecture.

A Sol-gel Integrated Dual-readout Microarray Platform for Quantification and Identification of Prostate-specific Antigen.

Science.gov (United States)

Lee, SangWook; Lee, Jong Hyun; Kwon, Hyuck Gi; Laurell, Thomas; Jeong, Ok Chan; Kim, Soyoun

2018-01-01

Here, we report a sol-gel integrated affinity microarray for on-chip matrix-assisted laser desorption/ionization time-of-flight mass spectrometry (MALDI-TOF-MS) that enables capture and identification of prostate?specific antigen (PSA) in samples. An anti-PSA antibody (H117) was mixed with a sol?gel, and the mixture was spotted onto a porous silicon (pSi) surface without additional surface modifications. The antibody easily penetrates the sol-gel macropore fluidic network structure, making possible high affinities. To assess the capture affinity of the platform, we performed a direct assay using fluorescein isothiocyanate-labeled PSA. Pure PSA was subjected to on-chip MALDI-TOF-MS analysis, yielding three clear mass peptide peaks (m/z = 1272, 1407, and 1872). The sol-gel microarray platform enables dual readout of PSA both fluorometric and MALDI-TOF MS analysis in biological samples. Here we report a useful method for a means for discovery of biomarkers in complex body fluids.

A reconfigurable image tube using an external electronic image readout

Science.gov (United States)

Lapington, J. S.; Howorth, J. R.; Milnes, J. S.

2005-08-01

We have designed and built a sealed tube microchannel plate (MCP) intensifier for optical/NUV photon counting applications suitable for 18, 25 and 40 mm diameter formats. The intensifier uses an electronic image readout to provide direct conversion of event position into electronic signals, without the drawbacks associated with phosphor screens and subsequent optical detection. The Image Charge technique is used to remove the readout from the intensifier vacuum enclosure, obviating the requirement for additional electrical vacuum feedthroughs and for the readout pattern to be UHV compatible. The charge signal from an MCP intensifier is capacitively coupled via a thin dielectric vacuum window to the electronic image readout, which is external to the sealed intensifier tube. The readout pattern is a separate item held in proximity to the dielectric window and can be easily detached, making the system easily reconfigurable. Since the readout pattern detects induced charge and is external to the tube, it can be constructed as a multilayer, eliminating the requirement for narrow insulator gaps and allowing it to be constructed using standard PCB manufacturing tolerances. We describe two readout patterns, the tetra wedge anode (TWA), an optimized 4 electrode device similar to the wedge and strip anode (WSA) but with a factor 2 improvement in resolution, and an 8 channel high speed 50 ohm device, both manufactured as multilayer PCBs. We present results of the detector imaging performance, image resolution, linearity and stability, and discuss the development of an integrated readout and electronics device based on these designs.

The Belle II SVD data readout system

Energy Technology Data Exchange (ETDEWEB)

Thalmeier, R., E-mail: Richard.Thalmeier@oeaw.ac.at [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Adamczyk, K. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Aihara, H. [Department of Physics, University of Tokyo, Tokyo 113-0033 (Japan); Angelini, C. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Aziz, T.; Babu, V. [Tata Institute of Fundamental Research, Mumbai 400005 (India); Bacher, S. [H. Niewodniczanski Institute of Nuclear Physics, Krakow 31-342 (Poland); Bahinipati, S. [Indian Institute of Technology Bhubaneswar, Satya Nagar (India); Barberio, E.; Baroncelli, Ti.; Baroncelli, To. [School of Physics, University of Melbourne, Melbourne, Victoria 3010 (Australia); Basith, A.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Batignani, G. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bauer, A. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Behera, P.K. [Indian Institute of Technology Madras, Chennai 600036 (India); Bergauer, T. [Institute of High Energy Physics, Austrian Academy of Sciences, 1050 Vienna (Austria); Bettarini, S. [Dipartimento di Fisica, Universita’ di Pisa, I-56127 Pisa (Italy); INFN Sezione di Pisa, I-56127 Pisa (Italy); Bhuyan, B. [Indian Institute of Technolog y Guwahati, Assam 781039 (India); Bilka, T. [Faculty of Mathematics and Physics, Charles University, 12116 Prague (Czech Republic); Bosi, F. [INFN Sezione di Pisa, I-56127 Pisa (Italy); and others

2017-02-11

The Belle II Experiment at the High Energy Accelerator Research Organization (KEK) in Tsukuba, Japan, will explore the asymmetry between matter and antimatter and search for new physics beyond the standard model. 172 double-sided silicon strip detectors are arranged cylindrically in four layers around the collision point to be part of a system which measures the tracks of the collision products of electrons and positrons. A total of 1748 radiation-hard APV25 chips read out 128 silicon strips each and send the analog signals by time-division multiplexing out of the radiation zone to 48 Flash Analog Digital Converter Modules (FADC). Each of them applies processing to the data; for example, it uses a digital finite impulse response filter to compensate line signal distortions, and it extracts the peak timing and amplitude from a set of several data points for each hit, using a neural network. We present an overview of the SVD data readout system, along with front-end electronics, cabling, power supplies and data processing.

Infrared readout electronics; Proceedings of the Meeting, Orlando, FL, Apr. 21, 22, 1992

Science.gov (United States)

Fossum, Eric R.

The present volume on IR readout electronics discusses cryogenic readout using silicon devices, cryogenic readout using III-V and LTS devices, multiplexers for higher temperatures, and focal-plane signal processing electronics. Attention is given to the optimization of cryogenic CMOS processes for sub-10-K applications, cryogenic measurements of aerojet GaAs n-JFETs, inP-based heterostructure device technology for ultracold readout applications, and a three-terminal semiconductor-superconductor transimpedance amplifier. Topics addressed include unfulfilled needs in IR astronomy focal-plane readout electronics, IR readout integrated circuit technology for tactical missile systems, and radiation-hardened 10-bit A/D for FPA signal processing. Also discussed are the implementation of a noise reduction circuit for spaceflight IR spectrometers, a real-time processor for staring receivers, and a fiber-optic link design for INMOS transputers.

Functional tests of 2S modules for the CMS Phase-2 Tracker Upgrade with a MicroTCA-based readout system

CERN Document Server

Preuten, Marius; Klein, Katja; Lipinski, Martin; Rauch, Max; Feld, Lutz

2017-01-01

First full size 2S module prototypes for the CMS Phase-2 Outer Tracker Upgrade have been assembled. With two sensors of realistic dimensions and 16 CBC2 readout ASICs on two front-end hybrids, the characteristics of these novel and complex objects can be studied.A MicroTCA based readout system was developed to test multiple front-end hybrids simultaneously. Therefore the concurrent information of the full module can be used for noise and signal studies.

Amorphous silicon based particle detectors

OpenAIRE

Wyrsch, N.; Franco, A.; Riesen, Y.; Despeisse, M.; Dunand, S.; Powolny, F.; Jarron, P.; Ballif, C.

2012-01-01

Radiation hard monolithic particle sensors can be fabricated by a vertical integration of amorphous silicon particle sensors on top of CMOS readout chip. Two types of such particle sensors are presented here using either thick diodes or microchannel plates. The first type based on amorphous silicon diodes exhibits high spatial resolution due to the short lateral carrier collection. Combination of an amorphous silicon thick diode with microstrip detector geometries permits to achieve micromete...

Cantilever-based micro-particle filter with simultaneous single particle detection

DEFF Research Database (Denmark)

Noeth, Nadine-Nicole; Keller, Stephan Sylvest; Boisen, Anja

2011-01-01

Currently, separation of whole blood samples on lab-on-a-chip systems is achieved via filters followed by analysis of the filtered matter such as counting of blood cells. Here, a micro-chip based on cantilever technology is developed, which enables simultaneous filtration and counting of micro-particles...... from a liquid. A hole-array is integrated into a micro-cantilever, which is inserted into a microfluidic channel perpendicular to the flow. A metal pad at the apex of the cantilever enables an optical read-out of the deflection of the cantilever. When a micro-particle is too large to pass a hole...

Polymeric cantilever-based biosensors with integrated readout

DEFF Research Database (Denmark)

Johansson, Alicia; Blagoi, Gabriela; Boisen, Anja

2006-01-01

The authors present an SU-8 cantilever chip with integrated piezoresistors for detection of surface stress changes due to adsorption of biomolecules on the cantilever surface. Mercaptohexanol is used as a model biomolecule to study molecular interactions with Au-coated SU-8 cantilevers and surfac...

Self-driven filter-based blood plasma separator microfluidic chip for point-of-care testing

International Nuclear Information System (INIS)

Madadi, Hojjat; Casals-Terré, Jasmina; Mohammadi, Mahdi

2015-01-01

There is currently a growing need for lab-on-a-chip devices for use in clinical analysis and diagnostics, especially in the area of patient care. The first step in most blood assays is plasma extraction from whole blood. This paper presents a novel, self-driven blood plasma separation microfluidic chip, which can extract more than 0.1 μl plasma from a single droplet of undiluted fresh human blood (∼5 μl). This volume of blood plasma is extracted from whole blood with high purity (more than 98%) in a reasonable time frame (3 to 5 min), and without the need for any external force. This would be the first step towards the realization of a single-use, self-blood test that does not require any external force or power source to deliver and analyze a fresh whole-blood sample, in contrast to the existing time-consuming conventional blood analysis. The prototypes are manufactured in polydimethylsiloxane that has been modified with a strong nonionic surfactant (Silwet L-77) to achieve hydrophilic behavior. The main advantage of this microfluidic chip design is the clogging delay in the filtration area, which results in an increased amount of extracted plasma (0.1 μl). Moreover, the plasma can be collected in one or more 10 μm-deep channels to facilitate the detection and readout of multiple blood assays. This high volume of extracted plasma is achieved thanks to a novel design that combines maximum pumping efficiency without disturbing the red blood cells’ trajectory through the use of different hydrodynamic principles, such as a constriction effect and a symmetrical filtration mode. To demonstrate the microfluidic chip’s functionality, we designed and fabricated a novel hybrid microdevice that exhibits the benefits of both microfluidics and lateral flow immunochromatographic tests. The performance of the presented hybrid microdevice is validated using rapid detection of thyroid stimulating hormone within a single droplet of whole blood. (paper)

A Distance Detector with a Strip Magnetic MOSFET and Readout Circuit.

Science.gov (United States)

Sung, Guo-Ming; Lin, Wen-Sheng; Wang, Hsing-Kuang

2017-01-10

This paper presents a distance detector composed of two separated metal-oxide semiconductor field-effect transistors (MOSFETs), a differential polysilicon cross-shaped Hall plate (CSHP), and a readout circuit. The distance detector was fabricated using 0.18 μm 1P6M Complementary Metal-Oxide Semiconductor (CMOS) technology to sense the magnetic induction perpendicular to the chip surface. The differential polysilicon CSHP enabled the magnetic device to not only increase the magnetosensitivity but also eliminate the offset voltage generated because of device mismatch and Lorentz force. Two MOSFETs generated two drain currents with a quadratic function of the differential Hall voltages at CSHP. A readout circuit-composed of a current-to-voltage converter, a low-pass filter, and a difference amplifier-was designed to amplify the current difference between two drains of MOSFETs. Measurements revealed that the electrostatic discharge (ESD) could be eliminated from the distance sensor by grounding it to earth; however, the sensor could be desensitized by ESD in the absence of grounding. The magnetic influence can be ignored if the magnetic body (human) stays far from the magnetic sensor, and the measuring system is grounded to earth by using the ESD wrist strap (Strap E-GND). Both 'no grounding' and 'grounding to power supply' conditions were unsuitable for measuring the induced Hall voltage.

Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

de La Taille, C

2008-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

Single-Readout High-Density Memristor Crossbar

KAUST Repository

Zidan, M. A.

2016-01-07

High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure is both its principal advantage and the source of undesired sneak-paths of current. This parasitic current could consume an enormous amount of energy and ruin the readout process. We introduce new adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer-memory system to address the sneak-paths problem. The proposed methods require a single memory access per pixel for an array readout. Besides, the memristive crossbar consumes an order of magnitude less power than state-of-the-art readout techniques.

Single-Readout High-Density Memristor Crossbar

KAUST Repository

Zidan, M. A.; Omran, Hesham; Naous, Rawan; Salem, Ahmed Sultan; Fahmy, H. A. H.; Lu, W. D.; Salama, Khaled N.

2016-01-01

High-density memristor-crossbar architecture is a very promising technology for future computing systems. The simplicity of the gateless-crossbar structure is both its principal advantage and the source of undesired sneak-paths of current. This parasitic current could consume an enormous amount of energy and ruin the readout process. We introduce new adaptive-threshold readout techniques that utilize the locality and hierarchy properties of the computer-memory system to address the sneak-paths problem. The proposed methods require a single memory access per pixel for an array readout. Besides, the memristive crossbar consumes an order of magnitude less power than state-of-the-art readout techniques.

The ALICE Silicon Pixel Detector System (SPD)

CERN Document Server

Kluge, A; Antinori, Federico; Burns, M; Cali, I A; Campbell, M; Caselle, M; Ceresa, S; Dima, R; Elias, D; Fabris, D; Krivda, Marian; Librizzi, F; Manzari, Vito; Morel, M; Moretto, Sandra; Osmic, F; Pappalardo, G S; Pepato, Adriano; Pulvirenti, A; Riedler, P; Riggi, F; Santoro, R; Stefanini, G; Torcato De Matos, C; Turrisi, R; Tydesjo, H; Viesti, G; PH-EP

2007-01-01

The ALICE silicon pixel detector (SPD) comprises the two innermost layers of the ALICE inner tracker system. The SPD includes 120 detector modules (half-staves) each consisting of 10 ALICE pixel chips bump bonded to two silicon sensors and one multi-chip read-out module. Each pixel chip contains 8192 active cells, so that the total number of pixel cells in the SPD is ≈ 107. The on-detector read-out is based on a multi-chip-module containing 4 ASICs and an optical transceiver module. The constraints on material budget and detector module dimensions are very demanding.

A digital Front-End and Readout MIcrosystem for calorimetry at LHC

CERN Multimedia

2002-01-01

% RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

A CMOS smart temperature and humidity sensor with combined readout.

Science.gov (United States)

Eder, Clemens; Valente, Virgilio; Donaldson, Nick; Demosthenous, Andreas

2014-09-16

A fully-integrated complementary metal-oxide semiconductor (CMOS) sensor for combined temperature and humidity measurements is presented. The main purpose of the device is to monitor the hermeticity of micro-packages for implanted integrated circuits and to ensure their safe operation by monitoring the operating temperature and humidity on-chip. The smart sensor has two modes of operation, in which either the temperature or humidity is converted into a digital code representing a frequency ratio between two oscillators. This ratio is determined by the ratios of the timing capacitances and bias currents in both oscillators. The reference oscillator is biased by a current whose temperature dependency is complementary to the proportional to absolute temperature (PTAT) current. For the temperature measurement, this results in an exceptional normalized sensitivity of about 0.77%/°C at the accepted expense of reduced linearity. The humidity sensor is a capacitor, whose value varies linearly with relative humidity (RH) with a normalized sensitivity of 0.055%/% RH. For comparison, two versions of the humidity sensor with an area of either 0.2 mm2 or 1.2 mm2 were fabricated in a commercial 0.18 μm CMOS process. The on-chip readout electronics operate from a 5 V power supply and consume a current of approximately 85 µA.

The GLUEchip: A custom VLSI chip for detectors readout and associative memories circuits

International Nuclear Information System (INIS)

Amendolia, S.R.; Galeotti, S.; Morsani, F.; Passuello, D.; Ristori, L.; Turini, N.

1993-01-01

An associative memory full-custom VLSI chip for pattern recognition has been designed and tested in the past years. It's the AMchip, that contains 128 patterns of 60 bits each. To expand the pattern capacity of an Associative Memory bank, the custom VLSI GLUEchip has been developed. The GLUEchip allows the interconnection of up to 16 AMchips or up to 16 GLUEchips: the resulting tree-like structure works like a single AMchip with an output pipelined structure and a pattern capacity increased by a factor 16 for each GLUEchip used

Tractor performance monitor based on a single-chip microcomputer

Energy Technology Data Exchange (ETDEWEB)

Bedri, A.R.; Marley, S.J.; Buchelle, W.F.; Smay, T.A.

1981-01-01

A tractor performance monitor based on a single-chip microcomputer was developed to measure ground speed, slip, fuel consumption (rate and total), total area, theoretical time, and total time. Transducers used are presented in detail. 5 refs.

CERNDxCTA counting mode chip

International Nuclear Information System (INIS)

Moraes, D.; Kaplon, J.; Nygard, E.

2008-01-01

This ASIC is a counting mode front-end electronic optimized for the readout of CdZnTe/CdTe and silicon sensors, for possible use in applications where the flux of ionizing radiation is high. The chip is implemented in 0.25 μm CMOS technology. The circuit comprises 128 channels equipped with a transimpedance amplifier followed by a gain shaper stage with 21 ns peaking time, two discriminators and two 18-bit counters. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. The amplifier shows a linear sensitivity of 118 mV/fC and an equivalent noise charge of about 711 e - , for a detector capacitance of 5 pF. Complete evaluation of the circuit is presented using electronic pulses and pixel detectors

A front end ASIC for the readout of the PMT in the KM3NeT detector

International Nuclear Information System (INIS)

Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

2010-01-01

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

Investigation of high resolution compact gamma camera module based on a continuous scintillation crystal using a novel charge division readout method

International Nuclear Information System (INIS)

Dai Qiusheng; Zhao Cuilan; Qi Yujin; Zhang Hualin

2010-01-01

The objective of this study is to investigate a high performance and lower cost compact gamma camera module for a multi-head small animal SPECT system. A compact camera module was developed using a thin Lutetium Oxyorthosilicate (LSO) scintillation crystal slice coupled to a Hamamatsu H8500 position sensitive photomultiplier tube (PSPMT). A two-stage charge division readout board based on a novel subtractive resistive readout with a truncated center-of-gravity (TCOG) positioning method was developed for the camera. The performance of the camera was evaluated using a flood 99m Tc source with a four-quadrant bar-mask phantom. The preliminary experimental results show that the image shrinkage problem associated with the conventional resistive readout can be effectively overcome by the novel subtractive resistive readout with an appropriate fraction subtraction factor. The response output area (ROA) of the camera shown in the flood image was improved up to 34%, and an intrinsic spatial resolution better than 2 mm of detector was achieved. In conclusion, the utilization of a continuous scintillation crystal and a flat-panel PSPMT equipped with a novel subtractive resistive readout is a feasible approach for developing a high performance and lower cost compact gamma camera. (authors)

A viable on-chip FPGA configuration memory scrubbing approach for CBM-ToF

Energy Technology Data Exchange (ETDEWEB)

Oancea, Andrei-Dumitru; Stuellein, Christian; Manz, Sebastian; Gebelein, Jano; Kebschull, Udo [Infrastruktur und Rechnersysteme in der Informationsverarbeitung (IRI), Goethe-Universitaet, Senckenberganlage 31, 60325 Frankfurt am Main (Germany); Collaboration: CBM-Collaboration

2015-07-01

The ToF Detector of the CBM Experiment will be equipped with FPGA-based read-out boards (ROBs). These ROBs will be operated in a radiation environment, and therefore need a mitigation mechanism against soft errors in the SRAM-based configuration memories of the FPGAs. The proposed approach combines intrinsic on-chip single upset correction with extrinsic selective frame scrubbing for multiple-bit upsets. The slow control is realized using the GBT-SCA, which is capable of handling interrupts. This enables the new approach of event-driven configuration frame correction. While conventional blind scrubbing leads to a continuous load on the control path, the selective frame scrubbing reduces this load to a minimum. For verification purposes, radiation tests with a proton beam were performed at COSY, Juelich. The occurred soft errors were classified into single and multiple- bit upsets, enabling an estimation of the rate at which extrinsic intervention is necessary.

An Integrated Circuit for Chip-Based Analysis of Enzyme Kinetics and Metabolite Quantification.

Science.gov (United States)

Cheah, Boon Chong; Macdonald, Alasdair Iain; Martin, Christopher; Streklas, Angelos J; Campbell, Gordon; Al-Rawhani, Mohammed A; Nemeth, Balazs; Grant, James P; Barrett, Michael P; Cumming, David R S

2016-06-01

We have created a novel chip-based diagnostic tools based upon quantification of metabolites using enzymes specific for their chemical conversion. Using this device we show for the first time that a solid-state circuit can be used to measure enzyme kinetics and calculate the Michaelis-Menten constant. Substrate concentration dependency of enzyme reaction rates is central to this aim. Ion-sensitive field effect transistors (ISFET) are excellent transducers for biosensing applications that are reliant upon enzyme assays, especially since they can be fabricated using mainstream microelectronics technology to ensure low unit cost, mass-manufacture, scaling to make many sensors and straightforward miniaturisation for use in point-of-care devices. Here, we describe an integrated ISFET array comprising 2(16) sensors. The device was fabricated with a complementary metal oxide semiconductor (CMOS) process. Unlike traditional CMOS ISFET sensors that use the Si3N4 passivation of the foundry for ion detection, the device reported here was processed with a layer of Ta2O5 that increased the detection sensitivity to 45 mV/pH unit at the sensor readout. The drift was reduced to 0.8 mV/hour with a linear pH response between pH 2-12. A high-speed instrumentation system capable of acquiring nearly 500 fps was developed to stream out the data. The device was then used to measure glucose concentration through the activity of hexokinase in the range of 0.05 mM-231 mM, encompassing glucose's physiological range in blood. Localised and temporal enzyme kinetics of hexokinase was studied in detail. These results present a roadmap towards a viable personal metabolome machine.

An automatic single channel analyzer based on single-chip microcomputer

International Nuclear Information System (INIS)

Yan Xuekun; Jia Mingchun; Zhang Yan; Liu Mingjian; Luo Ming

2008-01-01

The hardware and software of an automatic single channel analyzer based on AT89C51RC single-chip microcomputer is described in this paper. The equipment takes a method of channel-width-adjusting symmetrically, and makes use of single-chip microcomputer to control the two DAC0832 so as to adjust the discriminating threshold and channel-width automatically. As a result, the auto-measuring of the single channel analyzer is realized. Its circuit configuration is simple, and the uniformity of its channel-width is well, too. (authors)

Microwave multiplex readout for superconducting sensors

Energy Technology Data Exchange (ETDEWEB)

Ferri, E., E-mail: elena.ferri@mib.infn.it [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Becker, D.; Bennett, D. [NIST, Boulder, CO (United States); Faverzani, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Fowler, J.; Gard, J. [NIST, Boulder, CO (United States); Giachero, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Hays-Wehle, J.; Hilton, G. [NIST, Boulder, CO (United States); Maino, M. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Mates, J. [NIST, Boulder, CO (United States); Puiu, A.; Nucciotti, A. [Università Milano-Bicocca, Milan (Italy); INFN Sez. di Milano-Bicocca, Milan (Italy); Reintsema, C.; Schmidt, D.; Swetz, D.; Ullom, J.; Vale, L. [NIST, Boulder, CO (United States)

2016-07-11

The absolute neutrino mass scale is still an outstanding challenge in both particle physics and cosmology. The calorimetric measurement of the energy released in a nuclear beta decay is a powerful tool to determine the effective electron-neutrino mass. In the last years, the progress on low temperature detector technologies has allowed to design large scale experiments aiming at pushing down the sensitivity on the neutrino mass below 1 eV. Even with outstanding performances in both energy (~ eV on keV) and time resolution (~ 1 μs) on the single channel, a large number of detectors working in parallel is required to reach a sub-eV sensitivity. Microwave frequency domain readout is the best available technique to readout large array of low temperature detectors, such as Transition Edge Sensors (TESs) or Microwave Kinetic Inductance Detectors (MKIDs). In this way a multiplex factor of the order of thousands can be reached, limited only by the bandwidth of the available commercial fast digitizers. This microwave multiplexing system will be used to readout the HOLMES detectors, an array of 1000 microcalorimeters based on TES sensors in which the {sup 163}Ho will be implanted. HOLMES is a new experiment for measuring the electron neutrino mass by means of the electron capture (EC) decay of {sup 163}Ho. We present here the microwave frequency multiplex which will be used in the HOLMES experiment and the microwave frequency multiplex used to readout the MKID detectors developed in Milan as well.

On-chip RF-to-optical transducer

DEFF Research Database (Denmark)

Simonsen, Anders; Tsaturyan, Yeghishe; Seis, Yannick

2016-01-01

these diverse systems, plus technologies that utilize them, and the mature toolbox of optical techniques that routinely operates at the quantum limit. In a previous work [1], we demonstrated such a bridge by realizing simultaneous coupling between an electronic LC circuit and a quantum-noise limited optical...... noise temperatures far below the actual temperature of the mechanical element. On-chip integration of the electrical, mechanical and optical elements is necessary for an implementation of the transduction scheme that is viable for commercial applications. Reliable assembly of a strongly coupled...... electromechanical device, and inclusion of an optical cavity for enhanced optical readout, are key features of the new platform. Both can be achieved with standard cleanroom fabrication techniques. We will furthermore present ongoing work to couple our transducer to an RF or microwave antenna, for low...

dc readout experiment at the Caltech 40m prototype interferometer

International Nuclear Information System (INIS)

Ward, R L; Adhikari, R; Abbott, B; Abbott, R; Bork, R; Fricke, T; Heefner, J; Ivanov, A; Miyakawa, O; Smith, M; Taylor, R; Vass, S; Waldman, S; Weinstein, A; Barron, D; Frolov, V; McKenzie, K; Slagmolen, B

2008-01-01

The Laser Interferometer Gravitational Wave Observatory (LIGO) operates a 40m prototype interferometer on the Caltech campus. The primary mission of the prototype is to serve as an experimental testbed for upgrades to the LIGO interferometers and for gaining experience with advanced interferometric techniques, including detuned resonant sideband extraction (i.e. signal recycling) and dc readout (optical homodyne detection). The former technique will be employed in Advanced LIGO, and the latter in both Enhanced and Advanced LIGO. Using dc readout for gravitational wave signal extraction has several technical advantages, including reduced laser and oscillator noise couplings as well as reduced shot noise, when compared to the traditional rf readout technique (optical heterodyne detection) currently in use in large-scale ground-based interferometric gravitational wave detectors. The Caltech 40m laboratory is currently prototyping a dc readout system for a fully suspended interferometric gravitational wave detector. The system includes an optical filter cavity at the interferometer's output port, and the associated controls and optics to ensure that the filter cavity is optimally coupled to the interferometer. We present the results of measurements to characterize noise couplings in rf and dc readout using this system

Addressing On-Chip Power Converstion and Dissipation Issues in Many-Core System-on-a-Chip Based on Conventional Silicon and Emerging Nanotechnologies

Science.gov (United States)

Ashenafi, Emeshaw

Integrated circuits (ICs) are moving towards system-on-a-chip (SOC) designs. SOC allows various small and large electronic systems to be implemented in a single chip. This approach enables the miniaturization of design blocks that leads to high density transistor integration, faster response time, and lower fabrication costs. To reap the benefits of SOC and uphold the miniaturization of transistors, innovative power delivery and power dissipation management schemes are paramount. This dissertation focuses on on-chip integration of power delivery systems and managing power dissipation to increase the lifetime of energy storage elements. We explore this problem from two different angels: On-chip voltage regulators and power gating techniques. On-chip voltage regulators reduce parasitic effects, and allow faster and efficient power delivery for microprocessors. Power gating techniques, on the other hand, reduce the power loss incurred by circuit blocks during standby mode. Power dissipation (Ptotal = Pstatic and Pdynamic) in a complementary metal-oxide semiconductor (CMOS) circuit comes from two sources: static and dynamic. A quadratic dependency on the dynamic switching power and a more than linear dependency on static power as a form of gate leakage (subthreshold current) exist. To reduce dynamic power loss, the supply power should be reduced. A significant reduction in power dissipation occurs when portions of a microprocessor operate at a lower voltage level. This reduction in supply voltage is achieved via voltage regulators or converters. Voltage regulators are used to provide a stable power supply to the microprocessor. The conventional off-chip switching voltage regulator contains a passive floating inductor, which is difficult to be implemented inside the chip due to excessive power dissipation and parasitic effects. Additionally, the inductor takes a very large chip area while hampering the scaling process. These limitations make passive inductor based on-chip

Test-Access Planning and Test Scheduling for Embedded Core-Based System Chips

OpenAIRE

Goel, Sandeep Kumar

2005-01-01

Advances in the semiconductor process technology enable the creation of a complete system on one single die, the so-called system chip or SOC. To reduce time-to-market for large SOCs, reuse of pre-designed and pre-veried blocks called cores is employed. Like the design style, testing of SOCs can be best approached in a core-based fashion. In order to enable core-based test development, an embedded core should be isolated from its surrounding circuitry and electrical test access from chip pins...

Optical readout and control interface for the BTeV pixel vertex detector

CERN Document Server

Vergara-Limon, S; Sheaff, M; Vargas, M A

2002-01-01

Optical links will be used for sending data back and forth from the counting room to the detector in the data acquisition systems for future high energy physics experiments, including ATLAS and CMS in the LHC at CERN (Switzerland) and BTeV at Fermilab (USA). This is because they can be ultra-high speed and are relatively immune to electro-magnetic interference (EMI). The baseline design for the BTeV Pixel Vertex Detector includes two types of optical link, one to control and monitor and the other to read out the hit data from the multi-chip modules on each half-plane of the detector. The design and performance of the first prototype of the Optical Readout and Control Interface for the BTeV Pixel Vertex Detector is described.

A new avalanche photo diode based readout for the crystal barrel calorimeter

Energy Technology Data Exchange (ETDEWEB)

Urban, Martin [Helmholtz-Institut fuer Strahlen- und Kernphysik, Nussallee 14-16, 53115 Bonn (Germany); Collaboration: CBELSA/TAPS-Collaboration

2015-07-01

The CBELSA/TAPS experiment at ELSA has proven successful in the measurement of double polarization observables in meson photoproduction off protons and neutrons. To be able to measure purely neutral reactions on a polarized neutron target with high efficiency, the main calorimeter consisting of 1320 CsI(Tl) crystals has to be integrated into the first level trigger. Key requirement to achieve this goal is an exchange of the existing PIN photo diode by a new avalanche photo diode (APD) readout. The main advantage of the new readout system is that it will provide timing information which allows a fast trigger signal. The energy resolution will remain compatible to the previous system. Besides the development of automated test routines for the front end electronics, the characterization of all APDs was successfully accomplished in Bonn. After tests with a 3 x 3 CsI(Tl) crystal matrix at the tagged photon beam facilities at ELSA and MAMI the first half of the Crystal Barrel was upgraded in 2014. This talk shows the result of the latest test measurements including the gain stabilization of the new APD readout electronics and presents the progress of the ongoing upgrade.

The New APD Based Readout for the Crystal Barrel Calorimeter

International Nuclear Information System (INIS)

Urban, M; Honisch, Ch; Steinacher, M

2015-01-01

The CBELSA/TAPS experiment at ELSA measures double polarization observables in meson photoproduction off protons and neutrons. To be able to measure purely neutral reactions off polarized neutrons with high efficiency, the main calorimeter has to be integrated into the first level trigger. This requires to exchange the existing PIN photo diode by a new avalanche photo diode (APD) readout. The newly developed readout electronics will provide an energy resolution compatible to the previous set-up and a fast trigger signal down to 10 MeV energy deposit per crystal. After the successful final tests with a 3x3 CsI crystal matrix in Bonn at ELSA and in Mainz at MAMI all front-end electronics were produced in fall 2013. Automated test routines for the front-end electronics were developed and the characterization measurements of all APDs were successfully accomplished in Bonn. The project is supported by the Deutsche Forschungsgemeinschaft (SFB/TR16) and Schweizerischer Nationalfonds

Progress on the development of a detector mounted analog and digital readout system for the ATLAS TRT

CERN Document Server

Baxter, C; Dressnandt, N; Gay, C; Lundberg, B; Munar, A; Mayers, G; Newcomer, M; Van Berg, R; Williams, H H

2004-01-01

The 430,000 element ATLAS Transition Radiation straw tube Tracker (TRT) is divided into a central barrel tracker consisting of 104,000 axially mounted straws and two radially arranged end caps on either side of the barrel with 160,000 straws each. To achieve a track position resolution of 140 mu m, the front end electronics must operate at a low (2fC) threshold with a time marking capability of ~1ns. Two ASICs, the ASDBLR and DTMROC provide the complete pipelined readout chain. Custom designed FBGA packages for the ASICs provide a small enough outline to be detector mounted and the extensive use of low level differential signals make mounting the analog packages on printed circuit boards directly opposite the 40 MHz digital chips feasible. The readout electronics for the barrel occupies a potentially important part of the active tracker volume and an aggressive effort has been made to make it as compact as possible. Utilizing a single board for both analog and digital ASICS a 0.1 cm /sup 3/ per channel volume...

Chip-based microtrap arrays for cold polar molecules

Science.gov (United States)

Hou, Shunyong; Wei, Bin; Deng, Lianzhong; Yin, Jianping

2017-12-01

Compared to the atomic chip, which has been a powerful platform to perform an astonishing range of applications from rapid Bose-Einstein condensate (BEC) production to the atomic clock, the molecular chip is only in its infant stages. Recently a one-dimensional electric lattice was demonstrated to trap polar molecules on a chip. This excellent work opens up the way to building a molecular chip laboratory. Here we propose a two-dimensional (2D) electric lattice on a chip with concise and robust structure, which is formed by arrays of squared gold wires. Arrays of microtraps that originate in the microsize electrodes offer a steep gradient and thus allow for confining both light and heavy polar molecules. Theoretical analysis and numerical calculations are performed using two types of sample molecules, N D3 and SrF, to justify the possibility of our proposal. The height of the minima of the potential wells is about 10 μm above the surface of the chip and can be easily adjusted in a wide range by changing the voltages applied on the electrodes. These microtraps offer intriguing perspectives for investigating cold molecules in periodic potentials, such as quantum computing science, low-dimensional physics, and some other possible applications amenable to magnetic or optical lattice. The 2D adjustable electric lattice is expected to act as a building block for a future gas-phase molecular chip laboratory.

A Time-Based Front End Readout System for PET & CT

CERN Document Server

Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

2007-01-01

In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

Hybrid Macro-Micro Fluidics System for a Chip-Based Biosensor

National Research Council Canada - National Science Library

Tamanaha, C. R; Whitman, L. J; Colton, R.J

2002-01-01

We describe the engineering of a hybrid fluidics platform for a chip-based biosensor system that combines high-performance microfluidics components with powerful, yet compact, millimeter-scale pump and valve actuators...

Absolute quantification of DNA methylation using microfluidic chip-based digital PCR.

Science.gov (United States)

Wu, Zhenhua; Bai, Yanan; Cheng, Zule; Liu, Fangming; Wang, Ping; Yang, Dawei; Li, Gang; Jin, Qinghui; Mao, Hongju; Zhao, Jianlong

2017-10-15

Hypermethylation of CpG islands in the promoter region of many tumor suppressor genes downregulates their expression and in a result promotes tumorigenesis. Therefore, detection of DNA methylation status is a convenient diagnostic tool for cancer detection. Here, we reported a novel method for the integrative detection of methylation by the microfluidic chip-based digital PCR. This method relies on methylation-sensitive restriction enzyme HpaII, which cleaves the unmethylated DNA strands while keeping the methylated ones intact. After HpaII treatment, the DNA methylation level is determined quantitatively by the microfluidic chip-based digital PCR with the lower limit of detection equal to 0.52%. To validate the applicability of this method, promoter methylation of two tumor suppressor genes (PCDHGB6 and HOXA9) was tested in 10 samples of early stage lung adenocarcinoma and their adjacent non-tumorous tissues. The consistency was observed in the analysis of these samples using our method and a conventional bisulfite pyrosequencing. Combining high sensitivity and low cost, the microfluidic chip-based digital PCR method might provide a promising alternative for the detection of DNA methylation and early diagnosis of epigenetics-related diseases. Copyright © 2017 Elsevier B.V. All rights reserved.

A multi-channel time-to-digital converter chip for drift chamber readout

International Nuclear Information System (INIS)

Santos, D.M.; Chau, A.; DeBusshere, D.; Dow, S.; Flasck, J.; Levi, M.; Kirsten, F.; Su, E.

1995-12-01

A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e. 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using one eight channel TDC comprised of a delay locked loop and eight sets of latches and encoders. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. The timing and amplitude information is multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are then transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in a 0.8μ triple metal CMOS process. The TDC sub-element has been measured to have better than 135 ps time resolution and 35 ps jitter. The DRAM has a measured cycle time of 80 MHz

A frame simulator for data produced by 'multi-accumulation' readout detectors

Science.gov (United States)

Bonoli, Carlotta; Bortoletto, Favio; Giro, Enrico; Corcione, Leonardo; Ligori, Sebastiano; Nicastro, Luciano

2010-07-01

A simulator of data frames produced by 'multi-accumulation' readout detectors has been developed during the feasibility study for the NIS spectrograph, part of the European Euclid mission. The software can emulate various readout strategies, allowing to compare the efficiency of different sampling techniques. Special care is given to two crucial aspects: the minimization of the noise and the effects produced by cosmic hits. The resulting readout noise is analyzed as a function of the background sources, detector native characteristics and readout strategy, while the image deterioration by cosmic rays covers the simulation of hits and their correction efficiency varying the readout modalities. Simulated "multi-accumulation" frames, typical of multiplexer based detectors, are an ideal tool for testing the efficiency of cosmic ray rejection techniques. In the present case cosmic rays are added to each raw frame conforming to the rates and energy expected in the operational L2 region and in the chosen exposure time. Procedures efficiency for cosmic ray identification and correction can also be easily tested in terms of memory occupancy and telemetry rates.

A new PCI card for readout in high energy physics experiments

CERN Document Server

Floris, M; Marras, D; Usai, G L; David, A

2004-01-01

Recently some high energy physics experiments started to adopt readout systems based on the PCI architecture. In this context a new PCI card that can be adapted to several readout schemes has been designed. The card contains a large 64 MB local buffer, programmable FPGA logic and a PLX PCI bridge. The solution to use a PCI bridge external to the programmable logic allows to greatly simplify projects at the level of the on-board local bus. The card is presently used as the basic readout unit of the NA60 experiment. In this context, coupling it to different mezzanine cards it is possible to create interfaces to VME/CAMAC modules or to custom front-end electronics as for the case of the silicon vertex detector. Moreover, it is used as a readout test system for the ALICE muon chambers. (10 refs).

Fully integrated low-noise readout circuit with automatic offset cancellation loop for capacitive microsensors.

Science.gov (United States)

Song, Haryong; Park, Yunjong; Kim, Hyungseup; Cho, Dong-Il Dan; Ko, Hyoungho

2015-10-14

Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL) for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR) logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS) process with an active area of 1.76 mm². The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of -250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Fully Integrated Low-Noise Readout Circuit with Automatic Offset Cancellation Loop for Capacitive Microsensors

Directory of Open Access Journals (Sweden)

Haryong Song

2015-10-01

Full Text Available Capacitive sensing schemes are widely used for various microsensors; however, such microsensors suffer from severe parasitic capacitance problems. This paper presents a fully integrated low-noise readout circuit with automatic offset cancellation loop (AOCL for capacitive microsensors. The output offsets of the capacitive sensing chain due to the parasitic capacitances and process variations are automatically removed using AOCL. The AOCL generates electrically equivalent offset capacitance and enables charge-domain fine calibration using a 10-bit R-2R digital-to-analog converter, charge-transfer switches, and a charge-storing capacitor. The AOCL cancels the unwanted offset by binary-search algorithm based on 10-bit successive approximation register (SAR logic. The chip is implemented using 0.18 μm complementary metal-oxide-semiconductor (CMOS process with an active area of 1.76 mm2. The power consumption is 220 μW with 3.3 V supply. The input parasitic capacitances within the range of −250 fF to 250 fF can be cancelled out automatically, and the required calibration time is lower than 10 ms.

Organ/body-on-a-chip based on microfluidic technology for drug discovery.

Science.gov (United States)

Kimura, Hiroshi; Sakai, Yasuyuki; Fujii, Teruo

2018-02-01

Although animal experiments are indispensable for preclinical screening in the drug discovery process, various issues such as ethical considerations and species differences remain. To solve these issues, cell-based assays using human-derived cells have been actively pursued. However, it remains difficult to accurately predict drug efficacy, toxicity, and organs interactions, because cultivated cells often do not retain their original organ functions and morphologies in conventional in vitro cell culture systems. In the μTAS research field, which is a part of biochemical engineering, the technologies of organ-on-a-chip, based on microfluidic devices built using microfabrication, have been widely studied recently as a novel in vitro organ model. Since it is possible to physically and chemically mimic the in vitro environment by using microfluidic device technology, maintenance of cellular function and morphology, and replication of organ interactions can be realized using organ-on-a-chip devices. So far, functions of various organs and tissues, such as the lung, liver, kidney, and gut have been reproduced as in vitro models. Furthermore, a body-on-a-chip, integrating multi organ functions on a microfluidic device, has also been proposed for prediction of organ interactions. We herein provide a background of microfluidic systems, organ-on-a-chip, Body-on-a-chip technologies, and their challenges in the future. Copyright © 2017 The Japanese Society for the Study of Xenobiotics. Published by Elsevier Ltd. All rights reserved.

Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

International Nuclear Information System (INIS)

Michalowska, A.

2013-01-01

designed two ASICs. The first one, Caterpylar, is a test-chip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D 2 R 1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16 *16 array. Each channel fits into a layout area of 300 μm - 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW/channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV. (author) [fr

Resonance Frequency Readout Circuit for a 900 MHz SAW Device.

Science.gov (United States)

Liu, Heng; Zhang, Chun; Weng, Zhaoyang; Guo, Yanshu; Wang, Zhihua

2017-09-15

A monolithic resonance frequency readout circuit with high resolution and short measurement time is presented for a 900 MHz RF surface acoustic wave (SAW) sensor. The readout circuit is composed of a fractional-N phase-locked loop (PLL) as the stimulus source to the SAW device and a phase-based resonance frequency detecting circuit using successive approximation (SAR). A new resonance frequency searching strategy has been proposed based on the fact that the SAW device phase-frequency response crosses zero monotonically around the resonance frequency. A dedicated instant phase difference detecting circuit is adopted to facilitate the fast SAR operation for resonance frequency searching. The readout circuit has been implemented in 180 nm CMOS technology with a core area of 3.24 mm². In the experiment, it works with a 900 MHz SAW resonator with a quality factor of Q = 130. Experimental results show that the readout circuit consumes 7 mW power from 1.6 V supply. The frequency resolution is 733 Hz, and the relative accuracy is 0.82 ppm, and it takes 0.48 ms to complete one measurement. Compared to the previous results in the literature, this work has achieved the shortest measurement time with a trade-off between measurement accuracy and measurement time.

Determination of Apparent Amylose Content in Rice by Using Paper-Based Microfluidic Chips.

Science.gov (United States)

Hu, Xianqiao; Lu, Lin; Fang, Changyun; Duan, Binwu; Zhu, Zhiwei

2015-11-11

Determination of apparent amylose content in rice is a key function for rice research and the rice industry. In this paper, a novel approach with paper-based microfluidic chip is reported to determine apparent amylose content in rice. The conventional color reaction between amylose and iodine was employed. Blue color of amylose-iodine complex generated on-chip was converted to gray and measured with Photoshop after the colored chip was scanned. The method for preparation of the paper chip is described. In situ generation of iodine for on-chip color reaction was designed, and factors influencing color reaction were investigated in detail. Elimination of yellow color interference of excess iodine by exploiting color removal function of Photoshop was presented. Under the optimized conditions, apparent amylose content in rice ranging from 1.5 to 26.4% can be determined, and precision was 6.3%. The analytical results obtained with the developed approach were in good agreement with those with the continuous flow analyzer method.

Digital radiography using amorphous selenium: photoconductively activated switch (PAS) readout system.

Science.gov (United States)

Reznik, Nikita; Komljenovic, Philip T; Germann, Stephen; Rowlands, John A

2008-03-01

A new amorphous selenium (a-Se) digital radiography detector is introduced. The proposed detector generates a charge image in the a-Se layer in a conventional manner, which is stored on electrode pixels at the surface of the a-Se layer. A novel method, called photoconductively activated switch (PAS), is used to read out the latent x-ray charge image. The PAS readout method uses lateral photoconduction at the a-Se surface which is a revolutionary modification of the bulk photoinduced discharge (PID) methods. The PAS method addresses and eliminates the fundamental weaknesses of the PID methods--long readout times and high readout noise--while maintaining the structural simplicity and high resolution for which PID optical readout systems are noted. The photoconduction properties of the a-Se surface were investigated and the geometrical design for the electrode pixels for a PAS radiography system was determined. This design was implemented in a single pixel PAS evaluation system. The results show that the PAS x-ray induced output charge signal was reproducible and depended linearly on the x-ray exposure in the diagnostic exposure range. Furthermore, the readout was reasonably rapid (10 ms for pixel discharge). The proposed detector allows readout of half a pixel row at a time (odd pixels followed by even pixels), thus permitting the readout of a complete image in 30 s for a 40 cm x 40 cm detector with the potential of reducing that time by using greater readout light intensity. This demonstrates that a-Se based x-ray detectors using photoconductively activated switches could form a basis for a practical integrated digital radiography system.

Characterization of imaging pixel detectors of Si and CdTe read out with the counting X-ray chip MPEC 2.3

International Nuclear Information System (INIS)

Loecker, M.

2007-04-01

Single photon counting detectors with Si- and CdTe-sensors have been constructed and characterized. As readout chip the MPEC 2.3 is used which consists of 32 x 32 pixels with 200 x 200 μm 2 pixel size and which has a high count rate cabability (1 MHz per pixel) as well as a low noise performance (55 e - ). Measurements and simulations of the detector homogeneity are presented. It could be shown that the theoretical maximum of the homogeneity is reached (quantum limit). By means of the double threshold of the MPEC chip the image contrast can be enhanced which is demonstrated by measurement and simulation. Also, multi-chip-modules consisting of 4 MPEC chips and a single Si- or CdTe-sensor have been constructed and successfully operated. With these modules modulation-transfer-function measurements have been done showing a good spatial resolution of the detectors. In addition, multi-chip-modules according to the Sparse-CMOS concept have been built and tests characterizing the interconnection technologies have been performed

Debugging systems-on-chip communication-centric and abstraction-based techniques

CERN Document Server

Vermeulen, Bart

2014-01-01

This book describes an approach and supporting infrastructure to facilitate debugging the silicon implementation of a System-on-Chip (SOC), allowing its associated product to be introduced into the market more quickly.  Readers learn step-by-step the key requirements for debugging a modern, silicon SOC implementation, nine factors that complicate this debugging task, and a new debug approach that addresses these requirements and complicating factors.  The authors’ novel communication-centric, scan-based, abstraction-based, run/stop-based (CSAR) debug approach is discussed in detail, showing how it helps to meet debug requirements and address the nine, previously identified factors that complicate debugging silicon implementations of SOCs. The authors also derive the debug infrastructure requirements to support debugging of a silicon implementation of an SOC with their CSAR debug approach. This debug infrastructure consists of a generic on-chip debug architecture, a configurable automated design-for-debug ...

Study of Charge Diffusion in a Silicon Detector Using an Energy Sensitive Pixel Readout Chip

CERN Document Server

Schioppa, E. J.; van Beuzekom, M.; Visser, J.; Koffeman, E.; Heijne, E.; Engel, K. J.; Uher, J.

2015-01-01

A 300 μm thick thin p-on-n silicon sensor was connected to an energy sensitive pixel readout ASIC and exposed to a beam of highly energetic charged particles. By exploiting the spectral information and the fine segmentation of the detector, we were able to measure the evolution of the transverse profile of the charge carriers cloud in the sensor as a function of the drift distance from the point of generation. The result does not rely on model assumptions or electric field calculations. The data are also used to validate numerical simulations and to predict the detector spectral response to an X-ray fluorescence spectrum for applications in X-ray imaging.

Study of the spatial resolution for binary readout detectors

Energy Technology Data Exchange (ETDEWEB)

Yonamine, R., E-mail: ryo.yonamine@ulb.ac.be; Maerschalk, T.; Lentdecker, G. De

2016-07-11

Often the binary readout is proposed for high granularity detectors to reduce the generated data volume to be readout at the price of a somewhat reduced spatial resolution compared to an analogue readout. We have been studying single hit resolutions obtained with a binary readout using simulations as well as analytical approaches. In this note we show that the detector geometry could be optimized to offer an equivalent spatial resolution than with an analogue readout.

Development of a Crosstalk Suppression Algorithm for KID Readout

Science.gov (United States)

Lee, Kyungmin; Ishitsuka, H.; Oguri, S.; Suzuki, J.; Tajima, O.; Tomita, N.; Won, Eunil; Yoshida, M.

2018-06-01

The GroundBIRD telescope aims to detect B-mode polarization of the cosmic microwave background radiation using the kinetic inductance detector array as a polarimeter. For the readout of the signal from detector array, we have developed a frequency division multiplexing readout system based on a digital down converter method. These techniques in general have the leakage problems caused by the crosstalks. The window function was applied in the field programmable gate arrays to mitigate the effect of these problems and tested it in algorithm level.

An SOI CMOS-Based Multi-Sensor MEMS Chip for Fluidic Applications.

Science.gov (United States)

Mansoor, Mohtashim; Haneef, Ibraheem; Akhtar, Suhail; Rafiq, Muhammad Aftab; De Luca, Andrea; Ali, Syed Zeeshan; Udrea, Florin

2016-11-04

An SOI CMOS multi-sensor MEMS chip, which can simultaneously measure temperature, pressure and flow rate, has been reported. The multi-sensor chip has been designed keeping in view the requirements of researchers interested in experimental fluid dynamics. The chip contains ten thermodiodes (temperature sensors), a piezoresistive-type pressure sensor and nine hot film-based flow rate sensors fabricated within the oxide layer of the SOI wafers. The silicon dioxide layers with embedded sensors are relieved from the substrate as membranes with the help of a single DRIE step after chip fabrication from a commercial CMOS foundry. Very dense sensor packing per unit area of the chip has been enabled by using technologies/processes like SOI, CMOS and DRIE. Independent apparatuses were used for the characterization of each sensor. With a drive current of 10 µA-0.1 µA, the thermodiodes exhibited sensitivities of 1.41 mV/°C-1.79 mV/°C in the range 20-300 °C. The sensitivity of the pressure sensor was 0.0686 mV/(V excit kPa) with a non-linearity of 0.25% between 0 and 69 kPa above ambient pressure. Packaged in a micro-channel, the flow rate sensor has a linearized sensitivity of 17.3 mV/(L/min) -0.1 in the tested range of 0-4.7 L/min. The multi-sensor chip can be used for simultaneous measurement of fluid pressure, temperature and flow rate in fluidic experiments and aerospace/automotive/biomedical/process industries.

Technology for the compatible integration of silicon detectors with readout electronics

International Nuclear Information System (INIS)

Zimmer, G.

1984-01-01

Compatible integration of detectors and readout electronics on the same silicon substrate is of growing interest. As the methods of microelectronics technology have already been adapted for detector fabrication, a common technology basis for detectors and readout electronics is available. CMOS technology exhibits most attractive features for the compatible realization of readout electronics when advanced LSI processing steps are combined with detector requirements. The essential requirements for compatible integration are the availability of high resistivity (100)-oriented single crystalline silicon substrate, the formation of suitably doped areas for MOS circuits and the isolation of the low voltage circuit from the detector operated at much higher supply voltage. Junction isolation as a first approach based on present production technology and dielectric isolation based on an advanced SOI-LSI technology are discussed as the most promising solutions for present and future applications, respectively. (orig.)

Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

Energy Technology Data Exchange (ETDEWEB)

Li, Xuelian [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Zang, Jianfeng [Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC 27708 (United States); Liu, Yingshuai; Lu, Zhisong [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); Li, Qing, E-mail: Qli@swu.edu.cn [School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Li, Chang Ming, E-mail: ecmli@swu.edu.cn [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China)

2013-04-10

Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

A Cardiac Cell Outgrowth Assay for Evaluating Drug Compounds Using a Cardiac Spheroid-on-a-Chip Device

Directory of Open Access Journals (Sweden)

Jonas Christoffersson

2018-05-01

Full Text Available Three-dimensional (3D models with cells arranged in clusters or spheroids have emerged as valuable tools to improve physiological relevance in drug screening. One of the challenges with cells cultured in 3D, especially for high-throughput applications, is to quickly and non-invasively assess the cellular state in vitro. In this article, we show that the number of cells growing out from human induced pluripotent stem cell (hiPSC-derived cardiac spheroids can be quantified to serve as an indicator of a drug’s effect on spheroids captured in a microfluidic device. Combining this spheroid-on-a-chip with confocal high content imaging reveals easily accessible, quantitative outgrowth data. We found that effects on outgrowing cell numbers correlate to the concentrations of relevant pharmacological compounds and could thus serve as a practical readout to monitor drug effects. Here, we demonstrate the potential of this semi-high-throughput “cardiac cell outgrowth assay” with six compounds at three concentrations applied to spheroids for 48 h. The image-based readout complements end-point assays or may be used as a non-invasive assay for quality control during long-term culture.

Droplet-based Biosensing for Lab-on-a-Chip, Open Microfluidics Platforms

Directory of Open Access Journals (Sweden)

Piyush Dak

2016-04-01

Full Text Available Low cost, portable sensors can transform health care by bringing easily available diagnostic devices to low and middle income population, particularly in developing countries. Sample preparation, analyte handling and labeling are primary cost concerns for traditional lab-based diagnostic systems. Lab-on-a-chip (LoC platforms based on droplet-based microfluidics promise to integrate and automate these complex and expensive laboratory procedures onto a single chip; the cost will be further reduced if label-free biosensors could be integrated onto the LoC platforms. Here, we review some recent developments of label-free, droplet-based biosensors, compatible with “open” digital microfluidic systems. These low-cost droplet-based biosensors overcome some of the fundamental limitations of the classical sensors, enabling timely diagnosis. We identify the key challenges that must be addressed to make these sensors commercially viable and summarize a number of promising research directions.

Readout Unit-FPGA version for link multipexers, DAQ and VELO trigger

CERN Document Server

Müller, H; Guirao, A; Bal, F

2003-01-01

The FPGA-based Readout Unit (RU) was designed as entry stage to the readout networks of the LHCb data acquisition and L1-VELO topology trigger systems. The RU performs subevent building from up to 16 custom S-link inputs towards a commercial readout network via a PCI interface card. For output to custom links, as required in datalink multiplexer applications, an output S-link transmitter interface is alternatively available. Baseline readout networks for the RU are intelligent Gbit-ethernet NIC cards for the DAQ system and SCI shared memory network for the L1-VELO system. Any new protocols, like 10Gbit ethernet or Infiniband may be adopted as far as proper PCI interfaces and Linux device drivers will become available. The two baseline RU modes of operation are: 1.) link-multiplexer with N*Slink to single-Slink 2.) eventbuilder interface with quad Slink-to-PCI network interface.

A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

Science.gov (United States)

Quilligan, G.; Aslam, S.; DuMonthier, J.

2012-01-01

A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

Characterization of Medipix3 with the MARS readout and software

CERN Document Server

Ronaldson, J P; van Leeuwen, D; Doesburg, R M N; Ballabriga, R; Butler, A P H; Donaldson, J; Walsh, M; Nik, S J; Clyne, M N

2011-01-01

The Medipix3 x-ray imaging detector has been characterized using the MARS camera. This x-ray camera comprises custom built readout electronics and software libraries designed for the Medipix family of detectors. The performance of the Medipix3 and MARS camera system is being studied prior to use in real-world applications such as the recently developed MARS-CT3 spectroscopic micro-CT scanner. We present the results of characterization measurements, describe methods for optimizing performance and give examples of spectroscopic images acquired with Medipix3 and the MARS camera system. A limited number of operating modes of the Medipix3 chip have been characterized and single-pixel mode has been found to give acceptable performance in terms of energy response, image quality and stability over time. Spectroscopic performance is significantly better in charge-summing mode than single-pixel mode however image quality and stability over time are compromised. There are more modes of operation to be tested and further...

Hybrid macro-micro fluidics system for a chip-based biosensor