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Sample records for atlas pixel front-end

  1. Dead-time free pixel readout architecture for ATLAS front-end IC

    CERN Document Server

    Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

    1999-01-01

    A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

  2. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  3. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  4. Total Ionising Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00439451

    2016-01-01

    The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the LV current, produced by the FE-I4 chip, was observed. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations. This report presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

  5. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  6. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  7. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  8. Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Peschke, Richard

    2017-03-15

    As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

  9. Front end electronics for pixel detector of the PANDA MVD

    CERN Document Server

    Kugathasan, Thanushan; De Remigis, P; Mazza, G; Mignone, M; Rivetti, A; Wheadon, R

    2009-01-01

    ToPix 2.0 is a prototype in a CMOS 0.13 ¹m technology of the front-end chip for the hybrid pixel sensors that will equip the Micro-Vertex Detector of the PANDA experiment at GSI. The Time over Threshold (ToT) approach has been employed to provide a high charge dynamic range (up to 100 fC) with a low power dissipation (15 ¹W/cell). In an area of 100¹m£100¹m each cell incorporates the analog and digital electronics necessary to amplify the detector signal and to digitize the time and charge information. The ASIC includes 320 pixel readout cells organized in four columns and a simplified version of the end of column readout.

  10. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  11. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  12. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  13. The 025 mum front-end for the CMS pixel detector

    CERN Document Server

    Erdmann, W

    2005-01-01

    The front-end for the CMS pixel detector has been translated from the radiation hard DMILL process to a commercial 0.25 mum technology. The smaller feature size of this technology permitted a reduction of the pixel size and other improvements. First results obtained with the translated chip are discussed.

  14. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  15. ATLAS ITk Pixel detector

    CERN Document Server

    Gemme, Claudia; The ATLAS collaboration

    2016-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

  16. Design and implementation of the ATLAS TRT front end electronics

    Science.gov (United States)

    Newcomer, Mitch; Atlas TRT Collaboration

    2006-07-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

  17. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  18. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  19. Development of front-end electronics and TDC LSI for the ATLAS MDT

    CERN Document Server

    Arai, Y

    2000-01-01

    Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

  20. Electromagnetic Compatibility of a Low Voltage Power Supply for the ATLAS Tile Calorimeter Front-End Electronics

    CERN Document Server

    Blanchot, Georges; Hruska, I; Korolkov, I Ya; Palan, B; Pontt, J; Toro, A; Usai, G

    2007-01-01

    The front-end electronics of the ATLAS Tile Calorimeter is powered by DC/DC converters that sit close to it. The performance of the detector electronics is constrained by the conducted noise emissions of its power supply. A compatibility limit is defined for the system. The noise susceptibility of the front-end electronics is evaluated, and different solutions to reduce the front-end electronics noise are discussed and tested.

  1. Test system for the production of the ATLAS Tile Calorimeter front- end electronics

    CERN Document Server

    Calvet, D

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called "super-drawers". The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.

  2. Front-end I/O of the ATLAS Detector Control System

    CERN Document Server

    Burckhart, Helfried J

    1999-01-01

    The importance of using a powerful Detector Control System (DCS) has much increased with the size and complexity of High-Energy Physics detectors. The generation of detectors for the LHC experiments puts further requirements onto the front-end I/O system due to the inaccessibility of the equipment and the hostile environment concerning radiation and magnetic field. Novel techniques such as fieldbuses for distributed input/output and Programmable Logic Controllers (PLC) for closed loop control have to be employed. These represent the layer closest to the detector of a hierarchically organized multi-layer DCS. After an introduction of the organization of the ATLAS detector and of the concept and the architecture of DCS the paper will concentrate on the usage of fieldbuses as front-end I/O bus with special emphasis on industrial standards of hardware and software.

  3. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  4. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00029377; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  5. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  6. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  7. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  8. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  9. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  10. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    Energy Technology Data Exchange (ETDEWEB)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-03-19

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.

  11. Design of the Front-End Detector Control System of the ATLAS New Small Wheels

    CERN Document Server

    Koulouris, Aimilianos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

  12. SEU rate estimates for the ATLAS/SCT front-end ASIC

    CERN Document Server

    Eklund, L; Grigson, C; Kramberger, G; Mandic, I; Mikuz, M; Phillips, P

    2003-01-01

    We present a method of estimating the sensitivity to radiation- induced Single Event Upset (SEU) in the front-end ASICs for the ATLAS Semiconductor Tracker. The method is using ASICs of the final design with limited read-back possibilities of internal registers. Hence the measurement is adapted to utilise the event-data flow in the digital part of the ASIC to detect bit-flips. Furthermore, we report on the application of this method to estimate the SEU sensitivity. The results presented are based on data from three irradiation periods using prototype electronics hybrids and detector modules. The measurements were done with 24 GeV/c protons and 200 MeV/c pions.

  13. Irradiation tests of the pixel front-end readout electronics for the ALICE experiment at LHC

    Energy Technology Data Exchange (ETDEWEB)

    Badala, A.; Barbera, R.; Lo Re, G.; Palmeri, A.; Pappalardo, G.S.; Riggi, F. E-mail: franco.riggi@ct.infn.it; Di Liberto, S.; Meddi, F.; Cavagnoli, A.; Morando, M.; Scarlassara, F.; Segato, G.; Soramel, F.; Vannucci, L

    2002-01-11

    The problem of radiation damage for the electronics of the pixel detectors in the Inner-Tracking-System of the ALICE experiment is discussed. Simulations allowed to estimate total doses and particle fluences during 10 years of operation period. Several irradiation tests have been carried out on the various prototypes of the readout chips. The results obtained so far points out that the recent prototypes will retain their functionality up to doses and neutron fluences well above those expected in ALICE.

  14. Irradiation studies of multimode optical fibres for use in ATLAS front-end links

    CERN Document Server

    Mahout, G; Andrieux, M L; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, R James; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, A R; Wilson, J A; Ye, J

    2000-01-01

    The radiation tolerance of three multimode optical fibres has been investigated to establish their suitability for the use in the front- end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of ~0.05 dB/m at 330 kGy (Si) and 1*10/sup 15/ n(1 MeV Si)/cm/sup 2/ and is suitable for use with the inner detector links which operate at 40-80 Mb/s. A graded- index fibre with a predominantly germanium-doped core exhibits an induced attenuation of ~0.1 dB/m at 800 Gy(Si) and 2*10/sup 13/ n(1 MeV Si)/cm/sup 2/ and is suitable for the calorimeter links which operate at 1.6 Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower. (30 refs).

  15. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  16. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  17. Irradiation Studies of Multimode Fibres for use in ATLAS Front-end Links

    CERN Document Server

    Mahout, G; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, RJ; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Pearce, M; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, AR; Wilson, J A; Ye, J

    1999-01-01

    The radiation tolerance of three multimode optical fibres has been investigatedto establish their suitability for use in the front-end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of $\\sim$0.05~dB/mat 330~kGy(Si) and 1$\\times$10$^{15}$~n(1~MeV~Si)/cm$^{2}$ and is suitablefor use with the inner detector links which operate at 40-80~Mb/s. A graded-indexfibre with a predominantly germanium doped core exhibits an induced attenuation of $\\sim$0.1~dB/mat 800~Gy(Si) and 2$\\times$10$^{13}$~n(1~MeV~Si)/cm$^{2}$ and is suitable for the calorimeterlinks which operate at 1.6~Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower.

  18. Front-end Intelligence for triggering and local track recognition in Gas Pixel Detectors

    CERN Document Server

    Hessey, NP; The ATLAS collaboration; van der Graaf, H; Vermeulen, J; Jansweijer, P; Romaniouk, A

    2012-01-01

    The combination of gaseous detectors with pixel readout chips gives unprecedented hit resolution (improving from O(100 um) for wire chambers to 10 um), as well as high-rate capability, low radiation length and giving in addition angular information on the local track. These devices measure individually every electron liberated by the passage of a charged particle, leading to a large quantity of data to be read out. Typically an external trigger is used to start the read-out. We are investigating the addition of local intelligence to the pixel read-out chip. A first level of processing detects the passage of a particle through the gas volume, and accurately determines the time of passage. A second level measures in an approximate but fast way the tilt-angle of the track. This can be used to trigger a third stage in which all hits associated to the track are processed locally to give a least-squares-fit to the track. The chip can then send out just the fitted track parameters instead of the individual electron ...

  19. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the Atlas Tile Calorimeter

    CERN Document Server

    Drake, G; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Mellado, B; Proudfoot, J

    2012-01-01

    –We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. This may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present conclusions for improvements to the power distribution system for the LHC Phase 2 upgrade.

  20. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the ATLAS Tile Calorimeter

    CERN Document Server

    Senthilkumaran, A; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Drake, G; Proudfoot, J

    2012-01-01

    We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. We will illustrate the technique, which may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present our preliminary design work for improvements in the power distribution system for the LHC Phase 2 upgrade.

  1. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  2. Pixel readout chip for the ATLAS experiment

    CERN Document Server

    Ackers, M; Blanquart, L; Bonzom, V; Comes, G; Fischer, P; Keil, M; Kühl, T; Meuser, S; Delpierre, P A; Treis, J; Raith, B A; Wermes, N

    1999-01-01

    Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4*10/sup 8/ individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector. Consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported. (6 refs).

  3. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  4. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  5. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    INSPIRE-00218666

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with X-ray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  6. Upgrade of ATLAS ITk Pixel Detector

    CERN Document Server

    Huegging, Fabian; The ATLAS collaboration

    2017-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current inner detector will be replaced with an entirely-silicon inner tracker (ITk) which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation levels are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors and low mass global and local support structures. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the ITk ATLAS Pixel detector developments as well as different layout options will be reviewed.

  7. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Hofsajer, I; Govender, M; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is the portable test-bench for the full certification of the front-end electronics of the ATLAS Tile calorimeter designed for the upgrade phase-II. It is a high throughput electronics system designed to simultaneously read-out all the samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read-out and control the front-end boards. The rest of the functionalities of the system are provided by a HV mezzanine board that to turn on the gain of the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog output of the front-end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  8. Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

  9. An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  10. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  11. Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

    CERN Document Server

    Drake, G; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

  12. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  13. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  14. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 During the first year of the IBL operation in 2015 a significant increase of the LV current of the front-end chip and the detuning of its parameters (threshold and time-over- threshold) have been observed in relation to the received TID. In this talk , the TID effects in the FE-I4 chip are reported based on studies performed in the laboratory using X-ray and proton irradiation sources for various temperature and irradiation intensity conditions. Based on these results, an operation guideline of the IBL detector is presented.

  15. An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

  16. An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

  17. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  18. A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

    Science.gov (United States)

    Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

    2017-06-01

    A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

  19. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  20. JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

    CERN Document Server

    Moschovakos, Paris

    2018-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

  1. A Simulation of the Front End Signal Digitization for the ATLAS Muon Spectrometer thin RPC trigger upgrade project

    Science.gov (United States)

    Meng, Xiangting; Chapman, John; Levin, Daniel; Dai, Tiesheng; Zhu, Junjie; Zhou, Bing; Um Atlas Group Team

    2016-03-01

    The ATLAS Muon Spectrometer Phase-I (and Phase-II) upgrade includes the BIS78 muon trigger detector project: two sets of eight very thin Resistive Place Chambers (tRPCs) combined with small Monitored Drift Tube (MDT) chambers in the pseudorapidity region 1Digitization of the strip signals will be done by 32-channel CERN HPTDC chips. The HPTDC is a highly configurable ASIC designed by the CERN Microelectronics group. It can work in both trigger and trigger-less modes, be readout in parallel or serially. For Phase-I operation, a stringent latency requirement of 43 bunch crossings (1075 ns) is imposed. The latency budget for the front end digitization must be kept to a minimal value, ideally less than 350 ns. We conducted detailed HPTDC latency simulations using the Behavioral Verilog code from the CERN group. We will report the results of these simulations run for the anticipated detector operating environment and for various HPTDC configurations.

  2. Initial Measurements on Pixel Detector Modules for the ATLAS Upgrades

    CERN Document Server

    Gallrapp, C; The ATLAS collaboration

    2011-01-01

    Delicate conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel Detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming Pixel Detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation for silicon planar and 3D pixel sensors, which give a first impression on the charge collection properties of the different sensor technologies, are presented.

  3. Optical Links for ATLAS Liquid Argon Calorimeter Front-end Electronics Readout

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We present optical data links for the ATLAS liquid argon calorimeter. The current status of the VCSEL failures, the up-to-date results in searching for the failure cause, experiences gained in the searching process, possible backup plans for the optical transmitters and the lessons learned are also discussed.

  4. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  5. Initial Measurements On Pixel Detector Modules For The ATLAS Upgrades

    CERN Document Server

    Gallrapp, C; The ATLAS collaboration

    2011-01-01

    Sophisticated conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming pixel detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation, which give a first impression on the charge collection properties of the different sensor technologies are presented.

  6. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  7. Pixel electronics for the ATLAS experiment

    CERN Document Server

    Fischer, P

    2001-01-01

    The ATLAS experiment at LHC will use 3 barrel layers and 2*5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mm*60.8 mm which include an n/sup +/ on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode...

  8. Serial powering for the upgrades of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Gonella, Laura; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Physikalisches Institut, Univ. Bonn, Nussallee 12, 53115 Bonn (Germany)

    2012-07-01

    A serial powering scheme is proposed for the upgrades of the ATLAS pixel detector at the High Luminosity (HL-)LHC, to provide an efficient and low material power distribution. The main regulation element is the Shunt-LDO regulator, a new regulator concept designed to meet the requirements of serially powered detector systems. The Shunt-LDO working principle was successfully demonstrated with two prototypes, and two Shunt-LDO regulators are integrated in the new ATLAS pixel FE (Front-End) chip, the FE-I4. Results of the characterization of the regulators in FE-I4 are shown, and the chip performance is compared for different powering options, with and without regulators. At the same time a serial powering demonstrator is being developed. This will include a chain of four 2-chips pixel modules, AC-coupled data transmission, dedicated HV distribution scheme, and possibly a stave protection chip. Results on the stave demonstrator are presented as well.

  9. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  10. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    Science.gov (United States)

    Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

    2016-12-01

    The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  11. The ATLAS tracker Pixel detector for HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00214676; The ATLAS collaboration

    2017-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current Inner Detector will be replaced with an all-silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected dense tracking environment and high radiation levels require the development of higher granularity radiation hard silicon sensors and a new front-end readout chip. The data rates require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLAS Pixel detector developments as well as the various layout options are presented in this paper.

  12. Overview of the ATLAS Insertable B-Layer Pixel Detector

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2011-01-01

    ATLAS currently develops a new pixel detector for the first upgrade of its tracking system: The ATLAS Insertable B-Layer Pixel detector (IBL). The new layer will be inserted between the inner most layer of the current pixel detector and a new beam pipe. The sensors are placed at a radius of 3.4cm. The expected high radiation levels and high hit occupancy require new developments for front-end chip and the sensor which can stand radiation levels beyond 5E15 neq/cm2. ATLAS has developed the new FEI4 and new silicon sensors to be used as pixel modules. Furthermore a new lightweight support and cooling structure was developed, which minimizes the overall radiation and allows detector cooling with CO2 at -40C coolant temperature. Currently the overall integration and installation procedure is being developed and test ready for installation in ATLAS in 2013. The presentation summarizes the current state of development of IBL modules, first preliminary test results of the new chip with new sensors, the construction ...

  13. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  14. ATLAS Pixel Detector System Test

    CERN Document Server

    Triplett, N

    2007-01-01

    On June 25th of 2007 the ATLAS collaboration lowered the pixel detector into place, however before this the detector had to be qualified through a series of tests. Prior to assembly, each individual piece of the detector and services chain passed a set of quality controls. This was followed by the construction and test of the whole pixel detector. This test of the full chain of services -including the voltage supplies, opto-boards, cooling, temperature monitoring, control software, and the pixel modules themselves- is referred to as the Pixel System Test. The System Test took place in an above-ground laboratory setting at CERN and consisted of two main parts. The first half of the test focused on one of the pixel detector’s endcaps. This endcap consists of 144 modules, making up roughly 10% of the total pixel detector. For the pixel endcap test, most of the 144 modules were operated simultaneously which required that the pixel endcap’s cooling system be functioning as well[1]. Additionally, four scintilla...

  15. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

  16. The ATLAS Silicon Pixel Sensors

    CERN Document Server

    Alam, M S; Einsweiler, K F; Emes, J; Gilchriese, M G D; Joshi, A; Kleinfelder, S A; Marchesini, R; McCormack, F; Milgrome, O; Palaio, N; Pengg, F; Richardson, J; Zizka, G; Ackers, M; Andreazza, A; Comes, G; Fischer, P; Keil, M; Klasen, V; Kühl, T; Meuser, S; Ockenfels, W; Raith, B; Treis, J; Wermes, N; Gössling, C; Hügging, F G; Wüstenfeld, J; Wunstorf, R; Barberis, D; Beccherle, R; Darbo, G; Gagliardi, G; Gemme, C; Morettini, P; Musico, P; Osculati, B; Parodi, F; Rossi, L; Blanquart, L; Breugnon, P; Calvet, D; Clemens, J-C; Delpierre, P A; Hallewell, G D; Laugier, D; Mouthuy, T; Rozanov, A; Valin, I; Aleppo, M; Caccia, M; Ragusa, F; Troncon, C; Lutz, Gerhard; Richter, R H; Rohe, T; Brandl, A; Gorfine, G; Hoeferkamp, M; Seidel, SC; Boyd, GR; Skubic, P L; Sícho, P; Tomasek, L; Vrba, V; Holder, M; Ziolkowski, M; D'Auria, S; del Papa, C; Charles, E; Fasching, D; Becks, K H; Lenzen, G; Linder, C

    2001-01-01

    Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to the attachment of the readout integrated circuit electronics is also desired.

  17. Status of the ATLAS pixel detector

    CERN Document Server

    Saavedra Aldo, F

    2005-01-01

    The ATLAS pixel detector is currently being constructed and will be installed in 2006 to be ready for commissioning at the Large Hadron Collider. The complete pixel detector is composed of three concentric barrels and six disks that are populated by 1744 ATLAS Pixel modules. The main components of the pixel module are the readout electronics and the silicon sensor whose active region is instrumented with rectangular pixels. The module has been designed to be able to survive 10 years of operation within the ATLAS detector. A brief description of the pixel detector will be presented with results and problems encountered during the production stage.

  18. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Djama, Fares; The ATLAS collaboration

    2017-01-01

    Run 2 of the LHC collider sets new challenges to track and vertex reconstruction because of its higher energy, pileup and luminosity. The ATLAS tracking performance relies critically on the Pixel Detector. Therefore, in view of Run 2, the ATLAS collaboration has constructed the first 4-layer pixel detector in Particle Physics by installing a new pixel layer, called Insertable B-Layer (IBL). Operational experience and performance of the 4-layer Pixel Detector during Run 2 are presented.

  19. ATLAS pixel detector electronics and sensors

    Energy Technology Data Exchange (ETDEWEB)

    Aad, G; Bernardet, K [CPPM, Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Ackers, M; Barbero, M B [Physikalisches Institut der Universitaet Bonn, Nussallee 12, D - 53115 Bonn (Germany); Alberti, F A; Aleppo, M; Alimonti, G; Andreani, A; Andreazza, A [INFN Milano, via Celoria 16, IT - 20133 Milano (Italy); Alonso, J; Anderssen, E C; Arguin, J-F; Beringer, J [Lawrence Berkeley National Laboratory and University of California, Physics Division MS50B-6227, 1 Cyclotron Road, Berkeley, CA 94720, United States of America (United States); Arms, K E [Ohio State University, 191 West Woodruff Ave, Columbus, OH 43210-1117, United States of America (United States); Barberis, D; Beccherle, R B [INFN Genova, via Dodecaneso 33, IT - 16146 Genova (Italy); Bazalova, M [Institute of Physics, Academy of Sciences of the Czech Republic Na Slovance 2, CZ - 18221 Praha 8 (Czech Republic); Becks, K H; Bellina, F [Bergische Universitaet, Fachbereich C, Physik Postfach 100127, Gauss-Strasse 20, D- 42097 Wuppertal (Germany); Behera, P K [203 VAN ALLEN HALL, IOWA CITY IA 52242-1479, United States of America (United States)], E-mail: MGGilchriese@lbl.gov (and others)

    2008-07-15

    The silicon pixel tracking system for the ATLAS experiment at the Large Hadron Collider is described and the performance requirements are summarized. Detailed descriptions of the pixel detector electronics and the silicon sensors are given. The design, fabrication, assembly and performance of the pixel detector modules are presented. Data obtained from test beams as well as studies using cosmic rays are also discussed.

  20. ATLAS Pixel Opto-Electronics

    CERN Document Server

    Arms, K E; Gan, K K; Holder, M; Jackson, P; Johnson, M; Kagan, H; Kass, R; Rahimi, A M; Roggenbuck, A; Rush, C; Schade, P; Smith, S; Ter-Antonian, R; Ziolkowski, M; Zoeller, M M

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 micron CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results of the performance of these chips, including irradiation with 24 GeV protons up to 61 Mrad (2.3 x 10e15 p/cm^2).

  1. Front-end electronics for imaging detectors

    CERN Document Server

    Geronimo, G D; Radeka, V; Yu, B

    2001-01-01

    Front-end electronics for imaging detectors with large numbers of pixels (10 sup 5 -10 sup 7) is reviewed. The noise limits as a function of detector capacitance and power dissipation are presented for CMOS technology. Active matrix flat panel imagers (AMFPIs) are discussed and their potential noise performance is illustrated.

  2. Development of an analogue optical link for the front-end read-out of the ATLAS electromagnetic calorimeter

    CERN Document Server

    Dinkespiler, B; Olivetto, C; Martin, O; Mirea, A; Monnier, E; Tisserant, S; Wielers, M; Andrieux, M L; Ballon, J; Collot, J; Patti, A; Eek, L O; Go, A; Lund-Jensen, B; Pearce, M; Söderqvist, J; Coulon, J P

    1999-01-01

    We have developed an analogue optical data transmission system intended to meet the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. Eight-way demonstrators have been built and tested. The link uses arrays of VCSEL diodes as the optical emitters, coupled to a 70 m long fibre ribbon to simulate the distance between the detector and the control room. The receiver is based around a custom-designed PIN photodiode array. We describe here the final results of laboratory tests on a demonstrator, laying stress on the VCSEL-to-fibre coupling issues, and the overall performance of the full link. A 9-bit dynamic range is achieved, with a 5on-linearity.

  3. Commissioning of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Golling, Tobias

    2008-09-01

    The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and summer 2008, and is ready for the imminent LHC turn-on. The highlights of the past and future commissioning activities of the ATLAS pixel system are presented.

  4. Results from the commissioning of the ATLAS Pixel detector

    CERN Document Server

    Biesiada, J

    2010-01-01

    The ATLAS Pixel detector is a high-resolution, low-noise silicon-based device designed to provide tracking and vertexing information within a distance of 12 cm from the LHC beam axis. It consists of approximately 80 million pixel channels with radiation-hard front-end electronics connected through optical fibers to a custom-controlled DAQ system away from the detector. Following the successful installation of the detector in June 2007, an intense commissioning period was conducted in the year 2008 and more than 400,000 cosmic-ray tracks were recorded in conjunction with other ATLAS sub-detectors. By the end of the year, 96% of the detector was tuned, calibrated, and taking data at 99.8% tracking hit efficiency and with noise occupancy at the 10^-10 level. We present here the results of the commissioning, calibration, and data-taking as well as the outlook for future performance with LHC collision-based data.

  5. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  6. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  7. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Rossi, Leonardo Paolo; The ATLAS collaboration

    2018-01-01

    The upgrade of the ATLAS experiment for the operation at the High Luminosity Large Hadron Collider requires a new and more performant inner tracker, the ITk. The innermost part of this tracker will be built using silicon pixel detectors. This paper describes the ITk pixel project, which, after few years of design and test e ort, is now defined in detail.

  8. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  9. Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2014-09-01

    ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

  10. EXCALIBUR: a small-pixel photon counting area detector for coherent X-ray diffraction - Front-end design, fabrication and characterisation

    Science.gov (United States)

    Marchal, J.; Horswell, I.; Willis, B.; Plackett, R.; Gimenez, E. N.; Spiers, J.; Ballard, D.; Booker, P.; Thompson, J. A.; Gibbons, P.; Burge, S. R.; Nicholls, T.; Lipp, J.; Tartoni, N.

    2013-03-01

    Coherent X-ray diffraction experiments on synchrotron X-ray beamlines require detectors with high spatial resolution and large detection area. The read-out chip developed by the MEDIPIX3 collaboration offers a small pixel size of 55 microns resulting in a very high spatial resolution when coupled to a direct X-ray conversion segmented silicon sensor. MEDIPIX3 assemblies present also the advantages of hybrid pixel detectors working in single photon counting mode: noiseless imaging, large dynamic range, extremely high frame rate. The EXCALIBUR detector is under development for the X-ray Coherence and Imaging Beamline I13 of the Diamond Light Source. This new detector consists of three modules, each with 16 MEDIPIX3 chips which can be read-out at 100 frames per second in continuous mode or 1000 frames per second in burst mode. In each module, the sensor is a large single silicon die covering 2 rows of 8 individual MEDIPIX3 read-out chips and provides a continuous active detection region within a module. Each module includes 1 million solder bumps connecting the 55 microns pixels of the silicon sensor to the 55 microns pixels of the 16 MEDIPIX3 read-out chips. The detection area of the 3-module EXCALIBUR detector is 115 mm × 100 mm with a small 6.8 mm wide inactive region between modules. Each detector module is connected to 2 FPGA read-out boards via a flexi-rigid circuit to allow a fully parallel read-out of the 16 MEDIPIX3 chips. The 6 FPGA read-out boards used in the EXCALIBUR detector are interfaced to 6 computing nodes via 10Gbit/s fibre-optic links to maintain the very high frame-rate capability. The standard suite of EPICS control software is used to operate the detector and to integrate it with the Diamond Light Source beamline software environment. This article describes the design, fabrication and characterisation of the MEDIPIX3-based modules composing the EXCALIBUR detector.

  11. Commissioning Perspectives for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2067982; Klingenberg, Reiner

    2007-01-01

    The ATLAS Pixel Detector, the innermost sub-detector of the ATLAS experiment at the Large Hadron Collider, CERN, is an 80 million channel silicon pixel tracking detector designed for high-precision charged particle tracking and secondary vertex reconstruction. It was installed in the ATLAS experiment and commissioning for the first proton-proton collision data taking in 2008 has begun. Due to the complex layout and limited accessibility, quality assurance measurements were continuously performed during production and assembly to ensure that no problematic components are integrated. The assembly of the detector at CERN and related quality assurance measurement results, including comparison to previous production measurements, will be presented. In order to verify that the integrated detector, its data acquisition readout chain, the ancillary services and cooling system as well as the detector control and data acquisition software perform together as expected approximately 8% of the detector system was progress...

  12. Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

    Science.gov (United States)

    Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

    2018-01-01

    The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

  13. ATLAS Tracker and Pixel Operational Experience

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00222525; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pile-up and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker, are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  14. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  15. Upgrades of the ATLAS Pixel Detector

    CERN Document Server

    Hügging, F; The ATLAS collaboration

    2013-01-01

    The upgrade for the ATLAS detector will undergo different phases towards HL-LHC. The first upgrade for the Pixel Detector (Phase 1) consists in the construction of a new pixel layer, which will be installed during the 1st long shutdown of the LHC machine (LS1) in 2013/14. The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of about 3.2 cm. The IBL requires the development of several new technologies to cope with the increase of radiation and pixel occupancy as well as to improve the physics performance of the existing pixel detector. The pixel size is reduced and the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system. For Phase 2 upgrade of LHC a complete new 4-layer pixel system is planned as part of a new all silicon Inner Detector. The increase in luminosity to about $5\\cdot 10^{34}$cm$^{-2}$s$^{-1}$ together with a total expected lifetime of ab...

  16. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    The calibration of the Pixel detector fulfills two main purposes: to tune front-end registers for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied toghether to chips with dierent characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  17. Optical Link of the Atlas Pixel Detector

    CERN Document Server

    Gan, K.K.; Jackson, P.D.; Johnson, M.; Kagan, H.; Buchholz, P.; Holder, M.; Roggenbuck, A.; Schade, P.

    2007-01-01

    The on-detector optical link of the ATLAS pixel detector contains radiation-hard receiver chips to decode bi-phase marked signals received on PIN arrays and data transmitter chips to drive VCSEL arrays. The components are mounted on hybrid boards (opto-boards). We present results from the irradiation studies with 24 GeV protons up to 32 Mrad (1.2 x 10^15 p/cm^2) and the experience from the production.

  18. ATLAS ITk and new pixel sensors technologies

    CERN Document Server

    Gaudiello, A

    2016-01-01

    During the 2023–2024 shutdown, the Large Hadron Collider (LHC) will be upgraded to reach an instantaneous luminosity up to 7×10$^{34}$ cm$^{−2}$s$^{−1}$. This upgrade of the accelerator is called High-Luminosity LHC (HL-LHC). The ATLAS detector will be changed to meet the challenges of HL-LHC: an average of 200 pile-up events in every bunch crossing, and an integrated luminosity of 3000 fb $^{−1}$ over ten years. The HL-LHC luminosity conditions are too extreme for the current silicon (pixel and strip) detectors and straw tube transition radiation tracker (TRT) of the current ATLAS tracking system. Therefore the ATLAS inner tracker is being completely rebuilt for data-taking and the new system is called Inner Tracker (ITk). During this upgrade the TRT will be removed in favor of an all-new all-silicon tracker composed only by strip and pixel detectors. An overview of new layouts in study will be reported and the new pixel sensor technologies in development will be explained.

  19. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, M

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3•10^34 cm^−2 s^ −1 and IBL is designed for an integrated luminosity of 700 fb^−1 . This corresponds to an expected fluence of 5 • 10^15 1 MeV n_eqcm^−2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design...

  20. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, Malte

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3centerdot1034 cm-2s-1 and IBL is designed for an integrated luminosity of 700 fb-1. This corresponds to an expected fluence of 5centerdot1015 1 MeV neqcm-2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design of the ...

  1. ATLAS rewards two pixel detector suppliers

    CERN Multimedia

    2007-01-01

    Peter Jenni, ATLAS spokesperson, presented the ATLAS supplier award to Herbert Reichl, IZM director, and to Simonetta Di Gioia, from the SELEX company.Two of ATLAS’ suppliers were awarded prizes at a ceremony on Wednesday 13 June attended by representatives of the experiment’s management and of CERN. The prizes went to the Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM) in Berlin and the company SELEX Sistemi Integrati in Rome for the manufacture of modules for the ATLAS pixel detector. SELEX supplied 1500 of the modules for the tracker, while IZM produced a further 1300. The modules, each made up of 46080 channels, form the active part of the ATLAS pixel detector. IZM and SELEX received the awards for the excellent quality of their work: the average number of faulty channels per module was less than 2.10-3. They also stayed within budget and on schedule. The difficulty they faced was designing modules based on electronic components and sensor...

  2. The Phase II ATLAS ITk Pixel Upgrade

    CERN Document Server

    Terzo, Stefano; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the "ITk" (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and and ring-shaped supports in the endcap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m$^2$ , depending on the final layout choice, which is expected to take place in early 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel-endcap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as $|\\eta| < 4$. Supporting structures will be ...

  3. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

  4. The ATLAS Pixel nSQP Readout Chain

    CERN Document Server

    Welch, S; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel New Service Quarter Panel (nSQP) project aims to deliver replacements for all on-detector services of the ATLAS Pixel Detector. The nSQPs will have replacements for the electro-optical converters. The replacement devices are LVDS transceiver boards (E-Boards) and they communicate with the existing ATLAS Pixel MCC chips over the original type 0 cables. In the other direction the E-Boards communicate over a 6.6 meter long transmission line with the VCSEL driver chips in the new electro-optical converters. These converters have been relocated to a region that is much more accessible.

  5. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  6. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

    2016-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  7. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  8. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Rossi, Leonardo Paolo; The ATLAS collaboration

    2018-01-01

    The entire tracking system of the ATLAS experiment will be replaced in 2025 during the LHC Phase-II shutdown by an all-silicon detector called the “ITk” (Inner Tracker). The innermost part of ITk will be a pixel detector containing about 12.5m2 of sensitive silicon. The silicon modules are arranged on 5 layers of stave-like support structures in the most central region and ring-shaped supports in the endcap regions covering out to |η| < 4; a mid-eta region (~1 < |η| < ~2) will be occupied by novel inclined support structures which keep the angle of incidence of high-momentum tracks more closely normal to the sensitive silicon. All supports will be based on low mass, highly stable and highly thermally-conductive carbon-based materials cooled by evaporative carbon dioxide flowing in thin-walled titanium pipes. An extensive prototyping programme, including thermal, mechanical and electrical studies, is being carried out on all the types of support structures. The HL-LHC is expected to deliver up t...

  9. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Benoit, Mathieu; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The innermost portion of the ITk will consist of a pixel detector with stave-like support structures in the most central region and ring-shaped supports in the endcap regions; there may also be novel inclined support structures in the barrel-endcap overlap regions. The new detector could have as much as 14 m2 of sensitive silicon. Support structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide. The ITk will be instrumented with new sensors and readout electronics to provide improved tracking performance compared to the current detector. All the module components must be performant enough and robust enough to cope with the expected high particle multiplicity and severe radiation background of the High-Luminosity LHC. Readout...

  10. Dynamic Efficiency Measurements for Irradiated ATLAS Pixel Single Chip Modules

    CERN Document Server

    Pfaff, Mike; Grosse-Knetter, Jorn

    2011-01-01

    The ATLAS pixel detector is the innermost subdetector of the ATLAS experiment. Due to this, the pixel detector has to be particularly radiation hard. In this diploma thesis effects on the sensor and the electronics which are caused by irradiation are examined. It is shown how the behaviour changes between an unirradiated sample and a irradiated sample, which was treated with the same radiation dose that is expected at the end of the lifetime of ATLAS. For this study a laser system, which is used for dynamic efficiency measurements was constructed. Furthermore, the behaviour of the noise during the detection of a particle was evaluated studied.

  11. End-Users, Front Ends and Librarians.

    Science.gov (United States)

    Bourne, Donna E.

    1989-01-01

    The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

  12. Status and new layout of the ATLAS pixel detector

    CERN Document Server

    Netchaeva, P

    2002-01-01

    The ATLAS pixel detector is based on a set of radiation-hard electronics chips able to resist a dose of 500 kGy. The implementation of these chips in the DMILL technology did not give the expected results. Re-design of the radiation-hard chips in Deep SubMicron technology is ongoing, but has implied a one and a half year delay in an already tight schedule. Major layout changes have therefore been necessary to allow installation of the ATLAS pixel detector at LHC start-up. This paper illustrates the status of the ATLAS pixel project, die motivations for the new layout, the way this should be implemented and the prototype fabrication and testing. (4 refs).

  13. LBNL delivers front end of SNS

    CERN Document Server

    Keller, R

    2002-01-01

    After four years of construction, the linear accelerator injector that will form the front end of the US SNS has been commissioned at LBNL. Fulfilling all its major design requirements and performing reliably, the system was shipped by July.

  14. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

    CERN Document Server

    Rubinskiy, Igor

    2013-01-01

    The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013-14). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase of the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the pixel detector. An overview of the sensor technologies’ qualification with particular emphasis on irradiation and beam tests are presented.

  15. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

    CERN Document Server

    Rubinskiy, I

    2013-01-01

    The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–2014). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase in the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector. An overview of the sensor technologies' qualification with particular emphasis on irradiation and beam tests is presented.

  16. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Martin, Christopher Blake; The ATLAS collaboration

    2018-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 1.3 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  17. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Martin, Christopher Blake; The ATLAS collaboration

    2018-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of $1.3\\times10^{34}\\text{cm}^{{-2}}\\text{s}^{{-1}}$ recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarized, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  18. ATLAS Inner Detector (Pixel Detector and Silicon Tracker)

    CERN Multimedia

    ATLAS Outreach

    2006-01-01

    To raise awareness of the basic functions of the Pixel Detector and Silicon Tracker in the ATLAS detector on the LHC at CERN. This colorful 3D animation is an excerpt from the film "ATLAS-Episode II, The Particles Strike Back." Shot with a bug's eye view of the inside of the detector. The viewer is taken on a tour of the inner workings of the detector, seeing critical pieces of the detector and hearing short explanations of how each works.

  19. New results on diamond pixel sensors using ATLAS frontend electronics

    CERN Document Server

    Keil, Markus; Berdermann, E; Bergonzo, P; de Boer, Wim; Bogani, F; Borchi, E; Brambilla, A; Bruzzi, Mara; Colledani, C; Conway, J; D'Angelo, P; Dabrowski, W; Delpierre, P A; Dulinski, W

    2003-01-01

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

  20. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Yang, Hongtao; The ATLAS collaboration

    2018-01-01

    In this presentation, I will discuss the operation of ATLAS Pixel Detector during Run 2 proton-proton data-taking at √s=13 TeV in 2017. The topics to be covered include 1) the bandwidth issue and how it is mitigated through readout upgrade and threshold adjustment; 2) the auto-corrective actions; 3) monitoring of radiation effects.

  1. A Novel Optical Package for ATLAS Pixel Detector

    CERN Document Server

    Gan, K K

    2001-01-01

    An optical package of novel design has been developed for the ATLAS pixel detector. The package contains two VCSELs and one PIN diode to transmit and receive optical signals. The design is based on a simple connector-type concept and is made of radiation-hard material. Several packages have been fabricated and show promising results.

  2. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is preparing for an extensive modification of its detectors in the course of the planned HL-LHC accelerator upgrade around 2025. The ATLAS upgrade includes the replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will be a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in 2017. In this paper an overview of the ongoing R\\&D activities on modules and electronics for the ATLAS ITk is given including the main developments and achievements in silicon planar and 3D sensor technologies, readout and power challenges.

  3. Results from the Commissioning of the ATLAS Pixel Detector

    CERN Document Server

    Strandberg, S

    2009-01-01

    The ATLAS pixel detector is a high resolution, silicon based, tracking detector with its innermost layer located only 5 cm away from the ATLAS interaction point. It is designed to provide good hit resolution and low noise, both important qualities for pattern recognition and for finding secondary vertices originating from decays of long-lived particles. The pixel detector has 80 million readout channels and is built up of three barrel layers and six disks, three on each side of the barrel. The detector was installed in the center of ATLAS in June 2007 and is currently being calibrated and commissioned. Details from the installation, commissioning and calibration are presented together with the current status.

  4. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Nachman, Benjamin Philip; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of $10^{15}$ 1 MeV $n_\\mathrm{eq}/\\mathrm{cm}^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This talk presents a digitization model that includes radiation damage effects to the ATLAS Pixel sensors for the first time. After a thorough description of the setup, predictions for basic Pixel cluster properties are presented alongside first validation studies with Run 2 collision data.

  5. Planar Pixel Sensors for the ATLAS Upgrade: Beam Tests results

    CERN Document Server

    Weingarten, J

    2012-01-01

    The performance of planar silicon pixel sensors, in development for the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades, has been examined in a series of beam tests at the CERN SPS facilities since 2009. Salient results are reported on the key parameters, including the spatial resolution, the charge collection and the charge sharing between adjacent cells, for different bulk materials and sensor geometries. Measurements are presented for n+-in-n pixel sensors irradiated with a range of fluences and for p-type silicon sensors with various layouts from different vendors. All tested sensors were connected via bump-bonding to the ATLAS Pixel read-out chip. The tests reveal that both n-type and p-type planar sensors are able to collect significant charge even after the lifetime fluence expected at the HL-LHC.

  6. Online calibrations and performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

  7. Production accompanying testing of the ATLAS Pixel module

    CERN Document Server

    AUTHOR|(CDS)2067982; Klingenberg, R

    2004-01-01

    The ATLAS Pixel detector, innermost sub-detector of the ATLAS experiment at LHC, CERN, can be sensibly tested in its entirety the first time after its installation in 2006. Because of the poor accessibility (probably once per year) of the Pixel detector and tight scheduling the replacement of damaged modules after integration as well as during operation will become a highly exposed business. Therefore and to ensure that no affected parts will be used in following production steps, it is necessary that each production step is accompanied by testing the components before assembly and make sure the operativeness afterwards. Probably 300 of about total 2000 semiconductor hybrid pixel detector modules will be build at the Universität Dortmund. Thus a production test setup has been build up and examined before starting serial production. These tests contain the characterization and inspection of the module components and the module itself under different environmental conditions and diverse operating parameters. O...

  8. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  9. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development. This con......Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  10. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. In the ATLAS track reconstruction algorithm, an artificial neural network is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The robustness of the neural network algorithm is presented, probing its sensitivity to uncertainties in the detector conditions. The robustness is studied by evaluating the stability of the algorithm's performance under a range of variations in the inputs to the neural networks. Within reasonable variation magnitudes, the neural networks prove to be robust to most variation types.

  11. Operational experience of ATLAS SCT and Pixel Detector

    CERN Document Server

    Kocian, Martin; The ATLAS collaboration

    2017-01-01

    The ATLAS Inner Detector based on silicon sensors is consisting of a strip detector (SCT) and a pixel detector. It is the crucial component for vertexing and tracking in the ATLAS experiment. With the excellent performance of the LHC well beyond the original specification the silicon tracking detectors are facing substantial challenges in terms of data acquisition, radiation damage to the sensors, and SEUs in the readout ASICs. The approaches on how the detector systems cope with the demands of high luminosity operation while maintaining excellent performance through hardware upgrades, software and firmware algorithms, and operational settings, are presented.

  12. Online calibration and performance of the ATLAS Pixel Detector

    Energy Technology Data Exchange (ETDEWEB)

    Keil, Markus, E-mail: markus.keil@cern.ch [CERN, 1211 Geneva 23 (Switzerland); II. Physikalisches Institut, Universitaet Goettingen, Friedrich-Hund-Platz 1, 37077 Goettingen (Germany)

    2011-09-11

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  13. Online Calibration and Performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  14. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

  15. Dispersion management of the SULF front end

    Science.gov (United States)

    Li, Shuai; Wang, Cheng; Liu, Yanqi; Xu, Yi; Liu, Zhengzheng; Lu, Jun; Li, Yanyan; Liu, Xingyan; Li, Zhaoyang; Leng, Yuxin; Li, Ruxin

    2017-04-01

    To manage dispersion of the front end in the Shanghai Superintense Ultrafast Laser Facility (SULF), which is a large-scale project aimed at delivering 10 PW laser pulses, a stretcher based on a combination of a grating and a prism (grism) pair is inserted between an Öffner-triplet-type stretcher and a regenerative amplifier to reduce high-order dispersion introduced by optical materials at the amplification stage. The alignment of the grism pair is implemented by controlling the far-field pattern of the output beam of the grism pair. The energy of the front end reaches up to 7 J at a 1-Hz repetition rate. Experimental results show that the pulse duration can be compressed to 22.4 fs and the spectral distortion over the spectrum is less than 2.25 rad.

  16. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  17. Pixel detector modules performance for ATLAS IBL and future pixel detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00355104; Pernegger, Heinz

    2015-11-06

    The ATLAS Detector is one of the four big particle physics experiments at CERN’s LHC. Its innermost tracking system consisted of the 3-Layer silicon Pixel Detector (~80M readout channels) in the first run (2010-2012). Over the past two years it was refurbished and equipped with new services as well as a new beam monitor. The major upgrade, however, was the Insertable B-Layer (IBL). It adds ~12M readout channels for improved vertexing, tracking robustness and b-tagging performance for the upcoming runs, before the high luminosity upgrade of the LHC will take place. This thesis covers two main aspects of Pixel detector performance studies: The main work was the planning, commissioning and operation of a test bench that meets the requirements of current pixel detector components. Each newly built ATLAS IBL stave was thoroughly tested, following a specifically developed procedure, and initially calibrated in that setup. A variety of production accompanying measurements as well as preliminary results after integ...

  18. Modeling radiation damage to pixel sensors in the ATLAS detector

    CERN Document Server

    Ducourthial, Audrey; The ATLAS collaboration

    2017-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15}n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside ...

  19. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Ducourthial, Audrey; The ATLAS collaboration

    2017-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15} n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside...

  20. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

  1. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in 2017. A new on-detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on-going R&D within the ATLAS ITK project towards the new pixel modules and the off-detector electronics. Planar and 3D sensors are being re-designed with cell sizes of 50x50 or 25x100 μm2, compatible with the RD53 chip. A sensor thickness equal or less th...

  2. Development of a Micro Pixel Chamber for the ATLAS Upgrade

    CERN Document Server

    Ochi, Atsuhiko; Komai, Hidetoshi; Edo, Yuki; Yamaguchi, Takahiro

    2012-01-01

    The Micro Pixel Chamber (μ-PIC) is being developed a sacandidate for the muon system of the ATLAS detector for upgrading in LHC experiments. The μ-PIC is a micro-pattern gaseous detector that doesn’t have floating structure such as wires, mesh, or foil. This detector can be made by printed-circuit-board (PCB) technology, which is commercially available and suited for mass production. Operation tests have been performed under high flux neutrons under similar conditions to the ATLAS cavern. Spark rates are measured using several gas mixtures under 7 MeV neutron irradiation, and good properties were observed using neon, ethane, and CF4 mixture of gases.Using resistive materials as electrodes, we are also developing a new μ-PIC, which is not expected to damage the electrodes in the case of discharge sparks.

  3. ATLAS Phase-II Upgrade Pixel Data Transmission Development

    CERN Document Server

    Nielsen, Jason; The ATLAS collaboration

    2017-01-01

    The current tracking system of the ATLAS experiment will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics indicates that the planned trigger rate of 1 MHz will require readout speeds up to 5.12 Gb/s per data link. The high-radiation environment precludes optical data transmission, so the first part of the data transmission has to be implemented electrically, over a 6-m distance between the pixel modules and the optical transceivers. Several high-speed electrical data transmission solutions involving small-gauge wire cables or flexible circuits have been prototyped and characterized. A combination of carefully-selected physical layers and aggressive signal conditioning are required to achieve the proposed specifications.

  4. ATLAS Phase-II Upgrade Pixel Data Transmission Development

    CERN Document Server

    Nielsen, Jason; The ATLAS collaboration

    2017-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  5. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off de...

  6. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Rummler, Andr{e}; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

  7. The Phase-II ATLAS ITk pixel upgrade

    Science.gov (United States)

    Terzo, S.

    2017-07-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase-II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 m2 of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| chip. The pixel off-detector readout electronics will be implemented in the framework of the general ATLAS trigger and DAQ system. A readout speed of up to 5 Gb/s per data link will be needed in the innermost layers going down to 640 Mb/s for the outermost. Because of the very high radiation level inside the detector, the first part of the transmission has to be implemented electrically, with signals converted for optical transmission at larger radii. Extensive tests are being carried out to prove the feasibility of implementing serial powering, which has been chosen as the baseline for the ITk pixel system due to the reduced material in the servicing cables foreseen for this option.

  8. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  9. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  10. The ALICE TPC front end electronics

    CERN Document Server

    Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

    2004-01-01

    In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

  11. Transfer Function and Fluorescence Measurements on New CMOS Pixel Sensor for ATLAS

    CERN Document Server

    Kaemingk, Michael

    2017-01-01

    A new generation of pixel sensors is being designed for the phase II upgrade of the ATLAS Inner Tracker (ITk). These pixel sensors are being tested to ensure that they meet the demands of the ATLAS detector. As a summer student, I was involved in some of the measurements taken for this purpose.

  12. Pixel-Cluster Counting Luminosity Measurement In ATLAS

    CERN Document Server

    AUTHOR|(SzGeCERN)782710; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measure- ments of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster- counting method a...

  13. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Rossini, Lorenzo; The ATLAS collaboration

    2018-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of 10^15 neq/cm^2 and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current and future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time and considers both planar and 3D sensor designs. In addition to thoroughly describing the setup, we compare predictions for b...

  14. Pixel-Cluster Counting Luminosity Measurement in ATLAS

    CERN Document Server

    McCormack, William Patrick; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measurements of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster-counting method are ...

  15. The CMS Tracker Readout Front End Driver

    CERN Document Server

    Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

    2004-01-01

    The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

  16. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    Smart, Ben; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline. High-eta particles will therefore hit these sensors at shallow angles, leaving elongated charge clusters. The length of such a charge cluster can be used to estimate the angle of the passing particle. This information can then be used in track reconstruction to improve tracking efficiency and reduce fake rates. Inclined designs ...

  17. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00237541; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362 mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline, while inclined designs have sensors angled such that they point towards the interaction point. The relative advantages and challenges of these two classes of designs will be examined in this paper, along with the mechanical solutions being considered. Thermal management, radiation-length mapping, and electrical services will al...

  18. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  19. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    OpenAIRE

    Bourrion, O.; Bosson, G.; Grignon, C.; Richer, J. P.; Guillaudin, O.; Mayet, F.; Billard, J.; Santos, D.

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i...

  20. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mathes, Markus

    2008-12-15

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  1. The Phase II ATLAS Pixel Upgrade: The Inner Tracker (ITk)

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m^2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to eta < 3.2 and two to eta < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions. Support...

  2. The Phase-II ATLAS ITk Pixel Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00349918; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase~2 shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 $\\mathrm{m^2}$ of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| $<4$. Supporting structures will be based on low mass, highly stabl...

  3. ATLAS Pixel-Optoboard Production and Simulation Studies

    CERN Document Server

    Nderitu, Simon

    At CERN, a Large collider will collide protons at high energies. There are four experiments being built to study the particle properties from the collision. The ATLAS experiment is the largest. It has many sub detectors among which is the Pixel detector which is the innermost part. The Pixel detector has eighty million channels that have to be read out. An optical link is utilized for the read out. It has optical to electronic interfaces both on the detector and off the detector at the counting room. The component on the detector in called the opto-board. This work discusses the production testing of the opto-boards to be installed on the detector. A total of 300 opto-boards including spares have been produced. The production was done in three laboratories among which is the laboratory at the University of Wuppertal which had the responsibility of Post production testing of all the one third of the total opto-boards. The results are discussed in this work. The analysis of the results from the total productio...

  4. The front-end electronics for LHCb calorimeters

    CERN Document Server

    Breton, D

    2002-01-01

    For the readout of the calorimeters of the LHCb experiment at CERN, specific front-end electronics have been designed. In particular, three different front-end analog chips were studied respectively for the ECAL/HCAL, preshower and scintillator pad detector. We will present the three front-end electronic chains, point out their specific requirements together with their common purpose, and describe the corresponding ASICs. (6 refs).

  5. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  6. A programmable front-end system for arrays of bolometers

    Science.gov (United States)

    Alessandrello, A.; Brofferio, C.; Bucci, C.; Cremonesi, O.; Giuliani, A.; Nucciotti, A.; Pavan, M.; Perego, M.; Pessina, G.; Pirro, S.; Previtali, E.; Vanzini, M.

    2000-04-01

    We report on a new front-end system developed to readout an array of large mass bolometers. The front-end allows setting all the necessary parameters for each detector by remote control. A special circuit, also fired remotely, has been developed in order to adjust the output voltage, allowing the DC coupling to the detector.

  7. A programmable front-end system for arrays of bolometers

    Energy Technology Data Exchange (ETDEWEB)

    Alessandrello, A.; Brofferio, C.; Bucci, C.; Cremonesi, O.; Giuliani, A.; Nucciotti, A.; Pavan, M.; Perego, M.; Pessina, G. E-mail: pessina@mi.infn.it; Pirro, S.; Previtali, E.; Vanzini, M

    2000-04-07

    We report on a new front-end system developed to readout an array of large mass bolometers. The front-end allows setting all the necessary parameters for each detector by remote control. A special circuit, also fired remotely, has been developed in order to adjust the output voltage, allowing the DC coupling to the detector.

  8. Cost of pedestrian and bicycle accidents involving car front ends.

    NARCIS (Netherlands)

    Kampen, L.T.B. van & Huijbers, J.J.W.

    1995-01-01

    A cost study has been carried out, based on Dutch insurance data of payments to victims (pedestrians and cyclists) of collisions against car front ends. The results of this study will be used for a cost-benefit analysis of a proposed amendment (a series of car front end crash tests) to the existing

  9. MMIC tuned front-end for a coherent optical receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

    1993-01-01

    A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

  10. A via last TSV process applied to ATLAS pixel detector modules: proof of principle demonstration

    CERN Document Server

    Barbero, M; Gonella, L; Hügging, F; Krüger, H; Rothermund, M; Wermes, N

    2012-01-01

    Via last Through Silicon Vias (TSVs) can be exploited to build low material modules for the upgrades of the ATLAS pixel detector at the High Luminosity LHC. To prove this concept a via last TSV process is demonstrated on ATLAS pixel readout wafers. Demonstrator modules featuring 90 mm thin readout chips with TSVs are operated using the connection from the back side of the chip. This paper illustrates the via formation process and the results from the characterization of modules with TSVs.

  11. Development and Characterization of Diamond and 3D-Silicon Pixel Detectors with ATLAS-Pixel Readout Electronics

    CERN Document Server

    Mathes, Markus

    2008-01-01

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10^16 particles per cm^2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 × 50 um^2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm^2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 × 6 cm^2). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection ...

  12. Achievements of the ATLAS upgrade planar pixel sensors R and D project

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy)

    2014-11-21

    This paper reports on recent accomplishments and ongoing work of the ATLAS Planar Pixel Sensors R and D project. Special attention is given in particular to new testbeam results obtained with highly irradiated sensors, developments in the field of slim and active edges and first step towards prototypes of future pixel modules.

  13. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  14. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  15. Status of the ATLAS Pixel Detector and its performance after three years of operation

    CERN Document Server

    Favareto, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is very important for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, and a good alignment allows high quality track resolution

  16. Simulations of 3D-Si sensors for the innermost layer of the ATLAS pixel upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Baselga, M.; Pellegrini, G., E-mail: giulio.pellegrini@imb-cnm.csic.es; Quirion, D.

    2017-03-01

    The LHC is expected to reach luminosities up to 3000 fb{sup −1} and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non-passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade. It shows the charge collection response before and after irradiation, and the response of 3D-Si sensors located at large η angles.

  17. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  18. Indico front-end: From spaghetti to lasagna

    CERN Multimedia

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  19. Testbeam Measurements with Pixel Sensors for the ATLAS Insertable b-Layer Project

    CERN Document Server

    George, Matthias; Quadt, Arnulf

    During the current long machine shutdown of the Large Hadron Collider (LHC) at CERN (Geneva), the innermost part of the ATLAS experiment, the pixel detector, is upgraded. The existing ATLAS pixel system is equipped with silicon sensors, organized in three barrel layers and three end cap disks on either side. To cope with the higher instantaneous luminosity in the future and for compensation of radiation damages due to past and near future running time of the experiment, a new fourth pixel detector layer is inserted into the existing system. This additional pixel layer is called “Insertable b-Layer” (IBL). The IBL is a detector system, based on silicon pixel sensors. Due to the smaller radius, compared to all other detectors of the ATLAS experiment, it has to be more radiation tolerant, than e.g. the current pixel layers. Furthermore, a reduced pixel size is necessary to cope with the expected higher particle flux. During the planning phase for the IBL upgrade, three different sensor technologies were comp...

  20. Overview of Silicon Pixel Sensor Development for the ATLAS Insertable B-Layer (IBL)

    CERN Document Server

    Grinstein, S; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost part of the ATLAS tracking system and is critical for track and vertex reconstruction. In order to preserve the tracking performance notwithstanding the increasing instantaneous luminosity delivered by the LHC, ATLAS plans to introduce a new pixel layer (IBL) mounted directly on a reduced diameter beam pipe. The IBL will have to sustain an estimated radiation dose, including safety factors, of $5 imes 10^{15}$~n$_{eq}$/cm$^2$. Two sensor technologies are currently being considered for the IBL, planar n-on-n slim edge and 3D double sided designs. Results of the characterization, irradiation and beam test studies of IBL pixel devices are presented.

  1. ALMA North American Integration Center Front-End Test System

    Science.gov (United States)

    Ediss, Geoffrey A.; Crabtree, Joshua; Crady, Kirk; Gaines, Erik; McLeod, Morgan; Morris, Greg; Williams, Rick; Perfetto, Antonio; Webber, John

    2010-10-01

    The Atacama Large Millimeter/submillimeter (ALMA) Array Front End (FE) system is the first element in a complex chain of signal receiving, conversion, processing and recording. 70 Front Ends will be required for the project. The Front End is designed to receive signals in ten different frequency bands. In the initial phase of operations, the antennas will be fully equipped with six bands. These are Band 3 (84-116 GHz), Band 4 (125-163 GHz), Band 6 (211-275 GHz), Band 7 (275-373 GHz), Band 8 (385-500 GHz) and Band 9 (602-720 GHz). It is planned to equip the antennas with the missing bands at a later stage of ALMA operations, with a few Band 5 (163-211 GHz) and Band 10 (787-950 GHz) receivers in use before the end of the construction project. The ALMA Front End is far superior to any existing receiver systems; spin-offs of the ALMA prototypes are leading to improved sensitivities in existing millimeter and submillimeter observatories. The Front End units are comprised of numerous elements, produced at different locations in Europe, North America and East Asia and are integrated at several Front End integration centers (FEIC) to insure timely delivery of all the units to Chile. The North American FEIC (NA FEIC) is at the National Radio Astronomy Observatory facility in Charlottesville, Virginia, USA. This paper describes the design and performance of the test set used at the NA FEIC to check the performance of the Front Ends, following integration and prior to shipment to Chile.

  2. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  3. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00232885; The ATLAS collaboration; Banerjee, Swagato; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian Choate; Wu, Sau Lan; Yang, Hongtao

    2015-01-01

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN.

  4. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Giugliarelli, Gilberto; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  5. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Wallangen, Veronica; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10$^{15}$ n$_\\mathrm{eq}$/cm$^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This work presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS detector.

  6. Operational Experience and Performance with the ATLAS Pixel detector with emphasis on radiation damage

    CERN Document Server

    Garcia Pascual, Juan Antonio; The ATLAS collaboration

    2017-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 1.3 x 10$^{34}$ cm$^{-2}$ s$^{-1}$ recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  7. Radiation Damage Modeling for 3D Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Wallangen, Veronica; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  8. Operational Experience and Performance with the ATLAS Pixel detector with emphasis on radiation damage

    CERN Document Server

    Butti, Pierfrancesco; The ATLAS collaboration

    2017-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 1.3 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  9. Recent results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    AUTHOR|(CDS)2073610

    2011-01-01

    The ATLAS detector has to undergo significant updates at the end of the current decade, in order to withstand the increased occupancy and radiation damage that will be produced by the high-luminosity upgrade of the Large Hadron Collider. In this presentation we give an overview of the recent accomplishments of the R&D activity on the planar pixel sensors for the ATLAS Inner Detector upgrade.

  10. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, M; The ATLAS collaboration

    2011-01-01

    For the ATLAS pixel detector, a fourth hybrid pixel detector layer known as Insertable B-Layer (IBL) is developed, which will be slid into the present pixel detector. Due to the very small distance to the interaction point of about 3.4 cm, the IBL will improve the track reconstruction and vertexing of the pixel detector. In order to handle the extreme particle flux and radiation damage close to the interaction point, new sensor concepts as well as a new readout chip, FE-I4, are currently developed. To reduce the pixel occupancy, the pixel size in FE-I4 is reduced from the 50 x 400 µm² of the readout chip of the current ATLAS pixel detector (FE-I3) to 50 x 250 µm². The FE-I4 active area will cover ~ 2 x 1.7 cm², resulting in 26.880, a nearly ten fold increase in pixel number with respect to FE-I3. This translates into an increased active over inactive area ratio of less than 75% in FE-I3 to 90% in FE-I4. This enables a better, more integrated module concept, with a smaller amount of periphery to achieve a...

  11. Characterisation of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, M; The ATLAS collaboration

    2011-01-01

    For the ATLAS pixel detector, a fourth hybrid pixel detector layer known as Insertable B-Layer (IBL) is developed, which will be slid into the present pixel detector. Due to the very small distance to the interaction point of about 3.4 cm, the IBL will improve the track reconstruction and vertexing of the pixel detector. In order to handle the extreme particle flux and radiation damage close to the interaction point, new sensor concepts as well as a new readout chip, FE-I4, are currently developed. To reduce the pixel occupancy, the pixel size in FE-I4 is reduced from the 50 x 400 µm² of the readout chip of the current ATLAS pixel detector (FE-I3) to 50 x 250 µm². The FE-I4 active area will cover ~ 2 x 1.7 cm², resulting in 26.880, a nearly ten fold increase in pixel number with respect to FE-I3. This translates into an increased active over inactive area ratio of less than 75% in FE-I3 to 90% in FE-I4. This enables a better, more integrated module concept, with a smaller amount of periphery to achieve a...

  12. Concepts for a Muon Accelerator Front-End

    Energy Technology Data Exchange (ETDEWEB)

    Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

    2017-03-16

    We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

  13. CMOS front-end electronics for radiation sensors

    CERN Document Server

    AUTHOR|(CDS)2071026

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  14. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00016406

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. An overview of the refurbishing of the Pixel Detector and of the IBL project as well as early performance tests using cosmic rays and beam data will be presented.

  15. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Savic, N.; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-02-01

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm2). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm2 pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  16. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Savic, N., E-mail: natascha.savic@mpp.mpg.de; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-02-11

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm{sup 2}). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm{sup 2} pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  17. Operational performance and status of the ATLAS pixel detector at the LHC

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  18. Operational Performance and Status of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Jentzsch, J; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  19. Status and future of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Rozanov, A; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  20. Operational Performance and Status of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Jentzsch, J; The ATLAS collaboration

    2014-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experi- ment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individu- ally read out via chips bump-bonded to 1744 n+-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including moni- toring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 · 1033 cm−2s−1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silico...

  1. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00235789; The ATLAS collaboration

    2016-01-01

    During Run-1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This includes the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore a new readout chip and two new sensor technologies (planar and 3D) are used in IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanic...

  2. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  3. The Front-End System For MARE In Milano

    Science.gov (United States)

    Arnaboldi, Claudio; Pessina, Gianluigi

    2009-12-01

    The first phase of MARE consists of 72 μ-bolometers composed each of a crystal of AgReO4 readout by Si thermistors. The spread in the thermistor characteristics and bolometer thermal coupling leads to different energy conversion gains and optimum operating points of the detectors. Detector biasing levels and voltage gains are completely remote-adjustable by the front end system developed, the subject of this paper, achieving the same signal range at the input of the DAQ system. The front end consists of a cold buffer stage, a second pseudo differential stage followed by a gain stage, an antialiasing filter, and a battery powered detector biasing set up. The DAQ system can be used to set all necessary parameters of the electronics remotely, by writing to a μ-controller located on each board. Fiber optics are used for the serial communication between the DAQ and the front end. To suppress interference noise during normal operation, the clocked devices of the front end are maintained in sleep-mode, except during the set-up phase of the experiment. An automatic DC detector characterization procedure is used to establish the optimum operating point of every detector of the array. A very low noise level has been achieved: about 3nV/□Hz at 1 Hz and 1 nV/□Hz for the white component, high frequencies.

  4. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  5. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...

  6. A socio-internactive framework for the fuzzy front end

    NARCIS (Netherlands)

    Smulders, Frido E.; van den Broek, Egon; van der Voort, Mascha C.; Fernandes, A.; Teixeira, A.; Natal Jorge, R.

    2007-01-01

    This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary socio-interactive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive

  7. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the

  8. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Giugliarelli, Gilberto; The ATLAS collaboration

    2018-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS experiment. They constitute the part of ATLAS closest to the interaction point and for this reason they will be exposed – over their lifetime – to a significant amount of radiation: prior to the HL-LHC, the innermost layers will receive a fluence of 10^15 neq/cm2 and their HL–LHC upgrades will have to cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  9. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  10. Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

    CERN Document Server

    Macchiolo, A; Beimforde, M; Moser, H G; Nisius, R; Richter, R H

    2009-01-01

    We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.

  11. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  12. Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Libov, Vladyslav

    2013-08-15

    measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

  13. Effets de rayonnement sur les detecteurs au silicium a pixels du detecteur ATLAS

    CERN Document Server

    Lebel, Celine

    2007-01-01

    Two detection systems are using pixel silicon detectors in the ATLAS detector: the Pixel, which is the subdetector closest to the interaction point, and the MPX network. The activation of the materials present in the Pixel produced by radiation has been measured in two experiments which we performed at CERF (CERN) and NPI-ASCR (Czech Republic). These experimental studies of activation are com- pared with GEANT4 simulations. The results of these comparisons show that the simulation can predict the activities with a precision of an order of magnitude. They also show that GEANT4 fails to produce certain radioisotopes seen in the experimental activation studies. The contribution to background and the resid- ual doses due to the desintegration of the radioisotopes produced by fast neutrons (category in which falls the expected average neutron energy of 1 MeV in ATLAS) are extrapolated to ATLAS conditions. It is found that this background in the AT- LAS Pixel subdetector will be negligible and that the doses are we...

  14. Evaluation of testing strategies for the radiation tolerant ATLAS n **+-in-n pixel sensor

    CERN Document Server

    Klaiber Lodewigs, Jonas M

    2003-01-01

    The development of particle tracker systems for high fluence environments in new high-energy physics experiments raises new challenges for the development, manufacturing and reliable testing of radiation tolerant components. The ATLAS pixel detector for use at the LHC, CERN, is designed to cover an active sensor area of 1.8 m**2 with 1.1 multiplied by 10 **8 read-out channels usable for a particle fluence up to 10 **1**5 cm**-**2 (1 MeV neutron equivalent) and an ionization dose up to 500 kGy of mainly charged hadron radiation. To cope with such a harsh environment the ATLAS Pixel Collaboration has developed a radiation hard n **+-in-n silicon pixel cell design with a standard cell size of 50 multiplied by 400 mum**2. Using this design on an oxygenated silicon substrate, sensor production has started in 2001. This contribution describes results gained during the development of testing procedures of the ATLAS pixel sensor and evaluates quality assurance procedures regarding their relevance for detector operati...

  15. Spatial and vertex resolution studies on the ATLAS Pixel Detector based on Combined Testbeam 2004 data

    CERN Document Server

    Reisinger, Ingo; Klingenberg, Reiner

    2006-01-01

    This diploma thesis deals with spatial and vertex resolution studies on the ATLAS Pixel detector based on real data taken during the Combined Testbeam period 2004 (17th May - 15th November). For the Combined Testbeam a barrel segment of the ATLAS Detector was build up and tested under real experimental conditions. Several data sets, being recorded during that time, are reconstructed by the ATLAS control framework called ATHENA. The input information for the reconstruction of the particle tracks through the Pixel Detector are the so-called spacepoints. Their uncertainty affects the resolution of the reconstructed particle tracks and thus, also the accuracy of the vertex reconstruction. Since traversing particles deposite their charge mostly (but not compellingly) within more than one pixel, all pixels corresponding to one hit have to be grouped together to a cluster. To compute the spacepoint from the cluster information two different strategies can be performed. The first one is a digital clustering, w...

  16. SEU tolerant memory design for the ATLAS pixel readout chip

    CERN Document Server

    Menouni, M; Backhaus, M; Barbero, M; Beccherle, R; Breugnon, P; Caminada, L; Dube, S; Darbo, G; Fleury, J; Fougeron, D; Garcia-Sciveres, M; Gensolen, F; Gnani, D; Gonella, L; Gromov, V; Hemperek, T; Jensen, F; karagounis, M; Kluit, R; Krüger, G; Kruth, A; Lu, Y; Mekkaoui, A; Rozanov, A; Schipper, J.D; Zivkovic, V

    2013-01-01

    The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

  17. The Pixels find their way to the heart of ATLAS

    CERN Multimedia

    Kevin Einsweiler

    Since the last e-news article on the Pixel Detector in December 2006, there has been much progress. At that time, we were just about to receive the Beryllium beampipe, and to integrate the innermost layer of the Pixel Detector around it. This innermost layer is referred to as the B-layer because of the powerful role it plays in finding the secondary vertices that are the key signature for the presence of b-quarks, and with somewhat greater difficulty, c-quarks and tau leptons. The integration of the central 7m long beampipe into the Pixel Detector was completed in December, and the B-layer was successfully integrated around it. In January this year, we had largely completed the central 1.5m long detector, including the three barrel layers and the three disk layers on each end of the barrel. Although this region contains all of the 80 million readout channels, it cannot be integrated into the Inner Detector without additional services and infrastructure. Therefore, the next step was to add the Service Panels...

  18. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  19. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  20. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    This paper addresses Front End Innovation as an object for the management and staging of innovation processes. We examine the role which devices play in the managing of Front End Innovation, with inspiration from Science and Technology Studies (STS). The paper contributes to a new understanding...... into realisations. Inputs from different knowledge domains must be grappled with, both in terms of needing to be elucidated as well as synthesized, in the engineering design process. The paper argues that the existing research may be seen as a response to perceived difficulties in dealing with uncertain conditions...... in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other devices such as representations of users...

  1. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  2. Managing Front-End Innovation through Idea Markets at Novozymes

    DEFF Research Database (Denmark)

    Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank

    2013-01-01

    Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in whic...... and screening and that active involvement of R&D management is a key success factor in any idea competition.......Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in which...... a relatively small number of highly motivated participants screened their colleagues' inventions through an "idea market." The idea competition fulfilled its goals of generating two ideas with high growth potential within a short time, uncovering and recombining old proposals that inventors had not previously...

  3. Radiation validation for the CMS HCAL front-end electronics

    CERN Document Server

    Whitmore, J; Elias, J E; Holm, S; Knickerbocker, K; Los, S; Rivetta, C; Ronzhin, A; Shenai, A; Yarema, R J; Zimmerman, T

    2002-01-01

    Over a 10 year operating period, the CMS Hadron Calorimeter (HCAL) detector will be exposed to radiation fields of approximately 1 kRad of total ionizing dose (TID) and a neutron fluence of 4E11 n/cm/sup 2 /. All front-end electronics must be qualified to survive this radiation environment with no degradation in performance. In addition, digital components in this environment can experience single-event upset (SEU) and single-event latch-up (SEL). A measurement of these single-event effects (SEE) for all components is necessary in order to understand the level that will be encountered. Radiation effects in all electronic components of the HCAL front-end system have been studied. Results from these studies will be presented. (17 refs).

  4. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  5. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  6. Operational Experience of the ATLAS SemiConductor Tracker and Pixel Detector

    CERN Document Server

    Robinson, Dave; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  7. The Pixel Detector of the ATLAS Experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO$_2$ based cooling system have been adopted. The IBL construction and installation in the ATLAS Experiment has been completed very successfu...

  8. Holographic Optical Receiver Front End for Wireless Infrared Indoor Communications

    Science.gov (United States)

    Jivkova, S.; Kavehrad, M.

    2001-06-01

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver s small size, light weight, and low cost make the receiver front end a promising candidate for a user s portable equipment in broadband indoor wireless multimedia access.

  9. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  10. A Leakage Current-based Measurement of the Radiation Damage in the ATLAS Pixel Detector

    CERN Document Server

    Gorelov, Igor; The ATLAS collaboration

    2015-01-01

    A measurement has been made of the radiation damage incurred by the ATLAS Pixel Detector barrel silicon modules from the beginning of operations through the end of 2012. This translates to hadronic fluence received over the full period of operation at energies up to and including 8 TeV. The measurement is based on a per-module measurement of the silicon sensor leakage current. The results are presented as a function of integrated luminosity and compared to predictions by the Hamburg Model. This information can be used to predict limits on the lifetime of the Pixel Detector due to current, for various operating scenarios.

  11. Passive front-ends for wideband millimeter wave electronic warfare

    Science.gov (United States)

    Jastram, Nathan Joseph

    This thesis presents the analysis, design and measurements of novel passive front ends of interest to millimeter wave electronic warfare systems. However, emerging threats in the millimeter waves (18 GHz and above) has led to a push for new systems capable of addressing these threats. At these frequencies, traditional techniques of design and fabrication are challenging due to small size, limited bandwidth and losses. The use of surface micromachining technology for wideband direction finding with multiple element antenna arrays for electronic support is demonstrated. A wideband tapered slot antenna is first designed and measured as an array element for the subsequent arrays. Both 18--36 GHz and 75--110 GHz amplitude only and amplitude/phase two element direction finding front ends are designed and measured. The design of arrays using Butler matrix and Rotman lens beamformers for greater than two element direction finding over W band and beyond using is also presented. The design of a dual polarized high power capable front end for electronic attack over an 18--45 GHz band is presented. To combine two polarizations into the same radiating aperture, an orthomode transducer (OMT) based upon a new double ridge waveguide cross section is developed. To provide greater flexibility in needed performance characteristics, several different turnstile junction matching sections are tested. A modular horn section is proposed to address flexible and ever changing operational requirements, and is designed for performance criteria such as constant gain, beamwidth, etc. A multi-section branch guide coupler and low loss Rotman lens based upon the proposed cross section are also developed. Prototyping methods for the herein designed millimeter wave electronic warfare front ends are investigated. Specifically, both printed circuit board (PCB) prototyping of micromachined systems and 3D printing of conventionally machined horns are presented. A 4--8 GHz two element array with

  12. New Technique for Luminosity Measurement Using 3D Pixel Modules in the ATLAS IBL Detector

    CERN Document Server

    Liu, Peilian; The ATLAS collaboration

    2017-01-01

    The Insertable b-Layer ( IBL ) is the innermost layer of the ATLAS tracking system. It consists of planar pixel modules in the central region and 3D modules at two extremities. We use the cluster length distributions in 3D sensor modules of the IBL to determine the number of primary charged particles per event and suppress backgrounds. This Pixel Cluster Counting ( PCC ) algorithm provides a bunch-by-bunch luminosity measurement. An accurate luminosity measurement is a key component for precision measurements at the Large Hadron Collider and one of the largest uncertainties on the luminosity determination in ATLAS arises from the long-term stability of the measurement technique. The comparison of the PCC algorithm with other existing algorithms provides key insights in assessing and reducing such uncertainty.

  13. Studies for the detector control system of the ATLAS pixel at the HL-LHC

    CERN Document Server

    Püllen, L; Boek, J; Kersten, S; Kind, P; Mättig, P; Zeitnitz, C

    2012-01-01

    experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

  14. Radiation-Hard Opto-Link for the Atlas Pixel Detector

    CERN Document Server

    INSPIRE-00083439; Arms, Kregg E.; Johnson, M.; Kagan, H.; Kass, R.; Rush, C.; Smith, S.; Ter-Antonian, R.; Zoeller, M.M.; Buchholz, P.; Holder, M.; Roggenbuck, A.; Schade, P.; Ziolkowski, M.

    2004-01-01

    The on-detector optical link of the ATLAS pixel detector contains radiation-hard receiver chips to decode bi-phase marked signals received on PIN arrays and data transmitter chips to drive VCSEL arrays. The components are mounted on hybrid boards (opto-boards). We present results from the opto-boards and from irradiation studies with 24 GeV protons up to 33 Mrad (1.2 x 10^15 p/cm^2).

  15. Energy resolution and power consumption of Timepix detector for different detector settings and saturation of front-end electronics

    Science.gov (United States)

    Kroupa, M.; Hoang, S.; Stoffle, N.; Soukup, P.; Jakubek, J.; Pinsky, L. S.

    2014-05-01

    An ongoing research project in the area of radiation monitoring employing the Timepix technology from the CERN-based Medipix2 Collaboration profits greatly from optimizing the precision of the position and energy information obtained for the detected quanta. Wider applications of the Timepix technology as a radiation monitor also puts new demands on the precision and speed of the energy calibration. We compare the analog signal in pixel front-end electronics for different sources used during detector evaluation and energy calibration. We use the direct measurement of the analog signal from the pixel preamplifier and comparator to characterize pulse shape differences for different sources, e.g. internal test pulses, external test pulses, ionizing radiation, etc. and study their interchangeability. Accurate per-pixel energy calibration of the Timepix detector enables the direct measurement of the energy deposited by different types of ionizing radiation. The energy calibration process requires the application of a known charge to front-end electronics of each pixel. The small pixel size limits use of the radioactive sources. The 59.54 keV line from 241Am is commonly used as the highest point in calibration curve. The heavy ion dosimetry as encountered in the space radiation environment requires a considerable extrapolation to the energies in the MeV range. We have observed that for energies around and beyond 1 MeV the response of the Timepix's front-end electronics no longer follows the extrapolated calibration function. We have investigated this non-linearity and identified its source. We also propose both hardware and software solutions to suppress this effect. In this paper we show the impact on pixel calibration and the subsequent energy resolution for different detector settings as well as the resulting power consumptions. We discuss the parameter optimization for several different real-world applications.

  16. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  17. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2 at the LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00084948; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130 nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented using collision data.

  18. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    Run-2 of the LHC will provide new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed as well as a new read-out chip within CMOS 130nm technology and with larger area, smaller pixel size and faster readout capability. The new detector is the first large scale application of of 3D detectors and CMOS 130nm technology. An overview of the lessons learned during the IBL project will be presented, focusing on the challenges and highlighting the issues met during the productio...

  19. The ATLAS Pixel Detector for Run II at the Large Hadron Collider

    CERN Document Server

    Marx, Marilyn; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  20. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  1. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    INSPIRE-00237659

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detect or and of the IBL project as...

  2. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  3. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Takubo, Y; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair the modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using light weight staves and CO$_{2}$ based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and the IBL pr...

  4. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  5. Novel Silicon n-on-p Edgeless Planar Pixel Sensors for the ATLAS upgrade

    CERN Document Server

    Bomben, M.; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-in-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the 'active edge' concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

  6. Novel Silicon n-on-p Edgeless Planar Pixel Sensors for the ATLAS upgrade

    CERN Document Server

    Bomben, M

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

  7. Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Bomben, M., E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Bagolini, A.; Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, L. [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, Pisa (Italy); INFN Sez. di Pisa, Pisa (Italy); Chauveau, J. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

    2013-12-01

    In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

  8. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  9. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  10. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  11. Thermal diagnostics front-end electronics for LISA Pathfinder.

    Science.gov (United States)

    Sanjuán, J; Lobo, A; Nofrarias, M; Ramos-Castro, J; Riu, P J

    2007-10-01

    Precision temperature measurements are required in the LTP, the LISA technology package, for various diagnostics objectives. In this article, we describe in detail the front-end electronics design and the associated temperature sensors to achieve the LTP requirements: noise equivalent temperature of 10 microK Hz(-12) in the frequency range from 1 to 30 mHz at room temperature. We designed an ac Wheatstone bridge and a subsequent digital demodulation to minimize 1/f noise. We show experimental results where the required sensitivity in the measurement bandwidth is fulfilled.

  12. The ATLAS Diamond Beam Monitor

    CERN Document Server

    Cerv, M

    2014-01-01

    The ATLAS Diamond Beam Monitor is a novel charged-particle detector. It will be used in the ATLAS experiment to measure luminosity and beam backgrounds. The monitor’s pCVD diamond sensors are instrumented with pixellated FE-I4 front-end chips. The CVD diamond sensor material was chosen to ensure long-term durability of the sensors in a radiation-hard environment. This document describes the principles of luminosity measurements. It is then explained how the Diamond Beam Monitor will carry out this task.

  13. Underwater fiber-wireless communication with a passive front end

    Science.gov (United States)

    Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

    2017-11-01

    We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

  14. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  15. Front-end electronics for the readout of CdZnTe sensors

    CERN Document Server

    Moraes, D; Rudge, A

    2006-01-01

    The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.

  16. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end... Compliance Status specified in § 63.506(e)(5). (1) For each batch front-end process vent complying with § 63...

  17. FE-I4, the New ATLAS Pixel Chip for Upgraded LHC Luminosities

    CERN Document Server

    "Barbero, M; The ATLAS collaboration

    2009-01-01

    The new ATLAS pixel chip FE-I4 is being developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. FE-I4 is designed in a 130 nm technology and is based on an array of 80 by 336 pixels, each 50×250 μm2 and consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides an elegant solution to the problem of timewalk. The chip periphery contains a control block, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which handles data transmission up to 160 Mb/s for the IBL.

  18. Recent Results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    Weigell, Philipp

    2013-01-01

    To cope with the higher occupancy and radiation damage at the HL-LHC also the LHC experiments will be upgraded. The ATLAS Planar Pixel Sensor R&D Project (PPS) is an international collaboration of 17 institutions and more than 80 scientists, exploring the feasibility of employing planar pixel sensors for this scenario. Depending on the radius, different pixel concepts are investigated using laboratory and beam test measurements. At small radii the extreme radiation environment and strong space constraints are addressed with very thin pixel sensors active thickness in the range of (75-150) mum, and the development of slim as well as active edges. At larger radii the main challenge is the cost reduction to allow for instrumenting the large area of (7-10) m^2. To reach this goal the pixel productions are being transferred to 6 inch production lines. Additionally, investigated are more cost-efficient and industrialised interconnection techniques as well as the n-in-p technology, which, being a single-sided pr...

  19. Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

    CERN Document Server

    Macchiolo, Anna; Savic, Natascha; Terzo, Stefano

    2016-01-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region...

  20. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  1. The Pixel Detector of the ATLAS experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is the fourth layer of the Run 2 Pixel Detector, and it was installed in May 2014 between the existing Pixel Detector and the new smaller-radius beam pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project...

  2. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  3. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, Heinz; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as we...

  4. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Mullier, Geoffrey Andre; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed. A new readout chip has been developed within CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical performan...

  5. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  6. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  7. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gallrapp, Christian

    2015-07-01

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

  8. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... process vent, reduce organic HAP emissions for the batch cycle by 90 weight percent using a control device... control device as it relates to continuous front-end process vents shall be used. Furthermore, the...

  9. 40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... § 63.491 Batch front-end process vents—recordkeeping requirements. (a) Group determination records for batch front-end process vents. Except as provided in paragraphs (a)(7) and (a)(8) of this section, each...

  10. 40 CFR 63.486 - Batch front-end process vent provisions.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vent provisions... Batch front-end process vent provisions. (a) Batch front-end process vents. Except as specified in paragraph (b) of this section, owners and operators of new and existing affected sources with batch front...

  11. TCAD Simulations of ATLAS Pixel Guard Ring and Edge Structure for SLHC Upgrade

    CERN Document Server

    Lounis, A; The ATLAS collaboration; Calderini, G; Marchiori, G; Benoit, M; Dinu, N

    2010-01-01

    In this work, the magnitude of the electric field and the depletion inside a simplified two dimensional model of the ATLAS planar pixel sensor for the insertable b-layer and the super-LHC upgrade have been studied. The parameters influencing the breakdown behavior were studied using a finite-element method to solve the drift-diffusion equations coupled to Poisson's equation. Using these models, the number of guard rings, dead edge width and sensor's thickness were modified with respect to the ATLAS actual pixel sensor to investigate their influence on the sensor's depletion at the edge and on its internal electrical field distribution. The goal of the simulation is to establish a model to discriminate between different designs and to select the most optimized to fit the needs in radiation hardness and low material budget of ATLAS inner detector during super-LHC operation. A three defects level model has been implemented in the simulations to study the behavior of such sensors under different level of irradiat...

  12. Recent progress of the ATLAS Planar Pixel Sensor R&D Project

    CERN Document Server

    Bomben, M

    2012-01-01

    The foreseen luminosity upgrade for the LHC (a factor of 5-10 more in peak luminosity by 2021) poses serious constraints on the technology for the ATLAS tracker in this High Luminosity era (HL-LHC). In fact, such luminosity increase leads to increased occupancy and radiation damage of the tracking detectors. To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Planar Pixel Sensor R&D Project was established comprising 17 institutes and more than 80 scientists. Main areas of research are the performance of planar pixel sensors at highest fluences, the exploration of possibilities for cost reduction to enable the instrumentation of large areas, the achievement of slim or active edge designs to provide low geometric inefficiencies without the need for shingling of modules and the investigation of the operation of highly irradiated sensors at low thresholds to increase the efficiency. In the following I will present results from the group, conc...

  13. 3D silicon pixel detectors for the ATLAS Forward Physics experiment

    CERN Document Server

    INSPIRE-00397348; Cavallaro, E.; Grinstein, S.; López Paz, I.

    2015-01-01

    The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2-3 mm). This implies the need of slim edges of about 100-200 $\\mu$m width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 $\\mu$m width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 10$^{15}$ n$_{eq}$/cm$^2$ with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al ma...

  14. SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades

    CERN Document Server

    Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P

    2012-01-01

    We present the results of the characterization of pixel modules composed of 75 μm thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is explored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module, ICVs are etched over the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation is presented.

  15. Simulations of planar pixel sensors for the ATLAS high luminosity upgrade

    CERN Document Server

    Calderini, G; Dinu, N; Lounis, A; Marchiori, G

    2011-01-01

    A physics-based device simulation was used to study the charge carrier distribution and the electric field configuration inside simplified two-dimensional models for pixel layouts based on the ATLAS pixel sensor. In order to study the behavior of such detectors under different levels of irradiation, a three-level defect model was implemented into the simulation. Using these models, the number of guard rings, the dead edge width and the detector thickness were modified to investigate their influence on the detector depletion at the edge and on its internal electric field distribution in order to optimize the layout parameters. Simulations indicate that the number of guard rings can be reduced by a few hundred microns with respect to the layout used for the present ATLAS sensors, with a corresponding extension of the active area of the sensors. A study of the inter-pixel capacitance and of the capacitance between the implants and the high-voltage contact as a function of several parameters affecting the geometr...

  16. DESIGN OF MEDICAL RADIOMETER FRONT-END FOR IMPROVED PERFORMANCE

    Science.gov (United States)

    Klemetsen, Ø.; Birkelund, Y.; Jacobsen, S. K.; Maccarini, P. F.; Stauffer, P. R.

    2011-01-01

    We have investigated the possibility of building a singleband Dicke radiometer that is inexpensive, small-sized, stable, highly sensitive, and which consists of readily available microwave components. The selected frequency band is at 3.25–3.75 GHz which provides a reasonable compromise between spatial resolution (antenna size) and sensing depth for radiometry applications in lossy tissue. Foreseen applications of the instrument are non-invasive temperature monitoring for breast cancer detection and temperature monitoring during heating. We have found off-the-shelf microwave components that are sufficiently small (radiometers have been realized: one is a conventional design with the Dicke switch at the front-end to select either the antenna or noise reference channels for amplification. The second design places a matched pair of low noise amplifiers in front of the Dicke switch to reduce system noise figure. Numerical simulations were performed to test the design concepts before building prototype PCB front-end layouts of the radiometer. Both designs provide an overall power gain of approximately 50 dB over a 500 MHz bandwidth centered at 3.5 GHz. No stability problems were observed despite using triple-cascaded amplifier configurations to boost the thermal signals. The prototypes were tested for sensitivity after calibration in two different water baths. Experiments showed superior sensitivity (36% higher) when implementing the low noise amplifier before the Dicke switch (close to the antenna) compared to the other design with the Dicke switch in front. Radiometer performance was also tested in a multilayered phantom during alternating heating and radiometric reading. Empirical tests showed that for the configuration with Dicke switch first, the switch had to be locked in the reference position during application of microwave heating to avoid damage to the active components (amplifiers and power meter). For the configuration with a low noise amplifier up front

  17. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  18. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  19. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  20. Gravitational Reference Sensor Front-End Electronics Simulator for LISA

    Science.gov (United States)

    Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; ten Pierick, Jan; Zweifel, Peter; Giardini, Domenico; ">LISA Pathfinder colaboration, Front End Electronics (FEE) for LISA Gravitational Reference Sensor (GRS). It is based on the GRS FEE-simulator already implemented for LISA Pathfinder. It considers, in particular, the non-linearity and the critical details of hardware, such as the non-linear multiplicative noise caused by voltage reference instability, test mass charging and detailed actuation and sensing algorithms. We present the simulation modules, considering the above-mentioned features. Based on the ETH GRS FEE-simulator for LISA Pathfinder we aim to develop a modular simulator that provides a realistic simulation of GRS FEE for LISA.

  1. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...... to the importance of being aligned with the strategy and mindset of the rest of the organization. This approximate alignment will induce alternative ways to set the stage for a development spaces that is configured to perform in new ways allowing for different types of development....

  2. A neural network clustering algorithm for the ATLAS silicon pixel detector

    CERN Document Server

    Aad, Georges; Abdallah, Jalal; Abdel Khalek, Samah; Abdinov, Ovsat; Aben, Rosemarie; Abi, Babak; Abolins, Maris; AbouZeid, Ossama; Abramowicz, Halina; Abreu, Henso; Abreu, Ricardo; Abulaiti, Yiming; Acharya, Bobby Samir; Adamczyk, Leszek; Adams, David; Adelman, Jahred; Adomeit, Stefanie; Adye, Tim; Agatonovic-Jovin, Tatjana; Aguilar-Saavedra, Juan Antonio; Agustoni, Marco; Ahlen, Steven; Ahmadov, Faig; Aielli, Giulio; Akerstedt, Henrik; Åkesson, Torsten Paul Ake; Akimoto, Ginga; Akimov, Andrei; Alberghi, Gian Luigi; Albert, Justin; Albrand, Solveig; Alconada Verzini, Maria Josefina; Aleksa, Martin; Aleksandrov, Igor; Alexa, Calin; Alexander, Gideon; Alexandre, Gauthier; Alexopoulos, Theodoros; Alhroob, Muhammad; Alimonti, Gianluca; Alio, Lion; Alison, John; Allbrooke, Benedict; Allison, Lee John; Allport, Phillip; Almond, John; Aloisio, Alberto; Alonso, Alejandro; Alonso, Francisco; Alpigiani, Cristiano; Altheimer, Andrew David; Alvarez Gonzalez, Barbara; Alviggi, Mariagrazia; Amako, Katsuya; Amaral Coutinho, Yara; Amelung, Christoph; Amidei, Dante; Amor Dos Santos, Susana Patricia; Amorim, Antonio; Amoroso, Simone; Amram, Nir; Amundsen, Glenn; Anastopoulos, Christos; Ancu, Lucian Stefan; Andari, Nansi; Andeen, Timothy; Anders, Christoph Falk; Anders, Gabriel; Anderson, Kelby; Andreazza, Attilio; Andrei, George Victor; Anduaga, Xabier; Angelidakis, Stylianos; Angelozzi, Ivan; Anger, Philipp; Angerami, Aaron; Anghinolfi, Francis; Anisenkov, Alexey; Anjos, Nuno; Annovi, Alberto; Antonaki, Ariadni; Antonelli, Mario; Antonov, Alexey; Antos, Jaroslav; Anulli, Fabio; Aoki, Masato; Aperio Bella, Ludovica; Apolle, Rudi; Arabidze, Giorgi; Aracena, Ignacio; Arai, Yasuo; Araque, Juan Pedro; Arce, Ayana; Arguin, Jean-Francois; Argyropoulos, Spyridon; Arik, Metin; Armbruster, Aaron James; Arnaez, Olivier; Arnal, Vanessa; Arnold, Hannah; Arratia, Miguel; Arslan, Ozan; Artamonov, Andrei; Artoni, Giacomo; Asai, Shoji; Asbah, Nedaa; Ashkenazi, Adi; Åsman, Barbro; Asquith, Lily; Assamagan, Ketevi; Astalos, Robert; Atkinson, Markus; Atlay, Naim Bora; Auerbach, Benjamin; Augsten, Kamil; Aurousseau, Mathieu; Avolio, Giuseppe; Azuelos, Georges; Azuma, Yuya; Baak, Max; Baas, Alessandra; Bacci, Cesare; Bachacou, Henri; Bachas, Konstantinos; Backes, Moritz; Backhaus, Malte; Backus Mayes, John; Badescu, Elisabeta; Bagiacchi, Paolo; Bagnaia, Paolo; Bai, Yu; Bain, Travis; Baines, John; Baker, Oliver Keith; Balek, Petr; Balli, Fabrice; Banas, Elzbieta; Banerjee, Swagato; Bannoura, Arwa A E; Bansal, Vikas; Bansil, Hardeep Singh; Barak, Liron; Baranov, Sergei; Barberio, Elisabetta Luigia; Barberis, Dario; Barbero, Marlon; Barillari, Teresa; Barisonzi, Marcello; Barklow, Timothy; Barlow, Nick; Barnett, Bruce; Barnett, Michael; Barnovska, Zuzana; Baroncelli, Antonio; Barone, Gaetano; Barr, Alan; Barreiro, Fernando; Barreiro Guimarães da Costa, João; Bartoldus, Rainer; Barton, Adam Edward; Bartos, Pavol; Bartsch, Valeria; Bassalat, Ahmed; Basye, Austin; Bates, Richard; Batkova, Lucia; Batley, Richard; Battaglia, Marco; Battistin, Michele; Bauer, Florian; Bawa, Harinder Singh; Beau, Tristan; Beauchemin, Pierre-Hugues; Beccherle, Roberto; Bechtle, Philip; Beck, Hans Peter; Becker, Anne Kathrin; Becker, Sebastian; Beckingham, Matthew; Becot, Cyril; Beddall, Andrew; Beddall, Ayda; Bedikian, Sourpouhi; Bednyakov, Vadim; Bee, Christopher; Beemster, Lars; Beermann, Thomas; Begel, Michael; Behr, Katharina; Belanger-Champagne, Camille; Bell, Paul; Bell, William; Bella, Gideon; Bellagamba, Lorenzo; Bellerive, Alain; Bellomo, Massimiliano; Belotskiy, Konstantin; Beltramello, Olga; Benary, Odette; Benchekroun, Driss; Bendtz, Katarina; Benekos, Nektarios; Benhammou, Yan; Benhar Noccioli, Eleonora; Benitez Garcia, Jorge-Armando; Benjamin, Douglas; Bensinger, James; Benslama, Kamal; Bentvelsen, Stan; Berge, David; Bergeaas Kuutmann, Elin; Berger, Nicolas; Berghaus, Frank; Beringer, Jürg; Bernard, Clare; Bernat, Pauline; Bernius, Catrin; Bernlochner, Florian Urs; Berry, Tracey; Berta, Peter; Bertella, Claudia; Bertoli, Gabriele; Bertolucci, Federico; Bertsche, David; Besana, Maria Ilaria; Besjes, Geert-Jan; Bessidskaia, Olga; Bessner, Martin Florian; Besson, Nathalie; Betancourt, Christopher; Bethke, Siegfried; Bhimji, Wahid; Bianchi, Riccardo-Maria; Bianchini, Louis; Bianco, Michele; Biebel, Otmar; Bieniek, Stephen Paul; Bierwagen, Katharina; Biesiada, Jed; Biglietti, Michela; Bilbao De Mendizabal, Javier; Bilokon, Halina; Bindi, Marcello; Binet, Sebastien; Bingul, Ahmet; Bini, Cesare; Black, Curtis; Black, James; Black, Kevin; Blackburn, Daniel; Blair, Robert; Blanchard, Jean-Baptiste; Blazek, Tomas; Bloch, Ingo; Blocker, Craig; Blum, Walter; Blumenschein, Ulrike; Bobbink, Gerjan; Bobrovnikov, Victor; Bocchetta, Simona Serena; Bocci, Andrea; Bock, Christopher; Boddy, Christopher Richard; Boehler, Michael; Boek, Thorsten Tobias; Bogaerts, Joannes Andreas; Bogdanchikov, Alexander; Bogouch, Andrei; Bohm, Christian; Bohm, Jan; Boisvert, Veronique; Bold, Tomasz; Boldea, Venera; Boldyrev, Alexey; Bomben, Marco; Bona, Marcella; Boonekamp, Maarten; Borisov, Anatoly; Borissov, Guennadi; Borri, Marcello; Borroni, Sara; Bortfeldt, Jonathan; Bortolotto, Valerio; Bos, Kors; Boscherini, Davide; Bosman, Martine; Boterenbrood, Hendrik; Boudreau, Joseph; Bouffard, Julian; Bouhova-Thacker, Evelina Vassileva; Boumediene, Djamel Eddine; Bourdarios, Claire; Bousson, Nicolas; Boutouil, Sara; Boveia, Antonio; Boyd, James; Boyko, Igor; Bracinik, Juraj; Brandt, Andrew; Brandt, Gerhard; Brandt, Oleg; Bratzler, Uwe; Brau, Benjamin; Brau, James; Braun, Helmut; Brazzale, Simone Federico; Brelier, Bertrand; Brendlinger, Kurt; Brennan, Amelia Jean; Brenner, Richard; Bressler, Shikma; Bristow, Kieran; Bristow, Timothy Michael; Britton, Dave; Brochu, Frederic; Brock, Ian; Brock, Raymond; Bromberg, Carl; Bronner, Johanna; Brooijmans, Gustaaf; Brooks, Timothy; Brooks, William; Brosamer, Jacquelyn; Brost, Elizabeth; Brown, Jonathan; Bruckman de Renstrom, Pawel; Bruncko, Dusan; Bruneliere, Renaud; Brunet, Sylvie; Bruni, Alessia; Bruni, Graziano; Bruschi, Marco; Bryngemark, Lene; Buanes, Trygve; Buat, Quentin; Bucci, Francesca; Buchholz, Peter; Buckingham, Ryan; Buckley, Andrew; Buda, Stelian Ioan; Budagov, Ioulian; Buehrer, Felix; Bugge, Lars; Bugge, Magnar Kopangen; Bulekov, Oleg; Bundock, Aaron Colin; Burckhart, Helfried; Burdin, Sergey; Burghgrave, Blake; Burke, Stephen; Burmeister, Ingo; Busato, Emmanuel; Büscher, Daniel; Büscher, Volker; Bussey, Peter; Buszello, Claus-Peter; Butler, Bart; Butler, John; Butt, Aatif Imtiaz; Buttar, Craig; Butterworth, Jonathan; Butti, Pierfrancesco; Buttinger, William; Buzatu, Adrian; Byszewski, Marcin; Cabrera Urbán, Susana; Caforio, Davide; Cakir, Orhan; Calafiura, Paolo; Calandri, Alessandro; Calderini, Giovanni; Calfayan, Philippe; Calkins, Robert; Caloba, Luiz; Calvet, David; Calvet, Samuel; Camacho Toro, Reina; Camarda, Stefano; Cameron, David; Caminada, Lea Michaela; Caminal Armadans, Roger; Campana, Simone; Campanelli, Mario; Campoverde, Angel; Canale, Vincenzo; Canepa, Anadi; Cano Bret, Marc; Cantero, Josu; Cantrill, Robert; Cao, Tingting; Capeans Garrido, Maria Del Mar; Caprini, Irinel; Caprini, Mihai; Capua, Marcella; Caputo, Regina; Cardarelli, Roberto; Carli, Tancredi; Carlino, Gianpaolo; Carminati, Leonardo; Caron, Sascha; Carquin, Edson; Carrillo-Montoya, German D; Carter, Janet; Carvalho, João; Casadei, Diego; Casado, Maria Pilar; Casolino, Mirkoantonio; Castaneda-Miranda, Elizabeth; Castelli, Angelantonio; Castillo Gimenez, Victoria; Castro, Nuno Filipe; Catastini, Pierluigi; Catinaccio, Andrea; Catmore, James; Cattai, Ariella; Cattani, Giordano; Caughron, Seth; Cavaliere, Viviana; Cavalli, Donatella; Cavalli-Sforza, Matteo; Cavasinni, Vincenzo; Ceradini, Filippo; Cerio, Benjamin; Cerny, Karel; Santiago Cerqueira, Augusto; Cerri, Alessandro; Cerrito, Lucio; Cerutti, Fabio; Cerv, Matevz; Cervelli, Alberto; Cetin, Serkant Ali; Chafaq, Aziz; Chakraborty, Dhiman; Chalupkova, Ina; Chang, Philip; Chapleau, Bertrand; Chapman, John Derek; Charfeddine, Driss; Charlton, Dave; Chau, Chav Chhiv; Chavez Barajas, Carlos Alberto; Cheatham, Susan; Chegwidden, Andrew; Chekanov, Sergei; Chekulaev, Sergey; Chelkov, Gueorgui; Chelstowska, Magda Anna; Chen, Chunhui; Chen, Hucheng; Chen, Karen; Chen, Liming; Chen, Shenjian; Chen, Xin; Chen, Yujiao; Cheng, Hok Chuen; Cheng, Yangyang; Cheplakov, Alexander; Cherkaoui El Moursli, Rajaa; Chernyatin, Valeriy; Cheu, Elliott; Chevalier, Laurent; Chiarella, Vitaliano; Chiefari, Giovanni; Childers, John Taylor; Chilingarov, Alexandre; Chiodini, Gabriele; Chisholm, Andrew; Chislett, Rebecca Thalatta; Chitan, Adrian; Chizhov, Mihail; Chouridou, Sofia; Chow, Bonnie Kar Bo; Chromek-Burckhart, Doris; Chu, Ming-Lee; Chudoba, Jiri; Chwastowski, Janusz; Chytka, Ladislav; Ciapetti, Guido; Ciftci, Abbas Kenan; Ciftci, Rena; Cinca, Diane; Cindro, Vladimir; Ciocio, Alessandra; Cirkovic, Predrag; Citron, Zvi Hirsh; Citterio, Mauro; Ciubancan, Mihai; Clark, Allan G; Clark, Philip James; Clarke, Robert; Cleland, Bill; Clemens, Jean-Claude; Clement, Christophe; Coadou, Yann; Cobal, Marina; Coccaro, Andrea; Cochran, James H; Coffey, Laurel; Cogan, Joshua Godfrey; Coggeshall, James; Cole, Brian; Cole, Stephen; Colijn, Auke-Pieter; Collot, Johann; Colombo, Tommaso; Colon, German; Compostella, Gabriele; Conde Muiño, Patricia; Coniavitis, Elias; Conidi, Maria Chiara; Connell, Simon Henry; Connelly, Ian; Consonni, Sofia Maria; Consorti, Valerio; Constantinescu, Serban; Conta, Claudio; Conti, Geraldine; Conventi, Francesco; Cooke, Mark; Cooper, Ben; Cooper-Sarkar, Amanda; Cooper-Smith, Neil; Copic, Katherine; Cornelissen, Thijs; Corradi, Massimo; Corriveau, Francois; Corso-Radu, Alina; Cortes-Gonzalez, Arely; Cortiana, Giorgio; Costa, Giuseppe; Costa, María José; Costanzo, Davide; Côté, David; Cottin, Giovanna; Cowan, Glen; Cox, Brian; Cranmer, Kyle; Cree, Graham; Crépé-Renaudin, Sabine; Crescioli, Francesco; Cribbs, Wayne Allen; Crispin Ortuzar, Mireia; Cristinziani, Markus; Croft, Vince; Crosetti, Giovanni; Cuciuc, Constantin-Mihai; Cuhadar Donszelmann, Tulay; Cummings, Jane; Curatolo, Maria; Cuthbert, Cameron; Czirr, Hendrik; Czodrowski, Patrick; Czyczula, Zofia; D'Auria, Saverio; D'Onofrio, Monica; Da Cunha Sargedas De Sousa, Mario Jose; Da Via, Cinzia; Dabrowski, Wladyslaw; Dafinca, Alexandru; Dai, Tiesheng; Dale, Orjan; Dallaire, Frederick; Dallapiccola, Carlo; Dam, Mogens; Daniells, Andrew Christopher; Dano Hoffmann, Maria; Dao, Valerio; Darbo, Giovanni; Darmora, Smita; Dassoulas, James; Dattagupta, Aparajita; Davey, Will; David, Claire; Davidek, Tomas; Davies, Eleanor; Davies, Merlin; Davignon, Olivier; Davison, Adam; Davison, Peter; Davygora, Yuriy; Dawe, Edmund; Dawson, Ian; Daya-Ishmukhametova, Rozmin; De, Kaushik; de Asmundis, Riccardo; De Castro, Stefano; De Cecco, Sandro; De Groot, Nicolo; de Jong, Paul; De la Torre, Hector; De Lorenzi, Francesco; De Nooij, Lucie; De Pedis, Daniele; De Salvo, Alessandro; De Sanctis, Umberto; De Santo, Antonella; De Vivie De Regie, Jean-Baptiste; Dearnaley, William James; Debbe, Ramiro; Debenedetti, Chiara; Dechenaux, Benjamin; Dedovich, Dmitri; Deigaard, Ingrid; Del Peso, Jose; Del Prete, Tarcisio; Deliot, Frederic; Delitzsch, Chris Malena; Deliyergiyev, Maksym; Dell'Acqua, Andrea; Dell'Asta, Lidia; Dell'Orso, Mauro; Della Pietra, Massimo; della Volpe, Domenico; Delmastro, Marco; Delsart, Pierre-Antoine; Deluca, Carolina; Demers, Sarah; Demichev, Mikhail; Demilly, Aurelien; Denisov, Sergey; Derendarz, Dominik; Derkaoui, Jamal Eddine; Derue, Frederic; Dervan, Paul; Desch, Klaus Kurt; Deterre, Cecile; Deviveiros, Pier-Olivier; Dewhurst, Alastair; Dhaliwal, Saminder; Di Ciaccio, Anna; Di Ciaccio, Lucia; Di Domenico, Antonio; Di Donato, Camilla; Di Girolamo, Alessandro; Di Girolamo, Beniamino; Di Mattia, Alessandro; Di Micco, Biagio; Di Nardo, Roberto; Di Simone, Andrea; Di Sipio, Riccardo; Di Valentino, David; Dias, Flavia; Diaz, Marco Aurelio; Diehl, Edward; Dietrich, Janet; Dietzsch, Thorsten; Diglio, Sara; Dimitrievska, Aleksandra; Dingfelder, Jochen; Dionisi, Carlo; Dita, Petre; Dita, Sanda; Dittus, Fridolin; Djama, Fares; Djobava, Tamar; Barros do Vale, Maria Aline; Do Valle Wemans, André; Doan, Thi Kieu Oanh; Dobos, Daniel; Doglioni, Caterina; Doherty, Tom; Dohmae, Takeshi; Dolejsi, Jiri; Dolezal, Zdenek; Dolgoshein, Boris; Donadelli, Marisilvia; Donati, Simone; Dondero, Paolo; Donini, Julien; Dopke, Jens; Doria, Alessandra; Dova, Maria-Teresa; Doyle, Tony; Dris, Manolis; Dubbert, Jörg; Dube, Sourabh; Dubreuil, Emmanuelle; Duchovni, Ehud; Duckeck, Guenter; Ducu, Otilia Anamaria; Duda, Dominik; Dudarev, Alexey; Dudziak, Fanny; Duflot, Laurent; Duguid, Liam; Dührssen, Michael; Dunford, Monica; Duran Yildiz, Hatice; Düren, Michael; Durglishvili, Archil; Dwuznik, Michal; Dyndal, Mateusz; Ebke, Johannes; Edson, William; Edwards, Nicholas Charles; Ehrenfeld, Wolfgang; Eifert, Till; Eigen, Gerald; Einsweiler, Kevin; Ekelof, Tord; El Kacimi, Mohamed; Ellert, Mattias; Elles, Sabine; Ellinghaus, Frank; Ellis, Nicolas; Elmsheuser, Johannes; Elsing, Markus; Emeliyanov, Dmitry; Enari, Yuji; Endner, Oliver Chris; Endo, Masaki; Engelmann, Roderich; Erdmann, Johannes; Ereditato, Antonio; Eriksson, Daniel; Ernis, Gunar; Ernst, Jesse; Ernst, Michael; Ernwein, Jean; Errede, Deborah; Errede, Steven; Ertel, Eugen; Escalier, Marc; Esch, Hendrik; Escobar, Carlos; Esposito, Bellisario; Etienvre, Anne-Isabelle; Etzion, Erez; Evans, Hal; Ezhilov, Alexey; Fabbri, Laura; Facini, Gabriel; Fakhrutdinov, Rinat; Falciano, Speranza; Falla, Rebecca Jane; Faltova, Jana; Fang, Yaquan; Fanti, Marcello; Farbin, Amir; Farilla, Addolorata; Farooque, Trisha; Farrell, Steven; Farrington, Sinead; Farthouat, Philippe; Fassi, Farida; Fassnacht, Patrick; Fassouliotis, Dimitrios; Favareto, Andrea; Fayard, Louis; Federic, Pavol; Fedin, Oleg; Fedorko, Wojciech; Fehling-Kaschek, Mirjam; Feigl, Simon; Feligioni, Lorenzo; Feng, Cunfeng; Feng, Eric; Feng, Haolu; Fenyuk, Alexander; Fernandez Perez, Sonia; Ferrag, Samir; Ferrando, James; Ferrari, Arnaud; Ferrari, Pamela; Ferrari, Roberto; Ferreira de Lima, Danilo Enoque; Ferrer, Antonio; Ferrere, Didier; Ferretti, Claudio; Ferretto Parodi, Andrea; Fiascaris, Maria; Fiedler, Frank; Filipčič, Andrej; Filipuzzi, Marco; Filthaut, Frank; Fincke-Keeler, Margret; Finelli, Kevin Daniel; Fiolhais, Miguel; Fiorini, Luca; Firan, Ana; Fischer, Adam; Fischer, Julia; Fisher, Wade Cameron; Fitzgerald, Eric Andrew; Flechl, Martin; Fleck, Ivor; Fleischmann, Philipp; Fleischmann, Sebastian; Fletcher, Gareth Thomas; Fletcher, Gregory; Flick, Tobias; Floderus, Anders; Flores Castillo, Luis; Florez Bustos, Andres Carlos; Flowerdew, Michael; Formica, Andrea; Forti, Alessandra; Fortin, Dominique; Fournier, Daniel; Fox, Harald; Fracchia, Silvia; Francavilla, Paolo; Franchini, Matteo; Franchino, Silvia; Francis, David; Franklin, Melissa; Franz, Sebastien; Fraternali, Marco; French, Sky; Friedrich, Conrad; Friedrich, Felix; Froidevaux, Daniel; Frost, James; Fukunaga, Chikara; Fullana Torregrosa, Esteban; Fulsom, Bryan Gregory; Fuster, Juan; Gabaldon, Carolina; Gabizon, Ofir; Gabrielli, Alessandro; Gabrielli, Andrea; Gadatsch, Stefan; Gadomski, Szymon; Gagliardi, Guido; Gagnon, Pauline; Galea, Cristina; Galhardo, Bruno; Gallas, Elizabeth; Gallo, Valentina Santina; Gallop, Bruce; Gallus, Petr; Galster, Gorm Aske Gram Krohn; Gan, KK; Gandrajula, Reddy Pratap; Gao, Jun; Gao, Yongsheng; Garay Walls, Francisca; Garberson, Ford; García, Carmen; García Navarro, José Enrique; Garcia-Sciveres, Maurice; Gardner, Robert; Garelli, Nicoletta; Garonne, Vincent; Gatti, Claudio; Gaudio, Gabriella; Gaur, Bakul; Gauthier, Lea; Gauzzi, Paolo; Gavrilenko, Igor; Gay, Colin; Gaycken, Goetz; Gazis, Evangelos; Ge, Peng; Gecse, Zoltan; Gee, Norman; Geerts, Daniël Alphonsus Adrianus; Geich-Gimbel, Christoph; Gellerstedt, Karl; Gemme, Claudia; Gemmell, Alistair; Genest, Marie-Hélène; Gentile, Simonetta; George, Matthias; George, Simon; Gerbaudo, Davide; Gershon, Avi; Ghazlane, Hamid; Ghodbane, Nabil; Giacobbe, Benedetto; Giagu, Stefano; Giangiobbe, Vincent; Giannetti, Paola; Gianotti, Fabiola; Gibbard, Bruce; Gibson, Stephen; Gilchriese, Murdock; Gillam, Thomas; Gillberg, Dag; Gilles, Geoffrey; Gingrich, Douglas; Giokaris, Nikos; Giordani, MarioPaolo; Giordano, Raffaele; Giorgi, Filippo Maria; Giorgi, Francesco Michelangelo; Giraud, Pierre-Francois; Giugni, Danilo; Giuliani, Claudia; Giulini, Maddalena; Gjelsten, Børge Kile; Gkaitatzis, Stamatios; Gkialas, Ioannis; Gladilin, Leonid; Glasman, Claudia; Glatzer, Julian; Glaysher, Paul; Glazov, Alexandre; Glonti, George; Goblirsch-Kolb, Maximilian; Goddard, Jack Robert; Godfrey, Jennifer; Godlewski, Jan; Goeringer, Christian; Goldfarb, Steven; Golling, Tobias; Golubkov, Dmitry; Gomes, Agostinho; Gomez Fajardo, Luz Stella; Gonçalo, Ricardo; Goncalves Pinto Firmino Da Costa, Joao; Gonella, Laura; González de la Hoz, Santiago; Gonzalez Parra, Garoe; Gonzalez-Sevilla, Sergio; Goossens, Luc; Gorbounov, Petr Andreevich; Gordon, Howard; Gorelov, Igor; Gorini, Benedetto; Gorini, Edoardo; Gorišek, Andrej; Gornicki, Edward; Goshaw, Alfred; Gössling, Claus; Gostkin, Mikhail Ivanovitch; Gouighri, Mohamed; Goujdami, Driss; Goulette, Marc Phillippe; Goussiou, Anna; Goy, Corinne; Gozpinar, Serdar; Grabas, Herve Marie Xavier; Graber, Lars; Grabowska-Bold, Iwona; Grafström, Per; Grahn, Karl-Johan; Gramling, Johanna; Gramstad, Eirik; Grancagnolo, Sergio; Grassi, Valerio; Gratchev, Vadim; Gray, Heather; Graziani, Enrico; Grebenyuk, Oleg; Greenwood, Zeno Dixon; Gregersen, Kristian; Gregor, Ingrid-Maria; Grenier, Philippe; Griffiths, Justin; Grillo, Alexander; Grimm, Kathryn; Grinstein, Sebastian; Gris, Philippe Luc Yves; Grishkevich, Yaroslav; Grivaz, Jean-Francois; Grohs, Johannes Philipp; Grohsjean, Alexander; Gross, Eilam; Grosse-Knetter, Joern; Grossi, Giulio Cornelio; Groth-Jensen, Jacob; Grout, Zara Jane; Guan, Liang; Guescini, Francesco; Guest, Daniel; Gueta, Orel; Guicheney, Christophe; Guido, Elisa; Guillemin, Thibault; Guindon, Stefan; Gul, Umar; Gumpert, Christian; Gunther, Jaroslav; Guo, Jun; Gupta, Shaun; Gutierrez, Phillip; Gutierrez Ortiz, Nicolas Gilberto; Gutschow, Christian; Guttman, Nir; Guyot, Claude; Gwenlan, Claire; Gwilliam, Carl; Haas, Andy; Haber, Carl; Hadavand, Haleh Khani; Haddad, Nacim; Haefner, Petra; Hageböck, Stephan; Hajduk, Zbigniew; Hakobyan, Hrachya; Haleem, Mahsana; Hall, David; Halladjian, Garabed; Hamacher, Klaus; Hamal, Petr; Hamano, Kenji; Hamer, Matthias; Hamilton, Andrew; Hamilton, Samuel; Hamnett, Phillip George; Han, Liang; Hanagaki, Kazunori; Hanawa, Keita; Hance, Michael; Hanke, Paul; Hanna, Remie; Hansen, Jørgen Beck; Hansen, Jorn Dines; Hansen, Peter Henrik; Hara, Kazuhiko; Hard, Andrew; Harenberg, Torsten; Hariri, Faten; Harkusha, Siarhei; Harper, Devin; Harrington, Robert; Harris, Orin; Harrison, Paul Fraser; Hartjes, Fred; Hasegawa, Satoshi; Hasegawa, Yoji; Hasib, A; Hassani, Samira; Haug, Sigve; Hauschild, Michael; Hauser, Reiner; Havranek, Miroslav; Hawkes, Christopher; Hawkings, Richard John; Hawkins, Anthony David; Hayashi, Takayasu; Hayden, Daniel; Hays, Chris; Hayward, Helen; Haywood, Stephen; Head, Simon; Heck, Tobias; Hedberg, Vincent; Heelan, Louise; Heim, Sarah; Heim, Timon; Heinemann, Beate; Heinrich, Lukas; Hejbal, Jiri; Helary, Louis; Heller, Claudio; Heller, Matthieu; Hellman, Sten; Hellmich, Dennis; Helsens, Clement; Henderson, James; Henderson, Robert; Heng, Yang; Hengler, Christopher; Henrichs, Anna; Henriques Correia, Ana Maria; Henrot-Versille, Sophie; Hensel, Carsten; Herbert, Geoffrey Henry; Hernández Jiménez, Yesenia; Herrberg-Schubert, Ruth; Herten, Gregor; Hertenberger, Ralf; Hervas, Luis; Hesketh, Gavin Grant; Hessey, Nigel; Hickling, Robert; Higón-Rodriguez, Emilio; Hill, Ewan; Hill, John; Hiller, Karl Heinz; Hillert, Sonja; Hillier, Stephen; Hinchliffe, Ian; Hines, Elizabeth; Hirose, Minoru; Hirschbuehl, Dominic; Hobbs, John; Hod, Noam; Hodgkinson, Mark; Hodgson, Paul; Hoecker, Andreas; Hoeferkamp, Martin; Hoffman, Julia; Hoffmann, Dirk; Hofmann, Julia Isabell; Hohlfeld, Marc; Holmes, Tova Ray; Hong, Tae Min; Hooft van Huysduynen, Loek; Hostachy, Jean-Yves; Hou, Suen; Hoummada, Abdeslam; Howard, Jacob; Howarth, James; Hrabovsky, Miroslav; Hristova, Ivana; Hrivnac, Julius; Hryn'ova, Tetiana; Hsu, Catherine; Hsu, Pai-hsien Jennifer; Hsu, Shih-Chieh; Hu, Diedi; Hu, Xueye; Huang, Yanping; Hubacek, Zdenek; Hubaut, Fabrice; Huegging, Fabian; Huffman, Todd Brian; Hughes, Emlyn; Hughes, Gareth; Huhtinen, Mika; Hülsing, Tobias Alexander; Hurwitz, Martina; Huseynov, Nazim; Huston, Joey; Huth, John; Iacobucci, Giuseppe; Iakovidis, Georgios; Ibragimov, Iskander; Iconomidou-Fayard, Lydia; Ideal, Emma; Iengo, Paolo; Igonkina, Olga; Iizawa, Tomoya; Ikegami, Yoichi; Ikematsu, Katsumasa; Ikeno, Masahiro; Ilchenko, Iurii; Iliadis, Dimitrios; Ilic, Nikolina; Inamaru, Yuki; Ince, Tayfun; Ioannou, Pavlos; Iodice, Mauro; Iordanidou, Kalliopi; Ippolito, Valerio; Irles Quiles, Adrian; Isaksson, Charlie; Ishino, Masaya; Ishitsuka, Masaki; Ishmukhametov, Renat; Issever, Cigdem; Istin, Serhat; Iturbe Ponce, Julia Mariana; Iuppa, Roberto; Ivarsson, Jenny; Iwanski, Wieslaw; Iwasaki, Hiroyuki; Izen, Joseph; Izzo, Vincenzo; Jackson, Brett; Jackson, Matthew; Jackson, Paul; Jaekel, Martin; Jain, Vivek; Jakobs, Karl; Jakobsen, Sune; Jakoubek, Tomas; Jakubek, Jan; Jamin, David Olivier; Jana, Dilip; Jansen, Eric; Jansen, Hendrik; Janssen, Jens; Janus, Michel; Jarlskog, Göran; Javadov, Namig; Javůrek, Tomáš; Jeanty, Laura; Jejelava, Juansher; Jeng, Geng-yuan; Jennens, David; Jenni, Peter; Jentzsch, Jennifer; Jeske, Carl; Jézéquel, Stéphane; Ji, Haoshuang; Ji, Weina; Jia, Jiangyong; Jiang, Yi; Jimenez Belenguer, Marcos; Jin, Shan; Jinaru, Adam; Jinnouchi, Osamu; Joergensen, Morten Dam; Johansson, Erik; Johansson, Per; Johns, Kenneth; Jon-And, Kerstin; Jones, Graham; Jones, Roger; Jones, Tim; Jongmanns, Jan; Jorge, Pedro; Joshi, Kiran Daniel; Jovicevic, Jelena; Ju, Xiangyang; Jung, Christian; Jungst, Ralph Markus; Jussel, Patrick; Juste Rozas, Aurelio; Kaci, Mohammed; Kaczmarska, Anna; Kado, Marumi; Kagan, Harris; Kagan, Michael; Kajomovitz, Enrique; Kalderon, Charles William; Kama, Sami; Kamenshchikov, Andrey; Kanaya, Naoko; Kaneda, Michiru; Kaneti, Steven; Kantserov, Vadim; Kanzaki, Junichi; Kaplan, Benjamin; Kapliy, Anton; Kar, Deepak; Karakostas, Konstantinos; Karastathis, Nikolaos; Karnevskiy, Mikhail; Karpov, Sergey; Karpova, Zoya; Karthik, Krishnaiyengar; Kartvelishvili, Vakhtang; Karyukhin, Andrey; Kashif, Lashkar; Kasieczka, Gregor; Kass, Richard; Kastanas, Alex; Kataoka, Yousuke; Katre, Akshay; Katzy, Judith; Kaushik, Venkatesh; Kawagoe, Kiyotomo; Kawamoto, Tatsuo; Kawamura, Gen; Kazama, Shingo; Kazanin, Vassili; Kazarinov, Makhail; Keeler, Richard; Kehoe, Robert; Keil, Markus; Keller, John; Kempster, Jacob Julian; Keoshkerian, Houry; Kepka, Oldrich; Kerševan, Borut Paul; Kersten, Susanne; Kessoku, Kohei; Keung, Justin; Khalil-zada, Farkhad; Khandanyan, Hovhannes; Khanov, Alexander; Khodinov, Alexander; Khomich, Andrei; Khoo, Teng Jian; Khoriauli, Gia; Khoroshilov, Andrey; Khovanskiy, Valery; Khramov, Evgeniy; Khubua, Jemal; Kim, Hee Yeun; Kim, Hyeon Jin; Kim, Shinhong; Kimura, Naoki; Kind, Oliver; King, Barry; King, Matthew; King, Robert Steven Beaufoy; King, Samuel Burton; Kirk, Julie; Kiryunin, Andrey; Kishimoto, Tomoe; Kisielewska, Danuta; Kiss, Florian; Kittelmann, Thomas; Kiuchi, Kenji; Kladiva, Eduard; Klein, Max; Klein, Uta; Kleinknecht, Konrad; Klimek, Pawel; Klimentov, Alexei; Klingenberg, Reiner; Klinger, Joel Alexander; Klioutchnikova, Tatiana; Klok, Peter; Kluge, Eike-Erik; Kluit, Peter; Kluth, Stefan; Kneringer, Emmerich; Knoops, Edith; Knue, Andrea; Kobayashi, Dai; Kobayashi, Tomio; Kobel, Michael; Kocian, Martin; Kodys, Peter; Koevesarki, Peter; Koffas, Thomas; Koffeman, Els; Kogan, Lucy Anne; Kohlmann, Simon; Kohout, Zdenek; Kohriki, Takashi; Koi, Tatsumi; Kolanoski, Hermann; Koletsou, Iro; Koll, James; Komar, Aston; Komori, Yuto; Kondo, Takahiko; Kondrashova, Nataliia; Köneke, Karsten; König, Adriaan; König, Sebastian; Kono, Takanori; Konoplich, Rostislav; Konstantinidis, Nikolaos; Kopeliansky, Revital; Koperny, Stefan; Köpke, Lutz; Kopp, Anna Katharina; Korcyl, Krzysztof; Kordas, Kostantinos; Korn, Andreas; Korol, Aleksandr; Korolkov, Ilya; Korolkova, Elena; Korotkov, Vladislav; Kortner, Oliver; Kortner, Sandra; Kostyukhin, Vadim; Kotov, Vladislav; Kotwal, Ashutosh; Kourkoumelis, Christine; Kouskoura, Vasiliki; Koutsman, Alex; Kowalewski, Robert Victor; Kowalski, Tadeusz; Kozanecki, Witold; Kozhin, Anatoly; Kral, Vlastimil; Kramarenko, Viktor; Kramberger, Gregor; Krasnopevtsev, Dimitriy; Krasny, Mieczyslaw Witold; Krasznahorkay, Attila; Kraus, Jana; Kravchenko, Anton; Kreiss, Sven; Kretz, Moritz; Kretzschmar, Jan; Kreutzfeldt, Kristof; Krieger, Peter; Kroeninger, Kevin; Kroha, Hubert; Kroll, Joe; Kroseberg, Juergen; Krstic, Jelena; Kruchonak, Uladzimir; Krüger, Hans; Kruker, Tobias; Krumnack, Nils; Krumshteyn, Zinovii; Kruse, Amanda; Kruse, Mark; Kruskal, Michael; Kubota, Takashi; Kuday, Sinan; Kuehn, Susanne; Kugel, Andreas; Kuhl, Andrew; Kuhl, Thorsten; Kukhtin, Victor; Kulchitsky, Yuri; Kuleshov, Sergey; Kuna, Marine; Kunkle, Joshua; Kupco, Alexander; Kurashige, Hisaya; Kurochkin, Yurii; Kurumida, Rie; Kus, Vlastimil; Kuwertz, Emma Sian; Kuze, Masahiro; Kvita, Jiri; La Rosa, Alessandro; La Rotonda, Laura; Lacasta, Carlos; Lacava, Francesco; Lacey, James; Lacker, Heiko; Lacour, Didier; Lacuesta, Vicente Ramón; Ladygin, Evgueni; Lafaye, Remi; Laforge, Bertrand; Lagouri, Theodota; Lai, Stanley; Laier, Heiko; Lambourne, Luke; Lammers, Sabine; Lampen, Caleb; Lampl, Walter; Lançon, Eric; Landgraf, Ulrich; Landon, Murrough; Lang, Valerie Susanne; Lankford, Andrew; Lanni, Francesco; Lantzsch, Kerstin; Laplace, Sandrine; Lapoire, Cecile; Laporte, Jean-Francois; Lari, Tommaso; Lassnig, Mario; Laurelli, Paolo; Lavrijsen, Wim; Law, Alexander; Laycock, Paul; Le, Bao Tran; Le Dortz, Olivier; Le Guirriec, Emmanuel; Le Menedeu, Eve; LeCompte, Thomas; Ledroit-Guillon, Fabienne Agnes Marie; Lee, Claire Alexandra; Lee, Hurng-Chun; Lee, Jason; Lee, Shih-Chang; Lee, Lawrence; Lefebvre, Guillaume; Lefebvre, Michel; Legger, Federica; Leggett, Charles; Lehan, Allan; Lehmacher, Marc; Lehmann Miotto, Giovanna; Lei, Xiaowen; Leight, William Axel; Leisos, Antonios; Leister, Andrew Gerard; Leite, Marco Aurelio Lisboa; Leitner, Rupert; Lellouch, Daniel; Lemmer, Boris; Leney, Katharine; Lenz, Tatjana; Lenzen, Georg; Lenzi, Bruno; Leone, Robert; Leone, Sandra; Leonhardt, Kathrin; Leonidopoulos, Christos; Leontsinis, Stefanos; Leroy, Claude; Lester, Christopher; Lester, Christopher Michael; Levchenko, Mikhail; Levêque, Jessica; Levin, Daniel; Levinson, Lorne; Levy, Mark; Lewis, Adrian; Lewis, George; Leyko, Agnieszka; Leyton, Michael; Li, Bing; Li, Bo; Li, Haifeng; Li, Ho Ling; Li, Lei; Li, Liang; Li, Shu; Li, Yichen; Liang, Zhijun; Liao, Hongbo; Liberti, Barbara; Lichard, Peter; Lie, Ki; Liebal, Jessica; Liebig, Wolfgang; Limbach, Christian; Limosani, Antonio; Lin, Simon; Lin, Tai-Hua; Linde, Frank; Lindquist, Brian Edward; Linnemann, James; Lipeles, Elliot; Lipniacka, Anna; Lisovyi, Mykhailo; Liss, Tony; Lissauer, David; Lister, Alison; Litke, Alan; Liu, Bo; Liu, Dong; Liu, Jianbei; Liu, Kun; Liu, Lulu; Liu, Miaoyuan; Liu, Minghui; Liu, Yanwen; Livan, Michele; Livermore, Sarah; Lleres, Annick; Llorente Merino, Javier; Lloyd, Stephen; Lo Sterzo, Francesco; Lobodzinska, Ewelina; Loch, Peter; Lockman, William; Loddenkoetter, Thomas; Loebinger, Fred; Loevschall-Jensen, Ask Emil; Loginov, Andrey; Loh, Chang Wei; Lohse, Thomas; Lohwasser, Kristin; Lokajicek, Milos; Lombardo, Vincenzo Paolo; Long, Brian Alexander; Long, Jonathan; Long, Robin Eamonn; Lopes, Lourenco; Lopez Mateos, David; Lopez Paredes, Brais; Lopez Paz, Ivan; Lorenz, Jeanette; Lorenzo Martinez, Narei; Losada, Marta; Loscutoff, Peter; Lou, XinChou; Lounis, Abdenour; Love, Jeremy; Love, Peter; Lowe, Andrew; Lu, Feng; Lubatti, Henry; Luci, Claudio; Lucotte, Arnaud; Luehring, Frederick; Lukas, Wolfgang; Luminari, Lamberto; Lundberg, Olof; Lund-Jensen, Bengt; Lungwitz, Matthias; Lynn, David; Lysak, Roman; Lytken, Else; Ma, Hong; Ma, Lian Liang; Maccarrone, Giovanni; Macchiolo, Anna; Machado Miguens, Joana; Macina, Daniela; Madaffari, Daniele; Madar, Romain; Maddocks, Harvey Jonathan; Mader, Wolfgang; Madsen, Alexander; Maeno, Mayuko; Maeno, Tadashi; Magradze, Erekle; Mahboubi, Kambiz; Mahlstedt, Joern; Mahmoud, Sara; Maiani, Camilla; Maidantchik, Carmen; Maier, Andreas Alexander; Maio, Amélia; Majewski, Stephanie; Makida, Yasuhiro; Makovec, Nikola; Mal, Prolay; Malaescu, Bogdan; Malecki, Pawel; Maleev, Victor; Malek, Fairouz; Mallik, Usha; Malon, David; Malone, Caitlin; Maltezos, Stavros; Malyshev, Vladimir; Malyukov, Sergei; Mamuzic, Judita; Mandelli, Beatrice; Mandelli, Luciano; Mandić, Igor; Mandrysch, Rocco; Maneira, José; Manfredini, Alessandro; Manhaes de Andrade Filho, Luciano; Manjarres Ramos, Joany Andreina; Mann, Alexander; Manning, Peter; Manousakis-Katsikakis, Arkadios; Mansoulie, Bruno; Mantifel, Rodger; Mapelli, Livio; March, Luis; Marchand, Jean-Francois; Marchiori, Giovanni; Marcisovsky, Michal; Marino, Christopher; Marjanovic, Marija; Marques, Carlos; Marroquim, Fernando; Marsden, Stephen Philip; Marshall, Zach; Marti, Lukas Fritz; Marti-Garcia, Salvador; Martin, Brian; Martin, Brian Thomas; Martin, Tim; Martin, Victoria Jane; Martin dit Latour, Bertrand; Martinez, Homero; Martinez, Mario; Martin-Haugh, Stewart; Martyniuk, Alex; Marx, Marilyn; Marzano, Francesco; Marzin, Antoine; Masetti, Lucia; Mashimo, Tetsuro; Mashinistov, Ruslan; Masik, Jiri; Maslennikov, Alexey; Massa, Ignazio; Massol, Nicolas; Mastrandrea, Paolo; Mastroberardino, Anna; Masubuchi, Tatsuya; Mättig, Peter; Mattmann, Johannes; Maurer, Julien; Maxfield, Stephen; Maximov, Dmitriy; Mazini, Rachid; Mazzaferro, Luca; Mc Goldrick, Garrin; Mc Kee, Shawn Patrick; McCarn, Allison; McCarthy, Robert; McCarthy, Tom; McCubbin, Norman; McFarlane, Kenneth; Mcfayden, Josh; Mchedlidze, Gvantsa; McMahon, Steve; McPherson, Robert; Meade, Andrew; Mechnich, Joerg; Medinnis, Michael; Meehan, Samuel; Mehlhase, Sascha; Mehta, Andrew; Meier, Karlheinz; Meineck, Christian; Meirose, Bernhard; Melachrinos, Constantinos; Mellado Garcia, Bruce Rafael; Meloni, Federico; Mengarelli, Alberto; Menke, Sven; Meoni, Evelin; Mercurio, Kevin Michael; Mergelmeyer, Sebastian; Meric, Nicolas; Mermod, Philippe; Merola, Leonardo; Meroni, Chiara; Merritt, Frank; Merritt, Hayes; Messina, Andrea; Metcalfe, Jessica; Mete, Alaettin Serhan; Meyer, Carsten; Meyer, Christopher; Meyer, Jean-Pierre; Meyer, Jochen; Middleton, Robin; Migas, Sylwia; Mijović, Liza; Mikenberg, Giora; Mikestikova, Marcela; Mikuž, Marko; Milic, Adriana; Miller, David; Mills, Corrinne; Milov, Alexander; Milstead, David; Milstein, Dmitry; Minaenko, Andrey; Minashvili, Irakli; Mincer, Allen; Mindur, Bartosz; Mineev, Mikhail; Ming, Yao; Mir, Lluisa-Maria; Mirabelli, Giovanni; Mitani, Takashi; Mitrevski, Jovan; Mitsou, Vasiliki A; Mitsui, Shingo; Miucci, Antonio; Miyagawa, Paul; Mjörnmark, Jan-Ulf; Moa, Torbjoern; Mochizuki, Kazuya; Mohapatra, Soumya; Mohr, Wolfgang; Molander, Simon; Moles-Valls, Regina; Mönig, Klaus; Monini, Caterina; Monk, James; Monnier, Emmanuel; Montejo Berlingen, Javier; Monticelli, Fernando; Monzani, Simone; Moore, Roger; Moraes, Arthur; Morange, Nicolas; Moreno, Deywis; Moreno Llácer, María; Morettini, Paolo; Morgenstern, Marcus; Morii, Masahiro; Moritz, Sebastian; Morley, Anthony Keith; Mornacchi, Giuseppe; Morris, John; Morvaj, Ljiljana; Moser, Hans-Guenther; Mosidze, Maia; Moss, Josh; Motohashi, Kazuki; Mount, Richard; Mountricha, Eleni; Mouraviev, Sergei; Moyse, Edward; Muanza, Steve; Mudd, Richard; Mueller, Felix; Mueller, James; Mueller, Klemens; Mueller, Thibaut; Mueller, Timo; Muenstermann, Daniel; Munwes, Yonathan; Murillo Quijada, Javier Alberto; Murray, Bill; Musheghyan, Haykuhi; Musto, Elisa; Myagkov, Alexey; Myska, Miroslav; Nackenhorst, Olaf; Nadal, Jordi; Nagai, Koichi; Nagai, Ryo; Nagai, Yoshikazu; Nagano, Kunihiro; Nagarkar, Advait; Nagasaka, Yasushi; Nagel, Martin; Nairz, Armin Michael; Nakahama, Yu; Nakamura, Koji; Nakamura, Tomoaki; Nakano, Itsuo; Namasivayam, Harisankar; Nanava, Gizo; Narayan, Rohin; Nattermann, Till; Naumann, Thomas; Navarro, Gabriela; Nayyar, Ruchika; Neal, Homer; Nechaeva, Polina; Neep, Thomas James; Nef, Pascal Daniel; Negri, Andrea; Negri, Guido; Negrini, Matteo; Nektarijevic, Snezana; Nelson, Andrew; Nelson, Timothy Knight; Nemecek, Stanislav; Nemethy, Peter; Nepomuceno, Andre Asevedo; Nessi, Marzio; Neubauer, Mark; Neumann, Manuel; Neves, Ricardo; Nevski, Pavel; Newman, Paul; Nguyen, Duong Hai; Nickerson, Richard; Nicolaidou, Rosy; Nicquevert, Bertrand; Nielsen, Jason; Nikiforou, Nikiforos; Nikiforov, Andriy; Nikolaenko, Vladimir; Nikolic-Audit, Irena; Nikolics, Katalin; Nikolopoulos, Konstantinos; Nilsson, Paul; Ninomiya, Yoichi; Nisati, Aleandro; Nisius, Richard; Nobe, Takuya; Nodulman, Lawrence; Nomachi, Masaharu; Nomidis, Ioannis; Norberg, Scarlet; Nordberg, Markus; Novgorodova, Olga; Nowak, Sebastian; Nozaki, Mitsuaki; Nozka, Libor; Ntekas, Konstantinos; Nunes Hanninger, Guilherme; Nunnemann, Thomas; Nurse, Emily; Nuti, Francesco; O'Brien, Brendan Joseph; O'grady, Fionnbarr; O'Neil, Dugan; O'Shea, Val; Oakham, Gerald; Oberlack, Horst; Obermann, Theresa; Ocariz, Jose; Ochi, Atsuhiko; Ochoa, Ines; Oda, Susumu; Odaka, Shigeru; Ogren, Harold; Oh, Alexander; Oh, Seog; Ohm, Christian; Ohman, Henrik; Ohshima, Takayoshi; Okamura, Wataru; Okawa, Hideki; Okumura, Yasuyuki; Okuyama, Toyonobu; Olariu, Albert; Olchevski, Alexander; Olivares Pino, Sebastian Andres; Oliveira Damazio, Denis; Oliver Garcia, Elena; Olszewski, Andrzej; Olszowska, Jolanta; Onofre, António; Onyisi, Peter; Oram, Christopher; Oreglia, Mark; Oren, Yona; Orestano, Domizia; Orlando, Nicola; Oropeza Barrera, Cristina; Orr, Robert; Osculati, Bianca; Ospanov, Rustem; Otero y Garzon, Gustavo; Otono, Hidetoshi; Ouchrif, Mohamed; Ouellette, Eric; Ould-Saada, Farid; Ouraou, Ahmimed; Oussoren, Koen Pieter; Ouyang, Qun; Ovcharova, Ana; Owen, Mark; Ozcan, Veysi Erkcan; Ozturk, Nurcan; Pachal, Katherine; Pacheco Pages, Andres; Padilla Aranda, Cristobal; Pagáčová, Martina; Pagan Griso, Simone; Paganis, Efstathios; Pahl, Christoph; Paige, Frank; Pais, Preema; Pajchel, Katarina; Palacino, Gabriel; Palestini, Sandro; Palka, Marek; Pallin, Dominique; Palma, Alberto; Palmer, Jody; Pan, Yibin; Panagiotopoulou, Evgenia; Panduro Vazquez, William; Pani, Priscilla; Panikashvili, Natalia; Panitkin, Sergey; Pantea, Dan; Paolozzi, Lorenzo; Papadopoulou, Theodora; Papageorgiou, Konstantinos; Paramonov, Alexander; Paredes Hernandez, Daniela; Parker, Michael Andrew; Parodi, Fabrizio; Parsons, John; Parzefall, Ulrich; Pasqualucci, Enrico; Passaggio, Stefano; Passeri, Antonio; Pastore, Fernanda; Pastore, Francesca; Pásztor, Gabriella; Pataraia, Sophio; Patel, Nikhul; Pater, Joleen; Patricelli, Sergio; Pauly, Thilo; Pearce, James; Pedersen, Maiken; Pedraza Lopez, Sebastian; Pedro, Rute; Peleganchuk, Sergey; Pelikan, Daniel; Peng, Haiping; Penning, Bjoern; Penwell, John; Perepelitsa, Dennis; Perez Codina, Estel; Pérez García-Estañ, María Teresa; Perez Reale, Valeria; Perini, Laura; Pernegger, Heinz; Perrino, Roberto; Peschke, Richard; Peshekhonov, Vladimir; Peters, Krisztian; Peters, Yvonne; Petersen, Brian; Petersen, Troels; Petit, Elisabeth; Petridis, Andreas; Petridou, Chariclia; Petrolo, Emilio; Petrucci, Fabrizio; Pettersson, Nora Emilia; Pezoa, Raquel; Phillips, Peter William; Piacquadio, Giacinto; Pianori, Elisabetta; Picazio, Attilio; Piccaro, Elisa; Piccinini, Maurizio; Piegaia, Ricardo; Pignotti, David; Pilcher, James; Pilkington, Andrew; Pina, João Antonio; Pinamonti, Michele; Pinder, Alex; Pinfold, James; Pingel, Almut; Pinto, Belmiro; Pires, Sylvestre; Pitt, Michael; Pizio, Caterina; Plazak, Lukas; Pleier, Marc-Andre; Pleskot, Vojtech; Plotnikova, Elena; Plucinski, Pawel; Poddar, Sahill; Podlyski, Fabrice; Poettgen, Ruth; Poggioli, Luc; Pohl, David-leon; Pohl, Martin; Polesello, Giacomo; Policicchio, Antonio; Polifka, Richard; Polini, Alessandro; Pollard, Christopher Samuel; Polychronakos, Venetios; Pommès, Kathy; Pontecorvo, Ludovico; Pope, Bernard; Popeneciu, Gabriel Alexandru; Popovic, Dragan; Poppleton, Alan; Portell Bueso, Xavier; Pospisil, Stanislav; Potamianos, Karolos; Potrap, Igor; Potter, Christina; Potter, Christopher; Poulard, Gilbert; Poveda, Joaquin; Pozdnyakov, Valery; Pralavorio, Pascal; Pranko, Aliaksandr; Prasad, Srivas; Pravahan, Rishiraj; Prell, Soeren; Price, Darren; Price, Joe; Price, Lawrence; Prieur, Damien; Primavera, Margherita; Proissl, Manuel; Prokofiev, Kirill; Prokoshin, Fedor; Protopapadaki, Eftychia-sofia; Protopopescu, Serban; Proudfoot, James; Przybycien, Mariusz; Przysiezniak, Helenka; Ptacek, Elizabeth; Puddu, Daniele; Pueschel, Elisa; Puldon, David; Purohit, Milind; Puzo, Patrick; Qian, Jianming; Qin, Gang; Qin, Yang; Quadt, Arnulf; Quarrie, David; Quayle, William; Queitsch-Maitland, Michaela; Quilty, Donnchadha; Qureshi, Anum; Radeka, Veljko; Radescu, Voica; Radhakrishnan, Sooraj Krishnan; Radloff, Peter; Rados, Pere; Ragusa, Francesco; Rahal, Ghita; Rajagopalan, Srinivasan; Rammensee, Michael; Randle-Conde, Aidan Sean; Rangel-Smith, Camila; Rao, Kanury; Rauscher, Felix; Rave, Tobias Christian; Ravenscroft, Thomas; Raymond, Michel; Read, Alexander Lincoln; Readioff, Nathan Peter; Rebuzzi, Daniela; Redelbach, Andreas; Redlinger, George; Reece, Ryan; Reeves, Kendall; Rehnisch, Laura; Reisin, Hernan; Relich, Matthew; Rembser, Christoph; Ren, Huan; Ren, Zhongliang; Renaud, Adrien; Rescigno, Marco; Resconi, Silvia; Rezanova, Olga; Reznicek, Pavel; Rezvani, Reyhaneh; Richter, Robert; Ridel, Melissa; Rieck, Patrick; Rieger, Julia; Rijssenbeek, Michael; Rimoldi, Adele; Rinaldi, Lorenzo; Ritsch, Elmar; Riu, Imma; Rizatdinova, Flera; Rizvi, Eram; Robertson, Steven; Robichaud-Veronneau, Andree; Robinson, Dave; Robinson, James; Robson, Aidan; Roda, Chiara; Rodrigues, Luis; Roe, Shaun; Røhne, Ole; Rolli, Simona; Romaniouk, Anatoli; Romano, Marino; Romero Adam, Elena; Rompotis, Nikolaos; Roos, Lydia; Ros, Eduardo; Rosati, Stefano; Rosbach, Kilian; Rose, Matthew; Rosendahl, Peter Lundgaard; Rosenthal, Oliver; Rossetti, Valerio; Rossi, Elvira; Rossi, Leonardo Paolo; Rosten, Rachel; Rotaru, Marina; Roth, Itamar; Rothberg, Joseph; Rousseau, David; Royon, Christophe; Rozanov, Alexandre; Rozen, Yoram; Ruan, Xifeng; Rubbo, Francesco; Rubinskiy, Igor; Rud, Viacheslav; Rudolph, Christian; Rudolph, Matthew Scott; Rühr, Frederik; Ruiz-Martinez, Aranzazu; Rurikova, Zuzana; Rusakovich, Nikolai; Ruschke, Alexander; Rutherfoord, John; Ruthmann, Nils; Ryabov, Yury; Rybar, Martin; Rybkin, Grigori; Ryder, Nick; Saavedra, Aldo; Sacerdoti, Sabrina; Saddique, Asif; Sadeh, Iftach; Sadrozinski, Hartmut; Sadykov, Renat; Safai Tehrani, Francesco; Sakamoto, Hiroshi; Sakurai, Yuki; Salamanna, Giuseppe; Salamon, Andrea; Saleem, Muhammad; Salek, David; Sales De Bruin, Pedro Henrique; Salihagic, Denis; Salnikov, Andrei; Salt, José; Salvachua Ferrando, Belén; Salvatore, Daniela; Salvatore, Pasquale Fabrizio; Salvucci, Antonio; Salzburger, Andreas; Sampsonidis, Dimitrios; Sanchez, Arturo; Sánchez, Javier; Sanchez Martinez, Victoria; Sandaker, Heidi; Sandbach, Ruth Laura; Sander, Heinz Georg; Sanders, Michiel; Sandhoff, Marisa; Sandoval, Tanya; Sandoval, Carlos; Sandstroem, Rikard; Sankey, Dave; Sansoni, Andrea; Santoni, Claudio; Santonico, Rinaldo; Santos, Helena; Santoyo Castillo, Itzebelt; Sapp, Kevin; Sapronov, Andrey; Saraiva, João; Sarrazin, Bjorn; Sartisohn, Georg; Sasaki, Osamu; Sasaki, Yuichi; Sauvage, Gilles; Sauvan, Emmanuel; Savard, Pierre; Savu, Dan Octavian; Sawyer, Craig; Sawyer, Lee; Saxon, David; Saxon, James; Sbarra, Carla; Sbrizzi, Antonio; Scanlon, Tim; Scannicchio, Diana; Scarcella, Mark; Scarfone, Valerio; Schaarschmidt, Jana; Schacht, Peter; Schaefer, Douglas; Schaefer, Ralph; Schaepe, Steffen; Schaetzel, Sebastian; Schäfer, Uli; Schaffer, Arthur; Schaile, Dorothee; Schamberger, R. Dean; Scharf, Veit; Schegelsky, Valery; Scheirich, Daniel; Schernau, Michael; Scherzer, Max; Schiavi, Carlo; Schieck, Jochen; Schillo, Christian; Schioppa, Marco; Schlenker, Stefan; Schmidt, Evelyn; Schmieden, Kristof; Schmitt, Christian; Schmitt, Christopher; Schmitt, Sebastian; Schneider, Basil; Schnellbach, Yan Jie; Schnoor, Ulrike; Schoeffel, Laurent; Schoening, Andre; Schoenrock, Bradley Daniel; Schorlemmer, Andre Lukas; Schott, Matthias; Schouten, Doug; Schovancova, Jaroslava; Schramm, Steven; Schreyer, Manuel; Schroeder, Christian; Schuh, Natascha; Schultens, Martin Johannes; Schultz-Coulon, Hans-Christian; Schulz, Holger; Schumacher, Markus; Schumm, Bruce; Schune, Philippe; Schwanenberger, Christian; Schwartzman, Ariel; Schwegler, Philipp; Schwemling, Philippe; Schwienhorst, Reinhard; Schwindling, Jerome; Schwindt, Thomas; Schwoerer, Maud; Sciacca, Gianfranco; Scifo, Estelle; Sciolla, Gabriella; Scott, Bill; Scuri, Fabrizio; Scutti, Federico; Searcy, Jacob; Sedov, George; Sedykh, Evgeny; Seidel, Sally; Seiden, Abraham; Seifert, Frank; Seixas, José; Sekhniaidze, Givi; Sekula, Stephen; Selbach, Karoline Elfriede; Seliverstov, Dmitry; Sellers, Graham; Semprini-Cesari, Nicola; Serfon, Cedric; Serin, Laurent; Serkin, Leonid; Serre, Thomas; Seuster, Rolf; Severini, Horst; Sfiligoj, Tina; Sforza, Federico; Sfyrla, Anna; Shabalina, Elizaveta; Shamim, Mansoora; Shan, Lianyou; Shang, Ruo-yu; Shank, James; Shapiro, Marjorie; Shatalov, Pavel; Shaw, Kate; Shehu, Ciwake Yusufu; Sherwood, Peter; Shi, Liaoshan; Shimizu, Shima; Shimmin, Chase Owen; Shimojima, Makoto; Shiyakova, Mariya; Shmeleva, Alevtina; Shochet, Mel; Short, Daniel; Shrestha, Suyog; Shulga, Evgeny; Shupe, Michael; Shushkevich, Stanislav; Sicho, Petr; Sidiropoulou, Ourania; Sidorov, Dmitri; Sidoti, Antonio; Siegert, Frank; Sijacki, Djordje; Silva, José; Silver, Yiftah; Silverstein, Daniel; Silverstein, Samuel; Simak, Vladislav; Simard, Olivier; Simic, Ljiljana; Simion, Stefan; Simioni, Eduard; Simmons, Brinick; Simoniello, Rosa; Simonyan, Margar; Sinervo, Pekka; Sinev, Nikolai; Sipica, Valentin; Siragusa, Giovanni; Sircar, Anirvan; Sisakyan, Alexei; Sivoklokov, Serguei; Sjölin, Jörgen; Sjursen, Therese; Skottowe, Hugh Philip; Skovpen, Kirill; Skubic, Patrick; Slater, Mark; Slavicek, Tomas; Sliwa, Krzysztof; Smakhtin, Vladimir; Smart, Ben; Smestad, Lillian; Smirnov, Sergei; Smirnov, Yury; Smirnova, Lidia; Smirnova, Oxana; Smith, Kenway; Smizanska, Maria; Smolek, Karel; Snesarev, Andrei; Snidero, Giacomo; Snyder, Scott; Sobie, Randall; Socher, Felix; Soffer, Abner; Soh, Dart-yin; Solans, Carlos; Solar, Michael; Solc, Jaroslav; Soldatov, Evgeny; Soldevila, Urmila; Solfaroli Camillocci, Elena; Solodkov, Alexander; Soloshenko, Alexei; Solovyanov, Oleg; Solovyev, Victor; Sommer, Philip; Song, Hong Ye; Soni, Nitesh; Sood, Alexander; Sopczak, Andre; Sopko, Bruno; Sopko, Vit; Sorin, Veronica; Sosebee, Mark; Soualah, Rachik; Soueid, Paul; Soukharev, Andrey; South, David; Spagnolo, Stefania; Spanò, Francesco; Spearman, William Robert; Spettel, Fabian; Spighi, Roberto; Spigo, Giancarlo; Spousta, Martin; Spreitzer, Teresa; Spurlock, Barry; St Denis, Richard Dante; Staerz, Steffen; Stahlman, Jonathan; Stamen, Rainer; Stanecka, Ewa; Stanek, Robert; Stanescu, Cristian; Stanescu-Bellu, Madalina; Stanitzki, Marcel Michael; Stapnes, Steinar; Starchenko, Evgeny; Stark, Jan; Staroba, Pavel; Starovoitov, Pavel; Staszewski, Rafal; Stavina, Pavel; Steinberg, Peter; Stelzer, Bernd; Stelzer, Harald Joerg; Stelzer-Chilton, Oliver; Stenzel, Hasko; Stern, Sebastian; Stewart, Graeme; Stillings, Jan Andre; Stockton, Mark; Stoebe, Michael; Stoicea, Gabriel; Stolte, Philipp; Stonjek, Stefan; Stradling, Alden; Straessner, Arno; Stramaglia, Maria Elena; Strandberg, Jonas; Strandberg, Sara; Strandlie, Are; Strauss, Emanuel; Strauss, Michael; Strizenec, Pavol; Ströhmer, Raimund; Strom, David; Stroynowski, Ryszard; Stucci, Stefania Antonia; Stugu, Bjarne; Styles, Nicholas Adam; Su, Dong; Su, Jun; Subramania, Halasya Siva; Subramaniam, Rajivalochan; Succurro, Antonella; Sugaya, Yorihito; Suhr, Chad; Suk, Michal; Sulin, Vladimir; Sultansoy, Saleh; Sumida, Toshi; Sun, Xiaohu; Sundermann, Jan Erik; Suruliz, Kerim; Susinno, Giancarlo; Sutton, Mark; Suzuki, Yu; Svatos, Michal; Swedish, Stephen; Swiatlowski, Maximilian; Sykora, Ivan; Sykora, Tomas; Ta, Duc; Taccini, Cecilia; Tackmann, Kerstin; Taenzer, Joe; Taffard, Anyes; Tafirout, Reda; Taiblum, Nimrod; Takahashi, Yuta; Takai, Helio; Takashima, Ryuichi; Takeda, Hiroshi; Takeshita, Tohru; Takubo, Yosuke; Talby, Mossadek; Talyshev, Alexey; Tam, Jason; Tan, Kong Guan; Tanaka, Junichi; Tanaka, Reisaburo; Tanaka, Satoshi; Tanaka, Shuji; Tanasijczuk, Andres Jorge; Tannenwald, Benjamin Bordy; Tannoury, Nancy; Tapprogge, Stefan; Tarem, Shlomit; Tarrade, Fabien; Tartarelli, Giuseppe Francesco; Tas, Petr; Tasevsky, Marek; Tashiro, Takuya; Tassi, Enrico; Tavares Delgado, Ademar; Tayalati, Yahya; Taylor, Frank; Taylor, Geoffrey; Taylor, Wendy; Teischinger, Florian Alfred; Teixeira Dias Castanheira, Matilde; Teixeira-Dias, Pedro; Temming, Kim Katrin; Ten Kate, Herman; Teng, Ping-Kun; Teoh, Jia Jian; Terada, Susumu; Terashi, Koji; Terron, Juan; Terzo, Stefano; Testa, Marianna; Teuscher, Richard; Therhaag, Jan; Theveneaux-Pelzer, Timothée; Thomas, Juergen; Thomas-Wilsker, Joshuha; Thompson, Emily; Thompson, Paul; Thompson, Peter; Thompson, Stan; Thomsen, Lotte Ansgaard; Thomson, Evelyn; Thomson, Mark; Thong, Wai Meng; Thun, Rudolf; Tian, Feng; Tibbetts, Mark James; Tikhomirov, Vladimir; Tikhonov, Yury; Timoshenko, Sergey; Tiouchichine, Elodie; Tipton, Paul; Tisserant, Sylvain; Todorov, Theodore; Todorova-Nova, Sharka; Toggerson, Brokk; Tojo, Junji; Tokár, Stanislav; Tokushuku, Katsuo; Tollefson, Kirsten; Tomlinson, Lee; Tomoto, Makoto; Tompkins, Lauren; Toms, Konstantin; Topilin, Nikolai; Torrence, Eric; Torres, Heberth; Torró Pastor, Emma; Toth, Jozsef; Touchard, Francois; Tovey, Daniel; Tran, Huong Lan; Trefzger, Thomas; Tremblet, Louis; Tricoli, Alessandro; Trigger, Isabel Marian; Trincaz-Duvoid, Sophie; Tripiana, Martin; Triplett, Nathan; Trischuk, William; Trocmé, Benjamin; Troncon, Clara; Trottier-McDonald, Michel; Trovatelli, Monica; True, Patrick; Trzebinski, Maciej; Trzupek, Adam; Tsarouchas, Charilaos; Tseng, Jeffrey; Tsiareshka, Pavel; Tsionou, Dimitra; Tsipolitis, Georgios; Tsirintanis, Nikolaos; Tsiskaridze, Shota; Tsiskaridze, Vakhtang; Tskhadadze, Edisher; Tsukerman, Ilya; Tsulaia, Vakhtang; Tsuno, Soshi; Tsybychev, Dmitri; Tudorache, Alexandra; Tudorache, Valentina; Tuna, Alexander Naip; Tupputi, Salvatore; Turchikhin, Semen; Turecek, Daniel; Turk Cakir, Ilkay; Turra, Ruggero; Tuts, Michael; Tykhonov, Andrii; Tylmad, Maja; Tyndel, Mike; Uchida, Kirika; Ueda, Ikuo; Ueno, Ryuichi; Ughetto, Michael; Ugland, Maren; Uhlenbrock, Mathias; Ukegawa, Fumihiko; Unal, Guillaume; Undrus, Alexander; Unel, Gokhan; Ungaro, Francesca; Unno, Yoshinobu; Urbaniec, Dustin; Urquijo, Phillip; Usai, Giulio; Usanova, Anna; Vacavant, Laurent; Vacek, Vaclav; Vachon, Brigitte; Valencic, Nika; Valentinetti, Sara; Valero, Alberto; Valery, Loic; Valkar, Stefan; Valladolid Gallego, Eva; Vallecorsa, Sofia; Valls Ferrer, Juan Antonio; Van Den Wollenberg, Wouter; Van Der Deijl, Pieter; van der Geer, Rogier; van der Graaf, Harry; Van Der Leeuw, Robin; van der Ster, Daniel; van Eldik, Niels; van Gemmeren, Peter; Van Nieuwkoop, Jacobus; van Vulpen, Ivo; van Woerden, Marius Cornelis; Vanadia, Marco; Vandelli, Wainer; Vanguri, Rami; Vaniachine, Alexandre; Vankov, Peter; Vannucci, Francois; Vardanyan, Gagik; Vari, Riccardo; Varnes, Erich; Varol, Tulin; Varouchas, Dimitris; Vartapetian, Armen; Varvell, Kevin; Vazeille, Francois; Vazquez Schroeder, Tamara; Veatch, Jason; Veloso, Filipe; Veneziano, Stefano; Ventura, Andrea; Ventura, Daniel; Venturi, Manuela; Venturi, Nicola; Venturini, Alessio; Vercesi, Valerio; Verducci, Monica; Verkerke, Wouter; Vermeulen, Jos; Vest, Anja; Vetterli, Michel; Viazlo, Oleksandr; Vichou, Irene; Vickey, Trevor; Vickey Boeriu, Oana Elena; Viehhauser, Georg; Viel, Simon; Vigne, Ralph; Villa, Mauro; Villaplana Perez, Miguel; Vilucchi, Elisabetta; Vincter, Manuella; Vinogradov, Vladimir; Virzi, Joseph; Vivarelli, Iacopo; Vives Vaque, Francesc; Vlachos, Sotirios; Vladoiu, Dan; Vlasak, Michal; Vogel, Adrian; Vogel, Marcelo; Vokac, Petr; Volpi, Guido; Volpi, Matteo; von der Schmitt, Hans; von Radziewski, Holger; von Toerne, Eckhard; Vorobel, Vit; Vorobev, Konstantin; Vos, Marcel; Voss, Rudiger; Vossebeld, Joost; Vranjes, Nenad; Vranjes Milosavljevic, Marija; Vrba, Vaclav; Vreeswijk, Marcel; Vu Anh, Tuan; Vuillermet, Raphael; Vukotic, Ilija; Vykydal, Zdenek; Wagner, Peter; Wagner, Wolfgang; Wahlberg, Hernan; Wahrmund, Sebastian; Wakabayashi, Jun; Walder, James; Walker, Rodney; Walkowiak, Wolfgang; Wall, Richard; Waller, Peter; Walsh, Brian; Wang, Chao; Wang, Chiho; Wang, Fuquan; Wang, Haichen; Wang, Hulin; Wang, Jike; Wang, Jin; Wang, Kuhan; Wang, Rui; Wang, Song-Ming; Wang, Tan; Wang, Xiaoxiao; Wanotayaroj, Chaowaroj; Warburton, Andreas; Ward, Patricia; Wardrope, David Robert; Warsinsky, Markus; Washbrook, Andrew; Wasicki, Christoph; Watkins, Peter; Watson, Alan; Watson, Ian; Watson, Miriam; Watts, Gordon; Watts, Stephen; Waugh, Ben; Webb, Samuel; Weber, Michele; Weber, Stefan Wolf; Webster, Jordan S; Weidberg, Anthony; Weigell, Philipp; Weinert, Benjamin; Weingarten, Jens; Weiser, Christian; Weits, Hartger; Wells, Phillippa; Wenaus, Torre; Wendland, Dennis; Weng, Zhili; Wengler, Thorsten; Wenig, Siegfried; Wermes, Norbert; Werner, Matthias; Werner, Per; Wessels, Martin; Wetter, Jeffrey; Whalen, Kathleen; White, Andrew; White, Martin; White, Ryan; White, Sebastian; Whiteson, Daniel; Wicke, Daniel; Wickens, Fred; Wiedenmann, Werner; Wielers, Monika; Wienemann, Peter; Wiglesworth, Craig; Wiik-Fuchs, Liv Antje Mari; Wijeratne, Peter Alexander; Wildauer, Andreas; Wildt, Martin Andre; Wilkens, Henric George; Will, Jonas Zacharias; Williams, Hugh; Williams, Sarah; Willis, Christopher; Willocq, Stephane; Wilson, Alan; Wilson, John; Wingerter-Seez, Isabelle; Winklmeier, Frank; Winter, Benedict Tobias; Wittgen, Matthias; Wittig, Tobias; Wittkowski, Josephine; Wollstadt, Simon Jakob; Wolter, Marcin Wladyslaw; Wolters, Helmut; Wosiek, Barbara; Wotschack, Jorg; Woudstra, Martin; Wozniak, Krzysztof; Wright, Michael; Wu, Mengqing; Wu, Sau Lan; Wu, Xin; Wu, Yusheng; Wulf, Evan; Wyatt, Terry Richard; Wynne, Benjamin; Xella, Stefania; Xiao, Meng; Xu, Da; Xu, Lailin; Yabsley, Bruce; Yacoob, Sahal; Yamada, Miho; Yamaguchi, Hiroshi; Yamaguchi, Yohei; Yamamoto, Akira; Yamamoto, Kyoko; Yamamoto, Shimpei; Yamamura, Taiki; Yamanaka, Takashi; Yamauchi, Katsuya; Yamazaki, Yuji; Yan, Zhen; Yang, Haijun; Yang, Hongtao; Yang, Un-Ki; Yang, Yi; Yanush, Serguei; Yao, Liwen; Yao, Weiming; Yasu, Yoshiji; Yatsenko, Elena; Yau Wong, Kaven Henry; Ye, Jingbo; Ye, Shuwei; Yen, Andy L; Yildirim, Eda; Yilmaz, Metin; Yoosoofmiya, Reza; Yorita, Kohei; Yoshida, Rikutaro; Yoshihara, Keisuke; Young, Charles; Young, Christopher John; Youssef, Saul; Yu, David Ren-Hwa; Yu, Jaehoon; Yu, Jiaming; Yu, Jie; Yuan, Li; Yurkewicz, Adam; Yusuff, Imran; Zabinski, Bartlomiej; Zaidan, Remi; Zaitsev, Alexander; Zaman, Aungshuman; Zambito, Stefano; Zanello, Lucia; Zanzi, Daniele; Zeitnitz, Christian; Zeman, Martin; Zemla, Andrzej; Zengel, Keith; Zenin, Oleg; Ženiš, Tibor; Zerwas, Dirk; Zevi della Porta, Giovanni; Zhang, Dongliang; Zhang, Fangzhou; Zhang, Huaqiao; Zhang, Jinlong; Zhang, Lei; Zhang, Xueyao; Zhang, Zhiqing; Zhao, Zhengguo; Zhemchugov, Alexey; Zhong, Jiahang; Zhou, Bing; Zhou, Lei; Zhou, Ning; Zhu, Cheng Guang; Zhu, Hongbo; Zhu, Junjie; Zhu, Yingchun; Zhuang, Xuai; Zhukov, Konstantin; Zibell, Andre; Zieminska, Daria; Zimine, Nikolai; Zimmermann, Christoph; Zimmermann, Robert; Zimmermann, Simone; Zimmermann, Stephanie; Zinonos, Zinonas; Ziolkowski, Michael; Zobernig, Georg; Zoccoli, Antonio; zur Nedden, Martin; Zurzolo, Giovanni; Zutshi, Vishnu; Zwalinski, Lukasz

    2014-09-15

    A novel technique to identify and split clusters created by multiple charged particles in the ATLAS pixel detector using a set of artificial neural networks is presented. Such merged clusters are a common feature of tracks originating from highly energetic objects, such as jets. Neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. This technique replaces the former clustering approach based on a connected component analysis and charge interpolation. The performance of the neural network splitting technique is quantified using data from proton-proton collisions at the LHC collected by the ATLAS detector in 2011 and from Monte Carlo simulations. This technique reduces the number of clusters shared between tracks in highly energetic jets by up to a factor of three. It also provides more precise position and error estimates of the clusters in both the transverse and longitudinal impact parameter resolution.

  3. A Neural-Network Clusterisation Algorithm for the ATLAS Silicon Pixel Detector

    CERN Document Server

    Leney, KJC; The ATLAS collaboration

    2014-01-01

    A novel technique using a set of artificial neural networks to identify and split merged measurements created by multiple charged particles in the ATLAS pixel detector is presented. Such merged measurements are a common feature of boosted physics objects such as tau leptons or strongly energetic jets where particles are highly collimated. The neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. The performance of the splitting technique is quantified using LHC data collected by the ATLAS detector and Monte Carlo simulation. The number of shared hits per track is significantly reduced, particularly in boosted systems, which increases the reconstruction efficiency and quality. The improved position and error estimates of the measurements lead to a sizable improvement of the track and vertex resolution.

  4. A Neural-Network Clusterisation Algorithm for the ATLAS Silicon Pixel Detector

    CERN Document Server

    Leney, KJC; The ATLAS collaboration

    2013-01-01

    We present a novel technique using a set of artificial neural networks to identify and split merged measurements created by multiple charged particles in the ATLAS pixel detector. Such merged measurements are a common feature of boosted physics objects such as tau leptons or strongly energetic jets where particles get highly collimated. The neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. The performance of the splitting technique is quantified using LHC data collected by the ATLAS detector in 2011 and Monte Carlo simulation. The number of shared hits per track is significantly reduced, particularly in boosted systems, which increases the reconstruction efficiency and quality. The improved position and error estimates of the measurements lead to a sizable improvement of the track and vertex resolution.

  5. Performance of Irradiated Thin Edgeless N-on-P Planar Pixel Sensors for ATLAS Upgrades

    CERN Document Server

    AUTHOR|(CDS)2081098; Boscardin, M; Bosisio, L; Calderini, G; Chauveau, J; Giacomini, G; La Rosa, A; Marchori, G; Zorzi, N

    2013-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, a complete overview of the electrical characterization of several irradiated samples will be discussed. Some comments about detector modules being assembled will be made and eventually some plans will be outlined.

  6. Electrical Characterization of a Thin Edgeless N-on-p Planar Pixel Sensors For ATLAS Upgrades

    CERN Document Server

    Bomben, M; Boscardin, M; Bosisio, L; Calderini, G; Chauveau, J; Giacomini, G; La Rosa, A; Marchori, G; Zorzi, N

    2013-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulation results, a complete overview of the electrical characterization of the produced devices will be given.

  7. Electrical characterization of thin edgeless N-on-p planar pixel sensors for ATLAS upgrades

    CERN Document Server

    Bomben, M

    2014-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulation results, a complete overview of the electrical characterization of the produced devices will be given.

  8. Design, production, and reliability of the new ATLAS pixel opto-boards

    Science.gov (United States)

    Gan, K. K.; Buchholz, P.; Che, S.; Ishmukhametov, R.; Kagan, H. P.; Kass, R. D.; Looper, K.; Moore, J. R.; Moss, J.; Smith, D. S.; Yang, Y.; Ziolkowski, M.

    2015-02-01

    New fiber optical transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed in the ATLAS pixel detector and for the new pixel layer, the insertable barrel layer (IBL). Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver and driver ASICs. The new opto-board design benefits from the production and operational experience of the first generation opto-boards and contains several improvements. The new opto-boards have been successfully installed. Additionally, a set of the new opto-boards have been subjected to an accelerated lifetime experiment at 85 C and 85% relative humidity for over 1,000 hours. No failures were observed. We are cautiously optimistic that the new opto-boards will survive until the shutdown for the detector upgrade for the high-luminosity Large Hadron Collider (HL-LHC).

  9. The phase-II ATLAS pixel tracker upgrade: layout and mechanics.

    CERN Document Server

    Sharma, Abhishek; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment will upgrade its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The upgraded tracker will consist of silicon-strip modules surrounding a pixel detector, and will likely cover an extended eta range, perhaps as far as |eta|<4.0. A number of layout and supporting-structure options are being considered for the pixel detector, with the final choice expected to be made in early 2017. The proposed supporting structures are based on lightweight, highly-thermally-conductive carbon-based materials and are cooled by evaporative carbon dioxide. The various layouts will be described and a description of the supporting structures will be presented, along with results from testing of prototypes.

  10. Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

    CERN Document Server

    Savic, Natascha

    2016-01-01

    In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023-2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more ra- diation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 {\\mu}m recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of th...

  11. Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Wittig, Tobias

    2013-05-08

    One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

  12. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    CERN Document Server

    Boek, J; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2013-01-01

    inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University ofWuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

  13. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  14. The off-detector opto-electronics for the optical links of the ATLAS Semiconductor Tracker and Pixel detector

    CERN Document Server

    Chu, M L; Su, D S; Teng, P K; Goodrick, M; Kundu, N; Weidberg, T; French, M; MacWaters, C P; Matheson, J

    2004-01-01

    The off-detector part of the optical links for the ATLAS SCT and Pixel detectors is described. The VCSELs and p-i-n diodes used and the associated ASICs are described. A novel array packaging technique is explained and an analysis of the performance of the arrays and the overall system performance is given. The proposed procedure for the set-up of the optical links in ATLAS is described.

  15. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  16. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    INSPIRE-00399968

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  17. Front-end electronics for the Muon Portal project

    Energy Technology Data Exchange (ETDEWEB)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M.C. [INAF, Osservatorio Astrofisico di Catania, Via S. Sofia 78, I-95123 Catania (Italy); Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D.G. [Università di Catania, Dipartimento di Fisica e Astronomia, and INFN, Sezione di Catania, Via S. Sofia 64, I-95123 Catania (Italy); Fallica, G.; Valvo, G. [ST-Microelectronics, Stradale V Primosole 50, Catania (Italy)

    2016-10-11

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  18. The LHCb front-end electronics and data acquisition system

    CERN Document Server

    Jost, B

    2000-01-01

    The LHCb experiment is the most recently approved of the four experiments under construction at CERN's LHC accelerator. It is a special purpose experiment designed to precisely measure the CP violation parameters in the B-B system and to study rare B-decays. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. We therefore decided to implement a four-level triggering scheme. The LHCb data acquisition (DAQ) system will have to cope with an average trigger rate of 40 kHz, after two levels of hardware triggers, and an average event size of 100 kB. Thus, an event-building network which can sustain an average bandwidth of 4 GB /s is required. A powerful software trigger farm will have to be installed to reduce the rate from 40 kHz to 100 Hz of events written for permanent storage. In this paper we will outline the general architectures of the front-end electronics and of the trigger and DAQ system and the readout protocols...

  19. Broadband beamforming compensation algorithm in CI front-end acquisition.

    Science.gov (United States)

    Chen, Yousheng; Gong, Qin

    2013-02-27

    To increase the signal to noise ratio (SNR) and to suppress directional noise in front-end signal acquisition, microphone array technologies are being applied in the cochlear implant (CI). Due to size constraints, the dual microphone-based system is most suitable for actual application. However, direct application of the array technology will result in the low frequency roll-off problem, which can noticeably distort the desired signal. In this paper, we theoretically analyze the roll-off characteristic on the basis of CI parameters and present a new low-complexity compensation algorithm. We obtain the linearized frequency response of the two-microphone array from modeling and analysis for further algorithm realization. REALIZATION AND RESULTS: Linear method was used to approximate the theoretical response with adjustable delay and weight parameters. A CI dual-channel hardware platform is constructed for experimental research. Experimental results show that our algorithm performs well in compensation and realization. We discuss the effect from environment noise. Actual daily noise with more low-frequency energy will weaken the algorithm performance. A balance between low-frequency distortion and corresponding low-frequency noise need to be considered. Our novel compensation algorithm uses linear function to obtain the desired system response, which is a low computational-complexity method for CI real-time processing. Algorithm performance is tested in CI CIS modulation and the influence of experimental distance and environmental noise were further analyzed to evaluate algorithm constraint.

  20. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  1. DESIGN OF MEDICAL RADIOMETER FRONT-END FOR IMPROVED PERFORMANCE.

    Science.gov (United States)

    Klemetsen, O; Birkelund, Y; Jacobsen, S K; Maccarini, P F; Stauffer, P R

    2011-01-01

    We have investigated the possibility of building a singleband Dicke radiometer that is inexpensive, small-sized, stable, highly sensitive, and which consists of readily available microwave components. The selected frequency band is at 3.25-3.75 GHz which provides a reasonable compromise between spatial resolution (antenna size) and sensing depth for radiometry applications in lossy tissue. Foreseen applications of the instrument are non-invasive temperature monitoring for breast cancer detection and temperature monitoring during heating. We have found off-the-shelf microwave components that are sufficiently small (water baths. Experiments showed superior sensitivity (36% higher) when implementing the low noise amplifier before the Dicke switch (close to the antenna) compared to the other design with the Dicke switch in front. Radiometer performance was also tested in a multilayered phantom during alternating heating and radiometric reading. Empirical tests showed that for the configuration with Dicke switch first, the switch had to be locked in the reference position during application of microwave heating to avoid damage to the active components (amplifiers and power meter). For the configuration with a low noise amplifier up front, damage would occur to the active components of the radiometer if used in presence of the microwave heating antenna. Nevertheless, this design showed significantly improved sensitivity of measured temperatures and merits further investigation to determine methods of protecting the radiometer for amplifier first front ends.

  2. Front-end electronics and trigger systems - status and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-08-21

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described.

  3. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  4. A high performance SAR ADC for WLAN analog front end

    Science.gov (United States)

    Lian, Pengfei; Yi, Bo; Wu, Bin; Wang, Han; Pu, Yilin

    2017-08-01

    A 10 bit 100 MS/s successive approximation register (SAR) analog to digital converter (ADC) for WLAN analog front end is presented. To ensure high performance and low power, we presented a method that is based on figure of merit (FOM) to obtain the optimal unit capacitance of the digital-to-analog converter (DAC) capacitor network. With this method, we obtain the minimum FOM 17.92 fJ/Conv.-step as well as the optimal unit capacitance of the DAC capacitor network 1.59 fF. What is more, to ensure high performance of the dynamic comparator, a comparator clock logic is presented. Post-simulation results in 55 nm CMOS technology show that, this 10-bit 100-MS/s ADC achieves the signal-to-noise-and-distortion ratio (SNDR), the signal-to-noise ratio (SNR) and the spurious-free dynamic range (SFDR) of 61.7 dB, 63.7 dB and 72.5 dB with 1.3V supply. The ADC consumes 1.67 mW, and the active area is only 0.0162 mm2.

  5. Digital Front End for Wide-Band VLBI Science Receiver

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Navarro, Robert; Goodhart, Charles; Rogstad, Steve; Chandra, Kumar; Finley, Sue; Trinh, Joseph; Soriano, Melissa; White, Les; hide

    2006-01-01

    An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

  6. The front-end systems for the Spallation Neutron Source

    CERN Document Server

    Keller, R

    2001-01-01

    The front-end systems (FES) of the Spallation Neutron Source (SNS) project are being built by Berkeley Lab and will deliver a 52-mA H /sup -/ ion beam at 2.5 MeV energy to the subsequent drift-tube linac, to be built by Los Alamos National Laboratory. The FES comprise a volume-production, cesium-enhanced ion source, an electrostatic low-energy beam transport (LEBT), an RFQ accelerator, and a medium-energy beam transport (MEBT) that includes rebuncher cavities, magnetic quadrupoles, and beam diagnostics. The macro-pulse duty factor is 6%, and the macro pulses have to be chopped into a minipulse structure with a time scale of hundreds of ns, to reduce beam losses and component activation during extraction from the SNS Accumulator Ring. Delivery of the entire FES to the main SNS facility in Oak Ridge is planned for April 2002. This paper discusses the design features and status of the major FES subsystems with special emphasis on ion source and LEBT for which first experimental results have been obtained. After ...

  7. First MCM-D modules for the b-physics layer of the ATLAS Pixel Detector

    CERN Document Server

    Basken, O; Ehrmann, O; Gerlach, P; Grah, C; Gregor, I M; Linder, C; Meuser, S; Richardson, J; Topper, M; Wolf, J

    2000-01-01

    The innermost layer (b-physics layer) of the ATLAS Pixel Detector will consist of modules based on MCM-D technology. Such a module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out ICs, each serving 24* 160 pixel unit cells, a module controller chip (MCC), an optical transceiver and the local signal interconnection and power distribution busses. We show a prototype of such a module with additional test pads on both sides. The outer dimensions of the final module will be 21.4 mm*67.8 mm. The extremely high wiring density, which is necessary to interconnect the read-out chips, was achieved using a thin film copper/photo-BCB process on the pixel array. The bumping of the read out chips was done using electroplating PbSn. All dice are then attached by flip-chip assembly to the sensor diodes and the local busses. The focus of this paper is the description of the first results of such MCM-D-type modules. (11 refs).

  8. System test and noise performance studies at the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Weingarten, J.

    2007-09-15

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  9. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture simp...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  10. Silvaco ATLAS model of ESA's Gaia satellite e2v CCD91-72 pixels

    Science.gov (United States)

    Seabroke, George; Holland, Andrew; Burt, David; Robbins, Mark

    2010-07-01

    The Gaia satellite is a high-precision astrometry, photometry and spectroscopic ESA cornerstone mission, currently scheduled for launch in 2012. Its primary science drivers are the composition, formation and evolution of the Galaxy. Gaia will achieve its unprecedented accuracy requirements with detailed calibration and correction for CCD radiation damage and CCD geometric distortion. In this paper, the third of the series, we present our 3D Silvaco ATLAS model of the Gaia e2v CCD91-72 pixel. We publish e2v's design model predictions for the capacities of one of Gaia's pixel features, the supplementary buried channel (SBC), for the first time. Kohley et al. (2009) measured the SBC capacities of a Gaia CCD to be an order of magnitude smaller than e2v's design. We have found the SBC doping widths that yield these measured SBC capacities. The widths are systematically 2 μm offset to the nominal widths. These offsets appear to be uncalibrated systematic offsets in e2v photolithography, which could either be due to systematic stitch alignment offsets or lateral ABD shield doping diffusion. The range of SBC capacities were used to derive the worst-case random stitch error between two pixel features within a stitch block to be +/-0.25 μm, which cannot explain the systematic offsets. It is beyond the scope of our pixel model to provide the manufacturing reason for the range of SBC capacities, so it does not allow us to predict how representative the tested CCD is. This open question has implications for Gaia's radiation damage and geometric calibration models.

  11. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  12. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  13. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation.

    CERN Document Server

    Lantzsch, K; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  14. Beam Test Studies of 3D Pixel Sensors Irradiated Non-Uniformly for the ATLAS Forward Physics Detector

    CERN Document Server

    Grinstein, S; Boscardin, M; Christophersen, M; Da Via, C; Betta, G -F Dalla; Darbo, G; Fadeyev, V; Fleta, C; Gemme, C; Grenier, P; Jimenez, A; Lopez, I; Micelli, A; Nelist, C; Parker, S; Pellegrini, G; Phlips, B; Pohl, D L; Sadrozinski, H F -W; Sicho, P; Tsiskaridze, S

    2013-01-01

    Pixel detectors with cylindrical electrodes that penetrate the silicon substrate (so called 3D detectors) offer advantages over standard planar sensors in terms of radiation hardness, since the electrode distance is decoupled from the bulk thickness. In recent years significant progress has been made in the development of 3D sensors, which culminated in the sensor production for the ATLAS Insertable B-Layer (IBL) upgrade carried out at CNM (Barcelona, Spain) and FBK (Trento, Italy). Based on this success, the ATLAS Forward Physics (AFP) experiment has selected the 3D pixel sensor technology for the tracking detector. The AFP project presents a new challenge due to the need for a reduced dead area with respect to IBL, and the in-homogeneous nature of the radiation dose distribution in the sensor. Electrical characterization of the first AFP prototypes and beam test studies of 3D pixel devices irradiated non-uniformly are presented in this paper.

  15. Full simulation of a testbeam experiment including modeling of the Bonn Atlas Telescope and Atlas 3D pixel silicon sensors

    CERN Document Server

    Sjøbæk, Kyrre Ness; Rohne, O M; Bolle, E

    2010-01-01

    3D silicon pixel sensors are a strong candidate for the sensor component of a new B-layer in the ATLAS detector, and for the ATLAS sLHC tracker, as these sensors can be highly radiation hard, fast, and sensitive to the edge. In order to characterize the sensors before large-scale application, samples are mounted in small fixed-target testbeam experiments. Here the samples are exposed to high-energy charged hadrons, and the response to this radiation is measured. The hit position in the sensor is estimated using a beam telescope, which measures the position of the particle while in flight up- and downstream of the sample. The hit position is then estimated by assuming that particle flies in a straight line between the telescope measurements and the sample. This thesis presents a full Geant4 simulation of the interaction between the beam particles and the material in the testbeam, including but not limited to sensors. The output from the simulation is then used for detailed modeling of the signal formation and ...

  16. Readout board upgrade for the Pixel Detectors: reasons, status and results in ATLAS

    CERN Document Server

    Giangiacomi, Nico; The ATLAS collaboration

    2017-01-01

    The increase of luminosity in the LHC accelerator at CERN constitutes a challenge for the data readout since the rate of data to be transmitted depends on both pileup and trigger frequency. In the ATLAS experiment, the effect of the increased luminosity is most evident in the Pixel Detector, which is the detector closest to the beam pipe. In order to face the difficult experimental challenges, the readout system was upgraded during the last few years. The main purpose of the upgrade was to provide a higher bandwidth by exploiting more recent technologies. The new readout system is composed by two paired electronic boards named Back Of Crate (BOC) and ReadOut Driver (ROD). In this work the main readout limitation related to increased luminosity will be discussed as well as the strategy and the technological solutions adopted in order to cope with the future operational challenges. In addition the general progresses and achievements will be presented.

  17. Alignment of the Pixel and SCT Modules for the 2004 ATLAS Combined Test Beam

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Ahmad, A.; Andreazza, A.; Atkinson, T.; Baines, J.; Barr, A.J.; Beccherle, R.; Bell, P.J.; Bernabeu, J.; Broklova, Z.; Bruckman de Renstrom, P.A.; Cauz, D.; Chevalier, L.; Chouridou, S.; Citterio, M.; Clark, A.; Cobal, M.; Cornelissen, T.; Correard, S.; Costa, M.J.; Costanzo, D.; Cuneo, S.; Dameri, M.; Darbo, G.; de Vivie, J.B.; Di Girolamo, B.; Dobos, D.; Drasal, Z.; Drohan, J.; Einsweiler, K.; Elsing, M.; Emelyanov, D.; Escobar, C.; Facius, K.; Ferrari, P.; Fergusson, D.; Ferrere, D.; Flick,, T.; Froidevaux, D.; Gagliardi, G.; Gallas, M.; Gallop, B.J.; Gan, K.K.; Garcia, C.; Gavrilenko, I.L.; Gemme, C.; Gerlach, P.; Golling, T.; Gonzalez-Sevilla, S.; Goodrick, M.J.; Gorfine, G.; Gottfert, T.; Grosse-Knetter, J.; Hansen, P.H.; Hara, K.; Hartel, R.; Harvey, A.; Hawkings, R.J.; Heinemann, F.E.W.; Henss, T.; Hill, J.C.; Huegging, F.; Jansen, E.; Joseph, J.; Unel, M. Karagoz; Kataoka, M.; Kersten, S.; Khomich, A.; Klingenberg, R.; Kodys, P.; Koffas, T.; Konstantinidis, N.; Kostyukhin, V.; Lacasta, C.; Lari, T.; Latorre, S.; Lester, C.G.; Liebig, W.; Lipniacka, A.; Lourerio, K.F.; Mangin-Brinet, M.; Marti i Garcia, S.; Mathes, M.; Meroni, C.; Mikulec, B.; Mindur, B.; Moed, S.; Moorhead, G.; Morettini, P.; Moyse, E.W.J.; Nakamura, K.; Nechaeva, P.; Nikolaev, K.; Parodi, F.; Parzhitskiy, S.; Pater, J.; Petti, R.; Phillips, P.W.; Pinto, B.; Poppleton, A.; Reeves, K.; Reisinger, I.; Reznicek, P.; Risso, P.; Robinson, D.; Roe, S.; Rozanov, A.; Salzburger, A.; Sandaker, H.; Santi, L.; Schiavi, C.; Schieck, J.; Schultes, J.; Sfyrla, A.; Shaw, C.; Tegenfeldt, F.; Timmermans, C.J.W.P.; Toczek, B.; Troncon, C.; Tyndel, M.; Vernocchi, F.; Virzi, J.; Anh, T. Vu; Warren, M.; Weber, J.; Weber, M.; Weidberg, A.R.; Weingarten, J.; Wellsf, P.S.; Zhelezkow, A.

    2008-06-02

    A small set of final prototypes of the ATLAS Inner Detector silicon tracking system(Pixel Detector and SemiConductor Tracker), were used to take data during the 2004 Combined Test Beam. Data were collected from runs with beams of different flavour (electrons, pions, muons and photons) with a momentum range of 2 to 180 GeV/c. Four independent methods were used to align the silicon modules. The corrections obtained were validated using the known momenta of the beam particles and were shown to yield consistent results among the different alignment approaches. From the residual distributions, it is concluded that the precision attained in the alignmentof the silicon modules is of the order of 5 mm in their most precise coordinate.

  18. Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector

    CERN Document Server

    Gan, K K; Johnson, M; Kagan, H; Kass, R; Rush, C; Smith, S; Ter-Antonian, R; Zöller, M; Ciliox, A; Holderb, M; Ziolkowski, M

    2006-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 80 Mrad (2.6 x 10^15 p/cm^2).

  19. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    INSPIRE-00083439; Arms, Kregg E.; Johnson, M.; Kagan, H.; Kass, R.; Rush, C.; Smith, S.; Ter-Antonian, R.; Zoeller, M.M.; Ciliox, A.; Holder, M.; Ziolkowski, M.

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 62 Mrad (2.3 x 10^15 p/cm^2).

  20. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Kass, R; Gan, K K; Johnson, M; Kagan, H; Rush, C J; Rahimi, A; Smith, S; Ter-Antonian, R; Zoeller, M M; Ciliox, A; Holder, M; Nderitu, S; Ziolkowski, M

    2003-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 um CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from prototype circuits and from irradiation studies with 24 GeV protons up to 57 Mrad (1.9 x 10e15 p/cm2).

  1. Alignment of the Pixel and SCT Modules for the 2004 ATLAS Combined Test Beam

    Science.gov (United States)

    Ahmad, A.; Andreazza, A.; Atkinson, T.; Baines, J.; Barr, A. J.; Beccherle, R.; Bell, P. J.; Bernabeu, J.; Broklova, Z.; Bruckman de Renstrom, P. A.; Cauz, D.; Chevalier, L.; Chouridou, S.; Citterio, M.; Clark, A.; Cobal, M.; Cornelissen, T.; Correard, S.; Costa, M. J.; Costanzo, D.; Cuneo, S.; Dameri, M.; Darbo, G.; de Vivie, J. B.; Di Girolamo, B.; Dobos, D.; Drasal, Z.; Drohan, J.; Einsweiler, K.; Elsing, M.; Emelyanov, D.; Escobar, C.; Facius, K.; Ferrari, P.; Fergusson, D.; Ferrere, D.; Flick, T.; Froidevaux, D.; Gagliardi, G.; Gallas, M.; Gallop, B. J.; Gan, K. K.; Garcia, C.; Gavrilenko, I. L.; Gemme, C.; Gerlach, P.; Golling, T.; Gonzalez-Sevilla, S.; Goodrick, M. J.; Gorfine, G.; Göttfert, T.; Grosse-Knetter, J.; Hansen, P. H.; Hara, K.; Härtel, R.; Harvey, A.; Hawkings, R. J.; Heinemann, F. E. W.; Henss, T.; Hill, J. C.; Huegging, F.; Jansen, E.; Joseph, J.; Karagöz Ünel, M.; Kataoka, M.; Kersten, S.; Khomich, A.; Klingenberg, R.; Kodys, P.; Koffas, T.; Konstantinidis, N.; Kostyukhin, V.; Lacasta, C.; Lari, T.; Latorre, S.; Lester, C. G.; Liebig, W.; Lipniacka, A.; Lourerio, K. F.; Mangin-Brinet, M.; Garcia, S. Marti i.; Mathes, M.; Meroni, C.; Mikulec, B.; Mindur, B.; Moed, S.; Moorhead, G.; Morettini, P.; Moyse, E. W. J.; Nakamura, K.; Nechaeva, P.; Nikolaev, K.; Parodi, F.; Parzhitskiy, S.; Pater, J.; Petti, R.; Phillips, P. W.; Pinto, B.; Poppleton, A.; Reeves, K.; Reisinger, I.; Reznicek, P.; Risso, P.; Robinson, D.; Roe, S.; Rozanov, A.; Salzburger, A.; Sandaker, H.; Santi, L.; Schiavi, C.; Schieck, J.; Schultes, J.; Sfyrla, A.; Shaw, C.; Tegenfeldt, F.; Timmermans, C. J. W. P.; Toczek, B.; Troncon, C.; Tyndel, M.; Vernocchi, F.; Virzi, J.; Anh, T. Vu; Warren, M.; Weber, J.; Weber, M.; Weidberg, A. R.; Weingarten, J.; Wells, P. S.; Zhelezko, A.

    2008-09-01

    A small set of final prototypes of the ATLAS Inner Detector silicon tracking system (Pixel Detector and SemiConductor Tracker), were used to take data during the 2004 Combined Test Beam. Data were collected from runs with beams of different flavour (electrons, pions, muons and photons) with a momentum range of 2 to 180 GeV/c. Four independent methods were used to align the silicon modules. The corrections obtained were validated using the known momenta of the beam particles and were shown to yield consistent results among the different alignment approaches. From the residual distributions, it is concluded that the precision attained in the alignment of the silicon modules is of the order of 5 μm in their most precise coordinate.

  2. Experience in fabrication of multichip-modules for the ATLAS pixel detector

    Science.gov (United States)

    Fritzsch, T.; Jordan, R.; Töpper, M.; Röder, J.; Kuna, I.; Lutz, M.; Defo Kamga, F.; Wolf, J.; Ehrmann, O.; Oppermann, H.; Reichl, H.

    2006-09-01

    About 1100 ATLAS bare modules will be assembled at Fraunhofer IZM. The bumping and assembly technology of these multichip-modules is described in this paper. Pixel contacts and lead-tin interconnection bumps are deposited by electroplating. A high yield manufacturing technology requires electrical test and optical inspection on wafer level as well as on chip level. In this paper, the result of optical inspection of more than 7600 readout chips is presented. Handling mistakes are the main reason for rejection of chips before flip chip assembly. A reliable process technology, the assembly of electrical Known Good Die (KGD), optical inspection after bumping and the development of a single chip repair technology result in 98% of good modules after flip chip assembly. The reliability of the bump interconnections was even checked by thermal cycling and accelerated thermal aging.

  3. Development of edgeless n-on-p planar pixel sensors for future ATLAS upgrades

    Energy Technology Data Exchange (ETDEWEB)

    Bomben, Marco, E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Bagolini, Alvise; Boscardin, Maurizio [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, Luciano [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, and INFN Sez. di Pisa, Pisa (Italy); Chauveau, Jacques [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Giacomini, Gabriele [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, Alessandro [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Zorzi, Nicola [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

    2013-06-01

    The development of n-on-p “edgeless” planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the “active edge” technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of 1×10{sup 15}n{sub eq}/cm{sup 2} comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb{sup −1}) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach. -- Highlights: ► We conceive n-on-p edgeless planar silicon sensors. ► These sensors are aimed at the Phase-II of the ATLAS experiment. ► Simulations show sensors can be operated well in overdepletion. ► Simulations show the sensor capability to collect charge at the periphery. ► Simulations prove the above statements to be true even after irradiation.

  4. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  5. Characterization of silicon 3D pixel detectors for the ATLAS Forward Physics experiment

    Energy Technology Data Exchange (ETDEWEB)

    Lopez Paz, I.; Cavallaro, E.; Lange, J. [Institut de Fisica d' Altes Energies - IFAE, 08193 Bellaterra, Barcelona (Spain); Grinstein, S. [Institut de Fisica d' Altes Energies - IFAE, 08193 Bellaterra, Barcelona (Spain); Catalan Institution for Research and Advanced Studies - ICREA, Barcelona (Spain)

    2015-07-01

    The ATLAS Forward Physics (AFP) project aims to measure protons scattered under a small angle from the pp collisions in ATLAS. In order to perform such measurements, a new silicon tracker, together with a time-of-flight detector for pile-up removal, are planned to be installed at ∼210 m from the interaction point and at 2-3 mm from the LHC proton beam. To cope with such configuration and maximize the physics outcome, the tracker has to fulfil three main requirements: endure highly non-uniform radiation doses, due to the very inhomogeneous beam profile, have slim and efficient edges to improve the acceptance of the tracker, and provide good position resolution. Recent laboratory and beam test characterization results of AFP prototypes will be presented. Slim-edged 3D pixel detectors down to 100-200 μm were studied and later non-uniformly irradiated (with a peak fluence of several 10{sup 15} n{sub eq}/cm{sup 2}) to determine the fulfilment of the AFP requirements. (authors)

  6. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  7. Characterization and Performance of Silicon n-in-p Pixel Detectors for the ATLAS Upgrades

    CERN Document Server

    Weigell, Philipp; Gallrapp, Christian; La Rosa, Alessandro; Macchiolo, Anna; Nisius, Richard; Pernegger, Heinz; Richter, Rainer

    2011-01-01

    The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities (super LHC) the development of new structures and materials which can cope with the resulting particle fluences is needed. N-in-p silicon devices are a promising candidate for tracking detectors to achieve these goals, since they are radiation hard, cost efficient and are not type inverted after irradiation. A n-in-p pixel production based on a MPP/HLL design and performed by CiS (Erfurt, Germany) on 300 \\mu m thick Float-Zone material is characterised and the electrical properties of sensors and single chip modules (SCM) are presented, including noise, charge collection efficiencies, and measurements with MIPs as well as an 241Am source. The SCMs are built with sensors connected to the current the ATLAS read-out chip FE-I3. The characterisation has been performed with the ATL...

  8. Upgrade Design of TileCal Front-end Readout Electronics and Radiation Hardness Studies

    CERN Document Server

    Anderson, K; The ATLAS collaboration; Drake, G; Eriksson, D; Muschter, S; Oreglia, M; Pilcher, J; Price, L; Tang, F

    2011-01-01

    The ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of hadrons and taus produced in LHC collisions. The TileCal consists of "tiles" of plastic scintillator dispersed in a fine-grained steel matrix . Optical fibers from the tiles are sent to ~10,000 photomultiplier tubes (PMT) and associated readout electronics. The TileCal front-end analog readout electronics process the signals from ~10,000 PMTs. Signals from each PMT are shaped with a 7-pole passive LC shaper and split it to two channels amplified by a pair of clamping amplifiers with a gain ratio of 32. Incorporated with two 40Msps 12-bit ADCs, the readout electronics provide a combined dynamic range of 17-bits. With this dynamic range, the readout system is capable of measuring the energy deposition in the calorimeter cells from ~220MeV to 1.3TeV with the least signal-to-noise ratio of greater than 20. The digitized data from each PMT are transmitted off-detector optically, where the data are further processed with ded...

  9. Simulation of the depletion voltage evolution of the ATLAS Pixel Detector

    CERN Document Server

    Beyer, Julien-christopher; The ATLAS collaboration

    2017-01-01

    The ATLAS Pixel detector has been operating since 2010 and consists of hybrid pixel modules where the sensitive elements are planar n-in-n sensors. In order to investigate and predict the evolution of the depletion voltage and of the leakage current in the different layers, a fully analytical implementation of the Hamburg model was derived. The parameters of the model, describing the dependence of the depletion voltage (U_depl) on fluence, temperature and time were tuned with a fit to the available measurements of Udepl in the last years of operation. A particular emphasis is put on the B-Layer, where the highest fluence has been accumulated up to now. A precise input of temperature and radiation dose is generated from the on-module temperature monitoring and the luminosity data. The analysis is then also extended to the Insertable B-Layer (IBL), installed at the end of Run-1, where we expect the fastest evolution of the radiation damage with luminosity, due to its closer position to the interaction point. Di...

  10. Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

    The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

  11. Development of Edgeless n-on-p Planar Pixel Sensors for future ATLAS Upgrades

    CERN Document Server

    Bomben, M

    2013-01-01

    The development of n-on-p “edgeless” planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the “active edge” technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of View the MathML source1×1015neq/cm2 comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb−1) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity...

  12. YARR - A PCIe based Readout Concept for Current and Future ATLAS Pixel Modules

    Science.gov (United States)

    Heim, Timon

    2017-10-01

    The Yet Another Rapid Readout (YARR) system is a DAQ system designed for the readout of current generation ATLAS Pixel FE-I4 and next generation chips. It utilises a commercial-off-the-shelf PCIe FPGA card as a reconfigurable I/O interface, which acts as a simple gateway to pipe all data from the Pixel modules via the high speed PCIe connection into the host system’s memory. Relying on modern CPU architectures, which enables the usage of parallelised processing in threads and commercial high speed interfaces in everyday computers, it is possible to perform all processing on a software level in the host CPU. Although FPGAs are very powerful at parallel signal processing their firmware is hard to maintain and constrained by their connected hardware. Software, on the other hand, is very portable and upgraded frequently with new features coming at no cost. A DAQ concept which does not rely on the underlying hardware for acceleration also eases the transition from prototyping in the laboratory to the full scale implementation in the experiment. The overall concept and data flow will be outlined, as well as the challenges and possible bottlenecks which can be encountered when moving the processing from hardware to software.

  13. Development of Edgeless n-on-p Planar Pixel Sensors for future ATLAS Upgrades

    CERN Document Server

    INSPIRE-00052711; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchori, G.; Zorzi, N.

    2013-01-01

    The development of n-on-p "edgeless" planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the "active edge" technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of $1 \\times 10^{15} {\\rm n_{eq}}/{\\rm cm}^2$ comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb$^{-1}$) for the outer pixel layers. We show that, after irradiation, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach.

  14. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    Abstract. Final results on a CMOS 0.18 µm front-end chip for silicon strips readout are summarized and ... In any detector concept foreseen at the ILC, a front-end readout system for tracking silicon detectors has to ... signal processing techniques such as analog sampling and on-chip digitization. For detectors that covers of ...

  15. PHYSICS RESULTS OF THE NSLS-II LINAC FRONT END TEST STAND

    Energy Technology Data Exchange (ETDEWEB)

    Fliller R. P.; Gao, F.; Yang, X.; Rose, J.; Shaftan, T.; Piel, C

    2012-05-20

    The Linac Front End Test Stand (LFETS) was installed at the Source Development Laboratory (SDL) in the fall of 2011 in order to test the Linac Front End. The goal of these tests was to test the electron source against the specifications of the linac. In this report, we discuss the results of these measurements and the effect on linac performance.

  16. Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

    1994-01-01

    In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range...

  17. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  18. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  19. ATLAS-TPX: a two-layer pixel detector setup for neutron detection and radiation field characterization

    Science.gov (United States)

    Bergmann, B.; Caicedo, I.; Leroy, C.; Pospisil, S.; Vykydal, Z.

    2016-10-01

    A two-layer pixel detector setup (ATLAS-TPX), designed for thermal and fast neutron detection and radiation field characterization is presented. It consists of two segmented silicon detectors (256 × 256 pixels, pixel pitch 55 μm, thicknesses 300 μm and 500 μm) facing each other. To enhance the neutron detection efficiency a set of converter layers is inserted in between these detectors. The pixelation and the two-layer design allow a discrimination of neutrons against γs by pattern recognition and against charged particles by using the coincidence and anticoincidence information. The neutron conversion and detection efficiencies are measured in a thermal neutron field and fast neutron fields with energies up to 600 MeV. A Geant4 simulation model is presented, which is validated against the measured detector responses. The reliability of the coincidence and anticoincidence technique is demonstrated and possible applications of the detector setup are briefly outlined.

  20. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider -- Plot Approval (Pixel, IBL) : This is a submission of plot approval request for Pixel+IBL, facing on a talk at ICHEP 2014 conference

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  1. A novel high input impedance front-end for capacitive biopotential measurement.

    Science.gov (United States)

    Wu, Rongrong; Tang, Yue; Li, Zhiyu; Zhang, Limin; Yan, Feng

    2018-01-08

    For capacitive biopotential measurement, a novel high input impedance front-end is proposed. The input impedance of the front-end can achieve more than 100 GΩ by matching the peripheral parameters. The front-end's noise model is provided, and noise optimization is given further. The analysis shows the proposed front-end can achieve at least two orders of input impedance more than the non-inverting amplifier circuit with the same peripheral parameters at the cost of only increasing twice input-referred noise. The final experimental results verify the analysis and show the front-end's feasibility of capacitive sensing electrocardiogram signal. Graphical abstract A novel high input impedance front-end is proposed, which impedance can achieve more than 100 GΩ by matching the peripheral parameters. The analysis and noise optimization results show the proposed front-end can achieve at least two orders of input impedance more than the non-inverting amplifier circuit with the same peripheral parameters at the cost of only increasing twice input-referred noise. The final experimental results verify the analysis and show its feasibility of capacitive sensing electrocardiogram signal.

  2. Programmer's guide to FFE: a fast front-end data-acquisition program

    Energy Technology Data Exchange (ETDEWEB)

    Million, D.L.

    1983-05-01

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system.

  3. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...

  4. Analog front-end electronics for the outer layers of the SuperB SVT: Design and expected performances

    Science.gov (United States)

    Bombelli, Luca; Fiorini, Carlo; Nasri, Bayan; Trigilio, Paolo; Citterio, Mauro; Neri, Nicola

    2013-08-01

    The Silicon Vertex Tracker (SVT) of the new SuperB collider will be composed of 6 different detector layers [1]. The innermost layer (L0) will be composed by striplets or pixels [2]; the other 5 detector layers will be double-sided long-strip detectors. The strip geometries and the foreseen hit-rates will change according to the different layers. As a consequence, different optimization of the analog read-out electronics is needed in order to provide high detection-efficiency and low noise level in the different layers. Two readout ASICs are currently developed, one for layers 0-3, another for layers 4 and 5; they differ mainly in the analog front-end. In this work, we present the design and the expected performances of the analog front-end for layers 4 and 5. For these layers, the strip detectors show a very high stray capacitance and high series resistance. In this condition, the noise optimization is our primary concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been found. We will present the design of preamplifier and shaper and the results of simulation of noise performance and efficiency (with the expected background rates). In addition, the design of the time-over-threshold and its use to correct the time-walk of the event trigger is discussed as well as the achievable timing accuracy of the circuit.

  5. Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

    Science.gov (United States)

    Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

    2017-12-01

    Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

  6. Depleted fully monolithic CMOS pixel detectors using acolumn based readout architecture for the ATLAS InnerTracker upgrade

    CERN Document Server

    Wang, Tianyang; Berdalovic, Ivan; Bespin, Christian; Bhat, Siddharth; Breugnon, Patrick; Caicedo, Ivan; Cardella, Roberto; Chen, Zongde; Degerli, Yavuz; Egidos, Nuria; Godiot, Stéphanie; Guilloux, Fabrice; Hemperek, Tomasz; Hirono, Toko; Krüger, Hans; Kugathasan, Thanushan; Hügging, Fabian; Marin Tobon, Cesar Augusto; Moustakas, Konstantinos; Pangaud, Patrick; Schwemling, Philippe; Pernegger, Heinz; Pohl, David-Leon; Rozanov, Alexandre; Rymaszewski, Piotr; Snoeys, Walter; Wermes, Norbert

    2017-01-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/orhigh resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sens-ing volume, have proven to have high radiation tolerance towards the requirements of ATLAS inthe high-luminosity LHC era. Depleted fully monolithic CMOS pixels with fast readout architec-tures are currently being developed as promising candidates for the outer pixel layers of the futureATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year2025. In this work, two DMAPS prototype designs, named LF-MonoPix and TJ-MonoPix, arepresented. LF-MonoPix was designed and fabricated in the LFoundry 150 nm CMOS technology,and TJ-MonoPix has been designed in the TowerJazz 180 nm CMOS technology. Both chipsemploy the same readout architecture, i.e. the column drain architecture, whereas different sensorimplementation concepts are pursued. The design of the two prototypes will be described. Firstmeasurement ...

  7. Readout board upgrade for the Pixel Detectors: reasons, status and results in ATLAS

    CERN Document Server

    Giangiacomi, Nico; The ATLAS collaboration

    2017-01-01

    At LHC the design luminosity, 1034 cm -2 s -1 , has already been reached during Summer 2016. LHC is planning, in the short term future, to further enhance the luminosity, resulting in a higher trigger frequency and an increased pileup. These factors constitute a challenge for the data readout since the rate of data to be transmitted depends on both pileup and trigger frequency. In the ATLAS experiment, the effect of the increased luminosity is most evident in the Pixel Detector, which is the detector closest to the beam pipe. In order to face the difficult experimental challenges, the readout system was upgraded during the last few years. The main purpose of the upgrade was to provide a higher bandwidth by exploiting recent technologies. The new readout system is composed by two paired electronic boards, Back Of Crate (BOC) and ReadOut Driver (ROD). In this presentation the main readout limitation related to increased luminosity will be discussed as well as the strategy and the technological solutions adopted...

  8. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  9. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  10. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  11. Front end electronics for silicon strip detectors in 90nm CMOS technology: advantages and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Kaplon, J; Noy, M, E-mail: Jan.Kaplon@cern.c [CERN, CH-1211 Geneva 23 (Switzerland)

    2010-11-15

    We present a 16 channel front end prototype implemented in 90nm CMOS IBM process and optimized for 5pF input capacitance. The primary motivation for this project is to study the usefulness of the CMOS technologies below 130nm for front end amplifiers optimized for short strip silicon detectors in Super Large Hadron Collider (SLHC) experiments [1]. In the presented design we show critical aspects of the front end stages implemented in the deep submicron technologies. Particular effort has been put into minimization of the power consumed by the front end electronics. The nominal power consumption providing Equivalent Noise Charge (ENC) level below 1000e- for the chip loaded with 5pF input capacitance is around 220{mu}W per channel.

  12. Desarrollo de un terminal punto de venta (TPV) : Arquitectura front-end con Angular2

    OpenAIRE

    López Jurado, Francisco Carlos

    2017-01-01

    Desarrollo de la arquitectura front-end para un terminal de punto de venta. Diseño y maquetación de las vistas de la aplicación. Implementación de todas las vistas, utilizando una arquitectura de componentes con Angular2. Definición de los endpoints del back-end que debe utilizar la capa front-end. Definición e implementación de los modelos de la capa front-end, que serán recibidos por la capa back-end como wrappers. Implantación de un plan de pruebas para la capa front-end, haciend...

  13. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  14. Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

    CERN Document Server

    Aruntinov, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Wermes, N; Breugnon, P; Chantepie, B; Clemens, J.C; Fei, R; Fougeron, D; Godiot, S; Pangaud, P; Rozanov, A; Garcia-Sciveres, M; Mekkaoui, A

    2013-01-01

    3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.

  15. Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

    CERN Document Server

    INSPIRE-00304438; Gkougkousis, E.; Lounis, A.

    2015-01-01

    The LHC accelerator complex will be upgraded between 2020-2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented.

  16. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  17. Muon capture in the front end of the IDS neutrino factory

    OpenAIRE

    Neuffer, D.; M. Martini; Prior, G.; Rogers, C; Yoshikawa, C.

    2012-01-01

    We discuss the design of the muon capture front end of the neutrino factory International Design Study. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then accelerated to high energy where their decays ...

  18. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  19. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  20. 75 FR 16819 - Notice of Proposed Information Collection for Public Comment Civil Rights Front End and Limited...

    Science.gov (United States)

    2010-04-02

    ... URBAN DEVELOPMENT Notice of Proposed Information Collection for Public Comment Civil Rights Front End... responses. This notice also lists the following information: Title of Proposal: Civil Rights Front End and.... Civil rights Front- End Limited Monitoring reviews shall be conducted for twenty (20) Tier 1 PHAs. The...

  1. 40 CFR 63.490 - Batch front-end process vents-performance test methods and procedures to determine compliance.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... Pollutant Emissions: Group I Polymers and Resins § 63.490 Batch front-end process vents—performance test... interim status requirements of 40 CFR part 265, subpart O. (c) Batch front-end process vent testing and...

  2. The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407702

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

  3. Proposal for a readout driver card for the ATLAS Insertable B-Layer

    CERN Document Server

    Falchieri, D; The ATLAS collaboration; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N C; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHC-PHASE1. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The poster presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

  4. Performance and description of the upgraded readout with the new back-end electronics for the ATLAS Pixel detector

    CERN Document Server

    Yajima, Kazuki; The ATLAS collaboration

    2017-01-01

    LHC increased drastically its performance during the RUN2 data taking, starting from a peak instantaneous luminosity of up to $5\\times10^{33} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in 2015 to conclude with the record value of $1.4\\times10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in November 2016. The concurrent increase of the trigger rate and event size forced the ATLAS experiment to exploit its sub-detectors to the maximum, approaching and possibly overcoming the design parameters. The ATLAS Pixel data acquisition system was upgraded to avoid possible bandwidth limitations. Two upgrades of the read-out electronics have been done. The first one during 2015/16 YETS, when the outermost pixel layer (Layer-2) was upgraded and its bandwidth was doubled. This upgrade partly contributed to maintain the data taking efficiency of the Pixel detector at a relatively high level ($\\sim$99%) during the 2016 run. A similar upgrade of the read-out system for the middle layer (Layer-1) is ongoing during 2016/17 EYETS. The details o...

  5. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    CERN Document Server

    Terzo, Stefano; Nisius, R.; Paschen, B.

    2014-01-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 $\\mu$m, produced at CiS, and 100-200 $\\mu$m thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The perfo...

  6. Silicon sensor technologies for ATLAS IBL upgrade

    CERN Document Server

    Grenier, P; The ATLAS collaboration

    2011-01-01

    New pixel sensors are currently under development for ATLAS Upgrades. The first upgrade stage will consist in the construction of a new pixel layer that will be installed in the detector during the 2013 LHC shutdown. The new layer (Insertable-B-Layer, IBL) will be inserted between the inner most layer of the current pixel detector and the beam pipe at a radius of 3.2cm. The expected high radiation levels require the use of radiation hard technology for both the front-end chip and the sensor. Two different pixel sensor technologies are envisaged for the IBL. The sensor choice will occur in July 2011. One option is developed by the ATLAS Planar Pixel Sensor (PPS) Collaboration and is based on classical n-in-n planar silicon sensors which have been used for the ATLAS Pixel detector. For the IBL, two changes were required: The thickness was reduced from 250 um to 200 um to improve the radiation hardness. In addition, so-called "slim edges" were designed to reduce the inactive edge of the sensors from 1100 um to o...

  7. Design of the NSLS-II Linac Front End Test Stand

    Energy Technology Data Exchange (ETDEWEB)

    Fliller III, R.; Johanson, M.; Lucas, M.; Rose, J.; Shaftan, T.

    2011-03-28

    The NSLS-II operational parameters place very stringent requirements on the injection system. Among these are the charge per bunch train at low emittance that is required from the linac along with the uniformity of the charge per bunch along the train. The NSLS-II linac is a 200 MeV linac produced by Research Instruments Gmbh. Part of the strategy for understanding to operation of the injectors is to test the front end of the linac prior to its installation in the facility. The linac front end consists of a 100 kV electron gun, 500 MHz subharmonic prebuncher, focusing solenoids and a suite of diagnostics. The diagnostics in the front end need to be supplemented with an additional suite of diagnostics to fully characterize the beam. In this paper we discuss the design of a test stand to measure the various properties of the beam generated from this section. In particular, the test stand will measure the charge, transverse emittance, energy, energy spread, and bunching performance of the linac front end under all operating conditions of the front end.

  8. The front-end desaturase: structure, function, evolution and biotechnological use.

    Science.gov (United States)

    Meesapyodsuk, Dauenpen; Qiu, Xiao

    2012-03-01

    Very long chain polyunsaturated fatty acids such as arachidonic acid (ARA, 20:4n-6), eicosapentaenoic acid (EPA, 20:5n-3), docosapentaenoic acid (DPA, 22:5n-3) and docosahexaenoic acid (DHA, 22:6n-3) are essential components of cell membranes, and are precursors for a group of hormone-like bioactive compounds (eicosanoids and docosanoids) involved in regulation of various physiological activities in animals and humans. The biosynthesis of these fatty acids involves an alternating process of fatty acid desaturation and elongation. The desaturation is catalyzed by a unique class of oxygenases called front-end desaturases that introduce double bonds between the pre-existing double bond and the carboxyl end of polyunsaturated fatty acids. The first gene encoding a front-end desaturase was cloned in 1993 from cyanobacteria. Since then, front-end desaturases have been identified and characterized from a wide range of eukaryotic species including algae, protozoa, fungi, plants and animals including humans. Unlike front-end desaturases from bacteria, those from eukaryotes are structurally characterized by the presence of an N-terminal cytochrome b₅-like domain fused to the main desaturation domain. Understanding the structure, function and evolution of front-end desaturases, as well as their roles in the biosynthesis of very long chain polyunsaturated fatty acids offers the opportunity to engineer production of these fatty acids in transgenic oilseed plants for nutraceutical markets.

  9. Development of edgeless silicon pixel sensors on p-type substrate for the ATLAS high-luminosity upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste and INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2014-11-21

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R and D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  10. Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

    CERN Document Server

    Giacomini, Gabriele; Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

    2014-01-01

    In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch.

  11. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    Calderini, G; Bomben, M; Boscardin, M; Bosisio, L; Chauveau, J; Giacomini, G; La Rosa, A; Marchiori, G; Zorzi, N

    2014-01-01

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R&D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  12. Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    INSPIRE-00052711; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

    2016-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

  13. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  14. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, Michael

    2010-07-19

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 10{sup 35}/cm{sup 2}s{sup 1} is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).10{sup 16} 1-MeV-neutrons per square centimeter (n{sub eq}/cm{sup 2}). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 {mu}m and 150 {mu}m proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive

  15. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Beccherle, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Pisa (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste (Italy); INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2016-09-21

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  16. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  17. Front-end Electronics Test for the LHCb Muon Wire Chambers

    CERN Document Server

    Nobrega, R; Carboni, G; Massafferri, A; Santovetti, E

    2007-01-01

    This document describes the apparatus and procedures implemented to test Multi Wire Proportional Chambers (MWPC) after front-end assembly for the LHCb Muon Detector. Results of measurements of key noise parameters are also described. Given a fully equipped chamber, this system is able to diagnose every channel performing an analysis of front-end output drivers’ response and noise rate versus threshold. Besides, it allows to assess if the noise rate at the experiment threshold region is within appropriate limits. Aiming at an automatic, fast and user-friendly system for mass production tests of MWPC, the project has foreseen as well electronic identification of every chamber and front-end board, and data archiving in such a way to make it available to the Experiment Control System (ECS) while in operation.

  18. Report on the value engineering workshop on APS beamline front ends

    Energy Technology Data Exchange (ETDEWEB)

    Kuzay, T.

    1993-01-01

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions.

  19. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  20. A tunable RF Front-End with Narrowband Antennas for Mobile Devices

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Olesen, Poul; Madsen, Peter

    2015-01-01

    are replaced by tunable filters and antennas, providing a duplexer function over the air between the Tx and the Rx. A hardware system has been designed and fabricated to demonstrate the performance of this front-end architecture. Measurements demonstrate how the architecture addresses inter-modulation and Rx......In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex filters...

  1. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using...... subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AFE will enable various desired features, as for example the ability to use the front-end with antenna...... arrays needing one receiver per antenna (Synthetic Aperture Radiometer, SARad), reduced weight for airborne missions and an easy temperature stabilization, i.e. improved instrument stability. The new front-end possesses an improved system noise temperature of only 76 K (roughly 40 K improvement) measured...

  2. Design of an analog front-end for ambulatory biopotential measurement systems

    Energy Technology Data Exchange (ETDEWEB)

    Wang Jiazhen; Xu Jun; Zheng Lirong; Ren Junyan, E-mail: jxu@fudan.edu.c [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-10-15

    A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 {mu}Vrms (0.48-2000 Hz). The chip is fabricated via a SMIC 0.18 {mu}m CMOS process. Although the power consumption is only 32.1 {mu}W under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals. (semiconductor integrated circuits)

  3. Preparation for the upgrade of CMS Hadron Endcap Calorimeter front-end

    Science.gov (United States)

    Bychkova, O. V.; Popova, E. V.; Parygin, P. P.; Bunin, P. D.; Kalinin, A. Yu

    2017-01-01

    The hadron endcap (HE) calorimeter is one of the major sections of CMS detector, used for measurement of the hadrons energy. Phase1 upgrade of the front-end electronics components in the HE calorimeter is being prepared, in particular to improve ability to handle increased pile-up and mitigate radiation damage of optical system in the high eta region. Tests of Phase1 HE Front-end system including new photo-sensors, silicon photomultipliers (SiPM), as well as new charge integrator encoder (QIE11) were performed in the Burn-in station in b904 at CERN. In this note, analysis and measurement results for the new generation front-end electronics components are presented.

  4. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Science.gov (United States)

    Gevin, O.; Lemaire, O.; Lugiez, F.; Michalowska, A.; Baron, P.; Limousin, O.; Delagnes, E.

    2012-12-01

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  5. Flexible Analog Front Ends of Reconfigurable Radios Based on Sampling and Reconstruction with Internal Filtering

    Directory of Open Access Journals (Sweden)

    Poberezhskiy Yefim S.

    2005-01-01

    Full Text Available Bandpass sampling, reconstruction, and antialiasing filtering in analog front ends potentially provide the best performance of software defined radios. However, conventional techniques used for these procedures limit reconfigurability and adaptivity of the radios, complicate integrated circuit implementation, and preclude achieving potential performance. Novel sampling and reconstruction techniques with internal filtering eliminate these drawbacks and provide many additional advantages. Several ways to overcome the challenges of practical realization and implementation of these techniques are proposed and analyzed. The impact of sampling and reconstruction with internal filtering on the analog front end architectures and capabilities of software defined radios is discussed.

  6. LHCb calorimeter front-end electronics radiation dose and single event effects

    CERN Document Server

    Beigbeder-Beau, C; Charlet, D; Lefrançois, J; Machefert, F P; Tocut, V; Truong, K D

    2002-01-01

    The LHCb calorimeter front-end electronics will be located above the ECAL / HCAL, i.e. in a region which is not protected from radiations. We present here an estimation of the radiation effect for the electronics and the solutions we investigate to reduce it. Two irradiation tests of the calorimeter front-end shaper have been performed, in June 2001 at the Centre de Proton Thérapie (Orsay) and in December 2001 at GANIL (Caen). The results of the tests clearly show the satisfying resistance of the shaper to SEL.

  7. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    Directory of Open Access Journals (Sweden)

    Bin You

    2013-01-01

    Full Text Available A new ultrahigh frequency radio frequency identification (UHF RFID reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both the sensitivity and detection range compared to the conventional designs.

  8. Alternative Muon Front-end for the International Design Study (IDS)

    CERN Document Server

    Alekou, A; Martini, M; Prior, G; Rogers, C; Stratakis, D; Yoshikawa, C; Zisman, M

    2010-01-01

    We discuss alternative designs of the muon capture front end of the Neutrino Factory International Design Study (IDS). In the front end, a proton bunch on a target creates secondary pions that drift into a capture channel, decaying into muons. A sequence of RF cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. This design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  9. Muon capture in the front end of the IDS neutrino factory

    CERN Document Server

    Neuffer, D.; Prior, G.; Rogers, C.; Yoshikawa, C.

    2010-01-01

    We discuss the design of the muon capture front end of the neutrino factory International Design Study. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. For the International Design Study (IDS), a baseline design must be developed and optimized for an engineering and cost study. The design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  10. Understanding and addressing racial/ethnic disproportionality in the front end of the child welfare system.

    Science.gov (United States)

    Osterling, Kathy Lemon; D'Andrade, Amy; Austin, Michael J

    2008-01-01

    Racial/ethnic disproportionality in the child welfare system is a complicated social problem that is receiving increasing amounts of attention from researchers and practitioners. This review of the literature examines disproportionality in the front-end of the child welfare system and interventions that may address it. While none of the interventions had evidence suggesting that they reduced disproportionality in child welfare front-end processes, some of the interventions may improve child welfare case processes related to disproportionality and outcomes for families of color.

  11. Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A M

    1992-01-01

    Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...... available GaInAs/InP pin photo diode. The procedure for measuring the transimpedance and the equivalent input noise current density is outlined in this paper and demonstrated using one of the MMICs. The MMICs were fabricated using the Plessey F20 process by GEC-Marconi through the ESPRIT programme EUROCHIP...

  12. Detector Control System of the ATLAS Insertable B-Layer

    CERN Document Server

    Kersten, S; Lantzsch, K; Zeitnitz, C; Verlaat, B; Meroni, C; Citterio, M; Gensolen, F; Mättig, P; Kind, P

    2011-01-01

    To improve tracking robustness and precision of the ATLAS inner tracker, an additional, fourth pixel layer is foreseen, called Insertable B-Layer (IBL). It will be installed between the innermost present Pixel layer and a new, smaller beam pipe and is presently under construction. As, once installed into the experiment, no access is possible, a highly reliable control system is required. It has to supply the detector with all entities required for operation and protect it at all times. Design constraints are the high power density inside the detector volume, the sensitivity of the sensors against heat-ups, and the protection of the front end electronics against transients. We present the architecture of the control system with an emphasis on the CO2 cooling system, the power supply system, and protection strategies. As we aim for a common operation of Pixel and IBL detector, the integration of the IBL control system into the Pixel control system will also be discussed.

  13. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  14. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens

    2009-01-01

    This paper addresses the design, implementation and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design comprises commercial-of-the-shelf modules and newly purpose-built components at a centre frequency of 435 MHz with 20% relat...

  15. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  16. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... § 63.489 Batch front-end process vents—monitoring equipment. (a) General requirements. Each owner or... indicator that takes a reading at least once every 15 minutes. Records shall be generated as specified in... shall be submitted with the information in paragraph (e)(2) of this section. The definition of operating...

  17. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified...

  18. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

    DEFF Research Database (Denmark)

    di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere

    2016-01-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point s...

  19. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  20. User Consultation during the Fuzzy Front End: Evaluating Student's Design Outcomes

    Science.gov (United States)

    Conradie, Peter; De Marez, Lieven; Saldien, Jelle

    2017-01-01

    In this paper we evaluate the involvement of a partially blind user as lead user in the early stages of a product redesign during an undergraduate product design-engineering course. Throughout the early stages of product design, or fuzzy front end, there is a high level of uncertainty. End users, with their increased contextual knowledge can play…

  1. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    2015-11-27

    Nov 27, 2015 ... Abstract. Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  2. Low power analog readout front-end electronics for time and energy measurements

    Science.gov (United States)

    Kleczek, R.; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR-RC shaper with the peaking time tp=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR-(RC)2 shaper with the peaking time tp=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation Pdiss=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  3. Multi-channel reconfigurable front-end architecture for waveform-agile radar

    NARCIS (Netherlands)

    Calabrese, G.; Pagli, L.; Krasnov, O.A.; Yarovoy, A.G.

    2013-01-01

    This paper presents the design of a multi-channel reconfigurable front-end architecture for a waveform-agile radar. At first the purpose of the design is explained following the status of research on software-defined radar at MTSR. A description of the proposed system architecture is given with

  4. Front-end electronics development for TPC detector in the MPD/NICA project

    Science.gov (United States)

    Cheremukhina, G.; Movchan, S.; Vereschagin, S.; Zaporozhets, S.

    2017-06-01

    The article is aimed at describing the development status, measuring results and design changes of the TPC front-end electronics. The TPC is placed in the middle of Multi-Purpose Detector (MPD) and provides tracing and identifying of charged particles in the pseudorapidity range |η| electronics of each readout chamber is an independent system. The whole system contains 95232 channels, 1488 64-channel—front-end cards (FEC), 24 readout control units (RCU). The front-end electronics (FEE) is based on ASICs, FPGAs and high-speed serial links. The concept of the TPC front-end electronics has been motivated from one side—by the requirements concerning the NICA accelerator complex which will operate at the luminosity up to 1027 cm-2 s-1 for Au79+ ions over the energy range of 4 < √SNN < 11 GeV with the trigger rate up to 7 kHz and from the other side—by the requirements of the 4-π geometry to minimize the substance on the end-caps of the TPC.

  5. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Science.gov (United States)

    Chunhua, Wang; Minglin, Ma; Jingru, Sun; Sichun, Du; Xiaorong, Guo; Haizhen, He

    2011-02-01

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (Gm-LNA) and a differential current-mode down converted mixer. The single terminal of the Gm-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, Cx1 and Cx2, can not only reduce the effects of gate-source Cgs on resonance frequency and input-matching impedance, but they also enable the gate inductance Lg1,2 to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 μm CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations.

  6. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube

  7. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  8. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken...

  9. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  10. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  11. Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

    Science.gov (United States)

    2016-09-01

    the front - end and back - end system integration stage to ensure accurate EM parameter measurements. The seamless integration resulted in a robust and...and B. Krantz, “RF photonics for radar front - ends ,” in IEEE Radar Conf.,Boston, MA, Apr. 2007, pp. 965–970. [8] M. E . Manka, “Microwave photonics...PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT - END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION by Chew K. Tan

  12. Prototyping of larger structures for the Phase-II upgrade of the pixel detector of the ATLAS experiment

    CERN Document Server

    Alvarez Feito, Diego; The ATLAS collaboration

    2017-01-01

    For the high luminosity era of the Large Hadron Collider (HL-LHC) it is forseen to replace the current inner tracker of the ATLAS experiment with a new detector to cope with the occuring increase in occupancy, bandwidth and radiation damage. It will consist of an inner pixel and outer strip detector aiming to provide tracking coverage up to |η|<4. The layout of the pixel detector is foreseen to consist of five layers of pixel silicon sensor modules in the central region and several ring-shaped layers in the forward region. It results in up to 14 m² of silicon depending on the selected layout. Beside the challenge of radiation hardness and high-rate capable silicon sensors and readout electronics many system aspects have to be considered for a fully functional detector. Both stable and low mass mechanical structures and services are important. Within the collaboration a large effort is started to prototype larger detector structures for both the central and forward region of the detector. The aspect of sy...

  13. Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268

    The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

  14. Performance of n-in-p pixel detectors irradiated at fluences up to $5x10^{15} n_{eq}/cm^{2}$ for the future ATLAS upgrades

    CERN Document Server

    INSPIRE-00219560; La Rosa, A.; Nisius, R.; Pernegger, H.; Richter, R.H.; Weigell, P.

    We present the results of the characterization of novel n-in-p planar pixel detectors, designed for the future upgrades of the ATLAS pixel system. N-in-p silicon devices are a promising candidate to replace the n-in-n sensors thanks to their radiation hardness and cost effectiveness, that allow for enlarging the area instrumented with pixel detectors. The n-in-p modules presented here are composed of pixel sensors produced by CiS connected by bump-bonding to the ATLAS readout chip FE-I3. The characterization of these devices has been performed with the ATLAS pixel read-out systems, TurboDAQ and USBPIX, before and after irradiation with 25 MeV protons and neutrons up to a fluence of 5x10**15 neq /cm2. The charge collection measurements carried out with radioactive sources have proven the feasibility of employing this kind of detectors up to these particle fluences. The collected charge has been measured to be for any fluence in excess of twice the value of the FE-I3 threshold, tuned to 3200 e. The first result...

  15. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  16. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing

    Directory of Open Access Journals (Sweden)

    Lin Hu

    2016-11-01

    Full Text Available The cognitive radio wireless sensor network (CR-WSN has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  17. DSP-based Mitigation of RF Front-end Non-linearity in Cognitive Wideband Receivers

    Science.gov (United States)

    Grimm, Michael; Sharma, Rajesh K.; Hein, Matthias A.; Thomä, Reiner S.

    2012-09-01

    Software defined radios are increasingly used in modern communication systems, especially in cognitive radio. Since this technology has been commercially available, more and more practical deployments are emerging and its challenges and realistic limitations are being revealed. One of the main problems is the RF performance of the front-end over a wide bandwidth. This paper presents an analysis and mitigation of RF impairments in wideband front-ends for software defined radios, focussing on non-linear distortions in the receiver. We discuss the effects of non-linear distortions upon spectrum sensing in cognitive radio and analyse the performance of a typical wideband software-defined receiver. Digital signal processing techniques are used to alleviate non-linear distortions in the baseband signal. A feed-forward mitigation algorithm with an adaptive filter is implemented and applied to real measurement data. The results obtained show that distortions can be suppressed significantly and thus increasing the reliability of spectrum sensing.

  18. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... are: • What are the objectives of measurement in radical design? and • What are the most crucial future challenges related with the selection of the relevant measurement objectives? Based on the theoretical part of this paper, our framework of the Balanced Design Front-End Model (BDFEM) for measuring...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

  19. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

    2013-01-01

    -end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...... structures, technical features and design, creativity and social interaction. The analysis inputs an initial conceptualisation of a new theoretical framework of idea management. The theoretical framework suggests a dynamic network structure comprised of the dimensions of space, content, and process....... been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front...

  20. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front...... structures, technical features and design, creativity and social interaction. The analysis inputs an initial conceptualisation of a new theoretical framework of idea management. The theoretical framework suggests a dynamic network structure comprised of the dimensions of space, content, and process.......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  1. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  2. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  3. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  4. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas......Product-service systems (PSS) adoption has increased over the last years due to its potential for innovative value creation. However, the identification of ideas and opportunities in the innovation planning and the structuring of PSS projects are still incipient in organizations, following the same...... patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...

  5. Muon capture in the front end of the IDS neutrino factory

    CERN Document Server

    Neuffer, D; Prior, G; Rogers, C; Yoshikawa, C

    2012-01-01

    We discuss the design of the muon capture front end of the neutrino factory International Design Study. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then accelerated to high energy where their decays provide neutrino beams. For the International Design Study (IDS), a baseline design must be developed and optimized for an engineering and cost study. We present a baseline design that can be used to establish the scope of a future neutrino Factory facility.

  6. Status of the Warm Front End of PIP-II Injector Test

    Energy Technology Data Exchange (ETDEWEB)

    Shemyakin, Alexander [Fermilab; Alvarez, Matthew [Fermilab; Andrews, Richard [Fermilab; Baffes, Curtis [Fermilab; Carneiro, Jean-Paul [Fermilab; Chen, Alex [Fermilab; Derwent, Paul [Fermilab; Edelen, Jonathan [Fermilab; Frolov, Daniil [Fermilab; Hanna, Bruce [Fermilab; Prost, Lionel [Fermilab; Saewert, Gregory [Fermilab; Saini, Arun [Fermilab; Scarpine, Victor [Fermilab; Sista, V. Lalitha [Fermilab; Steimel, Jim [Fermilab; Sun, Ding [Fermilab; Warner, Arden [Fermilab

    2017-05-01

    The Proton Improvement Plan II (PIP-II) at Fermilab is a program of upgrades to the injection complex. At its core is the design and construction of a CW-compatible, pulsed H⁻ SRF linac. To validate the concept of the front-end of such machine, a test accelerator known as PIP-II Injector Test is under construction. It includes a 10 mA DC, 30 keV H⁻ ion source, a 2 m-long Low Energy Beam Transport (LEBT), a 2.1 MeV CW RFQ, followed by a Medium Energy Beam Transport (MEBT) that feeds the first of 2 cryomodules increasing the beam energy to about 25 MeV, and a High Energy Beam Transport section (HEBT) that takes the beam to a dump. The ion source, LEBT, RFQ, and initial version of the MEBT have been built, installed, and commissioned. This report presents the overall status of the warm front end.

  7. A High Input Impedance Low Noise Integrated Front-End Amplifier for Neural Monitoring.

    Science.gov (United States)

    Zhou, Zhijun; Warr, Paul A

    2016-12-01

    Within neural monitoring systems, the front-end amplifier forms the critical element for signal detection and pre-processing, which determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a novel combined feedback loop-controlled approach is proposed to compensate for input leakage currents generated by low noise amplifiers when in integrated circuit form alongside signal leakage into the input bias network. This loop topology ensures the Front-End Amplifier (FEA) maintains a high input impedance across all manufacturing and operational variations. Measured results from a prototype manufactured on the AMS 0.35 [Formula: see text] CMOS technology is provided. This FEA consumes 3.1 [Formula: see text] in 0.042 [Formula: see text], achieves input impedance of 42 [Formula: see text], and 18.2 [Formula: see text] input-referred noise.

  8. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing.

    Science.gov (United States)

    Hu, Lin; Ma, Hong; Zhang, Hua; Zhao, Wen

    2016-11-25

    The cognitive radio wireless sensor network (CR-WSN) has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF) front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC) algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  9. A multi-host front end concentrator system for asynchronous consoles

    CERN Document Server

    Palandri, E M

    1974-01-01

    Describes a front end concentrator system for asynchronous time sharing consoles which has recently been put into operation at CERN. The concentrator will control up to 36 consoles at speeds up to 9600 bits per second and has the capability of dynamically connecting these consoles to several large Host processors. Features of the system include specially designed hardware and software to connect a wide range of different types of consoles in a flexible and expandable way, and the use of special purpose microcode to optimise console handling and facilitate the implementation of the system. The system runs in an HP2100 computer initially front-ending CDC 6000 series computers using the INTERCOM time sharing system. (6 refs).

  10. Étude des détecteurs planaires pixels durcis aux radiations pour la mise à jour du détecteur de vertex d'ATLAS

    CERN Document Server

    Benoit, Mathieu

    In this work, is presented a study, using TCAD simulation, of the possible methods of designing of a planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure,a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor's process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain ...

  11. Ultra-light and stable composite structure to support and cool the ATLAS pixel detector barrel electronics modules

    CERN Document Server

    Olcese, M; Castiglioni, G; Cereseto, R; Cuneo, S; Dameri, M; Gemme, C; Glitza, K W; Lenzen, G; Mora, F; Netchaeva, P; Ockenfels, W; Piano, E; Pizzorno, C; Puppo, R; Rebora, A; Rossi, L; Thadome, J; Vernocchi, F; Vigeolas, E; Vinci, A

    2004-01-01

    The design of an ultra light structure, the so-called "stave", to support and cool the sensitive elements of the Barrel Pixel detector, the innermost part of the ATLAS detector to be installed on the new Large Hadron Collider at CERN (Geneva), is presented. Very high- dimensional stability, minimization of the material and ability of operating 10 years in a high radiation environment are the key design requirements. The proposed solution consists of a combination of different carbon-based materials (impregnated carbon-carbon, ultra high modulus carbon fibre composites) coupled to a thin aluminum tube to form a very light support with an integrated cooling channel. Our design has proven to successfully fulfil the requirements. The extensive prototyping and testing program to fully qualify the design and release the production are discussed.

  12. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

    2011-02-15

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  13. Production of the front-end boards of the LHCb muon system

    CERN Document Server

    Bonivento, W; Auriemma, G

    2008-01-01

    This note describes the production of the front end boards CARDIAC, for the 1368 MWPC, and CARDIAC-GEM, for the 12 triple-GEM chambers, of the LHCb muon system. The PCB structure and component layout and the production issues, such as component soldering, quality assurance at the company and delivery rates, are described. The performance of these boards will be the subject of a future publication.

  14. Unified analytical expressions for calculating resonant frequencies, transimpedances, and equivalent input noise current densities of tuned receiver front ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1992-01-01

    Unified analytical expressions have been derived for calculating the resonant frequencies, transimpedance and equivalent input noise current densities of the four most widely used tuned optical receiver front ends built with FETs and p-i-n diodes. A more accurate FET model has been used to improve...... the accuracy of the analysis. The Miller capacitance has been taken into account, and its impact on the performances of the tuned front ends has been demonstrated. The accuracy of the expressions has been verified by Touchstone simulations. The agreement between the calculated and simulated performances...... of the front ends is very good. The expressions can be used to investigate the performances of different tuned front ends in a very simple way and provide a good starting point for further computer optimizations of the front ends...

  15. Web-based DAQ systems: connecting the user and electronics front-ends

    Science.gov (United States)

    Lenzi, Thomas

    2016-12-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  16. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  17. Reviewed approach to defining the Active Interlock Envelope for Front End ray tracing

    Energy Technology Data Exchange (ETDEWEB)

    Seletskiy, S. [Brookhaven National Lab. (BNL), Upton, NY (United States); Shaftan, T. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2015-09-24

    To protect the NSLS-II Storage Ring (SR) components from damage from synchrotron radiation produced by insertion devices (IDs) the Active Interlock (AI) keeps electron beam within some safe envelope (a.k.a Active Interlock Envelope or AIE) in the transverse phase space. The beamline Front Ends (FEs) are designed under assumption that above certain beam current (typically 2 mA) the ID synchrotron radiation (IDSR) fan is produced by the interlocked e-beam. These assumptions also define how the ray tracing for FE is done. To simplify the FE ray tracing for typical uncanted ID it was decided to provide the Mechanical Engineering group with a single set of numbers (x,x’,y,y’) for the AIE at the center of the long (or short) ID straight section. Such unified approach to the design of the beamline Front Ends will accelerate the design process and save valuable human resources. In this paper we describe our new approach to defining the AI envelope and provide the resulting numbers required for design of the typical Front End.

  18. 45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

    Science.gov (United States)

    Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

    2012-07-30

    In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

  19. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  20. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    CERN Document Server

    Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P; 10.1088/1748-0221/5/12/C12025

    2010-01-01

    The presented R&D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut für Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 1016neqcm−2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the ...

  1. Effects of vehicle impact velocity, vehicle front-end shapes on pedestrian injury risk.

    Science.gov (United States)

    Han, Yong; Yang, Jikuang; Mizuno, Koji; Matsui, Yasuhiro

    2012-09-01

    This study aimed at investigating the effects of vehicle impact velocity, vehicle front-end shape, and pedestrian size on injury risk to pedestrians in collisions with passenger vehicles with various frontal shapes. A series of parametric studies was carried out using 2 total human model for safety (THUMS) pedestrian models (177 and 165 cm) and 4 vehicle finite element (FE) models with different front-end shapes (medium-size sedan, minicar, one-box vehicle, and sport utility vehicle [SUV]). The effects of the impact velocity on pedestrian injury risk were analyzed at velocities of 20, 30, 40, and 50 km/h. The dynamic response of the pedestrian was investigated, and the injury risk to the head, chest, pelvis, and lower extremities was compared in terms of the injury parameters head injury criteria (HIC), chest deflection, and von Mises stress distribution of the rib cage, pelvis force, and bending moment diagram of the lower extremities. Vehicle impact velocity has the most significant influence on injury severity for adult pedestrians. All injury parameters can be reduced in severity by decreasing vehicle impact velocities. The head and lower extremities are at greater risk of injury in medium-size sedan and SUV collisions. The chest injury risk was particularly high in one-box vehicle impacts. The fracture risk of the pelvis was also high in one-box vehicle and SUV collisions. In minicar collisions, the injury risk was the smallest if the head did not make contact with the A-pillar. The vehicle impact velocity and vehicle front-end shape are 2 dominant factors that influence the pedestrian kinematics and injury severity. A significant reduction of all injuries can be achieved for all vehicle types when the vehicle impact velocity is less than 30 km/h. Vehicle designs consisting of a short front-end and a wide windshield area can protect pedestrians from fatalities. The results also could be valuable in the design of a pedestrian-friendly vehicle front-end shape

  2. Test-beam activities and results for the ATLAS ITk pixel detector

    Science.gov (United States)

    Bisanz, T.

    2017-12-01

    The Phase-II upgrade of the LHC aims at an increase of the instantaneous luminosity up to about 5×1034 cm‑2 s‑1. To cope with the resulting challenges the current Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) system. The Pixel Detector will have to deal with occupancies of about 300 hits/FE/s as well as a fluence of around 2×1016 neq cm‑2. Various sensor layouts are under development, aiming at providing a high performance, cost effective pixel instrumentation to cover an active area of about 10 m2. These range from thin planar silicon, 3D silicon, to active CMOS sensors. After extensive characterization of the sensors in the lab, their charge collection properties and hit efficiency are measured in common testbeam campaigns, which provide valuable feedback for improvements of the layout. Testbeam measurements of the final prototypes will be used for the decision of which sensor types will be installed in ITk. The setups used in the ITk Pixel testbeam campaigns will be presented, including the common track reconstruction and analysis software. Results from the latest measurements will be shown, highlighting some of the developments and challenges for the ITk Pixel sensors.

  3. Test beam Characterizations of 3D Silicon Pixel detectors

    CERN Document Server

    Mathes, M; Da Via, C.; Garcia-Sciveres, M.; Einsweiler, K.; Hasi, J.; Kenney, C.; Parker, Sherwood; Reuen, L.; Ruspa, M.; Velthuis, J.; Watts, S.; Wermes, N.

    2008-01-01

    3D silicon detectors are characterized by cylindrical electrodes perpendicular to the surface and penetrating into the bulk material in contrast to standard Si detectors with planar electrodes on its top and bottom. This geometry renders them particularly interesting to be used in environments where standard silicon detectors have limitations, such as for example the radiation environment expected in an LHC upgrade. For the first time, several 3D sensors were assembled as hybrid pixel detectors using the ATLAS-pixel front-end chip and readout electronics. Devices with different electrode configurations have been characterized in a 100 GeV pion beam at the CERN SPS. Here we report results on unirradiated devices with three 3D electrodes per 50 x 400 um2 pixel area. Full charge collection is obtained already with comparatively low bias voltages around 10 V. Spatial resolution with binary readout is obtained as expected from the cell dimensions. Efficiencies of 95.9% +- 0.1 % for tracks parallel to the electrode...

  4. Qualification measurements of the voltage supply system as well as conceptionation of a state machine for the detector control of the ATLAS pixel detector; Qualifizierungsmessungen des Spannungsversorgungssystems sowie Konzeptionierung einer Zustandsmaschine fuer die Detektorkontrolle des ATLAS-Pixeldetektors

    Energy Technology Data Exchange (ETDEWEB)

    Schultes, Joachim

    2007-02-15

    The supply system and the control system of the ATLAS pixel detector represent important building blocks of the pixel detector. Corresponding studies of the supply system, which were performed within a comprehensive test system, the so-called system test, with nearly all final components and the effects on the pixel detector are object of this thesis. A further point of this thesis is the coordination and further development of the detector-control-system software under regardment of the different partial systems. A main topic represents thereby the conceptionation of the required state machine as interface for the users and the connection to the data acquisition system.

  5. An Introduction to ATLAS Pixel Detector DAQ and Calibration Software Based on a Year's Work at CERN for the Upgrade from 8 to 13 TeV

    CERN Document Server

    AUTHOR|(CDS)2094561

    An overview is presented of the ATLAS pixel detector Data Acquisition (DAQ) system obtained by the author during a year-long opportunity to work on calibration software for the 2015-16 Layer‑2 upgrade. It is hoped the document will function more generally as an easy entry point for future work on ATLAS pixel detector calibration systems. To begin with, the overall place of ATLAS pixel DAQ within the CERN Large Hadron Collider (LHC), the purpose of the Layer-2 upgrade and the fundamentals of pixel calibration are outlined. This is followed by a brief look at the high level structure and key features of the calibration software. The paper concludes by discussing some difficulties encountered in the upgrade project and how these led to unforeseen alternative enhancements, such as development of calibration “simulation” software allowing the soundness of the ongoing upgrade work to be verified while not all of the actual readout hardware was available for the most comprehensive testing.

  6. Fluorocarbon evaporative cooling developments for the ATLAS pixel and semiconductor tracking detectors

    CERN Document Server

    Anderssen, E; Berry, S; Bonneau, P; Bosteels, Michel; Bouvier, P; Cragg, D; English, R; Godlewski, J; Górski, B; Grohmann, S; Hallewell, G D; Hayler, T; Ilie, S; Jones, T; Kadlec, J; Lindsay, S; Miller, W; Niinikoski, T O; Olcese, M; Olszowska, J; Payne, B; Pilling, A; Perrin, E; Sandaker, H; Seytre, J F; Thadome, J; Vacek, V

    1999-01-01

    Heat transfer coefficients 2-5.103 Wm-2K-1 have been measured in a 3.6 mm I.D. heated tube dissipating 100 Watts - close to the full equivalent power (~110 W) of a barrel SCT detector "stave" - over a range of power dissipations and mass flows in the above fluids. Aspects of full-scale evaporative cooling circulator design for the ATLAS experiment are discussed, together with plans for future development.

  7. The ATLAS Pixel detector and its use in a Search for Metastable Heavy Charged Particles

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00399154

    The discovery of the Higgs boson, the missing piece in the Standard Model puzzle, at the electroweak scale in 2012 by the ATLAS and CMS experiments, closed an important season of particle physics and a search lasted 50 years. Even though the discovery of the Higgs boson is a great achievement, the Standard Model is incomplete, since it does not include the gravitational field and can not explain some experimental measurements such as the dark matter observed in galaxy studies and the matter and anti-matter asymmetry observed in the universe. The experiments at LHC have the exciting goal to give answers to the SM open questions and make available the hint or the evidence that may allow to proceed beyond it. An introduction on the Standard Model and the LHC is provided in Chapter 1 where the ATLAS detector is also described. ATLAS is the largest of the detectors placed along the LHC ring and is able to detect products from pp and heavy ion collisions. The detector has a cylindrical geometry around the interac...

  8. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Ristic, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on technologies that allow to use high depletion voltages (HV-MAPS) and high resistivity wafers (HR-MAPS) for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics to be embedded safely into the sensor substrate. We are investigating depleted CMOS pixels with monolithic or hybrid designs concerning their suitability for high rate, fast timing and high radiation operation at LHC. This paper will discuss recent results on the main candidate technologies and the current development towards a monolithic solution.

  9. Test-beam activities and results for the ATLAS ITk pixel detector

    CERN Document Server

    Bisanz, Tobias; The ATLAS collaboration

    2017-01-01

    The Phase-II upgrade of the LHC will result in an increase of the instantaneous luminosity up to about 5×1034 cm−2s−1. To cope with the challenges the current Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) system. The Pixel Detector will have to deal with occupancies of about 300~hits/FE/s as well as a fluence of 2×1016neqcm−2. Various sensor layouts are under development, aiming at providing a high performance, cost effective pixel instrumentation to cover an active area of about 10~m2. These range from thin planar silicon, over 3D silicon, to active CMOS sensors. After extensive characterization of the sensors in the lab, their charge collection properties and hit efficiency are measured in common testbeam campaigns, which provide valuable feedback for improvements of the layout. Testbeam measurements of the final prototypes will be used for the decision of which sensor types will be installed in ITk. The setups used in the ITk Pixel testbeam campaigns will be presented, inclu...

  10. Design and simulation of front end power converter for a microgrid with fuel cells and solar power sources

    Science.gov (United States)

    Jeevargi, Chetankumar; Lodhi, Anuj; Sateeshkumar, Allu; Elangovan, D.; Arunkumar, G.

    2017-11-01

    The need for Renewable Energy Sources (RES) is increasing due to increased demand for the supply of power and it is also environment friendly.In the recent few years, the cost of generation of the power from the RES has been decreased. This paper aims to design the front end power converter which is required for integrating the fuel cells and solar power sources to the micro grid. The simulation of the designed front end converter is carried out in the PSIM 9.1.1 software. The results show that the designed front end power converter is sufficient for integrating the micro grid with fuel cells and solar power sources.

  11. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland)

    2015-07-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  12. Serial powering optimization for CMS and ATLAS pixel detectors within RD53 collaboration for HL-LHC: System Level Simulations and Testing

    CERN Document Server

    Orfanelli, Stella; Hamer, Matthias; Hinterkeuser, F; Karagounis, M; Pradas Luengo, Alvaro; Marconi, Sara; Ruini, Daniele

    2017-01-01

    Serial powering is the baseline choice for low mass power distribution for the CMS and ATLAS HL-LHC pixel detectors. For this scheme, two 2.0\\,A Shunt-LDO (SLDO) regulators are integrated in the RD53 prototype chip (65\\,nm) and are used to provide constant supply voltages to its power domains from a constant input current. System level simulation studies will be presented, in which a detailed regulator design in a serially powered topology is used to evaluate and optimize system parameters for different operational scenarios of HL-LHC pixel detectors. Performance results from testing prototype SLDO chips will be shown, including x-ray irradiation.

  13. Effect of vehicle front end profiles leading to pedestrian secondary head impact to ground.

    Science.gov (United States)

    Gupta, Vishal; Yang, King H

    2013-11-01

    Most studies of pedestrian injuries focus on reducing traumatic injuries due to the primary impact between the vehicle and the pedestrian. However, based on the Pedestrian Crash Data Study (PCDS), some researchers concluded that one of the leading causes of head injury for pedestrian crashes can be attributed to the secondary impact, defined as the impact of the pedestrian with the ground after the primary impact of the pedestrian with the vehicle. The purpose of this study is to understand if different vehicle front-end profiles can affect the risk of pedestrian secondary head impact with the ground and thus help in reducing the risk of head injury during secondary head impact with ground. Pedestrian responses were studied using several front-end profiles based off a mid-size vehicle and a SUV that have been validated previously along with several MADYMO pedestrian models. Mesh morphing is used to explore changes to the bumper height, bonnet leading-edge height, and bonnet rear reference-line height. Simulations leading up to pedestrian secondary impact with ground are conducted at impact speeds of 40 and 30 km/h. In addition, three pedestrian sizes (50th, 5th and 6yr old child) are used to enable us to search for a front-end profile that performs well for multiple sizes of pedestrians, not just one particular size. In most of the simulations, secondary ground impact with pedestrian head/neck/shoulder region occurred. However, there were some front-end profiles that promoted secondary ground impact with pedestrian lower extremities, thus avoiding pedestrian secondary head impact with ground. Previous pedestrian safety research work has suggested the use of active safety methods, such as 'pop up hood', to reduce pedestrian head injury during primary impact. Accordingly, we also conducted simulations using a model with the hood raised to capture the effect of a pop-up hood. These simulations indicated that even though pop-up hood helped reducing the head injury

  14. A new wire chamber front-end system, based on the ASD-8 B chip

    Energy Technology Data Exchange (ETDEWEB)

    Kruesemann, B.A.M. E-mail: kruesemann@kvi.nl; Bassini, R.; Ellinghaus, F.; Frekers, D.; Hagemann, M.; Hannen, V.M.; Heynitz, H. von; Heyse, J.; Rakers, S.; Sohlbach, H.; Woertche, H.J

    1999-07-11

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  15. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  16. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  17. Investigation of characteristics and radiation hardness of the Beetle 1.0 front-end chip

    CERN Document Server

    Van Bakel, N; Jans, E; Klous, S; Verkooijen, H

    2001-01-01

    Noise characteristics of the Beetle 1.0 front-end chip have been investigated as a function of input capacitance. Values for the equivalent noise charge and ballastic deficit have been extracted. Amplification and pulse shape have been studied by varying the bias settings over a wide range. Results are compared with simulations that include realistic impedances at the input and output. The chip has been subjected to 10 Mrad of radiation. Subsequently, its behaviour is measured again and compared to that preceeding the irradiation. Observed radiation damage effects are discussed.

  18. The ALICE HMPID on-detector front-end and readout electronics

    CERN Document Server

    Santiard, Jean-Claude

    2004-01-01

    In the ALICE HMPID detector, Cherenkov photons are localised by measuring the charge induction on a MWPC cathode segmented into pads. Two ASICs have been developed: the Gassiplex07-3, which is an analogue 16-channels multiplexed front-end circuit dedicated to the readout of gaseous detector and the Dilogic-3, a sparse data scan digital processor. The combination of multiplexed and parallel- pipelined architecture allows to store several events between two L2 trigger and to transfer the 32-bits data words at a rate of 80 Mbytes per second through an optical data link.

  19. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  20. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  1. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  2. How can HR practices support front-end innovation and increase the innovativeness of companies?

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Andersen, Torben

    2014-01-01

    to be reinterpreted in a context of heterogeneity and polyvalence. Finally performance management and talent management should play a greater role in emphasising exclusive values and rational goal-oriented behaviour among employees, compared to the more inclusive mainstream values that characterise much HRM......This theoretical review is investigating how selected HR practices can help overcome the challenges companies face in establishing a basis for continuous innovation and thereby economic performance. In particular, the front end of innovation is being emphasised as a key element in companies...

  3. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2017-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  4. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives...

  5. Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

    Science.gov (United States)

    Prokop, Norman; Krasowski, Michael

    2013-01-01

    This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

  6. Design and implementation of a 5GHz radio front-end module

    OpenAIRE

    Backström, Anders; Ågesjö, Mats

    2004-01-01

    The overall goal of this diploma work is to produce a design of a 5 GHz radio frontend using Agilent Advanced Design System (ADS) and then build a working prototype. Using this prototype to determine if RF circuits at 5 GHz can be successfully produced using distributed components on a laminate substrate. The design process for the radio front-end consists of two stages. In the first stage the distributed components are designed and simulated, and in the second stage all components are merge...

  7. Performance of a 128 channel analogue front-end chip for read-out of Si strip detector modules for LHC experiments

    CERN Document Server

    Chesi, Enrico Guido; Cindro, V; Dabrowski, W; Ferrère, D; Kramberger, G; Kaplon, J; Lacasta, C; Lozano-Bahilo, J; Mikuz, M; Morone, C; Roe, S; Szczygiel, R; Tadel, M; Weilhammer, Peter; Zsenei, A

    2000-01-01

    We present a 128-channel analogue front-end chip, SCT128A-HC, for readout of silicon strip detectors employed in the inner tracking detectors of the LHC experiment. The chip is produced in the radiation hard DMILL technology. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in details in the test bench and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A-HC chips has been built and tested successfully in the lab with beta particles as well as in the test beam. The results concerning the signal-to-noise ratio, noise occupancy, efficiency and spatial resolution are presented. The radiation hardness issues are discussed. (5 refs).

  8. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  9. Test-beam activities and results for the ATLAS ITk pixel detector

    CERN Document Server

    Bisanz, Tobias; The ATLAS collaboration

    2017-01-01

    The Phase-II upgrade of the LHC will result in an increase of the instantaneous luminosity up to about $5\\times10^{34}~\\text{cm}^{-2}\\text{s}^{-1}$. To cope with the resulting challenges the current Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) system. The Pixel Detector will have to deal with occupancies of about 300~hits/FE/s as well as a fluence of $2\\times10^{16}~\\text{n}_\\text{eq}\\text{cm}^{-2}$. Various sensor layouts are under development, aiming at providing a high performance, cost effective pixel instrumentation to cover an active area of about $10~\\text{m}^2$. These range from thin planar silicon, over 3D silicon, to active CMOS sensors.\\par After extensive characterization of the sensors in the lab, their charge collection properties and hit efficiency are measured in common testbeam campaigns, which provide valuable feedback for improvements of the layout. Testbeam measurements of the final prototypes will be used for the decision of which sensor types will be installed in...

  10. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  11. BORA a front end board, with local intelligence, for the RICH detector of the Compass collaboration

    CERN Document Server

    Baum, G; Bradamante, Franco; Bressan, A; Colavita, A A; Crespo, M; Costa, S; Dalla Torre, S; Fauland, P; Finger, M H; Fratnik, Fabio; Giorgi, M A; Gobbo, B; Grasso, A; Lamanna, M; Martin, A; Menon, G I; Panzieri, D; Schiavon, R P; Tessarotto, F; Zanetti, A M

    1999-01-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as to be part of a computer network that connects several similar boards of the detector with a PC...

  12. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  13. Numerical study of a magnetically insulated front-end channel for a neutrino factory

    Directory of Open Access Journals (Sweden)

    Diktys Stratakis

    2011-01-01

    Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

  14. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  15. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  16. The TOTEM front end driver, its components and applications in the TOTEM experiment

    CERN Document Server

    Antchev G; Barney D; Reynaud S; Snoeys W; Vichoudis P

    2007-01-01

    The TOTEM Front End Driver, so-called TOTFED, receives and handles trigger building and tracking data from the TOTEM detectors, and interfaces to the global trigger and data acquisition systems. The TOTFED is based on the VME64x standard and has deliberately been kept modular. It is very flexible and programmable to deal with the different TOTEM sub-detectors and possible evolution of the data treatment and trigger algorithms over the duration of the experiment. The main objectives for each unit are to acquire ondetector data from up to 36 optical links, to perform fast data treatment (reduction, consistency checking, etc.), to transfer it to the next level of the system (via the Slink64 interface), and to store data on request for slow spy readout via VME64x or USB2.0. The TOTFED is fully compatible with CMS and permits TOTEM to run both standalone and together with CMS. The TOTEM Front End Driver, its components and applications in the TOTEM experiment are presented in this paper.

  17. Upgrades of the ALICE TPC Front-End Electronics for Long Shutdown 1 and 2

    CERN Document Server

    Velure, Arild

    2015-01-01

    This paper presents the front-end electronics upgrades of the ALICE Time Projection Chamber detector for the coming years, with a focus on the upgrades for Long Shutdown 2. The Large Hadron Collider is currently in Long Shutdown 1 following a successful first run, and upgrades of the detectors are underway to support the higher particle interaction rates planned for the next run. For the Time Projection Chamber, the increase in data due to the higher interaction rate and higher energy will cause a bottleneck in the Readout Control Unit and a new board is in development which increases the data-link speed to the back-end. Another more general upgrade of the ALICE experiment is planned for Long Shutdown 2, foreseen to start in 2018. In this case the goal is to cope with an even higher interaction rate of 50 kHz for Pb-Pb collisions. The present Multi Wire Proportional Chambers of the Time Projection Chamber will then be replaced by Gas Electron Multiplier technology. At the same time, the front-end electronics ...

  18. A low power dual-band multi-mode RF front-end for GNSS applications

    Science.gov (United States)

    Hao, Zhang; Zhiqun, Li; Zhigong, Wang

    2010-11-01

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  19. An ISM 2.4 GHz low power low-IF RF receiver front-end

    Science.gov (United States)

    Heping, Ma; Hua, Xu; Bei, Chen; Yin, Shi

    2015-08-01

    This paper describes the implementation of an RF receiver front-end for the 2.4 GHz industrial scientific medical band under TSMC 0.13 μm CMOS technology; it comprises a low noise amplifier (LNA) which uses an added gate-source capacitor for low power performance and a dual-converter composed of a single-balanced active RF mixer and double-balanced passive IF mixer. Dual-down-conversion technique is used for reducing power. A 2.4 GHz low power low-IF RF receiver front-end is proposed. An LNA for rejecting image signal, an inductor-capacitor (LC) tank is used in series with source of input-stage transistor of the RF mixer, and combined with the LC load of the LNA, 30-dB image rejection is realized. Fabricated in a 0.13 μm CMOS process, the proposed chip occupies 0.42 mm2 area, achieves 4 dB noise figure, -22 dBm IIP3 and 37 dB voltage gain dissipating only 4.2-mW under 1.2-V supply.

  20. Front-End Data Reduction in Computer-Aided Diagnosis of Mammograms: A Pilot Study

    Energy Technology Data Exchange (ETDEWEB)

    Gleason, S.S.; Nishikawa, R.M.; Sari-Sarraf, H.

    1999-02-20

    This paper presents the results of a pilot study whose primary objective was to further substantiate the efficacy of front-end data reduction in computer-aided diagnosis (CAD) of mammograms. This concept is realized by a preprocessing module that can be utilized at the front-end of most mammographic CAD systems. Based on fractal encoding, this module takes a mammo-graphic image as its input and generates, as its output, a collection of subregions called focus-of-attention regions (FARs). These FARs contain all structures in the input image that appear to be different from the normal background tissue. Subsequently, the CAD systems need only to process the presented FARs, rather than the entire input image. This accomplishes two objectives simultaneously: (1) an increase in throughput via a reduction in the input data, and (2) a reduction in false detections by limiting the scope of the detection algorithms to FARs only. The pilot study consisted of using the preprocessing module to analyze 80 mammographic images. The results were an average data reduction of 83% over all 80 images and an average false detection reduction of 86%. Furthermore, out of a total of 507 marked microcalcifications, 467 fell within FW, representing a coverage rate of 92%.

  1. Characterisation of the VMM3 Front-end read-out ASIC

    CERN Document Server

    Bartels, Lara Maria

    2018-01-01

    This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

  2. Front end with offset-free symmetrical current source optimized for time domain impedance spectroscopy.

    Science.gov (United States)

    Pliquett, Uwe; Schönfeldt, Markus; Barthel, Andreas; Frense, Dieter; Nacke, Thomas; Beckmann, Dieter

    2011-07-01

    Fast impedance measurements are often performed in time domain utilizing broad bandwidth excitation signals. Other than in frequency domain measurements harmonic distortion cannot be compensated which requires careful design of the analog front end. In order to minimize the influence of electrode polarization and noise, especially in low-frequency measurements, current injection shows several advantages compared to voltage application. Here, we show an active front end based on a voltage-controlled current source for a wide range of impedances. Using proper feedback, the majority of the parasitic capacitances are compensated. The bandwidth ranges from dc to 20 MHz for impedance magnitude below 5 kΩ. The output is a symmetric signal without dc-offset which is accomplished by combination of a current conveyor and a voltage inverter. An independent feedback loop compensates the offset arising from asymmetries within the circuitry. We focused especially on the stability of the current source for usage with small metal electrodes in aqueous solutions. At the monitor side two identical, high input impedance difference amplifiers convert the net current through the object and the voltage dropping across into a 50 Ω symmetric output. The entire circuitry is optimized for step response making it suitable for fast time domain measurements.

  3. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  4. An instrumentation amplifier as a front-end for a four-electrode bioimpedance measurement.

    Science.gov (United States)

    Zagar, T; Krizaj, D

    2007-08-01

    The performance of a monolithic instrumentation amplifier used as an interface for a four-electrode bioimpedance measurement is examined with a commercially available impedance meter based on an auto-balancing bridge. The errors due to particularities in the input stage of the impedance meter, when used without a front-end, were several orders of magnitude higher than the measured quantity. The analysis was performed on an electrical circuit model of the skin and electrodes over a frequency range of 20 Hz to 1 MHz. The achieved accuracy with balanced electrode impedances for the frequencies up to 100 kHz can be below 0.2% for impedance magnitude and 0.1 degrees for impedance phase, which is within the specified basic accuracy range of the LCR-meter used for the measurements. At frequencies above 100 kHz the errors are increasing and are higher than the LCR-meter's basic accuracy. This study indicates that use of an instrumentation amplifier as a front-end with the particular LCR-meter can significantly improve the measurement accuracy of the four-electrode bioimpedance measurement at low frequencies.

  5. Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Puellen, Lukas

    2015-02-10

    In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

  6. The next generation Front-End Controller for the Phase-I Upgrade of the CMS Hadron Calorimeters

    Science.gov (United States)

    Costanza, F.; Behrens, U.; Campbell, A.; Karakaya, T.; Martens, I.; Melzer-Pellmann, I. A.; Sahin, M. O.

    2017-03-01

    The next generation Front-End Controller (ngFEC) is the system responsible for slow and fast control within the Phase-I Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μTCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the front-end electronics through six GBT links. The latency of the fast control signals is fixed across power cycles. Even if the direct link to a front-end module is broken, a redundancy scheme ensures a successful communication using the link to the neighboring front-end module. Thanks to the ngFEC all front-end modules can be remotely programmed using the JTAG standard protocol. The CCM server software interfaces the ngFEC to the Detector Control System which constantly monitors voltages and temperatures on the front-end electronics. This document reviews the characteristics and the development status of the ngFEC.

  7. Test beam results of a depleted monolithic active pixel sensor (DMAPS) prototype

    Energy Technology Data Exchange (ETDEWEB)

    Obermann, Theresa; Hemperek, Tomasz; Huegging, Fabian; Krueger, Hans; Wermes, Norbert [Bonn Univ. (Germany); Schwenker, Benjamin [Goettingen Univ. (Germany); Collaboration: ATLAS Pixel-Collaboration

    2016-07-01

    New monolithic detector concepts are currently being explored for future particle physics experiments, in particular for the upgrade of the ATLAS detector. Common to monolithic pixel detectors is the integration of the front-end circuitry and the sensor on the same silicon substrate. The DMAPS concept makes use of high resistive silicon as substrate. It enables the application of a high bias voltage to create a drift field for the charge collection in the sensor part as well as the full usage of CMOS logic in the same piece of silicon. DMAPS prototypes from several foundries are available since three years and have been extensively characterized in the lab. In this talk, results of test beam campaigns, with neutron irradiated prototypes implemented in the ESPROS process, are presented.

  8. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371978; Gößling, Claus; Pernegger, Heinz

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ...

  9. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-09-02

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  10. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  11. Development of pixel detectors for the IBL and HL-LHC ATLAS experiment upgrade

    CERN Document Server

    Baselga Bacardit, Marta

    2016-03-18

    This thesis presents the development of advanced silicon technology detectors fabricated at CNM-Barcelona for High Energy Physics (HEP) experiments. The pixel size of the tracking silicon detectors for the upgrade of the HL-LHC will have to decrease in size in order to enhance the resolution in position for the measurements and they need to have lower occupancy for the electronics. The future experiments at CERN will cope with fuences up to 2 x 10^^16 neq/cm2, and the smaller 3D silicon detectors will have less trapping of the electron-holes generated in the bulk leading to a better performance under high radiation environment. This thesis studies silicon detectors fabricated at CNM-Barcelona applied to HEP experiments with two different kinds of novel technologies: 3D and Low Gain Avalanche Detectors (LGAD). The 3D detectors make it possible to reduce the size of the depleted region inside the detector and to work at lower voltages, whereas the LGAD detectors have an intrinsic gain which increases the collec...

  12. Stray light assessment and mitigation for the DESI front-end optical system

    Science.gov (United States)

    Miller, Timothy N.; Lampton, Michael; Besuner, Robert W.; Sholl, Michael J.; Liang, Ming; Ellis, Scott

    2016-08-01

    The Dark Energy Spectroscopic Instrument (DESI) is under construction to measure the expansion history of the Universe, using the Baryon Acoustic Oscillation technique and the growth of structure using redshift-space distortions (RSD). The spectra of 40 million galaxies over 14000 square degrees will be measured during the life of the experiment. A new prime focus corrector for the KPNO Mayall telescope will deliver light to 5000 fiber optic positioners. The fibers in turn feed ten broad-band spectrographs. We will describe modeling and mitigation of stray light within the front end of DESI, consisting of the Mayall telescope and the corrector assembly. This includes the creation of a stray light model, quantitative analysis of the unwanted light at the corrector focal surface, identification of the main scattering sources, and a description of mitigation strategies to remove the sources.

  13. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  14. Managing inter-firm collaboration in the fuzzy front-end

    DEFF Research Database (Denmark)

    Jørgensen, Jacob; Bergenholtz, Carsten; Goduscheit, René Chester

    2011-01-01

    Literature on innovation emphasises the potential for organisations to collaborate and network instead of carrying out innovation individually. Integrating suppliers, customers and other organisations into the innovation process is perceived as a key to success in innovation management (Chesbrough......, 2003). Furthermore, the management of the initial phase of the innovation process has proven vital to the overall innovation success (Kim and Wilemon, 2002a,b). Although the merits of network-based innovations are widely acknowledged, the managerial challenges of the initial integration of external...... organisations in an innovation network are somewhat neglected in the literature. The aim of this paper is hence to address the challenges that an organisation faces when integrating a plurality of suppliers, customers and other organisations into the Fuzzy Front End of the innovation process....

  15. An optimized analog to digital converter for WLAN analog front end

    Science.gov (United States)

    Mao, Ye; Yumei, Zhou; Bin, Wu; Jianhua, Jiang

    2012-04-01

    A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multi-bit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 μm 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz.

  16. A full custom analog front-end for long-time ECG monitoring.

    Science.gov (United States)

    Wen, Meiying; Cheng, Yayu; Li, Ye

    2013-01-01

    An analog front-end (AFE) used in portable electrocardiogram (ECG) monitoring devices is proposed. This AFE has included all necessary functions for the commercial applications. The core circuit consists of the instrumentation amplifier (IA), a 2(nd) order Butterworth low pass filter, and the second amplifying stage. The driven-right-leg circuit is integrated in the IA to effectively suppress the common mode interference. And the power management circuits provide a stable supply voltage, bias current and reference voltage for the other circuits. To guarantee the validity of the continuous monitoring data, the leadoff monitoring circuit is developed to monitor the connection of the leads. The chip is taped out with SMIC 0.18 µm CMOS process, and the measured results show that the common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) achieve 75 dB and 90dB respectively, and the equivalent input referred noise is 12 µV.

  17. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... recommendations for the manufacturer to improve the innovation process and enhance the chances of success. However, the waist majority of these projects belong to an intra-organizational paradigm where the manufacturer is considered to be the only part involved in the process, controlling and influencing...... and improved products and processes. Formal innovation partnerships has been researched widely through the past 45[jhj1]  years e.g. (Bart Nooteboom 2003;Faems, Van Looy, & Debackere 2005;Hagedoorn 2002;Powell, Koput, & Smith-Doerr 1996b). The research has provided useful insights in the dynamics...

  18. Integration and alignment through mechanical measurements: the example of the ESPRESSO front-end units

    Science.gov (United States)

    Aliverti, Matteo; Pariani, Giorgio; Moschetti, Manuele; Riva, Marco

    2016-08-01

    Traditional techniques usually rely on optical feedback to align optical elements over all the degrees of freedom needed. This strongly iterative process implies the use of bulky and/or flexible adjustable mountings. Another solution under study consists in the characterization of every optomechanical elements and the integration of the parts without any optical feedback. The characterization can be performed using different 3D Coordinate Measuring Machines (like Laser Tracker, Articulated Arms and Cartesian ones) and referencing different parts like the optomechanical mounts or the optical surfaces. The alignment of the system is done adjusting the six degrees of freedom of every element with metallic shims. Those calibrated elements are used to correct the interfaces position of the semikinematic system composed by 3 screws and 3 pins. In this paper, the integration and alignment of the ESPRESSO Front End Units (FEUs) will be used as pathfinder to test different alignment methods and evaluate their performances.

  19. Conductive Cooling of SDD and SSD Front-End Chips for ALICE

    CERN Document Server

    Van den Brink, A; Daudo, F; Feofilov, G A; Godisov, O N; Giraudo, G; Igolkin, S N; Kuijer, P; Nooren, G J L; Swichev, A; Tosello, F

    2001-01-01

    We present analysis, technology developments and test results of the heat drain system of the SDD and SSD front-end electronics for the ALICE Inner Tracker System (ITS). Application of super thermoconductive carbon fibre thin plates provides a practical solution for the development of miniature motherboards for the FEE chips situated inside the sensitive ITS volume. Unidirectional carbon fibre motherboards of 160 -300 micron thickness ensure the mounting of the FEE chips and an efficient heat sink to the cooling arteries. Thermal conductivity up to 1.3 times better than copper is achieved while preserving a negligible multiple scattering contribution by the material (less than 0.15 percent of X/Xo).

  20. First commissioning experience with the LINAC4 3 MeV front-end at CERN

    CERN Document Server

    Lallement, J B; Bellodi, G; Comblin, J F; Dimov, V A; Granemann Souza, E; Lettry, J; Lombardi, A M; Midttun, O; Ovalle, E; Raich, U; Roncarolo, F; Rossi, C; Sanchez Alvarez, R; Scrivens, C A; Valerio-Lizarraga, C A; Vretenar, M; Yarmohammadi Satri, M

    2013-01-01

    Linac4 is a normal-conducting 160 MeV H- linear accelerator presently under construction at CERN. It will replace the present 50 MeV Linac2 as injector of the proton accelerator complex as part of a project to increase the LHC luminosity. The Linac front-end, composed of a 45 keV ion source, a Low Energy Beam Transport (LEBT), a 352.2 MHz Radio Frequency Quadrupole (RFQ) and a Medium Energy Beam Transport (MEBT) housing a beam chopper, have been commissioned at the 3 MeV test stand during the first half of 2013. The status of the installation and the results of the first commissioning stage are presented in this paper.