WorldWideScience

Sample records for atlas pixel front-end

  1. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  2. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  3. Pixel front-end development in 65 nm CMOS technology

    CERN Document Server

    Havránek, M; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed.

  4. Total Ionising Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00439451

    2016-01-01

    The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the LV current, produced by the FE-I4 chip, was observed. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations. This report presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

  5. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  6. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  7. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  8. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  9. Data acquisition at the front-end of the Mu3e pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

    2016-07-01

    The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

  10. 65 nm CMOS analog front-end for pixel detectors at the HL-LHC

    Science.gov (United States)

    Gaioni, L.; De Canio, F.; Manghisoni, M.; Ratti, L.; Re, V.; Traversi, G.

    2016-02-01

    This work is concerned with the design and the experimental characterization of analog front-end electronics conceived for experiments with unprecedented particle rates and radiation levels at future high-energy physics colliders. A prototype chip integrating different test structures has been submitted in the framework of the CHIPIX65 project. These structures are standalone channels for the readout of hybrid pixels, featuring a charge sensitive preamplifier as the first stage of the readout chain, a high-speed comparator and a circuit for fine threshold tuning. The paper thoroughly discusses the results, mainly focused on the charge sensitive amplifier, coming from the characterization of the submitted test structures.

  11. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  12. ATLAS ITk Pixel detector

    CERN Document Server

    Gemme, Claudia; The ATLAS collaboration

    2016-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

  13. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  14. Study of the performance of ATLAS prototype detectors using analogue LHC front-end electronics

    CERN Document Server

    Riedler, P; Kaplon, J; Weilhammer, Peter

    2002-01-01

    The silicon strip detectors in the ATLAS experiment at LHC will be exposed to very high hadron fluences. In order to study the radiation damage effects ATLAS prototype detectors and small test detectors were irradiated to a fluence of 3 * 10/sup 14/ 24 GeV protons/cm/sup 2/. After irradiation, the detectors were annealed at 25 degrees C to simulate the damage foreseen after 10 years of ATLAS operation. The detectors were then connected to the SCT32A analogue front-end chips and tested with a /sup 106/Ru source. The performance of the irradiated detectors was compared to non-irradiated detectors from the same batch. The charge collection efficiency is discussed taking into account the electronic response of the readout chip and the ballistic deficit. (10 refs).

  15. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  16. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  17. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  18. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  20. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    Liu, Tiankuan; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  1. Development of ATLAS Liquid Argon Calorimeter front-end electronics for the HL-LHC

    Science.gov (United States)

    Liu, T.

    2017-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5–7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter cells at 40–80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented in this paper.

  2. Pixel front-end with synchronous discriminator and fast charge measurement for the upgrades of HL-LHC experiments

    Science.gov (United States)

    Monteil, E.; Demaria, N.; Pacher, L.; Rivetti, A.; Da Rocha Rolo, M.; Rotondo, F.; Leng, C.

    2016-03-01

    The upgrade of the silicon pixel sensors for the HL-LHC experiments requires the development of new readout integrated circuits due to unprecedented radiation levels, very high hit rates and increased pixel granularity. The design of a very compact, low power, low threshold analog very front-end in CMOS 65 nm technology is described. It contains a synchronous comparator which uses an offset compensation technique based on storing the offset in output. The latch can be turned into a local oscillator using an asynchronous logic feedback loop to implement a fast time-over-threshold counting. This design has been submitted and the measurement results are presented.

  3. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  4. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet...

  5. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    CERN Document Server

    Alves, J; The ATLAS collaboration; Hee Yeun, K; Minashvili, I; Moreno, P; Qin, G; Reed, R; Schettino, V; Shalyugin, A; Solans, C; Sousa, J; Usai, G; Valero, A

    2013-01-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicate

  6. Towards Optimal Filtering on ARM for ATLAS Tile Calorimeter Front-End Processing

    Science.gov (United States)

    Cox, Mitchell A.

    2015-10-01

    The Large Hadron Collider at CERN generates enormous amounts of raw data which presents a serious computing challenge. After planned upgrades in 2022, the data output from the ATLAS Tile Calorimeter will increase by 200 times to over 40 Tb/s. Advanced and characteristically expensive Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs) are currently used to process this quantity of data. It is proposed that a cost- effective, high data throughput Processing Unit (PU) can be developed by using several ARM System on Chips in a cluster configuration to allow aggregated processing performance and data throughput while maintaining minimal software design difficulty for the end-user. ARM is a cost effective and energy efficient alternative CPU architecture to the long established x86 architecture. This PU could be used for a variety of high-level algorithms on the high data throughput raw data. An Optimal Filtering algorithm has been implemented in C++ and several ARM platforms have been tested. Optimal Filtering is currently used in the ATLAS Tile Calorimeter front-end for basic energy reconstruction and is currently implemented on DSPs.

  7. Irradiation Studies of Multimode Fibres for use in ATLAS Front-end Links

    CERN Document Server

    Mahout, G; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, RJ; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Pearce, M; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, AR; Wilson, J A; Ye, J

    1999-01-01

    The radiation tolerance of three multimode optical fibres has been investigatedto establish their suitability for use in the front-end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of $\\sim$0.05~dB/mat 330~kGy(Si) and 1$\\times$10$^{15}$~n(1~MeV~Si)/cm$^{2}$ and is suitablefor use with the inner detector links which operate at 40-80~Mb/s. A graded-indexfibre with a predominantly germanium doped core exhibits an induced attenuation of $\\sim$0.1~dB/mat 800~Gy(Si) and 2$\\times$10$^{13}$~n(1~MeV~Si)/cm$^{2}$ and is suitable for the calorimeterlinks which operate at 1.6~Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower.

  8. Irradiation studies of multimode optical fibres for use in ATLAS front-end links

    CERN Document Server

    Mahout, G; Andrieux, M L; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, R James; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, A R; Wilson, J A; Ye, J

    2000-01-01

    The radiation tolerance of three multimode optical fibres has been investigated to establish their suitability for the use in the front- end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of ~0.05 dB/m at 330 kGy (Si) and 1*10/sup 15/ n(1 MeV Si)/cm/sup 2/ and is suitable for use with the inner detector links which operate at 40-80 Mb/s. A graded- index fibre with a predominantly germanium-doped core exhibits an induced attenuation of ~0.1 dB/m at 800 Gy(Si) and 2*10/sup 13/ n(1 MeV Si)/cm/sup 2/ and is suitable for the calorimeter links which operate at 1.6 Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower. (30 refs).

  9. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  10. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  11. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  12. Pixel readout chip for the ATLAS experiment

    CERN Document Server

    Ackers, M; Blanquart, L; Bonzom, V; Comes, G; Fischer, P; Keil, M; Kühl, T; Meuser, S; Delpierre, P A; Treis, J; Raith, B A; Wermes, N

    1999-01-01

    Pixel detectors with a high granularity and a very large number of sensitive elements (cells) are a very recent development used for high precision particle detection. At the Large Hadron Collider LHC at CERN (Geneva) a pixel detector with 1.4*10/sup 8/ individual pixel cells is developed for the ATLAS detector. The concept is a hybrid detector. Consisting of a pixel sensor connected to a pixel electronics chip by bump and flip chip technology in one-to-one cell correspondence. The development and prototype results of the pixel front end chip are presented together with the physical and technical requirements to be met at LHC. Lab measurements are reported. (6 refs).

  13. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  14. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    INSPIRE-00218666

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with X-ray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  15. Front-end electronics in a 65 nm CMOS process for high density readout of pixel sensors

    Science.gov (United States)

    Gaioni, Luigi; Manghisoni, Massimo; Ratti, Lodovico; Re, Valerio; Traversi, Gianluca

    2011-09-01

    In future high energy physics experiments (HEP), readout integrated circuits for vertexing and tracking applications will be implemented by means of CMOS devices belonging to processes with minimum feature size in the 100 nm span. In these nanoscale technologies the impact of new dielectric materials and processing techniques on the analog behavior of MOSFETs has to be carefully evaluated. This paper is concerned with the study of the analog properties, in particular in terms of noise performance and radiation hardness, of MOSFET devices belonging to a 65 nm CMOS low power technology. The behavior of the 1/ f and white noise terms is studied as a function of the main device parameters before and after exposure to 10 keV X-rays and 60Co γ-rays. A prototype chip designed in a 65 nm CMOS process including deep n-well MAPS structures and a fast front-end conceived for the readout of high-resistivity pixel sensors will be introduced.

  16. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  17. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 During the first year of the IBL operation in 2015 a significant increase of the LV current of the front-end chip and the detuning of its parameters (threshold and time-over- threshold) have been observed in relation to the received TID. In this talk , the TID effects in the FE-I4 chip are reported based on studies performed in the laboratory using X-ray and proton irradiation sources for various temperature and irradiation intensity conditions. Based on these results, an operation guideline of the IBL detector is presented.

  18. A Simulation of the Front End Signal Digitization for the ATLAS Muon Spectrometer thin RPC trigger upgrade project

    Science.gov (United States)

    Meng, Xiangting; Chapman, John; Levin, Daniel; Dai, Tiesheng; Zhu, Junjie; Zhou, Bing; Um Atlas Group Team

    2016-03-01

    The ATLAS Muon Spectrometer Phase-I (and Phase-II) upgrade includes the BIS78 muon trigger detector project: two sets of eight very thin Resistive Place Chambers (tRPCs) combined with small Monitored Drift Tube (MDT) chambers in the pseudorapidity region 1Phase-I operation, a stringent latency requirement of 43 bunch crossings (1075 ns) is imposed. The latency budget for the front end digitization must be kept to a minimal value, ideally less than 350 ns. We conducted detailed HPTDC latency simulations using the Behavioral Verilog code from the CERN group. We will report the results of these simulations run for the anticipated detector operating environment and for various HPTDC configurations.

  19. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  20. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    The calibration of the ATLAS Pixel detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied together to chips with different characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  1. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter

    CERN Document Server

    Dressnandt, N; Rescia, S; Vernon, E

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at the Large Hadron Collider upgrade (sLHC). IBM’s 8WL 130nm SiGe process was chosen for it’s radiation tolerance, low noise bipolar NPN devices, wide voltage rand and potential use in other sLHC detector subsystems. Although the requirements for the final design can not be set at this time, the prototype was designed to accommodate a 16 bit dynamic range. This was accomplished by using a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of the Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier which eases the input voltage noise requirement on the shaper. Each shaper stage is designed as a cascaded differential operational amplifier doublet with a common...

  2. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr

    CERN Document Server

    Rescia, S; Newcomer, F M; Dressnandt, N

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper with a (RC)2 – CR response to replace the existing ATLAS Liquid Argon readout for use at SLHC. IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished by utilization of a single stage, low noise, wide dynamic range preamp connected to a dual range shaper. The low noise of the preamp (~.01nA / √Hz) is achieved by utilizing the process Silicon Germanium bipolar transistors. The relatively high voltage rating of the npn transistors is exploited to allow a gain of 650V/A. With this gain the equivalent input voltage noise requirement on the shaper to about 2.2nV/ √Hz. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. The shaper outputs are designed to be compatible with the 130nm CMOS ADC being develo...

  3. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    Science.gov (United States)

    Li, H. S.; Jiang, X. S.; Liu, G.; Wang, N.; Sheng, H. Y.; Zhuang, B. A.; Zhao, J. W.

    2012-03-01

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  4. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  5. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  6. Development of a test beam telescope based on the ATLAS front end ASIC FE-I4

    CERN Document Server

    Obermann, Theresa

    2012-01-01

    A beam telescope using FE-I4 readout chip based pixel modules of the ATLAS IBL upgrade was set up and tested. The data acquisition as well as the analysis were adopted from an already existing framework developed specifically for that purpose, namely EUDAQ and EUTelescope. By adding one FE-I4 based reference plane to the EUDET telescope, a region of interest trigger was implemented into the existing framework. Tests with this trigger were done using both the FE-I4 beam telescope as well as the EUDET telescope. A commissioning of the new trigger was done with a DEPFET sensor as device under test, showing that the data acquisition can be improved in terms of track efficiency to more than 80 %.

  7. Improvement of Event Synchronization in the ATLAS Pixel Readout Development

    Science.gov (United States)

    Adams, Logan; Atlas Collaboration

    2017-01-01

    As the LHC continues in Run2, the B-Layer still uses the Atlas-SiROD Pixel readout system initially developed for Run 1. The higher luminosity occurring during Run 2 results in higher occupancy causing increased desynchronization errors in the Pixel Readout. In order to ensure lasting operation of the B-Layer until it is replaced after Run 3, changes were made to the firmware and software to add debug capabilities to identify when the errors are crossing certain thresholds and change the internal control logic accordingly. These features also allow for better debugging of the Event Counter Reset addition to the firmware. This talk will focus on the features implemented and measurements to demonstrate the positive impact on the Pixel DAQ system. A Pixel front-end chip emulator which can be used for readout system development beyond Run 3 will also be discussed. Presenter is Logan Adams, University of Washington.

  8. The ATLAS tracker Pixel detector for HL-LHC

    CERN Document Server

    Gemme, Claudia; The ATLAS collaboration

    2017-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current Inner Detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation levels are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLAS Pixel detector developments as well as the various layout options are reviewed.

  9. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  10. Overview of the ATLAS Insertable B-Layer Pixel Detector

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2011-01-01

    ATLAS currently develops a new pixel detector for the first upgrade of its tracking system: The ATLAS Insertable B-Layer Pixel detector (IBL). The new layer will be inserted between the inner most layer of the current pixel detector and a new beam pipe. The sensors are placed at a radius of 3.4cm. The expected high radiation levels and high hit occupancy require new developments for front-end chip and the sensor which can stand radiation levels beyond 5E15 neq/cm2. ATLAS has developed the new FEI4 and new silicon sensors to be used as pixel modules. Furthermore a new lightweight support and cooling structure was developed, which minimizes the overall radiation and allows detector cooling with CO2 at -40C coolant temperature. Currently the overall integration and installation procedure is being developed and test ready for installation in ATLAS in 2013. The presentation summarizes the current state of development of IBL modules, first preliminary test results of the new chip with new sensors, the construction ...

  11. Calibration analysis software for the ATLAS Pixel Detector

    Science.gov (United States)

    Stramaglia, Maria Elena

    2016-07-01

    The calibration of the ATLAS Pixel Detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel Detector scans and analyses is called calibration console. The introduction of a new layer, equipped with new FE-I4 chips, required an update of the console architecture. It now handles scans and scan analyses applied together to chips with different characteristics. An overview of the newly developed calibration analysis software will be presented, together with some preliminary results.

  12. Operational Experience with the ATLAS Pixel Detector at LHC

    CERN Document Server

    Keil, M

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus crucial for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via front-end chips bump-bonded to 1744 n-on-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, detector performance and measurements of radiation damage. The detector performance is excellent: more than 95% of the pixels are operational, noise occupancy and hit efficiency exceed the des...

  13. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  14. The ATLAS Insertable B-Layer Pixel Detector

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2011-01-01

    ATLAS currently develops a new pixel detector for the first upgrade of its tracking system: The ATLAS Insertable B-Layer Pixel detector (IBL). The new layer will be inserted between the inner most layer of the current pixel detector and a new beam pipe. The sensors are placed at a radius of 3.4 cm. The expected high radiation levels and high hit occupancy require new developments for front-end chip and sensors which can stand radiation levels beyond 5$ imes$10$^{15}$ n$_{eq}$/cm$^{2}$ . ATLAS has developed the new FEI4 chip and new silicon sensors to be used as pixel modules. Furthermore a new lightweight support and cooling structure was developed, which minimizes the overall radiation length and allows detector cooling with CO$_{2}$ at -40 $^{circ}$C coolant temperature. Currently the overall integration and installation procedure is being developed and tested ready for installation in 2013. The paper summarizes the current state of development of IBL modules, first preliminary test results of the new chip ...

  15. The ATLAS Silicon Pixel Sensors

    CERN Document Server

    Alam, M S; Einsweiler, K F; Emes, J; Gilchriese, M G D; Joshi, A; Kleinfelder, S A; Marchesini, R; McCormack, F; Milgrome, O; Palaio, N; Pengg, F; Richardson, J; Zizka, G; Ackers, M; Andreazza, A; Comes, G; Fischer, P; Keil, M; Klasen, V; Kühl, T; Meuser, S; Ockenfels, W; Raith, B; Treis, J; Wermes, N; Gössling, C; Hügging, F G; Wüstenfeld, J; Wunstorf, R; Barberis, D; Beccherle, R; Darbo, G; Gagliardi, G; Gemme, C; Morettini, P; Musico, P; Osculati, B; Parodi, F; Rossi, L; Blanquart, L; Breugnon, P; Calvet, D; Clemens, J-C; Delpierre, P A; Hallewell, G D; Laugier, D; Mouthuy, T; Rozanov, A; Valin, I; Aleppo, M; Caccia, M; Ragusa, F; Troncon, C; Lutz, Gerhard; Richter, R H; Rohe, T; Brandl, A; Gorfine, G; Hoeferkamp, M; Seidel, SC; Boyd, GR; Skubic, P L; Sícho, P; Tomasek, L; Vrba, V; Holder, M; Ziolkowski, M; D'Auria, S; del Papa, C; Charles, E; Fasching, D; Becks, K H; Lenzen, G; Linder, C

    2001-01-01

    Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to the attachment of the readout integrated circuit electronics is also desired.

  16. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  17. Test Beam Results of 3D Silicon Pixel Sensors for the ATLAS upgrade

    CERN Document Server

    Grenier, P; Barbero, M; Bates, R; Bolle, E; Borri, M; Boscardin, M; Buttar, C; Capua, M; Cavalli-Sforza, M; Cobal, M; Cristofoli, A; Dalla Betta, G F; Darbo, G; Da Via, C; Devetak, E; DeWilde, B; Di Girolamo, B; Dobos, D; Einsweiler, K; Esseni, D; Fazio, S; Fleta, C; Freestone, J; Gallrapp, C; Garcia-Sciveres, M; Gariano, G; Gemme, C; Giordani, M P; Gjersdal, H; Grinstein, S; Hansen, T; Hansen, T E; Hansson, P; Hasi, J; Helle, K; Hoeferkamp, M; Hugging, F; Jackson, P; Jakobs, K; Kalliopuska, J; Karagounis, M; Kenney, C; Köhler, M; Kocian, M; Kok, A; Kolya, S; Korokolov, I; Kostyukhin, V; Krüger, H; La Rosa, A; Lai, C H; Lietaer, N; Lozano, M; Mastroberardino, A; Micelli, A; Nellist, C; Oja, A; Oshea, V; Padilla, C; Palestri, P; Parker, S; Parzefall, U; Pater, J; Pellegrini, G; Pernegger, H; Piemonte, C; Pospisil, S; Povoli, M; Roe, S; Rohne, O; Ronchin, S; Rovani, A; Ruscino, E; Sandaker, H; Seidel, S; Selmi, L; Silverstein, D; Sjøbaek, K; Slavicek, T; Stapnes, S; Stugu, B; Stupak, J; Su, D; Susinno, G; Thompson, R; Tsung, J W; Tsybychev, D; Watts, S J; Wermes, N; Young, C; Zorzi, N

    2011-01-01

    Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable-B-Layer and High Luminosity LHC (HL-LHC)) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS Inner Detector solenoid field. Sensors were bump bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

  18. Test beam results of 3D silicon pixel sensors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Grenier, P., E-mail: grenier@slac.stanford.ed [SLAC National Accelerator Laboratory (United States); Alimonti, G. [INFN Sezione di Milano (Italy); Barbero, M. [Bonn University (Germany); Bates, R. [Glasgow University (United Kingdom); Bolle, E. [Oslo University (Norway); Borri, M. [University of Manchester (United Kingdom); Boscardin, M. [FBK-irst, Trento (Italy); Buttar, C. [Glasgow University (United Kingdom); Capua, M. [INFN Gruppo Collegato di Cosenza and Universita della Calabria (Italy); Cavalli-Sforza, M. [IFAE Barcelona (Spain); Cobal, M.; Cristofoli, A. [INFN Gruppo Collegato di Udine and Universita di Udine (Italy); Dalla Betta, G.-F. [INFN Gruppo Collegato di Trento and DISI Universita di Trento (Italy); Darbo, G. [INFN Sezione di Genova (Italy); Da Via, C. [University of Manchester (United Kingdom); Devetak, E.; DeWilde, B. [Stony Brook University (United States); Di Girolamo, B.; Dobos, D. [CERN (Switzerland); Einsweiler, K. [Lawrence Berkeley National Laboratory (United States)

    2011-05-11

    Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS inner detector solenoid field. Sensors were bump-bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

  19. Pixel architectures in a HV-CMOS process for the ATLAS inner detector upgrade

    Science.gov (United States)

    Degerli, Y.; Godiot, S.; Guilloux, F.; Hemperek, T.; Krüger, H.; Lachkar, M.; Liu, J.; Orsini, F.; Pangaud, P.; Rymaszewski, P.; Wang, T.

    2016-12-01

    In this paper, design details and simulation results of new pixel architectures designed in LFoundry 150 nm high voltage CMOS process in the framework of the ATLAS high luminosity inner detector upgrade are presented. These pixels can be connected to the FE-I4 readout chip via bump bonding or glue and some of them can also be tested without a readout chip. Negative high voltage is applied to the high resistivity (> 2 kΩ .cm) substrate in order to deplete the deep n-well charge collection diode, ensuring good charge collection and radiation tolerance. In these pixels, the front-end has been implemented inside the diode using both NMOS and PMOS transistors. The pixel pitch is 50 μm × 250 μm for all pixels. These pixels have been implemented in a demonstrator chip called LFCPIX.

  20. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  1. ATLAS Pixel Opto-Electronics

    CERN Document Server

    Arms, K E; Gan, K K; Holder, M; Jackson, P; Johnson, M; Kagan, H; Kass, R; Rahimi, A M; Roggenbuck, A; Rush, C; Schade, P; Smith, S; Ter-Antonian, R; Ziolkowski, M; Zoeller, M M

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 micron CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results of the performance of these chips, including irradiation with 24 GeV protons up to 61 Mrad (2.3 x 10e15 p/cm^2).

  2. Commissioning of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Golling, Tobias

    2008-09-01

    The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and summer 2008, and is ready for the imminent LHC turn-on. The highlights of the past and future commissioning activities of the ATLAS pixel system are presented.

  3. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  4. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  5. EXCALIBUR: a small-pixel photon counting area detector for coherent X-ray diffraction - Front-end design, fabrication and characterisation

    Science.gov (United States)

    Marchal, J.; Horswell, I.; Willis, B.; Plackett, R.; Gimenez, E. N.; Spiers, J.; Ballard, D.; Booker, P.; Thompson, J. A.; Gibbons, P.; Burge, S. R.; Nicholls, T.; Lipp, J.; Tartoni, N.

    2013-03-01

    Coherent X-ray diffraction experiments on synchrotron X-ray beamlines require detectors with high spatial resolution and large detection area. The read-out chip developed by the MEDIPIX3 collaboration offers a small pixel size of 55 microns resulting in a very high spatial resolution when coupled to a direct X-ray conversion segmented silicon sensor. MEDIPIX3 assemblies present also the advantages of hybrid pixel detectors working in single photon counting mode: noiseless imaging, large dynamic range, extremely high frame rate. The EXCALIBUR detector is under development for the X-ray Coherence and Imaging Beamline I13 of the Diamond Light Source. This new detector consists of three modules, each with 16 MEDIPIX3 chips which can be read-out at 100 frames per second in continuous mode or 1000 frames per second in burst mode. In each module, the sensor is a large single silicon die covering 2 rows of 8 individual MEDIPIX3 read-out chips and provides a continuous active detection region within a module. Each module includes 1 million solder bumps connecting the 55 microns pixels of the silicon sensor to the 55 microns pixels of the 16 MEDIPIX3 read-out chips. The detection area of the 3-module EXCALIBUR detector is 115 mm × 100 mm with a small 6.8 mm wide inactive region between modules. Each detector module is connected to 2 FPGA read-out boards via a flexi-rigid circuit to allow a fully parallel read-out of the 16 MEDIPIX3 chips. The 6 FPGA read-out boards used in the EXCALIBUR detector are interfaced to 6 computing nodes via 10Gbit/s fibre-optic links to maintain the very high frame-rate capability. The standard suite of EPICS control software is used to operate the detector and to integrate it with the Diamond Light Source beamline software environment. This article describes the design, fabrication and characterisation of the MEDIPIX3-based modules composing the EXCALIBUR detector.

  6. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Lantzsch, Kerstin; The ATLAS collaboration

    2016-01-01

    Run 2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). In addition the Pixel detector was refurbished with new service quarter panels to recover about 3% of defective modules lost during run 1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning, operation and performance of the 4-layer Pixel Detector will be presented.

  7. Test Beam Results of 3D Silicon Pixel Sensors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Grenier, P.; /SLAC; Alimonti, G.; /INFN, Milan; Barbero, M.; /Bonn U.; Bates, R.; /Glasgow U.; Bolle, E.; /Oslo U.; Borri, M.; /Manchester U.; Boscardin, M.; /Fond. Bruno Kessler, Povo; Buttar, C.; /Glasgow U.; Capua, M.; /Calabria U. /INFN, Cosenza; Cavalli-Sforza, M.; /Barcelona, IFAE; Cobal, M.; /Udine U. /INFN, Udine; Cristofoli, A.; /Udine U. /INFN, Udine; Dalla Betta, G.F.; /Trento U. /INFN, Trento; Darbo, G.; /INFN, Genoa; Da Via, C.; /Manchester U.; Devetak, E.; /SUNY, Stony Brook; DeWilde, B.; /SUNY, Stony Brook; Di Girolamo, B.; /CERN; Dobos, D.; /CERN; Einsweiler, K.; /LBL, Berkeley; Esseni, D.; /Udine U. /INFN, Udine /Calabria U. /INFN, Cosenza /Barcelona, Inst. Microelectron. /Manchester U. /CERN /LBL, Berkeley /INFN, Genoa /INFN, Genoa /Udine U. /INFN, Udine /Oslo U. /ICREA, Barcelona /Barcelona, IFAE /SINTEF, Oslo /SINTEF, Oslo /SLAC /SLAC /Bergen U. /New Mexico U. /Bonn U. /SLAC /Freiburg U. /VTT Electronics, Espoo /Bonn U. /SLAC /Freiburg U. /SLAC /SINTEF, Oslo /Manchester U. /Barcelona, IFAE /Bonn U. /Bonn U. /CERN /Manchester U. /SINTEF, Oslo /Barcelona, Inst. Microelectron. /Calabria U. /INFN, Cosenza /Udine U. /INFN, Udine /Manchester U. /VTT Electronics, Espoo /Glasgow U. /Barcelona, IFAE /Udine U. /INFN, Udine /Hawaii U. /Freiburg U. /Manchester U. /Barcelona, Inst. Microelectron. /CERN /Fond. Bruno Kessler, Povo /Prague, Tech. U. /Trento U. /INFN, Trento /CERN /Oslo U. /Fond. Bruno Kessler, Povo /INFN, Genoa /INFN, Genoa /Bergen U. /New Mexico U. /Udine U. /INFN, Udine /SLAC /Oslo U. /Prague, Tech. U. /Oslo U. /Bergen U. /SUNY, Stony Brook /SLAC /Calabria U. /INFN, Cosenza /Manchester U. /Bonn U. /SUNY, Stony Brook /Manchester U. /Bonn U. /SLAC /Fond. Bruno Kessler, Povo

    2011-08-19

    Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable-B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS Inner Detector solenoid field. Sensors were bump bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance. Full and partial 3D pixel detectors have been tested, with and without a 1.6T magnetic field, in high energy pion beams at the CERN SPS North Area in 2009. Sensors characteristics have been measured as a function of the beam incident angle and compared to a regular planar pixel device. Overall full and partial 3D devices have similar behavior. Magnetic field has no sizeable effect on 3D performances. Due to electrode inefficiency 3D devices exhibit some loss of tracking efficiency for normal incident tracks but recover full efficiency with tilted tracks. As expected due to the electric field configuration 3D sensors have little charge sharing between cells.

  8. ATLAS Tracker and Pixel Operational Experience

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00222525; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker, are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  9. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  10. FAZIA front-end electronics

    OpenAIRE

    Salomon F.; Edelbruck P.; Brulin G.; Boiano A.; Tortone G.; Ordine A.; Bini M.; Barlini S.; Valdré S.

    2015-01-01

    FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  11. FAZIA front-end electronics

    Directory of Open Access Journals (Sweden)

    Salomon F.

    2015-01-01

    Full Text Available FAZIA is a multi-detector specifically designed to optimize ion identification in heavy-ion experiments. Its electronic is fully digital; it was designed in the laboratories of the collaboration. This paper presents the front-end part of this electronic.

  12. Physics performance of the ATLAS Pixel Detector

    CERN Document Server

    Tsuno, Soshi; The ATLAS collaboration

    2016-01-01

    One noticeable upgrade from Run-1 to Run-2 with ATLAS detector in proton-proton collisions at LHC is the introduction of the new pixel detector, IBL, located on the beam pipe as the extra innermost pixel layer. The tracking and vertex reconstruction are significantly improved and good performance is expected in high level object such a $b$-quark jet tagging, in turn, it leads the better physics results. This note summarizes what is the impact on the IBL detector to the physics results especially focusing on the analyses using the $b$-quark jets throughout 2016 summer physics program.

  13. Physics performance of the ATLAS pixel detector

    Science.gov (United States)

    Tsuno, S.

    2017-01-01

    In preparation for LHC Run-2 the ATLAS detector introduced a new pixel detector, the Insertable B-Layer (IBL). This detector is located between the beampipe and what was the innermost pixel layer. The tracking and vertex reconstruction are significantly improved and good performance is expected in high level objects such a b-quark jet tagging. This in turn, leads to better physics results. This note summarizes the impact of the IBL detector on physics results, especially focusing on the analyses using b-quark jets throughout 2016 summer physics program.

  14. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, Malte

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3centerdot1034 cm-2s-1 and IBL is designed for an integrated luminosity of 700 fb-1. This corresponds to an expected fluence of 5centerdot1015 1 MeV neqcm-2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design of the ...

  15. Characterization of new hybrid pixel module concepts for the ATLAS Insertable B-Layer upgrade

    CERN Document Server

    Backhaus, M

    2012-01-01

    The ATLAS Insertable B-Layer (IBL) collaboration plans to insert a fourth pixel layer inside the present Pixel Detector to recover from eventual failures in the current pixel system, especially the b-layer. Additionally the IBL will ensure excellent tracking, vertexing and b-tagging performance during the LHC phase I and add robustness in tracking with high luminosity pile-up. The expected peak luminosity for IBL is 2 to 3•10^34 cm^−2 s^ −1 and IBL is designed for an integrated luminosity of 700 fb^−1 . This corresponds to an expected fluence of 5 • 10^15 1 MeV n_eqcm^−2 and a total ionizing dose of 250 MRad. In order to cope with these requirements, two new module concepts are under investigation, both based on a new front end IC, called FE-I4. This IC was designed as readout chip for future ATLAS Pixel Detectors and its first application will be the IBL. The planar pixel sensor (PPS) based module concept benefits from its well understood design, which is kept as similar as possible to the design...

  16. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    The calibration of the Pixel detector fulfills two main purposes: to tune front-end registers for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied toghether to chips with dierent characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  17. Upgrades of the ATLAS Pixel Detector

    CERN Document Server

    Hügging, F; The ATLAS collaboration

    2013-01-01

    The upgrade for the ATLAS detector will undergo different phases towards HL-LHC. The first upgrade for the Pixel Detector (Phase 1) consists in the construction of a new pixel layer, which will be installed during the 1st long shutdown of the LHC machine (LS1) in 2013/14. The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of about 3.2 cm. The IBL requires the development of several new technologies to cope with the increase of radiation and pixel occupancy as well as to improve the physics performance of the existing pixel detector. The pixel size is reduced and the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system. For Phase 2 upgrade of LHC a complete new 4-layer pixel system is planned as part of a new all silicon Inner Detector. The increase in luminosity to about $5\\cdot 10^{34}$cm$^{-2}$s$^{-1}$ together with a total expected lifetime of ab...

  18. ATLAS rewards two pixel detector suppliers

    CERN Multimedia

    2007-01-01

    Peter Jenni, ATLAS spokesperson, presented the ATLAS supplier award to Herbert Reichl, IZM director, and to Simonetta Di Gioia, from the SELEX company.Two of ATLAS’ suppliers were awarded prizes at a ceremony on Wednesday 13 June attended by representatives of the experiment’s management and of CERN. The prizes went to the Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM) in Berlin and the company SELEX Sistemi Integrati in Rome for the manufacture of modules for the ATLAS pixel detector. SELEX supplied 1500 of the modules for the tracker, while IZM produced a further 1300. The modules, each made up of 46080 channels, form the active part of the ATLAS pixel detector. IZM and SELEX received the awards for the excellent quality of their work: the average number of faulty channels per module was less than 2.10-3. They also stayed within budget and on schedule. The difficulty they faced was designing modules based on electronic components and sensor...

  19. FRIB Front End Design Status

    CERN Document Server

    Pozdeyev, E; Machicoane, G; Morgan, G; Rao, X; Zhao, Q; Stovall, J; Vorozhtsov, S; Sun, L

    2013-01-01

    The Facility for Rare Isotope Beams (FRIB) will provide a wide range of primary ion beams for nuclear physics research with rare isotope beams. The FRIB SRF linac will be capable of accelerating medium and heavy ion beams to energies beyond 200 MeV/u with a power of 400 kW on the fragmentation target. This paper presents the status of the FRIB Front End designed to produce uranium and other medium and heavy mass ion beams at world-record intensities. The paper describes the FRIB high performance superconducting ECR ion source, the beam transport designed to transport two-charge state ion beams and prepare them for the injection in to the SRF linac, and the design of a 4-vane 80.5 MHz RFQ. The paper also describes the integration of the front end with other accelerator and experimental systems.

  20. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  1. ATLAS Pixel IBL: Stave Quality Assurance

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    For Run 2 of the LHC a fourth innermost Pixel Detector layer on a smaller radius beam pipe has been installed in the ATLAS Detector to add redundancy against radiation damage of the current Pixel Detector and to ensure a high quality tracking and b-tagging performance of the Inner Detector over the coming years until the High Luminosity Upgrade. State of the art components have been produced and assembled onto support structures known as staves over the last two years. In total, 20 staves have been built and qualified in a designated Quality Assurance setup at CERN of which 14 have been integrated onto the beam pipe. Results from the testing are presented.

  2. optical links for the atlas pixel detector

    CERN Document Server

    Stucci, Stefania Antonia; The ATLAS collaboration

    2015-01-01

    Optical links are necessary to satisfy the high speed readout over long distances for advanced silicon detector systems. We report on the optical readout used in the newly installed central pixel layer (IBL) in the ATLAS experiment. The off detector readout employs commercial optical to analog converters, which were extensively tested for this application. Performance measurements during installation and commissioning will be shown. With the increasing instantaneous luminosity in the next years, the next layers outwards of IBL of the ATLAS Pixel detector (Layer 1 and Layer 2) will reach their bandwidth limits. A plan to increase the bandwidth by upgrading the off detector readout chain is put in place. The plan also involves new optical readout components, in particular the optical receivers, for which commercial units cannot be used and a new design has been made. The latter allows for a wider operational range in term of data frequency and light input power to match the on-detector sending units on the pres...

  3. Optical links for the ATLAS Pixel detector

    CERN Document Server

    Stucci, Stefania Antonia; The ATLAS collaboration

    2015-01-01

    Optical links are necessary to satisfy the high speed readout over long distances for advanced silicon detector systems. We report on the optical readout used in the newly installed central pixel layer (IBL) in the ATLAS experiment. The off detector readout employs commercial optical to analog converters, which were extensively tested for this application. Performance measurements during installation and commissioning will be shown. With the increasing instantaneous luminosity in the next years, the next layers outwards of IBL of the ATLAS Pixel detector (Layer 1 and Layer 2) will reach their bandwidth limits. A plan to increase the bandwidth by upgrading the off detector readout chain is put in place. The plan also involves new optical readout components, in particular the optical receivers, for which commercial units cannot be used and a new design has been made. The latter allows for a wider operational range in term of data frequency and light input power to match the on-detector sending units on the pres...

  4. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

  5. The Phase II ATLAS ITk Pixel Upgrade

    CERN Document Server

    Terzo, Stefano; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the "ITk" (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and and ring-shaped supports in the endcap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m$^2$ , depending on the final layout choice, which is expected to take place in early 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel-endcap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as $|\\eta| < 4$. Supporting structures will be ...

  6. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  7. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  8. ATLAS Pixel Radiation Monitoring with HVPP4 System

    CERN Document Server

    Gorelov, Igor; Seidel, Sally; Toms, Konstantin

    2009-01-01

    In this talk we present the basis for the protocol for radiation monitoring of the ATLAS Pixel Sensors. The monitoring is based on a current measurement system, HVPP4. The status on the ATLAS HVPP4 system development is also presented.

  9. The next generation CBM MVD front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Wiebusch, Michael; Michel, Jan; Klaus, Philipp; Stroth, Joachim [Goethe-Universitaet, Frankfurt (Germany); Collaboration: CBM-MVD-Collaboration

    2015-07-01

    The Micro Vertex Detector (MVD) for the CBM experiment is a highly granular precision tracking device. Due to the ambitious requirements regarding spatial resolution, radiation hardness, read-out speed and material budget, monolithic active pixel sensors (MAPS) are the most suited detector technology for this purpose. A full read-out chain for these sensors was designed and prototyped, comprising a multi-purpose FPGA platform and specialized front-end electronics. During the last year an updated version of the front-end electronics was produced and successfully commissioned. The current front-end electronics incorporate additional configuration and monitoring capabilities which shall be used to optimize the concept of biasing and routing critical analog signals to the sensor. Tests regarding these issues are ongoing. Recent efforts aim at building a quarter of an MVD station with more than a dozen individual MAPS sensors. This requires the adaption of the front-end electronics to the spacial constraints of the set-up. Also the schematics have to be streamlined based on the insights from the abovementioned tests. This contribution presents the outcomes of the adaption and optimization procedures.

  10. 3D silicon sensors: Design, large area production and quality assurance for the ATLAS IBL pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Da Via, Cinzia [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester, M13 9PL (United Kingdom); Boscardin, Maurizio [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [DISI, Universita degli Studi di Trento and INFN, Via Sommarive 14, I-38123 Trento (Italy); Darbo, Giovanni [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Fleta, Celeste [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Gemme, Claudia [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Grenier, Philippe [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Grinstein, Sebastian [Institut de Fisica d' Altes Energies (IFAE) and ICREA, Universitat Autonoma de Barcelona (UAB), E-08193 Bellaterra, Barcelona (Spain); Hansen, Thor-Erik [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Hasi, Jasmine; Kenney, Chris [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Kok, Angela [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Parker, Sherwood [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States); Pellegrini, Giulio [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Vianello, Elisa; Zorzi, Nicola [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

    2012-12-01

    3D silicon sensors, where electrodes penetrate the silicon substrate fully or partially, have successfully been fabricated in different processing facilities in Europe and USA. The key to 3D fabrication is the use of plasma micro-machining to etch narrow deep vertical openings allowing dopants to be diffused in and form electrodes of pin junctions. Similar openings can be used at the sensor's edge to reduce the perimeter's dead volume to as low as {approx}4 {mu}m. Since 2009 four industrial partners of the 3D ATLAS R and D Collaboration started a joint effort aimed at one common design and compatible processing strategy for the production of 3D sensors for the LHC Upgrade and in particular for the ATLAS pixel Insertable B-Layer (IBL). In this project, aimed for installation in 2013, a new layer will be inserted as close as 3.4 cm from the proton beams inside the existing pixel layers of the ATLAS experiment. The detector proximity to the interaction point will therefore require new radiation hard technologies for both sensors and front end electronics. The latter, called FE-I4, is processed at IBM and is the biggest front end of this kind ever designed with a surface of {approx}4 cm{sup 2}. The performance of 3D devices from several wafers was evaluated before and after bump-bonding. Key design aspects, device fabrication plans and quality assurance tests during the 3D sensors prototyping phase are discussed in this paper.

  11. Neural network based cluster creation in the ATLAS Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing be- tween pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. How- ever, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambigui- ties in the assignment of pixel detector measurement to tracks and improves the position accuracy with respect to standard techniques by taking into account the 2-dimensional charge distribution.

  12. Studio di Rivelatori a Pixel di nuova generazione per il Sistema di Tracciamento di ATLAS.

    CERN Document Server

    Gaudiello, Andrea; Schiavi, Carlo

    In 2013 the LHC will undergo a long shutdown (Phase 0) in preparation for a an energy and luminosity upgrade. During this period the ATLAS Pixel Detector (that is the tracking detector closest to the beamline) will be upgraded. The new detector, called Insertable B-Layer (IBL), will be installed between the existing pixel detector and a new beam-pipe of smaller radius in order to ensure and maintain excellent performance of tracking, vertexing and jet flavor tagging. To satisfy the new requirements a new electronic front- end (FE-I4) and 2 sensor technologies have been developed: Planar and 3D. Genova is one of two sites dedicated to the assembly of the modules of IBL. The work is then carried out in two parallel directions: on one hand the production and its optimization; on the other the comparison and testing of these new technologies. Chapter 1 gives an overview of the theoretical framework needed to understand the importance and the goals of the experiments operating at the Large Hadron Collider (LHC), w...

  13. Optimizing emergency department front-end operations.

    Science.gov (United States)

    Wiler, Jennifer L; Gentle, Christopher; Halfpenny, James M; Heins, Alan; Mehrotra, Abhi; Mikhail, Michael G; Fite, Diana

    2010-02-01

    As administrators evaluate potential approaches to improve cost, quality, and throughput efficiencies in the emergency department (ED), "front-end" operations become an important area of focus. Interventions such as immediate bedding, bedside registration, advanced triage (triage-based care) protocols, physician/practitioner at triage, dedicated "fast track" service line, tracking systems and whiteboards, wireless communication devices, kiosk self check-in, and personal health record technology ("smart cards") have been offered as potential solutions to streamline the front-end processing of ED patients, which becomes crucial during periods of full capacity, crowding, and surges. Although each of these operational improvement strategies has been described in the lay literature, various reports exist in the academic literature about their effect on front-end operations. In this report, we present a review of the current body of academic literature, with the goal of identifying select high-impact front-end operational improvement solutions.

  14. ATLAS Inner Detector (Pixel Detector and Silicon Tracker)

    CERN Multimedia

    ATLAS Outreach

    2006-01-01

    To raise awareness of the basic functions of the Pixel Detector and Silicon Tracker in the ATLAS detector on the LHC at CERN. This colorful 3D animation is an excerpt from the film "ATLAS-Episode II, The Particles Strike Back." Shot with a bug's eye view of the inside of the detector. The viewer is taken on a tour of the inner workings of the detector, seeing critical pieces of the detector and hearing short explanations of how each works.

  15. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules.

    CERN Document Server

    Rubinskiy, Igor; The ATLAS collaboration

    2011-01-01

    The upgrade for the ATLAS detector will undergo different phases towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013-14). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 3.2 cm. The IBL will require the development of several new technologies to cope with increase of radiation or pixel occupancy and also to improve the physics performance which will be achieved by reduction of the pixel size and of the material budget. Two different promising Silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the pixel detector. An overview of the sensor technologies qualification with particular emphasis on irradiation and beam tests will be presented.

  16. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

    CERN Document Server

    Rubinskiy, I

    2013-01-01

    The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–2014). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase in the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector. An overview of the sensor technologies' qualification with particular emphasis on irradiation and beam tests is presented.

  17. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

    CERN Document Server

    Rubinskiy, Igor

    2013-01-01

    The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013-14). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase of the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the pixel detector. An overview of the sensor technologies’ qualification with particular emphasis on irradiation and beam tests are presented.

  18. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  19. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik;

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  20. Fabrication of ATLAS pixel detector prototypes at IRST

    CERN Document Server

    Boscardin, M; Gregori, P; Zen, M; Zori, N

    2001-01-01

    We report on the development of a fabrication technology for n-on-n silicon pixel detectors oriented to the ATLAS experiment at LHC. The main processing issues and some selected results from the electrical characterization of detector prototypes and related test structures are presented and discussed. (5 refs).

  1. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  2. Planar Pixel Sensors for the ATLAS Upgrade: Beam Tests results

    CERN Document Server

    Weingarten, J; Beimforde, M; Benoit, M; Bomben, M; Calderini, G; Gallrapp, C; George, M; Gibson, S; Grinstein, S; Janoska, Z; Jentzsch, J; Jinnouchi, O; Kishida, T; La Rosa, A; Libov, V; Macchiolo, A; Marchiori, G; Münstermann, D; Nagai, R; Piacquadio, G; Ristic, B; Rubinskiy, I; Rummler, A; Takubo, Y; Troska, G; Tsiskaridtze, S; Tsurin, I; Unno, Y; Weigel, P; Wittig, T

    2012-01-01

    Results of beam tests with planar silicon pixel sensors aimed towards the ATLAS Insertable B-Layer and High Luminosity LHC (HL-LHC) upgrades are presented. Measurements include spatial resolution, charge collection performance and charge sharing between neighbouring cells as a function of track incidence angle for different bulk materials. Measurements of n-in-n pixel sensors are presented as a function of fluence for different irradiations. Furthermore p-type silicon sensors from several vendors with slightly differing layouts were tested. All tested sensors were connected by bump-bonding to the ATLAS Pixel read-out chip. We show that both n-type and p-type tested planar sensors are able to collect significant charge even after integrated fluences expected at HL-LHC.

  3. Online calibrations and performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

  4. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    . The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

  5. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. In the ATLAS track reconstruction algorithm, an artificial neural network is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The robustness of the neural network algorithm is presented, probing its sensitivity to uncertainties in the detector conditions. The robustness is studied by evaluating the stability of the algorithm's performance under a range of variations in the inputs to the neural networks. Within reasonable variation magnitudes, the neural networks prove to be robust to most variation types.

  6. ATLAS Pixel Group - Photo Gallery from Irradiation

    CERN Multimedia

    2001-01-01

    Photos 1,2,3,4,5,6,7 - Photos taken before irradiation of Pixel Test Analog Chip and Pmbars (April 2000) Photos 8,9,10,11 - Irradiation of VDC chips (May 2000) Photos 12, 13 - Irradiation of Passive Components (June 2000) Photos 14,15, 16 - Irradiation of Marebo Chip (November 1999)

  7. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  8. Online Calibration and Performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  9. Optical Links for the ATLAS Pixel Detector

    CERN Document Server

    Gregor, Ingrid-Maria

    In der vorliegenden Dissertation wird eine strahlentolerante optische Datenstrecke mit hoher Datenrate für den Einsatz in dem Hochenergiephysikexperiment Atlas am Lhc Beschleuniger entwickelt. Da die Lhc-Experimente extremen Strahlenbelastungen ausgesetzt sind, müssen die Komponenten spezielle Ansprüche hinsichtlich der Strahlentoleranz erfüllen. Die Qualifikation der einzelnen Bauteile wurde im Rahmen dieser Arbeit durchgeführt. Die zu erwartenden Fluenzen im Atlas Inner Detector für Silizium und Gallium Arsenid (GaAs) wurden berechnet. Siliziumbauteile werden einer Fluenz von bis zu 1.1.1015neq /cm2 in 1 MeV äquivalenten Neutronen ausgesetzt sein, wohingegen GaAs Bauteile bis zu 7.8.1015neq /cm2 ausgesetzt sein werden. Die Strahlentoleranz der einzelnen benötigten Komponenten wie z.B. der Laserdioden sowie der jeweiligen Treiberchips wurde untersucht. Sowohl die Photo- als auch die Laserdioden haben sich als strahlentolerant für die Fluenzen an dem vorgesehenen Radius erwiesen. Aus de...

  10. Monitoring Radiation Damage in the ATLAS Pixel Detector

    CERN Document Server

    Schorlemmer, André Lukas; Große-Knetter, Jörn; Rembser, Christoph; Di Girolamo, Beniamino

    2014-11-05

    Radiation hardness is one of the most important features of the ATLAS pixel detector in order to ensure a good performance and a long lifetime. Monitoring of radiation damage is crucial in order to assess and predict the expected performance of the detector. Key values for the assessment of radiation damage in silicon, such as the depletion voltage and depletion depth in the sensors, are measured on a regular basis during operations. This thesis summarises the monitoring program that is conducted in order to assess the impact of radiation damage and compares it to model predictions. In addition, the physics performance of the ATLAS detector highly depends on the amount of disabled modules in the ATLAS pixel detector. A worrying amount of module failures was observed during run I. Thus it was decided to recover repairable modules during the long shutdown (LS1) by extracting the pixel detector. The impact of the module repairs and module failures on the detector performance is analysed in this thesis.

  11. Pixel detector modules performance for ATLAS IBL and future pixel detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00355104; Pernegger, Heinz

    2015-11-06

    The ATLAS Detector is one of the four big particle physics experiments at CERN’s LHC. Its innermost tracking system consisted of the 3-Layer silicon Pixel Detector (~80M readout channels) in the first run (2010-2012). Over the past two years it was refurbished and equipped with new services as well as a new beam monitor. The major upgrade, however, was the Insertable B-Layer (IBL). It adds ~12M readout channels for improved vertexing, tracking robustness and b-tagging performance for the upcoming runs, before the high luminosity upgrade of the LHC will take place. This thesis covers two main aspects of Pixel detector performance studies: The main work was the planning, commissioning and operation of a test bench that meets the requirements of current pixel detector components. Each newly built ATLAS IBL stave was thoroughly tested, following a specifically developed procedure, and initially calibrated in that setup. A variety of production accompanying measurements as well as preliminary results after integ...

  12. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  13. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

  14. Development of a Micro Pixel Chamber for the ATLAS Upgrade

    CERN Document Server

    Ochi, Atsuhiko; Komai, Hidetoshi; Edo, Yuki; Yamaguchi, Takahiro

    2012-01-01

    The Micro Pixel Chamber (μ-PIC) is being developed a sacandidate for the muon system of the ATLAS detector for upgrading in LHC experiments. The μ-PIC is a micro-pattern gaseous detector that doesn’t have floating structure such as wires, mesh, or foil. This detector can be made by printed-circuit-board (PCB) technology, which is commercially available and suited for mass production. Operation tests have been performed under high flux neutrons under similar conditions to the ATLAS cavern. Spark rates are measured using several gas mixtures under 7 MeV neutron irradiation, and good properties were observed using neon, ethane, and CF4 mixture of gases.Using resistive materials as electrodes, we are also developing a new μ-PIC, which is not expected to damage the electrodes in the case of discharge sparks.

  15. ATLAS Phase-II-Upgrade Pixel Data Transmission Development

    CERN Document Server

    Wensing, Marius; The ATLAS collaboration

    2016-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  16. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    Sidebo, Per Edvin; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. The algorithms depend heavily on accurate estimation of the position of particles as they traverse the inner detector elements. An artificial neural network algorithm is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The method recovers otherwise lost tracks in dense environments where particles are separated by distances comparable to the size of the detector read-out elements. Such environments are highly relevant for LHC run 2, e.g. in searches for heavy resonances. Within the scope of run 2 track reconstruction performance and upgrades, the robustness of the neural network algorithm will be presented. The robustness has been studied by evaluating the stability of the algorithm’s performance under a range of variations in the pixel detector conditions.

  17. Validation studies of the ATLAS pixel detector control system

    Energy Technology Data Exchange (ETDEWEB)

    Schultes, Joachim [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany)]. E-mail: schultes@physik.uni-wuppertal.de; Becks, Karl-Heinz [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Flick, Tobias [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Henss, Tobias [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Imhaeuser, Martin [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Kersten, Susanne [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Kind, Peter [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Lantzsch, Kerstin [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Maettig, Peter [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Reeves, Kendall [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Weingarten, Jens [University of Bonn, Nussallee 12, 53115 Bonn (Germany)

    2006-09-01

    The ATLAS pixel detector consists of 1744 identical silicon pixel modules arranged in three barrel layers providing coverage for the central region, and three disk layers on either side of the primary interaction point providing coverage of the forward regions. Once deployed into the experiment, the detector will employ optical data transfer, with the requisite powering being provided by a complex system of commercial and custom-made power supplies. However, during normal performance and production tests in the laboratory, only single modules are operated and electrical readout is used. In addition, standard laboratory power supplies are used. In contrast to these normal tests, the data discussed here were obtained from a multi-module assembly which was powered and read out using production items: the optical data path, the final design power supply system using close to final services, and the Detector Control System (DCS)

  18. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off de...

  19. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Rummler, Andr{e}; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

  20. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  1. Pixel-Cluster Counting Luminosity Measurement In ATLAS

    CERN Document Server

    McCormack, William Patrick; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measure- ments of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster- counting method a...

  2. Pixel-Cluster Counting Luminosity Measurement in ATLAS

    CERN Document Server

    McCormack, William Patrick; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measurements of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster-counting method are ...

  3. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    Smart, Ben; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362 mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline, while inclined designs have sensors angled such that they point towards the interaction point. The relative advantages and challenges of these two classes of designs will be examined in this paper, along with the mechanical solutions being considered. Thermal management, radiation-length mapping, and electrical services will al...

  4. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    Smart, Ben; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline. High-eta particles will therefore hit these sensors at shallow angles, leaving elongated charge clusters. The length of such a charge cluster can be used to estimate the angle of the passing particle. This information can then be used in track reconstruction to improve tracking efficiency and reduce fake rates. Inclined designs ...

  5. ATLAS pixel detector design for the HL-LHC

    Science.gov (United States)

    Smart, B.

    2017-02-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector is called the Inner Tracker (ITk). The ITk will cover an extended η-range: at least to |η|<3.2, and likely up to 0|η|<4.. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362 mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into `extended' and `inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline, while inclined designs have sensors angled such that they point towards the interaction point. The relative advantages and challenges of these two classes of designs will be examined in this paper, along with the mechanical solutions being considered. Thermal management, radiation-length mapping, and electrical services will also be discussed.

  6. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  7. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  8. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mathes, Markus

    2008-12-15

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  9. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  10. The Phase II ATLAS Pixel Upgrade: The Inner Tracker (ITk)

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m^2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to eta < 3.2 and two to eta < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions. Support...

  11. ATLAS Pixel-Optoboard Production and Simulation Studies

    CERN Document Server

    Nderitu, Simon

    At CERN, a Large collider will collide protons at high energies. There are four experiments being built to study the particle properties from the collision. The ATLAS experiment is the largest. It has many sub detectors among which is the Pixel detector which is the innermost part. The Pixel detector has eighty million channels that have to be read out. An optical link is utilized for the read out. It has optical to electronic interfaces both on the detector and off the detector at the counting room. The component on the detector in called the opto-board. This work discusses the production testing of the opto-boards to be installed on the detector. A total of 300 opto-boards including spares have been produced. The production was done in three laboratories among which is the laboratory at the University of Wuppertal which had the responsibility of Post production testing of all the one third of the total opto-boards. The results are discussed in this work. The analysis of the results from the total productio...

  12. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  13. Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

    CERN Document Server

    Backhaus, M

    2013-01-01

    The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3• 10^34 cm^−2 s ^−1with an integrated luminosity over the IBL lifetime of 300 fb^−1 corresponding to a design lifetime fluence of 5 • 10^15 n_eqcm^−2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these resu...

  14. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  15. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  16. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  17. Simulations of 3D-Si sensors for the innermost layer of the ATLAS pixel upgrade

    Science.gov (United States)

    Baselga, M.; Pellegrini, G.; Quirion, D.

    2017-03-01

    The LHC is expected to reach luminosities up to 3000 fb-1 and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non-passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade. It shows the charge collection response before and after irradiation, and the response of 3D-Si sensors located at large η angles.

  18. Simulations of 3D-Si sensors for the innermost layer of the ATLAS pixel upgrade

    CERN Document Server

    Baselga, Marta

    2017-01-01

    The LHC is expected to reach luminosities up to 3000fb-1 and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade, shows the charge collection response before and after irradiation, and the response of 3D-Si sensors located at large $\\eta$ angles.

  19. Indico front-end: From spaghetti to lasagna

    CERN Document Server

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  20. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  1. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  2. The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

    Energy Technology Data Exchange (ETDEWEB)

    Backhaus, M., E-mail: malte.backhaus@cern.ch

    2016-09-21

    During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO{sub 2} based cooling system. This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

  3. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Viel, Simon, E-mail: sviel@lbl.gov [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Banerjee, Swagato [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Pranko, Aliaksandr [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Rieger, Julia [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); II Physikalisches Institut, Georg-August-Universität, Göttingen (Germany); Wolf, Julian [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Wu, Sau Lan; Yang, Hongtao [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States)

    2016-09-21

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN. - Highlights: • Extended inner pixel barrel layers are proposed for the ATLAS ITk upgrade. • Test beam results at small track incidence angles validate this ATLAS ITk design. • Long pixel clusters are reconstructed with high efficiency at low threshold values. • Excellent angular resolution is achieved using pixel cluster length information.

  4. SiPM and front-end electronics development for Cherenkov light detection

    CERN Document Server

    Ambrosi, G; Bissaldi, E; Ferri, A; Giordano, F; Gola, A; Ionica, M; Paoletti, R; Piemonte, C; Paternoster, G; Simone, D; Vagelli, V; Zappala, G; Zorzi, N

    2015-01-01

    The Italian Institute of Nuclear Physics (INFN) is involved in the development of a demonstrator for a SiPM-based camera for the Cherenkov Telescope Array (CTA) experiment, with a pixel size of 6$\\times$6 mm$^2$. The camera houses about two thousands electronics channels and is both light and compact. In this framework, a R&D program for the development of SiPMs suitable for Cherenkov light detection (so called NUV SiPMs) is ongoing. Different photosensors have been produced at Fondazione Bruno Kessler (FBK), with different micro-cell dimensions and fill factors, in different geometrical arrangements. At the same time, INFN is developing front-end electronics based on the waveform sampling technique optimized for the new NUV SiPM. Measurements on 1$\\times$1 mm$^2$, 3$\\times$3 mm$^2$, and 6$\\times$6 mm$^2$ NUV SiPMs coupled to the front-end electronics are presented

  5. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2013-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  6. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Perez Cavalcanti, T; The ATLAS collaboration

    2012-01-01

    The hit signals read out from pixels on planar semi-conductor sensors are grouped into clusters, to reconstruct the location where a charged particle passed through. The resolution of the individual pixel sizes can be improved significantly using the information from the cluster of adjacent pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years giving an excellent performance. However, in dense environments, such as those inside high-energy jets, is likely that the charge deposited by two or more close-by tracks merges into one single cluster. A new pattern recognition algorithm based on neural network methods has been developed for the ATLAS Pixel Detector. This can identify the shared clusters, split them if necessary, and estimate the positions of all particles traversing the cluster. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurements to tracks within jets, and improves the positional accuracy with respect to stand...

  7. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    CERN Document Server

    Bourrion, O; Grignon, C; Richer, J P; Guillaudin, O; Mayet, F; Billard, J; Santos, D

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i.e. decoded coordinates of hit tracks and corresponding energy measurements. The electronic designs, acquisition software and the results obtained are presented.

  8. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Ye, J; The ATLAS collaboration

    2010-01-01

    Optical data links are used in detector front-end electronics readout systems of experiments in the Tevatron and the LHC. Optical links in high energy particle physics experiments usually have special requirements such as radiation tolerance, ultra high reliability and low power dissipation. These requirements are often not met by commercial components which are designed for applications in non-radiation, accessible (for maintenance) environment, and for multi-vendor systems so the parts must comply with certain standards. Future HEP experiments such as the upgrades for the sLHC call for optical links with ultra high data bandwidth, higher radiation tolerance and ultra low power dissipation. To meet these challenges and in particular those in the upgrade for the ATLAS Liquid Argon Calorimeter readout that calls for an optical link system of 100 Gbps for each front-end board, we adopted a full custom front-end electronics system design based on application specific integrated circuits. Reported here are the de...

  9. ALMA North American Integration Center Front-End Test System

    CERN Document Server

    Ediss, Geoffrey A; Crady, Kirk; Gaines, Erik; McLeod, Morgan; Morris, Greg; Williams, Rick; Perfetto, Antonio; Webber, John; 10.1007/s10762-010-9688-y

    2010-01-01

    The Atacama Large Millimeter/submillimeter (ALMA) Array Front End (FE) system is the first element in a complex chain of signal receiving, conversion, processing and recording. 70 Front Ends will be required for the project. The Front End is designed to receive signals in ten different frequency bands. In the initial phase of operations, the antennas will be fully equipped with six bands. These are Band 3 (84-116 GHz), Band 4 (125-163 GHz), Band 6 (211-275 GHz), Band 7 (275-373 GHz), Band 8 (385-500 GHz) and Band 9 (602-720 GHz). It is planned to equip the antennas with the missing bands at a later stage of ALMA operations, with a few Band 5 (163-211 GHz) and Band 10 (787-950 GHz) receivers in use before the end of the construction project. The ALMA Front End is far superior to any existing receiver systems; spin-offs of the ALMA prototypes are leading to improved sensitivities in existing millimeter and submillimeter observatories. The Front End units are comprised of numerous elements, produced at different...

  10. Recent results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    AUTHOR|(CDS)2073610

    2011-01-01

    The ATLAS detector has to undergo significant updates at the end of the current decade, in order to withstand the increased occupancy and radiation damage that will be produced by the high-luminosity upgrade of the Large Hadron Collider. In this presentation we give an overview of the recent accomplishments of the R&D activity on the planar pixel sensors for the ATLAS Inner Detector upgrade.

  11. dE/dx measurement in the ATLAS Pixel Detector and its use for particle identification

    CERN Document Server

    The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector provides a measurement of the charge deposited by each track crossing it. This note presents a study of how this information can be used to identify low beta particles. This study uses hits recorded in the 7 TeV proton-proton collisions during the 2010 run period and the corresponding Monte Carlo simulation. The track reconstruction has been done in the standard ATLAS software environment.

  12. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Viel, Simon; Banerjee, Swagato; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian; Wu, Sau Lan; Yang, Hongtao

    2016-09-01

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN.

  13. Performance of Silicon Pixel Detectors at Small Track Incidence Angles for the ATLAS Inner Tracker Upgrade

    CERN Document Server

    Viel, Simon; The ATLAS collaboration; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian Choate; Wu, Sau Lan; Yang, Hongtao

    2015-01-01

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN.

  14. CMS ECAL Front-End boards the XFEST project

    CERN Document Server

    Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N; Romanteau, T

    2005-01-01

    The Front-End (FE) boards are part of the On-detector electronics system of the CMS electromagnetic calorimeter (ECAL). Their digital functionalities and properties are tested by a dedicated test bench located at Laboratoire Leprince-Ringuet, prior to the board integration in the CMS detector at CERN. XFEST, acronym for eXtended Front-End System Test, is designed to perform tests that can last several hours, on up to 12 FE boards in parallel. The system is designed to deliver 80 tested boards per week. This contribution presents the XFEST set-up and the results of the measurements on FE boards.

  15. HINS Linac front end focusing system R&D

    Energy Technology Data Exchange (ETDEWEB)

    Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

    2008-08-01

    This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

  16. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  17. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  18. Planar n{sup +}-in-n silicon pixel sensors for the ATLAS IBL upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Goessling, C.; Klingenberg, R. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Muenstermann, D., E-mail: Daniel.Muenstermann@TU-Dortmund.de [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Rummler, A.; Troska, G.; Wittig, T. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany)

    2011-09-11

    The ATLAS experiment at the LHC is planning to upgrade its pixel detector by the installation of a 4th pixel layer, the insertable b-layer IBL with a mean sensor radius of only 32 mm from the beam axis. Being very close to the beam, the radiation damage of the IBL sensors might be as high as 5x10{sup 15} n{sub eq} cm{sup -2} at their end-of-life. To investigate the radiation hardness and suitability of the current ATLAS pixel sensors for IBL fluences, n{sup +}-in-n silicon pixel sensors from the ATLAS Pixel production have been irradiated by reactor neutrons to the IBL design fluence and been tested with pions at the SPS and with electrons from a {sup 90}Sr source in the laboratory. The collected charge was found to exceed 10 000 electrons per MIP at 1 kV of bias voltage which is in agreement with data collected with strip sensors. With an expected threshold of 3000-4000 electrons, this result suggests that planar n{sup +}-in-n pixel sensors are radiation hard enough to be used as IBL sensor technology.

  19. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  20. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  1. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  2. A socio-interactive framework for the fuzzy front end

    NARCIS (Netherlands)

    Smulders, Frido E.; Broek, van den Egon L.; Voort, van der Mascha C.

    2007-01-01

    This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary sociointeractive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive framework

  3. Business modelling in the fuzzy front end of innovation

    NARCIS (Netherlands)

    Limonard, A.J.P.; Berkers, F.T.H.M.; Niamut, O.A.; Bachet, T.T.; Reuver, M. de

    2011-01-01

    In this paper we address the techno-economic dilemma in the fuzzy front end of R&D consortia: how to bridge the gap between the lack of knowledge on future demand for a technology and the need to make design decisions. The problem in these types of collaborations that the business interests to devel

  4. Instrumentation of a Track Trigger with Double Buffer Front-End Architecture

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The planned high luminosity upgrade for the LHC (SLHC), will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. We describe a possible design which splits the level-1 trigger into a two-level system, where the first level, using only calorimetry and muon chambers, defines regions of interest in the tracker from which to extract information for a second, refined trigger. The use of a two-buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency will be s...

  5. Development of planar pixel modules for the ATLAS high luminosity LHC tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Allport, P.P. [Department of Physics, University of Liverpool (United Kingdom); Ashby, J.; Bates, R.L.; Blue, A. [SUPA, School of Physics and Astronomy, University of Glasgow (United Kingdom); Burdin, S. [Department of Physics, University of Liverpool (United Kingdom); Buttar, C.M., E-mail: craig.buttar@glasgow.ac.uk [SUPA, School of Physics and Astronomy, University of Glasgow (United Kingdom); Casse, G.; Dervan, P. [Department of Physics, University of Liverpool (United Kingdom); Doonan, K. [SUPA, School of Physics and Astronomy, University of Glasgow (United Kingdom); Forshaw, D. [Department of Physics, University of Liverpool (United Kingdom); Lipp, J. [The Science and Technology Facilities Council, Rutherford Appleton Laboratory (United Kingdom); McMullen, T. [SUPA, School of Physics and Astronomy, University of Glasgow (United Kingdom); Pater, J. [School of Physics and Astronomy, University of Manchester (United Kingdom); Stewart, A. [SUPA, School of Physics and Astronomy, University of Glasgow (United Kingdom); Tsurin, I. [Department of Physics, University of Liverpool (United Kingdom)

    2014-11-21

    The high-luminosity LHC will present significant challenges for tracking systems. ATLAS is preparing to upgrade the entire tracking system, which will include a significantly larger pixel detector. This paper reports on the development of large area planar detectors for the outer pixel layers and the pixel endcaps. Large area sensors have been fabricated and mounted onto 4 FE-I4 readout ASICs, the so-called quad-modules, and their performance evaluated in the laboratory and testbeam. Results from characterisation of sensors prior to assembly, experience with module assembly, including bump-bonding and results from laboratory and testbeam studies are presented.

  6. Optical Readout in a Multi-Module System Test for the ATLAS Pixel Detector

    CERN Document Server

    Flick, T; Gerlach, P; Kersten, S; Mättig, P; Kirichu, S N; Reeves, K; Richter, J; Schultes, J; Flick, Tobias; Becks, Karl-Heinz; Gerlach, Peter; Kersten, Susanne; Maettig, Peter; Kirichu, Simon Nderitu; Reeves, Kendall; Richter, Jennifer; Schultes, Joachim

    2006-01-01

    The innermost part of the ATLAS experiment at the LHC, CERN, will be a pixel detector. The command messages and the readout data of the detector are transmitted over an optical data path. The readout chain consists of many components which are produced at several locations around the world, and must work together in the pixel detector. To verify that these parts are working together as expected a system test has been built up. In this paper the system test setup and the operation of the readout chain is described. Also, some results of tests using the final pixel detector readout chain are given.

  7. FE-I4 Chip Development for Upgraded ATLAS Pixel Detector at LHC

    CERN Document Server

    Barbero, M; The ATLAS collaboration

    2010-01-01

    A new ATLAS pixel chip FE-I4 has been developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 μm CMOS technology used for the current ATLAS pixel IC, FE-I3. FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 μm2, consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. It is based on a two-stage architecture with a pre-amp AC-coupled to a second stage of amplification. It features leakage current compensation circuitry, local 4-bit pre-amp feedback tuning and a discriminator locally adjusted through 5 configuration bits. The digital architecture is based on a 4-pixel unit called Pixel Digital Region (PDR) allowing for local storage of hits in 5-deep data buffers at pixel level for the duratio...

  8. The FE-I4 Pixel Readout Chip and the IBL Module

    CERN Document Server

    Barbero, Marlon; Backhaus, Malte; Fang, Xiaochao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Krueger, Hans; Kruth, Andre; Wermes, Norbert; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Sasha; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; Garcia-Sciveres, Maurice; Jensen, Frank; Lu, Yunpeng; Mekkaoui, Abderrezak; Gromov, Vladimir; Kluit, Ruud; Schipper, Jan David; Zivkovic, Vladimir; Grosse-Knetter, Joern; Weingarten; Kocian, Martin

    2011-01-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the “Insertable B-Layer” project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  9. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  10. The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, M

    2016-01-01

    During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for me...

  11. Novel silicon n-in-p pixel sensors for the future ATLAS upgrades

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, A., E-mail: alessandro.larosa@cern.ch [Section de Physique (DPNC), Université de Genève, 24 quai Ernest Ansermet, Genève 4, CH-1211 (Switzerland); Gallrapp, C. [CERN, Geneva 23, CH-1211 (Switzerland); Macchiolo, A.; Nisius, R. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut) Föhringer Ring 6, D-80805 München (Germany); Pernegger, H. [CERN, Geneva 23, CH-1211 (Switzerland); Richter, R.H. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, D-81739 München (Germany); Weigell, P. [Max-Planck-Institut für Physik (Werner-Heisenberg-Institut) Föhringer Ring 6, D-80805 München (Germany)

    2013-08-01

    In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the inner detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 10{sup 16}1-MeV n{sub eq}cm{sup −2}, and prove the operability of this kind of sensors in the harsh radiation environment foreseen for the pixel system at HL-LHC. We also present an overview of the new pixel production, which is on-going at CiS for sensors compatible with the new ATLAS readout chip FE-I4.

  12. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    During Run-1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This includes the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore a new readout chip and two new sensor technologies (planar and 3D) are used in IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanic...

  13. Operational Performance and Status of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Jentzsch, J; The ATLAS collaboration

    2014-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experi- ment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individu- ally read out via chips bump-bonded to 1744 n+-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including moni- toring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 · 1033 cm−2s−1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silico...

  14. Novel Silicon n-in-p Pixel Sensors for the future ATLAS Upgrades

    CERN Document Server

    La Rosa, A; Macchiolo, A; Nisius, R; Pernegger, H; Richter,R H; Weigell, P

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the Inner Detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost eectiveness, that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 1016 1-MeV $n_{eq}cm^{-2}$, and prove the operability of this kind of sensors in the harsh radiation environment foreseen for the pixel system at HL-LHC. We also present an overview of the new pixel production, which is on-going at CiS for sensors compatible with the new ATLAS readout chip FE-I4.

  15. Operational performance and status of the ATLAS pixel detector at the LHC

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  16. Status and future of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Rozanov, A; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  17. Operational Performance and Status of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Jentzsch, J; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  18. Achievements of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    Nellist, C

    2015-01-01

    In the framework of the HL-LHC upgrade, the ATLAS experiment plans to introduce an all-silicon inner tracker to cope with the elevated occupancy. To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Planar Pixel Sensor R&D Project (PPS) was established comprising 19 institutes and more than 90 scientists. The paper provides an overview of the research and development project and highlights accomplishments, among them: beam test results with planar sensors up to innermost layer fluences (> 10^16 n_eq cm^2); measurements obtained with irradiated thin edgeless n-in-p pixel assemblies; recent studies of the SCP technique to obtain almost active edges by postprocessing already existing sensors based on scribing, cleaving and edge passivation; an update on prototyping efforts for large areas: sensor design improvements and concepts for low-cost hybridisation; comparison between Secondary Ion Mass Spectrometry results and TCAD simulations. Togethe...

  19. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Savic, N.; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-02-01

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm2). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm2 pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  20. Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Libov, Vladyslav

    2013-08-15

    measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

  1. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    Energy Technology Data Exchange (ETDEWEB)

    Richer, J.P.; Bosson, G. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Bourrion, O., E-mail: olivier.bourrion@lpsc.in2p3.f [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France); Grignon, C.; Guillaudin, O.; Mayet, F.; Santos, D. [Laboratoire de Physique Subatomique et de Cosmologie, Universite Joseph Fourier Grenoble 1, CNRS/IN2P3, Institut Polytechnique de Grenoble, 53, rue des Martyrs, Grenoble (France)

    2010-08-21

    A front end ASIC (BiCMOS-SiGe 0.35{mu}m) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (a few keV) tracks with a gaseous {mu}TPC. The development of this front end ASIC is a key point of the project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronics. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips of pixels are monitored.

  2. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    CERN Document Server

    INSPIRE-00517212; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2016-01-01

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 um. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 um and a novel design with the optimized biasing structure and small pixel cells (50 um x 50 um and 25 um x 100 um). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represen...

  3. HDI flexible front-end hybrid prototype for the PS module of the CMS tracker upgrade

    Science.gov (United States)

    Kovacs, M.; Blanchot, G.; Gadek, T.; Honma, A.; Koliatos, A.

    2017-02-01

    The CMS tracker upgrade for the HL-LHC relies on different module types, depending on the position of the respective module. They are built with high-density interconnection flexible circuits that are wire bonded to silicon strip and pixel-strip sensors. The Front-End hybrids will contain several flip-chip bonded readout ASICs that are still under development. Mock-up prototypes are used to qualify the advanced flexible circuit technology and the parameters of the hybrids. This paper presents the Pixel-Strip (PS) mock-up hybrid in terms of testing, interconnection, fold-over, thermal properties and layout feasibility. Plans for circuit testing at operating temperature (-30o) are also presented.

  4. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  5. Single Front-End MIMO Architecture with Parasitic Antenna Elements

    Science.gov (United States)

    Yoshida, Mitsuteru; Sakaguchi, Kei; Araki, Kiyomichi

    In recent years, wireless communication technology has been studied intensively. In particular, MIMO which employs several transmit and receive antennas is a key technology for enhancing spectral efficiency. However, conventional MIMO architectures require some transceiver circuits for the sake of transmitting and receiving separate signals, which incurs the cost of one RF front-end per antenna. In addition to that, MIMO systems are assumed to be used in low spatial correlation environment between antennas. Since a short distance between each antenna causes high spatial correlation and coupling effect, it is difficult to miniaturize wireless terminals for mobile use. This paper shows a novel architecture which enables mobile terminals to be miniaturized and to work with a single RF front-end by means of adaptive analog beam-forming with parasitic antenna elements and antenna switching for spatial multiplexing. Furthermore, statistical analysis of the proposed architecture is also discussed in this paper.

  6. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  7. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  8. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  9. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...

  10. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    of the staging of inno-vation processes, which focuses on the content and framing of ideas at the front end. The understanding sensitises hereby towards con-cerns of path-dependency and translations, inclu-ding trade-offs and potentialities involved in su-stainning or reframing matters of significance as part...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

  11. Evaluation of the breakdown behaviour of ATLAS silicon pixel sensors after partial guard-ring removal

    Energy Technology Data Exchange (ETDEWEB)

    Goessling, C.; Klingenberg, R. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Muenstermann, D., E-mail: Daniel.Muenstermann@TU-Dortmund.d [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Wittig, T. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany)

    2010-12-11

    To avoid geometrical inefficiencies in the ATLAS pixel detector, the concept of shingling is used up to now in the barrel section. For the upgrades of ATLAS, it is desired to avoid this as it increases the volume and material budget of the pixel layers and complicates the cooling. A direct planar edge-to-edge arrangement of pixel modules has not been possible in the past due to about 1100{mu}m of inactive edge composed of approximately 600{mu}m of guard rings and 500{mu}m of safety margin. In this work, the safety margin and guard rings of ATLAS SingleChip sensors were cut at different positions using a standard diamond dicing saw and irradiated afterwards to explore the breakdown behaviour and the leakage current development. It is found that the inactive edge can be reduced to about 400{mu}m of guard rings with almost no reduction in pre-irradiation testability and leakage current performance. This is in particular important for the insertable b-layer upgrade of ATLAS (IBL) where inactive edges of less than 450{mu}m width are required.

  12. Holographic optical receiver front end for wireless infrared indoor communications.

    Science.gov (United States)

    Jivkova, S; Kavehrad, M

    2001-06-10

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver's small size, light weight, and low cost make the receiver front end a promising candidate for a user's portable equipment in broadband indoor wireless multimedia access.

  13. Spatial and vertex resolution studies on the ATLAS Pixel Detector based on Combined Testbeam 2004 data

    CERN Document Server

    Reisinger, Ingo; Klingenberg, Reiner

    2006-01-01

    This diploma thesis deals with spatial and vertex resolution studies on the ATLAS Pixel detector based on real data taken during the Combined Testbeam period 2004 (17th May - 15th November). For the Combined Testbeam a barrel segment of the ATLAS Detector was build up and tested under real experimental conditions. Several data sets, being recorded during that time, are reconstructed by the ATLAS control framework called ATHENA. The input information for the reconstruction of the particle tracks through the Pixel Detector are the so-called spacepoints. Their uncertainty affects the resolution of the reconstructed particle tracks and thus, also the accuracy of the vertex reconstruction. Since traversing particles deposite their charge mostly (but not compellingly) within more than one pixel, all pixels corresponding to one hit have to be grouped together to a cluster. To compute the spacepoint from the cluster information two different strategies can be performed. The first one is a digital clustering, w...

  14. Passive front-ends for wideband millimeter wave electronic warfare

    Science.gov (United States)

    Jastram, Nathan Joseph

    This thesis presents the analysis, design and measurements of novel passive front ends of interest to millimeter wave electronic warfare systems. However, emerging threats in the millimeter waves (18 GHz and above) has led to a push for new systems capable of addressing these threats. At these frequencies, traditional techniques of design and fabrication are challenging due to small size, limited bandwidth and losses. The use of surface micromachining technology for wideband direction finding with multiple element antenna arrays for electronic support is demonstrated. A wideband tapered slot antenna is first designed and measured as an array element for the subsequent arrays. Both 18--36 GHz and 75--110 GHz amplitude only and amplitude/phase two element direction finding front ends are designed and measured. The design of arrays using Butler matrix and Rotman lens beamformers for greater than two element direction finding over W band and beyond using is also presented. The design of a dual polarized high power capable front end for electronic attack over an 18--45 GHz band is presented. To combine two polarizations into the same radiating aperture, an orthomode transducer (OMT) based upon a new double ridge waveguide cross section is developed. To provide greater flexibility in needed performance characteristics, several different turnstile junction matching sections are tested. A modular horn section is proposed to address flexible and ever changing operational requirements, and is designed for performance criteria such as constant gain, beamwidth, etc. A multi-section branch guide coupler and low loss Rotman lens based upon the proposed cross section are also developed. Prototyping methods for the herein designed millimeter wave electronic warfare front ends are investigated. Specifically, both printed circuit board (PCB) prototyping of micromachined systems and 3D printing of conventionally machined horns are presented. A 4--8 GHz two element array with

  15. Operational Experience of the ATLAS SemiConductor Tracker and Pixel Detector

    CERN Document Server

    Robinson, Dave; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  16. ATLAS pixel IBL modules construction experience and developments for future upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gaudiello, A.

    2015-10-01

    The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, are used. Sensors are connected with the new generation 130 nm IBM CMOS FE-I4 read-out chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

  17. FE-I4, the new ATLAS pixel chip for upgraded LHC luminosities

    Energy Technology Data Exchange (ETDEWEB)

    Arutinov, David; Barbero, Marlon; Gronewald, Markus; Hemperek, Tomasz; Karagounis, Michael; Krueger, Hans; Kruth, Andre; Wermes, Norbert [Physikalisches Institut, Universitaet Bonn, Nussallee 12, D-53115 Bonn (Germany)

    2010-07-01

    The new ATLAS pixel chip FE-I4 is being developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project and the outer pixel layers of Super-LHC. FE-I4 is designed in a 130 nm CMOS technology and is based on an array of 80 x 336 pixels, each 50 x x250 {mu}m2 and consisting of analog and digital sections. The analog pixel section is designed for low power consumption. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides a handle to the problem of timewalk. The chip periphery contains a digital control block, a command decoder, powering blocks, a data reformatting unit, an 8b10b coder and a clock multiplier unit, which handles data transmission up to 160 Mb/s for the IBL. Increased power consumption in the inner layers of ATLAS translates into more material for cooling and power routing, which degrades the tracking and the b-tagging quality. As a consequence the FE-I4 collaboration places severe constraints on the power consumption of all blocks. First full scale FE-I4 submission will occur beginning 2010.

  18. A Leakage Current-based Measurement of the Radiation Damage in the ATLAS Pixel Detector

    CERN Document Server

    Gorelov, Igor; The ATLAS collaboration

    2015-01-01

    A measurement has been made of the radiation damage incurred by the ATLAS Pixel Detector barrel silicon modules from the beginning of operations through the end of 2012. This translates to hadronic fluence received over the full period of operation at energies up to and including 8 TeV. The measurement is based on a per-module measurement of the silicon sensor leakage current. The results are presented as a function of integrated luminosity and compared to predictions by the Hamburg Model. This information can be used to predict limits on the lifetime of the Pixel Detector due to current, for various operating scenarios.

  19. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Boscardin, Maurizio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Darbo, Giovanni; Gemme, Claudia [INFN, Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); La Rosa, Alessandro; Pernegger, Heinz [CERN-PH, CH-1211 Geneve 23 (Switzerland); Piemonte, Claudio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Povoli, Marco [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Ronchin, Sabina [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Zoboli, Andrea [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Zorzi, Nicola [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy)

    2011-04-21

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

  20. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    CERN Document Server

    Betta, G -F Dalla; Darbo, G; Gemme, C; La Rosa, A; Pernegger, H; Piemonte, C; Povoli, M; Ronchin, S; Zoboli, A; Zorzi, N

    2011-01-01

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are here discussed.

  1. Studies for the detector control system of the ATLAS pixel at the HL-LHC

    CERN Document Server

    Püllen, L; Boek, J; Kersten, S; Kind, P; Mättig, P; Zeitnitz, C

    2012-01-01

    experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

  2. The Pixels find their way to the heart of ATLAS

    CERN Multimedia

    Kevin Einsweiler

    Since the last e-news article on the Pixel Detector in December 2006, there has been much progress. At that time, we were just about to receive the Beryllium beampipe, and to integrate the innermost layer of the Pixel Detector around it. This innermost layer is referred to as the B-layer because of the powerful role it plays in finding the secondary vertices that are the key signature for the presence of b-quarks, and with somewhat greater difficulty, c-quarks and tau leptons. The integration of the central 7m long beampipe into the Pixel Detector was completed in December, and the B-layer was successfully integrated around it. In January this year, we had largely completed the central 1.5m long detector, including the three barrel layers and the three disk layers on each end of the barrel. Although this region contains all of the 80 million readout channels, it cannot be integrated into the Inner Detector without additional services and infrastructure. Therefore, the next step was to add the Service Panels...

  3. Beam Test Studies of 3D Pixel Sensors Irradiated Non-Uniformly for the ATLAS Forward Physics Detector

    Science.gov (United States)

    2013-02-21

    removal of pile up protons. The AFP tracker unit will consist of an array of six pixel sensors placed at 2-3 mm from the Large Hadron Collider (LHC...Experiment at the CERN Large Hadron Collider ”, JINST 3 S08003 (2008). [2] The ATLAS Collaboration, “Letter of Intent for the Phase-I Upgrade of the ATLAS

  4. Development and validation of a 64 channel front end ASIC for 3D directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the {\\mu}TPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the "Time Over Threshold" information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400MHz by eight LVDS serial links. Eight ASIC were validated on a 2x256 strips of pixels prototype.

  5. Development of a front end ASIC for Dark Matter directional detection with MIMAC

    CERN Document Server

    Richer, J P; Bourrion, O; Grignon, C; Guillaudin, O; Mayet, F; Santos, D

    2009-01-01

    A front end ASIC (BiCMOS-SiGe 0.35 um) has been developed within the framework of the MIMAC detector project, which aims at directional detection of non-baryonic Dark Matter. This search strategy requires 3D reconstruction of low energy (keV) tracks with a gazeous uTPC. The development of this front end ASIC is a key point in this project, allowing the 3D track reconstruction. Each ASIC monitors 16 strips of pixels with charge preamplifiers and their time over threshold is provided in real time by current discriminators via two serializing LVDS links working at 320 MHz. The charge is summed over the 16 strips and provided via a shaper. These specifications have been chosen in order to build an auto triggered electronic. An acquisition board and the related software were developed in order to validate this methodology on a prototype chamber. The prototype detector presents an anode where 2x96 strips are monitored.

  6. New RPC front-end electronics for hades

    CERN Document Server

    Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

    2007-01-01

    Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

  7. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  8. Review of the Neutrino Factory Muon Front End

    CERN Document Server

    Rogers, C

    2011-01-01

    Three major facilities have been proposed for the precision study of neutrino oscillation parameters, the Neutrino Factory, the Betabeam and the Superbeam. Of these the Neutrino Factory offers high precision measurement of oscillations parameters. The Neutrino Factory generates neutrinos by firing protons onto a target in order to produce pions. The pions decay to muons which are captured before being accelerated to 25 GeV and stored in racetrack-shaped rings where they decay to neutrinos. In this note the pion decay channel, longitudinal drift, adiabatic buncher, phase rotation and ionisation cooling system that make up the Neutrino Factory muon front end are reviewed.

  9. Instrument Front-Ends at Fermilab During Run II

    CERN Document Server

    Meyer, Thomas; Voy, Duane; 10.1088/1748-0221/6/11/T11004

    2012-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  10. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  11. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  12. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  13. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Energy Technology Data Exchange (ETDEWEB)

    Noy, M., E-mail: matthew.noy@cern.ch [CERN, CH-1211 Geneva 23 (Switzerland); Aglieri Rinella, G.; Ceccucci, A. [CERN, CH-1211 Geneva 23 (Switzerland); Dellacasa, G. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Fiorini, M. [CERN, CH-1211 Geneva 23 (Switzerland); Garbolino, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Jarron, P. [CERN, CH-1211 Geneva 23 (Switzerland); INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Kaplon, J.; Kluge, A. [CERN, CH-1211 Geneva 23 (Switzerland); Marchetto, F. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Martin, E. [Universite Catholique de Louvain 1, Place de l' Universite BE-1348 Louvain-la-Neuve (Belgium); Mazza, G.; Martoiu, S. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Morel, M.; Perktold, L. [CERN, CH-1211 Geneva 23 (Switzerland); Rivetti, A. [INFN - Torino, via Pietro Giuria 1 IT-10125-Torino (Italy); Tiuraniemi, S. [CERN, CH-1211 Geneva 23 (Switzerland)

    2011-06-15

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16cm{sup 2} active area made of an assembly of 10 readout ASICs bump bonded to a 200{mu}m thick pixel silicon sensor, comprising 18000 pixels of 300{mu}mx300{mu}m. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5Mhit s{sup -1}mm{sup -2} together with an extreme time resolution of 100ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4ns, with a planar silicon sensor operating up to 300V over depletion. Moreover, the radiation level is severe, 2x10{sup 14}1MeVn{sub eq.}cm{sup -2} per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X{sub 0} to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  14. Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Macchiolo, A.; Nisius, R.; Savic, N.; Terzo, S.

    2016-09-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14 ×1015 neq /cm2 . The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.

  15. Diamond Pixel Modules and the ATLAS Beam Conditions Monitor

    CERN Document Server

    Dobos, D

    2011-01-01

    The ATLAS Beam Conditions Monitor’s (BCM) main purpose is to protect the experiments silicon tracker from beam incidents. In total 16 1x1 cm^2 500 um thick diamond pCVD sensors are used in eight positions around the LHC interaction point. They perform time difference measurements with sub nanosecond resolution to distinguish between particles from a collision and spray particles from a beam incident; an abundance of the latter can lead the BCM to provoke an abort of LHC beam. The BCM diamond detector modules, their readout system and the algorithms used to detect beam incidents are described. Results of the BCM operation with circulating LHC beams and it’s commissioning with first LHC collisions are reported.

  16. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    INSPIRE-00237659

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detect or and of the IBL project as...

  17. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  18. The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

    CERN Document Server

    Giordani, MarioPaolo; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  19. The ATLAS Pixel Detector for Run II at the Large Hadron Collider

    CERN Document Server

    Marx, Marilyn; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  20. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    Run-2 of the LHC will provide new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed as well as a new read-out chip within CMOS 130nm technology and with larger area, smaller pixel size and faster readout capability. The new detector is the first large scale application of of 3D detectors and CMOS 130nm technology. An overview of the lessons learned during the IBL project will be presented, focusing on the challenges and highlighting the issues met during the productio...

  1. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2 at the LHC

    CERN Document Server

    Giordani, MarioPaolo; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130 nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented using collision data.

  2. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2

    CERN Document Server

    Ferrere, Didier; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  3. The Layer 1 / Layer 2 readout upgrade for the ATLAS Pixel Detector

    CERN Document Server

    Mullier, Geoffrey; The ATLAS collaboration

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC). The increase of instantaneous luminosity foreseen during the LHC Run 2, will lead to an increased detector occupancy that is expected to saturate the readout links of the outermost layers of the pixel detector: Layers 1 and 2. To ensure a smooth data taking under such conditions, the read out system of the recently installed fourth innermost pixel layer, the Insertable B-Layer, was modified to accomodate the needs of the older detector. The Layer 2 upgrade installation took place during the 2015 winter shutdown, with the Layer 1 installation scheduled for 2016. A report of the successful installation, together with the design of novel dedicated optical to electrical converters and the software and firmware updates will be presented.

  4. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  5. Front End Schaltung zur Online Auswertung von EKG-Signalen

    Directory of Open Access Journals (Sweden)

    E. Ayari

    2007-06-01

    Full Text Available Ein mobiles EKG-System zur Online Auswertung von EKG-Signalen wird dargestellt. Die Auswertung beruht auf ein energiesparendes Verfahren, das den Vorteil einer zulässigen Unterabtastung des Signals bietet und eine Interaktion zwischen der messenden Elektronik und dem funkgebundenen Auswertungsrechner ermöglicht. Diese Interaktion besteht darin, sowohl die Front End Schaltung im EKG-Sensor als auch den im ATmega8L eingebetteten A/D-Wandler vom Auswertungsrechner zu steuern und den Datenbedarf des Rechners dynamisch an die Erfordernisse des Analyseprogramms anzupassen. Das entwickelte EKG-System liefert erfolgreiche Charakterisierungen erfasster Elektrokardiogramme.

    A mobile ecg-system for an online analysis of electrocardiogram signals is presented. The analysis is based on an energy-saving procedure, which offers the advantage of an acceptable undersampling of the signal, and which allows an interaction between the measuring electronic and the radio-bound analysis-computer. In this interaction both the front-end circuit in the ecg-sensor and the A/D converter, which is embedded in the ATmega8L, are steered by the analysis computer. The data requirement of the computer is also dynamically adapted to the requirements of the analysis-program. The developed ecg-system supplies successful characterisations of measured electrocardiograms.

  6. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  7. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  8. FEC-CCS A common Front-End Controller card for the CMS detector electronics

    CERN Document Server

    Kloukinas, Kostas; Drouhin, F; Ljuslin, C; Marchioro, A; Murer, E; Paillard, C; Vlasov, E

    2007-01-01

    The FEC-CCS is a custom made 9U VME64x card for the CMS Off-Detector electronics. The FEC-CCS card is responsible for distributing the fast timing signals and the slow control data, through optical links, to the Front-End system. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS detectors namely the Tracker, ECAL, Preshower, PIXELs, RPCs and TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enable the common utilization by most of the CMS detectors. Results from the integration tests with the detector electronics subsystems and performance measurements will be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.

  9. Low-noise design issues for analog front-end electronics in 130 nm and 90 nm CMOS technologies

    CERN Document Server

    Manghisoni, M; Re, V; Speziali, V; Traversi, G

    2007-01-01

    Deep sub-micron CMOS technologies provide wellestablished solutions to the implementation of low-noise front-end electronics in various detector applications. The IC designers’ effort is presently shifting to 130 nm CMOS technologies, or even to the next technology node, to implement readout integrated circuits for silicon strip and pixel detectors, in view of future HEP applications. In this work the results of noise measurements carried out on CMOS devices in 130 nm and 90 nm commercial processes are presented. The behavior of the 1/f and white noise terms is studied as a function of the device polarity and of the gate length and width. The study is focused on low current density applications where devices are biased in weak or moderate inversion. Data obtained from the measurements provide a powerful tool to establish design criteria in nanoscale CMOS processes for detector front-ends in LHC upgrades.

  10. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  11. Towards third generation pixel readout chips

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@lbl.gov; Mekkaoui, A.; Ganani, D.

    2013-12-11

    We present concepts and prototyping results towards a third generation pixel readout chip. We consider the 130 nm feature size FE-I4 chip, in production for the ATLAS IBL upgrade, to be a second generation chip. A third generation chip would have to go significantly further. A possible direction is to make the IC design generic so that different experiments can configure it to meet significantly different requirements, without the need for everybody to develop their own ASIC from the ground up. In terms of target technology, a demonstrator 500-pixel matrix containing analog front ends only (no complex functionality), was designed and fabricated in 65 nm CMOS and irradiated with protons in December 2011 and May 2012.

  12. Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

    2015-07-01

    The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

  13. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  14. The Pixel Detector of the ATLAS experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is the fourth layer of the Run 2 Pixel Detector, and it was installed in May 2014 between the existing Pixel Detector and the new smaller-radius beam pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project...

  15. Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

    CERN Document Server

    Macchiolo, Anna; Savic, Natascha; Terzo, Stefano

    2016-01-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region...

  16. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Mullier, Geoffrey Andre; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed. A new readout chip has been developed within CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical performan...

  17. Pixel sensors with different pitch layouts for ATLAS Phase-II upgrade

    CERN Document Server

    Dervan, Paul

    2014-01-01

    Different pitch layouts are considered for the pixel detector being designed for the ATLAS up- graded tracking system which will be operating at the High Luminosity LHC. The tracking per- formance in the Endcap pixel regions could benefit from pixel layouts which differ from the ge- ometries used in the barrel region. Also, the performance in different barrel layers and eta regions could be optimised using different pixel sizes. This presentation will report on the development and tests of pitch layouts which could be readout by the FE-I4 ASICs. The pixel geometries in- clude 50 250 m m 2 , 25 500 m m 2 , 100 125 m m 2 , 125 167 m m 2 , 50 2000 m m 2 and 25 2000 m m 2 . The sensors with geometries 50 250 m m 2 , 25 500 m m 2 and 100 125 m m 2 were irradiated and tested at the DESY testbeam. These and other testbeam results as well as results from characterisation of these sensors in the laboratory will be presented

  18. FE-I4, the New ATLAS Pixel Chip for Upgraded LHC Luminosities

    CERN Document Server

    "Barbero, M; The ATLAS collaboration

    2009-01-01

    The new ATLAS pixel chip FE-I4 is being developed for use in upgraded luminosity environments, in the framework of the Insertable B-Layer (IBL) project but also for the outer pixel layers of Super-LHC. FE-I4 is designed in a 130 nm technology and is based on an array of 80 by 336 pixels, each 50×250 μm2 and consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. The digital architecture is based on a 4 pixel unit called region, which allows for a power-efficient, low recording inefficiency design, and provides an elegant solution to the problem of timewalk. The chip periphery contains a control block, powering blocks, a data reformatting unit, an asynchronous storage FIFO, an 8b10b coder and a clock multiplier unit, which handles data transmission up to 160 Mb/s for the IBL.

  19. Recent Results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    Weigell, Philipp

    2013-01-01

    To cope with the higher occupancy and radiation damage at the HL-LHC also the LHC experiments will be upgraded. The ATLAS Planar Pixel Sensor R&D Project (PPS) is an international collaboration of 17 institutions and more than 80 scientists, exploring the feasibility of employing planar pixel sensors for this scenario. Depending on the radius, different pixel concepts are investigated using laboratory and beam test measurements. At small radii the extreme radiation environment and strong space constraints are addressed with very thin pixel sensors active thickness in the range of (75-150) mum, and the development of slim as well as active edges. At larger radii the main challenge is the cost reduction to allow for instrumenting the large area of (7-10) m^2. To reach this goal the pixel productions are being transferred to 6 inch production lines. Additionally, investigated are more cost-efficient and industrialised interconnection techniques as well as the n-in-p technology, which, being a single-sided pr...

  20. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  1. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  2. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  3. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  4. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  5. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  6. Neural-network front ends in unsupervised learning.

    Science.gov (United States)

    Pedrycz, W; Waletzky, J

    1997-01-01

    Proposed is an idea of partial supervision realized in the form of a neural-network front end to the schemes of unsupervised learning (clustering). This neural network leads to an anisotropic nature of the induced feature space. The anisotropic property of the space provides us with some of its local deformation necessary to properly represent labeled data and enhance efficiency of the mechanisms of clustering to be exploited afterwards. The training of the network is completed based upon available labeled patterns-a referential form of the labeling gives rise to reinforcement learning. It is shown that the discussed approach is universal and can be utilized in conjunction with any clustering method. Experimental studies are concentrated on three main categories of unsupervised learning including FUZZY ISODATA, Kohonen self-organizing maps, and hierarchical clustering.

  7. A software-radio front-end for microwave applications

    Science.gov (United States)

    Streifinger, M.; Müller, T.; Luy, J.-F.; Biebl, E. M.

    2003-05-01

    In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC) shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  8. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  9. 3D silicon pixel detectors for the ATLAS Forward Physics experiment

    CERN Document Server

    INSPIRE-00397348; Cavallaro, E.; Grinstein, S.; López Paz, I.

    2015-01-01

    The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2-3 mm). This implies the need of slim edges of about 100-200 $\\mu$m width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 $\\mu$m width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 10$^{15}$ n$_{eq}$/cm$^2$ with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al ma...

  10. SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades

    CERN Document Server

    Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P

    2012-01-01

    We present the results of the characterization of pixel modules composed of 75 μm thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is explored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module, ICVs are etched over the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation is presented.

  11. A neural network clustering algorithm for the ATLAS silicon pixel detector

    CERN Document Server

    Aad, Georges; Abdallah, Jalal; Abdel Khalek, Samah; Abdinov, Ovsat; Aben, Rosemarie; Abi, Babak; Abolins, Maris; AbouZeid, Ossama; Abramowicz, Halina; Abreu, Henso; Abreu, Ricardo; Abulaiti, Yiming; Acharya, Bobby Samir; Adamczyk, Leszek; Adams, David; Adelman, Jahred; Adomeit, Stefanie; Adye, Tim; Agatonovic-Jovin, Tatjana; Aguilar-Saavedra, Juan Antonio; Agustoni, Marco; Ahlen, Steven; Ahmadov, Faig; Aielli, Giulio; Akerstedt, Henrik; Åkesson, Torsten Paul Ake; Akimoto, Ginga; Akimov, Andrei; Alberghi, Gian Luigi; Albert, Justin; Albrand, Solveig; Alconada Verzini, Maria Josefina; Aleksa, Martin; Aleksandrov, Igor; Alexa, Calin; Alexander, Gideon; Alexandre, Gauthier; Alexopoulos, Theodoros; Alhroob, Muhammad; Alimonti, Gianluca; Alio, Lion; Alison, John; Allbrooke, Benedict; Allison, Lee John; Allport, Phillip; Almond, John; Aloisio, Alberto; Alonso, Alejandro; Alonso, Francisco; Alpigiani, Cristiano; Altheimer, Andrew David; Alvarez Gonzalez, Barbara; Alviggi, Mariagrazia; Amako, Katsuya; Amaral Coutinho, Yara; Amelung, Christoph; Amidei, Dante; Amor Dos Santos, Susana Patricia; Amorim, Antonio; Amoroso, Simone; Amram, Nir; Amundsen, Glenn; Anastopoulos, Christos; Ancu, Lucian Stefan; Andari, Nansi; Andeen, Timothy; Anders, Christoph Falk; Anders, Gabriel; Anderson, Kelby; Andreazza, Attilio; Andrei, George Victor; Anduaga, Xabier; Angelidakis, Stylianos; Angelozzi, Ivan; Anger, Philipp; Angerami, Aaron; Anghinolfi, Francis; Anisenkov, Alexey; Anjos, Nuno; Annovi, Alberto; Antonaki, Ariadni; Antonelli, Mario; Antonov, Alexey; Antos, Jaroslav; Anulli, Fabio; Aoki, Masato; Aperio Bella, Ludovica; Apolle, Rudi; Arabidze, Giorgi; Aracena, Ignacio; Arai, Yasuo; Araque, Juan Pedro; Arce, Ayana; Arguin, Jean-Francois; Argyropoulos, Spyridon; Arik, Metin; Armbruster, Aaron James; Arnaez, Olivier; Arnal, Vanessa; Arnold, Hannah; Arratia, Miguel; Arslan, Ozan; Artamonov, Andrei; Artoni, Giacomo; Asai, Shoji; Asbah, Nedaa; Ashkenazi, Adi; Åsman, Barbro; Asquith, Lily; Assamagan, Ketevi; Astalos, Robert; Atkinson, Markus; Atlay, Naim Bora; Auerbach, Benjamin; Augsten, Kamil; Aurousseau, Mathieu; Avolio, Giuseppe; Azuelos, Georges; Azuma, Yuya; Baak, Max; Baas, Alessandra; Bacci, Cesare; Bachacou, Henri; Bachas, Konstantinos; Backes, Moritz; Backhaus, Malte; Backus Mayes, John; Badescu, Elisabeta; Bagiacchi, Paolo; Bagnaia, Paolo; Bai, Yu; Bain, Travis; Baines, John; Baker, Oliver Keith; Balek, Petr; Balli, Fabrice; Banas, Elzbieta; Banerjee, Swagato; Bannoura, Arwa A E; Bansal, Vikas; Bansil, Hardeep Singh; Barak, Liron; Baranov, Sergei; Barberio, Elisabetta Luigia; Barberis, Dario; Barbero, Marlon; Barillari, Teresa; Barisonzi, Marcello; Barklow, Timothy; Barlow, Nick; Barnett, Bruce; Barnett, Michael; Barnovska, Zuzana; Baroncelli, Antonio; Barone, Gaetano; Barr, Alan; Barreiro, Fernando; Barreiro Guimarães da Costa, João; Bartoldus, Rainer; Barton, Adam Edward; Bartos, Pavol; Bartsch, Valeria; Bassalat, Ahmed; Basye, Austin; Bates, Richard; Batkova, Lucia; Batley, Richard; Battaglia, Marco; Battistin, Michele; Bauer, Florian; Bawa, Harinder Singh; Beau, Tristan; Beauchemin, Pierre-Hugues; Beccherle, Roberto; Bechtle, Philip; Beck, Hans Peter; Becker, Anne Kathrin; Becker, Sebastian; Beckingham, Matthew; Becot, Cyril; Beddall, Andrew; Beddall, Ayda; Bedikian, Sourpouhi; Bednyakov, Vadim; Bee, Christopher; Beemster, Lars; Beermann, Thomas; Begel, Michael; Behr, Katharina; Belanger-Champagne, Camille; Bell, Paul; Bell, William; Bella, Gideon; Bellagamba, Lorenzo; Bellerive, Alain; Bellomo, Massimiliano; Belotskiy, Konstantin; Beltramello, Olga; Benary, Odette; Benchekroun, Driss; Bendtz, Katarina; Benekos, Nektarios; Benhammou, Yan; Benhar Noccioli, Eleonora; Benitez Garcia, Jorge-Armando; Benjamin, Douglas; Bensinger, James; Benslama, Kamal; Bentvelsen, Stan; Berge, David; Bergeaas Kuutmann, Elin; Berger, Nicolas; Berghaus, Frank; Beringer, Jürg; Bernard, Clare; Bernat, Pauline; Bernius, Catrin; Bernlochner, Florian Urs; Berry, Tracey; Berta, Peter; Bertella, Claudia; Bertoli, Gabriele; Bertolucci, Federico; Bertsche, David; Besana, Maria Ilaria; Besjes, Geert-Jan; Bessidskaia, Olga; Bessner, Martin Florian; Besson, Nathalie; Betancourt, Christopher; Bethke, Siegfried; Bhimji, Wahid; Bianchi, Riccardo-Maria; Bianchini, Louis; Bianco, Michele; Biebel, Otmar; Bieniek, Stephen Paul; Bierwagen, Katharina; Biesiada, Jed; Biglietti, Michela; Bilbao De Mendizabal, Javier; Bilokon, Halina; Bindi, Marcello; Binet, Sebastien; Bingul, Ahmet; Bini, Cesare; Black, Curtis; Black, James; Black, Kevin; Blackburn, Daniel; Blair, Robert; Blanchard, Jean-Baptiste; Blazek, Tomas; Bloch, Ingo; Blocker, Craig; Blum, Walter; Blumenschein, Ulrike; Bobbink, Gerjan; Bobrovnikov, Victor; Bocchetta, Simona Serena; Bocci, Andrea; Bock, Christopher; Boddy, Christopher Richard; Boehler, Michael; Boek, Thorsten Tobias; Bogaerts, Joannes Andreas; Bogdanchikov, Alexander; Bogouch, Andrei; Bohm, Christian; Bohm, Jan; Boisvert, Veronique; Bold, Tomasz; Boldea, Venera; Boldyrev, Alexey; Bomben, Marco; Bona, Marcella; Boonekamp, Maarten; Borisov, Anatoly; Borissov, Guennadi; Borri, Marcello; Borroni, Sara; Bortfeldt, Jonathan; Bortolotto, Valerio; Bos, Kors; Boscherini, Davide; Bosman, Martine; Boterenbrood, Hendrik; Boudreau, Joseph; Bouffard, Julian; Bouhova-Thacker, Evelina Vassileva; Boumediene, Djamel Eddine; Bourdarios, Claire; Bousson, Nicolas; Boutouil, Sara; Boveia, Antonio; Boyd, James; Boyko, Igor; Bracinik, Juraj; Brandt, Andrew; Brandt, Gerhard; Brandt, Oleg; Bratzler, Uwe; Brau, Benjamin; Brau, James; Braun, Helmut; Brazzale, Simone Federico; Brelier, Bertrand; Brendlinger, Kurt; Brennan, Amelia Jean; Brenner, Richard; Bressler, Shikma; Bristow, Kieran; Bristow, Timothy Michael; Britton, Dave; Brochu, Frederic; Brock, Ian; Brock, Raymond; Bromberg, Carl; Bronner, Johanna; Brooijmans, Gustaaf; Brooks, Timothy; Brooks, William; Brosamer, Jacquelyn; Brost, Elizabeth; Brown, Jonathan; Bruckman de Renstrom, Pawel; Bruncko, Dusan; Bruneliere, Renaud; Brunet, Sylvie; Bruni, Alessia; Bruni, Graziano; Bruschi, Marco; Bryngemark, Lene; Buanes, Trygve; Buat, Quentin; Bucci, Francesca; Buchholz, Peter; Buckingham, Ryan; Buckley, Andrew; Buda, Stelian Ioan; Budagov, Ioulian; Buehrer, Felix; Bugge, Lars; Bugge, Magnar Kopangen; Bulekov, Oleg; Bundock, Aaron Colin; Burckhart, Helfried; Burdin, Sergey; Burghgrave, Blake; Burke, Stephen; Burmeister, Ingo; Busato, Emmanuel; Büscher, Daniel; Büscher, Volker; Bussey, Peter; Buszello, Claus-Peter; Butler, Bart; Butler, John; Butt, Aatif Imtiaz; Buttar, Craig; Butterworth, Jonathan; Butti, Pierfrancesco; Buttinger, William; Buzatu, Adrian; Byszewski, Marcin; Cabrera Urbán, Susana; Caforio, Davide; Cakir, Orhan; Calafiura, Paolo; Calandri, Alessandro; Calderini, Giovanni; Calfayan, Philippe; Calkins, Robert; Caloba, Luiz; Calvet, David; Calvet, Samuel; Camacho Toro, Reina; Camarda, Stefano; Cameron, David; Caminada, Lea Michaela; Caminal Armadans, Roger; Campana, Simone; Campanelli, Mario; Campoverde, Angel; Canale, Vincenzo; Canepa, Anadi; Cano Bret, Marc; Cantero, Josu; Cantrill, Robert; Cao, Tingting; Capeans Garrido, Maria Del Mar; Caprini, Irinel; Caprini, Mihai; Capua, Marcella; Caputo, Regina; Cardarelli, Roberto; Carli, Tancredi; Carlino, Gianpaolo; Carminati, Leonardo; Caron, Sascha; Carquin, Edson; Carrillo-Montoya, German D; Carter, Janet; Carvalho, João; Casadei, Diego; Casado, Maria Pilar; Casolino, Mirkoantonio; Castaneda-Miranda, Elizabeth; Castelli, Angelantonio; Castillo Gimenez, Victoria; Castro, Nuno Filipe; Catastini, Pierluigi; Catinaccio, Andrea; Catmore, James; Cattai, Ariella; Cattani, Giordano; Caughron, Seth; Cavaliere, Viviana; Cavalli, Donatella; Cavalli-Sforza, Matteo; Cavasinni, Vincenzo; Ceradini, Filippo; Cerio, Benjamin; Cerny, Karel; Cerqueira, Augusto Santiago; Cerri, Alessandro; Cerrito, Lucio; Cerutti, Fabio; Cerv, Matevz; Cervelli, Alberto; Cetin, Serkant Ali; Chafaq, Aziz; Chakraborty, Dhiman; Chalupkova, Ina; Chang, Philip; Chapleau, Bertrand; Chapman, John Derek; Charfeddine, Driss; Charlton, Dave; Chau, Chav Chhiv; Chavez Barajas, Carlos Alberto; Cheatham, Susan; Chegwidden, Andrew; Chekanov, Sergei; Chekulaev, Sergey; Chelkov, Gueorgui; Chelstowska, Magda Anna; Chen, Chunhui; Chen, Hucheng; Chen, Karen; Chen, Liming; Chen, Shenjian; Chen, Xin; Chen, Yujiao; Cheng, Hok Chuen; Cheng, Yangyang; Cheplakov, Alexander; Cherkaoui El Moursli, Rajaa; Chernyatin, Valeriy; Cheu, Elliott; Chevalier, Laurent; Chiarella, Vitaliano; Chiefari, Giovanni; Childers, John Taylor; Chilingarov, Alexandre; Chiodini, Gabriele; Chisholm, Andrew; Chislett, Rebecca Thalatta; Chitan, Adrian; Chizhov, Mihail; Chouridou, Sofia; Chow, Bonnie Kar Bo; Chromek-Burckhart, Doris; Chu, Ming-Lee; Chudoba, Jiri; Chwastowski, Janusz; Chytka, Ladislav; Ciapetti, Guido; Ciftci, Abbas Kenan; Ciftci, Rena; Cinca, Diane; Cindro, Vladimir; Ciocio, Alessandra; Cirkovic, Predrag; Citron, Zvi Hirsh; Citterio, Mauro; Ciubancan, Mihai; Clark, Allan G; Clark, Philip James; Clarke, Robert; Cleland, Bill; Clemens, Jean-Claude; Clement, Christophe; Coadou, Yann; Cobal, Marina; Coccaro, Andrea; Cochran, James H; Coffey, Laurel; Cogan, Joshua Godfrey; Coggeshall, James; Cole, Brian; Cole, Stephen; Colijn, Auke-Pieter; Collot, Johann; Colombo, Tommaso; Colon, German; Compostella, Gabriele; Conde Muiño, Patricia; Coniavitis, Elias; Conidi, Maria Chiara; Connell, Simon Henry; Connelly, Ian; Consonni, Sofia Maria; Consorti, Valerio; Constantinescu, Serban; Conta, Claudio; Conti, Geraldine; Conventi, Francesco; Cooke, Mark; Cooper, Ben; Cooper-Sarkar, Amanda; Cooper-Smith, Neil; Copic, Katherine; Cornelissen, Thijs; Corradi, Massimo; Corriveau, Francois; Corso-Radu, Alina; Cortes-Gonzalez, Arely; Cortiana, Giorgio; Costa, Giuseppe; Costa, María José; Costanzo, Davide; Côté, David; Cottin, Giovanna; Cowan, Glen; Cox, Brian; Cranmer, Kyle; Cree, Graham; Crépé-Renaudin, Sabine; Crescioli, Francesco; Cribbs, Wayne Allen; Crispin Ortuzar, Mireia; Cristinziani, Markus; Croft, Vince; Crosetti, Giovanni; Cuciuc, Constantin-Mihai; Cuhadar Donszelmann, Tulay; Cummings, Jane; Curatolo, Maria; Cuthbert, Cameron; Czirr, Hendrik; Czodrowski, Patrick; Czyczula, Zofia; D'Auria, Saverio; D'Onofrio, Monica; Da Cunha Sargedas De Sousa, Mario Jose; Da Via, Cinzia; Dabrowski, Wladyslaw; Dafinca, Alexandru; Dai, Tiesheng; Dale, Orjan; Dallaire, Frederick; Dallapiccola, Carlo; Dam, Mogens; Daniells, Andrew Christopher; Dano Hoffmann, Maria; Dao, Valerio; Darbo, Giovanni; Darmora, Smita; Dassoulas, James; Dattagupta, Aparajita; Davey, Will; David, Claire; Davidek, Tomas; Davies, Eleanor; Davies, Merlin; Davignon, Olivier; Davison, Adam; Davison, Peter; Davygora, Yuriy; Dawe, Edmund; Dawson, Ian; Daya-Ishmukhametova, Rozmin; De, Kaushik; de Asmundis, Riccardo; De Castro, Stefano; De Cecco, Sandro; De Groot, Nicolo; de Jong, Paul; De la Torre, Hector; De Lorenzi, Francesco; De Nooij, Lucie; De Pedis, Daniele; De Salvo, Alessandro; De Sanctis, Umberto; De Santo, Antonella; De Vivie De Regie, Jean-Baptiste; Dearnaley, William James; Debbe, Ramiro; Debenedetti, Chiara; Dechenaux, Benjamin; Dedovich, Dmitri; Deigaard, Ingrid; Del Peso, Jose; Del Prete, Tarcisio; Deliot, Frederic; Delitzsch, Chris Malena; Deliyergiyev, Maksym; Dell'Acqua, Andrea; Dell'Asta, Lidia; Dell'Orso, Mauro; Della Pietra, Massimo; della Volpe, Domenico; Delmastro, Marco; Delsart, Pierre-Antoine; Deluca, Carolina; Demers, Sarah; Demichev, Mikhail; Demilly, Aurelien; Denisov, Sergey; Derendarz, Dominik; Derkaoui, Jamal Eddine; Derue, Frederic; Dervan, Paul; Desch, Klaus Kurt; Deterre, Cecile; Deviveiros, Pier-Olivier; Dewhurst, Alastair; Dhaliwal, Saminder; Di Ciaccio, Anna; Di Ciaccio, Lucia; Di Domenico, Antonio; Di Donato, Camilla; Di Girolamo, Alessandro; Di Girolamo, Beniamino; Di Mattia, Alessandro; Di Micco, Biagio; Di Nardo, Roberto; Di Simone, Andrea; Di Sipio, Riccardo; Di Valentino, David; Dias, Flavia; Diaz, Marco Aurelio; Diehl, Edward; Dietrich, Janet; Dietzsch, Thorsten; Diglio, Sara; Dimitrievska, Aleksandra; Dingfelder, Jochen; Dionisi, Carlo; Dita, Petre; Dita, Sanda; Dittus, Fridolin; Djama, Fares; Djobava, Tamar; do Vale, Maria Aline Barros; Do Valle Wemans, André; Doan, Thi Kieu Oanh; Dobos, Daniel; Doglioni, Caterina; Doherty, Tom; Dohmae, Takeshi; Dolejsi, Jiri; Dolezal, Zdenek; Dolgoshein, Boris; Donadelli, Marisilvia; Donati, Simone; Dondero, Paolo; Donini, Julien; Dopke, Jens; Doria, Alessandra; Dova, Maria-Teresa; Doyle, Tony; Dris, Manolis; Dubbert, Jörg; Dube, Sourabh; Dubreuil, Emmanuelle; Duchovni, Ehud; Duckeck, Guenter; Ducu, Otilia Anamaria; Duda, Dominik; Dudarev, Alexey; Dudziak, Fanny; Duflot, Laurent; Duguid, Liam; Dührssen, Michael; Dunford, Monica; Duran Yildiz, Hatice; Düren, Michael; Durglishvili, Archil; Dwuznik, Michal; Dyndal, Mateusz; Ebke, Johannes; Edson, William; Edwards, Nicholas Charles; Ehrenfeld, Wolfgang; Eifert, Till; Eigen, Gerald; Einsweiler, Kevin; Ekelof, Tord; El Kacimi, Mohamed; Ellert, Mattias; Elles, Sabine; Ellinghaus, Frank; Ellis, Nicolas; Elmsheuser, Johannes; Elsing, Markus; Emeliyanov, Dmitry; Enari, Yuji; Endner, Oliver Chris; Endo, Masaki; Engelmann, Roderich; Erdmann, Johannes; Ereditato, Antonio; Eriksson, Daniel; Ernis, Gunar; Ernst, Jesse; Ernst, Michael; Ernwein, Jean; Errede, Deborah; Errede, Steven; Ertel, Eugen; Escalier, Marc; Esch, Hendrik; Escobar, Carlos; Esposito, Bellisario; Etienvre, Anne-Isabelle; Etzion, Erez; Evans, Hal; Ezhilov, Alexey; Fabbri, Laura; Facini, Gabriel; Fakhrutdinov, Rinat; Falciano, Speranza; Falla, Rebecca Jane; Faltova, Jana; Fang, Yaquan; Fanti, Marcello; Farbin, Amir; Farilla, Addolorata; Farooque, Trisha; Farrell, Steven; Farrington, Sinead; Farthouat, Philippe; Fassi, Farida; Fassnacht, Patrick; Fassouliotis, Dimitrios; Favareto, Andrea; Fayard, Louis; Federic, Pavol; Fedin, Oleg; Fedorko, Wojciech; Fehling-Kaschek, Mirjam; Feigl, Simon; Feligioni, Lorenzo; Feng, Cunfeng; Feng, Eric; Feng, Haolu; Fenyuk, Alexander; Fernandez Perez, Sonia; Ferrag, Samir; Ferrando, James; Ferrari, Arnaud; Ferrari, Pamela; Ferrari, Roberto; Ferreira de Lima, Danilo Enoque; Ferrer, Antonio; Ferrere, Didier; Ferretti, Claudio; Ferretto Parodi, Andrea; Fiascaris, Maria; Fiedler, Frank; Filipčič, Andrej; Filipuzzi, Marco; Filthaut, Frank; Fincke-Keeler, Margret; Finelli, Kevin Daniel; Fiolhais, Miguel; Fiorini, Luca; Firan, Ana; Fischer, Adam; Fischer, Julia; Fisher, Wade Cameron; Fitzgerald, Eric Andrew; Flechl, Martin; Fleck, Ivor; Fleischmann, Philipp; Fleischmann, Sebastian; Fletcher, Gareth Thomas; Fletcher, Gregory; Flick, Tobias; Floderus, Anders; Flores Castillo, Luis; Florez Bustos, Andres Carlos; Flowerdew, Michael; Formica, Andrea; Forti, Alessandra; Fortin, Dominique; Fournier, Daniel; Fox, Harald; Fracchia, Silvia; Francavilla, Paolo; Franchini, Matteo; Franchino, Silvia; Francis, David; Franklin, Melissa; Franz, Sebastien; Fraternali, Marco; French, Sky; Friedrich, Conrad; Friedrich, Felix; Froidevaux, Daniel; Frost, James; Fukunaga, Chikara; Fullana Torregrosa, Esteban; Fulsom, Bryan Gregory; Fuster, Juan; Gabaldon, Carolina; Gabizon, Ofir; Gabrielli, Alessandro; Gabrielli, Andrea; Gadatsch, Stefan; Gadomski, Szymon; Gagliardi, Guido; Gagnon, Pauline; Galea, Cristina; Galhardo, Bruno; Gallas, Elizabeth; Gallo, Valentina Santina; Gallop, Bruce; Gallus, Petr; Galster, Gorm Aske Gram Krohn; Gan, KK; Gandrajula, Reddy Pratap; Gao, Jun; Gao, Yongsheng; Garay Walls, Francisca; Garberson, Ford; García, Carmen; García Navarro, José Enrique; Garcia-Sciveres, Maurice; Gardner, Robert; Garelli, Nicoletta; Garonne, Vincent; Gatti, Claudio; Gaudio, Gabriella; Gaur, Bakul; Gauthier, Lea; Gauzzi, Paolo; Gavrilenko, Igor; Gay, Colin; Gaycken, Goetz; Gazis, Evangelos; Ge, Peng; Gecse, Zoltan; Gee, Norman; Geerts, Daniël Alphonsus Adrianus; Geich-Gimbel, Christoph; Gellerstedt, Karl; Gemme, Claudia; Gemmell, Alistair; Genest, Marie-Hélène; Gentile, Simonetta; George, Matthias; George, Simon; Gerbaudo, Davide; Gershon, Avi; Ghazlane, Hamid; Ghodbane, Nabil; Giacobbe, Benedetto; Giagu, Stefano; Giangiobbe, Vincent; Giannetti, Paola; Gianotti, Fabiola; Gibbard, Bruce; Gibson, Stephen; Gilchriese, Murdock; Gillam, Thomas; Gillberg, Dag; Gilles, Geoffrey; Gingrich, Douglas; Giokaris, Nikos; Giordani, MarioPaolo; Giordano, Raffaele; Giorgi, Filippo Maria; Giorgi, Francesco Michelangelo; Giraud, Pierre-Francois; Giugni, Danilo; Giuliani, Claudia; Giulini, Maddalena; Gjelsten, Børge Kile; Gkaitatzis, Stamatios; Gkialas, Ioannis; Gladilin, Leonid; Glasman, Claudia; Glatzer, Julian; Glaysher, Paul; Glazov, Alexandre; Glonti, George; Goblirsch-Kolb, Maximilian; Goddard, Jack Robert; Godfrey, Jennifer; Godlewski, Jan; Goeringer, Christian; Goldfarb, Steven; Golling, Tobias; Golubkov, Dmitry; Gomes, Agostinho; Gomez Fajardo, Luz Stella; Gonçalo, Ricardo; Goncalves Pinto Firmino Da Costa, Joao; Gonella, Laura; González de la Hoz, Santiago; Gonzalez Parra, Garoe; Gonzalez-Sevilla, Sergio; Goossens, Luc; Gorbounov, Petr Andreevich; Gordon, Howard; Gorelov, Igor; Gorini, Benedetto; Gorini, Edoardo; Gorišek, Andrej; Gornicki, Edward; Goshaw, Alfred; Gössling, Claus; Gostkin, Mikhail Ivanovitch; Gouighri, Mohamed; Goujdami, Driss; Goulette, Marc Phillippe; Goussiou, Anna; Goy, Corinne; Gozpinar, Serdar; Grabas, Herve Marie Xavier; Graber, Lars; Grabowska-Bold, Iwona; Grafström, Per; Grahn, Karl-Johan; Gramling, Johanna; Gramstad, Eirik; Grancagnolo, Sergio; Grassi, Valerio; Gratchev, Vadim; Gray, Heather; Graziani, Enrico; Grebenyuk, Oleg; Greenwood, Zeno Dixon; Gregersen, Kristian; Gregor, Ingrid-Maria; Grenier, Philippe; Griffiths, Justin; Grillo, Alexander; Grimm, Kathryn; Grinstein, Sebastian; Gris, Philippe Luc Yves; Grishkevich, Yaroslav; Grivaz, Jean-Francois; Grohs, Johannes Philipp; Grohsjean, Alexander; Gross, Eilam; Grosse-Knetter, Joern; Grossi, Giulio Cornelio; Groth-Jensen, Jacob; Grout, Zara Jane; Guan, Liang; Guescini, Francesco; Guest, Daniel; Gueta, Orel; Guicheney, Christophe; Guido, Elisa; Guillemin, Thibault; Guindon, Stefan; Gul, Umar; Gumpert, Christian; Gunther, Jaroslav; Guo, Jun; Gupta, Shaun; Gutierrez, Phillip; Gutierrez Ortiz, Nicolas Gilberto; Gutschow, Christian; Guttman, Nir; Guyot, Claude; Gwenlan, Claire; Gwilliam, Carl; Haas, Andy; Haber, Carl; Hadavand, Haleh Khani; Haddad, Nacim; Haefner, Petra; Hageböck, Stephan; Hajduk, Zbigniew; Hakobyan, Hrachya; Haleem, Mahsana; Hall, David; Halladjian, Garabed; Hamacher, Klaus; Hamal, Petr; Hamano, Kenji; Hamer, Matthias; Hamilton, Andrew; Hamilton, Samuel; Hamnett, Phillip George; Han, Liang; Hanagaki, Kazunori; Hanawa, Keita; Hance, Michael; Hanke, Paul; Hanna, Remie; Hansen, Jørgen Beck; Hansen, Jorn Dines; Hansen, Peter Henrik; Hara, Kazuhiko; Hard, Andrew; Harenberg, Torsten; Hariri, Faten; Harkusha, Siarhei; Harper, Devin; Harrington, Robert; Harris, Orin; Harrison, Paul Fraser; Hartjes, Fred; Hasegawa, Satoshi; Hasegawa, Yoji; Hasib, A; Hassani, Samira; Haug, Sigve; Hauschild, Michael; Hauser, Reiner; Havranek, Miroslav; Hawkes, Christopher; Hawkings, Richard John; Hawkins, Anthony David; Hayashi, Takayasu; Hayden, Daniel; Hays, Chris; Hayward, Helen; Haywood, Stephen; Head, Simon; Heck, Tobias; Hedberg, Vincent; Heelan, Louise; Heim, Sarah; Heim, Timon; Heinemann, Beate; Heinrich, Lukas; Hejbal, Jiri; Helary, Louis; Heller, Claudio; Heller, Matthieu; Hellman, Sten; Hellmich, Dennis; Helsens, Clement; Henderson, James; Henderson, Robert; Heng, Yang; Hengler, Christopher; Henrichs, Anna; Henriques Correia, Ana Maria; Henrot-Versille, Sophie; Hensel, Carsten; Herbert, Geoffrey Henry; Hernández Jiménez, Yesenia; Herrberg-Schubert, Ruth; Herten, Gregor; Hertenberger, Ralf; Hervas, Luis; Hesketh, Gavin Grant; Hessey, Nigel; Hickling, Robert; Higón-Rodriguez, Emilio; Hill, Ewan; Hill, John; Hiller, Karl Heinz; Hillert, Sonja; Hillier, Stephen; Hinchliffe, Ian; Hines, Elizabeth; Hirose, Minoru; Hirschbuehl, Dominic; Hobbs, John; Hod, Noam; Hodgkinson, Mark; Hodgson, Paul; Hoecker, Andreas; Hoeferkamp, Martin; Hoffman, Julia; Hoffmann, Dirk; Hofmann, Julia Isabell; Hohlfeld, Marc; Holmes, Tova Ray; Hong, Tae Min; Hooft van Huysduynen, Loek; Hostachy, Jean-Yves; Hou, Suen; Hoummada, Abdeslam; Howard, Jacob; Howarth, James; Hrabovsky, Miroslav; Hristova, Ivana; Hrivnac, Julius; Hryn'ova, Tetiana; Hsu, Catherine; Hsu, Pai-hsien Jennifer; Hsu, Shih-Chieh; Hu, Diedi; Hu, Xueye; Huang, Yanping; Hubacek, Zdenek; Hubaut, Fabrice; Huegging, Fabian; Huffman, Todd Brian; Hughes, Emlyn; Hughes, Gareth; Huhtinen, Mika; Hülsing, Tobias Alexander; Hurwitz, Martina; Huseynov, Nazim; Huston, Joey; Huth, John; Iacobucci, Giuseppe; Iakovidis, Georgios; Ibragimov, Iskander; Iconomidou-Fayard, Lydia; Ideal, Emma; Iengo, Paolo; Igonkina, Olga; Iizawa, Tomoya; Ikegami, Yoichi; Ikematsu, Katsumasa; Ikeno, Masahiro; Ilchenko, Iurii; Iliadis, Dimitrios; Ilic, Nikolina; Inamaru, Yuki; Ince, Tayfun; Ioannou, Pavlos; Iodice, Mauro; Iordanidou, Kalliopi; Ippolito, Valerio; Irles Quiles, Adrian; Isaksson, Charlie; Ishino, Masaya; Ishitsuka, Masaki; Ishmukhametov, Renat; Issever, Cigdem; Istin, Serhat; Iturbe Ponce, Julia Mariana; Iuppa, Roberto; Ivarsson, Jenny; Iwanski, Wieslaw; Iwasaki, Hiroyuki; Izen, Joseph; Izzo, Vincenzo; Jackson, Brett; Jackson, Matthew; Jackson, Paul; Jaekel, Martin; Jain, Vivek; Jakobs, Karl; Jakobsen, Sune; Jakoubek, Tomas; Jakubek, Jan; Jamin, David Olivier; Jana, Dilip; Jansen, Eric; Jansen, Hendrik; Janssen, Jens; Janus, Michel; Jarlskog, Göran; Javadov, Namig; Javůrek, Tomáš; Jeanty, Laura; Jejelava, Juansher; Jeng, Geng-yuan; Jennens, David; Jenni, Peter; Jentzsch, Jennifer; Jeske, Carl; Jézéquel, Stéphane; Ji, Haoshuang; Ji, Weina; Jia, Jiangyong; Jiang, Yi; Jimenez Belenguer, Marcos; Jin, Shan; Jinaru, Adam; Jinnouchi, Osamu; Joergensen, Morten Dam; Johansson, Erik; Johansson, Per; Johns, Kenneth; Jon-And, Kerstin; Jones, Graham; Jones, Roger; Jones, Tim; Jongmanns, Jan; Jorge, Pedro; Joshi, Kiran Daniel; Jovicevic, Jelena; Ju, Xiangyang; Jung, Christian; Jungst, Ralph Markus; Jussel, Patrick; Juste Rozas, Aurelio; Kaci, Mohammed; Kaczmarska, Anna; Kado, Marumi; Kagan, Harris; Kagan, Michael; Kajomovitz, Enrique; Kalderon, Charles William; Kama, Sami; Kamenshchikov, Andrey; Kanaya, Naoko; Kaneda, Michiru; Kaneti, Steven; Kantserov, Vadim; Kanzaki, Junichi; Kaplan, Benjamin; Kapliy, Anton; Kar, Deepak; Karakostas, Konstantinos; Karastathis, Nikolaos; Karnevskiy, Mikhail; Karpov, Sergey; Karpova, Zoya; Karthik, Krishnaiyengar; Kartvelishvili, Vakhtang; Karyukhin, Andrey; Kashif, Lashkar; Kasieczka, Gregor; Kass, Richard; Kastanas, Alex; Kataoka, Yousuke; Katre, Akshay; Katzy, Judith; Kaushik, Venkatesh; Kawagoe, Kiyotomo; Kawamoto, Tatsuo; Kawamura, Gen; Kazama, Shingo; Kazanin, Vassili; Kazarinov, Makhail; Keeler, Richard; Kehoe, Robert; Keil, Markus; Keller, John; Kempster, Jacob Julian; Keoshkerian, Houry; Kepka, Oldrich; Kerševan, Borut Paul; Kersten, Susanne; Kessoku, Kohei; Keung, Justin; Khalil-zada, Farkhad; Khandanyan, Hovhannes; Khanov, Alexander; Khodinov, Alexander; Khomich, Andrei; Khoo, Teng Jian; Khoriauli, Gia; Khoroshilov, Andrey; Khovanskiy, Valery; Khramov, Evgeniy; Khubua, Jemal; Kim, Hee Yeun; Kim, Hyeon Jin; Kim, Shinhong; Kimura, Naoki; Kind, Oliver; King, Barry; King, Matthew; King, Robert Steven Beaufoy; King, Samuel Burton; Kirk, Julie; Kiryunin, Andrey; Kishimoto, Tomoe; Kisielewska, Danuta; Kiss, Florian; Kittelmann, Thomas; Kiuchi, Kenji; Kladiva, Eduard; Klein, Max; Klein, Uta; Kleinknecht, Konrad; Klimek, Pawel; Klimentov, Alexei; Klingenberg, Reiner; Klinger, Joel Alexander; Klioutchnikova, Tatiana; Klok, Peter; Kluge, Eike-Erik; Kluit, Peter; Kluth, Stefan; Kneringer, Emmerich; Knoops, Edith; Knue, Andrea; Kobayashi, Dai; Kobayashi, Tomio; Kobel, Michael; Kocian, Martin; Kodys, Peter; Koevesarki, Peter; Koffas, Thomas; Koffeman, Els; Kogan, Lucy Anne; Kohlmann, Simon; Kohout, Zdenek; Kohriki, Takashi; Koi, Tatsumi; Kolanoski, Hermann; Koletsou, Iro; Koll, James; Komar, Aston; Komori, Yuto; Kondo, Takahiko; Kondrashova, Nataliia; Köneke, Karsten; König, Adriaan; König, Sebastian; Kono, Takanori; Konoplich, Rostislav; Konstantinidis, Nikolaos; Kopeliansky, Revital; Koperny, Stefan; Köpke, Lutz; Kopp, Anna Katharina; Korcyl, Krzysztof; Kordas, Kostantinos; Korn, Andreas; Korol, Aleksandr; Korolkov, Ilya; Korolkova, Elena; Korotkov, Vladislav; Kortner, Oliver; Kortner, Sandra; Kostyukhin, Vadim; Kotov, Vladislav; Kotwal, Ashutosh; Kourkoumelis, Christine; Kouskoura, Vasiliki; Koutsman, Alex; Kowalewski, Robert Victor; Kowalski, Tadeusz; Kozanecki, Witold; Kozhin, Anatoly; Kral, Vlastimil; Kramarenko, Viktor; Kramberger, Gregor; Krasnopevtsev, Dimitriy; Krasny, Mieczyslaw Witold; Krasznahorkay, Attila; Kraus, Jana; Kravchenko, Anton; Kreiss, Sven; Kretz, Moritz; Kretzschmar, Jan; Kreutzfeldt, Kristof; Krieger, Peter; Kroeninger, Kevin; Kroha, Hubert; Kroll, Joe; Kroseberg, Juergen; Krstic, Jelena; Kruchonak, Uladzimir; Krüger, Hans; Kruker, Tobias; Krumnack, Nils; Krumshteyn, Zinovii; Kruse, Amanda; Kruse, Mark; Kruskal, Michael; Kubota, Takashi; Kuday, Sinan; Kuehn, Susanne; Kugel, Andreas; Kuhl, Andrew; Kuhl, Thorsten; Kukhtin, Victor; Kulchitsky, Yuri; Kuleshov, Sergey; Kuna, Marine; Kunkle, Joshua; Kupco, Alexander; Kurashige, Hisaya; Kurochkin, Yurii; Kurumida, Rie; Kus, Vlastimil; Kuwertz, Emma Sian; Kuze, Masahiro; Kvita, Jiri; La Rosa, Alessandro; La Rotonda, Laura; Lacasta, Carlos; Lacava, Francesco; Lacey, James; Lacker, Heiko; Lacour, Didier; Lacuesta, Vicente Ramón; Ladygin, Evgueni; Lafaye, Remi; Laforge, Bertrand; Lagouri, Theodota; Lai, Stanley; Laier, Heiko; Lambourne, Luke; Lammers, Sabine; Lampen, Caleb; Lampl, Walter; Lançon, Eric; Landgraf, Ulrich; Landon, Murrough; Lang, Valerie Susanne; Lankford, Andrew; Lanni, Francesco; Lantzsch, Kerstin; Laplace, Sandrine; Lapoire, Cecile; Laporte, Jean-Francois; Lari, Tommaso; Lassnig, Mario; Laurelli, Paolo; Lavrijsen, Wim; Law, Alexander; Laycock, Paul; Le, Bao Tran; Le Dortz, Olivier; Le Guirriec, Emmanuel; Le Menedeu, Eve; LeCompte, Thomas; Ledroit-Guillon, Fabienne Agnes Marie; Lee, Claire, Alexandra; Lee, Hurng-Chun; Lee, Jason; Lee, Shih-Chang; Lee, Lawrence; Lefebvre, Guillaume; Lefebvre, Michel; Legger, Federica; Leggett, Charles; Lehan, Allan; Lehmacher, Marc; Lehmann Miotto, Giovanna; Lei, Xiaowen; Leight, William Axel; Leisos, Antonios; Leister, Andrew Gerard; Leite, Marco Aurelio Lisboa; Leitner, Rupert; Lellouch, Daniel; Lemmer, Boris; Leney, Katharine; Lenz, Tatjana; Lenzen, Georg; Lenzi, Bruno; Leone, Robert; Leone, Sandra; Leonhardt, Kathrin; Leonidopoulos, Christos; Leontsinis, Stefanos; Leroy, Claude; Lester, Christopher; Lester, Christopher Michael; Levchenko, Mikhail; Levêque, Jessica; Levin, Daniel; Levinson, Lorne; Levy, Mark; Lewis, Adrian; Lewis, George; Leyko, Agnieszka; Leyton, Michael; Li, Bing; Li, Bo; Li, Haifeng; Li, Ho Ling; Li, Lei; Li, Liang; Li, Shu; Li, Yichen; Liang, Zhijun; Liao, Hongbo; Liberti, Barbara; Lichard, Peter; Lie, Ki; Liebal, Jessica; Liebig, Wolfgang; Limbach, Christian; Limosani, Antonio; Lin, Simon; Lin, Tai-Hua; Linde, Frank; Lindquist, Brian Edward; Linnemann, James; Lipeles, Elliot; Lipniacka, Anna; Lisovyi, Mykhailo; Liss, Tony; Lissauer, David; Lister, Alison; Litke, Alan; Liu, Bo; Liu, Dong; Liu, Jianbei; Liu, Kun; Liu, Lulu; Liu, Miaoyuan; Liu, Minghui; Liu, Yanwen; Livan, Michele; Livermore, Sarah; Lleres, Annick; Llorente Merino, Javier; Lloyd, Stephen; Lo Sterzo, Francesco; Lobodzinska, Ewelina; Loch, Peter; Lockman, William; Loddenkoetter, Thomas; Loebinger, Fred; Loevschall-Jensen, Ask Emil; Loginov, Andrey; Loh, Chang Wei; Lohse, Thomas; Lohwasser, Kristin; Lokajicek, Milos; Lombardo, Vincenzo Paolo; Long, Brian Alexander; Long, Jonathan; Long, Robin Eamonn; Lopes, Lourenco; Lopez Mateos, David; Lopez Paredes, Brais; Lopez Paz, Ivan; Lorenz, Jeanette; Lorenzo Martinez, Narei; Losada, Marta; Loscutoff, Peter; Lou, XinChou; Lounis, Abdenour; Love, Jeremy; Love, Peter; Lowe, Andrew; Lu, Feng; Lubatti, Henry; Luci, Claudio; Lucotte, Arnaud; Luehring, Frederick; Lukas, Wolfgang; Luminari, Lamberto; Lundberg, Olof; Lund-Jensen, Bengt; Lungwitz, Matthias; Lynn, David; Lysak, Roman; Lytken, Else; Ma, Hong; Ma, Lian Liang; Maccarrone, Giovanni; Macchiolo, Anna; Machado Miguens, Joana; Macina, Daniela; Madaffari, Daniele; Madar, Romain; Maddocks, Harvey Jonathan; Mader, Wolfgang; Madsen, Alexander; Maeno, Mayuko; Maeno, Tadashi; Magradze, Erekle; Mahboubi, Kambiz; Mahlstedt, Joern; Mahmoud, Sara; Maiani, Camilla; Maidantchik, Carmen; Maier, Andreas Alexander; Maio, Amélia; Majewski, Stephanie; Makida, Yasuhiro; Makovec, Nikola; Mal, Prolay; Malaescu, Bogdan; Malecki, Pawel; Maleev, Victor; Malek, Fairouz; Mallik, Usha; Malon, David; Malone, Caitlin; Maltezos, Stavros; Malyshev, Vladimir; Malyukov, Sergei; Mamuzic, Judita; Mandelli, Beatrice; Mandelli, Luciano; Mandić, Igor; Mandrysch, Rocco; Maneira, José; Manfredini, Alessandro; Manhaes de Andrade Filho, Luciano; Manjarres Ramos, Joany Andreina; Mann, Alexander; Manning, Peter; Manousakis-Katsikakis, Arkadios; Mansoulie, Bruno; Mantifel, Rodger; Mapelli, Livio; March, Luis; Marchand, Jean-Francois; Marchiori, Giovanni; Marcisovsky, Michal; Marino, Christopher; Marjanovic, Marija; Marques, Carlos; Marroquim, Fernando; Marsden, Stephen Philip; Marshall, Zach; Marti, Lukas Fritz; Marti-Garcia, Salvador; Martin, Brian; Martin, Brian; Martin, Tim; Martin, Victoria Jane; Martin dit Latour, Bertrand; Martinez, Homero; Martinez, Mario; Martin-Haugh, Stewart; Martyniuk, Alex; Marx, Marilyn; Marzano, Francesco; Marzin, Antoine; Masetti, Lucia; Mashimo, Tetsuro; Mashinistov, Ruslan; Masik, Jiri; Maslennikov, Alexey; Massa, Ignazio; Massol, Nicolas; Mastrandrea, Paolo; Mastroberardino, Anna; Masubuchi, Tatsuya; Mättig, Peter; Mattmann, Johannes; Maurer, Julien; Maxfield, Stephen; Maximov, Dmitriy; Mazini, Rachid; Mazzaferro, Luca; Mc Goldrick, Garrin; Mc Kee, Shawn Patrick; McCarn, Allison; McCarthy, Robert; McCarthy, Tom; McCubbin, Norman; McFarlane, Kenneth; Mcfayden, Josh; Mchedlidze, Gvantsa; McMahon, Steve; McPherson, Robert; Meade, Andrew; Mechnich, Joerg; Medinnis, Michael; Meehan, Samuel; Mehlhase, Sascha; Mehta, Andrew; Meier, Karlheinz; Meineck, Christian; Meirose, Bernhard; Melachrinos, Constantinos; Mellado Garcia, Bruce Rafael; Meloni, Federico; Mengarelli, Alberto; Menke, Sven; Meoni, Evelin; Mercurio, Kevin Michael; Mergelmeyer, Sebastian; Meric, Nicolas; Mermod, Philippe; Merola, Leonardo; Meroni, Chiara; Merritt, Frank; Merritt, Hayes; Messina, Andrea; Metcalfe, Jessica; Mete, Alaettin Serhan; Meyer, Carsten; Meyer, Christopher; Meyer, Jean-Pierre; Meyer, Jochen; Middleton, Robin; Migas, Sylwia; Mijović, Liza; Mikenberg, Giora; Mikestikova, Marcela; Mikuž, Marko; Milic, Adriana; Miller, David; Mills, Corrinne; Milov, Alexander; Milstead, David; Milstein, Dmitry; Minaenko, Andrey; Minashvili, Irakli; Mincer, Allen; Mindur, Bartosz; Mineev, Mikhail; Ming, Yao; Mir, Lluisa-Maria; Mirabelli, Giovanni; Mitani, Takashi; Mitrevski, Jovan; Mitsou, Vasiliki A; Mitsui, Shingo; Miucci, Antonio; Miyagawa, Paul; Mjörnmark, Jan-Ulf; Moa, Torbjoern; Mochizuki, Kazuya; Mohapatra, Soumya; Mohr, Wolfgang; Molander, Simon; Moles-Valls, Regina; Mönig, Klaus; Monini, Caterina; Monk, James; Monnier, Emmanuel; Montejo Berlingen, Javier; Monticelli, Fernando; Monzani, Simone; Moore, Roger; Moraes, Arthur; Morange, Nicolas; Moreno, Deywis; Moreno Llácer, María; Morettini, Paolo; Morgenstern, Marcus; Morii, Masahiro; Moritz, Sebastian; Morley, Anthony Keith; Mornacchi, Giuseppe; Morris, John; Morvaj, Ljiljana; Moser, Hans-Guenther; Mosidze, Maia; Moss, Josh; Motohashi, Kazuki; Mount, Richard; Mountricha, Eleni; Mouraviev, Sergei; Moyse, Edward; Muanza, Steve; Mudd, Richard; Mueller, Felix; Mueller, James; Mueller, Klemens; Mueller, Thibaut; Mueller, Timo; Muenstermann, Daniel; Munwes, Yonathan; Murillo Quijada, Javier Alberto; Murray, Bill; Musheghyan, Haykuhi; Musto, Elisa; Myagkov, Alexey; Myska, Miroslav; Nackenhorst, Olaf; Nadal, Jordi; Nagai, Koichi; Nagai, Ryo; Nagai, Yoshikazu; Nagano, Kunihiro; Nagarkar, Advait; Nagasaka, Yasushi; Nagel, Martin; Nairz, Armin Michael; Nakahama, Yu; Nakamura, Koji; Nakamura, Tomoaki; Nakano, Itsuo; Namasivayam, Harisankar; Nanava, Gizo; Narayan, Rohin; Nattermann, Till; Naumann, Thomas; Navarro, Gabriela; Nayyar, Ruchika; Neal, Homer; Nechaeva, Polina; Neep, Thomas James; Nef, Pascal Daniel; Negri, Andrea; Negri, Guido; Negrini, Matteo; Nektarijevic, Snezana; Nelson, Andrew; Nelson, Timothy Knight; Nemecek, Stanislav; Nemethy, Peter; Nepomuceno, Andre Asevedo; Nessi, Marzio; Neubauer, Mark; Neumann, Manuel; Neves, Ricardo; Nevski, Pavel; Newman, Paul; Nguyen, Duong Hai; Nickerson, Richard; Nicolaidou, Rosy; Nicquevert, Bertrand; Nielsen, Jason; Nikiforou, Nikiforos; Nikiforov, Andriy; Nikolaenko, Vladimir; Nikolic-Audit, Irena; Nikolics, Katalin; Nikolopoulos, Konstantinos; Nilsson, Paul; Ninomiya, Yoichi; Nisati, Aleandro; Nisius, Richard; Nobe, Takuya; Nodulman, Lawrence; Nomachi, Masaharu; Nomidis, Ioannis; Norberg, Scarlet; Nordberg, Markus; Novgorodova, Olga; Nowak, Sebastian; Nozaki, Mitsuaki; Nozka, Libor; Ntekas, Konstantinos; Nunes Hanninger, Guilherme; Nunnemann, Thomas; Nurse, Emily; Nuti, Francesco; O'Brien, Brendan Joseph; O'grady, Fionnbarr; O'Neil, Dugan; O'Shea, Val; Oakham, Gerald; Oberlack, Horst; Obermann, Theresa; Ocariz, Jose; Ochi, Atsuhiko; Ochoa, Ines; Oda, Susumu; Odaka, Shigeru; Ogren, Harold; Oh, Alexander; Oh, Seog; Ohm, Christian; Ohman, Henrik; Ohshima, Takayoshi; Okamura, Wataru; Okawa, Hideki; Okumura, Yasuyuki; Okuyama, Toyonobu; Olariu, Albert; Olchevski, Alexander; Olivares Pino, Sebastian Andres; Oliveira Damazio, Denis; Oliver Garcia, Elena; Olszewski, Andrzej; Olszowska, Jolanta; Onofre, António; Onyisi, Peter; Oram, Christopher; Oreglia, Mark; Oren, Yona; Orestano, Domizia; Orlando, Nicola; Oropeza Barrera, Cristina; Orr, Robert; Osculati, Bianca; Ospanov, Rustem; Otero y Garzon, Gustavo; Otono, Hidetoshi; Ouchrif, Mohamed; Ouellette, Eric; Ould-Saada, Farid; Ouraou, Ahmimed; Oussoren, Koen Pieter; Ouyang, Qun; Ovcharova, Ana; Owen, Mark; Ozcan, Veysi Erkcan; Ozturk, Nurcan; Pachal, Katherine; Pacheco Pages, Andres; Padilla Aranda, Cristobal; Pagáčová, Martina; Pagan Griso, Simone; Paganis, Efstathios; Pahl, Christoph; Paige, Frank; Pais, Preema; Pajchel, Katarina; Palacino, Gabriel; Palestini, Sandro; Palka, Marek; Pallin, Dominique; Palma, Alberto; Palmer, Jody; Pan, Yibin; Panagiotopoulou, Evgenia; Panduro Vazquez, William; Pani, Priscilla; Panikashvili, Natalia; Panitkin, Sergey; Pantea, Dan; Paolozzi, Lorenzo; Papadopoulou, Theodora; Papageorgiou, Konstantinos; Paramonov, Alexander; Paredes Hernandez, Daniela; Parker, Michael Andrew; Parodi, Fabrizio; Parsons, John; Parzefall, Ulrich; Pasqualucci, Enrico; Passaggio, Stefano; Passeri, Antonio; Pastore, Fernanda; Pastore, Francesca; Pásztor, Gabriella; Pataraia, Sophio; Patel, Nikhul; Pater, Joleen; Patricelli, Sergio; Pauly, Thilo; Pearce, James; Pedersen, Maiken; Pedraza Lopez, Sebastian; Pedro, Rute; Peleganchuk, Sergey; Pelikan, Daniel; Peng, Haiping; Penning, Bjoern; Penwell, John; Perepelitsa, Dennis; Perez Codina, Estel; Pérez García-Estañ, María Teresa; Perez Reale, Valeria; Perini, Laura; Pernegger, Heinz; Perrino, Roberto; Peschke, Richard; Peshekhonov, Vladimir; Peters, Krisztian; Peters, Yvonne; Petersen, Brian; Petersen, Troels; Petit, Elisabeth; Petridis, Andreas; Petridou, Chariclia; Petrolo, Emilio; Petrucci, Fabrizio; Pettersson, Nora Emilia; Pezoa, Raquel; Phillips, Peter William; Piacquadio, Giacinto; Pianori, Elisabetta; Picazio, Attilio; Piccaro, Elisa; Piccinini, Maurizio; Piegaia, Ricardo; Pignotti, David; Pilcher, James; Pilkington, Andrew; Pina, João Antonio; Pinamonti, Michele; Pinder, Alex; Pinfold, James; Pingel, Almut; Pinto, Belmiro; Pires, Sylvestre; Pitt, Michael; Pizio, Caterina; Plazak, Lukas; Pleier, Marc-Andre; Pleskot, Vojtech; Plotnikova, Elena; Plucinski, Pawel; Poddar, Sahill; Podlyski, Fabrice; Poettgen, Ruth; Poggioli, Luc; Pohl, David-leon; Pohl, Martin; Polesello, Giacomo; Policicchio, Antonio; Polifka, Richard; Polini, Alessandro; Pollard, Christopher Samuel; Polychronakos, Venetios; Pommès, Kathy; Pontecorvo, Ludovico; Pope, Bernard; Popeneciu, Gabriel Alexandru; Popovic, Dragan; Poppleton, Alan; Portell Bueso, Xavier; Pospisil, Stanislav; Potamianos, Karolos; Potrap, Igor; Potter, Christina; Potter, Christopher; Poulard, Gilbert; Poveda, Joaquin; Pozdnyakov, Valery; Pralavorio, Pascal; Pranko, Aliaksandr; Prasad, Srivas; Pravahan, Rishiraj; Prell, Soeren; Price, Darren; Price, Joe; Price, Lawrence; Prieur, Damien; Primavera, Margherita; Proissl, Manuel; Prokofiev, Kirill; Prokoshin, Fedor; Protopapadaki, Eftychia-sofia; Protopopescu, Serban; Proudfoot, James; Przybycien, Mariusz; Przysiezniak, Helenka; Ptacek, Elizabeth; Puddu, Daniele; Pueschel, Elisa; Puldon, David; Purohit, Milind; Puzo, Patrick; Qian, Jianming; Qin, Gang; Qin, Yang; Quadt, Arnulf; Quarrie, David; Quayle, William; Queitsch-Maitland, Michaela; Quilty, Donnchadha; Qureshi, Anum; Radeka, Veljko; Radescu, Voica; Radhakrishnan, Sooraj Krishnan; Radloff, Peter; Rados, Pere; Ragusa, Francesco; Rahal, Ghita; Rajagopalan, Srinivasan; Rammensee, Michael; Randle-Conde, Aidan Sean; Rangel-Smith, Camila; Rao, Kanury; Rauscher, Felix; Rave, Tobias Christian; Ravenscroft, Thomas; Raymond, Michel; Read, Alexander Lincoln; Readioff, Nathan Peter; Rebuzzi, Daniela; Redelbach, Andreas; Redlinger, George; Reece, Ryan; Reeves, Kendall; Rehnisch, Laura; Reisin, Hernan; Relich, Matthew; Rembser, Christoph; Ren, Huan; Ren, Zhongliang; Renaud, Adrien; Rescigno, Marco; Resconi, Silvia; Rezanova, Olga; Reznicek, Pavel; Rezvani, Reyhaneh; Richter, Robert; Ridel, Melissa; Rieck, Patrick; Rieger, Julia; Rijssenbeek, Michael; Rimoldi, Adele; Rinaldi, Lorenzo; Ritsch, Elmar; Riu, Imma; Rizatdinova, Flera; Rizvi, Eram; Robertson, Steven; Robichaud-Veronneau, Andree; Robinson, Dave; Robinson, James; Robson, Aidan; Roda, Chiara; Rodrigues, Luis; Roe, Shaun; Røhne, Ole; Rolli, Simona; Romaniouk, Anatoli; Romano, Marino; Romero Adam, Elena; Rompotis, Nikolaos; Roos, Lydia; Ros, Eduardo; Rosati, Stefano; Rosbach, Kilian; Rose, Matthew; Rosendahl, Peter Lundgaard; Rosenthal, Oliver; Rossetti, Valerio; Rossi, Elvira; Rossi, Leonardo Paolo; Rosten, Rachel; Rotaru, Marina; Roth, Itamar; Rothberg, Joseph; Rousseau, David; Royon, Christophe; Rozanov, Alexandre; Rozen, Yoram; Ruan, Xifeng; Rubbo, Francesco; Rubinskiy, Igor; Rud, Viacheslav; Rudolph, Christian; Rudolph, Matthew Scott; Rühr, Frederik; Ruiz-Martinez, Aranzazu; Rurikova, Zuzana; Rusakovich, Nikolai; Ruschke, Alexander; Rutherfoord, John; Ruthmann, Nils; Ryabov, Yury; Rybar, Martin; Rybkin, Grigori; Ryder, Nick; Saavedra, Aldo; Sacerdoti, Sabrina; Saddique, Asif; Sadeh, Iftach; Sadrozinski, Hartmut; Sadykov, Renat; Safai Tehrani, Francesco; Sakamoto, Hiroshi; Sakurai, Yuki; Salamanna, Giuseppe; Salamon, Andrea; Saleem, Muhammad; Salek, David; Sales De Bruin, Pedro Henrique; Salihagic, Denis; Salnikov, Andrei; Salt, José; Salvachua Ferrando, Belén; Salvatore, Daniela; Salvatore, Pasquale Fabrizio; Salvucci, Antonio; Salzburger, Andreas; Sampsonidis, Dimitrios; Sanchez, Arturo; Sánchez, Javier; Sanchez Martinez, Victoria; Sandaker, Heidi; Sandbach, Ruth Laura; Sander, Heinz Georg; Sanders, Michiel; Sandhoff, Marisa; Sandoval, Tanya; Sandoval, Carlos; Sandstroem, Rikard; Sankey, Dave; Sansoni, Andrea; Santoni, Claudio; Santonico, Rinaldo; Santos, Helena; Santoyo Castillo, Itzebelt; Sapp, Kevin; Sapronov, Andrey; Saraiva, João; Sarrazin, Bjorn; Sartisohn, Georg; Sasaki, Osamu; Sasaki, Yuichi; Sauvage, Gilles; Sauvan, Emmanuel; Savard, Pierre; Savu, Dan Octavian; Sawyer, Craig; Sawyer, Lee; Saxon, David; Saxon, James; Sbarra, Carla; Sbrizzi, Antonio; Scanlon, Tim; Scannicchio, Diana; Scarcella, Mark; Scarfone, Valerio; Schaarschmidt, Jana; Schacht, Peter; Schaefer, Douglas; Schaefer, Ralph; Schaepe, Steffen; Schaetzel, Sebastian; Schäfer, Uli; Schaffer, Arthur; Schaile, Dorothee; Schamberger, R. Dean; Scharf, Veit; Schegelsky, Valery; Scheirich, Daniel; Schernau, Michael; Scherzer, Max; Schiavi, Carlo; Schieck, Jochen; Schillo, Christian; Schioppa, Marco; Schlenker, Stefan; Schmidt, Evelyn; Schmieden, Kristof; Schmitt, Christian; Schmitt, Christopher; Schmitt, Sebastian; Schneider, Basil; Schnellbach, Yan Jie; Schnoor, Ulrike; Schoeffel, Laurent; Schoening, Andre; Schoenrock, Bradley Daniel; Schorlemmer, Andre Lukas; Schott, Matthias; Schouten, Doug; Schovancova, Jaroslava; Schramm, Steven; Schreyer, Manuel; Schroeder, Christian; Schuh, Natascha; Schultens, Martin Johannes; Schultz-Coulon, Hans-Christian; Schulz, Holger; Schumacher, Markus; Schumm, Bruce; Schune, Philippe; Schwanenberger, Christian; Schwartzman, Ariel; Schwegler, Philipp; Schwemling, Philippe; Schwienhorst, Reinhard; Schwindling, Jerome; Schwindt, Thomas; Schwoerer, Maud; Sciacca, Gianfranco; Scifo, Estelle; Sciolla, Gabriella; Scott, Bill; Scuri, Fabrizio; Scutti, Federico; Searcy, Jacob; Sedov, George; Sedykh, Evgeny; Seidel, Sally; Seiden, Abraham; Seifert, Frank; Seixas, José; Sekhniaidze, Givi; Sekula, Stephen; Selbach, Karoline Elfriede; Seliverstov, Dmitry; Sellers, Graham; Semprini-Cesari, Nicola; Serfon, Cedric; Serin, Laurent; Serkin, Leonid; Serre, Thomas; Seuster, Rolf; Severini, Horst; Sfiligoj, Tina; Sforza, Federico; Sfyrla, Anna; Shabalina, Elizaveta; Shamim, Mansoora; Shan, Lianyou; Shang, Ruo-yu; Shank, James; Shapiro, Marjorie; Shatalov, Pavel; Shaw, Kate; Shehu, Ciwake Yusufu; Sherwood, Peter; Shi, Liaoshan; Shimizu, Shima; Shimmin, Chase Owen; Shimojima, Makoto; Shiyakova, Mariya; Shmeleva, Alevtina; Shochet, Mel; Short, Daniel; Shrestha, Suyog; Shulga, Evgeny; Shupe, Michael; Shushkevich, Stanislav; Sicho, Petr; Sidiropoulou, Ourania; Sidorov, Dmitri; Sidoti, Antonio; Siegert, Frank; Sijacki, Djordje; Silva, José; Silver, Yiftah; Silverstein, Daniel; Silverstein, Samuel; Simak, Vladislav; Simard, Olivier; Simic, Ljiljana; Simion, Stefan; Simioni, Eduard; Simmons, Brinick; Simoniello, Rosa; Simonyan, Margar; Sinervo, Pekka; Sinev, Nikolai; Sipica, Valentin; Siragusa, Giovanni; Sircar, Anirvan; Sisakyan, Alexei; Sivoklokov, Serguei; Sjölin, Jörgen; Sjursen, Therese; Skottowe, Hugh Philip; Skovpen, Kirill; Skubic, Patrick; Slater, Mark; Slavicek, Tomas; Sliwa, Krzysztof; Smakhtin, Vladimir; Smart, Ben; Smestad, Lillian; Smirnov, Sergei; Smirnov, Yury; Smirnova, Lidia; Smirnova, Oxana; Smith, Kenway; Smizanska, Maria; Smolek, Karel; Snesarev, Andrei; Snidero, Giacomo; Snyder, Scott; Sobie, Randall; Socher, Felix; Soffer, Abner; Soh, Dart-yin; Solans, Carlos; Solar, Michael; Solc, Jaroslav; Soldatov, Evgeny; Soldevila, Urmila; Solfaroli Camillocci, Elena; Solodkov, Alexander; Soloshenko, Alexei; Solovyanov, Oleg; Solovyev, Victor; Sommer, Philip; Song, Hong Ye; Soni, Nitesh; Sood, Alexander; Sopczak, Andre; Sopko, Bruno; Sopko, Vit; Sorin, Veronica; Sosebee, Mark; Soualah, Rachik; Soueid, Paul; Soukharev, Andrey; South, David; Spagnolo, Stefania; Spanò, Francesco; Spearman, William Robert; Spettel, Fabian; Spighi, Roberto; Spigo, Giancarlo; Spousta, Martin; Spreitzer, Teresa; Spurlock, Barry; St Denis, Richard Dante; Staerz, Steffen; Stahlman, Jonathan; Stamen, Rainer; Stanecka, Ewa; Stanek, Robert; Stanescu, Cristian; Stanescu-Bellu, Madalina; Stanitzki, Marcel Michael; Stapnes, Steinar; Starchenko, Evgeny; Stark, Jan; Staroba, Pavel; Starovoitov, Pavel; Staszewski, Rafal; Stavina, Pavel; Steinberg, Peter; Stelzer, Bernd; Stelzer, Harald Joerg; Stelzer-Chilton, Oliver; Stenzel, Hasko; Stern, Sebastian; Stewart, Graeme; Stillings, Jan Andre; Stockton, Mark; Stoebe, Michael; Stoicea, Gabriel; Stolte, Philipp; Stonjek, Stefan; Stradling, Alden; Straessner, Arno; Stramaglia, Maria Elena; Strandberg, Jonas; Strandberg, Sara; Strandlie, Are; Strauss, Emanuel; Strauss, Michael; Strizenec, Pavol; Ströhmer, Raimund; Strom, David; Stroynowski, Ryszard; Stucci, Stefania Antonia; Stugu, Bjarne; Styles, Nicholas Adam; Su, Dong; Su, Jun; Subramania, Halasya Siva; Subramaniam, Rajivalochan; Succurro, Antonella; Sugaya, Yorihito; Suhr, Chad; Suk, Michal; Sulin, Vladimir; Sultansoy, Saleh; Sumida, Toshi; Sun, Xiaohu; Sundermann, Jan Erik; Suruliz, Kerim; Susinno, Giancarlo; Sutton, Mark; Suzuki, Yu; Svatos, Michal; Swedish, Stephen; Swiatlowski, Maximilian; Sykora, Ivan; Sykora, Tomas; Ta, Duc; Taccini, Cecilia; Tackmann, Kerstin; Taenzer, Joe; Taffard, Anyes; Tafirout, Reda; Taiblum, Nimrod; Takahashi, Yuta; Takai, Helio; Takashima, Ryuichi; Takeda, Hiroshi; Takeshita, Tohru; Takubo, Yosuke; Talby, Mossadek; Talyshev, Alexey; Tam, Jason; Tan, Kong Guan; Tanaka, Junichi; Tanaka, Reisaburo; Tanaka, Satoshi; Tanaka, Shuji; Tanasijczuk, Andres Jorge; Tannenwald, Benjamin Bordy; Tannoury, Nancy; Tapprogge, Stefan; Tarem, Shlomit; Tarrade, Fabien; Tartarelli, Giuseppe Francesco; Tas, Petr; Tasevsky, Marek; Tashiro, Takuya; Tassi, Enrico; Tavares Delgado, Ademar; Tayalati, Yahya; Taylor, Frank; Taylor, Geoffrey; Taylor, Wendy; Teischinger, Florian Alfred; Teixeira Dias Castanheira, Matilde; Teixeira-Dias, Pedro; Temming, Kim Katrin; Ten Kate, Herman; Teng, Ping-Kun; Teoh, Jia Jian; Terada, Susumu; Terashi, Koji; Terron, Juan; Terzo, Stefano; Testa, Marianna; Teuscher, Richard; Therhaag, Jan; Theveneaux-Pelzer, Timothée; Thomas, Juergen; Thomas-Wilsker, Joshuha; Thompson, Emily; Thompson, Paul; Thompson, Peter; Thompson, Stan; Thomsen, Lotte Ansgaard; Thomson, Evelyn; Thomson, Mark; Thong, Wai Meng; Thun, Rudolf; Tian, Feng; Tibbetts, Mark James; Tikhomirov, Vladimir; Tikhonov, Yury; Timoshenko, Sergey; Tiouchichine, Elodie; Tipton, Paul; Tisserant, Sylvain; Todorov, Theodore; Todorova-Nova, Sharka; Toggerson, Brokk; Tojo, Junji; Tokár, Stanislav; Tokushuku, Katsuo; Tollefson, Kirsten; Tomlinson, Lee; Tomoto, Makoto; Tompkins, Lauren; Toms, Konstantin; Topilin, Nikolai; Torrence, Eric; Torres, Heberth; Torró Pastor, Emma; Toth, Jozsef; Touchard, Francois; Tovey, Daniel; Tran, Huong Lan; Trefzger, Thomas; Tremblet, Louis; Tricoli, Alessandro; Trigger, Isabel Marian; Trincaz-Duvoid, Sophie; Tripiana, Martin; Triplett, Nathan; Trischuk, William; Trocmé, Benjamin; Troncon, Clara; Trottier-McDonald, Michel; Trovatelli, Monica; True, Patrick; Trzebinski, Maciej; Trzupek, Adam; Tsarouchas, Charilaos; Tseng, Jeffrey; Tsiareshka, Pavel; Tsionou, Dimitra; Tsipolitis, Georgios; Tsirintanis, Nikolaos; Tsiskaridze, Shota; Tsiskaridze, Vakhtang; Tskhadadze, Edisher; Tsukerman, Ilya; Tsulaia, Vakhtang; Tsuno, Soshi; Tsybychev, Dmitri; Tudorache, Alexandra; Tudorache, Valentina; Tuna, Alexander Naip; Tupputi, Salvatore; Turchikhin, Semen; Turecek, Daniel; Turk Cakir, Ilkay; Turra, Ruggero; Tuts, Michael; Tykhonov, Andrii; Tylmad, Maja; Tyndel, Mike; Uchida, Kirika; Ueda, Ikuo; Ueno, Ryuichi; Ughetto, Michael; Ugland, Maren; Uhlenbrock, Mathias; Ukegawa, Fumihiko; Unal, Guillaume; Undrus, Alexander; Unel, Gokhan; Ungaro, Francesca; Unno, Yoshinobu; Urbaniec, Dustin; Urquijo, Phillip; Usai, Giulio; Usanova, Anna; Vacavant, Laurent; Vacek, Vaclav; Vachon, Brigitte; Valencic, Nika; Valentinetti, Sara; Valero, Alberto; Valery, Loic; Valkar, Stefan; Valladolid Gallego, Eva; Vallecorsa, Sofia; Valls Ferrer, Juan Antonio; Van Den Wollenberg, Wouter; Van Der Deijl, Pieter; van der Geer, Rogier; van der Graaf, Harry; Van Der Leeuw, Robin; van der Ster, Daniel; van Eldik, Niels; van Gemmeren, Peter; Van Nieuwkoop, Jacobus; van Vulpen, Ivo; van Woerden, Marius Cornelis; Vanadia, Marco; Vandelli, Wainer; Vanguri, Rami; Vaniachine, Alexandre; Vankov, Peter; Vannucci, Francois; Vardanyan, Gagik; Vari, Riccardo; Varnes, Erich; Varol, Tulin; Varouchas, Dimitris; Vartapetian, Armen; Varvell, Kevin; Vazeille, Francois; Vazquez Schroeder, Tamara; Veatch, Jason; Veloso, Filipe; Veneziano, Stefano; Ventura, Andrea; Ventura, Daniel; Venturi, Manuela; Venturi, Nicola; Venturini, Alessio; Vercesi, Valerio; Verducci, Monica; Verkerke, Wouter; Vermeulen, Jos; Vest, Anja; Vetterli, Michel; Viazlo, Oleksandr; Vichou, Irene; Vickey, Trevor; Vickey Boeriu, Oana Elena; Viehhauser, Georg; Viel, Simon; Vigne, Ralph; Villa, Mauro; Villaplana Perez, Miguel; Vilucchi, Elisabetta; Vincter, Manuella; Vinogradov, Vladimir; Virzi, Joseph; Vivarelli, Iacopo; Vives Vaque, Francesc; Vlachos, Sotirios; Vladoiu, Dan; Vlasak, Michal; Vogel, Adrian; Vogel, Marcelo; Vokac, Petr; Volpi, Guido; Volpi, Matteo; von der Schmitt, Hans; von Radziewski, Holger; von Toerne, Eckhard; Vorobel, Vit; Vorobev, Konstantin; Vos, Marcel; Voss, Rudiger; Vossebeld, Joost; Vranjes, Nenad; Vranjes Milosavljevic, Marija; Vrba, Vaclav; Vreeswijk, Marcel; Vu Anh, Tuan; Vuillermet, Raphael; Vukotic, Ilija; Vykydal, Zdenek; Wagner, Peter; Wagner, Wolfgang; Wahlberg, Hernan; Wahrmund, Sebastian; Wakabayashi, Jun; Walder, James; Walker, Rodney; Walkowiak, Wolfgang; Wall, Richard; Waller, Peter; Walsh, Brian; Wang, Chao; Wang, Chiho; Wang, Fuquan; Wang, Haichen; Wang, Hulin; Wang, Jike; Wang, Jin; Wang, Kuhan; Wang, Rui; Wang, Song-Ming; Wang, Tan; Wang, Xiaoxiao; Wanotayaroj, Chaowaroj; Warburton, Andreas; Ward, Patricia; Wardrope, David Robert; Warsinsky, Markus; Washbrook, Andrew; Wasicki, Christoph; Watkins, Peter; Watson, Alan; Watson, Ian; Watson, Miriam; Watts, Gordon; Watts, Stephen; Waugh, Ben; Webb, Samuel; Weber, Michele; Weber, Stefan Wolf; Webster, Jordan S; Weidberg, Anthony; Weigell, Philipp; Weinert, Benjamin; Weingarten, Jens; Weiser, Christian; Weits, Hartger; Wells, Phillippa; Wenaus, Torre; Wendland, Dennis; Weng, Zhili; Wengler, Thorsten; Wenig, Siegfried; Wermes, Norbert; Werner, Matthias; Werner, Per; Wessels, Martin; Wetter, Jeffrey; Whalen, Kathleen; White, Andrew; White, Martin; White, Ryan; White, Sebastian; Whiteson, Daniel; Wicke, Daniel; Wickens, Fred; Wiedenmann, Werner; Wielers, Monika; Wienemann, Peter; Wiglesworth, Craig; Wiik-Fuchs, Liv Antje Mari; Wijeratne, Peter Alexander; Wildauer, Andreas; Wildt, Martin Andre; Wilkens, Henric George; Will, Jonas Zacharias; Williams, Hugh; Williams, Sarah; Willis, Christopher; Willocq, Stephane; Wilson, Alan; Wilson, John; Wingerter-Seez, Isabelle; Winklmeier, Frank; Winter, Benedict Tobias; Wittgen, Matthias; Wittig, Tobias; Wittkowski, Josephine; Wollstadt, Simon Jakob; Wolter, Marcin Wladyslaw; Wolters, Helmut; Wosiek, Barbara; Wotschack, Jorg; Woudstra, Martin; Wozniak, Krzysztof; Wright, Michael; Wu, Mengqing; Wu, Sau Lan; Wu, Xin; Wu, Yusheng; Wulf, Evan; Wyatt, Terry Richard; Wynne, Benjamin; Xella, Stefania; Xiao, Meng; Xu, Da; Xu, Lailin; Yabsley, Bruce; Yacoob, Sahal; Yamada, Miho; Yamaguchi, Hiroshi; Yamaguchi, Yohei; Yamamoto, Akira; Yamamoto, Kyoko; Yamamoto, Shimpei; Yamamura, Taiki; Yamanaka, Takashi; Yamauchi, Katsuya; Yamazaki, Yuji; Yan, Zhen; Yang, Haijun; Yang, Hongtao; Yang, Un-Ki; Yang, Yi; Yanush, Serguei; Yao, Liwen; Yao, Weiming; Yasu, Yoshiji; Yatsenko, Elena; Yau Wong, Kaven Henry; Ye, Jingbo; Ye, Shuwei; Yen, Andy L; Yildirim, Eda; Yilmaz, Metin; Yoosoofmiya, Reza; Yorita, Kohei; Yoshida, Rikutaro; Yoshihara, Keisuke; Young, Charles; Young, Christopher John; Youssef, Saul; Yu, David Ren-Hwa; Yu, Jaehoon; Yu, Jiaming; Yu, Jie; Yuan, Li; Yurkewicz, Adam; Yusuff, Imran; Zabinski, Bartlomiej; Zaidan, Remi; Zaitsev, Alexander; Zaman, Aungshuman; Zambito, Stefano; Zanello, Lucia; Zanzi, Daniele; Zeitnitz, Christian; Zeman, Martin; Zemla, Andrzej; Zengel, Keith; Zenin, Oleg; Ženiš, Tibor; Zerwas, Dirk; Zevi della Porta, Giovanni; Zhang, Dongliang; Zhang, Fangzhou; Zhang, Huaqiao; Zhang, Jinlong; Zhang, Lei; Zhang, Xueyao; Zhang, Zhiqing; Zhao, Zhengguo; Zhemchugov, Alexey; Zhong, Jiahang; Zhou, Bing; Zhou, Lei; Zhou, Ning; Zhu, Cheng Guang; Zhu, Hongbo; Zhu, Junjie; Zhu, Yingchun; Zhuang, Xuai; Zhukov, Konstantin; Zibell, Andre; Zieminska, Daria; Zimine, Nikolai; Zimmermann, Christoph; Zimmermann, Robert; Zimmermann, Simone; Zimmermann, Stephanie; Zinonos, Zinonas; Ziolkowski, Michael; Zobernig, Georg; Zoccoli, Antonio; zur Nedden, Martin; Zurzolo, Giovanni; Zutshi, Vishnu; Zwalinski, Lukasz

    2014-01-01

    A novel technique to identify and split clusters created by multiple charged particles in the ATLAS pixel detector using a set of artificial neural networks is presented. Such merged clusters are a common feature of tracks originating from highly energetic objects, such as jets. Neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. This technique replaces the former clustering approach based on a connected component analysis and charge interpolation. The performance of the neural network splitting technique is quantified using data from proton-proton collisions at the LHC collected by the ATLAS detector in 2011 and from Monte Carlo simulations. This technique reduces the number of clusters shared between tracks in highly energetic jets by up to a factor of three. It also provides more precise position and error estimates of the clusters in both the transverse and longitudinal impact parameter resolution.

  12. The phase-II ATLAS pixel tracker upgrade: layout and mechanics.

    CERN Document Server

    Sharma, Abhishek; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment will upgrade its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The upgraded tracker will consist of silicon-strip modules surrounding a pixel detector, and will likely cover an extended eta range, perhaps as far as |eta|<4.0. A number of layout and supporting-structure options are being considered for the pixel detector, with the final choice expected to be made in early 2017. The proposed supporting structures are based on lightweight, highly-thermally-conductive carbon-based materials and are cooled by evaporative carbon dioxide. The various layouts will be described and a description of the supporting structures will be presented, along with results from testing of prototypes.

  13. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    CERN Document Server

    Boek, J; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2013-01-01

    inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University ofWuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

  14. Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Wittig, Tobias

    2013-05-08

    One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

  15. The Pixel Detector of the ATLAS Experiment for the Run-2 at the Large Hadron Collider

    CERN Document Server

    Guescini, F; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radial distance of 3.3 cm from the beam axis. The realization of the IBL required the development of several new technologies and solutions in order to overcome the challenges introduced by the extreme environment and working conditions, such as the high radiation levels, the high pixel occupancy and the need of an exceptionally low material budget. Two silicon sensor technologies have been adopted for the IBL modules: planar n-in-n and 3D. Both of these are connected via bump bonding to the new generation 130 nm IBM CMOS FE-I4 ...

  16. Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

    CERN Document Server

    Savic, N

    2016-01-01

    In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023-2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more ra- diation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 {\\mu}m recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of th...

  17. Circuit techniques for cognitive radio receiver front-ends

    Science.gov (United States)

    Sadhu, Bodhisatwa

    This thesis discusses the design of the receiver front-end for software defined radio (SDR) based cognitive radio applications. Two aspects of SDRs for cognitive radios are distinguished: signaling and spectrum sensing. Narrowband wide tuning signaling architectures and instantaneous wideband spectrum sensing architectures are identified as candidates for feasible SDR implementations. Several architectures and circuit implementations are reviewed. Wide tuning range, low phase noise frequency synthesizers for signaling, and RF samplers and signal processors for spectrum sensing are identified as critical circuit design blocks. A number of voltage controlled oscillator (VCO) techniques for wide-tuning range, and low phase noise frequency synthesis techniques are developed. Wide-tuning range techniques based on switched inductors are proposed as a way to design inductor-capacitor (LC) VCOs with wide-tuning ranges that maintain a good phase noise and power dissipation performance over the entire tuning range. Switched inductor VCOs are analyzed in detail, and a design framework is developed. Optimized capacitor array design techniques for wide-tuning ranges are discussed. Based on these techniques, measurements from two prototype designs are presented, that achieve tuning ranges of 87% and 157% in measurement. They also maintain good phase noise, power consumption, and figure of merit (FOM) over the entire tuning range. In addition, a new family of VCOs that achieve superior phase noise is introduced. This set of novel topologies are based on linearized transconductance using capacitive feedback techniques. They achieve higher amplitudes of oscillation, and consequently, a superior phase noise performance. A wide tuning range is also maintained. The VCOs are analyzed, and detailed measurement results from a design prototype are presented. For spectrum sensing, the design of CRAFT (Charge Re-use Analog Fourier Transform): an RF front-end channelizer for software defined

  18. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    Cassina, L

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  19. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experi- ment at the Large Hadron Collider at CERN, providing high-resolution mea- surements of charged particle tracks in the high radiation environment close to the collision region. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. After three years of operation the detector performance is excellent: 96% of the pixels are opera- tional, at 3500 e threshold noise occupancy and efficiency exceed the design specification. The effect of radiation on the silicon sensor is measured and compared with model of radiation damage.

  20. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  1. DESIGN & IMPLEMENTATION OF RECONFIGURABLE FRONT END FOR MIMO-OFDM

    Directory of Open Access Journals (Sweden)

    VEENA M.B.

    2011-02-01

    Full Text Available This paper focuses on design, implement and optimization of digital front end module of Multiple Input Multiple Output (MIMO-Orthogonal Frequency Division Multiplexing (OFDM system on FPGA employing Alamouti Technique (Space Time Block coding. MIMO-OFDM can very effectively be used to achieve higher data rate’s and higher reliability and this is going to be the Key for 4G Technology. MIMO -OFDM designed in this work consists of Input/Output Memory, 16 QAM Modulator, MIMO Encoder (Space Time Encoder, Wireless Channel Model, MIMO Decoder Space Time Decoder and 16 QAM Demodulator. This paper has resulted in the development of a hardware prototype of a MIMO Transmitter, Receiver and channel, which is implemented on a Spartan-3 FPGA board. As the number format adopted is floating point,there was a need to develop a separate function which will show the equivalent real numbers for the corresponding floating point number. This made the task of debugging a lot easier. Test benches for individual model were developed and tested it for its correct functionality. The functional simulation was carried out for the entire design. The entire design was mapped on to FPGA. The results were compared with the MATLAB results and were found to be the same.

  2. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  3. Digital Front End for Wide-Band VLBI Science Receiver

    Science.gov (United States)

    Jongeling, Andre; Sigman, Elliott; Navarro, Robert; Goodhart, Charles; Rogstad, Steve; Chandra, Kumar; Finley, Sue; Trinh, Joseph; Soriano, Melissa; White, Les; Proctor, Robert; Rayhrer, Benno

    2006-01-01

    An upgrade to the very-long-baseline-interferometry (VLBI) science receiver (VSR) a radio receiver used in NASA's Deep Space Network (DSN) is currently being implemented. The current VSR samples standard DSN intermediate- frequency (IF) signals at 256 MHz and after digital down-conversion records data from up to four 16-MHz baseband channels. Currently, IF signals are limited to the 265-to-375-MHz range, and recording rates are limited to less than 80 Mbps. The new digital front end, denoted the Wideband VSR, provides improvements to enable the receiver to process wider bandwidth signals and accommodate more data channels for recording. The Wideband VSR utilizes state-of-the-art commercial analog-to-digital converter and field-programmable gate array (FPGA) integrated circuits, and fiber-optic connections in a custom architecture. It accepts IF signals from 100 to 600 MHz, sampling the signal at 1.28 GHz. The sample data are sent to a digital processing module, using a fiber-optic link for isolation. The digital processing module includes boards designed around an Advanced Telecom Computing Architecture (ATCA) industry-standard backplane. Digital signal processing implemented in FPGAs down-convert the data signals in up to 16 baseband channels with programmable bandwidths from 1 kHz to 16 MHz. Baseband samples are transmitted to a computer via multiple Ethernet connections allowing recording to disk at rates of up to 1 Gbps.

  4. Front-end electronics and trigger systems - status and challenges

    Energy Technology Data Exchange (ETDEWEB)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-08-21

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described.

  5. Highly scalable digital front end architectures for digital printing

    Science.gov (United States)

    Staas, David

    2011-01-01

    HP's digital printing presses consume a tremendous amount of data. The architectures of the Digital Front Ends (DFEs) that feed these large, very fast presses have evolved from basic, single-RIP (Raster Image Processor) systems to multirack, distributed systems that can take a PDF file and deliver data in excess of 3 Gigapixels per second to keep the presses printing at 2000+ pages per minute. This paper highlights some of the more interesting parallelism features of our DFE architectures. The high-performance architecture developed over the last 5+ years can scale up to HP's largest digital press, out to multiple mid-range presses, and down into a very low-cost single box deployment for low-end devices as appropriate. Principles of parallelism pervade every aspect of the architecture, from the lowest-level elements of jobs to parallel imaging pipelines that feed multiple presses. From cores to threads to arrays to network teams to distributed machines, we use a systematic approach to move bottlenecks. The ultimate goals of these efforts are: to take the best advantage of the prevailing hardware options at our disposal; to reduce power consumption and cooling requirements; and to ultimately reduce the cost of the solution to our customers.

  6. An Enhanced Front-End Algorithm for Reducing Channel Change Time in DVB-T System

    Science.gov (United States)

    Joe, Inwhee; Choi, Jongsung

    To address the low performance for channel scanning in the DVB-T system, we propose an enhanced front-end algorithm in this paper. The proposed algorithm consists of Auto Scan and Normal Scan, which is a part of the tuning algorithm for front-end (tuner) drivers in the DVB-T receiver. The key idea is that the frequency offset is saved when performing Auto Scan in order to reduce the channel change time for Normal Scan. In addition, the results of a performance evaluation demonstrate that our enhanced front-end algorithm improves the performance of channel scanning significantly, as compared to the generic front-end algorithm.

  7. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  8. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  9. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Gabrielli, Alessandro; The ATLAS collaboration; Balbi, Gabriele; Bindi, Marcello; Chen, Shaw-pin; Falchieri, Davide; Flick, Tobias; Hauck, Scott Alan; Hsu, Shih-Chieh; Kretz, Moritz; Kugel, Andreas; Lama, Luca; Travaglini, Riccardo; Wensing, Marius; ATLAS Pixel Collaboration

    2015-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data pat...

  10. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Balbi, G; The ATLAS collaboration; Gabrielli, A; Lama, L; Travaglini, R; Backhaus, M; Bindi, M; Chen, S-P; Flick, T; Kretz, M; Kugel, A; Wensing, M

    2014-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development was three-fold: keeping as much of the PixelROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path im...

  11. System test and noise performance studies at the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Weingarten, J.

    2007-09-15

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  12. Studio di un algoritmo lineare di ricostruzione analogica della posizione per il rivelatore a pixel di ATLAS

    CERN Document Server

    Arelli-Maffioli, A; Troncon, C; Lari, T

    2007-01-01

    A detailed study of spatial resolution of Atlas pixel sensors prototypes was performed. Charge interpolation was used and allowed for a significant improvement with respect to digital resolution. A simplified algorithm for charge interpolation was developed. Its application to both unirradiated and irradiated sensors is presented and discussed.

  13. The ATLAS Beam Condition Monitor Commissioning

    CERN Document Server

    Gorisek, A

    2008-01-01

    The ATLAS Beam Condition Monitor (BCM) based on radiation hard pCVD diamond sensors and event-by-event measurements of environment close to interaction point (z=±184 cm, r=5.5 cm) has been installed in the Pixel detector since early 2008 and together with the Pixel detector in the ATLAS cavern since June 2008. The sensors and front end electronics were shown to withstand 50 Mrad and 1015 particles/cm2 expected in LHC lifetime. Recently the full readout chain, partly made of radiation tolerant electronics, still inside of the ATLAS spectrometer and partly in the electronics room, was completed and the system was operated in time of the first LHC single beams and is ready now for the first collisions which will follow after the LHC repair.

  14. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation.

    CERN Document Server

    Heim, Timon; The ATLAS collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 x 10^33 cm-2 s-1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silicon leakage ...

  15. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  16. Beam Test Studies of 3D Pixel Sensors Irradiated Non-Uniformly for the ATLAS Forward Physics Detector

    CERN Document Server

    Grinstein, S; Boscardin, M; Christophersen, M; Da Via, C; Betta, G -F Dalla; Darbo, G; Fadeyev, V; Fleta, C; Gemme, C; Grenier, P; Jimenez, A; Lopez, I; Micelli, A; Nelist, C; Parker, S; Pellegrini, G; Phlips, B; Pohl, D L; Sadrozinski, H F -W; Sicho, P; Tsiskaridze, S

    2013-01-01

    Pixel detectors with cylindrical electrodes that penetrate the silicon substrate (so called 3D detectors) offer advantages over standard planar sensors in terms of radiation hardness, since the electrode distance is decoupled from the bulk thickness. In recent years significant progress has been made in the development of 3D sensors, which culminated in the sensor production for the ATLAS Insertable B-Layer (IBL) upgrade carried out at CNM (Barcelona, Spain) and FBK (Trento, Italy). Based on this success, the ATLAS Forward Physics (AFP) experiment has selected the 3D pixel sensor technology for the tracking detector. The AFP project presents a new challenge due to the need for a reduced dead area with respect to IBL, and the in-homogeneous nature of the radiation dose distribution in the sensor. Electrical characterization of the first AFP prototypes and beam test studies of 3D pixel devices irradiated non-uniformly are presented in this paper.

  17. Beam test studies of 3D pixel sensors irradiated non-uniformly for the ATLAS forward physics detector

    Energy Technology Data Exchange (ETDEWEB)

    Grinstein, S., E-mail: sgrinstein@ifae.es [ICREA and Institut de Física d' Altes Energies (IFAE), Barcelona (Spain); Baselga, M. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Boscardin, M. [Fondazione Bruno Kessler, FBK-CMM, Trento (Italy); Christophersen, M. [U.S. Naval Research Laboratory, Washington (United States); Da Via, C. [School of Physics and Astronomy, University of Manchester, Manchester (United Kingdom); Dalla Betta, G.-F. [Universita degli Studi di Trento and INFN, Trento (Italy); Darbo, G. [INFN Sezione di Genova, Genova (Italy); Fadeyev, V. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz (United States); Fleta, C. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Gemme, C. [Universita degli Studi di Trento and INFN, Trento (Italy); Grenier, P. [SLAC National Accelerator Laboratory, Menlo Park (United States); Jimenez, A.; Lopez, I.; Micelli, A. [ICREA and Institut de Física d' Altes Energies (IFAE), Barcelona (Spain); Nelist, C. [INFN Sezione di Genova, Genova (Italy); Parker, S. [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley (United States); Pellegrini, G. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Phlips, B. [U.S. Naval Research Laboratory, Washington (United States); Pohl, D.-L. [University of Bonn, Bonn (Germany); Sadrozinski, H.F.-W. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz (United States); and others

    2013-12-01

    Pixel detectors with cylindrical electrodes that penetrate the silicon substrate (so called 3D detectors) offer advantages over standard planar sensors in terms of radiation hardness, since the electrode distance is decoupled from the bulk thickness. In recent years significant progress has been made in the development of 3D sensors, which culminated in the sensor production for the ATLAS Insertable B-Layer (IBL) upgrade carried out at CNM (Barcelona, Spain) and FBK (Trento, Italy). Based on this success, the ATLAS Forward Physics (AFP) experiment has selected the 3D pixel sensor technology for the tracking detector. The AFP project presents a new challenge due to the need for a reduced dead area with respect to IBL, and the in-homogeneous nature of the radiation dose distribution in the sensor. Electrical characterization of the first AFP prototypes and beam test studies of 3D pixel devices irradiated non-uniformly are presented in this paper.

  18. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  19. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  20. PHYSICS RESULTS OF THE NSLS-II LINAC FRONT END TEST STAND

    Energy Technology Data Exchange (ETDEWEB)

    Fliller R. P.; Gao, F.; Yang, X.; Rose, J.; Shaftan, T.; Piel, C

    2012-05-20

    The Linac Front End Test Stand (LFETS) was installed at the Source Development Laboratory (SDL) in the fall of 2011 in order to test the Linac Front End. The goal of these tests was to test the electron source against the specifications of the linac. In this report, we discuss the results of these measurements and the effect on linac performance.

  1. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of Innov

  2. Preliminary results of 3D-DDTC pixel detectors for the ATLAS upgrade

    CERN Document Server

    La Rosa, Alessandro; Dalla Betta, G F; Darbo, G; Gemme, C; Pernegger, H; Piemonte, C; Povoli, M; Ronchin, S; Zoboli, A; Zorzi, N; Bolle, E; Borri, M; Da Via, C; Dong, S; Fazio, S; Grenier, P; Grinstein, S; Gjersdal, H; Hansson, P; Huegging, F; Jackson, P; Kocian, M; Rivero, F; Rohne, O; Sandaker, H; Sjobak, K; Slavicek, T; Tsung, W; Tsybychev, D; Wermes, N; Young, C

    2009-01-01

    3D Silicon sensors fabricated at FBK-irst with the Double-side Double Type Column (DDTC) approach and columnar electrodes only partially etched through p-type substrates were tested in laboratory and in a 1.35 Tesla magnetic field with a 180GeV pion beam at CERN SPS. The substrate thickness of the sensors is about 200um, and different column depths are available, with overlaps between junction columns (etched from the front side) and ohmic columns (etched from the back side) in the range from 110um to 150um. The devices under test were bump bonded to the ATLAS Pixel readout chip (FEI3) at SELEX SI (Rome, Italy). We report leakage current and noise measurements, results of functional tests with Am241 gamma-ray sources, charge collection tests with Sr90 beta-source and an overview of preliminary results from the CERN beam test.

  3. Preliminary Results of 3D-DDTC Pixel Detectors for the ATLAS Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, Alessandro; /CERN; Boscardin, M.; /Fond. Bruno Kessler, Povo; Dalla Betta, G.-F.; /Trento U. /INFN, Trento; Darbo, G.; Gemme, C.; /INFN, Genoa; Pernegger, H.; /CERN; Piemonte, C.; /Fond. Bruno Kessler, Povo; Povoli, M.; /Trento U. /INFN, Trento; Ronchin, S.; /Fond. Bruno Kessler, Povo; Zoboli, A.; /Trento U. /INFN, Trento; Zorzi, N.; /Fond. Bruno Kessler, Povo; Bolle, E.; /Oslo U.; Borri, M.; /INFN, Turin /Turin U.; Da Via, C.; /Manchester U.; Dong, S.; /SLAC; Fazio, S.; /Calabria U.; Grenier, P.; /SLAC; Grinstein, S.; /Barcelona, IFAE; Gjersdal, H.; /Oslo U.; Hansson, P.; /SLAC; Huegging, F.; /Bonn U. /SLAC /INFN, Turin /Turin U. /Oslo U. /Bergen U. /Oslo U. /Prague, Tech. U. /Bonn U. /SUNY, Stony Brook /Bonn U. /SLAC

    2012-04-04

    3D Silicon sensors fabricated at FBK-irst with the Double-side Double Type Column (DDTC) approach and columnar electrodes only partially etched through p-type substrates were tested in laboratory and in a 1.35 Tesla magnetic field with a 180 GeV pion beam at CERN SPS. The substrate thickness of the sensors is about 200 {mu}m, and different column depths are available, with overlaps between junction columns (etched from the front side) and ohmic columns (etched from the back side) in the range from 110 {mu}m to 150 {mu}m. The devices under test were bump bonded to the ATLAS Pixel readout chip (FEI3) at SELEX SI (Rome, Italy). We report leakage current and noise measurements, results of functional tests with Am{sup 241} {gamma}-ray sources, charge collection tests with Sr90 {beta}-source and an overview of preliminary results from the CERN beam test.

  4. Alignment of the Pixel and SCT Modules for the 2004 ATLAS Combined Test Beam

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Ahmad, A.; Andreazza, A.; Atkinson, T.; Baines, J.; Barr, A.J.; Beccherle, R.; Bell, P.J.; Bernabeu, J.; Broklova, Z.; Bruckman de Renstrom, P.A.; Cauz, D.; Chevalier, L.; Chouridou, S.; Citterio, M.; Clark, A.; Cobal, M.; Cornelissen, T.; Correard, S.; Costa, M.J.; Costanzo, D.; Cuneo, S.; Dameri, M.; Darbo, G.; de Vivie, J.B.; Di Girolamo, B.; Dobos, D.; Drasal, Z.; Drohan, J.; Einsweiler, K.; Elsing, M.; Emelyanov, D.; Escobar, C.; Facius, K.; Ferrari, P.; Fergusson, D.; Ferrere, D.; Flick,, T.; Froidevaux, D.; Gagliardi, G.; Gallas, M.; Gallop, B.J.; Gan, K.K.; Garcia, C.; Gavrilenko, I.L.; Gemme, C.; Gerlach, P.; Golling, T.; Gonzalez-Sevilla, S.; Goodrick, M.J.; Gorfine, G.; Gottfert, T.; Grosse-Knetter, J.; Hansen, P.H.; Hara, K.; Hartel, R.; Harvey, A.; Hawkings, R.J.; Heinemann, F.E.W.; Henss, T.; Hill, J.C.; Huegging, F.; Jansen, E.; Joseph, J.; Unel, M. Karagoz; Kataoka, M.; Kersten, S.; Khomich, A.; Klingenberg, R.; Kodys, P.; Koffas, T.; Konstantinidis, N.; Kostyukhin, V.; Lacasta, C.; Lari, T.; Latorre, S.; Lester, C.G.; Liebig, W.; Lipniacka, A.; Lourerio, K.F.; Mangin-Brinet, M.; Marti i Garcia, S.; Mathes, M.; Meroni, C.; Mikulec, B.; Mindur, B.; Moed, S.; Moorhead, G.; Morettini, P.; Moyse, E.W.J.; Nakamura, K.; Nechaeva, P.; Nikolaev, K.; Parodi, F.; Parzhitskiy, S.; Pater, J.; Petti, R.; Phillips, P.W.; Pinto, B.; Poppleton, A.; Reeves, K.; Reisinger, I.; Reznicek, P.; Risso, P.; Robinson, D.; Roe, S.; Rozanov, A.; Salzburger, A.; Sandaker, H.; Santi, L.; Schiavi, C.; Schieck, J.; Schultes, J.; Sfyrla, A.; Shaw, C.; Tegenfeldt, F.; Timmermans, C.J.W.P.; Toczek, B.; Troncon, C.; Tyndel, M.; Vernocchi, F.; Virzi, J.; Anh, T. Vu; Warren, M.; Weber, J.; Weber, M.; Weidberg, A.R.; Weingarten, J.; Wellsf, P.S.; Zhelezkow, A.

    2008-06-02

    A small set of final prototypes of the ATLAS Inner Detector silicon tracking system(Pixel Detector and SemiConductor Tracker), were used to take data during the 2004 Combined Test Beam. Data were collected from runs with beams of different flavour (electrons, pions, muons and photons) with a momentum range of 2 to 180 GeV/c. Four independent methods were used to align the silicon modules. The corrections obtained were validated using the known momenta of the beam particles and were shown to yield consistent results among the different alignment approaches. From the residual distributions, it is concluded that the precision attained in the alignmentof the silicon modules is of the order of 5 mm in their most precise coordinate.

  5. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  6. Characterization of silicon 3D pixel detectors for the ATLAS Forward Physics experiment

    Energy Technology Data Exchange (ETDEWEB)

    Lopez Paz, I.; Cavallaro, E.; Lange, J. [Institut de Fisica d' Altes Energies - IFAE, 08193 Bellaterra, Barcelona (Spain); Grinstein, S. [Institut de Fisica d' Altes Energies - IFAE, 08193 Bellaterra, Barcelona (Spain); Catalan Institution for Research and Advanced Studies - ICREA, Barcelona (Spain)

    2015-07-01

    The ATLAS Forward Physics (AFP) project aims to measure protons scattered under a small angle from the pp collisions in ATLAS. In order to perform such measurements, a new silicon tracker, together with a time-of-flight detector for pile-up removal, are planned to be installed at ∼210 m from the interaction point and at 2-3 mm from the LHC proton beam. To cope with such configuration and maximize the physics outcome, the tracker has to fulfil three main requirements: endure highly non-uniform radiation doses, due to the very inhomogeneous beam profile, have slim and efficient edges to improve the acceptance of the tracker, and provide good position resolution. Recent laboratory and beam test characterization results of AFP prototypes will be presented. Slim-edged 3D pixel detectors down to 100-200 μm were studied and later non-uniformly irradiated (with a peak fluence of several 10{sup 15} n{sub eq}/cm{sup 2}) to determine the fulfilment of the AFP requirements. (authors)

  7. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  8. Characterization and Performance of Silicon n-in-p Pixel Detectors for the ATLAS Upgrades

    CERN Document Server

    Weigell, Philipp; Gallrapp, Christian; La Rosa, Alessandro; Macchiolo, Anna; Nisius, Richard; Pernegger, Heinz; Richter, Rainer

    2011-01-01

    The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities (super LHC) the development of new structures and materials which can cope with the resulting particle fluences is needed. N-in-p silicon devices are a promising candidate for tracking detectors to achieve these goals, since they are radiation hard, cost efficient and are not type inverted after irradiation. A n-in-p pixel production based on a MPP/HLL design and performed by CiS (Erfurt, Germany) on 300 \\mu m thick Float-Zone material is characterised and the electrical properties of sensors and single chip modules (SCM) are presented, including noise, charge collection efficiencies, and measurements with MIPs as well as an 241Am source. The SCMs are built with sensors connected to the current the ATLAS read-out chip FE-I3. The characterisation has been performed with the ATL...

  9. Radiation hardness studies of n{sup +}-in-n planar pixel sensors for the ATLAS upgrades

    Energy Technology Data Exchange (ETDEWEB)

    Altenheiner, S.; Goessling, C.; Jentzsch, J.; Klingenberg, R. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Muenstermann, D., E-mail: Daniel.Muenstermann@TU-Dortmund.de [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany); Rummler, A.; Troska, G.; Wittig, T. [Lehrstuhl fuer Experimentelle Physik IV, TU Dortmund, 44221 Dortmund (Germany)

    2011-12-01

    The ATLAS experiment at the LHC is planning upgrades of its pixel detector to cope with the luminosity increase foreseen in the coming years within the transition from LHC to Super-LHC (SLHC/HL-LHC). Associated with the increase in instantaneous luminosity is a rise of the target integrated luminosity from 730 to about 3000 fb{sup -1} which directly translates into significantly higher radiation damage. These upgrades consist of the installation of a 4th pixel layer, the insertable b-layer IBL, with a mean sensor radius of only 32 mm from the beam axis, before 2016/17. In addition, the complete pixel detector will be exchanged before 2020/21. Being very close to the beam, the radiation damage of the IBL sensors might be as high as 5 Multiplication-Sign 10{sup 15}n{sub eq}cm{sup -2} at their end-of-life. The total fluence of the innermost pixel layer after the SLHC upgrade might even reach 2 Multiplication-Sign 10{sup 16}n{sub eq}cm{sup -2}. To investigate the radiation hardness and suitability of the current ATLAS pixel sensors for these fluences, n{sup +}-in-n silicon pixel sensors from the ATLAS Pixel production have been irradiated by reactor neutrons to the IBL design fluence and been tested with pions at the SPS and with electrons from a {sup 90}Sr source in the laboratory. The collected charge after IBL fluences was found to exceed 10 000 electrons per MIP at 1 kV of bias voltage which is in agreement with data collected with strip sensors. After SLHC fluences, still reliable operation of the devices could be observed with a collected charge of more than 5000 electrons per MIP.

  10. Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

    The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

  11. Silvaco ATLAS model of ESA's Gaia satellite e2v CCD91-72 pixels

    CERN Document Server

    Seabroke, G M; Burt, D; Robbins, M S; 10.1117/12.856958

    2010-01-01

    The Gaia satellite is a high-precision astrometry, photometry and spectroscopic ESA cornerstone mission, currently scheduled for launch in 2012. Its primary science drivers are the composition, formation and evolution of the Galaxy. Gaia will achieve its unprecedented accuracy requirements with detailed calibration and correction for CCD radiation damage and CCD geometric distortion. In this paper, the third of the series, we present our 3D Silvaco ATLAS model of the Gaia e2v CCD91-72 pixel. We publish e2v's design model predictions for the capacities of one of Gaia's pixel features, the supplementary buried channel (SBC), for the first time. Kohley et al. (2009) measured the SBC capacities of a Gaia CCD to be an order of magnitude smaller than e2v's design. We have found the SBC doping widths that yield these measured SBC capacities. The widths are systematically 2 {\\mu}m offset to the nominal widths. These offsets appear to be uncalibrated systematic offsets in e2v photolithography, which could either be du...

  12. Simulation of the depletion voltage evolution of the ATLAS Pixel Detector

    CERN Document Server

    Beyer, Julien-christopher; The ATLAS collaboration

    2017-01-01

    The ATLAS Pixel detector has been operating since 2010 and consists of hybrid pixel modules where the sensitive elements are planar n-in-n sensors. In order to investigate and predict the evolution of the depletion voltage and of the leakage current in the different layers, a fully analytical implementation of the Hamburg model was derived. The parameters of the model, describing the dependence of the depletion voltage (U_depl) on fluence, temperature and time were tuned with a fit to the available measurements of Udepl in the last years of operation. A particular emphasis is put on the B-Layer, where the highest fluence has been accumulated up to now. A precise input of temperature and radiation dose is generated from the on-module temperature monitoring and the luminosity data. The analysis is then also extended to the Insertable B-Layer (IBL), installed at the end of Run-1, where we expect the fastest evolution of the radiation damage with luminosity, due to its closer position to the interaction point. Di...

  13. Front-end ASIC for pixilated wide bandgap detectors

    Science.gov (United States)

    Vernon, Emerson; de Geronimo, Gianluigi; Fried, Jack; Herman, Cedric; Zhang, Feng; He, Zhong

    2009-08-01

    A CMOS application specific integrated circuit (ASIC) was developed for 3D Position Sensitive Detectors (PSD). The preamplifiers were optimized for pixellated Cadmium-Zinc-Telluride (CZT) Mercuric-Iodide (HgI2) and Thallium Bromide (TlBr) sensors. The ASIC responds to an ionizing event in the sensor by measuring both amplitude and timing in the pertinent anode and cathode channels. Each channel is sensitive to events and transients of positive or negative polarity and performs low-noise charge amplification, high-order shaping, peak and timing detection along with analog storage and multiplexing. Three methodologies are implemented to perform timing measurement in the cathode channel. Multiple sparse modes are available for the readout of channel data. The ASIC integrates 130 channels in an area of 12 x 9 mm2 and dissipates ~330 mW. With a CZT detector connected and biased, an electronic resolution of ~200 e- rms for charges up to 100 fC was measured. Spectral data from the University of Michigan revealed a cumulative single-pixel resolution of ~0.55 % FWHM at 662 KeV.

  14. ATLAS-TPX: a two-layer pixel detector setup for neutron detection and radiation field characterization

    Science.gov (United States)

    Bergmann, B.; Caicedo, I.; Leroy, C.; Pospisil, S.; Vykydal, Z.

    2016-10-01

    A two-layer pixel detector setup (ATLAS-TPX), designed for thermal and fast neutron detection and radiation field characterization is presented. It consists of two segmented silicon detectors (256 × 256 pixels, pixel pitch 55 μm, thicknesses 300 μm and 500 μm) facing each other. To enhance the neutron detection efficiency a set of converter layers is inserted in between these detectors. The pixelation and the two-layer design allow a discrimination of neutrons against γs by pattern recognition and against charged particles by using the coincidence and anticoincidence information. The neutron conversion and detection efficiencies are measured in a thermal neutron field and fast neutron fields with energies up to 600 MeV. A Geant4 simulation model is presented, which is validated against the measured detector responses. The reliability of the coincidence and anticoincidence technique is demonstrated and possible applications of the detector setup are briefly outlined.

  15. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  16. Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Macchiolo, A.; Beyer, J.; La Rosa, A.; Nisius, R.; Savic, N.

    2017-01-01

    The ATLAS experiment will undergo around the year 2025 a replacement of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) with a new 5-layer pixel system. Thin planar pixel sensors are promising candidates to instrument the innermost region of the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. The sensors of 50-150 μm thickness, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests. In particular active edge sensors have been investigated. The performance of two different versions of edge designs are compared: the first with a bias ring, and the second one where only a floating guard ring has been implemented. The hit efficiency at the edge has also been studied after irradiation at a fluence of 1015 neq/cm2. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angles with respect to the short pixel direction. Results on the hit efficiency in this configuration are discussed for different sensor thicknesses.

  17. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  18. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  19. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    Abstract: Most industries face continuing pressures from rising R&D costs, shortening product lifecycles and global competition. These challenges have increased the focus on shortening development times, which again puts pressure on the efficiency of front end innovation (FEI). In the attempt...... to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...

  20. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  1. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  2. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  3. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  4. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    OpenAIRE

    Bin You; Bo Yang; Xuan Wen; Liangyu Qu

    2013-01-01

    A new ultrahigh frequency radio frequency identification (UHF RFID) reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS) circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both th...

  5. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken into acco...... into account. The accuracy of the expressions has been verified by using Touchstone simulator. The agreement between the calculated and simulated front end performances is very good....

  6. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  7. Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

    Science.gov (United States)

    Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

    2017-01-01

    A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

  8. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  9. Submission of the first full scale prototype chip for upgraded ATLAS pixel detector at LHC, FE-I4A

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon, E-mail: barbero@physik.uni-bonn.de [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Arutinov, David [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Beccherle, Roberto; Darbo, Giovanni [INFN Genova, via Dodecaseno 33, IT-16146 Genova (Italy); Dube, Sourabh; Elledge, David; Fleury, Julien [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Fougeron, Denis [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Garcia-Sciveres, Maurice [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Gensolen, Fabrice [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Gnani, Dario [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Gromov, Vladimir [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); Jensen, Frank [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Hemperek, Tomasz; Karagounis, Michael [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Kluit, Ruud [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); Kruth, Andre [Physikalisches Institut Universitaet Bonn, Nussallee 12, 53115 Bonn (Germany); Mekkaoui, Abderrezak [Lawrence Berkeley National Laboratory, 1 Cyclotron Road, CA 94720 (United States); Menouni, Mohsine [CPPM Aix-Marseille Universite, CNRS/IN2P3, Marseille (France); Schipper, Jan David [NIKHEF, Science Park 105, 1098 XG Amsterdam (Netherlands); and others

    2011-09-11

    A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25{mu}m CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80x336 pixels, each 50x250{mu}m{sup 2}, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences between the FE-I4A IC and the final FE-I4 as envisioned for IBL.

  10. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-01-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  11. Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

    CERN Document Server

    INSPIRE-00304438; Gkougkousis, E.; Lounis, A.

    2015-01-01

    The LHC accelerator complex will be upgraded between 2020-2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented.

  12. Silicon sensor technologies for ATLAS IBL upgrade

    CERN Document Server

    Grenier, P; The ATLAS collaboration

    2011-01-01

    New pixel sensors are currently under development for ATLAS Upgrades. The first upgrade stage will consist in the construction of a new pixel layer that will be installed in the detector during the 2013 LHC shutdown. The new layer (Insertable-B-Layer, IBL) will be inserted between the inner most layer of the current pixel detector and the beam pipe at a radius of 3.2cm. The expected high radiation levels require the use of radiation hard technology for both the front-end chip and the sensor. Two different pixel sensor technologies are envisaged for the IBL. The sensor choice will occur in July 2011. One option is developed by the ATLAS Planar Pixel Sensor (PPS) Collaboration and is based on classical n-in-n planar silicon sensors which have been used for the ATLAS Pixel detector. For the IBL, two changes were required: The thickness was reduced from 250 um to 200 um to improve the radiation hardness. In addition, so-called "slim edges" were designed to reduce the inactive edge of the sensors from 1100 um to o...

  13. Custom single-photon avalanche diode with integrated front-end for parallel photon timing applications.

    Science.gov (United States)

    Cammi, C; Panzeri, F; Gulinatti, A; Rech, I; Ghioni, M

    2012-03-01

    Emerged as a solid state alternative to photo multiplier tubes (PMTs), single-photon avalanche diodes (SPADs) are nowadays widely used in the field of single-photon timing applications. Custom technology SPADs assure remarkable performance, in particular a 10 counts/s dark count rate (DCR) at low temperature, a high photon detection efficiency (PDE) with a 50% peak at 550 nm and a 30 ps (full width at half maximum, FWHM) temporal resolution, even with large area devices, have been obtained. Over the past few years, the birth of novel techniques of analysis has led to the parallelization of the measurement systems and to a consequent increasing demand for the development of monolithic arrays of detectors. Unfortunately, the implementation of a multidimensional system is a challenging task from the electrical point of view; in particular, the avalanche current pick-up circuit, used to obtain the previously reported performance, has to be modified in order to enable high parallel temporal resolution, while minimizing the electrical crosstalk probability between channels. In the past, the problem has been solved by integrating the front-end electronics next to the photodetector, in order to reduce the parasitic capacitances and consequently the filtering action on the current signal of the SPAD, leading to an improvement of the timing jitter at higher threshold. This solution has been implemented by using standard complementary metal-oxide-semiconductor (CMOS) technologies, which, however, do not allow a complete control on the SPAD structure; for this reason the intrinsic performance of CMOS SPADs, such as DCR, PDE, and afterpulsing probability, are worse than those attainable with custom detectors. In this paper, we propose a pixel architecture, which enables the development of custom SPAD arrays in which every channel maintains the performance of the best single photodetector. The system relies on the integration of the timing signal pick-up circuit next to the

  14. Design of the NSLS-II Linac Front End Test Stand

    Energy Technology Data Exchange (ETDEWEB)

    Fliller III, R.; Johanson, M.; Lucas, M.; Rose, J.; Shaftan, T.

    2011-03-28

    The NSLS-II operational parameters place very stringent requirements on the injection system. Among these are the charge per bunch train at low emittance that is required from the linac along with the uniformity of the charge per bunch along the train. The NSLS-II linac is a 200 MeV linac produced by Research Instruments Gmbh. Part of the strategy for understanding to operation of the injectors is to test the front end of the linac prior to its installation in the facility. The linac front end consists of a 100 kV electron gun, 500 MHz subharmonic prebuncher, focusing solenoids and a suite of diagnostics. The diagnostics in the front end need to be supplemented with an additional suite of diagnostics to fully characterize the beam. In this paper we discuss the design of a test stand to measure the various properties of the beam generated from this section. In particular, the test stand will measure the charge, transverse emittance, energy, energy spread, and bunching performance of the linac front end under all operating conditions of the front end.

  15. Prediction and control of front-end curvature in hot finish rolling process

    Directory of Open Access Journals (Sweden)

    Kyunghun Lee

    2015-11-01

    Full Text Available The purpose of this study is to predict the front-end curvature in hot strip finishing mills and to prevent it by controlling the rolling conditions. A theoretical model based on the slab method is developed for predicting the front-end curvature by taking into account the entrance angle of the strip, the friction condition and the back tension. To validate the developed theoretical model, the theoretically obtained curvature value is compared with the results of finite element analysis. Consequently, it is shown that the calculation results of the theoretical model are in good agreement with the measured results of the finite element analysis. Furthermore, a curvature control model based on geometrical and mathematical approaches that can reduce the front-end curvature by the control of the roll speed ratio of the upper to lower rolls is proposed. The proposed curvature control model is verified by finite element analysis, and it is shown that the front-end curvature can be reduced considerably using the proposed model. Therefore, it is concluded that the proposed control model for reducing the front-end curvature in a hot strip finishing mill can be used to improve the quality of the rolled product.

  16. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    Energy Technology Data Exchange (ETDEWEB)

    Prior, G. [Canterbury U.; Efthymiopoulos, I. [CERN; Stratakis, D. [Brookhaven; Neuffer, D. [Fermilab; Snopok, P. [Fermilab; Rogers, C. [Rutherford

    2013-06-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the front-end channel performance where the magnetic field direction has been altered compared to the baseline.

  17. The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407702

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

  18. Tracking and flavour-tagging performance for HV-CMOS sensors in the context of the ATLAS ITK pixel simulation program

    Science.gov (United States)

    Calandri, A.; Vacavant, L.; Barbero, M.; Rozanov, A.; Djama, F.

    2016-12-01

    The HV-CMOS (High Voltage - Complementary Metal-Oxide Semiconductor) pixel technology has recently risen interest for the upgrade of the pixel detector of the ATLAS experiment towards the High Luminosity phase of the Large Hadron Collider (LHC) . HV-CMOS sensors can be employed in the pixel outer layers (R >15 cm), where the radiation hardness requirements are less stringent, as they could instrument large areas at a relatively low cost. In addition, smaller pixel granularity can be achieved by exploiting sub-pixel encoding technology. Therefore, the largest impact on physics performance, tracking and flavour tagging, could be reached if exploited in the innermost layer (in place of the current IBL) or in the next-to-innermost layer. This proceeding will present studies on tracking and flavour-tagging performance in presence of HV-CMOS sensors in the innermost layer of the ATLAS detector.

  19. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

  20. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

  1. Performance and description of the upgraded readout with the new back-end electronics for the ATLAS Pixel detector

    CERN Document Server

    Yajima, Kazuki; The ATLAS collaboration

    2017-01-01

    LHC increased drastically its performance during the RUN2 data taking, starting from a peak instantaneous luminosity of up to $5\\times10^{33} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in 2015 to conclude with the record value of $1.4\\times10^{34} \\mathrm{cm}^{-2} \\mathrm{s}^{-1}$ in November 2016. The concurrent increase of the trigger rate and event size forced the ATLAS experiment to exploit its sub-detectors to the maximum, approaching and possibly overcoming the design parameters. The ATLAS Pixel data acquisition system was upgraded to avoid possible bandwidth limitations. Two upgrades of the read-out electronics have been done. The first one during 2015/16 YETS, when the outermost pixel layer (Layer-2) was upgraded and its bandwidth was doubled. This upgrade partly contributed to maintain the data taking efficiency of the Pixel detector at a relatively high level ($\\sim$99%) during the 2016 run. A similar upgrade of the read-out system for the middle layer (Layer-1) is ongoing during 2016/17 EYETS. The details o...

  2. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    CERN Document Server

    Terzo, Stefano; Nisius, R.; Paschen, B.

    2014-01-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 $\\mu$m, produced at CiS, and 100-200 $\\mu$m thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The perfo...

  3. A wide bandwidth analog front-end circuit for 60-GHz wireless communication receiver

    Science.gov (United States)

    Furuta, M.; Okuni, H.; Hosoya, M.; Sai, A.; Matsuno, J.; Saigusa, S.; Itakura, T.

    2014-03-01

    This paper presents an analog front-end circuit for a 60-GHz wireless communication receiver. The feature of the proposed analog front-end circuit is a bandwidth more than 1-GHz wide. To expand the bandwidth of a low-pass filter and a voltage gain amplifier, a technique to reduce the parasitic capacitance of a transconductance amplifier is proposed. Since the bandwidth is also limited by on-resistance of the ADC sampling switch, a switch separation technique for reduction of the on-resistance is also proposed. In a high-speed ADC, the SNDR is limited by the sampling jitter. The developed high resolution VCO auto tuning effectively reduces the jitter of PLL. The prototype is fabricated in 65nm CMOS. The analog front-end circuit achieves over 1-GHz bandwidth and 27.2-dB SNDR with 224 mW Power consumption.

  4. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  5. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology.

  6. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... and tendencies in formal R&D partnering relations. This paper, however, focuses on collaboration between independent companies prior to such formal agreements as joint ventures or other contractual agreements. This first phase of the innovation process is often referred to as the Fuzzy Front-End (FFE......) and is traditionally seen as an intra-organizational process (Jongbae & David 2002;Kim & Wilemon 2002e;Qingyu & William 2001;Reid & de Brentani 2004a). As the innovation process becomes an interfirm-collaboration the management of the Fuzzy Front-End also changes and calls for new ways of collaboration...

  7. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  8. SEMICONDUCTOR INTEGRATED CIRCUITS Design of an analog front-end for ambulatory biopotential measurement systems

    Science.gov (United States)

    Jiazhen, Wang; Jun, Xu; Lirong, Zheng; Junyan, Ren

    2010-10-01

    A continuously tunable gain and bandwidth analog front-end for ambulatory biopotential measurement systems is presented. The front-end circuit is capable of amplifying and conditioning different biosignals. To optimize the power consumption and simplify the system architecture, the front-end only adopts two-stage amplifiers. In addition, careful design eliminates the need for chopping circuits. The input-referred noise of the system is only 1.19 μVrms (0.48-2000 Hz). The chip is fabricated via a SMIC 0.18 μm CMOS process. Although the power consumption is only 32.1 μW under a 3 V voltage supply, test results show that the chip can successfully extract biopotential signals.

  9. Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

    CERN Document Server

    Giacomini, Gabriele; Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

    2014-01-01

    In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch.

  10. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    Calderini, G; Bomben, M; Boscardin, M; Bosisio, L; Chauveau, J; Giacomini, G; La Rosa, A; Marchiori, G; Zorzi, N

    2014-01-01

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R&D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  11. Implementation of Low-Cost UHF RFID Reader Front-Ends with Carrier Leakage Suppression Circuit

    Directory of Open Access Journals (Sweden)

    Bin You

    2013-01-01

    Full Text Available A new ultrahigh frequency radio frequency identification (UHF RFID reader’s front-end circuit which is based on zero-IF, single antenna structure and composed of discrete components has been designed. The proposed design brings a significant improvement of the reading performance by adopting a carrier leakage suppression (CLS circuit instead of a circulator which is utilized by most of the conventional RF front-end circuit. Experimental results show that the proposed design improves both the sensitivity and detection range compared to the conventional designs.

  12. Implementation of a 66 MHz analog memory as a front end for LHC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Munday, D.J.; Parker, M.A. (Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE (United Kingdom)); Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Gros, J.; Jarron, P.; Heijne, E.H.M.; Meddeler, G.; Pollet, L.; Santiard, J.C.; Verweij, H. (CERN, CH-1211 Geneva 23 (Switzerland)); Goessling, C.; Lisowsky, B. (Institut fuer Physik, Universitaet Dortmund, D-4600 Dortmund (Germany)); Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; La Marra, D.; Wu, X. (DPNC, Geneva University, CH-1211, Geneva 4 (Switzerland)); Moorhead, G. (School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia)); Weidberg, A. (Department of Nuclear Physics, Oxford University, Oxford (United Kingdom)); Campbell, D.; Murray, P.; Seller, P.; Stevens, R. (Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)); Beuville, E.; Rouger, M.; Teiger, J. (Centre d' Etudes Nucleaires de Saclay, F-91191 Gif-sur-Yvette (France))

    1992-02-05

    We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

  13. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...... be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  14. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Energy Technology Data Exchange (ETDEWEB)

    Gevin, O.; Lemaire, O.; Lugiez, F. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Michalowska, A., E-mail: alicja.michalowska@cea.fr [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Baron, P. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France); Limousin, O. [CEA, Irfu, Service d' Astrophysique, Bat. 709 Orme des Merisiers, F-91191 Gif-sur-Yvette (France); Delagnes, E. [CEA, Irfu, Service d' Electronique, de Detecteurs et d' Informatique, Bat. 141, F-91191 Gif-sur-Yvette (France)

    2012-12-11

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16 Multiplication-Sign 16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 {mu}m CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 {mu}W per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 {mu}s peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 Degree-Sign C.

  15. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Science.gov (United States)

    Gevin, O.; Lemaire, O.; Lugiez, F.; Michalowska, A.; Baron, P.; Limousin, O.; Delagnes, E.

    2012-12-01

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  16. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Energy Technology Data Exchange (ETDEWEB)

    Sekiya, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)]. E-mail: sekiya@cr.scphys.kyoto-u.ac.jp; Hattori, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Kubo, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Miuchi, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Nagayoshi, T. [Advanced Research Institute for Science and Engineering, Waseda University, 17 Kikui-cho, Shinjuku, Tokyo 162-0044 (Japan); Nishimura, H. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Okada, Y. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Orito, R. [Department of Physics, Graduate School of Science and Technology, Kobe University, 1-1 Rokkoudai, Nada, Kobe 657-8501 (Japan); Takada, A. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Takeda, A. [Kamioka Observatory, ICRR, University of Tokyo, 456 Higasi-mozumi, Hida-shi, Gifu 506-1205 (Japan); Tanimori, T. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan); Ueno, K. [Department of Physics, Graduate School of Science, Kyoto University, Kitashirakawa, Sakyo, Kyoto 606-8502 (Japan)

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6x6x20mm{sup 3} which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of {sup 137}Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  17. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    CERN Document Server

    Sekiya, H; Kubo, H; Miuchi, K; Nagayoshi, T; Nishimura, H; Okada, Y; Orito, R; Takada, A; Takeda, A; Tanimori, T; Ueno, K

    2006-01-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of $6\\times6\\times20{\\rm mm}^3$ which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to readout every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of $^{137}$Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  18. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    Science.gov (United States)

    Sekiya, H.; Hattori, K.; Kubo, H.; Miuchi, K.; Nagayoshi, T.; Nishimura, H.; Okada, Y.; Orito, R.; Takada, A.; Takeda, A.; Tanimori, T.; Ueno, K.

    2006-07-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6×6×20 mm3 which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6 mm) was clearly resolved by flood field irradiation of 137Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors.

  19. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  20. Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    INSPIRE-00052711; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

    2016-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

  1. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, Michael

    2010-07-19

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 10{sup 35}/cm{sup 2}s{sup 1} is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).10{sup 16} 1-MeV-neutrons per square centimeter (n{sub eq}/cm{sup 2}). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 {mu}m and 150 {mu}m proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive

  2. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Beccherle, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Pisa (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste (Italy); INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2016-09-21

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  3. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Science.gov (United States)

    Calderini, G.; Bagolini, A.; Beccherle, R.; Bomben, M.; Boscardin, M.; Bosisio, L.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

    2016-09-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  4. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  5. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  6. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  7. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study aim

  8. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  9. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  10. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels;

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

  11. Low power analog readout front-end electronics for time and energy measurements

    Energy Technology Data Exchange (ETDEWEB)

    Kleczek, R., E-mail: rafal.kleczek@agh.edu.pl; Grybos, P.; Szczygiel, R.

    2014-06-01

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time t{sub p}=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC){sup 2} shaper with the peaking time t{sub p}=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation P{sub diss}=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results.

  12. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  13. Advances ,n Digital Front-End and Software RF Processing: Part I

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    One of the biggest technology trends in wireless broadband, radar, sonar, and broadcasting systems is software radio frequency processing and digital front-end. This trend encompasses a broad range of topics, from circuit design and signal processing to system integration. It includes digital up-conversion (DUC) and down-conversion (DDC), digital predistortion (DPD),

  14. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  15. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo;

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing...

  16. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  17. The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

    2015-07-01

    The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

  18. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which...

  19. Radiation hardness improvement of analog front-end microelectronic devices for particle accelerator

    Science.gov (United States)

    Miroshnichenko, A. G.; Rodin, A. S.; Bakerenkov, A. S.; Felitsyn, V. A.

    2016-10-01

    Series of schematic techniques for increasing radiation hardness of the current mirrors is developed. These techniques can be used for the design of analog front-end microelectronic devices based on the operational amplifiers. The circuit simulation of radiation degradation of current transmission coefficients was performed for various circuit solutions in LTSpice software.

  20. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J.A.; Kooijman, P.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  1. Commissioning and operation of the FNAL front end injection line and ion sources

    Science.gov (United States)

    Karns, Patrick R.

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  2. Practices of a "green" front end of innovation; A gateway to environmental innovation

    NARCIS (Netherlands)

    Hassi, L.; Wever, R.

    2010-01-01

    Activities in the fuzzy front end of the innovation process (FFE) are the root of success for any company hoping to compete on the basis of innovations. Considering the importance of the FFE, it would seem logical to bring the environmental considerations already to the activities of the early stage

  3. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; Van Engelen, Jo; Achterkamp, Madolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to supp

  4. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, A.D.

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition o

  5. Managing inter-firm collaboration in the fuzzy front-end

    DEFF Research Database (Denmark)

    Jørgensen, Jacob; Bergenholtz, Carsten; Goduscheit, René Chester

    2011-01-01

    organisations in an innovation network are somewhat neglected in the literature. The aim of this paper is hence to address the challenges that an organisation faces when integrating a plurality of suppliers, customers and other organisations into the Fuzzy Front End of the innovation process....

  6. Understanding Managers Decision Making Process for Tools Selection in the Core Front End of Innovation

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.

    2011-01-01

    New product development (NPD) describes the process of bringing a new product or service to the market. The Fuzzy Front End (FFE) of Innovation is the term describing the activities happening before the product development phase of NPD. In the FFE of innovation, several tools are used to facilitate...

  7. High speed data transmission on small gauge cables for the ATLAS Phase-II Pixel detector upgrade

    Science.gov (United States)

    Shahinian, J.; Volk, J.; Fadeyev, V.; Grillo, A. A.; Meimban, B.; Nielsen, J.; Wilder, M.

    2016-03-01

    The High Luminosity LHC will present a number of challenges for the upgraded ATLAS detector. In particular, data transmission requirements for the upgrade of the ATLAS Pixel detector will be difficult to meet. The expected trigger rate and occupancy imply multi-gigabit per second transmission rates will be required but radiation levels at the smallest radius preclude completely optical solutions. Electrical transmission up to distances of 7m will be necessary to move optical components to an area with lower radiation levels. Here, we explore the use of small gauge electrical cables as a high-bandwidth, radiation hard solution with a sufficiently small radiation length. In particular, we present a characterization of various twisted wire pair (TWP) configurations of various material structures, including measurements of their bandwidth, crosstalk, and radiation hardness. We find that a custom ``hybrid'' cable consisting of 1m of a multi-stranded TWP with Poly-Ether-Ether-Ketone (PEEK) insulation and a thin Al shield followed by 6m of a thin twin-axial cable presents a low-mass solution that fulfills bandwidth requirements and is expected to be sufficiently radiation hard. Additionally, we discuss preliminary results of using measured S-parameters to produce a SPICE model for a 1m sample of the custom TWP to be used for the development of new pixel readout chips.

  8. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  9. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric,I et al.

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  10. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  11. The front-end electronics of the Spectrometer Telescope for Imaging X-Rays (STIX) on the ESA Solar Orbiter satellite

    Science.gov (United States)

    Grimm, O.; Bednarzik, M.; Commichau, V.; Graczyk, R.; Gröbelbauer, H. P.; Hurford, G.; Krucker, S.; Limousin, O.; Meuris, A.; Orleański, P.; Przepiórka, A.; Seweryn, K.; Skup, K.; Viertel, G.

    2012-12-01

    Solar Orbiter is an ESA mission to study the heliosphere in proximity to the Sun, scheduled for launch in January 2017. It carries a suite of ten instruments for comprehensive remote-sensing and in-situ measurements. The Spectrometer Telescope for Imaging X-Rays (STIX), one of the remote sensing instruments, images X-rays between 4 and 150keV using an Fourier technique. The angular resolution is 7 arcsec and the spectral resolution 1keV full-width-half-maximum at 6keV. X-ray detection uses pixelized Cadmium Telluride crystals provided by the Paul Scherrer Institute. The crystals are bonded to read-out hybrids developed by CEA Saclay, called Caliste-SO, incorporating a low-noise, low-power analog front-end ASIC IDeF-X HD. The crystals are cooled to -20°C to obtain very low leakage currents of less than 60pA per pixel, the prerequisite for obtaining the required spectral resolution. This article briefly describes the mission goals and then details the front-end electronics design and main challenges, resulting in part from the allocation limit in mass of 7kg and in power of 4W. Emphasis is placed on the design influence of the cooling requirement within the warm environment of a mission approaching the Sun to within the orbit of Mercury. The design for the long-term in-flight energy calibration is also explained.

  12. Active pixel sensors in AMS H18/H35 HV-CMOS technology for the ATLAS HL-LHC upgrade

    Science.gov (United States)

    Ristic, Branislav

    2016-09-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement signal processing electronics in deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150 V leading to a depletion depth of several 10 μm. Prototype sensors in the AMS H18 180 nm and H35 350 nm HV-CMOS processes were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiations with X-rays and protons revealed a tolerance to ionizing doses of 1 Grad while Edge-TCT studies assessed the effects of radiation on the charge collection. The sensors showed high detection efficiencies after neutron irradiation to 1015neq cm-2 in testbeam experiments. A full reticle size demonstrator chip, implemented in the H35 process is being submitted to prove the large scale feasibility of the HV-CMOS concept.

  13. Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268

    The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

  14. A MEMS-Based Power-Scalable Hearing Aid Analog Front End.

    Science.gov (United States)

    Deligoz, I; Naqvi, S R; Copani, T; Kiaei, S; Bakkaloglu, B; Sang-Soo Je; Junseok Chae

    2011-06-01

    A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.

  15. General-Purpose Front End for Real-Time Data Processing

    Science.gov (United States)

    James, Mark

    2007-01-01

    FRONTIER is a computer program that functions as a front end for any of a variety of other software of both the artificial intelligence (AI) and conventional data-processing types. As used here, front end signifies interface software needed for acquiring and preprocessing data and making the data available for analysis by the other software. FRONTIER is reusable in that it can be rapidly tailored to any such other software with minimum effort. Each component of FRONTIER is programmable and is executed in an embedded virtual machine. Each component can be reconfigured during execution. The virtual-machine implementation making FRONTIER independent of the type of computing hardware on which it is executed.

  16. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  17. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999......, Steven & Burly, 2003, and Vernorn et al., 2008) and that innovation strategies play a central role in optimization of innovation (Clark & Wheelwright, 1995; Cottam et al., 2001; Morgan & Berthon, 2008). Innovation strategies are suggested in literature (e.g. Page, 1993; Oke, 2002; Adams et al., 2006......; Igartua, 2010) as a facilitator of innovation and may therefore also be targeted at FEI support. The pharmaceutical industry has experienced a worldwide decline in the number of applications for new molecular entities to regulatory agencies since 1997. Therefore high pressures are put on pharmaceutical...

  18. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  19. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  20. All-Dielectric Photonic-Assisted Radio Front-End Technology

    Science.gov (United States)

    Ayazi, Hossein Ali

    The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

  1. Common front end systems for Space Shuttle and Space Station control centers at Johnson Space Center

    Science.gov (United States)

    Uljon, Linda; Muratore, John

    1993-03-01

    In the beginning of the fiscal year 1992, the development organizations of Johnson Space Center (JSC) were poised to begin two major projects: the Space Station Control Center and the refurbishment of the telemetry processing area of the Space Shuttle Mission Control Center. A study team established that a common front end concept could be used and could reduce development costs for both projects. A standard processor was defined to support most of the front end functions of both control centers and supports a consolidation of control positions which effectively reduces operations cost. This paper defines that common concept and describes the progress that has been made in development of the Consolidated Communications Facility (CCF) during the past year.

  2. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  3. A-3 dBm RF transmitter front-end for 802.11g application

    Institute of Scientific and Technical Information of China (English)

    Zhao Jinxin; Yan Jun; Shi Yin

    2013-01-01

    A 2.4 GHz,direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals.The front-end output power is-3 dBm while the corresponding EVM is-27 dB which is necessary for the 802.11 g standard of EVM at-25 dB.With the adopted gain control strategy the output power changes from-14.3 to-3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process.A power detector indicates the output power and delivers a voltage to the baseband to control the output power.

  4. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  5. Development of a front end controller/heap manager for PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Allen, M.D.; Musrock, M.S.; Walker, J.W.; Britton, C.L. Jr.; Wintenberg, A.L.; Young, G.R.

    1996-12-31

    A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

  6. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  7. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  8. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  9. FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

    1989-05-01

    The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.

  10. Software-defined radio with flexible RF front end for satellite maritime radio applications

    Science.gov (United States)

    Budroweit, Jan

    2016-09-01

    This paper presents the concept of a software-defined radio with a flexible RF front end. The design and architecture of this system, as well as possible application examples will be explained. One specific scenario is the operation in maritime frequency bands. A well-known service is the Automatic Identification System (AIS), which has been captured by the DLR mission AISat, and will be chosen as a maritime application example. The results of an embedded solution for AIS on the SDR platform are presented in this paper. Since there is an increasing request for more performance on maritime radio bands, services like AIS will be enhanced by the International Association of Marine Aids to Navigation and Lighthouse Authorities (IALA). The new VHF Data Exchange Service (VDES) shall implement a dedicated satellite link. This paper describes that the SDR with a flexible RF front end can be used as a technology demonstration platform for this upcoming data exchange service.

  11. Improvement of EEG Signal Acquisition: An Electrical Aspect for State of the Art of Front End

    Directory of Open Access Journals (Sweden)

    Ali Bulent Usakli

    2010-01-01

    Full Text Available The aim of this study is to present some practical state-of-the-art considerations in acquiring satisfactory signals for electroencephalographic signal acquisition. These considerations are important for users and system designers. Especially choosing correct electrode and design strategy of the initial electronic circuitry front end plays an important role in improving the system's measurement performance. Considering the pitfalls in the design of biopotential measurement system and recording session conditions creates better accuracy. In electroencephalogram (EEG recording electrodes, system electronics including filtering, amplifying, signal conversion, data storing, and environmental conditions affect the recording performance. In this paper, EEG electrode principles and main points of electronic noise reduction methods in EEG signal acquisition front end are discussed, and some suggestions for improving signal acquisition are presented.

  12. Fuzzy Decision Support for Tools Selection in the Core Front End Activities of New Product Development

    DEFF Research Database (Denmark)

    Achiche, S.; Appio, F.P.; McAloone, Tim C.

    2013-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition......, an economic evaluation of the cost of tool usage is critical, and there is furthermore a need to characterize them in terms of their influence on the FE. This paper focuses on decision support for managers/ designers in their process of assessing the cost of choosing/using tools in the core front end (CFE......) activities identified by Koen, namely Opportunity Identification and Opportunity Analysis. This is achieved by first analyzing the influencing factors (firm context, industry context, macroenvironment) along with data collection from managers followed by the automatic construction of fuzzy decision support...

  13. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  14. Compensation of impedance meters when using an external front-end amplifier

    OpenAIRE

    Torrents Dolz, Josep M.; Pallàs Areny, Ramon

    2002-01-01

    Four-terminal impedance meters based on pseudo-bridges yield unexpected uncertainties when using high-contact-impedance electrodes. Adding a front-end amplifier to the impedance meter and rearranging the connection of the meter terminals overcome the contact impedance problem. However, because the compensation provisions in the instrument are meant to compensate only impedance residuals of test fixtures, by either an open/short or an open/short/load correction procedure, the external fr...

  15. A front-end automation tool supporting design, verification and reuse of SOC

    Institute of Scientific and Technical Information of China (English)

    严晓浪; 余龙理; 王界兵

    2004-01-01

    This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

  16. Trends in the design of front-end systems for room temperature solid state detectors

    OpenAIRE

    Manfredi, Pier F.; Re, Valerio

    2003-01-01

    The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor...

  17. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  18. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    CERN Document Server

    Simi, G; Batignani, G; Bettarini, S; Bondioli, M; Boscardin, M; Bosisio, L; Dalla Betta, Gian Franco; Dittongo, S; Forti, F; Giorgi, M; Gregori, P; Manghisoni, M; Morganti, M; Ratti, L; Re, V; Rizzo, G; Speziali, V; Zorzi, N

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures.

  19. FBI Fingerprint Image Capture System High-Speed-Front-End throughput modeling

    Energy Technology Data Exchange (ETDEWEB)

    Rathke, P.M.

    1993-09-01

    The Federal Bureau of Investigation (FBI) has undertaken a major modernization effort called the Integrated Automated Fingerprint Identification System (IAFISS). This system will provide centralized identification services using automated fingerprint, subject descriptor, mugshot, and document processing. A high-speed Fingerprint Image Capture System (FICS) is under development as part of the IAFIS program. The FICS will capture digital and microfilm images of FBI fingerprint cards for input into a central database. One FICS design supports two front-end scanning subsystems, known as the High-Speed-Front-End (HSFE) and Low-Speed-Front-End, to supply image data to a common data processing subsystem. The production rate of the HSFE is critical to meeting the FBI`s fingerprint card processing schedule. A model of the HSFE has been developed to help identify the issues driving the production rate, assist in the development of component specifications, and guide the evolution of an operations plan. A description of the model development is given, the assumptions are presented, and some HSFE throughput analysis is performed.

  20. Front-end electronics for accurate energy measurement of double beta decays

    Energy Technology Data Exchange (ETDEWEB)

    Gil, A., E-mail: alejandro.gil@ific.uv.es [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Diaz, J.; Gomez-Cadenas, J.J. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Herrero, V. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Rodriguez, J.; Serra, L. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain); Toledo, J.; Esteve, R.; Monzo, J.M. [Instituto de Instrumentacion para Imagen Molecular (I3M). Centro mixto CSIC, Universitat Politecnica de Valencia, CIEMAT, Valencia (Spain); Monrabal, F.; Yahlali, N. [Instituto de Fisica Corpuscular (CSIC-UV), 46071 Valencia (Spain)

    2012-12-11

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-{beta} decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  1. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  2. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  3. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  4. Implementing method of optimum front-end conditioner based on Butterworth filter

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The front-end conditioner is an essential part of digital systems of nuclear spectrometer, which functions in two ways: (1) prevents saturation of the subsequent ADC; (2) limits the bandwidth of frequency to realize anti-aliasing. To realize the above-mentioned functions, an optimum front-end conditioner for a resistive feedback charge-sensitive preamplifier is designed. In the conditioner, the pole-zero compensation (P/Z compensation) technique was used to effectively filter signals from the preamplifier. The Butterworth filter was improved after the pole-zero position was optimally set up to shape the wave of output, which tallied with the whole system. The front-end conditioner can resolve the aberration of waveform of nuclear signals in a regular Butterworth filter. Compared with the traditional triple-pole filtering circuitry, the circuitry of this conditioner is more compact and flexible.Moreover, its output waveform is more symmetrical and the signal-to-noise ratio (SNR) is higher. The improvement in the resolution of spectrometer is also significant.

  5. Web-based DAQ systems: connecting the user and electronics front-ends

    Science.gov (United States)

    Lenzi, Thomas

    2016-12-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  6. Étude des détecteurs planaires pixels durcis aux radiations pour la mise à jour du détecteur de vertex d'ATLAS

    CERN Document Server

    Benoit, Mathieu

    In this work, is presented a study, using TCAD simulation, of the possible methods of designing of a planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure,a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor's process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain ...

  7. Ultra-light and stable composite structure to support and cool the ATLAS pixel detector barrel electronics modules

    CERN Document Server

    Olcese, M; Castiglioni, G; Cereseto, R; Cuneo, S; Dameri, M; Gemme, C; Glitza, K W; Lenzen, G; Mora, F; Netchaeva, P; Ockenfels, W; Piano, E; Pizzorno, C; Puppo, R; Rebora, A; Rossi, L; Thadome, J; Vernocchi, F; Vigeolas, E; Vinci, A

    2004-01-01

    The design of an ultra light structure, the so-called "stave", to support and cool the sensitive elements of the Barrel Pixel detector, the innermost part of the ATLAS detector to be installed on the new Large Hadron Collider at CERN (Geneva), is presented. Very high- dimensional stability, minimization of the material and ability of operating 10 years in a high radiation environment are the key design requirements. The proposed solution consists of a combination of different carbon-based materials (impregnated carbon-carbon, ultra high modulus carbon fibre composites) coupled to a thin aluminum tube to form a very light support with an integrated cooling channel. Our design has proven to successfully fulfil the requirements. The extensive prototyping and testing program to fully qualify the design and release the production are discussed.

  8. Diamond Pixel Detectors and 3D Diamond Devices

    Science.gov (United States)

    Venturi, N.

    2016-12-01

    Results from detectors of poly-crystalline chemical vapour deposited (pCVD) diamond are presented. These include the first analysis of data of the ATLAS Diamond Beam Monitor (DBM). The DBM module consists of pCVD diamond sensors instrumented with pixellated FE-I4 front-end electronics. Six diamond telescopes, each with three modules, are placed symmetrically around the ATLAS interaction point. The DBM tracking capabilities allow it to discriminate between particles coming from the interaction point and background particles passing through the ATLAS detector. Also, analysis of test beam data of pCVD DBM modules are presented. A new low threshold tuning algorithm based on noise occupancy was developed which increases the DBM module signal to noise ratio significantly. Finally first results from prototypes of a novel detector using pCVD diamond and resistive electrodes in the bulk, forming a 3D diamond device, are discussed. 3D devices based on pCVD diamond were successfully tested with test beams at CERN. The measured charge is compared to that of a strip detector mounted on the same pCVD diamond showing that the 3D device collects significantly more charge than the planar device.

  9. The Phase-II ATLAS Pixel Tracker Upgrade: Layout and Mechanics

    CERN Document Server

    Sharma, Abhishek; The ATLAS collaboration

    2016-01-01

    In early 2017 a new layout will be decided for the ATLAS experiment as it undergoes an upgrade of its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The various layouts are described and a description of the supporting structures are presented, along with results from testing of prototypes.

  10. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    CERN Document Server

    Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P; 10.1088/1748-0221/5/12/C12025

    2010-01-01

    The presented R&D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut für Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 1016neqcm−2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the ...

  11. Qualification measurements of the voltage supply system as well as conceptionation of a state machine for the detector control of the ATLAS pixel detector; Qualifizierungsmessungen des Spannungsversorgungssystems sowie Konzeptionierung einer Zustandsmaschine fuer die Detektorkontrolle des ATLAS-Pixeldetektors

    Energy Technology Data Exchange (ETDEWEB)

    Schultes, Joachim

    2007-02-15

    The supply system and the control system of the ATLAS pixel detector represent important building blocks of the pixel detector. Corresponding studies of the supply system, which were performed within a comprehensive test system, the so-called system test, with nearly all final components and the effects on the pixel detector are object of this thesis. A further point of this thesis is the coordination and further development of the detector-control-system software under regardment of the different partial systems. A main topic represents thereby the conceptionation of the required state machine as interface for the users and the connection to the data acquisition system.

  12. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  13. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland)

    2015-07-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  14. A front-end ASIC design for non-uniformity correction

    Science.gov (United States)

    Shen, X.; Ding, R. J.; Lin, J. M.; Liu, F.

    2008-12-01

    A front-end design of an ASIC that implements calibration and correction for IRFPA non-uniformity is presented. An algorithm suitable for ASIC implementation is introduced, and one kind of architecture that implements this algorithm has been designed. We map the architecture to TSMC 0.25um process. After evaluating the chip area and operation speed, we confirm that this architect will also be effective when the FPA scale in enlarged to 1Kby1K. Finally the flow of circuit implementation and method of verification are introduced briefly.

  15. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

    DEFF Research Database (Denmark)

    di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere;

    2016-01-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point......). The designs that minimally satisfy the specifications are based on an 8-b 30-MSPS Nyquist converter and a single-bit third-order 240-MSPS modulator, with an SNR for the LNA in both cases equal to 64 dB. The mean lateral FWHM and CR are 2.4% and 7.1% lower for the architecture compared with the Nyquistrate one...

  16. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions.

  17. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  18. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  19. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  20. Investigation of characteristics and radiation hardness of the Beetle 1.0 front-end chip

    CERN Document Server

    Van Bakel, N; Jans, E; Klous, S; Verkooijen, H

    2001-01-01

    Noise characteristics of the Beetle 1.0 front-end chip have been investigated as a function of input capacitance. Values for the equivalent noise charge and ballastic deficit have been extracted. Amplification and pulse shape have been studied by varying the bias settings over a wide range. Results are compared with simulations that include realistic impedances at the input and output. The chip has been subjected to 10 Mrad of radiation. Subsequently, its behaviour is measured again and compared to that preceeding the irradiation. Observed radiation damage effects are discussed.

  1. Effect of vehicle front end profiles leading to pedestrian secondary head impact to ground.

    Science.gov (United States)

    Gupta, Vishal; Yang, King H

    2013-11-01

    Most studies of pedestrian injuries focus on reducing traumatic injuries due to the primary impact between the vehicle and the pedestrian. However, based on the Pedestrian Crash Data Study (PCDS), some researchers concluded that one of the leading causes of head injury for pedestrian crashes can be attributed to the secondary impact, defined as the impact of the pedestrian with the ground after the primary impact of the pedestrian with the vehicle. The purpose of this study is to understand if different vehicle front-end profiles can affect the risk of pedestrian secondary head impact with the ground and thus help in reducing the risk of head injury during secondary head impact with ground. Pedestrian responses were studied using several front-end profiles based off a mid-size vehicle and a SUV that have been validated previously along with several MADYMO pedestrian models. Mesh morphing is used to explore changes to the bumper height, bonnet leading-edge height, and bonnet rear reference-line height. Simulations leading up to pedestrian secondary impact with ground are conducted at impact speeds of 40 and 30 km/h. In addition, three pedestrian sizes (50th, 5th and 6yr old child) are used to enable us to search for a front-end profile that performs well for multiple sizes of pedestrians, not just one particular size. In most of the simulations, secondary ground impact with pedestrian head/neck/shoulder region occurred. However, there were some front-end profiles that promoted secondary ground impact with pedestrian lower extremities, thus avoiding pedestrian secondary head impact with ground. Previous pedestrian safety research work has suggested the use of active safety methods, such as 'pop up hood', to reduce pedestrian head injury during primary impact. Accordingly, we also conducted simulations using a model with the hood raised to capture the effect of a pop-up hood. These simulations indicated that even though pop-up hood helped reducing the head injury

  2. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Science.gov (United States)

    Lombigit, L.; Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-01

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  3. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  4. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    OpenAIRE

    al., H. Albrecht et

    2004-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns...

  5. Low-Power Fully Integrated CMOS DTV Tuner Front-End for ATSC Terrestrial Broadcasting

    Directory of Open Access Journals (Sweden)

    Jianhong Xiao

    2007-01-01

    Full Text Available A low-cost low-power DTV tuner for current digital television application is described. In order to increase integration level and reduce power consumption for off-air DTV tuner application, an SAW-filterless tuner front-end architecture is adopted. As a part of the concept, key building blocks for this architecture are implemented on a main stream 0.35 μm CMOS technology. Experimental measurements for the prototype chip validate the system architecture; the prototype consumes 300 mw and achieves 45 dB of image rejection ratio within the entire 750 MHz frequency band.

  6. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter;

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N....... A non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study...

  7. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    This paper addresses the design, implementation and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design comprises commercial-of-the-shelf modules and newly purpose-built components at a centre frequency of 435 MHz with 20......% relative bandwidth. The transmitter uses two amplifiers combined in parallel to generate more than >128 W peak power, with system >60% PAE and 47 dB in-band to out-of-band signal ratio. The four channel receiver features digitally controlled variable gain to achieve more than 100 dB dynamic range, 2.4 d...

  8. Simulation of wind power with front-end converter into interconnected grid system

    Directory of Open Access Journals (Sweden)

    Sharad W. Mohod

    2009-09-01

    Full Text Available In the growing electricity supply industry and open access market for electricity worldwide, renewable sources are getting added into the grid system. This affects the grid power quality. To assess the impact on grid due to wind energy integration, the knowledge of electrical characteristic of wind turbine and associated control equipments are required. The paper presents a simulation set-up for wind turbine in MATLAB / SIMULINK, with front end converter and interconnected system. The presented control scheme provides the wind power flow to the grid through a converter. The injected power in the system at the point of common coupling is ensured within the power quality norms.

  9. Noise limits in a front-end system based on time-over-threshold signal processing

    CERN Document Server

    Manfredi, P F; Mandelli, E; Perazzo, A; Re, V

    2000-01-01

    An analog signal processor based on the Time-over-Threshold (ToT) range compression is employed in the front-end section of the readout chip of the microstrip vertex detector for the BaBar experiment. The paper, after describing the circuit solutions that have been adopted to optimize the ToT operation, focuses on the noise aspects of the ToT processor. Comparisons are made between the signal-to-noise ratio in the linear processor preceding the ToT circuit and that obtained at the output of the entire analog channel including the ToT function.

  10. Testing of the front-end hybrid circuits for the CMS Tracker upgrade

    Science.gov (United States)

    Gadek, T.; Blanchot, G.; Honma, A.; Kovacs, M.; Raymond, M.; Rose, P.

    2017-01-01

    The upgrade of the CMS Tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high-density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  11. HTS filter and front-end subsystem for GSM1800 wireless base station

    Institute of Scientific and Technical Information of China (English)

    2002-01-01

    The first HTS front-end subsystem for wireless base station in China was developed. This demonstration system, which aims at the application in GSM1800 mobile communication base station, consists of a single RF path, i.e. one filter and one LNA, integrated with the pulse tube cooler. The subsystem works at a pass band of 1710-1785 MHz with a gain of 18 dB and at a temperature of 70 K. The accomplishment of such a demonstration subsystem can boost the development of HTS commercial subsystem.

  12. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  13. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  14. THz semiconductor-based front-end receiver technology for space applications

    Science.gov (United States)

    Mehdi, Imran; Siegel, Peter

    2004-01-01

    Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

  15. A wide dynamics neutron monitor with BF3 and logarithmic amplifier based front-end electronics

    OpenAIRE

    2010-01-01

    In this paper a wide dynamics neutron monitor based on BF3 neutron detector is described. The detector is used in current mode, and a front-end electronics based on a logarithmic amplifier is used in order to have a measurement capability ranging over many decades. The system has been calibrated at Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamics ranging ov...

  16. SYSTEMATIC METHOD TO GENERATE NEW IDEAS IN FUZZY FRONT END USING TRIZ

    Institute of Scientific and Technical Information of China (English)

    TAN Runhua; MA Lihui; YANG Bojun; SUN Jianguang

    2008-01-01

    The obstacle for idea generation in fuzzy front end (FFE) is difficult to apply knowledge in different fields for designers. Theory of inventive problem solving TRIZ and computer-aided innovation systems (CAIs) which are TRIZ-base software systems with a knowledge base provide a framework for knowledge application in different fields. The major methods in TRIZ are selected, which have four types. The problems to be solved for each method are summarized and mapping from the problems to the methods is given. Systematic method with eight paths to integrate the methods and problems is formed. A case study shows the idea generation in FFE using the integrated method step by step.

  17. Compact Agile Antenna Concept Utilizing Reconfigurable Front End for Wireless Communications

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Jagielski, Ole; Svendsen, Simon

    2014-01-01

    that separates the Tx and Rx chain throughout the front end (FE). The complexity of the FE is reduced dramatically by replacing the duplex filters with tunable filters and closely integrating the tunable antennas in the FE, providing filtering which can be used to lower requirements for the tunable filters....... For this purpose, very small narrow-band antennas are designed, which can cover 1710–2170 MHz by using tunable capacitors. Simulations and measurements of the antenna concept are carried out in the proposed FE architecture, serving as a proof of concept....

  18. Impact of Spectral Filter on Phase Modulation Pulse in Fiber Front End System

    Institute of Scientific and Technical Information of China (English)

    LI Jing; JING Feng; WANG Jian-Jun; XU Dang-Peng; LIN Hong-Huan; GENG Yuan-Chao; LI Ming-Zhong; DENG Ying; ZHU Na; ZHANG Rui

    2011-01-01

    The transmission characteristics of phase modulation pulse transmitted through the filter in the power amplifier are investigated theoretically and experimentally. The narrow bandpass filter can induce large temporal modula-tion depth for the phase modulation pulse and induce double amplitude modulation(AM)if the frequency shift is lower than half bandwidth of the signal spectrum. We should choose a wider bandwidth filter to minimize the impact of the filter on the output pulse and suppress the amplified spontaneous emission(ASE) for the power fiber amplifier. These results are of benefit to the design of the fiber front end system.

  19. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  20. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2016-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  1. Development of a Detector Control System for the ATLAS Pixel detector in the HL-LHC

    Science.gov (United States)

    Lehmann, N.; Karagounis, M.; Kersten, S.; Zeitnitz, C.

    2016-11-01

    The upgrade of the LHC to the HL-LHC requires a new ITk detector. The innermost part of this new tracker is a pixel detector. The University of Wuppertal is developing a new DCS to monitor and control this new pixel detector. The current concept envisions three parallel paths of the DCS. The first path, called security path, is hardwired and provides an interlock system to guarantee the safety of the detector and human beings. The second path is a control path. This path is used to supervise the entire detector. The control path has its own communication lines independent from the regular data readout for reliable operation. The third path is for diagnostics and provides information on demand. It is merged with the regular data readout and provides the highest granularity and most detailed information. To reduce the material budget, a serial power scheme is the baseline for the pixel modules. A new ASIC used in the control path is in development at Wuppertal for this serial power chain. A prototype exists already and a proof of principle was demonstrated. Development and research is ongoing to guarantee the correct operation of the new ASIC in the harsh environment of the HL-LHC. The concept for the new DCS will be presented in this paper. A focus will be made on the development of the DCS chip, used for monitoring and control of pixel modules in a serial power chain.

  2. Fluorocarbon evaporative cooling developments for the ATLAS pixel and semiconductor tracking detectors

    CERN Document Server

    Anderssen, E; Berry, S; Bonneau, P; Bosteels, Michel; Bouvier, P; Cragg, D; English, R; Godlewski, J; Górski, B; Grohmann, S; Hallewell, G D; Hayler, T; Ilie, S; Jones, T; Kadlec, J; Lindsay, S; Miller, W; Niinikoski, T O; Olcese, M; Olszowska, J; Payne, B; Pilling, A; Perrin, E; Sandaker, H; Seytre, J F; Thadome, J; Vacek, V

    1999-01-01

    Heat transfer coefficients 2-5.103 Wm-2K-1 have been measured in a 3.6 mm I.D. heated tube dissipating 100 Watts - close to the full equivalent power (~110 W) of a barrel SCT detector "stave" - over a range of power dissipations and mass flows in the above fluids. Aspects of full-scale evaporative cooling circulator design for the ATLAS experiment are discussed, together with plans for future development.

  3. Unified analytical expressions for calculating resonant frequencies, transimpedances, and equivalent input noise current densities of tuned receiver front ends

    OpenAIRE

    1992-01-01

    Unified analytical expressions have been derived for calculating the resonant frequencies, transimpedance and equivalent input noise current densities of the four most widely used tuned optical receiver front ends built with FETs and p-i-n diodes. A more accurate FET model has been used to improve the accuracy of the analysis. The Miller capacitance has been taken into account, and its impact on the performances of the tuned front ends has been demonstrated. The accuracy of the expressions ha...

  4. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Energy Technology Data Exchange (ETDEWEB)

    Rivetti, Angelo

    2014-11-21

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  5. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  6. An instrumentation amplifier as a front-end for a four-electrode bioimpedance measurement.

    Science.gov (United States)

    Zagar, T; Krizaj, D

    2007-08-01

    The performance of a monolithic instrumentation amplifier used as an interface for a four-electrode bioimpedance measurement is examined with a commercially available impedance meter based on an auto-balancing bridge. The errors due to particularities in the input stage of the impedance meter, when used without a front-end, were several orders of magnitude higher than the measured quantity. The analysis was performed on an electrical circuit model of the skin and electrodes over a frequency range of 20 Hz to 1 MHz. The achieved accuracy with balanced electrode impedances for the frequencies up to 100 kHz can be below 0.2% for impedance magnitude and 0.1 degrees for impedance phase, which is within the specified basic accuracy range of the LCR-meter used for the measurements. At frequencies above 100 kHz the errors are increasing and are higher than the LCR-meter's basic accuracy. This study indicates that use of an instrumentation amplifier as a front-end with the particular LCR-meter can significantly improve the measurement accuracy of the four-electrode bioimpedance measurement at low frequencies.

  7. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    Science.gov (United States)

    Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

    2008-08-01

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector.

  8. An ultra low-power front-end IC for wearable health monitoring system.

    Science.gov (United States)

    Yu-Pin Hsu; Zemin Liu; Hella, Mona M

    2016-08-01

    This paper presents a low-power front-end IC for wearable health monitoring systems. The IC, designed in a standard 0.13μm CMOS technology, fully integrates a low-noise analog front-end (AFE) to process the weak bio-signals, followed by an analog-to-digital converter (ADC) to digitize the extracted signals. An AC-coupled driving buffer, that interfaces between the AFE and the ADC is introduced to scale down the power supply of the ADC. The power consumption decreases by 50% compared to the case without power supply scaling. The AFE passes signals from 0.5Hz to 280Hz and from 0.7Hz to 160Hz with a simulated input referred noise of 1.6μVrms and achieves a maximum gain of 35dB/41dB respectively, with a noise-efficiency factor (NEF) of the AFE is 1. The 8-bit ADC achieves a simulated 7.96-bit resolution at 10KS/s sampling rate under 0.5V supply voltage. The overall system consumes only 0.86μW at dual supply voltages of 1V (AFE) and 0.5 V (ADC).

  9. Implementation of re-configurable Digital front end module of MIMO-OFDM module using NCO

    Directory of Open Access Journals (Sweden)

    Veena M.B.

    2011-09-01

    Full Text Available This paper focuses on FPGA implementation of Reconfigurable Digital Front end MIMO-OFDM module. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. Unlike the conventional OFDM based systems, the Numerically Controlled Oscillators (NCO is used for mapping modulated data onto the sub carriers. The use of NCO in the MIMO-OFDM system reduces the resource utilization of the design on FPGA along with reduced power consumption. The major modules that were designed, which constitute the digital front end module, are Quadrature Phase Shift Keying (QPSK modulator/demodulator, 16-Quadrature Amplitude Modulation (QAM modulator/demodulator and NCOs. Each of the modules was tested for their functionality by developing corresponding test benches. In order to achieve real time reconfigurability of the proposed architecture, the proposed approach is realized on FPGAs optimizing area, power and speed. Reconfigurability of the proposed approach is dependent upon user requirement. Hence the proposed approach can support future generation communication technologies that are based on MIMO-OFDM.

  10. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    Science.gov (United States)

    Alexanian, H.; Appelquist, G.; Bailly, P.; Benetta, R.; Berglund, S.; Bezamat, J.; Blouzon, F.; Bohm, C.; Breveglieri, L.; Brigati, S.; Cattaneo, P. W.; Dadda, L.; David, J.; Engström, M.; Genat, J. F.; Givoletti, M.; Goggi, V. G.; Gong, S.; Grieco, G. M.; Hansen, M.; Hentzell, H.; Holmberg, T.; Höglund, I.; Inkinen, S. J.; Kerek, A.; Landi, C.; Ledortz, O.; Lippi, M.; Lofstedt, B.; Lund-Jensen, B.; Maloberti, F.; Mutz, S.; Nayman, P.; Piuri, V.; Polesello, G.; Sami, M.; Savoy-Navarro, A.; Schwemling, P.; Stefanelli, R.; Sundblad, R.; Svensson, C.; Torelli, G.; Vanuxem, J. P.; Yamdagni, N.; Yuan, J.; Ödmark, A.; Fermi Collaboration

    1995-02-01

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed {A}/{D} converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design.

  11. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  12. Towards a smart Holter system with high performance analogue front-end and enhanced digital processing.

    Science.gov (United States)

    Du, Leilei; Yan, Yan; Wu, Wenxian; Mei, Qiujun; Luo, Yu; Li, Yang; Wang, Lei

    2013-01-01

    Multiple-lead dynamic ECG recorders (Holter) play an important role in the earlier detection of various cardiovascular diseases. In this paper, we present the first several steps towards a 12-lead Holter system with high-performance AFE (Analogue Front-End) and enhanced digital processing. The system incorporates an analogue front-end chip (ADS1298 from TI), which has not yet been widely used in most commercial Holter products. A highly-efficient data management module was designated to handle the data exchange between the ADS1298 and the microprocessor (STM32L151 from ST electronics). Furthermore, the system employs a Field Programmable Gate Array (Spartan-3E from Xilinx) module, on which a dedicated real-time 227-step FIR filter was executed to improve the overall filtering performance, since the ADS1298 has no high-pass filtering capability and only allows limited low-pass filtering. The Spartan-3E FPGA is also capable of offering further on-board computational ability for a smarter Holter. The results indicate that all functional blocks work as intended. In the future, we will conduct clinical trials and compare our system with other state-of-the-arts.

  13. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  14. Characterization of RF front-ends by long-tail pulse response

    Science.gov (United States)

    Mazzaro, Gregory J.; Ranney, Kenneth I.

    2010-04-01

    The recognition of unauthorized communications devices at the entry-point of a secure location is one way to guard against the compromise of sensitive information by wireless transmission. Such recognition may be achieved by backscatter x-ray and millimeter-wave imaging; however, implementation of these systems is expensive, and the ability to image the contours of the human body has raised privacy concerns. In this paper, we present a cheaper and less-invasive radio-frequency (RF) alternative for recognizing wireless communications devices. Characterization of the device-under-test (DUT) is accomplished using a stepped-frequency radar waveform. Single-frequency pulses excite resonance in the device's RF front-end. Microsecond periods of zero-signal are placed between each frequency transition to listen for the resonance. The stepped-frequency transmission is swept through known communications bands. Reception of a long-tail decay response between active pulses indicates the presence of a narrowband filter and implies the presence of a front-end circuit. The frequency of the received resonance identifies its communications band. In this work, cellular-band and handheld-radio filters are characterized.

  15. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  16. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  17. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  18. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  19. The next generation Front-End Controller for the Phase-I Upgrade of the CMS Hadron Calorimeters

    Science.gov (United States)

    Costanza, F.; Behrens, U.; Campbell, A.; Karakaya, T.; Martens, I.; Melzer-Pellmann, I. A.; Sahin, M. O.

    2017-03-01

    The next generation Front-End Controller (ngFEC) is the system responsible for slow and fast control within the Phase-I Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μTCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the front-end electronics through six GBT links. The latency of the fast control signals is fixed across power cycles. Even if the direct link to a front-end module is broken, a redundancy scheme ensures a successful communication using the link to the neighboring front-end module. Thanks to the ngFEC all front-end modules can be remotely programmed using the JTAG standard protocol. The CCM server software interfaces the ngFEC to the Detector Control System which constantly monitors voltages and temperatures on the front-end electronics. This document reviews the characteristics and the development status of the ngFEC.

  20. System Electronics for the ATLAS Upgraded Strip Detector

    CERN Document Server

    Affolder, T; The ATLAS collaboration; Clark, A; Dabrowskic, W; Dewitt, J; Diez Cornell, S; Dressdant, N; Fadeyev, V; Farthouat, P; Ferrere, D; Greenall, A; Grillo, A; Kaplon, J; Key-Charriere, M; La Marra, D; Lipeles, E; Lynn, D; Newcomer, M; Pereirab, F; Phillips, P; Spencer, E; Swientekc, K; Warren, M; Weidberg, A

    2013-01-01

    The basic concept of the front-end system of the Silicon Strip Detector in the Atlas Detector upgraded for the HL-LHC is being elaborated and proposed. The readout electronics of this new detector is based on front-end chips (ABC130), Hybrid Controller chips (HCC) and End of Stave Controller chips (EOSC). This document defines the basic functionality of the front-end system and of the different ASICs.

  1. Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Puellen, Lukas

    2015-02-10

    In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

  2. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-09-02

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  3. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  4. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement

  5. Opto-box: Optical modules and mini-crate for ATLAS pixel and IBL detectors

    Science.gov (United States)

    Bertsche, David

    2016-11-01

    The opto-box is a custom mini-crate for housing optical modules which process and transfer optoelectronic data. Many novel solutions were developed for the custom design and manufacturing. The system tightly integrates electrical, mechanical, and thermal functionality into a small package of size 35×10x8 cm3. Special attention was given to ensure proper shielding, grounding, cooling, high reliability, and environmental tolerance. The custom modules, which incorporate Application Specific Integrated Circuits, were developed through a cycle of rigorous testing and redesign. In total, fourteen opto-boxes have been installed and loaded with modules on the ATLAS detector. They are currently in operation as part of the LHC run 2 data read-out chain. This conference proceeding is in support of the poster presented at the International Conference on New Frontiers in Physics (ICNFP) 2015 [1].

  6. Opto-box: Optical modules and mini-crate for ATLAS pixel and IBL detectors

    Directory of Open Access Journals (Sweden)

    Bertsche David

    2016-01-01

    Full Text Available The opto-box is a custom mini-crate for housing optical modules which process and transfer optoelectronic data. Many novel solutions were developed for the custom design and manufacturing. The system tightly integrates electrical, mechanical, and thermal functionality into a small package of size 35×10x8 cm3. Special attention was given to ensure proper shielding, grounding, cooling, high reliability, and environmental tolerance. The custom modules, which incorporate Application Specific Integrated Circuits, were developed through a cycle of rigorous testing and redesign. In total, fourteen opto-boxes have been installed and loaded with modules on the ATLAS detector. They are currently in operation as part of the LHC run 2 data read-out chain. This conference proceeding is in support of the poster presented at the International Conference on New Frontiers in Physics (ICNFP 2015 [1].

  7. Harmonic Mitigated Front End Three Level Diode Clamped High Frequency Link Inverter by Using MCI Technique

    Directory of Open Access Journals (Sweden)

    Sreedhar Madichetty

    2014-02-01

    Full Text Available In this paper it proposes a high efficient soft-switching scheme based on zero-voltage-switching (ZVS and zero-current-switching(ZCS principle operated with a simple auxiliary circuit extended range for the front-end isolated DC-AC-DC-AC high power converter with an three phase three level diode clamped multi level inverter by using Minority Charge Carrier inspired optimization technique (MCI with Total Harmonic Distortion(THD,Switching losses, Selective harmonic elimination maintaining with its fundamental as an objective function. Input to the inverter is obtained by the photo voltaic cells and with battery bank. The switching scheme is optimized by MCI technique, analyzed and executed in Matlab and implemented with a digital signal processor (DSP .Experimental results with different loads have observed and shows its effectives, robustness of the applied technique.

  8. An analog front-end circuit for ISO/IEC 15693-compatible RFID transponder IC

    Institute of Scientific and Technical Information of China (English)

    LIU Dong-sheng; ZOU Xue-cheng; YANG Qiu-ping; XIONG Ting-wen

    2006-01-01

    The 13.56 MHz analog front-end circuit for ISO/IEC 15693-compatible radio frequency identification (RFID) transponder IC presented in this paper converts RF power to DC and extracts clock and data from the interrogator by 10% or 100% ASK modulation. The transponder sends data back to the interrogator by load modulation technology. The electrostatic discharge (ESD)protection circuits function to limit RF voltage to a safe level. An inductive coupling simulation modelling for 13.56 MHz RFID system is presented, with simulation results showing that the transponder operates over a wide range of electromagnetic field strength from Hmin (150 mA/m) to Hmax (5 A/m). The transponder IC is implemented in SMIC 0.35-μm three-metal two-poly mixed signal CMOS technology with embedded EEPROM.

  9. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  10. Developments for the upgrade of the CMS HCAL front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Baden, D [Univ. of Maryland, College Park, MD 20742 (United States); Frahm, E; Mans, J [Univ. of Minnesota, Minneapolis, MN 55455 (United States); Freeman, J; Grassi, T; Los, S; Shaw, T; Whitmore, J; Zimmerman, T [FERMILAB, Batavia, IL 60510 (United States); Tully, C, E-mail: tullio.grassi@cern.c [Princeton University, Princeton NJ 08544 (United States)

    2010-11-15

    We present a scheme to upgrade the CMS HCAL front-end electronics in 2015-16. The HCAL upgrade is required to handle a major luminosity increase of LHC which is expected for 2017. This paper focuses on the requirements for the new electronics and on the proposed solutions. The requirements include increased channel count, additional timing capabilities, and additional redundancy in a harsh environment which is constrained by the existing system. The proposed solutions span from chip level to system level. They include the development of a new ADC ASIC, the evaluation and use of circuits from other developments, evaluation of commercial FPGAs, better thermal design and improvements in the overall architecture.

  11. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  12. Multi-channel front-end board for SiPM readout

    Science.gov (United States)

    Auger, M.; Ereditato, A.; Goeldi, D.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Weber, M. S.

    2016-10-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias for the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The signal-to-noise ratio of 12 is attained for the first photo-electron peak. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  13. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Acqua, A.; Hansen, M.; Lofstedt, B.; Vanuxem, J.P. (CERN, Geneva (Switzerland)); Svensson, C.; Yuan, J. (Univ. of Linkoeping (Sweden). Dept. of Physics and Measurement Technology); Hentzell, H. (Univ. of Linkoeping (Sweden). Center for Industrial Microelectronics and Materials Technology); Alippi, C.; Breveglieri, L.; Dadda, L.; Piuri, V.; Salice, F.; Sami, M.; Stefanelli, R. (Sezione INFN, Pavia, Milano (Italy). Dept. di Ellettronica); Cattaneo, P.; Fumagalli, G.; Goggi, V.G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Fisica Nucleare); Brigati, S.; Gatti, U.; Maloberti, F.; Torelli, G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Electronica); Carlson, P.; Fuglesang, C.; Kerek, A. (Manne Siegbahn Inst. of Physics, Stockholm (Sweden)); Appelquist, G.; Berglund, S.; Bohm, C.; Yamdagni, N. (Univ. of Stockholm (Sweden)); Sundblad, R. (SiCon AB, Linkoeping (Sweden))

    1993-08-01

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.

  14. NOVEL ELECTRONIC TUNER USING VARACTORS FOR TUNABLE RF FRONT-ENDS

    Institute of Scientific and Technical Information of China (English)

    Li Liang; Liu Taijun; Ye Yan; Zhang Haili; Hui Ming; Li Jun; Wen Huafeng

    2013-01-01

    This paper presents a novel electronic tuner with high power handling capability utilizing varactors based on the asymmetric bilateral coupled microstrip transmission line.Through varying the bias voltage of the varactor at the Ultra High Frequency (UHF) band,the performance of the tuner is demonstrated according to simulated and measured results from several cases with the return loss (S11)below-20 dB and the insertion loss (S21) within ±0.5 dB.Compared with tuners using π and T network,electronic tuner of this paper shows superior frequency agility as well as wide impendence coverage.Advanced biasing structure has been developed to improve power handling for high power level applications.It is expected that the novel tuner would be part of intelligent Radio Frequency (RF)front-ends system and cognitive wireless system in the future.

  15. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  16. Conductive Cooling of SDD and SSD Front-End Chips for ALICE

    CERN Document Server

    Van den Brink, A; Daudo, F; Feofilov, G A; Godisov, O N; Giraudo, G; Igolkin, S N; Kuijer, P; Nooren, G J L; Swichev, A; Tosello, F

    2001-01-01

    We present analysis, technology developments and test results of the heat drain system of the SDD and SSD front-end electronics for the ALICE Inner Tracker System (ITS). Application of super thermoconductive carbon fibre thin plates provides a practical solution for the development of miniature motherboards for the FEE chips situated inside the sensitive ITS volume. Unidirectional carbon fibre motherboards of 160 -300 micron thickness ensure the mounting of the FEE chips and an efficient heat sink to the cooling arteries. Thermal conductivity up to 1.3 times better than copper is achieved while preserving a negligible multiple scattering contribution by the material (less than 0.15 percent of X/Xo).

  17. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  18. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  19. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  20. Ionization Readout Electronics for SuperCDMS SNOLAB Employing a HEMT Front-End

    Science.gov (United States)

    Partridge, R.

    2014-09-01

    The SuperCDMS SNOLAB experiment seeks to deploy 200 kg of cryogenic Ge detectors employing phonon and ionization readout to identify dark matter interactions. One of the design challenges for the experiment is to provide amplification of the high impedance ionization signal while minimizing power dissipation and noise. This paper describes the design and expected performance of the ionization readout being developed for an engineering model of the SuperCDMS SNOLAB Ge Tower System. The readout features the use of a low-noise HEMT front end transistor operating at 4 K to achieve a power dissipation of 100 W per channel, local grounding to minimize noise injection, and biasing circuitry that allows precise control of the HEMT operating point.

  1. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  2. A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

    Directory of Open Access Journals (Sweden)

    Eric Bharucha

    2014-11-01

    Full Text Available When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

  3. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  4. Thermal analysis of the first canted-undulator front-end components at SSRF

    Energy Technology Data Exchange (ETDEWEB)

    Xu, Zhongmin, E-mail: xuzhongmin@sinap.ac.cn; Feng, Xinkang; Wang, Naxiu; Wu, Guanyuan; Zhang, Min; Wang, Jie

    2015-02-21

    The performance of three kinds of masks: pre-mask, splitter mask and fixed mask-photon shutter, used for the first canted-undulator front end under heat loads at SSRF, is studied. Because these components are shared with two beamlines, the X-rays from both dual undulators and bending magnets can strike on them. Under these complicated conditions, they will absorb much more thermal power than when they operate in usual beamline. So thermal and stress analysis is indispensable for their mechanical design. The method of applying the non-uniform power density using Ansys is presented. During thermal stress analysis, the normal operation or the worst possible case is considered. The finite element analyses results, such as the maximum temperature of the body and the cooling wall and the maximum stress of these components, show the design of them is reasonable and safe.

  5. Design of fast signal processing readout front-end electronics implemented in CMOS 40 nm technology

    Science.gov (United States)

    Kleczek, Rafal

    2016-12-01

    The author presents considerations on the design of fast readout front-end electronics implemented in a CMOS 40 nm technology with an emphasis on the system dead time, noise performance and power dissipation. The designed processing channel consists of a charge sensitive amplifier with different feedback types (Krummenacher, resistive and constant current blocks), a threshold setting block, a discriminator and a counter with logic circuitry. The results of schematic and post-layout simulations with randomly generated input pulses in a time domain according to the Poisson distribution are presented and analyzed. Dead time below 20 ns is possible while keeping noise ENC ≈ 90 e- for a detector capacitance CDET = 160 fF.

  6. Front-end signal analysis of the transverse feedback system for SSRF

    Institute of Scientific and Technical Information of China (English)

    HAN Lifeng; YUAN Renxian; YU Luyang; YE Kairong

    2008-01-01

    Multi-bunch instabilities degrade beam quality through increased beam emittance, energy spread and even cause beam loss. A feedback system is used to suppress multi-bunch instabilities associated with resistive wall of the beam ducts, cavity-like structures, and trapped ions. A digital TFS (Transverse Feedback System) is in construction at the SSRF (Shanghai Synchrotron Radiation Facility), which is based on the latest generation of FPGA (Field Programmable Gate Array) processor. Before we get such FPGA digital board, investigation and simulation of the front-end were done in the first place. The signal flow was analyzed by SystemView. Construction and optimization of the entire system is our next goal.

  7. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  8. An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

    Institute of Scientific and Technical Information of China (English)

    WANG Min; ZHANG Xiao; ZHANG Chun-feng; CAO Mao-yong; LI Cai-fang; KONG Hui-min; QIN Feng-ju; YAN Yu-qin

    2007-01-01

    Abstract.Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here,a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end ( AFE), while a computer ( Pentium Ⅲ ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

  9. Ka-Band SiGe Receiver Front-End MMIC for Transponder Applications

    Science.gov (United States)

    Venkatesan, Jaikrishna; Mysoor, Narayan R.; Hashemi, Hassein; Aflatouni, Firooz

    2010-01-01

    A fully integrated, front-end Ka-band monolithic microwave integrated circuit (MMIC) was developed that houses an LNA (low noise amplifier) stage, a down-conversion stage, and output buffer amplifiers. The MMIC design employs a two-step quadrature down-conversion architecture, illustrated in the figure, which results in improved quality of the down-converted IF quadrature signals. This is due to the improved sensitivity of this architecture to amplitude and phase mismatches in the quadrature down-conversion process. Current sharing results in reduced power consumption, while 3D-coupled inductors reduce the chip area. Improved noise figure is expected over previous SiGe-based, frontend designs

  10. System considerations and RF front-end design for integration of satellite navigation and mobile standards

    Directory of Open Access Journals (Sweden)

    A. Miskiewicz

    2009-05-01

    Full Text Available The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF, and 1dB compression point (P1dB of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

  11. Understanding the Front-end of Large-scale Engineering Programs

    DEFF Research Database (Denmark)

    Lucae, Sebastian; Rebentisch, Eric; Oehmen, Josef

    2014-01-01

    from large cost overruns. Significant problems in program execution can be traced back to practices performed, or more frequently not performed, in the so-called “fuzzy front end” of the program. The lack of sufficient and effective efforts in the early stages of a program can result in unstable......, to propose a model for the front-end of large-scale engineering programs based on a review of existing, suitable models in literature and to better understand the complexity drivers that are impeding reliable planning and common planning mistakes made in large-scale engineering programs......., unclear and incomplete requirements, unclear roles and responsibilities within the program organization, insufficient planning, and unproductive tensions between program management and systems engineering. This study intends to clarify the importance of up-front planning to improve program performance...

  12. A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

    Science.gov (United States)

    Singh, Harjit; Loach, James; Poon, Alan

    2012-10-01

    One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.

  13. First commissioning experience with the LINAC4 3 MeV front-end at CERN

    CERN Document Server

    Lallement, J B; Bellodi, G; Comblin, J F; Dimov, V A; Granemann Souza, E; Lettry, J; Lombardi, A M; Midttun, O; Ovalle, E; Raich, U; Roncarolo, F; Rossi, C; Sanchez Alvarez, R; Scrivens, C A; Valerio-Lizarraga, C A; Vretenar, M; Yarmohammadi Satri, M

    2013-01-01

    Linac4 is a normal-conducting 160 MeV H- linear accelerator presently under construction at CERN. It will replace the present 50 MeV Linac2 as injector of the proton accelerator complex as part of a project to increase the LHC luminosity. The Linac front-end, composed of a 45 keV ion source, a Low Energy Beam Transport (LEBT), a 352.2 MHz Radio Frequency Quadrupole (RFQ) and a Medium Energy Beam Transport (MEBT) housing a beam chopper, have been commissioned at the 3 MeV test stand during the first half of 2013. The status of the installation and the results of the first commissioning stage are presented in this paper.

  14. Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

    DEFF Research Database (Denmark)

    Song, Zhanfeng; Tian, Yanjun; Chen, Wei;

    2016-01-01

    of optimal duty cycles is made by predicting the effect of duty cycles on instantaneous current variations and minimizing the cost function. Due to the adoption of behavior prediction, the proposed controller inherits the excellent dynamic characteristics of predictive controllers. Moreover, the application......This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...... of optimal duty cycles determined by cost function minimization automatically ensures optimum operations of converters within each sampling period. Improved transient and steady-state features of the proposed strategy are confirmed by experimental validations and in-depth comparisons with linear controllers...

  15. The front-end chip of the SuperB SVT detector

    Energy Technology Data Exchange (ETDEWEB)

    Giorgi, F., E-mail: giorgi@bo.infn.it [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Comotti, D. [Università degli Studi di Bergamo (Italy); Manghisoni, M.; Re, V.; Traversi, G. [Università degli Studi di Bergamo (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Pavia (Italy); Fabbri, L.; Gabrielli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Pellegrini, G.; Sbarra, C. [Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A. [Università degli Studi di Bologna (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Bologna (Italy); Berra, A.; Lietti, D.; Prest, M. [Università dell' Insubria, Como (Italy); Istituto Nazionale di Fisica Nucleare, Sezione di Milano Bicocca (Italy); Bevan, A. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); Wilson, F. [STFC Rutherford Appleton Laboratory, Harwell Oxford, Didcot OX11 0QX (United Kingdom); Beck, G.; Morris, J. [School of Physics and Astronomy Queen Mary, University of London, London E1 4NS (United Kingdom); and others

    2013-08-01

    The asymmetric e{sup +}e{sup −} collider SuperB is designed to deliver a high luminosity, greater than 10{sup 36}cm{sup −2}s{sup −1}, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  16. Onboard calibration circuit for the DAMPE BGO calorimeter front-end electronics

    Science.gov (United States)

    Zhang, De-Liang; Feng, Chang-Qing; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Shen, Zhong-Tao; Jiang, Di; Gao, Shan-Shan; Zhang, Yun-Long; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2016-05-01

    DAMPE (DArk Matter Particle Explorer) is a scientific satellite which is mainly aimed at indirectly searching for dark matter in space. One critical sub-detector of the DAMPE payload is the BGO (bismuth germanium oxide) calorimeter, which contains 1848 PMT (photomultiplier tube) dynodes and 16 FEE (Front-End Electronics) boards. VA160 and VATA160, two 32-channel low power ASICs (Application Specific Integrated Circuits), are adopted as the key components on the FEEs to perform charge measurement for the PMT signals. In order to monitor the parameter drift which may be caused by temperature variation, aging, or other environmental factors, an onboard calibration circuit is designed for the VA160 and VATA160 ASICs. It is mainly composed of a 12-bit DAC (Digital to Analog Converter), an operational amplifier and an analog switch. Test results showed that a dynamic range of 0-30 pC with a precision of 5 fC (Root Meam Square, RMS) was achieved, which covers the VA160’s input range. It can be used to compensate for the temperature drift and test the trigger function of the FEEs. The calibration circuit has been implemented for the front-end electronics of the BGO Calorimeter and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite was launched at the end of 2015 and the calibration circuit will operate periodically in space. Supported by Strategic Priority Research Program on Space Science of Chinese Academy of Sciences (XDA04040202-4), and National Basic Research Program (973 Program) of China (2010CB833002) and National Natural Science Foundation of China (11273070)

  17. Low-Cost Ratiometric Front-End for Industrial PRT Applications

    Science.gov (United States)

    Smorgon, D.; Fernicola, V. C.; Coslovi, L.

    2011-12-01

    Cost, size, speed, and measurement range limitations make the resistance bridge not always suitable for temperature measurements with platinum resistance thermometers (PRTs) in industrial applications. However, high-accuracy resistance thermometer systems are often needed in many industrial applications, where measurement performances comparable to resistance bridges are often needed at a lower cost and size. A tiny, portable, ratiometric front-end exploiting a 24-bit analog-to-digital converter (ADC) with Σ Δ modulator is described. It was designed to measure the resistance ratio between a 100 Ω industrial PRT (IPRT) and a reference resistor with repeatability to within a few parts in 106. Its small size makes it ideal for integration in the stem-handle assembly of a thermometric probe, enabling an early transmission of measurement data in digital form. The ADC-based system design, development, and performance testing are discussed. The system was investigated in the resistance ratio range from about 4 × 10-3 to 5 × 10-2. Furthermore, a comparison between the system performance and a commercial AC resistance bridge was carried out and the results reported in this paper. An accurate thermometer for industrial applications resulted from the above developments. The compactness of the devices enabled an implementation of the `smart sensor' concept in the measurement chain, where the front-end electronics was placed inside the IPRT handle together with an integrated memory to hold device identification, calibration coefficients, and the associated uncertainty. All data are transmitted to the readout module and are available to the user at a 5 Hz update rate for further analysis.

  18. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371978; Gößling, Claus; Pernegger, Heinz

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ...

  19. Pixel Hybridization Technologies for the HL-LHC

    Science.gov (United States)

    Alimonti, G.; Biasotti, M.; Ceriale, V.; Darbo, G.; Gariano, G.; Gaudiello, A.; Gemme, C.; Rossi, L.; Rovani, A.; Ruscino, E.

    2016-12-01

    During the 2024-2025 shut-down, the Large Hadron Collider (LHC) will be upgraded to reach an instantaneous luminosity up to 7×1034 cm-2s-1. This upgrade of the collider is called High-Luminosity LHC (HL-LHC). ATLAS and CMS detectors will be upgraded to meet the new challenges of HL-LHC: an average of 200 pile-up events in every bunch crossing and an integrated luminosity of 3000 fb-1 over ten years. In particular, the current trackers will be completely replaced. In HL-LHC the trackers should operate under high fluences (up to 1.4 × 1016 neq cm-2), with a correlated high radiation damage. The pixel detectors, the innermost part of the trackers, needed a completely new design in the readout electronics, sensors and interconnections. A new 65 nm front-end (FE) electronics is being developed by the RD53 collaboration compatible with smaller pixel sizes than the actual ones to cope with the high track densities. Consequently the bump density will increase up to 4 ·104 bumps/cm2. Preliminary results of two hybridization technologies study are presented in this paper. In particular, the on-going bump-bonding qualification program at Leonardo-Finmeccanica is discussed, together with alternative hybridization techniques, as the capacitive coupling for HV-CMOS detectors.

  20. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Science.gov (United States)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C. J.; Müller, W. F. J.

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.