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Sample records for atlas pixel front-end

  1. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  2. Total Ionising Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    Dette, Karola; The ATLAS collaboration

    2016-01-01

    The ATLAS Pixel Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of data taking, an increase of the LV current, produced by the FE-I4 chip, was observed. This increase was traced back to radiation damage in the chip. The dependence of the current from the Total Ionizing Dose (TID) and temperature has been tested with X-ray irradiations. This report presents the measurement results and gives a parameterisation of the leakage current and detector operation guidelines.

  3. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  4. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  5. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  6. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  7. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  8. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    International Nuclear Information System (INIS)

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented

  9. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    International Nuclear Information System (INIS)

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

  10. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2014-01-01

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing the consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I.

  11. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  12. Low noise, low power front end electronics for pixelized TFA sensors

    CERN Document Server

    Poltorak, K; Dabrowski, W; Despeisse, M; Jarron, P; Kaplon, J; Wyrschb, N

    2009-01-01

    Thin Film on ASIC (TFA) technology combines advantages of two commonly used pixel imaging detectors, namely, Monolithic Active Pixels (MAPs) and Hybrid Pixel detectors. Thanks to direct deposition of a hydrogenated amorphous silicon (a- Si:H) sensor lm on top of the readout ASIC, TFA shows the similarity to MAP imagers, allowing, however, more sophisticated front–end circuitry to extract the signals, like in case of Hybrid Pixel technology. In this paper we present preliminary experimental results of TFA structures, obtained with 10 μm thick hydrogenated amorphous silicon sensors, deposited directly on top of integrated circuit optimized for tracking applications at linear collider experiments. The signal charges delivered by such a-Si:H n-i-p diode are small; about 37 e-/μm for minimum ionizing particles, therefore a low noise, high gain and very low power of the front- end are of primary importance. The developed demonstrator chip, designed in 250 nm CMOS technology, comprises an array of 64 by 64 pi...

  13. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  14. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  15. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    CERN Document Server

    Solans, C; The ATLAS collaboration; Kim, H Y; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J; Usai, G; Valero, A

    2013-01-01

    After two years of operation of the LHC, the ATLAS Tile Calorimeter is undergoing the consolidation process of its front-end electronics. The first layer of certification of the repairs is performed in the experimental area with a portable test-bench which is capable of controlling and reading out all the inputs and outputs of one front-end module through dedicated cables. This test-bench has been redesigned to improve the quality assessment of the data until the end of Phase I. It is now possible to identify low occurrence errors due to its increased read-out bandwidth and perform more sophisticated quality checks due to its enhanced computing power. Improved results provide fast and reliable feedback to the user.

  16. Study of the performance of ATLAS prototype detectors using analogue LHC front-end electronics

    CERN Document Server

    Riedler, P; Kaplon, J; Weilhammer, Peter

    2002-01-01

    The silicon strip detectors in the ATLAS experiment at LHC will be exposed to very high hadron fluences. In order to study the radiation damage effects ATLAS prototype detectors and small test detectors were irradiated to a fluence of 3 * 10/sup 14/ 24 GeV protons/cm/sup 2/. After irradiation, the detectors were annealed at 25 degrees C to simulate the damage foreseen after 10 years of ATLAS operation. The detectors were then connected to the SCT32A analogue front-end chips and tested with a /sup 106/Ru source. The performance of the irradiated detectors was compared to non-irradiated detectors from the same batch. The charge collection efficiency is discussed taking into account the electronic response of the readout chip and the ballistic deficit. (10 refs).

  17. Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

    CERN Document Server

    Cooper, B; The ATLAS collaboration

    2012-01-01

    Around 2021 the Large Hadron Collider will be upgraded to provide instantaneous luminosities 5x10^34, leading to excessive rates from the ATLAS Level-1 trigger. We describe a double-buffer front-end architecture for the ATLAS tracker replacement which should enable tracking information to be used in the Level-1 decision. This will allow Level-1 rates to be controlled whilst preserving high efficiency for single lepton triggers at relatively low transverse momentum thresholds pT ~25 GeV, enabling ATLAS to remain sensitive to physics at the electroweak scale. In particular, a potential hardware solution for the communication between the upgraded silicon barrel strip detectors and the external processing within this architecture will be described, and discrete event simulations used to demonstrate that this fits within the tight latency constraints.

  18. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    International Nuclear Information System (INIS)

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  20. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  1. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  2. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  3. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, H Y; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    The stand-alone test-bench deployed in the past for the verification of the Tile Calorimeter (TileCal) front-end electronics is reaching the end of its life cycle. A new version of the test-bench has been designed and built with the aim of improving the portability and exploring new technologies for future versions of the TileCal read-out electronics. An FPGA based motherboard with an embedded hardware processor and a few dedicated daughter-boards are used to implement all the functionalities needed to interface with the front-end electronics (TTC, G-Link, CANbus) and to verify the functionalities using electronic signals and LED pulses. The new device is portable and performs well, allowing the validation in realistic conditions of the data transmission rate. We discuss the system implementation and all the tests required to gain full confidence in the operation of the front-end electronics of the TileCal in the ATLAS detector.

  4. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  5. Design of a Portable Test Facility for the ATLAS Tile Calorimeter Front-End Electronics Verification

    CERN Document Server

    Kim, HY; The ATLAS collaboration; Carrio, F; Moreno, P; Masike, T; Reed, R; Sandrock, C; Schettino, V; Shalyugin, A; Solans, C; Souza, J; Suter, R; Usai, G; Valero, A

    2013-01-01

    An FPGA-based motherboard with an embedded hardware processor is used to implement a portable test- bench for the full certification of Tile Calorimeter front-end electronics in the ATLAS experiment at CERN. This upgrade will also allow testing future versions of the TileCal read-out electronics as well. Because of its lightness the new facility is highly portable, allowing on-detector validation using sophisticated algorithms. The new system comprises a front-end GUI running on an external portable computer which controls the motherboard. It also includes several dedicated daughter-boards that exercise the different specialized functionalities of the system. Apart from being used to evaluate different technologies for the future upgrades, it will be used to certify the consolidation of the electronics by identifying low frequency failures. The results of the tests presented here show that new system is well suited for the 2013 ATLAS Long Shutdown. We discuss all requirements necessary to give full confidence...

  6. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  7. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  8. A CMOS analog front-end for silicon pixel detectors for γ imaging in medical application

    International Nuclear Information System (INIS)

    In recent works we presented the γ0, a chip expressely designed for γ imaging in medical application. The chip was designed to be the anode of an Integrated Silicon Pixel Array (ISPA) tube. This chip consists of a matrix of 1024 pixels each 135u by 135u, each pixel comprises a CSA, designed to handle signals of few thousand electrons, a shaper, a discriminator and a 10 bit event buffer. The chip addresses many issues that are essential for the realization of cheap and fast detectors. Particularly it integrates a DAC controlled biasing network and an energy discrimination system. In this work, we present the test system and the first test results for the γ0

  9. Evaluation of 65nm technology for CLIC pixel front-end

    CERN Document Server

    Valerio, P; Ballabriga, R; Campbell, M; Llopart, X

    2011-01-01

    The CLIC vertex detector design requires a high single point resolution (~ 3 μm) and a precise time stamp (≤ 10 ns). In order to achieve this spatial resolution, small pixels (in the order of 20 μm pitch) must be used, together with the measurement of the charge deposition of neighbouring channels. Designing such small pixels requires the use of a deep downscaled CMOS technology. This note describes the design and characterisation of suitable building blocks implemented in a commercial 65 nm process. The characterisation included an evaluation of the radiation hardness of the blocks.

  10. An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

    CERN Document Server

    Porter, Ryan

    This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

  11. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  12. Front-end intelligence for triggering and local track measurement in gaseous pixel detectors

    Science.gov (United States)

    Gromov, V.; Hessey, N.; Vermeulen, J.

    2012-11-01

    A number of applications in high-energy physics and medicine requires three-dimensional reconstruction of the particle trajectories: for example, high momentum particles in accelerator-based experiments can be identified on the basis of the properties of their tracks, while in proton computed tomography accurate knowledge of the incoming and outgoing beam trajectory is crucial in reconstructing the most probable path of the proton traversing the patient. In this work we investigate the potential of Gaseous Pixel (GridPix) detectors for fast and efficient recognition of tracks and determination of their properties. This includes selection, without external trigger, of tracks with desired angles, for example tracks with small tilt angles corresponding to high momentum particles in a magnetic field. Being able to select these fast and without external input is of interest for the future upgrades of the LHC detectors. In this paper we present a track selection algorithm, and its physical implementation in 130 nm CMOS technology with estimates of power consumption, data rates, latency, and chip area. The Timepix3 chip, currently being designed for a wide range of applications, will also be suitable for readout of GridPix detectors. Both arrival time information (accuracy 1.6 ns) and charge deposit information will be delivered for each hit together with the coordinates of the active pixel. A short overview is presented of its architecture, which allows continuous self-triggered readout of sparsely distributed data with a rate up to 20 × 106 hits cm-2sec-1. The addition of fast track pattern recognition logic to TimePix3 in a successor chip is currently being investigated.

  13. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with X-ray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  14. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  15. The ATLAS pixel detector

    OpenAIRE

    Cristinziani, M.

    2007-01-01

    After a ten years planning and construction phase, the ATLAS pixel detector is nearing its completion and is scheduled to be integrated into the ATLAS detector to take data with the first LHC collisions in 2007. An overview of the construction is presented with particular emphasis on some of the major and most recent problems encountered and solved.

  16. Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The Large Hadron Collider will be upgraded to provide instantaneous luminosity $L=5\\times10^{34}\\,\\mbox{cm}^{-2}\\mbox{s}^{-1}$, leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20$\\,\\mu$s in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of $p_{T}\\sim25\\,$GeV, which will be of great benefit to the future physics programme of ATLAS

  17. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  18. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 During the first year of the IBL operation in 2015 a significant increase of the LV current of the front-end chip and the detuning of its parameters (threshold and time-over- threshold) have been observed in relation to the received TID. In this talk , the TID effects in the FE-I4 chip are reported based on studies performed in the laboratory using X-ray and proton irradiation sources for various temperature and irradiation intensity conditions. Based on these results, an operation guideline of the IBL detector is presented.

  19. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  20. Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

    Science.gov (United States)

    Kureba, C. O.; Govender, M.; Hofsajer, I.; Ruan, X.; Sandrock, C.; Spoor, M.

    2015-10-01

    The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade.

  1. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    The calibration of the ATLAS Pixel detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied together to chips with different characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  2. Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

    CERN Document Server

    Cooper, B; The ATLAS collaboration

    2012-01-01

    The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC upgrade. We demonstrate that, in terms of the communication between the external processing and the tracking detector frontends, a hardware solution is possible that fits within the latency constraints of level-1.

  3. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr

    CERN Document Server

    Rescia, S; Newcomer, F M; Dressnandt, N

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper with a (RC)2 – CR response to replace the existing ATLAS Liquid Argon readout for use at SLHC. IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished by utilization of a single stage, low noise, wide dynamic range preamp connected to a dual range shaper. The low noise of the preamp (~.01nA / √Hz) is achieved by utilizing the process Silicon Germanium bipolar transistors. The relatively high voltage rating of the npn transistors is exploited to allow a gain of 650V/A. With this gain the equivalent input voltage noise requirement on the shaper to about 2.2nV/ √Hz. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. The shaper outputs are designed to be compatible with the 130nm CMOS ADC being develo...

  4. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter

    CERN Document Server

    Dressnandt, N; Rescia, S; Vernon, E

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at the Large Hadron Collider upgrade (sLHC). IBM’s 8WL 130nm SiGe process was chosen for it’s radiation tolerance, low noise bipolar NPN devices, wide voltage rand and potential use in other sLHC detector subsystems. Although the requirements for the final design can not be set at this time, the prototype was designed to accommodate a 16 bit dynamic range. This was accomplished by using a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of the Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier which eases the input voltage noise requirement on the shaper. Each shaper stage is designed as a cascaded differential operational amplifier doublet with a common...

  5. GEM400: A front-end chip based on capacitor-switch array for pixel-based GEM detector

    International Nuclear Information System (INIS)

    The upgrade of Beijing Synchrotron Radiation Facility (BSRF) needs two-dimensional position-sensitive detection equipment to improve the experimental performance. Gas Electron Multiplier (GEM) detector, in particular, pixel-based GEM detector has good application prospects in the domain of synchrotron radiation. The read-out of larger scale pixel-based GEM detector is difficult for the high density of the pixels (PAD for collecting electrons). In order to reduce the number of cables, this paper presents a read-out scheme for pixel-based GEM detector, which is based on System-in-Package technology and ASIC technology. We proposed a circuit structure based on capacitor switch array circuit, and design a chip GEM400, which is a 400 channels ASIC. The proposed circuit can achieve good stability and low power dissipation. The chip is implemented in a 0.35μm CMOS process. The basic functional circuitry in ths chip includes analog switch, analog buffer, voltage amplifier, bandgap and control logic block, and the layout of this chip takes 5mm × 5mm area. The simulation results show that the chip can allow the maximum amount of input charge 70pC on the condition of 100pF external integrator capacitor. Besides, the chip has good channel uniformity (INL is better than 0.1%) and lower power dissipation.

  6. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  7. ATLAS Pixel Detector Operational Experience

    CERN Document Server

    Di Girolamo, B; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.9% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  8. Pixel electronics for the ATLAS experiment

    CERN Document Server

    Fischer, P

    2001-01-01

    The ATLAS experiment at LHC will use 3 barrel layers and 2*5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mm*60.8 mm which include an n/sup +/ on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode...

  9. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  10. Overview of the ATLAS Insertable B-Layer Pixel Detector

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2011-01-01

    ATLAS currently develops a new pixel detector for the first upgrade of its tracking system: The ATLAS Insertable B-Layer Pixel detector (IBL). The new layer will be inserted between the inner most layer of the current pixel detector and a new beam pipe. The sensors are placed at a radius of 3.4cm. The expected high radiation levels and high hit occupancy require new developments for front-end chip and the sensor which can stand radiation levels beyond 5E15 neq/cm2. ATLAS has developed the new FEI4 and new silicon sensors to be used as pixel modules. Furthermore a new lightweight support and cooling structure was developed, which minimizes the overall radiation and allows detector cooling with CO2 at -40C coolant temperature. Currently the overall integration and installation procedure is being developed and test ready for installation in ATLAS in 2013. The presentation summarizes the current state of development of IBL modules, first preliminary test results of the new chip with new sensors, the construction ...

  11. Calibration analysis software for the ATLAS Pixel Detector

    Science.gov (United States)

    Stramaglia, Maria Elena

    2016-07-01

    The calibration of the ATLAS Pixel Detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel Detector scans and analyses is called calibration console. The introduction of a new layer, equipped with new FE-I4 chips, required an update of the console architecture. It now handles scans and scan analyses applied together to chips with different characteristics. An overview of the newly developed calibration analysis software will be presented, together with some preliminary results.

  12. Operational Experience with the ATLAS Pixel Detector at LHC

    CERN Document Server

    Keil, M

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus crucial for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via front-end chips bump-bonded to 1744 n-on-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, detector performance and measurements of radiation damage. The detector performance is excellent: more than 95% of the pixels are operational, noise occupancy and hit efficiency exceed the des...

  13. The ATLAS Silicon Pixel Sensors

    CERN Document Server

    Alam, M S; Einsweiler, K F; Emes, J; Gilchriese, M G D; Joshi, A; Kleinfelder, S A; Marchesini, R; McCormack, F; Milgrome, O; Palaio, N; Pengg, F; Richardson, J; Zizka, G; Ackers, M; Andreazza, A; Comes, G; Fischer, P; Keil, M; Klasen, V; Kühl, T; Meuser, S; Ockenfels, W; Raith, B; Treis, J; Wermes, N; Gössling, C; Hügging, F G; Wüstenfeld, J; Wunstorf, R; Barberis, D; Beccherle, R; Darbo, G; Gagliardi, G; Gemme, C; Morettini, P; Musico, P; Osculati, B; Parodi, F; Rossi, L; Blanquart, L; Breugnon, P; Calvet, D; Clemens, J-C; Delpierre, P A; Hallewell, G D; Laugier, D; Mouthuy, T; Rozanov, A; Valin, I; Aleppo, M; Caccia, M; Ragusa, F; Troncon, C; Lutz, Gerhard; Richter, R H; Rohe, T; Brandl, A; Gorfine, G; Hoeferkamp, M; Seidel, SC; Boyd, GR; Skubic, P L; Sícho, P; Tomasek, L; Vrba, V; Holder, M; Ziolkowski, M; D'Auria, S; del Papa, C; Charles, E; Fasching, D; Becks, K H; Lenzen, G; Linder, C

    2001-01-01

    Prototype sensors for the ATLAS silicon pixel detector have been developed. The design of the sensors is guided by the need to operate them in the severe LHC radiation environment at up to several hundred volts while maintaining a good signal-to-noise ratio, small cell size, and minimal multiple scattering. The ability to be operated under full bias for electrical characterization prior to the attachment of the readout integrated circuit electronics is also desired.

  14. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  15. ATLAS Pixel Opto-Electronics

    OpenAIRE

    Arms, K.E; Buchholz, P.; Gan, K. K.; Holder, M; Jackson, P.; Johnson, M.; Kagan, H.; Kass, R; Rahimi, A. M.; Roggenbuck, A.; Rush, C; Schade, P.; Smith, S.; Ter-Antonian, R.; Ziolkowski, M.

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 micron CMOS technology using enclosed layout transistors and guard rings for increased ...

  16. Results on 0.7% X0 thick pixel modules for the ATLAS detector

    CERN Document Server

    Netchaeva, P; Darbo, G; Einsweiler, Kevin F; Gagliardi, G; Gemme, C; Gilchriese, M G D; Oppizzi, P; Richardson, J; Rossi, L; Ruscino, E; Vernocchi, F; Znizka, G

    2001-01-01

    Modules are the basic building blocks of the ATLAS pixel detector system, they are made of a silicon sensor tile containing ~46000 pixel cells of 50 mu m*400 mu m, 16 front-end chips connected to the sensor through bump bonding, a kapton flex circuit and the module controller chip. The pixel detector is the first to encounter particles emerging from LHC interactions, minimization of radiation length of pixel modules is therefore very important. We report here on the construction techniques and on the operation of the first ATLAS pixel modules of 0.7% radiation length thickness. We have operated these modules with threshold of 3700*10+or-300*10, mean noise value of 225*10 and 0.3% dead channels. (3 refs).

  17. A Simulation of the Front End Signal Digitization for the ATLAS Muon Spectrometer thin RPC trigger upgrade project

    Science.gov (United States)

    Meng, Xiangting; Chapman, John; Levin, Daniel; Dai, Tiesheng; Zhu, Junjie; Zhou, Bing; Um Atlas Group Team

    2016-03-01

    The ATLAS Muon Spectrometer Phase-I (and Phase-II) upgrade includes the BIS78 muon trigger detector project: two sets of eight very thin Resistive Place Chambers (tRPCs) combined with small Monitored Drift Tube (MDT) chambers in the pseudorapidity region 1conducted detailed HPTDC latency simulations using the Behavioral Verilog code from the CERN group. We will report the results of these simulations run for the anticipated detector operating environment and for various HPTDC configurations.

  18. Intelligent Front Ends

    OpenAIRE

    Bundy, Alan

    1984-01-01

    An intelligent front end is a user-friendly interface to a software package, which uses Artificial Intelligence techniques to enable the user to interact with the computer using his/her own terminology rather than that demanded by the package. Several such systems exist and provide interfaces for finite element. statistical and simulation packages, and the area is an important area of growth for expert systems. In this paper we discuss the techniques required in an intelligent ...

  19. Test Beam Results of 3D Silicon Pixel Sensors for the ATLAS upgrade

    CERN Document Server

    Grenier, P; Barbero, M; Bates, R; Bolle, E; Borri, M; Boscardin, M; Buttar, C; Capua, M; Cavalli-Sforza, M; Cobal, M; Cristofoli, A; Dalla Betta, G F; Darbo, G; Da Via, C; Devetak, E; DeWilde, B; Di Girolamo, B; Dobos, D; Einsweiler, K; Esseni, D; Fazio, S; Fleta, C; Freestone, J; Gallrapp, C; Garcia-Sciveres, M; Gariano, G; Gemme, C; Giordani, M P; Gjersdal, H; Grinstein, S; Hansen, T; Hansen, T E; Hansson, P; Hasi, J; Helle, K; Hoeferkamp, M; Hugging, F; Jackson, P; Jakobs, K; Kalliopuska, J; Karagounis, M; Kenney, C; Köhler, M; Kocian, M; Kok, A; Kolya, S; Korokolov, I; Kostyukhin, V; Krüger, H; La Rosa, A; Lai, C H; Lietaer, N; Lozano, M; Mastroberardino, A; Micelli, A; Nellist, C; Oja, A; Oshea, V; Padilla, C; Palestri, P; Parker, S; Parzefall, U; Pater, J; Pellegrini, G; Pernegger, H; Piemonte, C; Pospisil, S; Povoli, M; Roe, S; Rohne, O; Ronchin, S; Rovani, A; Ruscino, E; Sandaker, H; Seidel, S; Selmi, L; Silverstein, D; Sjøbaek, K; Slavicek, T; Stapnes, S; Stugu, B; Stupak, J; Su, D; Susinno, G; Thompson, R; Tsung, J W; Tsybychev, D; Watts, S J; Wermes, N; Young, C; Zorzi, N

    2011-01-01

    Results on beam tests of 3D silicon pixel sensors aimed at the ATLAS Insertable-B-Layer and High Luminosity LHC (HL-LHC)) upgrades are presented. Measurements include charge collection, tracking efficiency and charge sharing between pixel cells, as a function of track incident angle, and were performed with and without a 1.6 T magnetic field oriented as the ATLAS Inner Detector solenoid field. Sensors were bump bonded to the front-end chip currently used in the ATLAS pixel detector. Full 3D sensors, with electrodes penetrating through the entire wafer thickness and active edge, and double-sided 3D sensors with partially overlapping bias and read-out electrodes were tested and showed comparable performance.

  20. Development of an analogue optical link for the front-end read-out of the ATLAS electromagnetic calorimeter

    CERN Document Server

    Dinkespiler, B; Olivetto, C; Martin, O; Mirea, A; Monnier, E; Tisserant, S; Wielers, M; Andrieux, M L; Ballon, J; Collot, J; Patti, A; Eek, L O; Go, A; Lund-Jensen, B; Pearce, M; Söderqvist, J; Coulon, J P

    1999-01-01

    We have developed an analogue optical data transmission system intended to meet the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. Eight-way demonstrators have been built and tested. The link uses arrays of VCSEL diodes as the optical emitters, coupled to a 70 m long fibre ribbon to simulate the distance between the detector and the control room. The receiver is based around a custom-designed PIN photodiode array. We describe here the final results of laboratory tests on a demonstrator, laying stress on the VCSEL-to-fibre coupling issues, and the overall performance of the full link. A 9-bit dynamic range is achieved, with a 5on-linearity.

  1. ATLAS Pixel Opto-Electronics

    CERN Document Server

    Arms, K E; Gan, K K; Holder, M; Jackson, P; Johnson, M; Kagan, H; Kass, R; Rahimi, A M; Roggenbuck, A; Rush, C; Schade, P; Smith, S; Ter-Antonian, R; Ziolkowski, M; Zoeller, M M

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 micron CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results of the performance of these chips, including irradiation with 24 GeV protons up to 61 Mrad (2.3 x 10e15 p/cm^2).

  2. Commissioning of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Golling, Tobias

    2008-09-01

    The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and summer 2008, and is ready for the imminent LHC turn-on. The highlights of the past and future commissioning activities of the ATLAS pixel system are presented.

  3. Operational experience of the ATLAS Pixel Detector

    CERN Document Server

    Marcisovsky, M; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  4. Operational experience of the ATLAS Pixel detector

    CERN Document Server

    Hirschbuehl, D; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  5. Operational experience with the ATLAS Pixel Detector

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost element of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  6. Commissioning of the ATLAS Pixel Detector

    OpenAIRE

    Golling, Tobias; ATLAS Collaboration

    2008-01-01

    The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and su...

  7. SNS Front End Diagnostics

    CERN Document Server

    Doornbos, J; Oshatz, D; Ratti, A; Staples, J W

    2000-01-01

    The Front End of the Spallation Neutron Source (SNS) extends from the Ion Source (IS), through a 65 keV LEBT, a 402.5 MHz RFQ, a 2.5 MeV MEBT, ending at the entrance to the DTL. The diagnostics suite in this space includes stripline beam position and phase monitors (BPM), toroid beam current monitors (BCM), and an emittance scanner. Provision is included for beam profile measurement, either gas fluorescence, laser-based photodissociation, or a crawling wire. Mechanical and electrical design and prototyping of BPM and BCM subsystems are proceeding. Significant effort has been devoted to packaging the diagnostic devices in minimal space. Close ties are maintained to the rest of the SNS effort, to ensure long term compatibility of interfaces and in fact share some design work and construction. The data acquisition, digital processing, and control system interface needs for the BPM, BCM, and LEBT diagnostic are similar, and we are committed to using an architecture common with the rest of the SNS collaboration.

  8. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  9. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Lantzsch, Kerstin; The ATLAS collaboration

    2016-01-01

    Run 2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). In addition the Pixel detector was refurbished with new service quarter panels to recover about 3% of defective modules lost during run 1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning, operation and performance of the 4-layer Pixel Detector will be presented.

  10. Test su fascio di prototipi del rivelatore a pixel per l'esperimento ATLAS

    CERN Document Server

    Matera, Andrea; Andreazza, A

    2005-01-01

    Silicon pixel detectors, developed to meet LHC requirements, were tested within the ATLAS collaboration in the H8 beam at CERN. Different sensor designs were studied using various versions of front end electronics developed during the R&D process. In this thesis a detailed experimental study of the overall performance of both irradiated and unirradiated detectors is presented, with special enphasis on efficiency, charge collection and spatial resolution. For the first time their dependence on timewalk is carefully investigated. Possible solutions to avoid spatial resolution deterioration due to timewalk are presented and discussed.

  11. Characterization of the ePix100 prototype: a front-end ASIC for second-generation LCLS integrating hybrid pixel detectors

    Science.gov (United States)

    Caragiulo, P.; Dragone, A.; Markovic, B.; Herbst, R.; Nishimura, K.; Reese, B.; Herrmann, S.; Hart, P.; Blaj, G.; Segal, J.; Tomada, A.; Hasi, J.; Carini, G.; Kenney, C.; Haller, G.

    2014-09-01

    ePix100 is the first variant of a novel class of integrating pixel ASICs architectures optimized for the processing of signals in second generation LINAC Coherent Light Source (LCLS) X-Ray cameras. ePix100 is optimized for ultra-low noise application requiring high spatial resolution. ePix ASICs are based on a common platform composed of a random access analog matrix of pixel with global shutter, fast parallel column readout, and dedicated sigma-delta analog to digital converters per column. The ePix100 variant has 50μmx50μm pixels arranged in a 352x384 matrix, a resolution of 50e- r.m.s. and a signal range of 35fC (100 photons at 8keV). In its final version it will be able to sustain a frame rate of 1kHz. A first prototype has been fabricated and characterized and the measurement results are reported here.

  12. Physics performance of the ATLAS Pixel Detector

    CERN Document Server

    Tsuno, Soshi; The ATLAS collaboration

    2016-01-01

    One noticeable upgrade from Run-1 to Run-2 with ATLAS detector in proton-proton collisions at LHC is the introduction of the new pixel detector, IBL, located on the beam pipe as the extra innermost pixel layer. The tracking and vertex reconstruction are significantly improved and good performance is expected in high level object such a $b$-quark jet tagging, in turn, it leads the better physics results. This note summarizes what is the impact on the IBL detector to the physics results especially focusing on the analyses using the $b$-quark jets throughout 2016 summer physics program.

  13. Upgrades of the ATLAS Pixel Detector

    CERN Document Server

    Hügging, F; The ATLAS collaboration

    2013-01-01

    The upgrade for the ATLAS detector will undergo different phases towards HL-LHC. The first upgrade for the Pixel Detector (Phase 1) consists in the construction of a new pixel layer, which will be installed during the 1st long shutdown of the LHC machine (LS1) in 2013/14. The new detector, called Insertable B-Layer (IBL), will be inserted between the existing pixel detector and a new (smaller radius) beam-pipe at a radius of about 3.2 cm. The IBL requires the development of several new technologies to cope with the increase of radiation and pixel occupancy as well as to improve the physics performance of the existing pixel detector. The pixel size is reduced and the material budget is minimized by using new lightweight mechanical support materials and a CO2 based cooling system. For Phase 2 upgrade of LHC a complete new 4-layer pixel system is planned as part of a new all silicon Inner Detector. The increase in luminosity to about $5\\cdot 10^{34}$cm$^{-2}$s$^{-1}$ together with a total expected lifetime of ab...

  14. Optical Link of the Atlas Pixel Detector

    OpenAIRE

    Gan, K. K.

    2007-01-01

    The on-detector optical link of the ATLAS pixel detector contains radiation-hard receiver chips to decode bi-phase marked signals received on PIN arrays and data transmitter chips to drive VCSEL arrays. The components are mounted on hybrid boards (opto-boards). We present results from the irradiation studies with 24 GeV protons up to 32 Mrad (1.2 x 10^15 p/cm^2) and the experience from the production.

  15. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    The calibration of the Pixel detector fulfills two main purposes: to tune front-end registers for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied toghether to chips with dierent characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  16. ATLAS rewards two pixel detector suppliers

    CERN Multimedia

    2007-01-01

    Peter Jenni, ATLAS spokesperson, presented the ATLAS supplier award to Herbert Reichl, IZM director, and to Simonetta Di Gioia, from the SELEX company.Two of ATLAS’ suppliers were awarded prizes at a ceremony on Wednesday 13 June attended by representatives of the experiment’s management and of CERN. The prizes went to the Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM) in Berlin and the company SELEX Sistemi Integrati in Rome for the manufacture of modules for the ATLAS pixel detector. SELEX supplied 1500 of the modules for the tracker, while IZM produced a further 1300. The modules, each made up of 46080 channels, form the active part of the ATLAS pixel detector. IZM and SELEX received the awards for the excellent quality of their work: the average number of faulty channels per module was less than 2.10-3. They also stayed within budget and on schedule. The difficulty they faced was designing modules based on electronic components and sensor...

  17. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  18. Multi Front-End Engineering

    Science.gov (United States)

    Botterweck, Goetz

    Multi Front-End Engineering (MFE) deals with the design of multiple consistent user interfaces (UI) for one application. One of the main challenges is the conflict between commonality (all front-ends access the same application core) and variability (multiple front-ends on different platforms). This can be overcome by extending techniques from model-driven user interface engineering.We present the MANTRA approach, where the common structure of all interfaces of an application is modelled in an abstract UI model (AUI) annotated with temporal constraints on interaction tasks. Based on these constraints we adapt the AUI, e.g., to tailor presentation units and dialogue structures for a particular platform. We use model transformations to derive concrete, platform-specific UI models (CUI) and implementation code. The presented approach generates working prototypes for three platforms (GUI, web, mobile) integrated with an application core via web service protocols. In addition to static evaluation, such prototypes facilitate early functional evaluations by practical use cases.

  19. optical links for the atlas pixel detector

    CERN Document Server

    Stucci, Stefania Antonia; The ATLAS collaboration

    2015-01-01

    Optical links are necessary to satisfy the high speed readout over long distances for advanced silicon detector systems. We report on the optical readout used in the newly installed central pixel layer (IBL) in the ATLAS experiment. The off detector readout employs commercial optical to analog converters, which were extensively tested for this application. Performance measurements during installation and commissioning will be shown. With the increasing instantaneous luminosity in the next years, the next layers outwards of IBL of the ATLAS Pixel detector (Layer 1 and Layer 2) will reach their bandwidth limits. A plan to increase the bandwidth by upgrading the off detector readout chain is put in place. The plan also involves new optical readout components, in particular the optical receivers, for which commercial units cannot be used and a new design has been made. The latter allows for a wider operational range in term of data frequency and light input power to match the on-detector sending units on the pres...

  20. Optical links for the ATLAS Pixel detector

    CERN Document Server

    Stucci, Stefania Antonia; The ATLAS collaboration

    2015-01-01

    Optical links are necessary to satisfy the high speed readout over long distances for advanced silicon detector systems. We report on the optical readout used in the newly installed central pixel layer (IBL) in the ATLAS experiment. The off detector readout employs commercial optical to analog converters, which were extensively tested for this application. Performance measurements during installation and commissioning will be shown. With the increasing instantaneous luminosity in the next years, the next layers outwards of IBL of the ATLAS Pixel detector (Layer 1 and Layer 2) will reach their bandwidth limits. A plan to increase the bandwidth by upgrading the off detector readout chain is put in place. The plan also involves new optical readout components, in particular the optical receivers, for which commercial units cannot be used and a new design has been made. The latter allows for a wider operational range in term of data frequency and light input power to match the on-detector sending units on the pres...

  1. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    Science.gov (United States)

    Gabrielli, A.; Backhaus, M.; Balbi, G.; Bindi, M.; Chen, S. P.; Falchieri, D.; Flick, T.; Hauck, S.; Hsu, S. C.; Kretz, M.; Kugel, A.; Lama, L.; Travaglini, R.; Wensing, M.

    2015-03-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014.

  2. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

  3. Operational experience with the ATLAS Pixel Detector at the LHC

    Science.gov (United States)

    Lapoire, C.; Atlas Collaboration

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as B-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy is sufficiently low and hit efficiency exceed the design specification.

  4. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Hirschbuehl, D; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.7% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  5. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  6. Operational experience with the ATLAS Pixel detector at the LHC

    CERN Document Server

    Deluca, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5\\% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, ...

  7. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.8% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  8. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lapoire, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  9. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lapoire, C; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as B-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification.

  10. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lange, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump- bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, a...

  11. Operational experience with the ATLAS Pixel detector at the LHC

    CERN Document Server

    Deluca, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  12. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  13. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  14. ATLAS Pixel Radiation Monitoring with HVPP4 System

    CERN Document Server

    Gorelov, Igor; Seidel, Sally; Toms, Konstantin

    2009-01-01

    In this talk we present the basis for the protocol for radiation monitoring of the ATLAS Pixel Sensors. The monitoring is based on a current measurement system, HVPP4. The status on the ATLAS HVPP4 system development is also presented.

  15. Module concepts with ultra thin FE chips and Through Silicon Vias for the upgrades of the ATLAS pixel detector

    International Nuclear Information System (INIS)

    The development of trackers for High Energy Physics experiments at high luminosity poses strict requirements on the material budget to allow good vertexing and b-tagging performance. State-of-the-art silicon technologies offer a variety of processes that can be used to achieve light modules design. Together with IZM Berlin we investigated the thinning of FE (Front-End) chips down to 90 μm, and developed a dedicated flip chip process to assure a reliable mechanical and electrical connection between thin FE chips and sensor. The selected flip chip method is currently used for the production of modules for the IBL (Insertable B-Layer) project, the first ATLAS pixel detector upgrade. Results from the characterization of IBL modules with 100 and 150 μm thin FE chip are shown. For future upgrades of the ATLAS pixel detector we propose more advanced module concepts with Through Silicon Vias (TSVs). IZM offers two via last TSV processes, Straight Side Wall TSVs and Tapered Side Wall TSVs. Both processes were successfully demonstrated with ATLAS pixel readout electronics (FE-I2/3). Results from prototype modules with planar sensor and 90 μm thin FE-I2 with Tapered TSV and back side redistribution layer are shown.

  16. DAQ hardware and software development for the ATLAS Pixel Detector

    Science.gov (United States)

    Stramaglia, Maria Elena

    2016-07-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed readout hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the readout boards. The same boards will be used to upgrade the readout bandwidth for the two outermost barrel layers of the ATLAS Pixel Detector. We present the IBL readout hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel Detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  17. SPD very front end electronics

    International Nuclear Information System (INIS)

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  18. Neural network based cluster creation in the ATLAS Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing be- tween pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. How- ever, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambigui- ties in the assignment of pixel detector measurement to tracks and improves the position accuracy with respect to standard techniques by taking into account the 2-dimensional charge distribution.

  19. Studio di Rivelatori a Pixel di nuova generazione per il Sistema di Tracciamento di ATLAS.

    CERN Document Server

    Gaudiello, Andrea; Schiavi, Carlo

    In 2013 the LHC will undergo a long shutdown (Phase 0) in preparation for a an energy and luminosity upgrade. During this period the ATLAS Pixel Detector (that is the tracking detector closest to the beamline) will be upgraded. The new detector, called Insertable B-Layer (IBL), will be installed between the existing pixel detector and a new beam-pipe of smaller radius in order to ensure and maintain excellent performance of tracking, vertexing and jet flavor tagging. To satisfy the new requirements a new electronic front- end (FE-I4) and 2 sensor technologies have been developed: Planar and 3D. Genova is one of two sites dedicated to the assembly of the modules of IBL. The work is then carried out in two parallel directions: on one hand the production and its optimization; on the other the comparison and testing of these new technologies. Chapter 1 gives an overview of the theoretical framework needed to understand the importance and the goals of the experiments operating at the Large Hadron Collider (LHC), w...

  20. ATLAS Inner Detector (Pixel Detector and Silicon Tracker)

    CERN Multimedia

    ATLAS Outreach

    2006-01-01

    To raise awareness of the basic functions of the Pixel Detector and Silicon Tracker in the ATLAS detector on the LHC at CERN. This colorful 3D animation is an excerpt from the film "ATLAS-Episode II, The Particles Strike Back." Shot with a bug's eye view of the inside of the detector. The viewer is taken on a tour of the inner workings of the detector, seeing critical pieces of the detector and hearing short explanations of how each works.

  1. A Novel Optical Package for ATLAS Pixel Detector

    CERN Document Server

    Gan, K K

    2001-01-01

    An optical package of novel design has been developed for the ATLAS pixel detector. The package contains two VCSELs and one PIN diode to transmit and receive optical signals. The design is based on a simple connector-type concept and is made of radiation-hard material. Several packages have been fabricated and show promising results.

  2. The ATLAS pixel stave emulator for serial powering

    International Nuclear Information System (INIS)

    A serial powering scheme is being developed for the upgrade of the ATLAS pixel detector in view of sLHC. It offers in fact significant advantages over the presently used parallel powering scheme, namely reduced material budget in active area and power losses on cables, smaller number of power supplies, and no need for external, distant regulation of voltages. The development of this powering scheme requires not only the design of custom-developed voltage regulators, the basic elements of serial powering, but also the early study of system aspects connected to it, for instance the safety of the powering chain and AC-coupled data transmission. To this aim a test system emulating an ATLAS pixel stave is being developed. It will provide a realistic environment to test both concepts and sub-components. Due to its flexibility, it will offer the possibility to study not only serial powering concepts, but more generally system aspects related to the ATLAS pixel detector. In particular alternative powering schemes, data coding schemes, physical layer data transmission, and Detector Control System concepts will also be evaluated with this test system. The description and development of the ATLAS pixel stave emulator are presented and first results are discussed

  3. ATLAS Pixel Detector ROD card from IBL towards Layers 2 and 1

    Science.gov (United States)

    Balbi, G.; Falchieri, D.; Gabrielli, A.; Lama, L.; Giangiacomi, N.; Travaglini, R.

    2016-01-01

    The incoming and future upgrades of LHC will require better performance by the data acquisition system, especially in terms of throughput due to the higher luminosity that is expected. For this reason, during the first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector has been equipped with a fourth layer— the Insertable B-Layer or IBL—located at a radius smaller than the present three layers. To read out the new layer of pixels, with a smaller pixel size with respect to the other outer layers, a front end ASIC (FE-I4) was designed as well as a new off-detector read-out chain. The latter, accordingly to the structure of the other layers of pixels, is composed mainly of two 9U-VME read-out off-detector cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Another production of 15 ROD cards was done in Fall 2013, and commissioning was completed in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards were produced for a total initial batch of 20 boards. This paper describes some integration tests that were performed and our plan to install the new DAQ chain for the layer 2, which is the outermost, and layer 1, which is external to the B-layer. This latter is the only layer that will not be upgraded to a higher readout speed. Rather, it will be switched off in the near future as it has too many damaged sensors that were not possible to rework. To do that, slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. Thus, this contribution reports also how the adoption of the IBL ROD for ATLAS Pixel

  4. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2008-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

  5. Online calibrations and performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

  6. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik;

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... This contribution deals with the development of product platforms in front-end projects and introduces a modeling tool: the Conceptual Product Platform model. State of the art within platform modeling forms the base of a modeling formalism for a Conceptual Product Platform model. The modeling formalism is explored...... through an example and applied in a case in which the Conceptual Product Platform model has supported the front-end development of a platform for an electro-active polymer technology. The case describes the contents of the model and how its application supported the development work in the project...

  7. High-voltage pixel sensors for ATLAS upgrade

    Science.gov (United States)

    Perić, I.; Kreidl, C.; Fischer, P.; Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M.; Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B.; Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A.; Nessi, M.; Iacobucci, G.; Backhaus, M.; Hügging, Fabian; Krüger, H.; Hemperek, T.; Obermann, T.; Wermes, N.; Garcia-Sciveres, M.; Quadt, A.; Weingarten, J.; George, M.; Grosse-Knetter, J.; Rieger, J.; Bates, R.; Blue, A.; Buttar, C.; Hynds, D.

    2014-11-01

    The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

  8. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  9. The front end electronics for LHCb calorimeters

    CERN Document Server

    Beigbeder-Beau, C; Breton, D; Cacéres, T; Callot, O; Cros, P; Delcourt, B; Jean-Marie, B; Lefrançois, J; Hrisoho, A T; Tocut, V; Truong, K D; Videau, I

    1999-01-01

    The electronics for the electromagnetic and hadronic calorimeters of LHCb is under design. The 32 channel-9U front-end board offers the complete front-end and readout electronics for every channel including original shaping, 12bit-40MHz ADC, digital filtering and latency for level 0 and level 1 triggers. The clipped PM input signal is integrated during 25ns, but also delayed then subtracted to itself 25ns later which allows performant pile up independence. This board also includes the first processing levels of the L0 calorimeter trigger. A 16 channel-6U prototype board has been designed and used at CERN in test beam in 1999.

  10. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. In the ATLAS track reconstruction algorithm, an artificial neural network is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The robustness of the neural network algorithm is presented, probing its sensitivity to uncertainties in the detector conditions. The robustness is studied by evaluating the stability of the algorithm's performance under a range of variations in the inputs to the neural networks. Within reasonable variation magnitudes, the neural networks prove to be robust to most variation types.

  11. JFET-CMOS microstrip front-end

    International Nuclear Information System (INIS)

    While the CMOS version of the front-end chip developed for the microstrip vertex detector of the Aleph experiment is ready to go into operation, a new development is being carried on to achieve a reduction in noise. The improvement is related to the use of a JFET-CMOS chip design which is described in the present paper. (orig.)

  12. Online Calibration and Performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  13. Optical Links for the ATLAS Pixel Detector

    CERN Document Server

    Gregor, Ingrid-Maria

    In der vorliegenden Dissertation wird eine strahlentolerante optische Datenstrecke mit hoher Datenrate für den Einsatz in dem Hochenergiephysikexperiment Atlas am Lhc Beschleuniger entwickelt. Da die Lhc-Experimente extremen Strahlenbelastungen ausgesetzt sind, müssen die Komponenten spezielle Ansprüche hinsichtlich der Strahlentoleranz erfüllen. Die Qualifikation der einzelnen Bauteile wurde im Rahmen dieser Arbeit durchgeführt. Die zu erwartenden Fluenzen im Atlas Inner Detector für Silizium und Gallium Arsenid (GaAs) wurden berechnet. Siliziumbauteile werden einer Fluenz von bis zu 1.1.1015neq /cm2 in 1 MeV äquivalenten Neutronen ausgesetzt sein, wohingegen GaAs Bauteile bis zu 7.8.1015neq /cm2 ausgesetzt sein werden. Die Strahlentoleranz der einzelnen benötigten Komponenten wie z.B. der Laserdioden sowie der jeweiligen Treiberchips wurde untersucht. Sowohl die Photo- als auch die Laserdioden haben sich als strahlentolerant für die Fluenzen an dem vorgesehenen Radius erwiesen. Aus de...

  14. Monitoring Radiation Damage in the ATLAS Pixel Detector

    CERN Document Server

    Schorlemmer, André Lukas; Große-Knetter, Jörn; Rembser, Christoph; Di Girolamo, Beniamino

    2014-11-05

    Radiation hardness is one of the most important features of the ATLAS pixel detector in order to ensure a good performance and a long lifetime. Monitoring of radiation damage is crucial in order to assess and predict the expected performance of the detector. Key values for the assessment of radiation damage in silicon, such as the depletion voltage and depletion depth in the sensors, are measured on a regular basis during operations. This thesis summarises the monitoring program that is conducted in order to assess the impact of radiation damage and compares it to model predictions. In addition, the physics performance of the ATLAS detector highly depends on the amount of disabled modules in the ATLAS pixel detector. A worrying amount of module failures was observed during run I. Thus it was decided to recover repairable modules during the long shutdown (LS1) by extracting the pixel detector. The impact of the module repairs and module failures on the detector performance is analysed in this thesis.

  15. Planar pixel detector module development for the HL-LHC ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Bates, Richard L., E-mail: richard.bates@glasgow.ac.uk [SUPA School of Physics and Astronomy, University of Glasgow, Glasgow G12 8QQ (United Kingdom); Buttar, C.; Stewart, A.; Blue, A.; Doonan, K.; Ashby, J. [SUPA School of Physics and Astronomy, University of Glasgow, Glasgow G12 8QQ (United Kingdom); Casse, G.; Dervan, P.; Forshaw, D.; Tsurin, I. [The University of Liverpool, Liverpool (United Kingdom); Brown, S.; Pater, J. [The Univiersty of Manchester, Manchester (United Kingdom)

    2013-12-11

    The ATLAS pixel detector for the HL-LHC requires the development of large area pixel modules that can withstand doses up to 10{sup 16} 1 MeV n{sub eq} cm{sup −2}. The area of the pixel detector system will be over 5 m{sup 2} and as such low cost, large area modules are required. The development of a quad module based on 4 FE-I4 readout integrated chips (ROIC) will be discussed. The FE-I4 ROIC is a large area chip and the yield of the flip-chip process to form an assembly is discussed for single chip assemblies. The readout of the quad module for laboratory tests will be reported.

  16. Planar pixel detector module development for the HL-LHC ATLAS pixel system

    Science.gov (United States)

    Bates, Richard L.; Buttar, C.; Stewart, A.; Blue, A.; Doonan, K.; Ashby, J.; Casse, G.; Dervan, P.; Forshaw, D.; Tsurin, I.; Brown, S.; Pater, J.

    2013-12-01

    The ATLAS pixel detector for the HL-LHC requires the development of large area pixel modules that can withstand doses up to 1016 1 MeV neq cm-2. The area of the pixel detector system will be over 5 m2 and as such low cost, large area modules are required. The development of a quad module based on 4 FE-I4 readout integrated chips (ROIC) will be discussed. The FE-I4 ROIC is a large area chip and the yield of the flip-chip process to form an assembly is discussed for single chip assemblies. The readout of the quad module for laboratory tests will be reported.

  17. Planar pixel detector module development for the HL-LHC ATLAS pixel system

    International Nuclear Information System (INIS)

    The ATLAS pixel detector for the HL-LHC requires the development of large area pixel modules that can withstand doses up to 1016 1 MeV neq cm−2. The area of the pixel detector system will be over 5 m2 and as such low cost, large area modules are required. The development of a quad module based on 4 FE-I4 readout integrated chips (ROIC) will be discussed. The FE-I4 ROIC is a large area chip and the yield of the flip-chip process to form an assembly is discussed for single chip assemblies. The readout of the quad module for laboratory tests will be reported

  18. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  19. Pixel detector modules performance for ATLAS IBL and future pixel detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00355104; Pernegger, Heinz

    2015-11-06

    The ATLAS Detector is one of the four big particle physics experiments at CERN’s LHC. Its innermost tracking system consisted of the 3-Layer silicon Pixel Detector (~80M readout channels) in the first run (2010-2012). Over the past two years it was refurbished and equipped with new services as well as a new beam monitor. The major upgrade, however, was the Insertable B-Layer (IBL). It adds ~12M readout channels for improved vertexing, tracking robustness and b-tagging performance for the upcoming runs, before the high luminosity upgrade of the LHC will take place. This thesis covers two main aspects of Pixel detector performance studies: The main work was the planning, commissioning and operation of a test bench that meets the requirements of current pixel detector components. Each newly built ATLAS IBL stave was thoroughly tested, following a specifically developed procedure, and initially calibrated in that setup. A variety of production accompanying measurements as well as preliminary results after integ...

  20. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

  1. Development of a Micro Pixel Chamber for the ATLAS Upgrade

    CERN Document Server

    Ochi, Atsuhiko; Komai, Hidetoshi; Edo, Yuki; Yamaguchi, Takahiro

    2012-01-01

    The Micro Pixel Chamber (μ-PIC) is being developed a sacandidate for the muon system of the ATLAS detector for upgrading in LHC experiments. The μ-PIC is a micro-pattern gaseous detector that doesn’t have floating structure such as wires, mesh, or foil. This detector can be made by printed-circuit-board (PCB) technology, which is commercially available and suited for mass production. Operation tests have been performed under high flux neutrons under similar conditions to the ATLAS cavern. Spark rates are measured using several gas mixtures under 7 MeV neutron irradiation, and good properties were observed using neon, ethane, and CF4 mixture of gases.Using resistive materials as electrodes, we are also developing a new μ-PIC, which is not expected to damage the electrodes in the case of discharge sparks.

  2. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2010-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  3. PMF: The front end electronic of the ALFA detector

    Energy Technology Data Exchange (ETDEWEB)

    Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

    2010-11-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  4. Evaluation of novel KEK/HPK n-in-p pixel sensors for ATLAS upgrade with testbeam

    International Nuclear Information System (INIS)

    A new type of n-in-p planar pixel sensors have been developed at KEK/HPK in order to cope with the maximum particle fluence of 1–3×1016 1 MeV equivalent neutrons per square centimeter (neq/cm2) in the upcoming LHC upgrades. Four n-in-p devices were connected by bump-bonding to the new ATLAS Pixel front-end chip (FE-I4A) and characterized before and after the irradiation to 2×1015neq/cm2. These planar sensors are 150μm thick, using biasing structures made out of polysilicon or punch-through dot and isolation structures of common or individual p-stop. Results of measurements with radioactive 90Sr source and with a 120 GeV/c momentum pion beam at the CERN Super Proton Synchrotron (SPS) are presented. The common p-stop isolation structure shows a better performance than the individual p-stop design, after the irradiation. The flat distribution of the collected charge in the depth direction after the irradiation implies that the effect of charge trapping is small, at the fluence, with the bias voltage well above the full depletion voltage.

  5. CDF front end electronics: The RABBIT system

    International Nuclear Information System (INIS)

    A new crate-based front end system has been built featuring low cost, compact packaging, fast readout, command capability, 16 bit digitiziation, and a high degree of redundancy. The crate can contain a variety of instrumentation modules and is designed to be placed near the detector. Remote, special purpose processors direct the data readout. Channel-by-channel pedestal subtraction and threshold comparison in the crate allow the skipping of empty channels. The system is suitable for the readout of a very large number of channels. (orig.)

  6. ATLAS Phase-II-Upgrade Pixel Data Transmission Development

    CERN Document Server

    Wensing, Marius; The ATLAS collaboration

    2016-01-01

    The ATLAS tracking system will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics based on the currently foreseen trigger rate of 1 MHz indicate that a readout speed of up to 5 Gbps per data link is necessary. Due to radiation levels, the first part of transmission has to be implemented electrically. System simulation and test results of cable candidates will be presented.

  7. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    Sidebo, Per Edvin; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. The algorithms depend heavily on accurate estimation of the position of particles as they traverse the inner detector elements. An artificial neural network algorithm is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The method recovers otherwise lost tracks in dense environments where particles are separated by distances comparable to the size of the detector read-out elements. Such environments are highly relevant for LHC run 2, e.g. in searches for heavy resonances. Within the scope of run 2 track reconstruction performance and upgrades, the robustness of the neural network algorithm will be presented. The robustness has been studied by evaluating the stability of the algorithm’s performance under a range of variations in the pixel detector conditions.

  8. Validation studies of the ATLAS pixel detector control system

    Energy Technology Data Exchange (ETDEWEB)

    Schultes, Joachim [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany)]. E-mail: schultes@physik.uni-wuppertal.de; Becks, Karl-Heinz [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Flick, Tobias [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Henss, Tobias [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Imhaeuser, Martin [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Kersten, Susanne [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Kind, Peter [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Lantzsch, Kerstin [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Maettig, Peter [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Reeves, Kendall [University of Wuppertal, Gaussstr. 20, 42097 Wuppertal (Germany); Weingarten, Jens [University of Bonn, Nussallee 12, 53115 Bonn (Germany)

    2006-09-01

    The ATLAS pixel detector consists of 1744 identical silicon pixel modules arranged in three barrel layers providing coverage for the central region, and three disk layers on either side of the primary interaction point providing coverage of the forward regions. Once deployed into the experiment, the detector will employ optical data transfer, with the requisite powering being provided by a complex system of commercial and custom-made power supplies. However, during normal performance and production tests in the laboratory, only single modules are operated and electrical readout is used. In addition, standard laboratory power supplies are used. In contrast to these normal tests, the data discussed here were obtained from a multi-module assembly which was powered and read out using production items: the optical data path, the final design power supply system using close to final services, and the Detector Control System (DCS)

  9. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Rummler, Andr{e}; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

  10. Universal Millimeter-Wave Radar Front End

    Science.gov (United States)

    Perez, Raul M.

    2010-01-01

    A quasi-optical front end allows any arbitrary polarization to be transmitted by controlling the timing, amplitude, and phase of the two input ports. The front end consists of two independent channels horizontal and vertical. Each channel has two ports transmit and receive. The transmit signal is linearly polarized so as to pass through a periodic wire grid. It is then propagated through a ferrite Faraday rotator, which rotates the polarization state 45deg. The received signal is propagated through the Faraday rotator in the opposite direction, undergoing a further 45 of polarization rotation due to the non-reciprocal action of the ferrite under magnetic bias. The received signal is now polarized at 90deg relative to the transmit signal. This signal is now reflected from the wire grid and propagated to the receive port. The horizontal and vertical channels are propagated through, or reflected from, another wire grid. This design is an improvement on the state of the art in that any transmit signal polarization can be chosen in whatever sequence desired. Prior systems require switching of the transmit signal from the amplifier, either mechanically or by using high-power millimeter-wave switches. This design can have higher reliability, lower mass, and more flexibility than mechanical switching systems, as well as higher reliability and lower losses than systems using high-power millimeter-wave switches.

  11. Pixel-Cluster Counting Luminosity Measurement in ATLAS

    CERN Document Server

    McCormack, William Patrick; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measurements of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster-counting method are ...

  12. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    Smart, Ben; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline. High-eta particles will therefore hit these sensors at shallow angles, leaving elongated charge clusters. The length of such a charge cluster can be used to estimate the angle of the passing particle. This information can then be used in track reconstruction to improve tracking efficiency and reduce fake rates. Inclined designs ...

  13. Front-end Multiplexing - applied to SQUID multiplexing : Athena X-IFU and QUBIC experiments

    CERN Document Server

    Prêle, Damien

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device...

  14. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  15. ATLAS pixel detector timing optimisation with the back of crate card of the optical pixel readout system

    Energy Technology Data Exchange (ETDEWEB)

    Flick, T; Gerlach, P; Reeves, K; Maettig, P [Department of Physics, Bergische Universitaet Wuppertal (Germany)

    2007-04-15

    As with all detector systems at the Large Hadron Collider (LHC), the assignment of data to the correct bunch crossing, where bunch crossings will be separated in time by 25 ns, is one of the challenges for the ATLAS pixel detector. This document explains how the detector system will accomplish this by describing the general strategy, its implementation, the optimisation of the parameters, and the results obtained during a combined testbeam of all ATLAS subdetectors.

  16. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mathes, Markus

    2008-12-15

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  17. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  18. ATLAS Pixel-Optoboard Production and Simulation Studies

    CERN Document Server

    Nderitu, Simon

    At CERN, a Large collider will collide protons at high energies. There are four experiments being built to study the particle properties from the collision. The ATLAS experiment is the largest. It has many sub detectors among which is the Pixel detector which is the innermost part. The Pixel detector has eighty million channels that have to be read out. An optical link is utilized for the read out. It has optical to electronic interfaces both on the detector and off the detector at the counting room. The component on the detector in called the opto-board. This work discusses the production testing of the opto-boards to be installed on the detector. A total of 300 opto-boards including spares have been produced. The production was done in three laboratories among which is the laboratory at the University of Wuppertal which had the responsibility of Post production testing of all the one third of the total opto-boards. The results are discussed in this work. The analysis of the results from the total productio...

  19. Realisation of serial powering of ATLAS pixel modules

    CERN Document Server

    Stockmanns, Tobias; Fischer, P; Hügging, Fabian Georg; Peric, Ivan; Runólfsson, Ogmundur; Wermes, Norbert

    2004-01-01

    Modern hybrid pixel detectors as they will be used for the next generation of high energy collider experiments like LHC avail deep sub micron technology for the readout electronics. To operate chips in this technology low supply voltages of 2.0 V to 2.5 V and high currents to achieve the desired performance are needed. Due to the long and low mass supply cables this high current leads to a significant voltage drop so that voltage fluctuations at the chip result, when the supply current changes. Therefore the parallel connection of the readout electronics with the power supplies imposes severe constraints on a detector with respect to voltage fluctuations and cable mass. To bypass this problem a new concept of serially connecting modules in a supply chain was developed. The basic idea of the concept, the potential risk and ways to minimize these risks are presented. In addition, studies of the implementation of this technology as an alternative for a possible upgrade of the ATLAS pixel detector are shown. In p...

  20. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  1. The upgraded CDF front end electronics for calorimetry

    International Nuclear Information System (INIS)

    The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

  2. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  3. Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

    Science.gov (United States)

    Backhaus, M.

    2013-03-01

    The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3·1034 cm-2s-1with an integrated luminosity over the IBL lifetime of 300 fb-1 corresponding to a design lifetime fluence of 5·1015 neqcm-2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is described. Preliminary wafer to wafer distributions as well as yield calculations are given.

  4. Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

    CERN Document Server

    Backhaus, Malte

    2013-01-01

    The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3 x 10^34 cm^-2 s^-1 with an integrated luminosity over the IBL lifetime of 300 fb^-1 corresponding to a design lifetime fluence of 5 x 10^15 n_eq cm^-2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these results, is de...

  5. Characterization of the FE-I4B pixel readout chip production run for the ATLAS Insertable B-layer upgrade

    CERN Document Server

    Backhaus, M

    2013-01-01

    The Insertable B-layer (IBL) is a fourth pixel layer that will be added inside the existing ATLAS pixel detector during the long LHC shutdown of 2013 and 2014. The new four layer pixel system will ensure excellent tracking, vertexing and b-tagging performance in the high luminosity pile-up conditions projected for the next LHC run. The peak luminosity is expected to reach 3• 10^34 cm^−2 s ^−1with an integrated luminosity over the IBL lifetime of 300 fb^−1 corresponding to a design lifetime fluence of 5 • 10^15 n_eqcm^−2 and ionizing dose of 250 Mrad including safety factors. The production front-end electronics FE-I4B for the IBL has been fabricated at the end of 2011 and has been extensively characterized on diced ICs as well as at the wafer level. The production tests at the wafer level were performed during 2012. Selected results of the diced IC characterization are presented, including measurements of the on-chip voltage regulators. The IBL powering scheme, which was chosen based on these resu...

  6. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics b

  7. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  8. Development and Characterization of Diamond and 3D-Silicon Pixel Detectors with ATLAS-Pixel Readout Electronics

    CERN Document Server

    Mathes, Markus

    2008-01-01

    Abstract: Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10^16 particles per cm^2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 × 50 um^2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm^2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 × 6 cm^2). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge c...

  9. Simulation of gas mixture drift properties for GasPixel detector for modernization of ATLAS

    International Nuclear Information System (INIS)

    Results of simulation of gas mixture drift properties for GasPixel detector are presented. The properties of gaseous mixtures for the GasPixel detector have been studied in view of its use in high luminosity tracking applications for the ATLAS Inner Detector in a future super-LHC collider

  10. Simulations of 3D-Si sensors for the innermost layer of the ATLAS pixel upgrade

    CERN Document Server

    Baselga, Marta; Quirion, David

    2016-01-01

    The LHC is expected to reach luminosities up to 3000fb-1 and the innermost layer of the ATLAS upgrade plans to cope with higher occupancy and to decrease the pixel size. 3D-Si sensors are a good candidate for the innermost layer of the ATLAS pixel upgrade since they exhibit good performance under high fluences and the new designs will have smaller pixel size to fulfill the electronics expectations. This paper reports TCAD simulations of the 3D-Si sensors designed at IMB-CNM with non passing-through columns that are being fabricated for the next innermost layer of the ATLAS pixel upgrade, shows the charge collection response before and after irradiation, and the response of 3D-Si sensors located at large $\\eta$ angles.

  11. The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

    Science.gov (United States)

    Backhaus, M.

    2016-09-01

    During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO2 based cooling system. This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

  12. Status and future of the ATLAS Pixel Detector at the LHC

    International Nuclear Information System (INIS)

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of disks in each forward end-cap. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-on-n silicon substrates. Intensive calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. The record breaking instantaneous luminosities of 7.7×1033cm−2s−1 recently surpassed at the LHC generated a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulated, the first effects of radiation damage became observable in the silicon sensors as an increase in the silicon leakage current and the change of the voltage required to fully deplete the sensor. A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014) together with the replacement of pixel services. A letter of intent was submitted for a completely new Pixel Detector after 2023, capable to take data with extremely high leveled luminosities of 5×1034cm−2s−1 at the high luminosity LHC. -- Highlights: •The ATLAS Pixel Detector provides hermetic coverage with three layers with 80 million pixels. •Calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. •First effects of radiation damage became observable in the silicon sensors. •A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014). •Replacement of pixel services in 2013–2014. •A letter of intent was submitted for new Pixel Detector after 2023 for high luminosity LHC

  13. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  14. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2013-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  15. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Perez Cavalcanti, T; The ATLAS collaboration

    2012-01-01

    The hit signals read out from pixels on planar semi-conductor sensors are grouped into clusters, to reconstruct the location where a charged particle passed through. The resolution of the individual pixel sizes can be improved significantly using the information from the cluster of adjacent pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years giving an excellent performance. However, in dense environments, such as those inside high-energy jets, is likely that the charge deposited by two or more close-by tracks merges into one single cluster. A new pattern recognition algorithm based on neural network methods has been developed for the ATLAS Pixel Detector. This can identify the shared clusters, split them if necessary, and estimate the positions of all particles traversing the cluster. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurements to tracks within jets, and improves the positional accuracy with respect to stand...

  16. RF photonic front-end integrating with local oscillator loop.

    Science.gov (United States)

    Yu, H; Chen, M; Gao, H; Yang, S; Chen, H; Xie, S

    2014-02-24

    Broadband Radio frequency (RF) photonic front-ends are one of the vital applications of the microwave photonics. A tunable and broadband RF photonic front-end integrating with the optoelectronic oscillator (OEO) based local oscillator has been proposed and experimentally demonstrated, in which only one phase modulator (PM) is employed thanks to the characteristic of the PM. The silicon-on-insulator based narrow-bandwidth band-pass filter is introduced for signal processing. The application condition of the proposed RF photonic front-end has been discussed and the performance of the front-end has also been measured. The SFDR at a frequency of about 7.02 GHz is measured to be 88.6 dB-Hz(2/3). PMID:24663712

  17. Idea management in support of pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

  18. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2016-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case...... study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...... added and the contribution of this article to the existing FEI and HR literature therefore lies in the exploration and mapping of how radical front end innovation is and can be facilitated through targeted HR practices; and in identifying the unique opportunities and challenges of innovation...

  19. Radiation hardness on very front-end for SPD

    Energy Technology Data Exchange (ETDEWEB)

    Cano, Xavier [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain)]. E-mail: xcano@ub.edu; Graciani, Ricardo [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Gascon, David [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Garrido, Lluis [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Bota, Sebastia [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Herms, Atila [Departament d' Electronica, Universitat de Barcelona, Marti i Franques 1, 08028 Barcelona (Spain); Comerma, Albert [Departament d' Estructura i Constituents de la Materia, Universitat de Barcelona (Spain); Riera, Jordi [Departament d' Electronica, Universitat Ramon Llull (Spain)

    2005-10-11

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available.

  20. Phase 1 Front-End CMS Calorimeter (HE) Upgrade Preparation

    CERN Document Server

    Bunin, Pavel

    2016-01-01

    Preparation of HE Phase 1 Front-End upgrade is shown. For the final quality control of the new generation HE front-end electronics components a Burn-in stand has been prepared. All electronics components are being tested on the burn-in stand and should pass through the burn-in QC before the installation on the CMS. First tests and results are presented.

  1. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  2. SiPM and front-end electronics development for Cherenkov light detection

    CERN Document Server

    Ambrosi, G; Bissaldi, E; Ferri, A; Giordano, F; Gola, A; Ionica, M; Paoletti, R; Piemonte, C; Paternoster, G; Simone, D; Vagelli, V; Zappala, G; Zorzi, N

    2015-01-01

    The Italian Institute of Nuclear Physics (INFN) is involved in the development of a demonstrator for a SiPM-based camera for the Cherenkov Telescope Array (CTA) experiment, with a pixel size of 6$\\times$6 mm$^2$. The camera houses about two thousands electronics channels and is both light and compact. In this framework, a R&D program for the development of SiPMs suitable for Cherenkov light detection (so called NUV SiPMs) is ongoing. Different photosensors have been produced at Fondazione Bruno Kessler (FBK), with different micro-cell dimensions and fill factors, in different geometrical arrangements. At the same time, INFN is developing front-end electronics based on the waveform sampling technique optimized for the new NUV SiPM. Measurements on 1$\\times$1 mm$^2$, 3$\\times$3 mm$^2$, and 6$\\times$6 mm$^2$ NUV SiPMs coupled to the front-end electronics are presented

  3. Testbeam Measurements with Pixel Sensors for the ATLAS Insertable b-Layer Project

    CERN Document Server

    George, Matthias; Quadt, Arnulf

    During the current long machine shutdown of the Large Hadron Collider (LHC) at CERN (Geneva), the innermost part of the ATLAS experiment, the pixel detector, is upgraded. The existing ATLAS pixel system is equipped with silicon sensors, organized in three barrel layers and three end cap disks on either side. To cope with the higher instantaneous luminosity in the future and for compensation of radiation damages due to past and near future running time of the experiment, a new fourth pixel detector layer is inserted into the existing system. This additional pixel layer is called “Insertable b-Layer” (IBL). The IBL is a detector system, based on silicon pixel sensors. Due to the smaller radius, compared to all other detectors of the ATLAS experiment, it has to be more radiation tolerant, than e.g. the current pixel layers. Furthermore, a reduced pixel size is necessary to cope with the expected higher particle flux. During the planning phase for the IBL upgrade, three different sensor technologies were comp...

  4. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Viel, Simon; Banerjee, Swagato; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian; Wu, Sau Lan; Yang, Hongtao

    2016-09-01

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN.

  5. Simulations of planar pixel sensors for the ATLAS high luminosity upgrade

    OpenAIRE

    Calderini, G.; Benoit, M; Dinu, N.; Lounis, A.; Marchiori, G.

    2011-01-01

    A physics-based device simulation was used to study the charge carrier distribution and the electric field configuration inside simplified two-dimensional models for pixel layouts based on the ATLAS pixel sensor. In order to study the behavior of such detectors under different levels of irradiation, a three-level defect model was implemented into the simulation. Using these models, the number of guard rings, the dead edge width and the detector thickness were modified to investigate their inf...

  6. Commissioning of the read-out driver (ROD) card for the ATLAS IBL detector and upgrade studies for the pixel Layers 1 and 2

    Energy Technology Data Exchange (ETDEWEB)

    Balbi, G.; Bindi, M. [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Falchieri, D. [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Department of Physics and Astronomy, University of Bologna (Italy); Gabrielli, A., E-mail: alessandro.gabrielli@bo.infn.it [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Department of Physics and Astronomy, University of Bologna (Italy); Travaglini, R. [Istituto Nazionale di Fisica Nucleare (INFN), Bologna (Italy); Chen, S.-P.; Hsu, S.-C.; Hauck, S. [University of Washington, Seattle (United States); Kugel, A. [ZITI – Institute for Computer Engineering, University of Heidelberg at Mannheim (Germany)

    2014-11-21

    The higher luminosity that is expected for the LHC after future upgrades will require better performance by the data acquisition system, especially in terms of throughput. In particular, during the first shutdown of the LHC collider in 2013/14, the ATLAS Pixel Detector will be equipped with a fourth layer – the Insertable B-Layer or IBL – located at a radius smaller than the present three layers. Consequently, a new front end ASIC (FE-I4) was designed as well as a new off-detector chain. The latter is composed mainly of two 9U-VME cards called the Back-Of-Crate (BOC) and Read-Out Driver (ROD). The ROD is used for data and event formatting and for configuration and control of the overall read-out electronics. After some prototyping samples were completed, a pre-production batch of 5 ROD cards was delivered with the final layout. Actual production of another 15 ROD cards is ongoing in Fall 2013, and commissioning is scheduled in 2014. Altogether 14 cards are necessary for the 14 staves of the IBL detector, one additional card is required by the Diamond Beam Monitor (DBM), and additional spare ROD cards will be produced for a total of 20 boards. This paper describes some integration tests that were performed and our plan to test the production of the ROD cards. Slices of the IBL read-out chain have been instrumented, and ROD performance is verified on a test bench mimicking a small-sized final setup. This contribution will report also one view on the possible adoption of the IBL ROD for ATLAS Pixel Detector Layer 2 (firstly) and, possibly, in the future, for Layer 1.

  7. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other devices such as representations of users......This paper addresses Front End Innovation as an object for the management and staging of innovation processes. We examine the role which devices play in the managing of Front End Innovation, with inspiration from Science and Technology Studies (STS). The paper contributes to a new understanding...... and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The paper examines...

  8. Commissioning and Operation of the ATLAS Pixel Detector at the CERN LHC Collider

    CERN Document Server

    Djama, F; The ATLAS collaboration

    2010-01-01

    Physics program at the CERN LHC collider started in autumn 2009. Since then, LHC daily delivers collisions between its two proton beams. This talk was devoted to the commissioning and early operation of the ATLAS Pixel Detector. The Pixel Detector is working nicely and all the required performances like efficiency, resolution and low noise were met. The fraction of working modules is as high as 97.4 %. The Pixel Detector fully participates in the reconstruction of charged particles trajectories, and is a key element in finding primary and secondary verticies and in tagging of short-lived particles.

  9. Optical Readout in a Multi-Module System Test for the ATLAS Pixel Detector

    CERN Document Server

    Flick, T; Gerlach, P; Kersten, S; Mättig, P; Kirichu, S N; Reeves, K; Richter, J; Schultes, J; Flick, Tobias; Becks, Karl-Heinz; Gerlach, Peter; Kersten, Susanne; Maettig, Peter; Kirichu, Simon Nderitu; Reeves, Kendall; Richter, Jennifer; Schultes, Joachim

    2006-01-01

    The innermost part of the ATLAS experiment at the LHC, CERN, will be a pixel detector. The command messages and the readout data of the detector are transmitted over an optical data path. The readout chain consists of many components which are produced at several locations around the world, and must work together in the pixel detector. To verify that these parts are working together as expected a system test has been built up. In this paper the system test setup and the operation of the readout chain is described. Also, some results of tests using the final pixel detector readout chain are given.

  10. HINS Linac front end focusing system R&D

    Energy Technology Data Exchange (ETDEWEB)

    Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

    2008-08-01

    This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

  11. The front-end electronics for LHCb calorimeters

    CERN Document Server

    Beigbeder-Beau, C; Breton, D; Cacéres, T; Callot, O; Cros, P; Delcourt, B; De Vivie de Régie, J B; Falleau, I; Hrisoho, A; Jeanmarie, B; Lefrançois, J; Tocut, V; Truong, K D; Videau, I

    2000-01-01

    The electronics for the electromagnetic and hadronic calorimeters of LHCb is under design. The 32 channel-9U front-end board offers the complete front-end and readout electronics for every channel including original shaping, 12bit-40MHz ADC, digital filtering and latency for level 0 and level 1 triggers. The clipped PM input signal is integrated during 25ns, but also delayed then subtracted to itself 25ns later which allows performant pile up independence. This board also includes the first processing levels of the L0 calorimeter trigger. A 16 channel-6U prototype board has been designed and used at CERN in test beam in 1999.

  12. CMOS front-end electronics for radiation sensors

    CERN Document Server

    Rivetti, Angelo

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  13. Studies for the detector control system of the ATLAS pixel at the HL-LHC

    International Nuclear Information System (INIS)

    In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

  14. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  15. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    Dobos, Daniel; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. An overview of the refurbishing of the Pixel Detector and of the IBL project as well as early performance tests using cosmic rays and beam data will be presented.

  16. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    Science.gov (United States)

    Dobos, Daniel

    2016-07-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to the surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer, a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. An overview of the refurbishing of the Pixel Detector and of the IBL project as well as early performance tests using cosmic rays and beam data will be presented.

  17. Operational Performance and Status of the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Jentzsch, J; The ATLAS collaboration

    2014-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experi- ment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individu- ally read out via chips bump-bonded to 1744 n+-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including moni- toring, calibration procedures, timing optimization and detector performance. The record breaking instantaneous luminosities of 7.7 · 1033 cm−2s−1 recently surpassed at the Large Hadron Collider generate a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulates, the first effects of radiation damage are now observable in the silicon sensors. A regular monitoring program has been conducted and reveals an increase in the silico...

  18. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    During Run-1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This includes the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore a new readout chip and two new sensor technologies (planar and 3D) are used in IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanic...

  19. Novel Silicon n-in-p Pixel Sensors for the future ATLAS Upgrades

    CERN Document Server

    La Rosa, A; Macchiolo, A; Nisius, R; Pernegger, H; Richter,R H; Weigell, P

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the Inner Detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost eectiveness, that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 1016 1-MeV $n_{eq}cm^{-2}$, and prove the operability of this kind of sensors in the harsh radiation environment foreseen for the pixel system at HL-LHC. We also present an overview of the new pixel production, which is on-going at CiS for sensors compatible with the new ATLAS readout chip FE-I4.

  20. Novel silicon n-in-p pixel sensors for the future ATLAS upgrades

    Science.gov (United States)

    La Rosa, A.; Gallrapp, C.; Macchiolo, A.; Nisius, R.; Pernegger, H.; Richter, R. H.; Weigell, P.

    2013-08-01

    In view of the LHC upgrade phases towards HL-LHC the ATLAS experiment plans to upgrade the inner detector with an all silicon system. The n-in-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness that allow for enlarging the area instrumented with pixel detectors. We present the characterization and performance of novel n-in-p planar pixel sensors produced by CiS (Germany) connected by bump bonding to the ATLAS readout chip FE-I3. These results are obtained before and after irradiation up to a fluence of 10161-MeV neq cm-2, and prove the operability of this kind of sensors in the harsh radiation environment foreseen for the pixel system at HL-LHC. We also present an overview of the new pixel production, which is on-going at CiS for sensors compatible with the new ATLAS readout chip FE-I4.

  1. Smart front-ends, from vision to design

    NARCIS (Netherlands)

    Roermund, H.M. van; Baltus, P.; Bezooijen, A. van; Hegt, J.A.; Lopelli, E.; Mahmoudi, R.; Radulov, G.I.; Vidojkovic, M.

    2009-01-01

    An integral multi-disciplinary chain optimization based on a high-level cascaded Shannon-based channel modeling is proposed. It is argued that the analog part of the front-end (FE) will become a bottleneck in the overall chain. This requires a FE-centric design approach, aiming for maximizing the ef

  2. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  3. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  4. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  5. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  6. Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Libov, Vladyslav

    2013-08-15

    measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

  7. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    CERN Document Server

    Savic, N; Breuer, J; La Rosa, A; Macchiolo, A; Nisius, R; Terzo, S

    2016-01-01

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 um. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 um and a novel design with the optimized biasing structure and small pixel cells (50 um x 50 um and 25 um x 100 um). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represen...

  8. Study of planar pixel sensors hardener to radiations for the upgrade of the ATLAS vertex detector

    International Nuclear Information System (INIS)

    In this work, we present a study, using TCAD (Technology Computer-Assisted Design) simulation, of the possible methods of designing planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure, a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain the high charge collection observed in highly irradiated devices. A simple planar pixel sensor digitization model to be used in test beam and full detector system is detailed. It allows for easy comparison between experimental data and prediction by the various radiation damage models available. The digitizer has been validated using test beam data for unirradiated sensors and can be used to produce the first full scale simulation of the ATLAS detector with the IBL that include sensor effects such as slim edge and thinning of the sensor. (author)

  9. Operational Experience of the ATLAS SemiConductor Tracker and Pixel Detector

    CERN Document Server

    Robinson, Dave; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  10. ATLAS Pixel IBL Modules Construction Experience and Developments for Future Upgrade

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2015-01-01

    The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), just installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, were used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

  11. ATLAS Pixel IBL modules construction experience and developments for future upgrade

    CERN Document Server

    Gaudiello, A; The ATLAS collaboration

    2014-01-01

    The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), just installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, were used, connected with the new generation 130nm IBM CMOS FE-I4 readout chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

  12. ATLAS pixel IBL modules construction experience and developments for future upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gaudiello, A.

    2015-10-01

    The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, are used. Sensors are connected with the new generation 130 nm IBM CMOS FE-I4 read-out chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

  13. The Pixel Detector of the ATLAS Experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO$_2$ based cooling system have been adopted. The IBL construction and installation in the ATLAS Experiment has been completed very successfu...

  14. Sensor studies of n+-in-n planar pixel sensors for the ATLAS upgrades

    International Nuclear Information System (INIS)

    The ATLAS experiment at the LHC is planning upgrades of its pixel detector to cope with the luminosity increase foreseen in the coming years within the transition from LHC to Super-LHC (SLHC/HL-LHC). Associated with an increase in instantaneous luminosity is a rise of the target integrated luminosity from 730 fb-1 to about 3000 fb-1 which directly translates into significantly higher radiation damage. These upgrades consist of the installation of a 4th pixel layer, the insertable b-layer IBL, with a mean sensor radius of only 32 mm from the beam axis, before 2016/17. In addition, the complete pixel detector will be exchanged before 2020/21. Being very close to the beam, the radiation damage of the IBL sensors might be as high as 5.1015neqcm-2 at their end-of-life. The total fluence of the innermost pixel layer after the SLHC upgrade might even reach 2.1016neqcm-2. We have performed systematic measurements of planar pixel detectors based on the current ATLAS readout chip FE-I3 and obtained first experience with the new IBL readout chip FE-I4. First results will be presented.

  15. A Leakage Current-based Measurement of the Radiation Damage in the ATLAS Pixel Detector

    CERN Document Server

    Gorelov, Igor; The ATLAS collaboration

    2015-01-01

    A measurement has been made of the radiation damage incurred by the ATLAS Pixel Detector barrel silicon modules from the beginning of operations through the end of 2012. This translates to hadronic fluence received over the full period of operation at energies up to and including 8 TeV. The measurement is based on a per-module measurement of the silicon sensor leakage current. The results are presented as a function of integrated luminosity and compared to predictions by the Hamburg Model. This information can be used to predict limits on the lifetime of the Pixel Detector due to current, for various operating scenarios.

  16. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  17. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  18. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  19. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E.

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  20. Broadband RF front-end using microwave photonics filter.

    Science.gov (United States)

    Wang, Jingjing; Chen, Minghua; Liang, Yunhua; Chen, Hongwei; Yang, Sigang; Xie, Shizhong

    2015-01-26

    We propose and demonstrate a novel RF front-end with broadened processing bandwidth, where a tunable microwave photonic filter based on optical frequency comb (OFC) is incorporated to accomplish simultaneous down-conversion and filtering. By designing additional phase shaping and time delay controlling, the frequency tunability of the system could be enhanced. More importantly, the beating interferences generated from broadband RF input could also be suppressed, which help to break the limitation on the processing bandwidth. In our experiments, a photonics RF receiver front-end for RF input with wide bandwidth of almost 20 GHz was realized using 10-GHz-space OFC, where the center frequency of the pass band signals could be tuned continuously. PMID:25835844

  1. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit ...

  2. Enabling Front End of Innovation in a Mature Development Company

    DEFF Research Database (Denmark)

    Brønnum, Louise; Clausen, Christian

    2015-01-01

    Many mature development organizations find it difficult to handle radical and incremental innovations within the same organizational structures. We examine how organizational structures, management, development mindsets and cultures represent a constitution of development for the thinking...... in staging new temporary development spaces framing for alternative Front End of Innovation opportunities in a mature development organization. The analysis indicates that it is important to know of the implicit and explicit rules of the constitution of development as these are re-enacted and points...

  3. Studies for the detector control system of the ATLAS pixel at the HL-LHC

    CERN Document Server

    Püllen, L; Boek, J; Kersten, S; Kind, P; Mättig, P; Zeitnitz, C

    2012-01-01

    experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

  4. The Pixels find their way to the heart of ATLAS

    CERN Multimedia

    Kevin Einsweiler

    Since the last e-news article on the Pixel Detector in December 2006, there has been much progress. At that time, we were just about to receive the Beryllium beampipe, and to integrate the innermost layer of the Pixel Detector around it. This innermost layer is referred to as the B-layer because of the powerful role it plays in finding the secondary vertices that are the key signature for the presence of b-quarks, and with somewhat greater difficulty, c-quarks and tau leptons. The integration of the central 7m long beampipe into the Pixel Detector was completed in December, and the B-layer was successfully integrated around it. In January this year, we had largely completed the central 1.5m long detector, including the three barrel layers and the three disk layers on each end of the barrel. Although this region contains all of the 80 million readout channels, it cannot be integrated into the Inner Detector without additional services and infrastructure. Therefore, the next step was to add the Service Panels...

  5. The control system for the CMS tracker front-end

    CERN Document Server

    Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

    2002-01-01

    The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

  6. Holographic Optical Receiver Front End for Wireless Infrared Indoor Communications

    Science.gov (United States)

    Jivkova, S.; Kavehrad, M.

    2001-06-01

    Multispot diffuse configuration (MSDC) for indoor wireless optical communications, utilizing multibeam transmitter and angle diversity detection, is one of the most promising ways of achieving high capacities for use in high-bandwidth islands such as classrooms, hotel lobbies, shopping malls, and train stations. Typically, the optical front end of the receiver consists of an optical concentrator to increase the received optical signal power and an optical bandpass filter to reject the ambient light. Using the unique properties of holographic optical elements (HOE), we propose a novel design for the receiver optical subsystem used in MSDC. With a holographic curved mirror as an optical front end, the receiver would achieve more than an 10-dB improvement in the electrical signal-to-noise ratio compared with a bare photodetector. Features such as multifunctionality of the HOE and the receiver s small size, light weight, and low cost make the receiver front end a promising candidate for a user s portable equipment in broadband indoor wireless multimedia access.

  7. A Life Cycle Assessment of a Magnesium Automotive Front End

    Energy Technology Data Exchange (ETDEWEB)

    Das, Sujit [ORNL; Dubreuil, Alain [Natural Resources Canada; Bushi, Lindita [GreenhouseGasMeasurement.com; Tharumarajah, Ambalavanar [CSIRO/CAST-CRC

    2009-01-01

    The Magnesium Front End Research and Development (MFERD) project under the sponsorship of Canada, China and USA aims to develop key technologies and a knowledge base for increased use of magnesium in automobile. The goal of this life cycle assessment (LCA) study is to compare the energy and potential environmental impacts of advanced magnesium based front end parts of a North America built 2007 GM-Cadillac CTS with the standard carbon steel based design. This LCA uses the 'cradle-to-grave' approach by including primary material production, semi-fabrication production, autoparts manufacturing and assembly, transportation, use phase and end-of-life processing of autoparts. This LCA study was done in compliance with international standards ISO 14040:2006 and ISO 14044:2006. Furthermore, the LCA results for aluminum based front end autopart are presented. While weight savings result in reductions in energy use and carbon dioxide emissions during the use of the car, the impacts of fabrication and recycling of lightweight materials are substantial in regard to steel. Pathways for improving sustainability of magnesium use in automobiles through material management and technology improvements including recycling are also discussed.

  8. Radiation-Hard Opto-Link for the Atlas Pixel Detector

    OpenAIRE

    Gan, K. K.

    2004-01-01

    The on-detector optical link of the ATLAS pixel detector contains radiation-hard receiver chips to decode bi-phase marked signals received on PIN arrays and data transmitter chips to drive VCSEL arrays. The components are mounted on hybrid boards (opto-boards). We present results from the opto-boards and from irradiation studies with 24 GeV protons up to 33 Mrad (1.2 x 10^15 p/cm^2).

  9. Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Macchiolo, A.; Nisius, R.; Savic, N.; Terzo, S.

    2016-09-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14 ×1015 neq /cm2 . The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.

  10. The Layer 1 / Layer 2 readout upgrade for the ATLAS Pixel Detector

    CERN Document Server

    Mullier, Geoffrey; The ATLAS collaboration

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC). The increase of instantaneous luminosity foreseen during the LHC Run 2, will lead to an increased detector occupancy that is expected to saturate the readout links of the outermost layers of the pixel detector: Layers 1 and 2. To ensure a smooth data taking under such conditions, the read out system of the recently installed fourth innermost pixel layer, the Insertable B-Layer, was modified to accomodate the needs of the older detector. The Layer 2 upgrade installation took place during the 2015 winter shutdown, with the Layer 1 installation scheduled for 2016. A report of the successful installation, together with the design of novel dedicated optical to electrical converters and the software and firmware updates will be presented.

  11. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Takubo, Y; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair the modules and to ease installation of the Insertable B-Layer (IBL). The IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using light weight staves and CO$_{2}$ based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and the IBL pr...

  12. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  13. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Takubo, Yosuke

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detect or and of the IBL project as...

  14. The ATLAS Pixel Detector for Run II at the Large Hadron Collider

    CERN Document Server

    Marx, Marilyn; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  15. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Backhaus, Malte; The ATLAS collaboration

    2015-01-01

    Run-2 of the LHC will provide new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed as well as a new read-out chip within CMOS 130nm technology and with larger area, smaller pixel size and faster readout capability. The new detector is the first large scale application of of 3D detectors and CMOS 130nm technology. An overview of the lessons learned during the IBL project will be presented, focusing on the challenges and highlighting the issues met during the productio...

  16. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2

    CERN Document Server

    Ferrere, Didier; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  17. The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

    CERN Document Server

    Giordani, MarioPaolo; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  18. The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

    International Nuclear Information System (INIS)

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC) . Taking advantage of Long Shutdown 1 (LS1) during 2014/2015, the Pixel Detector was brought to surface to equip it with new service panels and to repair modules. The Insertable B-Layer (IBL), a fourth layer of pixel sensors, was installed in-between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) were used and a new readout chip has been designed with CMOS 130 nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical performance. An overview of the lessons learned during the IBL project is presented, focusing on the challenges and highlighting the issues met during the production, integration, installation and commissioning phases of the detector. Early performance tests using cosmic and beam data are also presented

  19. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  20. Commissioning of the upgraded ATLAS Pixel Detector for Run2 at LHC

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as ...

  1. Front-end electronics for the FAZIA experiment

    International Nuclear Information System (INIS)

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics

  2. Wideband monolithically integrated front-end subsystems and components

    Science.gov (United States)

    Mruk, Joseph Rene

    This thesis presents the analysis, design, and measurements of passive, monolithically integrated, wideband recta-coax and printed circuit board front-end components. Monolithic fabrication of antennas, impedance transformers, filters, and transitions lowers manufacturing costs by reducing assembly time and enhances performance by removing connectors and cabling between the devices. Computational design, fabrication, and measurements are used to demonstrate the capabilities of these front-end assemblies. Two-arm wideband planar log-periodic antennas fed using a horizontal feed that allows for filters and impedance transformers to be readily fabricated within the radiating region of the antenna are demonstrated. At microwave frequencies, low-cost printed circuit board processes are typically used to produce planar devices. A 1.8 to 11 GHz two-arm planar log-periodic antenna is designed with a monolithically integrated impedance transformer. Band rejection methods based on modifying the antenna aperture, use of an integrated filter, and the application of both methods are investigated with realized gain suppressions of over 25 dB achieved. The ability of standard circuit board technology to fabricate millimeter-wave devices up to 110 GHz is severely limited. Thin dielectrics are required to prevent the excitation of higher order modes in the microstrip substrate. Fabricating the thin line widths required for the antenna aperture also becomes prohibitively challenging. Surface micro-machining typically used in the fabrication of MEMS devices is capable of producing the extremely small features that can be used to fabricate antennas extending through W-band. A directly RF fed 18 to 110 GHz planar log-periodic antenna is developed. The antenna is fabricated with an integrated impedance transformer and additional transitions for measurement characterization. Singly terminated low-loss wideband millimeter-wave filters operating over V- and W- band are developed. High

  3. Front-end electronics for the FAZIA experiment

    Science.gov (United States)

    Salomon, F.; Edelbruck, P.; Brulin, G.; Borderie, B.; Richard, A.; Rivet, M. F.; Verde, G.; Wanlin, E.; Boiano, A.; Tortone, G.; Poggi, G.; Bini, M.; Casini, G.; Barlini, S.; Pasquali, G.; Valdré, S.; Petcu, M.; Bougault, R.; Le Neindre, N.; Alba, R.; Bonnet, E.; Bruno, M.; Chbihi, A.; Cinausero, M.; Dell'Aquila, D.; De Préaumont, H.; Duenas, J. A.; Fable, Q.; Fabris, D.; Francalanza, L.; Frankland, J. D.; Galichet, E.; Gramegna, F.; Gruyer, D.; Guerzoni, M.; Kordyasz, A.; Kozik, T.; La Torre, R.; Lombardo, I.; Lopez, O.; Mabiala, J.; Maiolino, C.; Marchi, T.; Maurenzig, P.; Meoli, A.; Merrer, Y.; Morelli, L.; Nannini, A.; Olmi, A.; Ordine, A.; Pârlog, M.; Pastore, G.; Piantelli, S.; Rosato, E.; Santonocito, D.; Scarlini, E.; Spadacini, G.; Stefaninni, A.; Vient, E.; Vigilante, M.

    2016-01-01

    FAZIA is a multidetector specifically designed to optimize A and Z reaction product identification in heavy-ion collision experiments. This multidetector is modular and based on three-layer telescopes made of two silicon detectors followed by a thick (10 cm) CsI(Tl) scintillator read-out by a photodiode. Its electronics is fully digital. The goal to push at maximum identification capability while preserving excellent energy resolution, can be achieved by using pulse-shape analysis techniques and by making an intensive use of high-speed flash ADCs. This paper presents the front-end part of the electronics.

  4. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  5. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  6. TCAD Simulations of ATLAS Pixel Guard Ring and Edge Structure for SLHC Upgrade

    CERN Document Server

    Lounis, A; The ATLAS collaboration; Calderini, G; Marchiori, G; Benoit, M; Dinu, N

    2010-01-01

    In this work, the magnitude of the electric field and the depletion inside a simplified two dimensional model of the ATLAS planar pixel sensor for the insertable b-layer and the super-LHC upgrade have been studied. The parameters influencing the breakdown behavior were studied using a finite-element method to solve the drift-diffusion equations coupled to Poisson's equation. Using these models, the number of guard rings, dead edge width and sensor's thickness were modified with respect to the ATLAS actual pixel sensor to investigate their influence on the sensor's depletion at the edge and on its internal electrical field distribution. The goal of the simulation is to establish a model to discriminate between different designs and to select the most optimized to fit the needs in radiation hardness and low material budget of ATLAS inner detector during super-LHC operation. A three defects level model has been implemented in the simulations to study the behavior of such sensors under different level of irradiat...

  7. Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

    2015-07-01

    The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

  8. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    International Nuclear Information System (INIS)

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

  9. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  10. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  11. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  12. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  13. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  14. The Pixel Detector of the ATLAS Experiment for LHC Run-2

    CERN Document Server

    Pernegger, Heinz; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and hit occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. An overview of the refurbishing of the Pixel Detector and of the IBL project as we...

  15. The upgraded Pixel Detector of the ATLAS Experiment for Run2 at the Large Hadron Collider

    CERN Document Server

    Mullier, Geoffrey Andre; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL), a fourth layer of pixel detectors, installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been developed. A new readout chip has been developed within CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical performan...

  16. Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

    CERN Document Server

    Macchiolo, Anna; Savic, Natascha; Terzo, Stefano

    2016-01-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region...

  17. Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

    CERN Document Server

    Macchiolo, A.; Savic, N.; Terzo, S.

    2016-01-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100–200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14×1015 neq/cm2. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. F...

  18. Recent Results of the ATLAS Upgrade Planar Pixel Sensors R&D Project

    CERN Document Server

    Weigell, Philipp

    2013-01-01

    To cope with the higher occupancy and radiation damage at the HL-LHC also the LHC experiments will be upgraded. The ATLAS Planar Pixel Sensor R&D Project (PPS) is an international collaboration of 17 institutions and more than 80 scientists, exploring the feasibility of employing planar pixel sensors for this scenario. Depending on the radius, different pixel concepts are investigated using laboratory and beam test measurements. At small radii the extreme radiation environment and strong space constraints are addressed with very thin pixel sensors active thickness in the range of (75-150) mum, and the development of slim as well as active edges. At larger radii the main challenge is the cost reduction to allow for instrumenting the large area of (7-10) m^2. To reach this goal the pixel productions are being transferred to 6 inch production lines. Additionally, investigated are more cost-efficient and industrialised interconnection techniques as well as the n-in-p technology, which, being a single-sided pr...

  19. The Pixel Detector of the ATLAS experiment for the Run 2 at the Large Hadron Collider

    CERN Document Server

    Oide, H; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run 1 of LHC. Taking advantage of the long shutdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). The IBL is the fourth layer of the Run 2 Pixel Detector, and it was installed in May 2014 between the existing Pixel Detector and the new smaller-radius beam pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project...

  20. High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

    Energy Technology Data Exchange (ETDEWEB)

    Backhaus, Malte

    2014-01-15

    The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the socalled Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosity increase in the shutdown of 2022 and 2023. The final chapter of this thesis introduces a new module concept that uses an industrial high voltage CMOS technology as sensor layer, which is capacitively coupled to the FE-I4 readout chip.

  1. 3D silicon pixel detectors for the ATLAS Forward Physics experiment

    CERN Document Server

    Lange, Jörn; Grinstein, Sebastian; Paz, Ivan Lopez

    2015-01-01

    The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2-3 mm). This implies the need of slim edges of about 100-200 $\\mu$m width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 $\\mu$m width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 10$^{15}$ n$_{eq}$/cm$^2$ with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al ma...

  2. SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades

    CERN Document Server

    Macchiolo, A; Moser, H G; Nisius, R; Richter, R H; Weigell, P

    2012-01-01

    We present the results of the characterization of pixel modules composed of 75 μm thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is explored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module, ICVs are etched over the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation is presented.

  3. High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

    CERN Document Server

    Backhaus, Malte

    2014-02-19

    The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the so-called Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosi...

  4. Simulations of planar pixel sensors for the ATLAS high luminosity upgrade

    CERN Document Server

    Calderini, G; Dinu, N; Lounis, A; Marchiori, G

    2011-01-01

    A physics-based device simulation was used to study the charge carrier distribution and the electric field configuration inside simplified two-dimensional models for pixel layouts based on the ATLAS pixel sensor. In order to study the behavior of such detectors under different levels of irradiation, a three-level defect model was implemented into the simulation. Using these models, the number of guard rings, the dead edge width and the detector thickness were modified to investigate their influence on the detector depletion at the edge and on its internal electric field distribution in order to optimize the layout parameters. Simulations indicate that the number of guard rings can be reduced by a few hundred microns with respect to the layout used for the present ATLAS sensors, with a corresponding extension of the active area of the sensors. A study of the inter-pixel capacitance and of the capacitance between the implants and the high-voltage contact as a function of several parameters affecting the geometr...

  5. High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

    International Nuclear Information System (INIS)

    The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the socalled Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosity increase in the shutdown of 2022 and 2023. The final chapter of this thesis introduces a new module concept that uses an industrial high voltage CMOS technology as sensor layer, which is capacitively coupled to the FE-I4 readout chip.

  6. Charge-Sensitive Front-End Electronics with Operational Amplifiers for CdZnTe Detectors

    CERN Document Server

    Födisch, P; Lange, B; Kirschke, T; Enghardt, W; Kaever, P

    2016-01-01

    Cadmium zinc telluride (CdZnTe, "CZT") radiation detectors are announced to be a game-changing detector technology. However, state-of-the-art detector systems require high-performance readout electronics as well. Even though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, our demands on a high dynamic range for energy measurement and a high throughput are not served by any commercially available circuit. Consequently, we had to develop the analog front-end electronics with operational amplifiers for an 8x8 pixelated CZT detector. For this purpose, we model an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Therefore, we present the mathematical equations for a detailed network analysis. Additionally, we enhance the design with numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, noise level and verify the performance with synthetic detector signals. With this benchm...

  7. FEC-CCS A common Front-End Controller card for the CMS detector electronics

    CERN Document Server

    Kloukinas, Kostas; Drouhin, F; Ljuslin, C; Marchioro, A; Murer, E; Paillard, C; Vlasov, E

    2007-01-01

    The FEC-CCS is a custom made 9U VME64x card for the CMS Off-Detector electronics. The FEC-CCS card is responsible for distributing the fast timing signals and the slow control data, through optical links, to the Front-End system. Special effort has been invested in the design of the card in order to make it compatible with the operational requirements of multiple CMS detectors namely the Tracker, ECAL, Preshower, PIXELs, RPCs and TOTEM. This paper describes the design architecture of the FEC-CCS card focusing on the special design features that enable the common utilization by most of the CMS detectors. Results from the integration tests with the detector electronics subsystems and performance measurements will be reported. The design of a custom made testbench for the production testing of the 150 cards produced will be presented and the attained yield will be reported.

  8. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end process vent or aggregate batch vent stream at an affected source shall submit the information...

  9. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... assumes that the batch unit operation is operating at the maximum design capacity of the EPPU for 12... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process...

  10. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  11. A neural network clustering algorithm for the ATLAS silicon pixel detector

    CERN Document Server

    Aad, Georges; Abdallah, Jalal; Abdel Khalek, Samah; Abdinov, Ovsat; Aben, Rosemarie; Abi, Babak; Abolins, Maris; AbouZeid, Ossama; Abramowicz, Halina; Abreu, Henso; Abreu, Ricardo; Abulaiti, Yiming; Acharya, Bobby Samir; Adamczyk, Leszek; Adams, David; Adelman, Jahred; Adomeit, Stefanie; Adye, Tim; Agatonovic-Jovin, Tatjana; Aguilar-Saavedra, Juan Antonio; Agustoni, Marco; Ahlen, Steven; Ahmadov, Faig; Aielli, Giulio; Akerstedt, Henrik; Åkesson, Torsten Paul Ake; Akimoto, Ginga; Akimov, Andrei; Alberghi, Gian Luigi; Albert, Justin; Albrand, Solveig; Alconada Verzini, Maria Josefina; Aleksa, Martin; Aleksandrov, Igor; Alexa, Calin; Alexander, Gideon; Alexandre, Gauthier; Alexopoulos, Theodoros; Alhroob, Muhammad; Alimonti, Gianluca; Alio, Lion; Alison, John; Allbrooke, Benedict; Allison, Lee John; Allport, Phillip; Almond, John; Aloisio, Alberto; Alonso, Alejandro; Alonso, Francisco; Alpigiani, Cristiano; Altheimer, Andrew David; Alvarez Gonzalez, Barbara; Alviggi, Mariagrazia; Amako, Katsuya; Amaral Coutinho, Yara; Amelung, Christoph; Amidei, Dante; Amor Dos Santos, Susana Patricia; Amorim, Antonio; Amoroso, Simone; Amram, Nir; Amundsen, Glenn; Anastopoulos, Christos; Ancu, Lucian Stefan; Andari, Nansi; Andeen, Timothy; Anders, Christoph Falk; Anders, Gabriel; Anderson, Kelby; Andreazza, Attilio; Andrei, George Victor; Anduaga, Xabier; Angelidakis, Stylianos; Angelozzi, Ivan; Anger, Philipp; Angerami, Aaron; Anghinolfi, Francis; Anisenkov, Alexey; Anjos, Nuno; Annovi, Alberto; Antonaki, Ariadni; Antonelli, Mario; Antonov, Alexey; Antos, Jaroslav; Anulli, Fabio; Aoki, Masato; Aperio Bella, Ludovica; Apolle, Rudi; Arabidze, Giorgi; Aracena, Ignacio; Arai, Yasuo; Araque, Juan Pedro; Arce, Ayana; Arguin, Jean-Francois; Argyropoulos, Spyridon; Arik, Metin; Armbruster, Aaron James; Arnaez, Olivier; Arnal, Vanessa; Arnold, Hannah; Arratia, Miguel; Arslan, Ozan; Artamonov, Andrei; Artoni, Giacomo; Asai, Shoji; Asbah, Nedaa; Ashkenazi, Adi; Åsman, Barbro; Asquith, Lily; Assamagan, Ketevi; Astalos, Robert; Atkinson, Markus; Atlay, Naim Bora; Auerbach, Benjamin; Augsten, Kamil; Aurousseau, Mathieu; Avolio, Giuseppe; Azuelos, Georges; Azuma, Yuya; Baak, Max; Baas, Alessandra; Bacci, Cesare; Bachacou, Henri; Bachas, Konstantinos; Backes, Moritz; Backhaus, Malte; Backus Mayes, John; Badescu, Elisabeta; Bagiacchi, Paolo; Bagnaia, Paolo; Bai, Yu; Bain, Travis; Baines, John; Baker, Oliver Keith; Balek, Petr; Balli, Fabrice; Banas, Elzbieta; Banerjee, Swagato; Bannoura, Arwa A E; Bansal, Vikas; Bansil, Hardeep Singh; Barak, Liron; Baranov, Sergei; Barberio, Elisabetta Luigia; Barberis, Dario; Barbero, Marlon; Barillari, Teresa; Barisonzi, Marcello; Barklow, Timothy; Barlow, Nick; Barnett, Bruce; Barnett, Michael; Barnovska, Zuzana; Baroncelli, Antonio; Barone, Gaetano; Barr, Alan; Barreiro, Fernando; Barreiro Guimarães da Costa, João; Bartoldus, Rainer; Barton, Adam Edward; Bartos, Pavol; Bartsch, Valeria; Bassalat, Ahmed; Basye, Austin; Bates, Richard; Batkova, Lucia; Batley, Richard; Battaglia, Marco; Battistin, Michele; Bauer, Florian; Bawa, Harinder Singh; Beau, Tristan; Beauchemin, Pierre-Hugues; Beccherle, Roberto; Bechtle, Philip; Beck, Hans Peter; Becker, Anne Kathrin; Becker, Sebastian; Beckingham, Matthew; Becot, Cyril; Beddall, Andrew; Beddall, Ayda; Bedikian, Sourpouhi; Bednyakov, Vadim; Bee, Christopher; Beemster, Lars; Beermann, Thomas; Begel, Michael; Behr, Katharina; Belanger-Champagne, Camille; Bell, Paul; Bell, William; Bella, Gideon; Bellagamba, Lorenzo; Bellerive, Alain; Bellomo, Massimiliano; Belotskiy, Konstantin; Beltramello, Olga; Benary, Odette; Benchekroun, Driss; Bendtz, Katarina; Benekos, Nektarios; Benhammou, Yan; Benhar Noccioli, Eleonora; Benitez Garcia, Jorge-Armando; Benjamin, Douglas; Bensinger, James; Benslama, Kamal; Bentvelsen, Stan; Berge, David; Bergeaas Kuutmann, Elin; Berger, Nicolas; Berghaus, Frank; Beringer, Jürg; Bernard, Clare; Bernat, Pauline; Bernius, Catrin; Bernlochner, Florian Urs; Berry, Tracey; Berta, Peter; Bertella, Claudia; Bertoli, Gabriele; Bertolucci, Federico; Bertsche, David; Besana, Maria Ilaria; Besjes, Geert-Jan; Bessidskaia, Olga; Bessner, Martin Florian; Besson, Nathalie; Betancourt, Christopher; Bethke, Siegfried; Bhimji, Wahid; Bianchi, Riccardo-Maria; Bianchini, Louis; Bianco, Michele; Biebel, Otmar; Bieniek, Stephen Paul; Bierwagen, Katharina; Biesiada, Jed; Biglietti, Michela; Bilbao De Mendizabal, Javier; Bilokon, Halina; Bindi, Marcello; Binet, Sebastien; Bingul, Ahmet; Bini, Cesare; Black, Curtis; Black, James; Black, Kevin; Blackburn, Daniel

    2014-01-01

    A novel technique to identify and split clusters created by multiple charged particles in the ATLAS pixel detector using a set of artificial neural networks is presented. Such merged clusters are a common feature of tracks originating from highly energetic objects, such as jets. Neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. This technique replaces the former clustering approach based on a connected component analysis and charge interpolation. The performance of the neural network splitting technique is quantified using data from proton-proton collisions at the LHC collected by the ATLAS detector in 2011 and from Monte Carlo simulations. This technique reduces the number of clusters shared between tracks in highly energetic jets by up to a factor of three. It also provides more precise position and error estimates of the clusters in both the transverse and longitudinal impact parameter resolution.

  12. The phase-II ATLAS pixel tracker upgrade: layout and mechanics.

    CERN Document Server

    Sharma, Abhishek; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment will upgrade its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The upgraded tracker will consist of silicon-strip modules surrounding a pixel detector, and will likely cover an extended eta range, perhaps as far as |eta|<4.0. A number of layout and supporting-structure options are being considered for the pixel detector, with the final choice expected to be made in early 2017. The proposed supporting structures are based on lightweight, highly-thermally-conductive carbon-based materials and are cooled by evaporative carbon dioxide. The various layouts will be described and a description of the supporting structures will be presented, along with results from testing of prototypes.

  13. Design, production, and reliability of the new ATLAS pixel opto-boards

    International Nuclear Information System (INIS)

    New fiber optical transceivers, opto-boards, were designed and produced to replace the first generation opto-boards installed in the ATLAS pixel detector and for the new pixel layer, the insertable barrel layer (IBL). Each opto-board contains one 12-channel PIN array and two 12-channel VCSEL arrays along with associated receiver and driver ASICs. The new opto-board design benefits from the production and operational experience of the first generation opto-boards and contains several improvements. The new opto-boards have been successfully installed. Additionally, a set of the new opto-boards have been subjected to an accelerated lifetime experiment at 85 C and 85% relative humidity for over 1,000 hours. No failures were observed. We are cautiously optimistic that the new opto-boards will survive until the shutdown for the detector upgrade for the high-luminosity Large Hadron Collider (HL-LHC)

  14. Charge-sensitive front-end electronics with operational amplifiers for CdZnTe detectors

    Science.gov (United States)

    Födisch, P.; Berthel, M.; Lange, B.; Kirschke, T.; Enghardt, W.; Kaever, P.

    2016-09-01

    Cadmium zinc telluride (CdZnTe, CZT) radiation detectors are suitable for a variety of applications, due to their high spatial resolution and spectroscopic energy performance at room temperature. However, state-of-the-art detector systems require high-performance readout electronics. Though an application-specific integrated circuit (ASIC) is an adequate solution for the readout, requirements of high dynamic range and high throughput are not available in any commercial circuit. Consequently, the present study develops the analog front-end electronics with operational amplifiers for an 8×8 pixelated CZT detector. For this purpose, we modeled an electrical equivalent circuit of the CZT detector with the associated charge-sensitive amplifier (CSA). Based on a detailed network analysis, the circuit design is completed by numerical values for various features such as ballistic deficit, charge-to-voltage gain, rise time, and noise level. A verification of the performance is carried out by synthetic detector signals and a pixel detector. The experimental results with the pixel detector assembly and a 22Na radioactive source emphasize the depth dependence of the measured energy. After pulse processing with depth correction based on the fit of the weighting potential, the energy resolution is 2.2% (FWHM) for the 511 keV photopeak.

  15. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    CERN Document Server

    Boek, J; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2013-01-01

    inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University ofWuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

  16. Fact Sheet for KM200 Front-end Electronics

    Energy Technology Data Exchange (ETDEWEB)

    Ianakiev, Kiril Dimitrov [Los Alamos National Laboratory; Iliev, Metodi [Los Alamos National Laboratory; Swinhoe, Martyn Thomas [Los Alamos National Laboratory

    2015-07-08

    The KM200 device is a versatile, configurable front-end electronics boards that can be used as a functional replacement for Canberra’s JAB-01 boards based on the Amptek A-111 hybrid chip, which continues to be the preferred choice of electronics for large number of the boards in junction boxes of multiplicity counters that process the signal from an array of 3He detectors. Unlike the A-111 chip’s fixed time constants and sensitivity range, the shaping time and sensitivity of the new KM200 can be optimized for demanding applications such as spent fuel, and thus could improve the safeguards measurements of existing systems where the A-111 or PDT electronics does not perform well.

  17. Software defined radio platform with wideband tunable front end

    Directory of Open Access Journals (Sweden)

    Daniel Iancu

    2015-01-01

    Full Text Available The paper presents a Software Defined Radio (SDR development platform with wideband tunable RF (Radio Frequency front end. The platform is based on the SB3500 Multicore Multithreaded Vector Processor and it is intended to be used for a wide variety of communication protocols as: Time Division Duplexing/Frequency Division Duplexing Long Term Evolution (TDD/FDD LTE, Global Positioning System (GPS, Global System for Mobile/General Packet Radio Service (GSM/GPRS, Wireless Local Area Network (WLAN, Legacy Worldwide Interoperability for Microwave Access (WiMAX. As an example, we describe briefly the implementation of the LTE TDD/FDD communication protocol. As far as we know, this is the only LTE category 1 communication protocol entirely developed and executed in software (SW, without any hardware (HW accelerators.

  18. Performance of Front-End Readout System for PHENIX RICH

    Energy Technology Data Exchange (ETDEWEB)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-11-15

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 {micro}s per event. The design specifications and test results of the system are presented in this paper.

  19. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  20. The ALMA Front-end Archive Setup and Performance

    Science.gov (United States)

    Wicenec, A.; Chen, A.; Checcucci, A.; Jeram, B.; Meuss, H.; Persson, A.; Burgos, P.; Cirami, R.

    2010-12-01

    The ALMA front-end archive system has to capture up to 64 MB/s for a period of several days plus the data of about 100,000 monitor points from all 66 antennas and the correlators. The main science data is delivered through corba based audio/video streams and finally stored on SATA disk arrays hosted on 6 computers and controlled by 12 daemons. All data is collected by software components running on computers in the antennas and then sent through dedicated fiber links to the Array Operations Site at 5000 m and from there to the Operations Support Facility (OSF) at 3000 m elevation. The various hardware and software components have been tuned and tested to be able to meet the performance requirements. This paper describes the setup and the various components in more detail and gives results of various test runs.

  1. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  2. Pion Irradiation of the APV25 Front-end Chip

    CERN Document Server

    Friedl, M; Pernicka, Manfred

    2001-01-01

    The Compact Muon Solenoid (CMS) experiment at the Large Hadron Collider (LHC) at CERN will include a Silicon Strip Tracker covering a sensitive area of 206m2. About ten million channels will be read out by APV25 front-end chips, fabricated in the 0.25um deep submicron process. Although permanent damage is not expected within CMS radiation levels, transient Single Event Upsets (SEUs) are inevitable and affect both digital and analog circuits. Eight APV25 chips (version S1) were exposed to a high-intensity pion beam at the Paul Scherrer Institute (Villigen/CH) to study the radiation induced effects in detail. The results, which are compatible to similar measurements performed with heavy ions, are used to predict the chip error rate at CMS.

  3. Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Wittig, Tobias

    2013-05-08

    One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

  4. Recent results of the ATLAS upgrade Planar Pixel Sensors R&D project

    Science.gov (United States)

    Forshaw, Dean

    2013-12-01

    To extend the physics reach of the LHC, upgrades to the accelerator are planned which will increase the integrated annual luminosity by a factor of 5-10. This will increase the occupancy and the radiation damage of the inner trackers. To cope with the elevated occupancy, the ATLAS experiment plans to introduce an all silicon inner tracker for High Luminosity LHC (HL-LHC) operation. With silicon, the occupancy can be adjusted by using the appropriate pitch for the pixels/micro-strips. Constraints due to high radiation damage mean that only sensors with electrode configuration designed to read out the electron signal (n-in-p and n-in-n) are considered. To investigate the suitability of planar pixel sensors (PPS) for the ATLAS tracker upgrade, a dedicated R&D project was established, with 17 institutes and more than 80 scientists. The main focuses of research are the performance of planar pixel sensors after the high fluences expected during HL-LHC operation, the optimisation of the detector and module production technologies for cost reduction to enable the instrumentation of large volumes and the reduction of the inactive areas needed for electrical insulation of the sensitive region from the cut edge of the sensors. An overview of recent accomplishments of the PPS (Planar Pixel Sensors) R&D project is given. The performance in terms of charge collection and tracking efficiency, evaluated with radioactive sources in the laboratory and from beam tests, is presented. Sensors with different thicknesses (ranging from 75 to 300 μm) were irradiated to several fluences up to 2 ×1016neqcm-2 to study the effect of varying thickness on the radiation hardness. The significant progresses made towards the reduction of the edge distance are reported.

  5. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  6. The Pixel Detector of the ATLAS Experiment for the Run-2 at the Large Hadron Collider

    CERN Document Server

    Guescini, F; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radial distance of 3.3 cm from the beam axis. The realization of the IBL required the development of several new technologies and solutions in order to overcome the challenges introduced by the extreme environment and working conditions, such as the high radiation levels, the high pixel occupancy and the need of an exceptionally low material budget. Two silicon sensor technologies have been adopted for the IBL modules: planar n-in-n and 3D. Both of these are connected via bump bonding to the new generation 130 nm IBM CMOS FE-I4 ...

  7. Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

    CERN Document Server

    Savic, N; Macchiolo, A; Nisius, R

    2016-01-01

    In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023-2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more ra- diation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 {\\mu}m recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of th...

  8. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experi- ment at the Large Hadron Collider at CERN, providing high-resolution mea- surements of charged particle tracks in the high radiation environment close to the collision region. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. After three years of operation the detector performance is excellent: 96% of the pixels are opera- tional, at 3500 e threshold noise occupancy and efficiency exceed the design specification. The effect of radiation on the silicon sensor is measured and compared with model of radiation damage.

  9. Analysis methods of testbeam data of irradiated ATLAS Planar Pixel Sensors

    International Nuclear Information System (INIS)

    The ATLAS Pixel detector is the innermost subdetector of the ATLAS-Experiment at CERN. The development of new sensor technologies is going on as detector-upgrades are foreseen to cope with higher fluences and more pile-up-events after accelerator upgrades (SLHC). For testing properties of sensors, testbeams are used. Beam-telescopes such as the EUDET-Telescope have been used for measuring the exact position of beam-tracks to determine the properties of different sensor technologies. Several sensors with different designs (e.g. slim edges) were read-out in testbeam after irradiation at differing fluences (up to 2.1016 neqcm-2) and voltages (up to 1500 V) to observe the performance of the sensors under conditions up to the end-lifetime of the ATLAS detector. The reconstruction chain of the so called Eutelescope framework including adaptions and the evaluation of the reconstructed data are presented. Typical results including hit- and charge-efficiency plots are shown and interpreted.

  10. 3D silicon pixel detectors for the ATLAS Forward Physics experiment

    International Nuclear Information System (INIS)

    The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2–3 mm). This implies the need of slim edges of about 100–200 μm width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 μm width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 1015 neq/cm2 with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al masks. The efficiency in the irradiated region is found to be similar to the one in the non-irradiated region and exceeds 97% in case of favourable chip-parameter settings. Only in a narrow transition area at the edge of the hole in the Al mask, a significantly lower efficiency is seen. A follow-up study of this effect using arrays of small pad diodes for position-resolved dosimetry via the leakage current is carried out

  11. Photodetectors and front-end electronics for the LHCb RICH upgrade

    CERN Document Server

    Cassina, L

    2016-01-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2 to 100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8$\\times$8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate ($\\sim$50 Hz/cm$^2$) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 $\\mu$m CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (\\hbox{$\\sim$1 mW/Ch}),...

  12. System test and noise performance studies at the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Weingarten, J.

    2007-09-15

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  13. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Gabrielli, Alessandro; The ATLAS collaboration; Balbi, Gabriele; Bindi, Marcello; Chen, Shaw-pin; Falchieri, Davide; Flick, Tobias; Hauck, Scott Alan; Hsu, Shih-Chieh; Kretz, Moritz; Kugel, Andreas; Lama, Luca; Travaglini, Riccardo; Wensing, Marius; ATLAS Pixel Collaboration

    2015-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data pat...

  14. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Balbi, G; The ATLAS collaboration; Gabrielli, A; Lama, L; Travaglini, R; Backhaus, M; Bindi, M; Chen, S-P; Flick, T; Kretz, M; Kugel, A; Wensing, M

    2014-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development was three-fold: keeping as much of the PixelROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path im...

  15. System test and noise performance studies at the ATLAS pixel detector

    International Nuclear Information System (INIS)

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  16. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  17. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  18. Front End CAMAC Controller for SLAC Control System

    CERN Document Server

    Browne, M J; Siskind, E J

    2001-01-01

    Most of the devices in the SLAC control system are accessed via interface modules in ~450 CAMAC crates. Low-cost controllers in these crates communicate via a SLAC-proprietary bit-serial protocol with 77 satellite control computers ("micros") within the accelerator complex. A proposed upgrade replaces the existing Multibus-I implementation of the micro hardware with commercial-off-the-shelf ("COTS") personal computers. For increased reliability and ease of maintenance, these micros will move from their current electrically noisy and environmentally challenging sites to the control center's computer room, with only a stand-alone portion of each micro's CAMAC interface remaining in the micro's original location. This paper describes the hardware/software architecture of that intelligent front-end CAMAC controller and the accompanying fiber optic link board that connects it to the PC-based micro's PCI bus. Emphasis is placed on the hardware/software techniques employed to minimize real-time latency for pulse-to-...

  19. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  20. Front-end electronics for the Muon Portal project

    Science.gov (United States)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M. C.; Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D. G.; Fallica, G.; Valvo, G.

    2016-10-01

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  1. Studio di un algoritmo lineare di ricostruzione analogica della posizione per il rivelatore a pixel di ATLAS

    CERN Document Server

    Arelli-Maffioli, A; Troncon, C; Lari, T

    2007-01-01

    A detailed study of spatial resolution of Atlas pixel sensors prototypes was performed. Charge interpolation was used and allowed for a significant improvement with respect to digital resolution. A simplified algorithm for charge interpolation was developed. Its application to both unirradiated and irradiated sensors is presented and discussed.

  2. Beam Test Studies of 3D Pixel Sensors Irradiated Non-Uniformly for the ATLAS Forward Physics Detector

    CERN Document Server

    Grinstein, S; Boscardin, M; Christophersen, M; Da Via, C; Betta, G -F Dalla; Darbo, G; Fadeyev, V; Fleta, C; Gemme, C; Grenier, P; Jimenez, A; Lopez, I; Micelli, A; Nelist, C; Parker, S; Pellegrini, G; Phlips, B; Pohl, D L; Sadrozinski, H F -W; Sicho, P; Tsiskaridze, S

    2013-01-01

    Pixel detectors with cylindrical electrodes that penetrate the silicon substrate (so called 3D detectors) offer advantages over standard planar sensors in terms of radiation hardness, since the electrode distance is decoupled from the bulk thickness. In recent years significant progress has been made in the development of 3D sensors, which culminated in the sensor production for the ATLAS Insertable B-Layer (IBL) upgrade carried out at CNM (Barcelona, Spain) and FBK (Trento, Italy). Based on this success, the ATLAS Forward Physics (AFP) experiment has selected the 3D pixel sensor technology for the tracking detector. The AFP project presents a new challenge due to the need for a reduced dead area with respect to IBL, and the in-homogeneous nature of the radiation dose distribution in the sensor. Electrical characterization of the first AFP prototypes and beam test studies of 3D pixel devices irradiated non-uniformly are presented in this paper.

  3. Beam test studies of 3D pixel sensors irradiated non-uniformly for the ATLAS forward physics detector

    Energy Technology Data Exchange (ETDEWEB)

    Grinstein, S., E-mail: sgrinstein@ifae.es [ICREA and Institut de Física d' Altes Energies (IFAE), Barcelona (Spain); Baselga, M. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Boscardin, M. [Fondazione Bruno Kessler, FBK-CMM, Trento (Italy); Christophersen, M. [U.S. Naval Research Laboratory, Washington (United States); Da Via, C. [School of Physics and Astronomy, University of Manchester, Manchester (United Kingdom); Dalla Betta, G.-F. [Universita degli Studi di Trento and INFN, Trento (Italy); Darbo, G. [INFN Sezione di Genova, Genova (Italy); Fadeyev, V. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz (United States); Fleta, C. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Gemme, C. [Universita degli Studi di Trento and INFN, Trento (Italy); Grenier, P. [SLAC National Accelerator Laboratory, Menlo Park (United States); Jimenez, A.; Lopez, I.; Micelli, A. [ICREA and Institut de Física d' Altes Energies (IFAE), Barcelona (Spain); Nelist, C. [INFN Sezione di Genova, Genova (Italy); Parker, S. [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley (United States); Pellegrini, G. [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona (Spain); Phlips, B. [U.S. Naval Research Laboratory, Washington (United States); Pohl, D.-L. [University of Bonn, Bonn (Germany); Sadrozinski, H.F.-W. [Santa Cruz Institute for Particle Physics, University of California, Santa Cruz (United States); and others

    2013-12-01

    Pixel detectors with cylindrical electrodes that penetrate the silicon substrate (so called 3D detectors) offer advantages over standard planar sensors in terms of radiation hardness, since the electrode distance is decoupled from the bulk thickness. In recent years significant progress has been made in the development of 3D sensors, which culminated in the sensor production for the ATLAS Insertable B-Layer (IBL) upgrade carried out at CNM (Barcelona, Spain) and FBK (Trento, Italy). Based on this success, the ATLAS Forward Physics (AFP) experiment has selected the 3D pixel sensor technology for the tracking detector. The AFP project presents a new challenge due to the need for a reduced dead area with respect to IBL, and the in-homogeneous nature of the radiation dose distribution in the sensor. Electrical characterization of the first AFP prototypes and beam test studies of 3D pixel devices irradiated non-uniformly are presented in this paper.

  4. Receiver front end for optical free space communications

    Science.gov (United States)

    Hildebrand, Ulrich

    1994-09-01

    The Receiver Front End (RFE) is the optical receiver of ESA's Semiconductor Laser Intersatellite Link Experiment (SILEX). Optical free space communication between satellites is characterized by narrow beams and therefore by demanding requirements for pointing accuracy. This applies for the steering of the laser beam in transmission, for the pointing of the receiver's field of view (FOV), and for the alignment between transmitted and received beams. The RFE housing, the optical system, the lens and detector's mounting have to be designed to meet the stringent requirements for angular stability. This paper concentrates on the mechanical and thermal aspects which strongly influence the performance. Thermal expansion effects are of major concern when keeping the optical axis stable. All materials have been matched to the thermal expansion characteristics of the hybrid circuit which contains the detector. Assuming only homogeneous temperature changes during life, no stress or angular deviations have to be expected. The relative changes of dimensions in any direction stays equal at different temperatures. The verification of opto-mechanical performance requires sophisticated measurement tools. Measurements have to be performed in order to determine the lateral stability of lens and detector. A dedicated autocollimator was developed which measures the angular stability of the optical axis after vibration, thermo-vacuum test and under temperature changes. It also serves as a test transmitter. Measurement accuracies of 5 (mu) rad have been achieved. For the measurements the RFE is mounted onto a test fixture. A reference mirror on the fixture is the stable reference which has to be more stable than the equipment itself.

  5. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  6. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Kass, R; Gan, K K; Johnson, M; Kagan, H; Rush, C J; Rahimi, A; Smith, S; Ter-Antonian, R; Zoeller, M M; Ciliox, A; Holder, M; Nderitu, S; Ziolkowski, M

    2003-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 um CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from prototype circuits and from irradiation studies with 24 GeV protons up to 57 Mrad (1.9 x 10e15 p/cm2).

  7. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Gan, K K; Johnson, M; Kagan, H; Kass, R; Rush, C; Smith, S; Ter-Antonian, R; Zoeller, M M; Ciliox, A; Holder, M; Ziolkowski, M

    2005-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 62 Mrad (2.3 x 10^15 p/cm^2).

  8. Radiation-Hard ASICs for Optical Data Transmission in the ATLAS Pixel Detector

    CERN Document Server

    Gan, K K; Johnson, M; Kagan, H; Kass, R; Rush, C; Smith, S; Ter-Antonian, R; Zöller, M; Ciliox, A; Holderb, M; Ziolkowski, M

    2006-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the LHC at CERN: a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode for 80 Mbit/s data transmission from the detector, and a Bi-Phase Mark decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode. We have successfully implemented both ASICs in 0.25 mm CMOS technology using enclosed layout transistors and guard rings for increased radiation hardness. We present results from circuits of final design and from irradiation studies with 24 GeV protons up to 80 Mrad (2.6 x 10^15 p/cm^2).

  9. Radiation-hard ASICs for optical data transmission in the ATLAS pixel detector

    CERN Document Server

    Ziolkowski, M; Buchholz, P; Ciliox, A; Gan, K K; Holder, M; Johnson, M; Kagan, H; Kass, R; Nderitu, S; Rahimi, A; Rush, C J; Smith, S; Ter-Antonian, R; Zoeller, M M

    2004-01-01

    We have developed two radiation-hard ASICs for optical data transmission in the ATLAS pixel detector at the CERN Large Hadron Collider (LHC). The first circuit is a driver chip for a Vertical Cavity Surface Emitting Laser (VCSEL) diode to be used for 80 Mbit/s data transmission from the detector. The second circuit is a Bi-Phase Mark, decoder chip to recover the control data and 40 MHz clock received optically by a PIN diode on the detector side. During ten years of operation at the LHC, the ATLAS optical link circuitry will be exposed to a maximum total fluence of 10/sup 15/ 1-MeV-equivalent neutrons per cm/sup 2/. We have successfully implemented both ASICs in a commercial 0.25 mu m CMOS technology using standard layout techniques to enhance the radiation tolerance. Both chips are four- channel devices compatible with common cathode PIN and VCSEL arrays. We present results from final prototype circuits and from irradiation studies of both circuits with 24 GeV protons up to a total dose of 57 Mrad. (3 refs).

  10. Upgrade Design of TileCal Front-end Readout Electronics and Radiation Hardness Studies

    CERN Document Server

    Anderson, K; The ATLAS collaboration; Drake, G; Eriksson, D; Muschter, S; Oreglia, M; Pilcher, J; Price, L; Tang, F

    2011-01-01

    The ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of hadrons and taus produced in LHC collisions. The TileCal consists of "tiles" of plastic scintillator dispersed in a fine-grained steel matrix . Optical fibers from the tiles are sent to ~10,000 photomultiplier tubes (PMT) and associated readout electronics. The TileCal front-end analog readout electronics process the signals from ~10,000 PMTs. Signals from each PMT are shaped with a 7-pole passive LC shaper and split it to two channels amplified by a pair of clamping amplifiers with a gain ratio of 32. Incorporated with two 40Msps 12-bit ADCs, the readout electronics provide a combined dynamic range of 17-bits. With this dynamic range, the readout system is capable of measuring the energy deposition in the calorimeter cells from ~220MeV to 1.3TeV with the least signal-to-noise ratio of greater than 20. The digitized data from each PMT are transmitted off-detector optically, where the data are further processed with ded...

  11. Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

    The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

  12. Silvaco ATLAS model of ESA's Gaia satellite e2v CCD91-72 pixels

    CERN Document Server

    Seabroke, G M; Burt, D; Robbins, M S; 10.1117/12.856958

    2010-01-01

    The Gaia satellite is a high-precision astrometry, photometry and spectroscopic ESA cornerstone mission, currently scheduled for launch in 2012. Its primary science drivers are the composition, formation and evolution of the Galaxy. Gaia will achieve its unprecedented accuracy requirements with detailed calibration and correction for CCD radiation damage and CCD geometric distortion. In this paper, the third of the series, we present our 3D Silvaco ATLAS model of the Gaia e2v CCD91-72 pixel. We publish e2v's design model predictions for the capacities of one of Gaia's pixel features, the supplementary buried channel (SBC), for the first time. Kohley et al. (2009) measured the SBC capacities of a Gaia CCD to be an order of magnitude smaller than e2v's design. We have found the SBC doping widths that yield these measured SBC capacities. The widths are systematically 2 {\\mu}m offset to the nominal widths. These offsets appear to be uncalibrated systematic offsets in e2v photolithography, which could either be du...

  13. Development of Edgeless n-on-p Planar Pixel Sensors for future ATLAS Upgrades

    CERN Document Server

    Bomben, M; Boscardin, M; Bosisio, L; Calderini, G; Chauveau, J; Giacomini, G; La Rosa, A; Marchori, G; Zorzi, N

    2012-01-01

    The development of n-on-p "edgeless" planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the "active edge" technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of $1 \\times 10^{15} {\\rm n_{eq}}/{\\rm cm}^2$ comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb$^{-1}$) for the outer pixel layers. We show that, after irradiation, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach.

  14. Development of Edgeless n-on-p Planar Pixel Sensors for future ATLAS Upgrades

    CERN Document Server

    Bomben, M

    2013-01-01

    The development of n-on-p “edgeless” planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the “active edge” technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of View the MathML source1×1015neq/cm2 comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb−1) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity...

  15. Development of edgeless n-on-p planar pixel sensors for future ATLAS upgrades

    Science.gov (United States)

    Bomben, Marco; Bagolini, Alvise; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Giacomini, Gabriele; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

    2013-06-01

    The development of n-on-p "edgeless" planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the "active edge" technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of 1×1015 neq/cm2 comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb-1) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach.

  16. Front-End Electronics in calorimetry: from LHC to ILC

    Energy Technology Data Exchange (ETDEWEB)

    De La Taille, Ch.

    2009-09-15

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the

  17. The ITER neutral beam front end components integration

    Energy Technology Data Exchange (ETDEWEB)

    Urbani, M., E-mail: marc.urbani@iter.org [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Hemsworth, R.; Schunke, B.; Graceffa, J.; Delmas, E.; Svensson, L.; Boilson, D. [ITER Organization, Route de Vinon sur Verdon, 13115 St Paul Lez Durance (France); Krylov, A.; Panasenkov, A. [RRC Kurchatov Institute, 1, Kurchatov Square, Moscow 123182 (Russian Federation); Agarici, G. [Fusion For Energy, C/Josep Pla 2, Torres Diagonal Litoral-B3, E-08019 Barcelona (Spain); Stafford Allen, R.; Jones, C.; Kalsey, M.; Muir, A.; Milnes, J. [Culham Centre for Fusion Energy, Culham Science Centre, Abingdon OX14 3DB (United Kingdom); Geli, F. [FGI Consulting, Le Garde d’Estienne, 4565 route du Puy Sainte Reparade, 13540 Puyricard (France); Sherlock, P. [AMEC Limited, Booths Park Chelford Road, Knutsford Cheshire WA16 8QZ (United Kingdom)

    2013-10-15

    The neutral beam (NB) system for ITER is composed of two heating neutral beam injectors (HNBs) and a diagnostic neutral beam injector (DNB). A third HNB can be installed as a future up-grade. This paper will present the design development of the components between the injectors and the tokamak; the so-called ‘front end components’: the drift duct consists of the NB bellows and the drift duct liner, the vacuum vessel pressure suppression system box (VVPSS box), the absolute valve, and the fast shutter. These components represent the key links between the ITER tokamak and the vessels of the NB injectors. The design of these components is demanding due to the different loads that these components will have to stand. The paper will describe the different design solutions which have to be implemented regarding the primary vacuum confinement, the power handling capability and the remote maintenance operations. The sizes of the components are determined by the large cross section of the neutral beam. The power handling capability is driven by the anticipated re-ionization of the neutral beam and the electromagnetic fields in this region. The drift duct bellows (with an inner diameter of 2.5 m) shall guarantee a leak tight vacuum enclosure during the vertical and radial displacements of the ITER vacuum vessel. The conductance of the VVPSS box must be maximized in the available space. The absolute valve remains a challenging development. The total leak rate through the valve must be ≤1 × 10{sup −8} Pa m{sup 3}/s when the valve is closed. Due to the radiation environment, the seals of the gate valve will be metallic. An R and D program has been launched to develop a suitable metallic seal solution with the required dimensions. The maximum allowed closing time for the fast shutter shall be less than 1 s. For all these components the leak tightness will be guaranteed by a welded lip seal and the mechanical stability by bolted structures.

  18. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... pressure drop. (B) If the scrubber is subject to regulations in 40 CFR parts 264 through 266 that have... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents... § 63.489 Batch front-end process vents—monitoring equipment. (a) General requirements. Each owner...

  19. Front-end research for a low-cost spectrum analyser v1 0 2

    NARCIS (Netherlands)

    Rovers, K.C.

    2006-01-01

    This report discusses front-end research for a low-cost spectrum analyser. Requirement of the front-end are derived and a topology study is performed, both from an analogue as a digital perspective. Simulations are carried out to confirm the findings. This master project was initiated by Bruco B.V.,

  20. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  1. 10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

    Institute of Scientific and Technical Information of China (English)

    Fan Chao; Chen Tangsheng; Yang Lijie; Feng Ou; Jiao Shilong; Wu Yunfeng; Ye Yutang

    2009-01-01

    A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fab ricated based on the φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simu lation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50×50 μm~2. The whole chip has an area of 1511×666 μm~2. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950×1910μm~2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 tnVpp.

  2. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  3. The Pixel Detector of the ATLAS experiment for the Run2 at the Large Hadron Collider -- Plot Approval (Pixel, IBL) : This is a submission of plot approval request for Pixel+IBL, facing on a talk at ICHEP 2014 conference

    CERN Document Server

    Mandelli, B; The ATLAS collaboration

    2014-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of LHC. Taking advantage of the long showdown, the detector was extracted from the experiment and brought to surface, to equip it with new service quarter panels, to repair modules and to ease installation of the Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and will be installed in May 2014 between the existing Pixel Detector and a new smaller radius beam-pipe at a radius of 3.3 cm. To cope with the high radiation and pixel occupancy due to the proximity to the interaction point, a new read-out chip and two different silicon sensor technologies (planar and 3D) have been developed. Furthermore, the physics performance will be improved through the reduction of pixel size while, targeting for a low material budget, a new mechanical support using lightweight staves and a CO2 based cooling system have been adopted. IBL construction is now completed. An overview of the IBL project as well as the ...

  4. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    International Nuclear Information System (INIS)

    In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerator's instantaneous luminosity by a factor of 5 and the integrated luminosity by a factor of 10. In the context of this upgrade, the inner detector (including the pixel detector) of the ATLAS experiment will be replaced. This new pixel detector requires a specific control system which complies with strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4×4 DCS chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub-micron technology. We present results from reliability measurements under irradiation from new prototypes of components for the DCS network.

  5. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  6. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-01-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  7. Radiation tests of photodiodes for the ATLAS SCT and PIXEL opto- links

    CERN Document Server

    Hou, L S; Lee, S C; Su, D S; Teng, P K

    2005-01-01

    In previous research, epitaxial Si PIN photodiodes produced by Centronic which will be used in the ATLAS semiconductor tracker have been irradiated with 1 MeV neutrons and 24 GeV protons with fluences up to an equivalent of $10^{15}$ 1 MeV neutrons (1,2) . In this work 30 MeV proton beams were used to irradiate Centronic and Truelight epitaxial Si PIN diodes with accumulated fluences of up to 2.1 multiplied by $10^{14}$-30 MeV p $cm^{-2}$, an equivalent of 5.7 multiplied by $10^{14} cm^{-2}$ 1 MeV neutrons, to reach the pixel radiation environment. The responsivity was measured with different levels of fluence in order to study the responsivity behaviour of two different types of photodiodes. The responsivity behaviour of these two photodiodes was similar: a linear degradation at large fluences, greater than $10^{14}$ 30 MeV p $cm^{-2}$, but with different slopes. The response of the Centronic PIN diode showed a degradation to 73% after a proton fluence of $10^{13}$ p $cm^{-2}$ of 30 MeV and a linear degradat...

  8. Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

    International Nuclear Information System (INIS)

    The LHC accelerator complex will be upgraded between 2020–2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented

  9. Experience with 3D integration technologies in the framework of the ATLAS pixel detector upgrade for the HL-LHC

    CERN Document Server

    Aruntinov, D; Gonella, L; Hemperek, T; Hügging, F; Krüger, H; Wermes, N; Breugnon, P; Chantepie, B; Clemens, J.C; Fei, R; Fougeron, D; Godiot, S; Pangaud, P; Rozanov, A; Garcia-Sciveres, M; Mekkaoui, A

    2013-01-01

    3D technologies are investigated for the upgrade of the ATLAS pixel detector at the HL-LHC. R&D focuses on both, IC design in 3D, as well as on post-processing 3D technologies such as Through Silicon Via (TSV). The first one uses a so-called via first technology, featuring the insertion of small aspect ratio TSV at the pixel level. As discussed in the paper, this technology can still present technical challenges for the industrial partners. The second one consists of etching the TSV via last. This technology is investigated to enable 4-side abuttable module concepts, using today's pixel detector technology. Both approaches are presented in this paper and results from first available prototypes are discussed.

  10. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  11. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  12. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

  13. Oxford Summer School "Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry"

    CERN Document Server

    2013-01-01

    Interdisciplinary Summer School on Intelligent Front-End Signal Processing for Frontier Exploitation in Research and Industry. For details about the school programme and registration, please visit: http://www.physics.ox.ac.uk/INFIERI2013/

  14. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  15. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  16. A NEW MODIFIED TOTAL FRONT END FRAMEWORK FOR INNOVATION: NEW INSIGHTS FROM HEALTH RELATED INDUSTRIES

    OpenAIRE

    PATRICK J. TROTTER

    2011-01-01

    This paper explores the front end innovation activities in a multinational Global Healthcare Company (GHC). A questionnaire was designed and distributed to front end innovators from 20 operating companies to understand team composition, essential skill sets, and the methodology used to assess customer needs, generate ideas, and define the selection criteria used during the go/no go decision. For each category the current state and best practice (based on the views of the individual respondent...

  17. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  18. Front-End Electronics Test System Status Information (After ASDQ++ boards TEST at CERN)

    CERN Document Server

    Nobrega, R; Cernicchiaro, G

    2003-01-01

    A Front-End Electronics Test System (FEET) is being implemented in order to test the Front-end electronics (FEE), in the production line, for the LHCb Muon System. This document discusses some aspects related to the test of ASDQ++ boards. FEET presently enables 5 different tests: Connectivity, Crosstalk, Noise, Sensitivity and Rate-Method tests. The system has detected 25 channels with problems out of 640 tested channels.

  19. A front-end stage with signal compression capability for XFEL detectors

    Science.gov (United States)

    Nasri, B.; Fiorini, C.; Grande, A.; Erdinger, F.; Fischer, P.; Porro, M.

    2015-01-01

    In this work, we present a front-end stage with signal compression capability to be used in detectors for the new European XFEL in Hamburg. This front-end is an alternative solution under study for the DEPFET Sensor with Signal Compression (DSSC) detection system for the European XFEL. The DEPFET sensor of the DSSC project has a high dynamic range and very good noise performance. The high gain for small collected charge and the compression for large signals will provide both desired features of single photon detection capability and wide dynamic range. However, manufacturing of the DEPFET sensor requires a sophisticated processing technology with a relatively long time fabrication process. Accordingly, an alternative solution, namely Day-0 solution, was introduced as an approach characterized not by the best performance of the DEPFET, but available in a shorter time to allow first beam tests and experiments. The alternative sensor is made of mini Silicon Drift Detector (mini-SDD) and the compression behavior is obtained from the front-end on the readout ASIC and not by the transistor integrated in the silicon sensor, as in the DEPFET. The first version of corresponding front-end of the Day-0 solution has been realized based on an input PMOSFET transistor placed on the readout chip. This simple front-end proved the working principle of the proposed compression technique and the desired noise performance. In this paper, an improved version of the Day-0 front-end is presented. In the new prototype, the current gain of the front-end stage has been increased by factor of 1.8, the total input capacitance (SDD+PMOSFET) has been reduced by factor of 2 with respect to the previous prototype and consequently the noise performance has been improved. Moreover, by introducing selectable extra branches in parallel with the main one, the compression behavior of the front-end can be tuned based on desired dynamic range.

  20. Ember.js front-end framework – SEO challenges and frameworks comparison

    OpenAIRE

    Shrestha, Sunil

    2015-01-01

    IWA Labs Oy, a Finnish company with extensive experience in modern information technology provides professional service in Search Engine Optimization (SEO), online marketing as well as develop mobile and web applications for its clients. In order to provide smooth and better user experience with web applications, the company has adapted front-end dedicated frameworks such as AngularJS, Backbone.js, etc. Therefore, the company is interested in Ember.js– another emerging front-end framework th...

  1. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    International Nuclear Information System (INIS)

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

  2. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  3. The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

    CERN Document Server

    Mullier, Geoffrey; The ATLAS collaboration

    2015-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

  4. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    CERN Document Server

    Terzo, S; Nisius, R; Paschen, B

    2014-01-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 $\\mu$m, produced at CiS, and 100-200 $\\mu$m thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The perfo...

  5. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Terzo, S.; Macchiolo, A.; Nisius, R.; Paschen, B.

    2014-12-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 μm, produced at CiS, and 100-200 μm thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The performance of the different sensor thicknesses and edge designs are compared before and after irradiation up to a fluence of 1.4 × 1016 neq/cm2.

  6. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

  7. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

  8. Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

    CERN Document Server

    Giacomini, Gabriele; Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

    2014-01-01

    In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch.

  9. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    Calderini, G; Bomben, M; Boscardin, M; Bosisio, L; Chauveau, J; Giacomini, G; La Rosa, A; Marchiori, G; Zorzi, N

    2014-01-01

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R&D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  10. Attenuation of front-end reflections in an impulse radar using high-speed switching

    Science.gov (United States)

    Mazzaro, Gregory J.; Ressler, Marc A.; Smith, Gregory D.

    2011-06-01

    Pulse reflection between front-end components is a common problem for impulse radar systems. Such reflections arise because radio frequency components are rarely impedance-matched over an ultra-wide bandwidth. Any mismatch between components causes a portion of the impulse to reflect within the radar front-end. If the reflection couples into the transmit antenna, the radar emits an unintended, delayed and distorted replica of the intended radar transmission. These undesired transmissions reflect from the radar environment, produce echoes in the radar image, and generate false alarms in the vicinity of actual targets. The proposed solution for eliminating these echoes, without redesigning the transmit antenna, is to dissipate pulse reflections in a matched load before they are emitted. A high-speed switch directs the desired pulse to the antenna and redirects the undesired reflection from the antenna to a matched load. The Synchronous Impulse Reconstruction (SIRE) radar developed by the Army Research Laboratory (ARL) is the case-study. This paper reviews the current front-end design, provides a recent radar image which displays the aforementioned echoes, and describes the switch-cable-load circuit solution for eliminating the echoes. The consequences of inserting each portion of the new hardware into the radar front-end are explained. Measurements on the front-end with the high-speed switch show an attenuation of the undesired pulse transmissions of more than 18 dB and an attenuation in the desired pulse transmission of less than 3 dB.

  11. Prediction and control of front-end curvature in hot finish rolling process

    Directory of Open Access Journals (Sweden)

    Kyunghun Lee

    2015-11-01

    Full Text Available The purpose of this study is to predict the front-end curvature in hot strip finishing mills and to prevent it by controlling the rolling conditions. A theoretical model based on the slab method is developed for predicting the front-end curvature by taking into account the entrance angle of the strip, the friction condition and the back tension. To validate the developed theoretical model, the theoretically obtained curvature value is compared with the results of finite element analysis. Consequently, it is shown that the calculation results of the theoretical model are in good agreement with the measured results of the finite element analysis. Furthermore, a curvature control model based on geometrical and mathematical approaches that can reduce the front-end curvature by the control of the roll speed ratio of the upper to lower rolls is proposed. The proposed curvature control model is verified by finite element analysis, and it is shown that the front-end curvature can be reduced considerably using the proposed model. Therefore, it is concluded that the proposed control model for reducing the front-end curvature in a hot strip finishing mill can be used to improve the quality of the rolled product.

  12. Study of the Radiation Hardness Performance of PiN diodes for the ATLAS Pixel Detector at the SLHC upgrade

    CERN Document Server

    Abi, B

    2009-01-01

    We study the radiation tolerance of the silicon and GaAs PiN diodes that will be the part of the readout system of the upgraded ATLAS pixel detector. The components were irradiated by 200 MeV protons up to total accumulated dose 1.2×1015 p/cm2 and by 24 GeV protons up to 2.6×1015 p/cm2. Based on obtained results, we conclude that radiation hardness does not depend on the sensitive area or cut off frequency of PiN diodes. We identify two diodes that can be used for the SLHC upgrade.

  13. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    OpenAIRE

    Terzo, S.; Macchiolo, A; Nisius, R.; Paschen, B.

    2014-01-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 $\\mu$m, produced at CiS, and 100-200 $\\mu$m thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowin...

  14. Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

    2016-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

  15. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Science.gov (United States)

    Calderini, G.; Bagolini, A.; Beccherle, R.; Bomben, M.; Boscardin, M.; Bosisio, L.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

    2016-09-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  16. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, Michael

    2010-07-19

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 10{sup 35}/cm{sup 2}s{sup 1} is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).10{sup 16} 1-MeV-neutrons per square centimeter (n{sub eq}/cm{sup 2}). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 {mu}m and 150 {mu}m proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive

  17. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 1035/cm2s1 is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).1016 1-MeV-neutrons per square centimeter (neq/cm2). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 μm and 150 μm proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive edge demonstrate that the active sensor

  18. A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

    Science.gov (United States)

    Sotiropoulou, C. L.; Gkaitatzis, S.; Annovi, A.; Beretta, M.; Kordas, K.; Nikolaidis, S.; Petridou, C.; Volpi, G.

    2014-10-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of

  19. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Science.gov (United States)

    Feng, Zhou; Ting, Gao; Fei, Lan; Wei, Li; Ning, Li; Junyan, Ren

    2010-11-01

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 μm RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  20. Electronically Tunable Antenna Pair and Novel RF Front-End Architecture for Software-Defined Radios

    Directory of Open Access Journals (Sweden)

    Oh Sung-Hoon

    2005-01-01

    Full Text Available This paper proposes a novel RF front-end architecture for software-defined radios (SDRs based on an electronically tunable antenna pair controlled by an antenna control unit (ACU consisting of field effect transistor (FET switches and a field programmable gate array (FPGA. The fundamental gain-bandwidth limitations of electrically small antennas prevent a small antenna from having high efficiency and wide bandwidth simultaneously. In the age of miniaturization, especially in the wireless communication industries, a promising solution to this limitation is to introduce reconfigurable antennas that can be tuned electronically to different frequency bands with both high efficiency and narrow instantaneous bandwidth. This reconfigurable antenna technology not only simplifies current RF front-end architectures, but can be reprogrammed on demand to transmit and receive RF signals in any desired frequency band. This novel RF front-end architecture implemented by a reconfigurable antenna pair can help realize SDRs.

  1. Front-end electronics for Micro Pattern Gas Detectors with integrated input protection against discharges

    International Nuclear Information System (INIS)

    One of the major problems that have to be addressed in the design of the front-end electronics for readout of MPGDs, is its resistance to possible random discharges inside active detector volume. This issue becomes particularly critical for the electronics built as ASICs implemented in a modern CMOS technology, for which the breakdown voltages are in the range of a few Volts, while the discharges may result in voltage spikes of even thousands Volts. The paper presents test results of input protection structures integrated with a specific design of the front-end electronics manufactured in the 350 nm CMOS process. The structures were tested using an electrical circuit to mimic discharges in the detectors for different voltage and current parameters of the sparks. Accomplished measurements showed no degradation in the front-end electronics performance even after very excessive discharge tests

  2. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  3. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  4. A low noise CMOS RF front-end for UWB 6-9 GHz applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhou Feng; Gao Ting; Lan Fei; Li Wei; Li Ning; Ren Junyan, E-mail: w-li@fudan.edu.cn [State Key Laboratory of ASIC and System, Fudan University, Shanghai 201203 (China)

    2010-11-15

    An integrated fully differential ultra-wideband CMOS RF front-end for 6-9 GHz is presented. A resistive feedback low noise amplifier and a gain controllable IQ merged folded quadrature mixer are integrated as the RF front-end. The ESD protected chip is fabricated in a TSMC 0.13 {mu}m RF CMOS process and achieves a maximum voltage gain of 23-26 dB and a minimum voltage gain of 16-19 dB, an averaged total noise figure of 3.3-4.6 dB while operating in the high gain mode and an in-band IIP3 of -12.6 dBm while in the low gain mode. This RF front-end consumes 17 mA from a 1.2 V supply voltage.

  5. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi;

    2012-01-01

    for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives......This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

  6. Performance Trade-Off Analysis Comparing Different Front-End Configurations for a Digital X-ray Imager.

    Science.gov (United States)

    Kuhls-Gilcrist, Andrew; Jain, Amit; Bednarek, Daniel R; Rudin, Stephen

    2010-10-30

    Performance of indirect digital x-ray imagers is typically limited by the front-end components. Present x-ray-to-light converting phosphors significantly reduce detector resolution due to stochastic blurring and k-fluorescent x-ray reabsorption. Thinner phosphors improve resolution at the cost of lowering quantum detection efficiency (QDE) and increasing Swank noise. Magnifying fiber optic tapers (FOTs) are commonly used to increase the field-of-view of small sensor imagers, such as CMOS, CCD, or electron-multiplying CCD (EMCCD) based detectors, which results in a reduction in detector sensitivity and further reduces the MTF. We investigate performance trade-offs for different front-end configurations coupled to an EMCCD sensor with 8 μm pixels. Six different columnar structured CsI(Tl) scintillators with thicknesses of 100, 200, 350, 500, and 1000 μm type high-light (HL) and a 350 μm type high-resolution (HR) (Hamamatsu) and four different FOTs with magnification ratios (M) of 1, 2.5, 3.3, and 4 were studied using the RQA5 x-ray spectrum. The relative signal of the different scintillators largely followed the relative QDE, indicating their light output per absorbed x-ray was similar, with the type HR CsI emitting 57% of the type HL. The efficiency of the FOTs was inversely proportional to M(2) with the M = 1 FOT transmitting 87% of the incident light. At 5 (10) cycles/mm, the CsI MTF was 0.38 (0.22), 0.33 (0.17), 0.37 (0.19), 0.23 (0.09), 0.19 (0.08), and 0.09 (0.03) for the 100, 200, 350HR, 350, 500, and 1000 μm CsI, respectively and the FOT MTF was 0.89 (0.84), 0.80 (0.72), 0.70 (0.60), and 0.69 (0.37) for M = 1, 2.5, 3.3, and 4, respectively. The 1000, 500, and 350HR μm CsI had the highest DQE for low, medium, and high spatial frequency ranges of 0 to 1.6, 1.6 to 4.5, and 4.5 to 10 cycles/mm, respectively. Larger FOT M resulted in a reduction in DQE. Quantifying performance of different front-end configurations will enable optimal selection of components

  7. Design of a Direct-conversion Radio Receiver Front-end in CMOS Technology

    OpenAIRE

    Erixon, Mats

    2002-01-01

    In this Master's thesis, a direct-conversion receiver front-end has been designed in a 0.18um CMOS technology. Direct-conversion receivers (DCR) have obvious advantages over the heterodyne counterpart. Since the intermediate frequency (IF) is zero, the problem of image is circumvented. As a result, no front-end image reject filter is required and the channel selection requires only a low-pass filter, which makes it easy to integrate directly on chip. However, the DCR also suffers from severa...

  8. Design and Optimization of an Analog Front-End for Biomedical Applications

    OpenAIRE

    Razzaghpour, Milad

    2011-01-01

    The state-of-the-art analog front-end of implantable biosensors is the class of current-mirror-based circuits. Despite their superior noise performance, power consumption and area, they suffer from systematic and random errors causing offset, gain and linearity error in reading out the sensor data. In the first part of this thesis, a new analog front-end is proposed to eliminate the systematic error. The proposed topology is able to accurately copy the sensor current which will be converted i...

  9. Flexible Analog Front Ends of Reconfigurable Radios Based on Sampling and Reconstruction with Internal Filtering

    Directory of Open Access Journals (Sweden)

    Poberezhskiy Gennady Y

    2005-01-01

    Full Text Available Bandpass sampling, reconstruction, and antialiasing filtering in analog front ends potentially provide the best performance of software defined radios. However, conventional techniques used for these procedures limit reconfigurability and adaptivity of the radios, complicate integrated circuit implementation, and preclude achieving potential performance. Novel sampling and reconstruction techniques with internal filtering eliminate these drawbacks and provide many additional advantages. Several ways to overcome the challenges of practical realization and implementation of these techniques are proposed and analyzed. The impact of sampling and reconstruction with internal filtering on the analog front end architectures and capabilities of software defined radios is discussed.

  10. Implementation of a 66 MHz analog memory as a front end for LHC detectors

    Energy Technology Data Exchange (ETDEWEB)

    Munday, D.J.; Parker, M.A. (Cavendish Laboratory, University of Cambridge, Cambridge CB3 OHE (United Kingdom)); Anghinolfi, F.; Aspell, P.; Campbell, M.; Chilingarov, A.; Gros, J.; Jarron, P.; Heijne, E.H.M.; Meddeler, G.; Pollet, L.; Santiard, J.C.; Verweij, H. (CERN, CH-1211 Geneva 23 (Switzerland)); Goessling, C.; Lisowsky, B. (Institut fuer Physik, Universitaet Dortmund, D-4600 Dortmund (Germany)); Bonino, R.; Clark, A.G.; Couyoumtzelis, C.; Kambara, H.; La Marra, D.; Wu, X. (DPNC, Geneva University, CH-1211, Geneva 4 (Switzerland)); Moorhead, G. (School of Physics, University of Melbourne, Parkville, Victoria 3052 (Australia)); Weidberg, A. (Department of Nuclear Physics, Oxford University, Oxford (United Kingdom)); Campbell, D.; Murray, P.; Seller, P.; Stevens, R. (Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 0QX (United Kingdom)); Beuville, E.; Rouger, M.; Teiger, J. (Centre d' Etudes Nucleaires de Saclay, F-91191 Gif-sur-Yvette (France))

    1992-02-05

    We describe the front end signal processing chip (HARP) being developed by the RD2 collaboration for LHC detectors. The HARP chip, based around an analog memory, will provide data storage at LHC rates for 2 [mu]sec and allow stored data to be accessed for trigger rates of up to 50--100 KHz. We have tested two different prototypes of the final chip as front end for silicon detectors, using a Sr90 source and high energy pions and electrons from the CERN-SPS test beam.

  11. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    International Nuclear Information System (INIS)

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  12. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric,I et al.

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  13. High speed data transmission on small gauge cables for the ATLAS Phase-II Pixel detector upgrade

    International Nuclear Information System (INIS)

    The High Luminosity LHC will present a number of challenges for the upgraded ATLAS detector. In particular, data transmission requirements for the upgrade of the ATLAS Pixel detector will be difficult to meet. The expected trigger rate and occupancy imply multi-gigabit per second transmission rates will be required but radiation levels at the smallest radius preclude completely optical solutions. Electrical transmission up to distances of 7m will be necessary to move optical components to an area with lower radiation levels. Here, we explore the use of small gauge electrical cables as a high-bandwidth, radiation hard solution with a sufficiently small radiation length. In particular, we present a characterization of various twisted wire pair (TWP) configurations of various material structures, including measurements of their bandwidth, crosstalk, and radiation hardness. We find that a custom ''hybrid'' cable consisting of 1m of a multi-stranded TWP with Poly-Ether-Ether-Ketone (PEEK) insulation and a thin Al shield followed by 6m of a thin twin-axial cable presents a low-mass solution that fulfills bandwidth requirements and is expected to be sufficiently radiation hard. Additionally, we discuss preliminary results of using measured S-parameters to produce a SPICE model for a 1m sample of the custom TWP to be used for the development of new pixel readout chips

  14. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  15. High speed data transmission on small gauge cables for the ATLAS Phase-II Pixel detector upgrade

    Science.gov (United States)

    Shahinian, J.; Volk, J.; Fadeyev, V.; Grillo, A. A.; Meimban, B.; Nielsen, J.; Wilder, M.

    2016-03-01

    The High Luminosity LHC will present a number of challenges for the upgraded ATLAS detector. In particular, data transmission requirements for the upgrade of the ATLAS Pixel detector will be difficult to meet. The expected trigger rate and occupancy imply multi-gigabit per second transmission rates will be required but radiation levels at the smallest radius preclude completely optical solutions. Electrical transmission up to distances of 7m will be necessary to move optical components to an area with lower radiation levels. Here, we explore the use of small gauge electrical cables as a high-bandwidth, radiation hard solution with a sufficiently small radiation length. In particular, we present a characterization of various twisted wire pair (TWP) configurations of various material structures, including measurements of their bandwidth, crosstalk, and radiation hardness. We find that a custom ``hybrid'' cable consisting of 1m of a multi-stranded TWP with Poly-Ether-Ether-Ketone (PEEK) insulation and a thin Al shield followed by 6m of a thin twin-axial cable presents a low-mass solution that fulfills bandwidth requirements and is expected to be sufficiently radiation hard. Additionally, we discuss preliminary results of using measured S-parameters to produce a SPICE model for a 1m sample of the custom TWP to be used for the development of new pixel readout chips.

  16. Development of a Standardised Readout System for Active Pixel Sensors in HV/HR-CMOS Technologies for ATLAS Inner Detector Upgrades

    International Nuclear Information System (INIS)

    The LHC Phase-II Upgrade results in new challenges for tracking detectors for example in terms of cost effectiveness, resolution and radiation hardness. Active Pixel Sensors in HV/HR-CMOS technologies show promising results coping with these challenges. In order to demonstrate the feasibility of hybrid modules with active CMOS sensors and readout chips for the future ATLAS Inner Tracker, ATLAS R and D activities have started. After introducing the basic concepts and the demonstrator program, the development of an ATLAS compatible readout system will be presented as well as tuning procedures and measurements with demonstrator modules to test the readout system

  17. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken...

  18. Front-end equipment protection system at the Advanced Photon Source

    International Nuclear Information System (INIS)

    The front-end Equipment Protection System (FE-EPS) at the Advanced Photon Source (APS) is a high reliability, fail-safe single-chain interlock and control system. It consists of an Allen-Bradley PLC-5/30 processor, local and remote I/O racks, monitoring and control panels, serial communication links, and field devices. Each front end is equipped with a dedicated EPS. The system monitors a variety of sensors (e.g., vacuum, cooling water, temperature, pneumatic pressure), and controls front-end (FE) photon shutters and UHV valves. The main functions of the FE-EPS are to guard the integrity of the storage ring vacuum against vacuum excursions in the FE and beam transport line, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. The FE-EPS interfaces to six other APS interlock and control systems. Information about FE interlocks and devices is displayed on UNIX machines using the EPICS software tool kit. The system design is presented. copyright 1996 American Institute of Physics

  19. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter;

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified...

  20. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  1. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; Van Engelen, Jo; Achterkamp, Madolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to supp

  2. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study aim

  3. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  4. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels;

    2009-01-01

    subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AFE will enable various desired features, as for example the ability to use the front-end with antenna...

  5. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube sig

  6. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  7. Fuzzy decision support for tools selection in the core front end activities of new product development

    NARCIS (Netherlands)

    Achiche, S.; Appio, F.; McAloone, T.; Di Minin, A.D.

    2012-01-01

    The innovation process may be divided into three main parts: the front end (FE), the new product development (NPD) process, and the commercialization. Every NPD process has a FE in which products and projects are defined. However, companies tend to begin the stages of FE without a clear definition o

  8. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh;

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which...

  9. Status on the development of front-end and readout electronics for large silicon trackers

    Indian Academy of Sciences (India)

    J David; M Dhellot; J-F Genat; F Kapusta; H Lebbolo; T-H Pham; F Rossel; A Savoy-Navarro; E Deumens; P Mallisse; D Fougeron; R Hermel; Y Karyotakis; S Vilalte

    2007-12-01

    Final results on a CMOS 0.18 m front-end chip for silicon strips readout are summarized and preliminary results on time measurement are discussed. The status of the next version in 0.13 m is briefly presented.

  10. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  11. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

    2015-05-15

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

  12. Impact of Fast Shaping at the Front-end on Signals from Micro Strip Gas Chambers

    CERN Document Server

    Sciacca, G F

    1997-01-01

    The ballistic deficit due to fast shaping time constants at the front-end amplifier is evaluated using Monte Carlo generated events simulating isolated hits in MSGCs of CMS performance. The effect of the track incidence angle is also investigated up to 45 degrees.

  13. Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

    International Nuclear Information System (INIS)

    A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities

  14. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  15. Commissioning and operation of the FNAL front end injection line and ion sources

    Science.gov (United States)

    Karns, Patrick R.

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  16. Low power analog readout front-end electronics for time and energy measurements

    International Nuclear Information System (INIS)

    We report on the design and measurements of an analog front-end readout electronics dedicated for silicon microstrip detectors with relatively large capacitance of the order of tens pF for time and energy measurements of incoming pulses. The front-end readout electronics is required to process input pulses with an average rate of 150 kHz/channel with low both power consumption and noise at the same time. In the presented solution the single channel is built of two different parallel processing paths: fast and slow. The fast path includes the fast CR–RC shaper with the peaking time tp=40 ns and is optimized to determine the input charge arrival time. The slow path, which consists of the slow CR–(RC)2 shaper with the peaking time tp=80 ns, is dedicated for low noise accurate energy measurement. The analog front-end electronics was implemented in UMC 180 nm CMOS technology as a prototype ASIC AFE. The AFE chip contains 8 channels with the size of 58 μm×1150 μm each. It has low power dissipation Pdiss=3.1 mW per single channel. The article presents the details of the front-end architecture and the measurement results

  17. Parameters-adjustable front-end controller in digital nuclear measurement system

    International Nuclear Information System (INIS)

    Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (Vin), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

  18. Active pixel sensors in AMS H18/H35 HV-CMOS technology for the ATLAS HL-LHC upgrade

    Science.gov (United States)

    Ristic, Branislav

    2016-09-01

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement signal processing electronics in deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150 V leading to a depletion depth of several 10 μm. Prototype sensors in the AMS H18 180 nm and H35 350 nm HV-CMOS processes were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiations with X-rays and protons revealed a tolerance to ionizing doses of 1 Grad while Edge-TCT studies assessed the effects of radiation on the charge collection. The sensors showed high detection efficiencies after neutron irradiation to 1015neq cm-2 in testbeam experiments. A full reticle size demonstrator chip, implemented in the H35 process is being submitted to prove the large scale feasibility of the HV-CMOS concept.

  19. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    A new pixel module concept is presented utilizing thin sensors and a novel vertical integration technique for the ATLAS pixel detector in view of the foreseen LHC luminosity upgrades. A first set of pixel sensors with active thicknesses of 75 and 150μm has been produced from wafers of standard thickness using a thinning process developed at the Max-Planck-Institut Halbleiterlabor (HLL) and the Max-Planck-Institut fuer Physik (MPP). Pre-irradiation characterizations of these sensors show a very good device yield and high break down voltage. First proton irradiations up to a fluence of 1015 neq cm-2 have been carried out and their impact on the electrical properties of thin sensors has been studied. The novel ICV-SLID vertical integration technology will allow for routing signals vertically to the back side of the readout chips. With this, four-side buttable detector devices with an increased active area fraction are made possible. A first production of SLID test structures was performed and showed a high connection efficiency for different pad sizes and a mild sensitivity to disturbances of the surface planarity.

  20. Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268

    The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

  1. Characterization of Thin Pixel Sensor Modules Interconnected with SLID Technology Irradiated to a Fluence of 2⋅10 15 $n_{eq}$ /cm 2

    CERN Document Server

    Weigell, P; Beimforde, M; Macchiolo, A; Moser, H G; Nisius, R; Richter, R H

    2011-01-01

    A new module concept for future ATLAS pixel detector upgrades is presented, where thin n-in-p silicon sensors are connected to the front-end chip exploiting the novel Solid Liquid Interdiffusion technique (SLID) and the signals are read out via Inter Chip Vias (ICV) etched through the front-end. This should serve as a proof of principle for future four-side buttable pixel assemblies for the ATLAS upgrades, without the cantilever presently needed in the chip for the wire bonding. The SLID interconnection, developed by the Fraunhofer EMFT, is a possible alternative to the standard bump-bonding. It is characterized by a very thin eutectic Cu-Sn alloy and allows for stacking of different layers of chips on top of the first one, without destroying the pre-existing bonds. This paves the way for vertical integration technologies. Results of the characterization of the first pixel modules interconnected through SLID as well as of one sample irradiated to 2⋅10 15 \\,\

  2. Qualification measurements of the voltage supply system as well as conceptionation of a state machine for the detector control of the ATLAS pixel detector

    International Nuclear Information System (INIS)

    The supply system and the control system of the ATLAS pixel detector represent important building blocks of the pixel detector. Corresponding studies of the supply system, which were performed within a comprehensive test system, the so-called system test, with nearly all final components and the effects on the pixel detector are object of this thesis. A further point of this thesis is the coordination and further development of the detector-control-system software under regardment of the different partial systems. A main topic represents thereby the conceptionation of the required state machine as interface for the users and the connection to the data acquisition system

  3. Front-End Board with Cyclone V as a Test High-Resolution Platform for the Auger-Beyond-2015 Front End Electronics

    CERN Document Server

    Szadkowski, Zbigniew

    2014-01-01

    The surface detector (SD) array of the Pierre Auger Observatory containing at present 1680 water Cherenkov detectors spread over an area of 3000 km^2 started to operate since 2004. The currently used Front-End Boards are equipped with no-more produced ACEX and obsolete Cyclone FPGA (40 MSps/15-bit of dynamic range). Huge progress in electronics and new challenges from physics impose a significant upgrade of the SD electronics either to improve a quality of measurements (much higher sampling and much wider dynamic range) or pick-up from a background extremely rare events (new FPGA algorithms based on sophisticated approaches like e.g. spectral triggers or neural networks). Much higher SD sensitivity is necessary to confirm or reject hypotheses critical for a modern astrophysics. The paper presents the Front-End Board (FEB) with the biggest Cyclone V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled with max. 250 MSps @ 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been de...

  4. Ultra-light and stable composite structure to support and cool the ATLAS pixel detector barrel electronics modules

    CERN Document Server

    Olcese, M; Castiglioni, G; Cereseto, R; Cuneo, S; Dameri, M; Gemme, C; Glitza, K W; Lenzen, G; Mora, F; Netchaeva, P; Ockenfels, W; Piano, E; Pizzorno, C; Puppo, R; Rebora, A; Rossi, L; Thadome, J; Vernocchi, F; Vigeolas, E; Vinci, A

    2004-01-01

    The design of an ultra light structure, the so-called "stave", to support and cool the sensitive elements of the Barrel Pixel detector, the innermost part of the ATLAS detector to be installed on the new Large Hadron Collider at CERN (Geneva), is presented. Very high- dimensional stability, minimization of the material and ability of operating 10 years in a high radiation environment are the key design requirements. The proposed solution consists of a combination of different carbon-based materials (impregnated carbon-carbon, ultra high modulus carbon fibre composites) coupled to a thin aluminum tube to form a very light support with an integrated cooling channel. Our design has proven to successfully fulfil the requirements. The extensive prototyping and testing program to fully qualify the design and release the production are discussed.

  5. The Outer Tracker Detector of the HERA-B Experiment. Part II: Front-End Electronics

    CERN Document Server

    Albrecht, H

    2005-01-01

    The HERA-B Outer Tracker is a large detector with 112674 drift chamber channels. It is exposed to a particle flux of up to 2x10^5/cm^2/s thus coping with conditions similar to those expected for the LHC experiments. The front-end readout system, based on the ASD-8 chip and a customized TDC chip, is designed to fulfil the requirements on low noise, high sensitivity, rate tolerance, and high integration density. The TDC system is based on an ASIC which digitizes the time in bins of about 0.5 ns within a total of 256 bins. The chip also comprises a pipeline to store data from 128 events which is required for a deadtime-free trigger and data acquisition system. We report on the development, installation, and commissioning of the front-end electronics, including the grounding and noise suppression schemes, and discuss its performance in the HERA-B experiment.

  6. Problems in Assessment of Novel Biopotential Front-End with Dry Electrode: A Brief Review

    Directory of Open Access Journals (Sweden)

    Gaetano D. Gargiulo

    2014-02-01

    Full Text Available Developers of novel or improved front-end circuits for biopotential recordings using dry electrodes face the challenge of validating their design. Dry electrodes allow more user-friendly and pervasive patient-monitoring, but proof is required that new devices can perform biopotential recording with a quality at least comparable to existing medical devices. Aside from electrical safety requirement recommended by standards and concise circuit requirement, there is not yet a complete validation procedure able to demonstrate improved or even equivalent performance of the new devices. This short review discusses the validation procedures presented in recent, landmark literature and offers interesting issues and hints for a more complete assessment of novel biopotential front-end.

  7. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N. [Oak Ridge National Lab., TN (United States); Allen, M.D. [Univ. of Tennessee, Knoxville, TN (United States); Boissevain, J. [Los Alamos National Lab., NM (United States)] [and others

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented.

  8. Development of a front end controller/heap manager for PHENIX

    Energy Technology Data Exchange (ETDEWEB)

    Ericson, M.N.; Allen, M.D.; Musrock, M.S.; Walker, J.W.; Britton, C.L. Jr.; Wintenberg, A.L.; Young, G.R.

    1996-12-31

    A controller/heap manager has been designed for applicability to all detector subsystem types of PHENIX. the heap manager performs all functions associated with front end electronics control including ADC and analog memory control, data collection, command interpretation and execution, and data packet forming and communication. Interfaces to the unit consist of a timing and control bus, a serial bus, a parallel data bus, and a trigger interface. The topology developed is modular so that many functional blocks are identical for a number of subsystem types. Programmability is maximized through the use of flexible modular functions and implementation using field programmable gate arrays (FPGAs). Details of unit design and functionality will be discussed with particular detail given to subsystems having analog memory-based front end electronics. In addition, mode control, serial functions, and FPGA implementation details will be presented.

  9. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  10. Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

    Directory of Open Access Journals (Sweden)

    Daniele Borio

    2015-01-01

    Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

  11. Onboard Calibration Circuit for the Front-end Electronics of DAMPE BGO Calorimeter

    CERN Document Server

    Zhang, De-Liang; Zhang, Jun-Bin; Wang, Qi; Ma, Si-Yuan; Gao, Shan-Shan; Shen, Zhong-Tao; Jiang, Di; Guo, Jian-Hua; Liu, Shu-Bin; An, Qi

    2015-01-01

    An onboard calibration circuit has been designed for the front-end electronics (FEE) of DAMPE BGO Calorimeter. It is mainly composed of a 12 bit DAC, an operation amplifier and an analog switch. Test results showed that a dynamic range of 0 ~ 30 pC with a precision of 5 fC was achieved, which meets the requirements of the front-end electronics. Furthermore, it is used to test the trigger function of the FEEs. The calibration circuit has been implemented and verified by all the environmental tests for both Qualification Model and Flight Model of DAMPE. The DAMPE satellite will be launched at the end of 2015 and the calibration circuit will perform onboard calibration in space.

  12. A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

    CERN Document Server

    Beccherle, R; Guerra, A D; Folli, M; Marchesini, R; Bisogni, M G; Ceccopieri, A; Rosso, V; Stefanini, A; Tripiccione, R; Kipnis, I

    1999-01-01

    An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 mu m CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution.

  13. FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

    Energy Technology Data Exchange (ETDEWEB)

    Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

    1989-05-01

    The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs.

  14. A MEMS-Based Power-Scalable Hearing Aid Analog Front End.

    Science.gov (United States)

    Deligoz, I; Naqvi, S R; Copani, T; Kiaei, S; Bakkaloglu, B; Sang-Soo Je; Junseok Chae

    2011-06-01

    A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 μ W from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-μ m complementary metal-oxide semciconductor TSMC process.

  15. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del;

    2015-01-01

    simplifies this by making few fully frequency tunable Tx and Rx chains that each cover multiple bands. Three implementations of antenna systems for the proposed architecture are shown and discussed. They all consist of separate Rx and Tx antennas with more than 25 dB of isolation in between. Combined......This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture...... with additional tunable Rx and Tx filters the Rx/Tx isolation reaches 50 dB which is comparable with the isolation achieved with commercially available static duplex filters. Based on these antenna designs it is concluded that the proposed architecture is feasible for LTE phones and makes full coverage of all LTE...

  16. Common front end systems for Space Shuttle and Space Station control centers at Johnson Space Center

    Science.gov (United States)

    Uljon, Linda; Muratore, John

    1993-03-01

    In the beginning of the fiscal year 1992, the development organizations of Johnson Space Center (JSC) were poised to begin two major projects: the Space Station Control Center and the refurbishment of the telemetry processing area of the Space Shuttle Mission Control Center. A study team established that a common front end concept could be used and could reduce development costs for both projects. A standard processor was defined to support most of the front end functions of both control centers and supports a consolidation of control positions which effectively reduces operations cost. This paper defines that common concept and describes the progress that has been made in development of the Consolidated Communications Facility (CCF) during the past year.

  17. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  18. General-Purpose Front End for Real-Time Data Processing

    Science.gov (United States)

    James, Mark

    2007-01-01

    FRONTIER is a computer program that functions as a front end for any of a variety of other software of both the artificial intelligence (AI) and conventional data-processing types. As used here, front end signifies interface software needed for acquiring and preprocessing data and making the data available for analysis by the other software. FRONTIER is reusable in that it can be rapidly tailored to any such other software with minimum effort. Each component of FRONTIER is programmable and is executed in an embedded virtual machine. Each component can be reconfigured during execution. The virtual-machine implementation making FRONTIER independent of the type of computing hardware on which it is executed.

  19. The PRISMA hyperspectral imaging spectrometer: detectors and front-end electronics

    Science.gov (United States)

    Camerini, Massimo; Mancini, Mauro; Fossati, Enrico; Battazza, Fabrizio; Formaro, Roberto

    2013-10-01

    Two detectors, SWIR and VNIR, and relevant front-end electronics were developed in the frame of the PRISMA(Precursore Iperspettrale della Missione Applicativa) project, an hyperspectral instrument for the earth observation. The two detectors were of the MCT type and, in particular, the VNIR was realized by Sofradir by using the CZT(Cadmium Zinc Telluride substrate of the PV diodes) substrate removal to obtain the sensitivity in the visible spectral range. The use of the same ROIC permitted to design an unique front-end electronics. Two test campaigns were carried out: by Sofradir, only on the detectors, and by Selex ES, by using the PRISMA flight electronics. This latter tests demonstrated that was possible to obtain the same detector performance, with respect of those ones obtained by a ground setup, with a flight hardware in terms of noise, linearity and thermal stability.

  20. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... are: • What are the objectives of measurement in radical design? and • What are the most crucial future challenges related with the selection of the relevant measurement objectives? Based on the theoretical part of this paper, our framework of the Balanced Design Front-End Model (BDFEM) for measuring...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

  1. Topology investigation of front end DC/DC converter for distributed power system

    OpenAIRE

    Yang, Bo

    2003-01-01

    Topology Investigation of Front End DC/DC Power Conversion for Distributed Power System by Bo Yang Fred C. Lee, Chairman Electrical Engineering (Abstract) With the fast advance in VLSI technology, smaller, more powerful digital system is available. It requires power supply with higher power density, lower profile and higher efficiency. PWM topologies have been widely used for this application. Unfortunately, hold up time requirement put huge penalties on the performance o...

  2. Modification of a Tractor Dynamic Model Considering the Rotatable Front End

    OpenAIRE

    Li, Zhen; Mitsuoka, Muneshi; Inoue, Eiji; OKAYASU, Takashi; Hirai, Yasumaru; Zhu, Zhongxiang

    2015-01-01

    A mathematical model for tractor dynamics was expanded by considering the rotatable tractor front end. The fundamental shortcoming of the simplified model was revealed by the loss of contact of the tire with a rigid horizontal surface in an obstacle–passing case. Further shortcom–ings of the simplified model arise from aspects of the motion and vibration characteristics. The improved model provides a better and more realistic representation of the tire–ground contact condition and is applicab...

  3. A Low-noise front-end circuit for 2D cMUT arrays

    OpenAIRE

    Güler, Ülkühan; Guler, Ulkuhan; Bozkurt, Ayhan

    2006-01-01

    cMUT technology enables 2D array design with front-end electronic integration through flip-chip bonding or cMUT-on-CMOS process. The size of a 2D array element is constrained in both dimensions due to the aperture sampling criteria, and therefore should be less than or equal to the half of the wavelength in both dimensions. Considering large parasitic capacitances introduced by the interconnections, such small transducer elements necessitate integrated low noise frontends for achieving accept...

  4. Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

    International Nuclear Information System (INIS)

    Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al2O3)- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

  5. A front-end automation tool supporting design, verification and reuse of SOC

    Institute of Scientific and Technical Information of China (English)

    严晓浪; 余龙理; 王界兵

    2004-01-01

    This paper describes an in-house developed language tool called VPerl used in developing a 250 MHz 32-bit high-performance low power embedded CPU core. The authors showed that use of this tool can compress the Verilog code by more than a factor of 5, increase the efficiency of the front-end design, reduce the bug rate significantly. This tool can be used to enhance the reusability of an intellectual property model, and facilitate porting design for different platforms.

  6. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    OpenAIRE

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels; Krozer, Viktor

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subharmonic sampling to sample directly at the RF-frequency, this radiometer obtains a fully polarimetric response and enables detection and removal of radio frequency interference (RFI). A more compact AF...

  7. Advances in Digital Front-End and Software RF Processing: Part II

    Institute of Scientific and Technical Information of China (English)

    2011-01-01

    In the first editorial of this two-part special issue, we pointed out that one of the biggest trends in wireless broadband, radar, sonar, and broadcasting technology is software RF processing and digital front-end [1]. Thistrend encompasses signal processing algorithms and integrated circuit design and includes digital pre-distortion (DPD), conversions between digital and analog signals, digita up-conversion (DUC), digital down-conversion (DDC), DC offset,

  8. A differential low-voltage high gain current-mode integrated RF receiver front-end

    Energy Technology Data Exchange (ETDEWEB)

    Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

    2011-02-15

    A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

  9. A CLIMATE OF PSYCHOLOGICAL SAFETY ENHANCES THE SUCCESS OF FRONT END TEAMS

    OpenAIRE

    ANN-MARIE I. NIENABER; VERENA HOLTORF; JENS LEKER; GERHARD SCHEWE

    2015-01-01

    This paper contributes to the discussion about initiative in teams at the front end of new product development processes (innovative teams). In contrast to the general opinion presented in the literature, this study points out that unstructured innovative teams are as much initiative in developing new ideas or in finding quick solutions when compared to structured innovative teams. Therefore we analyse the relationship between teamwork quality and team initiative in structured and unstructure...

  10. An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

    International Nuclear Information System (INIS)

    We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

  11. An ECG recording front-end with continuous-time level-crossing sampling.

    Science.gov (United States)

    Li, Yongjia; Mansano, Andre L; Yuan, Yuan; Zhao, Duan; Serdijn, Wouter A

    2014-10-01

    An ECG recording front-end with a continuous- time asynchronous level-crossing analog-to-digital converter (LC-ADC) is proposed. The system is a voltage and current mixed-mode system, which comprises a low noise amplifier (LNA), a programmable voltage-to-current converter (PVCC) as a programmable gain amplifier (PGA) and an LC-ADC with calibration DACs and an RC oscillator. The LNA shows an input referred noise of 3.77 μVrms over 0.06 Hz-950 Hz bandwidth. The total harmonic distortion (THD) of the LNA is 0.15% for a 10 mVPP input. The ECG front-end consumes 8.49 μW from a 1 V supply and achieves an ENOB up to 8 bits. The core area of the proposed front-end is 690 ×710 μm2, fabricated in a 0.18 μm CMOS technology. PMID:25330494

  12. Status of the Control Sytem for the Front-End of the Spallation Neutron Source

    CERN Document Server

    Lewis, S A; Cull, P T

    2001-01-01

    The Spallation Neutron Source (SNS) is a partnership between six laboratories. To ensure a truly integrated control system, many standards have been agreed upon, including the use of EPICS as the basic toolkit. However, unique within the partnership is the requirement for Lawrence Berkeley National Lab, responsible for constructing the Front End, to operate it locally before shipping it to the Oak Ridge National Lab (ORNL) site. Thus, its control system must be finished in 2001, well before the SNS completion date of 2006. Consequently many decisions regarding interface hardware, operator screen layout, equipment types, and so forth had to be made before the other five partners had completed their designs. In some cases the Front-End has defined a standard by default; in others an upgrade to a new standard is anticipated by ORNL later. Nearly all Front-End devices have been commissioned with the EPICS control system. Of the approximately 1500 signals required, about 60% are now under daily operational use. Th...

  13. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  14. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  15. 45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

    Science.gov (United States)

    Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

    2012-07-30

    In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W. PMID:23038384

  16. An 8 channel GaAs IC front-end discriminator for RPC detectors

    CERN Document Server

    Giannini, F; Orengo, G; Cardarelli, R

    1999-01-01

    Although not traditionally considered for particle detector readout, circuit solutions based upon GaAs IC technologies can offer considerable performance advantages in high speed detector signal processing: high f sub T devices, such as the GaAs MESFET, allow the realization of front-end tuned amplifiers and comparators with the same detector time resolution. Such a feature is well-suited for RPC particle detectors, characterized by short pulse duration and constant shaping responses. A new design procedure shows the suitability of high speed narrow band GaAs amplifiers as voltage-sensitive input stages of front-end discriminators to perform the required voltage amplification for the following comparator, ensuring, at the same time, SNR optimisation, high gain and low power consumption. As an application of the proposed approach, a full-custom analog chip has been designed and realized using 0.6 mu m GaAs MESFET technology from Triquint foundry. Eight channels of a front-end discriminator composed of a tuned ...

  17. Implementing method of optimum front-end conditioner based on Butterworth filter

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    The front-end conditioner is an essential part of digital systems of nuclear spectrometer, which functions in two ways: (1) prevents saturation of the subsequent ADC; (2) limits the bandwidth of frequency to realize anti-aliasing. To realize the above-mentioned functions, an optimum front-end conditioner for a resistive feedback charge-sensitive preamplifier is designed. In the conditioner, the pole-zero compensation (P/Z compensation) technique was used to effectively filter signals from the preamplifier. The Butterworth filter was improved after the pole-zero position was optimally set up to shape the wave of output, which tallied with the whole system. The front-end conditioner can resolve the aberration of waveform of nuclear signals in a regular Butterworth filter. Compared with the traditional triple-pole filtering circuitry, the circuitry of this conditioner is more compact and flexible.Moreover, its output waveform is more symmetrical and the signal-to-noise ratio (SNR) is higher. The improvement in the resolution of spectrometer is also significant.

  18. Front End Design of a Multi-GeV H-minus Linac

    CERN Document Server

    Ostroumov, Peter; Romanov, Gennady; Shepard, Kenneth; William Foster, G

    2005-01-01

    The proposed 8-GeV driver at FNAL is based on ~480 independently phased SC resonators. Significant cost saving is expected by using an rf power fan out from high-power klystrons to multiple cavities. Successful development of superconducting (SC) multi-spoke resonators operating at ~345-350 MHz provides a strong basis for their application in the front end of multi-GeV linear accelerators. Such a front-end operating at 325 MHz would enable direct transition to high-gradient 1300 MHz SC TESLA-style cavities at ~400 MeV. The proposed front end consists of 5 sections: a conventional RFQ, room-temperature (RT) cross-bar H-type (CH) cavities, single-, double- and triple-spoke superconducting resonators. For several reasons which are discussed in this paper there is a large advantage in using independently phased RT CH-cavities between the RFQ and SC sections in the energy range 3-15 MeV.

  19. FBI Fingerprint Image Capture System High-Speed-Front-End throughput modeling

    Energy Technology Data Exchange (ETDEWEB)

    Rathke, P.M.

    1993-09-01

    The Federal Bureau of Investigation (FBI) has undertaken a major modernization effort called the Integrated Automated Fingerprint Identification System (IAFISS). This system will provide centralized identification services using automated fingerprint, subject descriptor, mugshot, and document processing. A high-speed Fingerprint Image Capture System (FICS) is under development as part of the IAFIS program. The FICS will capture digital and microfilm images of FBI fingerprint cards for input into a central database. One FICS design supports two front-end scanning subsystems, known as the High-Speed-Front-End (HSFE) and Low-Speed-Front-End, to supply image data to a common data processing subsystem. The production rate of the HSFE is critical to meeting the FBI`s fingerprint card processing schedule. A model of the HSFE has been developed to help identify the issues driving the production rate, assist in the development of component specifications, and guide the evolution of an operations plan. A description of the model development is given, the assumptions are presented, and some HSFE throughput analysis is performed.

  20. All Fiber Technology for High-Energy Petawatt Front End Laser Systems

    Energy Technology Data Exchange (ETDEWEB)

    Dawson, J W; Liao, Z M; Jovanovic, I; Wattellier, B; Beach, R; Payne, S A; Barty, C P J

    2003-09-05

    We are developing an all fiber front end for the next generation high-energy petawatt (HEPW) laser at Lawrence Livermore National Laboratory (LLNL). The ultimate goal of the LLNL HEPW effort is to generate 5-kJ pulses capable of compression to 5ps at 1053nm, enabling advanced x-ray backlighters and possible demonstration of fast ignition. We discuss the front-end of the laser design from the fiber master oscillator, which generates the mode-locked 20nm bandwidth initial pulses through the 10mJ output of the large flattened mode (LFM) fiber amplifier. Development of an all fiber front end requires technological breakthroughs in the key areas of the master oscillator and fiber amplification. Chirped pulse amplification in optical fibers has been demonstrated to 1mJ. Further increase is limited by the onset of stimulated Raman scattering (SRS). We have recently demonstrated a new flattened mode fiber technology, which reduces peak power for a given energy and thus the onset of SRS. Controlled experiments with 1st generation fibers yielded 0.5mJ of energy while significantly increasing the point at which nonlinear optical effects degrade the amplified pulse. In this paper we will discuss our efforts to extend this work to greater than 20mJ using our large flattened mode fiber amplifier.

  1. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    Institute of Scientific and Technical Information of China (English)

    Mehmood A wan; Yannick Le Moullec; Peter Koch; Fred Harris

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N-path polyphase filter. Such a system allows resampling by arbitrary ratios while performing baseband aliasing from center frequencies at Nyquist zones that are not multiples of the output sample rate. This resampling technique is based on sliding cyclic data load interacting with cyclic-shifted coefficients. A non-maximally-decimated polyphase filterbank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study for embedded resamp/ing in SDR front-ends. These modes are (i) maximally decimated, (ii) Under-decimated, (iii) over-decimated, and combined up- and down-sampling with (iv) single stride length, and (v) multiple stride lengths. These modes can be used to obtain any required rational sampling rate change in an SDR front-end based on a polyphase channelizer. They can also be used for translation to and from arbitrary center frequencies that are unrelated to the output sample rates.

  2. Qualification measurements of the voltage supply system as well as conceptionation of a state machine for the detector control of the ATLAS pixel detector; Qualifizierungsmessungen des Spannungsversorgungssystems sowie Konzeptionierung einer Zustandsmaschine fuer die Detektorkontrolle des ATLAS-Pixeldetektors

    Energy Technology Data Exchange (ETDEWEB)

    Schultes, Joachim

    2007-02-15

    The supply system and the control system of the ATLAS pixel detector represent important building blocks of the pixel detector. Corresponding studies of the supply system, which were performed within a comprehensive test system, the so-called system test, with nearly all final components and the effects on the pixel detector are object of this thesis. A further point of this thesis is the coordination and further development of the detector-control-system software under regardment of the different partial systems. A main topic represents thereby the conceptionation of the required state machine as interface for the users and the connection to the data acquisition system.

  3. Radiationhard components for the control system of a future ATLAS pixel detector

    CERN Document Server

    Becker, K; Kersten, S; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2015-01-01

    will include a new pixel detector. A completely new detector control system (DCS) for this pixel detector will be required in order to cope with the substantial increase in radiation at the HL-LHC. The DCS has to have a very high reliability and all components installed within the detector volume have to be radiationhard. This will ensure a safe operation of the pixel detector and the experiment. A further design constraint is the minimization of the used material and cables in order to limit the impact on the tracking performance to a minimum. To meet these requirements we propose a DCS network which consists of a DCS chip and a DCS controller. In the following we present the development of the first prototypes for the DCS chip and the DCS controller with a special focus on the communication interface, radiation hardness and robustness against single event upsets.

  4. The Read-Out Driver (ROD) card for the ATLAS experiment: commissioning for the IBL detector and upgrade studies for the Pixel Layers 1 and 2

    CERN Document Server

    Travaglini, R; The ATLAS collaboration; Bindi, M; Falchieri, D; Gabrielli, A; Lama, L; Chen, S P; Hsu, S C; Hauck, S; Kugel, A; Flick, T; Wensing, M

    2013-01-01

    The upgrade of the ATLAS experiment at LHC foresees the insertion of an innermost silicon layer, called Insertable B-layer (IBL). IBL read-out system will be equipped with new electronics. The Readout-Driver card (ROD) is a VME board devoted to data processing, configuration and control. A pre-production batch has been delivered in order to perform tests with instrumented slices of the overall acquisition chain, aiming to finalize strategies for system commissioning. In this contribution both setups and results will be described, as well as preliminary studies on changes in order to adopt the ROD for the ATLAS Pixel Layers 1 and 2.

  5. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  6. A front-end readout Detector Board for the OpenPET electronics system

    OpenAIRE

    Choong, W. -S.; Abu-Nimeh, F.; Moses, W. W.; Peng, Q.; Vu, C.Q.; Wu, J.-Y.

    2015-01-01

    We present a 16-channel front-end readout board for the OpenPET electronics system. A major task in developing a nuclear medical imaging system, such as a positron emission computed tomograph (PET) or a single-photon emission computed tomograph (SPECT), is the electronics system. While there are a wide variety of detector and camera design concepts, the relatively simple nature of the acquired data allows for a common set of electronics requirements that can be met by a flexible, scalable, an...

  7. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  8. Front-End Electronics for the Dark Energy Survey Camera (DECam)

    Science.gov (United States)

    Shaw, Theresa M.; Huffman, D.; Kozlovsky, M.; Olsen, J.; Stuermer, W.; Barcelo, M.; Cardiel, L.; Castilla, J.; DeVicente, J.; Martinez, G.; Moore, P.; Schmidt, R.

    2006-12-01

    The front-end electronics design for the Dark Energy Survey Camera (DECam) is based on the MONSOON Image Acquisition System that was developed by the National Optical Astronomy Observatory (NOAO). MONSOON systems are currently being used to test and characterize CCDs. The Dark Energy Survey group both in the U.S. and Spain will produce custom versions of these systems for use in the production readout that will better match the requirements of a large focal plane of 70+ CCDs and the tight space constraints of a prime focus instrument. The customization of the MONSOON boards and the electronics path will be presented.

  9. Characterization of front-end electronics for CZT based handheld radioisotope identifier

    Energy Technology Data Exchange (ETDEWEB)

    Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

    2016-01-22

    A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

  10. Wideband Fully-Programmable Dual-Mode CMOS Analogue Front-End for Electrical Impedance Spectroscopy

    OpenAIRE

    Valente, V.; Demosthenous, A.

    2016-01-01

    This paper presents a multi-channel dual-mode CMOS analogue front-end (AFE) for electrochemical and bioimpedance analysis. Current-mode and voltage-mode readouts, integrated on the same chip, can provide an adaptable platform to correlate single-cell biosensor studies with large-scale tissue or organ analysis for real-time cancer detection, imaging and characterization. The chip, implemented in a 180-nm CMOS technology, combines two current-readout (CR) channels and four voltage-readout (VR) ...

  11. THz semiconductor-based front-end receiver technology for space applications

    Science.gov (United States)

    Mehdi, Imran; Siegel, Peter

    2004-01-01

    Advances in the design and fabrication of very low capacitance planar Schottky diodes and millimeter-wave power amplifiers, more accurate device and circuit models for commercial 3-D electromagnetic simulators, and the availability of both MEMS and high precision metal machining, have enabled RF engineers to extend traditional waveguide-based sensor and source technologies well into the TI-Iz frequency regime. This short paper will highlight recent progress in realizing THz space-qualified receiver front-ends based on room temperature semiconductor devices.

  12. CMOS front-end for duobinary data over 50-m SI-POF links

    Science.gov (United States)

    Aguirre, J.; Guerrero, E.; Gimeno, C.; Sánchez-Azqueta, C.; Celma, S.

    2015-06-01

    This paper presents a front-end for short-reach high-speed optical communications that compensates the limited bandwidth of 1-mm 50-m step-index plastic optical fiber (SI-POF). For that purpose, it combines two techniques: continuous-time equalization and duobinary modulation. An addition of both enables the receiver to operate at 3.125 Gbps. The prototype contains a transimpedance amplifier, a continuous-time equalizer and a duobinary decoder. The prototype has been implemented in a cost-effective 0.18-μm CMOS process and is fed with 1.8 V.

  13. Balancing research and organizational capacity building in front-end project design

    DEFF Research Database (Denmark)

    Hjortsø, Carsten Nico Portefée; Meilby, Henrik

    2013-01-01

    phase of RCB partnerships and examine how they influence the balance between performing collaborative research and developing general organizational capacity. Data collection was based on a survey (n = 25), and individual interviews and focus group discussions with 17 Danish project managers from...... is more complex. We identify 11 specific factors influencing front-end project management related to structure, process and relationship, and we theorize about how these factors influence the choice between research and more general capacity development activities. Copyright © 2013 John Wiley & Sons, Ltd...

  14. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    Product-service systems (PSS) adoption has increased over the last years due to its potential for innovative value creation. However, the identification of ideas and opportunities in the innovation planning and the structuring of PSS projects are still incipient in organizations, following the same...... be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

  15. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions. PMID:20192390

  16. Design of an Ultra-Low Noise Analogue Front-End for Fast Voltage Pulses Measurement

    CERN Document Server

    AUTHOR|(SzGeCERN)712364; Arpaia, Pasquale; Cerqueira Bastos, Miguel; Martino, Michele

    2015-01-01

    A 15MS/s, 10 ppm repeatable acquisition system to characterize 3 μs rise-time trapezoidal voltage pulses is proposed. The system is based mainly on a low-noise, 5MHz bandwidth analog front-end. In this paper, the requirements, the concept and physical design are illustrated. Simulation results aimed at assessing the circuit performance are presented. An experimental case study on the characterization of a pulsed power supply for the klystrons modulators of the Compact Linear Collider (CLIC) under study at CERN is reported. In particular, the experimental metrological characterization of the prototype in terms of bandwidth and noise is presented.

  17. Implementation in a FPGA of a configurable emulator of the LHCb Upgrade front end electronics

    CERN Document Server

    Pena Colaiocco, Diego Leonardo

    2016-01-01

    The LHCb collaboration at CERN is working towards the upgrade of the experiment, to be performed in 2019. As a part of that effort the electronics of the detector are being redesigned. There exist, already, prototypes of the back end boards. Extensive testing is required in order to check that they behave in the proper way. This work consisted in the implementation of an emulator of the front end electronics in order to test the back end prototypes. A C++ library that generates the same data as the emulator was also designed with the aim of doing, in the future, real time checking of the behaviour of the prototype.

  18. SYSTEMATIC METHOD TO GENERATE NEW IDEAS IN FUZZY FRONT END USING TRIZ

    Institute of Scientific and Technical Information of China (English)

    TAN Runhua; MA Lihui; YANG Bojun; SUN Jianguang

    2008-01-01

    The obstacle for idea generation in fuzzy front end (FFE) is difficult to apply knowledge in different fields for designers. Theory of inventive problem solving TRIZ and computer-aided innovation systems (CAIs) which are TRIZ-base software systems with a knowledge base provide a framework for knowledge application in different fields. The major methods in TRIZ are selected, which have four types. The problems to be solved for each method are summarized and mapping from the problems to the methods is given. Systematic method with eight paths to integrate the methods and problems is formed. A case study shows the idea generation in FFE using the integrated method step by step.

  19. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  20. Computer Aided Design of Microwave Front-End Components and Antennas for Ultrawideband Systems

    Science.gov (United States)

    Almalkawi, Mohammad J.

    This dissertation contributes to the development of novel designs, and implementation techniques for microwave front-end components and packaging employing both transmission line theory and classical circuit theory. For compact realization, all the presented components have been implemented using planar microstrip technology. Recently, there has been an increase in the demand for compact microwave front-ends which exhibit advanced functions. Under this trend, the development of multiband front-end components such as antennas with multiple band-notches, dual-band microwave filters, and high-Q reconfigurable filters play a pivotal role for more convenient and compact products. Therefore, the content of this dissertation is composed of three parts. The first part focuses on packaging as an essential process in RF/microwave integration that is used to mitigate unwanted radiations or crosstalk due to the connection traces. In printed circuit board (PCB) interconnects, crosstalk reduction has been achieved by adding a guard trace with/without vias or stitching capacitors that control the coupling between the traces. In this research, a new signal trace configuration to reduce crosstalk without adding additional components or guard traces is introduced. The second part of this dissertation considers the inherent challenges in the design of multiple-band notched ultrawideband antennas that include the integration of multilayer antennas with RF front-ends and the realization of compact size antennas. In this work, a compact UWB antenna with quad band-notched frequency characteristics was designed, fabricated, and tested demonstrating the desired performance. The third part discusses the design of single- and dual-band dual-mode filters exhibiting both symmetric and asymmetric transfer characteristics. In dual-mode filters, the numbers of resonators that determine the order of a filter are reduced by half while maintaining the performance of the actual filter order. Here, in

  1. How can HR practices support front-end innovation and increase the innovativeness of companies?

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Andersen, Torben

    2014-01-01

    This theoretical review is investigating how selected HR practices can help overcome the challenges companies face in establishing a basis for continuous innovation and thereby economic performance. In particular, the front end of innovation is being emphasised as a key element in companies......' innovativeness. If HR is to support these activities, focus should be on broader issues such as team-based organising, founded on a questioning attitude and a management style with a high level of empowerment. In addition, traditional HR themes such as recruitment, training and development have...

  2. Performance of the Fully Digital FPGA-based Front-End Electronics for the GALILEO Array

    CERN Document Server

    Barrientos, D; Bazzacco, D; Bortolato, D; Cocconi, P; Gadea, A; González, V; Gulmini, M; Isocrate, R; Mengoni, D; Pullia, A; Recchia, F; Rosso, D; Sanchis, E; Toniolo, N; Ur, C A; Valiente-Dobón, J J

    2014-01-01

    In this work we present the architecture and results of a fully digital Front End Electronics (FEE) read out system developed for the GALILEO array. The FEE system, developed in collaboration with the Advanced Gamma Tracking Array (AGATA) collaboration, is composed of three main blocks: preamplifiers, digitizers and preprocessing electronics. The slow control system contains a custom Linux driver, a dynamic library and a server implementing network services. The digital processing of the data from the GALILEO germanium detectors has demonstrated the capability to achieve an energy resolution of 1.53 per mil at an energy of 1.33 MeV.

  3. Policy, price formation, and the front end. A market-clearing model

    International Nuclear Information System (INIS)

    Demand for low enriched uranium (LEU) is met by an evolving combination of primary and secondary uranium sources and enrichment services. A market-clearing model to depict the time evolution of trade-offs between these industries under various policy and LEU demand scenarios is presented. By fixing short-run LEU demand, the model solves for the consumption of primary and secondary uranium and separative work units (SWUs) that minimizes overall front-end costs. Assuming frictionless markets at equilibrium, it projects cost minimizing tails U-235 enrichment, SWU and primary uranium prices over the next two decades by identifying producing and price-setting mines and enrichment facilities. (author)

  4. An analog bipolar-JFET master slice array for front-end electronics design

    International Nuclear Information System (INIS)

    An analog bipolar-JFET Master Slice Array (MSA) has been designed for implementation of ICs used in nuclear physics front-end electronics. The universal conception of MSAs active and passive elements provides great functional complexity to ICs in using them. The quality of active element parameters, number and values of available resistors and capacitors made it possible to integrate a four channel amplifier-shaper-discriminator with a base line restorer into the MSA die with dimensions 2.7 mmx3.6 mm. Eight-channel ICs can be made by connection of two chips by metal wiring on a wafer

  5. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  6. System Electronics for the ATLAS Upgraded Strip Detector

    CERN Document Server

    Affolder, T; The ATLAS collaboration; Clark, A; Dabrowskic, W; Dewitt, J; Diez Cornell, S; Dressdant, N; Fadeyev, V; Farthouat, P; Ferrere, D; Greenall, A; Grillo, A; Kaplon, J; Key-Charriere, M; La Marra, D; Lipeles, E; Lynn, D; Newcomer, M; Pereirab, F; Phillips, P; Spencer, E; Swientekc, K; Warren, M; Weidberg, A

    2013-01-01

    The basic concept of the front-end system of the Silicon Strip Detector in the Atlas Detector upgraded for the HL-LHC is being elaborated and proposed. The readout electronics of this new detector is based on front-end chips (ABC130), Hybrid Controller chips (HCC) and End of Stave Controller chips (EOSC). This document defines the basic functionality of the front-end system and of the different ASICs.

  7. Design, fabrication, installation and commissioning of water-cooled beam viewer for undulator front-ends of Indus-2

    International Nuclear Information System (INIS)

    A water-cooled beam viewer is developed indigenously to observe the bright synchrotron light coming from recently installed undulators in Indus-2 storage ring at RRCAT, Indore. The beam viewer is installed in the undulator front-end. The frontend is a long ultra high vacuum (UHV) assembly consisting of UHV valves, shutters, vacuum pumps and beam diagnostic devices. The front-end acts as an interface between Indus-2 ring and beamline. The beam viewer uses a fluorescent sheet of Chromium doped Alumina (CHROMOX) which produces visible fluorescent light when bright synchrotron light from the undulator falls on it. This visible fluorescent light is observed through a glass window by a CCD camera. The beam viewer has been successfully tested and commissioned in Indus-2 front-end for undulator. At present, the beam viewer is operating under vacuum of 5 x 10-10 mbar in the Indus-2 undulator front-end

  8. Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

    International Nuclear Information System (INIS)

    In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

  9. Development of a detector control system for the serially powered ATLAS pixel detector at the HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Puellen, Lukas

    2015-02-10

    In the years around 2020 the LHC will be upgraded to the HL-LHC. In terms of this upgrade, the ATLAS detector will also be upgraded. This also includes the pixel detector, the innermost of the sub-detectors in ATLAS. Thereby the powering concept of the pixel detector will be changed to reduce the material budget of the detector. From individual powering of each detector module, the concept changes to serial powering, where all modules of a powering group are connected in series. This change makes the development of a new detector control system (DCS) mandatory. Therefore, a new concept for the ATLAS pixel DCS is being developed at the University of Wuppertal. This concept is split into three paths: a safety path, a control path, and a diagnostics path. The safety path is a hard wired interlock system. The concept of this system will not differ significantly, compared to the interlock system of the current detector. The diagnostics path is embedded into the optical data read-out of the detector and will be used for detector tuning with high precision and granularity. The control path supervises the detector and provides a user interface to the hardware components. A concept for this path, including a prototype and proof-of-principle studies, has been developed in terms of this thesis. The control path consists of the DCS network, a read-out and controlling topology created by two types of ASICs: the DCS controller and the DCS chip. These ASICs measure and control all values, necessary for a safe detector operation in situ. This reduces the number of required cables and hence the material budget of the system. For the communication between these ASICs, two very fault tolerant bus protocols have been chosen: CAN bus carries data from the DCS computers, outside of the detector, to the DCS controllers at the edge of the pixel detector. For the communication between the DCS controller and the DCS chip, which is located close to each detector module, an enhanced I2C

  10. Management control systems as a tool to rationalize the intelligence gathering in the front end of innovation

    OpenAIRE

    Toivakka, Satu

    2016-01-01

    The objective of this study is to investigate how management control systems (MCS) are applied in the front end of innovation. Firstly, the focus will be to understand what kind of management controls, if any, are used in the front-end phase of innovation. Secondly, this study will clarify how these controls facilitate the intelligence gathering and the mobilization of the tacit knowledge that then leads to ideas and further to incremental innovations. The literature review explores the ...

  11. Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

    Science.gov (United States)

    Rivetti, Angelo

    2014-11-01

    In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8-10 bit resolution, 50-100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

  12. CPRF/ZTH front-end torus design and fabrication status

    International Nuclear Information System (INIS)

    Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

  13. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  14. Unformatted Digital Fiber-Optic Data Transmission for Radio Astronomy Front-Ends

    CERN Document Server

    Morgan, Matthew A; Castro, Jason J

    2013-01-01

    We report on the development of a prototype integrated receiver front-end that combines all conversions from RF to baseband, from analog to digital, and from copper to fiber into one compact assembly, with the necessary gain and stability suitable for radio astronomy applications. The emphasis in this article is on a novel digital data link over optical fiber which requires no formatting in the front-end, greatly reducing the complexity, bulk, and power consumption of digital electronics inside the antenna, facilitating its integration with the analog components, and minimizing the self-generated radio-frequency interference (RFI) which could leak into the signal path. Management of the serial data link is performed entirely in the back-end based on the statistical properties of signals with a strong random noise component. In this way, the full benefits of precision and stability afforded by conventional digital data transmission are realized with far less overhead at the focal plane of a radio telescope.

  15. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  16. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  17. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  18. Towards a smart Holter system with high performance analogue front-end and enhanced digital processing.

    Science.gov (United States)

    Du, Leilei; Yan, Yan; Wu, Wenxian; Mei, Qiujun; Luo, Yu; Li, Yang; Wang, Lei

    2013-01-01

    Multiple-lead dynamic ECG recorders (Holter) play an important role in the earlier detection of various cardiovascular diseases. In this paper, we present the first several steps towards a 12-lead Holter system with high-performance AFE (Analogue Front-End) and enhanced digital processing. The system incorporates an analogue front-end chip (ADS1298 from TI), which has not yet been widely used in most commercial Holter products. A highly-efficient data management module was designated to handle the data exchange between the ADS1298 and the microprocessor (STM32L151 from ST electronics). Furthermore, the system employs a Field Programmable Gate Array (Spartan-3E from Xilinx) module, on which a dedicated real-time 227-step FIR filter was executed to improve the overall filtering performance, since the ADS1298 has no high-pass filtering capability and only allows limited low-pass filtering. The Spartan-3E FPGA is also capable of offering further on-board computational ability for a smarter Holter. The results indicate that all functional blocks work as intended. In the future, we will conduct clinical trials and compare our system with other state-of-the-arts.

  19. Status report on front end electronics for the EUSO photon detector

    Energy Technology Data Exchange (ETDEWEB)

    Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P

    2002-12-01

    In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

  20. BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

    International Nuclear Information System (INIS)

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

  1. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    International Nuclear Information System (INIS)

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

  2. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  3. Implementation of re-configurable Digital front end module of MIMO-OFDM module using NCO

    Directory of Open Access Journals (Sweden)

    Veena M.B.

    2011-09-01

    Full Text Available This paper focuses on FPGA implementation of Reconfigurable Digital Front end MIMO-OFDM module. The modeling of the MIMO-OFDM system was carried out in MATLAB followed by Verilog HDL implementation. Unlike the conventional OFDM based systems, the Numerically Controlled Oscillators (NCO is used for mapping modulated data onto the sub carriers. The use of NCO in the MIMO-OFDM system reduces the resource utilization of the design on FPGA along with reduced power consumption. The major modules that were designed, which constitute the digital front end module, are Quadrature Phase Shift Keying (QPSK modulator/demodulator, 16-Quadrature Amplitude Modulation (QAM modulator/demodulator and NCOs. Each of the modules was tested for their functionality by developing corresponding test benches. In order to achieve real time reconfigurability of the proposed architecture, the proposed approach is realized on FPGAs optimizing area, power and speed. Reconfigurability of the proposed approach is dependent upon user requirement. Hence the proposed approach can support future generation communication technologies that are based on MIMO-OFDM.

  4. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  5. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    International Nuclear Information System (INIS)

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2. (paper)

  6. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00371978; Gößling, Claus; Pernegger, Heinz

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ...

  7. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  8. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

    Directory of Open Access Journals (Sweden)

    Trong-Hieu Tran

    2016-09-01

    Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

  9. The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors.

    Science.gov (United States)

    Tran, Trong-Hieu; Chao, Paul Chang-Po; Chien, Ping-Chieh

    2016-01-01

    This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an "MR reader" stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5-2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is -0.79-0.95 LSB while the differential non-linearity (DNL) is -0.68-0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within

  10. An Analog Front End for Recording Neuronal Activity in Freely Behaving Small Animals

    Institute of Scientific and Technical Information of China (English)

    WANG Min; ZHANG Xiao; ZHANG Chun-feng; CAO Mao-yong; LI Cai-fang; KONG Hui-min; QIN Feng-ju; YAN Yu-qin

    2007-01-01

    Abstract.Extracting characteristic brain signals and simultaneous recording animals behaving could help us to understand the complex behavior of neuronal ensembles. Here,a system was established to record local field potentials (LFP) and extracellular signal or multiple-unit discharge and behavior synchronously by utilizing electrophysiology and integrated circuit technique. It comprised microelectrodes and micro-driver assembly, analog front end ( AFE), while a computer ( Pentium Ⅲ ) was used as the platform for the graphic user interface, which was developed using the LabVIEW programming language. It was designed as a part of ongoing research to develop a portable wireless neural signal recording system. We believe that this information will be useful for the research of brain-computer interface.

  11. Modeling, simulation, and optimization of a front-end system for acetylene hydrogenation reactors

    Directory of Open Access Journals (Sweden)

    Gobbo R.

    2004-01-01

    Full Text Available The modeling, simulation, and dynamic optimization of an industrial reaction system for acetylene hydrogenation are discussed in the present work. The process consists of three adiabatic fixed-bed reactors, in series, with interstage cooling. These reactors are located after the compression and the caustic scrubbing sections of an ethylene plant, characterizing a front-end system; in contrast to the tail-end system where the reactors are placed after the de-ethanizer unit. The acetylene conversion and selectivity profiles for the reactors are optimized, taking into account catalyst deactivation and process constraints. A dynamic optimal temperature profile that maximizes ethylene production and meets product specifications is obtained by controlling the feed and intercoolers temperatures. An industrial acetylene hydrogenation system is used to provide the necessary data to adjust kinetics and transport parameters and to validate the approach.

  12. The Analog Front-end Prototype Electronics Designed for LHAASO WCDA

    CERN Document Server

    Ma, Cong; Guo, Yu-Xiang; Liu, Jian-Feng; Liu, Shu-Bin; An, Qi

    2015-01-01

    In the readout electronics of the Water Cerenkov Detector Array (WCDA) in the Large High Altitude Air Shower Observatory (LHAASO) experiment, both high-resolution charge and time measurement are required over a dynamic range from 1 photoelectron (P.E.) to 4000 P.E. The Analog Front-end (AFE) circuit is one of the crucial parts in the whole readout electronics. We designed and optimized a prototype of the AFE through parameter calculation and circuit simulation, and conducted initial electronics tests on this prototype to evaluate its performance. Test results indicate that the charge resolution is better than 1% @ 4000 P.E. and remains better than 10% @ 1 P.E., and the time resolution is better than 0.5 ns RMS, which is better than application requirement.

  13. The NA62 LAV front-end electronics and the L0 trigger generating firmware

    CERN Document Server

    Gonnella, Francesco; Corradi, Giovanni; Kozhuharov , Venelin ; Martellotti, Silvia; Moulson, Matthew; Raggi, Mauro; Spadaro, Tommaso

    2014-01-01

    The aim of the NA62 experiment is to measure the branching ratio of the decay K + ! p + n ̄ n to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from p + p 0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is 100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed.

  14. Front-End-Electronics Communication software for multiple detectors in the ALICE experiment

    CERN Document Server

    Bablok, Sebastian; Hartung, G; Keidel, R; Kofler, C; Krawutschke, T; Lindenstruth, V; Röhrich, D

    2006-01-01

    In the ALICE experiment at CERN, the Detector Control System (DCS) employs several interacting software components to accomplish its task of ensuring the correct operation and monitoring of the experiment. This paper describes the Front-End-Electronics Communication (FeeCommunication) software and its role within the DCS. The FeeCommunication software's central task is passing configuration and monitoring data between the top level DCS process control and the field devices of several detectors within ALICE. The lowest level of the FeeCommunication software runs on the DCS boards, specialized embedded systems which are in direct contact with the field devices and are physically located within the detector. The middle and upper layers run on standard PC hardware located in the counting room or other external locations. This paper focuses on the design and implementation of the FeeCommunication software and the steps that were taken to fulfill the imposed reliability and performance requirements, specifically th...

  15. Development of front-end readout electronics for silicon strip detectors

    CERN Document Server

    Qian, Yi; Kong, Jie; Dong, Cheng-Fu; Ma, Xiao-Li; Li, Xiao-Gang

    2011-01-01

    A front-end readout electronics system has been developed for silicon strip detectors. The system uses an application specific integrated circuit (ASIC) ATHED to realize multi-channel E&T measurement. The slow control of ASIC chips is achieved by parallel port and the timing control signals of ASIC chips are provided by the CPLD. The data acquisition is implemented with a PXI-DAQ card. The system software has a user-friendly GUI which uses LabWindows/CVI in Windows XP operating system. Test results showed that the energy resolution is about 1.22 % for alphas at 5.48 MeV and the maximum channel crosstalk of system is 4.6%. The performance of the system is very reliable and suitable for nuclear physics experiments.

  16. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  17. A Survey of Neural Front End Amplifiers and Their Requirements toward Practical Neural Interfaces

    Directory of Open Access Journals (Sweden)

    Eric Bharucha

    2014-11-01

    Full Text Available When designing an analog front-end for neural interfacing, it is hard to evaluate the interplay of priority features that one must upkeep. Given the competing nature of design requirements for such systems a good understanding of these trade-offs is necessary. Low power, chip size, noise control, gain, temporal resolution and safety are the salient ones. There is a need to expose theses critical features for high performance neural amplifiers as the density and performance needs of these systems increases. This review revisits the basic science behind the engineering problem of extracting neural signal from living tissue. A summary of architectures and topologies is then presented and illustrated through a rich set of examples based on the literature. A survey of existing systems is presented for comparison based on prevailing performance metrics.

  18. Front-end signal analysis of the transverse feedback system for SSRF

    Institute of Scientific and Technical Information of China (English)

    HAN Lifeng; YUAN Renxian; YU Luyang; YE Kairong

    2008-01-01

    Multi-bunch instabilities degrade beam quality through increased beam emittance, energy spread and even cause beam loss. A feedback system is used to suppress multi-bunch instabilities associated with resistive wall of the beam ducts, cavity-like structures, and trapped ions. A digital TFS (Transverse Feedback System) is in construction at the SSRF (Shanghai Synchrotron Radiation Facility), which is based on the latest generation of FPGA (Field Programmable Gate Array) processor. Before we get such FPGA digital board, investigation and simulation of the front-end were done in the first place. The signal flow was analyzed by SystemView. Construction and optimization of the entire system is our next goal.

  19. Multi-channel front-end board for SiPM readout

    CERN Document Server

    Auger, M; Goeldi, D; Kreslo, I; Lorca, D; Luethi, M; von Rohr, C Rudolf; Sinclair, J; Weber, M S

    2016-01-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias on the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  20. Indus-2 beam line front end controls using real time operating system

    International Nuclear Information System (INIS)

    Beam Line Front Ends (BLFE) are crucial interfaces between machine user beam lines and INDUS-2 synchrotron radiation source. Twenty-seven beam lines are proposed in INDUS-2 synchrotron facility out of which some are operational by now and many more are about to come. The purpose of these BLFE's is essentially to protect the machine vacuum from beam line failures and vice versa and allow a well co-ordinated and safe usage of machine by its users. For controlling these beam lines, BLFE control system is implemented. The BLFE control system is based on three-layer architecture with equipments connected ate the layer three, Layer two serves the purpose of metadata storage, layer one serves as operator console (GUI). This paper discusses the scheme and architecture of layer two and layer three implementation using RTOS OS-9. The diagnostic features incorporated in the architecture increases the system uptime by quick diagnosis of system faults. (author)

  1. A digital front-end and readout microsystem for calorimetry at LHC--The FERMI project

    Energy Technology Data Exchange (ETDEWEB)

    Dell' Acqua, A.; Hansen, M.; Lofstedt, B.; Vanuxem, J.P. (CERN, Geneva (Switzerland)); Svensson, C.; Yuan, J. (Univ. of Linkoeping (Sweden). Dept. of Physics and Measurement Technology); Hentzell, H. (Univ. of Linkoeping (Sweden). Center for Industrial Microelectronics and Materials Technology); Alippi, C.; Breveglieri, L.; Dadda, L.; Piuri, V.; Salice, F.; Sami, M.; Stefanelli, R. (Sezione INFN, Pavia, Milano (Italy). Dept. di Ellettronica); Cattaneo, P.; Fumagalli, G.; Goggi, V.G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Fisica Nucleare); Brigati, S.; Gatti, U.; Maloberti, F.; Torelli, G. (Univ. e Sezione INFN, Pavia (Italy). Dept. di Electronica); Carlson, P.; Fuglesang, C.; Kerek, A. (Manne Siegbahn Inst. of Physics, Stockholm (Sweden)); Appelquist, G.; Berglund, S.; Bohm, C.; Yamdagni, N. (Univ. of Stockholm (Sweden)); Sundblad, R. (SiCon AB, Linkoeping (Sweden))

    1993-08-01

    The authors present a digital solution to the front-end electronics for calorimetric detectors at future supercolliders based on high speed A/D converters, a fully programmable pipeline/digital filter chain and local intelligence. Questions of error correction, fault-tolerance and system redundancy are also considered. A system integration of a multichannel device in a multichip, Silicon-on-Silicon Microsystem hybrid will be used. This solution allows a new level of integration of complex analog and digital functions, with an excellent flexibility in mixing technologies for the different functional blocks. This type of VLSI multichip integration allows a high degree of programmability at both the function and the system level, and offers the possibility of customizing the microsystem with detector-specific functions.

  2. Performance of the front-end electronics of the ANTARES neutrino telescope

    International Nuclear Information System (INIS)

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  3. Performance of the front-end electronics of the ANTARES neutrino telescope

    Energy Technology Data Exchange (ETDEWEB)

    Aguilar, J.A. [IFIC - Instituto de Fisica Corpuscular, Edificios Investigacion de Paterna, CSIC - Universitat de Valencia, Apdo. de Correos 22085, 46071 Valencia (Spain); Al Samarai, I. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Albert, A. [GRPHE - Institut universitaire de technologie de Colmar, 34 rue du Grillenbreit BP 50568 - 68008 Colmar (France); Anghinolfi, M. [INFN - Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); Anton, G. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Anvar, S. [Direction des Sciences de la Matiere - Institut de recherche sur les lois fondamentales de l' Univers - Service d' Electronique des Detecteurs et d' Informatique, CEA Saclay, 91191 Gif-sur-Yvette Cedex (France); Ardid, M. [Institut d' Investigacio per a la Gestio Integrada de Zones Costaneres (IGIC) - Universitat Politecnica de Valencia. C/ Paranimf, 1. E-46730 Gandia (Spain); Assis Jesus, A.C.; Astraatmadja, T. [FOM Instituut voor Subatomaire Fysica Nikhef, Science Park 105, 1098 XG Amsterdam (Netherlands); Aubert, J.-J. [CPPM - Centre de Physique des Particules de Marseille, CNRS/IN2P3 et Universite de la Mediterranee, 163 Avenue de Luminy, Case 902, 13288 Marseille Cedex 9 (France); Auer, R. [Friedrich-Alexander-Universitaet Erlangen-Nuernberg, Erlangen Centre for Astroparticle Physics, Erwin-Rommel-Str. 1, D-91058 Erlangen (Germany); Baret, B. [APC - Laboratoire AstroParticule et Cosmologie, UMR 7164 (CNRS, Universite Paris 7 Diderot, CEA, Observatoire de Paris) 10, rue Alice Domon et Leonie Duquet 75205 Paris Cedex 13 (France); Basa, S. [LAM - Laboratoire d' Astrophysique de Marseille, Pole de l' Etoile Site de Ch-Gombert, rue Frederic Joliot-Curie 38, 13388 Marseille cedex 13 (France)

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  4. Evaluation of a front-end ASIC for the readout of PMTs in large dynamic range

    CERN Document Server

    Wu, Weihao; Liang, Yu; Yu, Li; Liu, Jianfeng; Liu, Shubin; An, Qi

    2015-01-01

    The Large High Altitude Air Shower Observatory (LHAASO) project has been proposed for the survey and study of cosmic rays. In the LHAASO project, the Water Cherenkov Detector Array (WCDA) is one of major detectors for searching gamma ray sources. A Charge-to-Time Convertor (QTC) ASIC (Application Specification Integrated Circuit) fabricated in Global Foundry 0.35 {\\mu}m CMOS technology, has been developed for readout of Photomultiplier Tubes (PMTs) in the WCDA. This paper focuses on the evaluation of this front-end readout ASIC performance. Test results indicate that the time resolution is better than 400 ps and the charge resolution is better than 1% with large input signals and remains better than 15% @ 1 Photo Electron (P.E.), both beyond the application requirement. Moreover, this ASIC has a weak ambient temperature dependence, low input rate dependence and high channel-to-channel isolation.

  5. Multi-channel front-end board for SiPM readout

    Science.gov (United States)

    Auger, M.; Ereditato, A.; Goeldi, D.; Kreslo, I.; Lorca, D.; Luethi, M.; von Rohr, C. Rudolf; Sinclair, J.; Weber, M. S.

    2016-10-01

    We describe a novel high-speed front-end electronic board (FEB) for interfacing an array of 32 Silicon Photo-multipliers (SiPM) with a computer. The FEB provides individually adjustable bias for the SiPMs, and performs low-noise analog signal amplification, conditioning and digitization. It provides event timing information accurate to 1.3 ns RMS. The signal-to-noise ratio of 12 is attained for the first photo-electron peak. The back-end data interface is realized on the basis of 100 Mbps Ethernet. The design allows daisy-chaining of up to 256 units into one network interface, thus enabling compact and efficient readout schemes for multi-channel scintillating detectors, using SiPMs as photo-sensors.

  6. Harmonic Mitigated Front End Three Level Diode Clamped High Frequency Link Inverter by Using MCI Technique

    Directory of Open Access Journals (Sweden)

    Sreedhar Madichetty

    2014-02-01

    Full Text Available In this paper it proposes a high efficient soft-switching scheme based on zero-voltage-switching (ZVS and zero-current-switching(ZCS principle operated with a simple auxiliary circuit extended range for the front-end isolated DC-AC-DC-AC high power converter with an three phase three level diode clamped multi level inverter by using Minority Charge Carrier inspired optimization technique (MCI with Total Harmonic Distortion(THD,Switching losses, Selective harmonic elimination maintaining with its fundamental as an objective function. Input to the inverter is obtained by the photo voltaic cells and with battery bank. The switching scheme is optimized by MCI technique, analyzed and executed in Matlab and implemented with a digital signal processor (DSP .Experimental results with different loads have observed and shows its effectives, robustness of the applied technique.

  7. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  8. Cognitive radio receiver front-ends RF/analog circuit techniques

    CERN Document Server

    Sadhu, Bodhisatwa

    2014-01-01

    This book focuses on the architecture and circuit design for cognitive radio receiver front-ends.  The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.   • Discusses in detail the circuit-level challenges that exist for cognitive radio systems; • Provides readers with a holistic understanding of RF circuits for cognitive radio systems; • Enables communications engineers and systems designers to design better cognitive radio architectures and communication protocols.

  9. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    CERN Document Server

    Impiombato, D; Mineo, T; Catalano, O; Gargano, C; La Rosa, G; Russo, F; Sottile, G; Billotta, S; Bonanno, G; Garozzo, S; Grillo, A; Marano, D; Romeo, G

    2015-01-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  10. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    Energy Technology Data Exchange (ETDEWEB)

    Impiombato, D., E-mail: Domenico.Impiombato@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Giarrusso, S., E-mail: Giarrusso@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Mineo, T., E-mail: Mineo@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Catalano, O., E-mail: Catalano@iasf-palermo.inaf.it [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G. [INAF, Istituto di Astrofisica Spaziale e Fisica cosmica di Palermo, via U. La Malfa 153, I-90146 Palermo (Italy); Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G. [INAF, Osservatorio Astrofisico di Catania, via S. Sofia 78, I-95123 Catania (Italy)

    2015-09-11

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  11. Characterization and performance of the ASIC (CITIROC) front-end of the ASTRI camera

    Science.gov (United States)

    Impiombato, D.; Giarrusso, S.; Mineo, T.; Catalano, O.; Gargano, C.; La Rosa, G.; Russo, F.; Sottile, G.; Billotta, S.; Bonanno, G.; Garozzo, S.; Grillo, A.; Marano, D.; Romeo, G.

    2015-09-01

    The Cherenkov Imaging Telescope Integrated Read Out Chip, CITIROC, is a chip adopted as the front-end of the camera at the focal plane of the imaging Cherenkov ASTRI dual-mirror small size telescope (ASTRI SST-2M) prototype. This paper presents the results of the measurements performed to characterize CITIROC tailored for the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger linearity and efficiency, as a function of the pulse amplitude. Moreover, we tested its response by performing a set of measurements using a silicon photomultiplier (SiPM) in dark conditions and under light pulse illumination. The CITIROC output signal is found to vary linearly as a function of the input pulse amplitude. Our results show that it is suitable for the ASTRI SST-2M camera.

  12. A CMOS analog front-end chip for amperometric electrochemical sensors

    Science.gov (United States)

    Zhichao, Li; Yuntao, Liu; Min, Chen; Jingbo, Xiao; Jie, Chen

    2015-07-01

    This paper reports a complimentary metal-oxide-semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I2C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma-delta analog to digital converter (Σ-Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm2. Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. Project supported by the National Key Basic Research and Development Project (No. 2015CB352103).

  13. A front-end electronics module for multi-gap resistive plate chambers

    International Nuclear Information System (INIS)

    Background: The output current signal of Multi-gap Resistive Plate Chambers (MRPCs) has low amplitude and fast speed. Purpose: Its amplitude and time information should be obtained in particle Time-of-Flight (TOF) detection. Methods: A simple electronics module for the presentation of the signals from MRPCs to standard existing digitization electronics is described. The circuit is based on 'off-the-shelf' discrete components. An optimization of the values of specific components is required to match the aspects of the MRPCs for the given application. The key electronic noise control plan is also discussed. Results: This electronics module has the excellent features including low prices, convenient making, easy assembling for testing system, etc. Conclusions: This electronics module is an attractive option for the front-end signal processing in MRPCs prototype and bench or beam-testing efforts, as well as in final implementations of small-area particle TOF system with existing data acquisition systems. (authors)

  14. Understanding the Front-end of Large-scale Engineering Programs

    DEFF Research Database (Denmark)

    Lucae, Sebastian; Rebentisch, Eric; Oehmen, Josef

    2014-01-01

    Large engineering programs like sociotechnical infrastructure constructions of airports, plant constructions, or the development of radically innovative, high-tech industrial products such as electric vehicles or aircraft are affected by a number of serious risks, and subsequently commonly suffer......, unclear and incomplete requirements, unclear roles and responsibilities within the program organization, insufficient planning, and unproductive tensions between program management and systems engineering. This study intends to clarify the importance of up-front planning to improve program performance......, to propose a model for the front-end of large-scale engineering programs based on a review of existing, suitable models in literature and to better understand the complexity drivers that are impeding reliable planning and common planning mistakes made in large-scale engineering programs....

  15. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  16. First photon-shutter development for APS insertion device beamline front ends

    Science.gov (United States)

    Shu, Deming; Nian, H. L. Thomas; Wang, Zhibi; Collins, Jeffrey T.; Ryding, David G.; Kuzay, Tuncer M.

    1993-02-01

    One of the most critical components on the Advanced Photon Source (APS) insertion device (ID) beamline front ends is the first photon shutter. It operates in two modes to fully intercept the high total power and high-heat-flux ID photon beam in seconds (normal mode) or in less than 100 ms (emergency fast mode). It is designed to operate in ultra high vacuum (UHV). The design incorporates a multi-channel rectangular bar, bent in a `hockey stick' configuration, with two-point suspension. The flanged end is an articulated bellows with rolling hinges. The actuation end is a spring-assisted, pneumatic fail-safe flexural pivot type. The coolant (water) channels incorporate brazed copper foam to enhance the heat transfer, a tube technology particular to the APS. The design development, and material aspects, as well as the extensive thermal and vibrational analyses in support of the design, are presented in this paper.

  17. System considerations and RF front-end design for integration of satellite navigation and mobile standards

    Directory of Open Access Journals (Sweden)

    A. Miskiewicz

    2009-05-01

    Full Text Available The paper presents the challenges involved in a system design of a robust reconfigurable RF front-end for navigation and mobile standards. Receiver architecture is chosen from the point of view of inter-system interference and 130nm CMOS process characteristics. System concept covers the implementation of GPS, Galileo, UMTS, GSM and CDMA2000 using a Zero-IF architecture with reconfigurable analog and digital path. Feasibility studies of the system cover analysis of the wireless regulations and performance criteria, such as overall gain, noise figure (NF, and 1dB compression point (P1dB of the RF chain, phase noise requirements and VCO tuning range [1]. The presented chip was fabricated in 130 nm CMOS technology. System considerations are confirmed with the chip measurements of gain, noise figure, and linearity. Prospects for the future work are presented including technology shrink.

  18. A low power low noise analog front end for portable healthcare system

    International Nuclear Information System (INIS)

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

  19. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens;

    2009-01-01

    % relative bandwidth. The transmitter uses two amplifiers combined in parallel to generate more than >128 W peak power, with system >60% PAE and 47 dB in-band to out-of-band signal ratio. The four channel receiver features digitally controlled variable gain to achieve more than 100 dB dynamic range, 2.4 d......B noise figure, 160 ns receiver recovery time and -46 dBc 3rd order IMD products. The system comprises also, a digital front-end, a digital signal generator, a microstrip antenna array and a control unit. All the subsystems were integrated, certified and functionally tested, and in May 2008 a successful...

  20. A Test Apparatus for the MAJORANA DEMONSTRATOR Front-end Electronics

    Science.gov (United States)

    Singh, Harjit; Loach, James; Poon, Alan

    2012-10-01

    One of the most important experimental programs in neutrino physics is the search for neutrinoless double-beta decay. The MAJORANA collaboration is searching for this rare nuclear process in the Ge-76 isotope using HPGe detectors. Each detector is instrumented with high-performance electronics to read out and amplify the signals. The part of the electronics close to the detectors, consisting of a novel front-end circuit, cables and connectors, is made of radio-pure materials and is exceedingly delicate. In this work a dedicated test apparatus was created to benchmark the performance of the electronics before installation in the experiment. The apparatus was designed for cleanroom use, with fixtures to hold the components without contaminating them, and included the electronics necessary for power and readout. In addition to testing, the station will find longer term use in development of future versions of the electronics.