WorldWideScience

Sample records for atlas pixel front-end

  1. Dead-time free pixel readout architecture for ATLAS front-end IC

    CERN Document Server

    Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

    1999-01-01

    A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

  2. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  3. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  4. Pixel front-end development in 65 nm CMOS technology

    International Nuclear Information System (INIS)

    Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

    2014-01-01

    Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

  5. Single Event Upsets in the ATLAS IBL Front End ASICs

    CERN Document Server

    Rozanov, Alexander; The ATLAS collaboration

    2018-01-01

    During operation at instantaneous luminosities of up to 2.1 10^{34} cm^{-2} s^{-1} the front end chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, among other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques will be presented.

  6. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  7. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  8. Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Peschke, Richard

    2017-03-15

    As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

  9. Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

    International Nuclear Information System (INIS)

    Peschke, Richard

    2017-03-01

    As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

  10. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  11. Test of ATLAS RPCs Front-End electronics

    International Nuclear Information System (INIS)

    Aielli, G.; Camarri, P.; Cardarelli, R.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Paoloni, A.; Pastori, E.; Santonico, R.

    2003-01-01

    The Front-End Electronics performing the ATLAS RPCs readout is a full custom 8 channels GaAs circuit, which integrates in a single die both the analog and digital signal processing. The die is bonded on the Front-End board which is completely closed inside the detector Faraday cage. About 50 000 FE boards are foreseen for the experiment. The complete functionality of the FE boards will be certificated before the detector assembly. We describe here the systematic test devoted to check the dynamic functionality of each single channel and the selection criteria applied. It measures and registers all relevant electronics parameters to build up a complete database for the experiment. The statistical results from more than 1100 channels are presented

  12. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    Havranek, Miroslav

    2014-09-01

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  13. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    Energy Technology Data Exchange (ETDEWEB)

    Havranek, Miroslav

    2014-09-15

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  14. Single Event Upsets in the ATLAS IBL Front End ASICs

    CERN Document Server

    Rozanov, Alexandre; The ATLAS collaboration

    2018-01-01

    During operation at instantaneous luminosities of up to 2.1 1034 cm2 s−1 frontend chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, amongst other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques are presented.

  15. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  16. Data acquisition at the front-end of the Mu3e pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

    2016-07-01

    The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

  17. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    International Nuclear Information System (INIS)

    Kim, D.; Rinella, G. Aglieri; Cavicchioli, C.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Mager, M.; Chanlek, N.; Collu, A.; Degerli, Y.; Flouzat, C.; Guilloux, F.; Dorokhov, A.; Gajanana, D.; Gao, C.; Kwon, Y.; Lattuca, A.

    2016-01-01

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m 2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented

  18. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    Science.gov (United States)

    Kim, D.; Aglieri Rinella, G.; Cavicchioli, C.; Chanlek, N.; Collu, A.; Degerli, Y.; Dorokhov, A.; Flouzat, C.; Gajanana, D.; Gao, C.; Guilloux, F.; Hillemanns, H.; Hristozkov, S.; Junique, A.; Keil, M.; Kofarago, M.; Kugathasan, T.; Kwon, Y.; Lattuca, A.; Mager, M.; Sielewicz, K. M.; Marin Tobon, C. A.; Marras, D.; Martinengo, P.; Mazza, G.; Mugnier, H.; Musa, L.; Pham, T. H.; Puggioni, C.; Reidt, F.; Riedler, P.; Rousset, J.; Siddhanta, S.; Snoeys, W.; Song, M.; Usai, G.; Van Hoorne, J. W.; Yang, P.

    2016-02-01

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.

  19. Design and implementation of the ATLAS TRT front end electronics

    Science.gov (United States)

    Newcomer, Mitch; Atlas TRT Collaboration

    2006-07-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

  20. Design and implementation of the ATLAS TRT front end electronics

    International Nuclear Information System (INIS)

    Newcomer, Mitch

    2006-01-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

  1. ATLAS ITk Pixel detector

    CERN Document Server

    Gemme, Claudia; The ATLAS collaboration

    2016-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

  2. FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    NARCIS (Netherlands)

    Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Plessl, C.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Zhang, J.

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will

  3. Development of Pixel Front-End Electronics using Advanced Deep Submicron CMOS Technologies

    CERN Document Server

    Havránek, Miroslav; Dingfelder, Jochen

    The content of this thesis is oriented on the R&D; of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore’s laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key pa...

  4. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  5. Development of front-end electronics and TDC LSI for the ATLAS MDT

    CERN Document Server

    Arai, Y

    2000-01-01

    Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

  6. Test system for the production of the Atlas Tile Calorimeter front-end electronics

    International Nuclear Information System (INIS)

    Calvet, David

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

  7. Criteria for setting the width of CCD front end transistor to reach minimum pixel noise

    International Nuclear Information System (INIS)

    Fasoli, L.; Sampietro, M.

    1996-01-01

    The paper gives the criteria to calculate the width of the front end transistor integrated next to the charge sensing electrode of CCD's or, in general, of semiconductor detectors, in order to reach the minimum noise in the readout of the signal charge. The paper, for the first time, accounts for white, series and parallel, and 1/f noise contribution. In addition, it points out two different design criteria depending whether a JFET or a MOSFET is used. The attention given to the JFET is due to a lower 1/f noise component, which makes these transistors more and more appealing as input devices in very high resolution detectors. The paper shows that there is a characteristic width of the FET gate that practically doesn't depend on the noise sources but depends only on the capacitance seen by the charge sensing electrode of the detector, making possible the optimum design of the transistor prior to the knowledge of the real values of the spectral density of the noise sources, which are usually precisely known only at the end of the fabrication process. The paper shows that the pixel noise raises sharply as the transistor gate width departs from its optimum value

  8. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    Venuto, D. de; Corsi, F.; Ohletz, M.J.

    1999-01-01

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  9. Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

    CERN Document Server

    Cooper, B; The ATLAS collaboration

    2012-01-01

    Around 2021 the Large Hadron Collider will be upgraded to provide instantaneous luminosities 5x10^34, leading to excessive rates from the ATLAS Level-1 trigger. We describe a double-buffer front-end architecture for the ATLAS tracker replacement which should enable tracking information to be used in the Level-1 decision. This will allow Level-1 rates to be controlled whilst preserving high efficiency for single lepton triggers at relatively low transverse momentum thresholds pT ~25 GeV, enabling ATLAS to remain sensitive to physics at the electroweak scale. In particular, a potential hardware solution for the communication between the upgraded silicon barrel strip detectors and the external processing within this architecture will be described, and discrete event simulations used to demonstrate that this fits within the tight latency constraints.

  10. Overview of the front end electronics for the Atlas LAR calorimeter

    International Nuclear Information System (INIS)

    Rescia, S.

    1997-11-01

    Proposed experiments for the Large Hadron Collider (LHC) set new demands on calorimeter readout electronics. The very high energy and large luminosity of the collider call for a large number of high speed, large dynamic range readout channels which have to be carefully synchronized. The ATLAS liquid argon collaboration, after more than 5 years of R and D developments has now finalized the architecture of its front end and read-out electronics, which have been written down in its Technical Design Report (TDR). An overview is presented

  11. Tester of the TRT front-end electronics for the ATLAS-experiment

    CERN Document Server

    Hajduk, Z; Kisielewski, B; Kotarba, A; Malecki, P; Natkaniec, Z; Olszowska, J; Ostrowicz, W; Krupinska, G

    2000-01-01

    The VME based tester for front-end electronics of the TRT (Transition Radiation Tracker) detector of the ATLAS-LHC experiment at CERN, Geneva, is described. The TRT read-out electronics for 424576 proportional tubes grouped on many thousands of cards requires stringent quality control after assembly and during installation. The tester provides all required data, pulses, timing and power supplies for tested cards. The essential part of the tester is its software that allows for device handling as well as facilitates functional and statistical tests. The prototype, present design as well as the new design for mass production tests are discussed. (17 refs).

  12. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  13. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    International Nuclear Information System (INIS)

    Anderson, J; Drake, G; Ryu, S; Zhang, J; Borga, A; Boterenbrood, H; Schreuder, F; Vermeulen, J; Chen, H; Chen, K; Lanni, F; Francis, D; Gorini, B; Miotto, G Lehmann; Schumacher, J; Vandelli, W; Levinson, L; Narevicius, J; Roich, A; Plessl, C

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed. (paper)

  14. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    International Nuclear Information System (INIS)

    Alves, J.; Carrio, F.; Moreno, P.; Usai, G.; Valero, A.; Kim, H.Y.; Minashvili, I.; Shalyugin, A.; Reed, R.; Schettino, V.; Souza, J.; Solans, C.

    2013-06-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

  15. Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

    International Nuclear Information System (INIS)

    Manazza, A.; Gaioni, L.; Re, V.

    2011-01-01

    This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end.

  16. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  17. Design of the Front-End Detector Control System of the ATLAS New Small Wheels

    CERN Document Server

    Koulouris, Aimilianos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

  18. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  19. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  20. Irradiation studies of multimode optical fibres for use in ATLAS front-end links

    International Nuclear Information System (INIS)

    Mahout, G.; Pearce, M.; Andrieux, M-L.; Arvidsson, C-B.; Charlton, D.G.; Dinkespiler, B.; Dowell, J.D.; Gallin-Martel, L.; Homer, R.J.; Jovanovic, P.; Kenyon, I.R.; Kuyt, G.; Lundquist, J.; Mandic, I.; Martin, O.; Shaylor, H.R.; Stroynowski, R.; Troska, J.; Wastie, R.L.; Weidberg, A.R.; Wilson, J.A.; Ye, J.

    2000-01-01

    The radiation tolerance of three multimode optical fibres has been investigated to establish their suitability for the use in the front-end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of ∼0.05 dB/m at 330 kGy(Si) and 1x10 15 n(1 MeV Si)/cm 2 and is suitable for use with the inner detector links which operate at 40-80 Mb/s. A graded-index fibre with a predominantly germanium-doped core exhibits an induced attenuation of ∼0.1 dB/m at 800 Gy(Si) and 2x10 13 n(1 MeV Si)/cm 2 and is suitable for the calorimeter links which operate at 1.6 Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower

  1. Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

    International Nuclear Information System (INIS)

    Wardrope, D

    2012-01-01

    The Large Hadron Collider will be upgraded to provide instantaneous luminosity L = 5 × 10 34 cm −2 s −1 , leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20 μs in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of p T ∼ 25 GeV, which will be of great benefit to the future physics programme of ATLAS.

  2. An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

    CERN Document Server

    Porter, Ryan

    This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

  3. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  4. The ALICE silicon pixel detector front-end and read-out electronics

    CERN Document Server

    Kluge, A

    2006-01-01

    The ALICE silicon pixel detector (SPD) comprises the two innermost barrel layers of the ALICE inner tracker system. The SPD includes 120 half staves each of which consists of a linear array of 10 ALICE pixel chips bump bonded to two silicon sensors. Each pixel chip contains 8192 active cells, so the total number of pixel cells in the SPD is ≈107. The tight material budget and the limitation in physical dimensions required by the detector design introduce new challenges for the integration of the on-detector electronics. An essential part of the half stave is a low-mass multi-layer flex that carries power, ground, and signals to the pixel chips. Each half stave is read out using a multi-chip module (MCM). The MCM contains three radiation hard ASICs and an 800 Mbit/s custom developed optical link for the data transfer between the detector and the control room. The detector components are less than 3 mm thick. The production of the half-staves and MCMs is currently under way. Test results as well as on overvie...

  5. Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

    OpenAIRE

    Kim, D; Rinella, G Aglieri; Cavicchioli, C; Chanlek, N; Collu, A; Degerli, Y; Dorokhov, A; Flouzat, C; Gajanana, D; Gao, C; Guilloux, F; Hillemanns, H; Hristozkov, S; Junique, A; Keil, M

    2016-01-01

    ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m(2) tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the ...

  6. Developments of the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Andreazza, Attilio

    2004-01-01

    The ATLAS silicon pixel detector is the innermost tracking device of the ATLAS experiment at the Large Hardon Collider, consisting of more than 1700 modules for a total sensitive area of about 1.7m2 and over 80 million pixel cells. The concept is a hybrid of front-end chips bump bonded to the pixel sensor. The elementary pixel cell has 50μmx400μm size, providing pulse height information via the time over threshold technique. Prototype devices with oxygenated silicon sensor and rad-hard electronics built in the IBM 0.25μm process have been tested and maintain good resolution, efficiency and timing performances even after receiving the design radiation damage of 1015neq/cm2

  7. Front-end Intelligence for triggering and local track recognition in Gas Pixel Detectors

    CERN Document Server

    Hessey, NP; The ATLAS collaboration; van der Graaf, H; Vermeulen, J; Jansweijer, P; Romaniouk, A

    2012-01-01

    The combination of gaseous detectors with pixel readout chips gives unprecedented hit resolution (improving from O(100 um) for wire chambers to 10 um), as well as high-rate capability, low radiation length and giving in addition angular information on the local track. These devices measure individually every electron liberated by the passage of a charged particle, leading to a large quantity of data to be read out. Typically an external trigger is used to start the read-out. We are investigating the addition of local intelligence to the pixel read-out chip. A first level of processing detects the passage of a particle through the gas volume, and accurately determines the time of passage. A second level measures in an approximate but fast way the tilt-angle of the track. This can be used to trigger a third stage in which all hits associated to the track are processed locally to give a least-squares-fit to the track. The chip can then send out just the fitted track parameters instead of the individual electron ...

  8. A 10 MHz micropower CMOS front end for direct readout of pixel detectors

    International Nuclear Information System (INIS)

    Campbell, M.; Heijne, E.H.M.; Jarron, P.; Krummenacher, F.; Enz, C.C.; Declercq, M.; Vittoz, E.; Viertel, G.

    1990-01-01

    In the framework of the CERN-LAA project for detector R and D, a micropower circuit of 200 μmx200 μm with a current amplifier, a latched comparator and a digital memory element has been tested electrically and operated in connection with linear silicon detector arrays. The experimental direct-readout (DRO) chip comprises a matrix of 9x12 circuit cells and has been manufactured in a 3 μm CMOS technology. Particles and X-ray photons below 22 keV were detected, and thresholds can be set between 2000 and 20000 e - . The noise is less than 4 keV FWHM or 500 e - rms and the power dissipation per pixel element is 30 μW. The chip can be coupled to a detector matrix using bump bonding. (orig.)

  9. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  10. The ATLAS Pixel Detector

    CERN Document Server

    Huegging, Fabian

    2006-06-26

    The contruction of the ATLAS Pixel Detector which is the innermost layer of the ATLAS tracking system is prgressing well. Because the pixel detector will contribute significantly to the ATLAS track and vertex reconstruction. The detector consists of identical sensor-chip-hybrid modules, arranged in three barrels in the centre and three disks on either side for the forward region. The position of the detector near the interaction point requires excellent radiation hardness, mechanical and thermal robustness, good long-term stability for all parts, combined with a low material budget. The final detector layout, new results from production modules and the status of assembly are presented.

  11. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Hofsajer, I; Govender, M; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is the portable test-bench for the full certification of the front-end electronics of the ATLAS Tile calorimeter designed for the upgrade phase-II. It is a high throughput electronics system designed to simultaneously read-out all the samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read-out and control the front-end boards. The rest of the functionalities of the system are provided by a HV mezzanine board that to turn on the gain of the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog output of the front-end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  12. CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

    International Nuclear Information System (INIS)

    CHASE, B.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, S.; RESCIA, S.; TAKAI, H.

    1999-01-01

    The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

  13. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  14. An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  15. Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

  16. Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

    CERN Document Server

    Drake, G; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

  17. CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

    International Nuclear Information System (INIS)

    CHASE, R.L.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, V.; RESCIA, S.; TAKAI, H.; BAN, J.; PARSONS, J.; SIPPACH, W.

    2000-01-01

    The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

  18. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  19. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  20. Upgrade of ATLAS ITk Pixel Detector

    CERN Document Server

    Huegging, Fabian; The ATLAS collaboration

    2017-01-01

    The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current inner detector will be replaced with an entirely-silicon inner tracker (ITk) which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation levels are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors and low mass global and local support structures. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the ITk ATLAS Pixel detector developments as well as different layout options will be reviewed.

  1. ATLAS Pixel Detector Upgrade

    CERN Document Server

    Flick, T; The ATLAS collaboration

    2009-01-01

    The first upgrade for higher luminosity at LHC for the ATLAS pixel detector is the insertion of a forth layer, the IBL. The talk gives an overview about what the IBL is and how it will be set up, as well as to give a status of the research and develoment work.

  2. An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

  3. An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

  4. Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

    CERN Document Server

    Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

    2014-01-01

    Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

  5. JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

    CERN Document Server

    Moschovakos, Paris

    2018-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

  6. An automated meta-monitoring mobile application and front-end interface for the ATLAS computing model

    Energy Technology Data Exchange (ETDEWEB)

    Kawamura, Gen; Quadt, Arnulf [II. Physikalisches Institut, Georg-August-Universitaet Goettingen (Germany)

    2016-07-01

    Efficient administration of computing centres requires advanced tools for the monitoring and front-end interface of the infrastructure. Providing the large-scale distributed systems as a global grid infrastructure, like the Worldwide LHC Computing Grid (WLCG) and ATLAS computing, is offering many existing web pages and information sources indicating the status of the services, systems and user jobs at grid sites. A meta-monitoring mobile application which automatically collects the information could give every administrator a sophisticated and flexible interface of the infrastructure. We describe such a solution; the MadFace mobile application developed at Goettingen. It is a HappyFace compatible mobile application which has a user-friendly interface. It also becomes very feasible to automatically investigate the status and problem from different sources and provides access of the administration roles for non-experts.

  7. Prototype ATLAS IBL modules using the FE-I4A front-end readout chip

    Czech Academy of Sciences Publication Activity Database

    Albert, J.; Alex, M.; Alimonti, G.; Hejtmánek, Martin; Janoška, Zdenko; Korchak, Oleksandr; Popule, Jiří; Šícho, Petr; Sloboda, Michal; Tomášek, Michal; Vrba, Václav

    2012-01-01

    Roč. 7, NOV (2012), 1-45 ISSN 1748-0221 R&D Projects: GA MŠk LA08032 Institutional research plan: CEZ:AV0Z10100502 Keywords : ATLAS * upgrade * tracker * silicon * FE-I4 * planar sensors * test beam Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.869, year: 2011 http://arxiv.org/abs/arXiv:1209.1906

  8. Total dose effects on ATLAS-SCT front-end electronics

    CERN Document Server

    Ullán, M; Dubbs, T; Grillo, A A; Spencer, E; Seiden, A; Spieler, H; Gilchriese, M G D; Lozano, M

    2002-01-01

    Low dose rate effects (LDRE) in bipolar technologies complicate the hardness assurance testing for high energy physics applications. The damage produced in the ICs in the real experiment can be underestimated if fast irradiations are carried out, while experiments done at the real dose rate are usually unpractical due to the still high total doses involved. In this work the sensitivity to LDRE of two bipolar technologies proposed for the ATLAS-SCT experiment at CERN is evaluated, finding one of them free of those effects. (12 refs).

  9. Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

    CERN Document Server

    Cooper, B; The ATLAS collaboration

    2012-01-01

    The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC upgrade. We demonstrate that, in terms of the communication between the external processing and the tracking detector frontends, a hardware solution is possible that fits within the latency constraints of level-1.

  10. Initial Measurements on Pixel Detector Modules for the ATLAS Upgrades

    CERN Document Server

    Gallrapp, C; The ATLAS collaboration

    2011-01-01

    Delicate conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel Detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming Pixel Detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation for silicon planar and 3D pixel sensors, which give a first impression on the charge collection properties of the different sensor technologies, are presented.

  11. Calibration Analysis Software for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

    2016-01-01

    The calibration of the ATLAS Pixel detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied together to chips with different characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

  12. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  13. Evaluation of the PANDA silicon pixel front-end electronics and investigation of the anti ΛΛ final state

    Energy Technology Data Exchange (ETDEWEB)

    Esch, Simone

    2014-04-28

    high precision particle beams for several experiments. The AntiProton Annihilation at Darmstadt (PANDA) experiment is one of the large detectors at FAIR. PANDAs main physics objectives center around the properties of particles and excited particles made from quarks of the first and second quark family. It is a fixed target experiment within the High Energy Storage Ring (HESR), which delivers an intense, phase-space cooled antiproton beam in the momentum range of 1.5 to 15 GeV/c. With the high precision of the HESR, PANDA will be able to perform precise spectroscopic studies of hadronic states in the charm quark mass range. The luminosity will be up to 2.10{sup 32} cm{sup -2}s{sup -1}, thus enabling very rare processes to be studied. This high luminosity leads to a high particle flux and a high radiation environment which the sub-detectors must withstand. The most highly affected sub-detector of this high radiation environment is the Micro Vertex Detector (MVD), the innermost detector of PANDA. The main task of the MVD is the detection of the interaction points of events (vertexing). This vertex finding is crucial for the analysis of short living particles like e.g. D-mesons, particles consisting of a c-quark and a light antiquark. An essential part of the MVD detector is the readout of the semiconductor sensors. The ToPix (Torino Pixel) Application Specific Integrated Circuit (ASIC) is the front-end electronics for the MVD sensor, developed at the Istituto Nazionale di Fisica Nucleare (INFN) in Turin, Italy. It measures the spatial coordinate, the time and the deposited charge of incident charged particles. The most recent prototype of this ASIC is the ToPix 3, a version of reduced size and functionality. The Juelich Digital Readout System (JDRS) was adopted and extended to be able to readout this prototype, thus enabling specific test measurements of the prototype. In addition, the performance of PANDA for detecting long lived. particles was studied, and the

  14. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter

    CERN Document Server

    Dressnandt, N; Rescia, S; Vernon, E

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at the Large Hadron Collider upgrade (sLHC). IBM’s 8WL 130nm SiGe process was chosen for it’s radiation tolerance, low noise bipolar NPN devices, wide voltage rand and potential use in other sLHC detector subsystems. Although the requirements for the final design can not be set at this time, the prototype was designed to accommodate a 16 bit dynamic range. This was accomplished by using a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of the Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier which eases the input voltage noise requirement on the shaper. Each shaper stage is designed as a cascaded differential operational amplifier doublet with a common...

  15. LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr

    CERN Document Server

    Rescia, S; Newcomer, F M; Dressnandt, N

    2009-01-01

    We have designed and fabricated a very low noise preamplifier and shaper with a (RC)2 – CR response to replace the existing ATLAS Liquid Argon readout for use at SLHC. IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished by utilization of a single stage, low noise, wide dynamic range preamp connected to a dual range shaper. The low noise of the preamp (~.01nA / √Hz) is achieved by utilizing the process Silicon Germanium bipolar transistors. The relatively high voltage rating of the npn transistors is exploited to allow a gain of 650V/A. With this gain the equivalent input voltage noise requirement on the shaper to about 2.2nV/ √Hz. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. The shaper outputs are designed to be compatible with the 130nm CMOS ADC being develo...

  16. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Schreuder, Frans Philip; The ATLAS collaboration

    2018-01-01

    Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

  17. Initial Measurements On Pixel Detector Modules For The ATLAS Upgrades

    CERN Document Server

    Gallrapp, C; The ATLAS collaboration

    2011-01-01

    Sophisticated conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming pixel detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation, which give a first impression on the charge collection properties of the different sensor technologies are presented.

  18. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  19. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    Energy Technology Data Exchange (ETDEWEB)

    Erdinger, Florian

    2016-11-22

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  20. ATLAS Pixel Detector Operational Experience

    CERN Document Server

    Di Girolamo, B; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.9% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  1. The TDCpix readout ASIC: A 75ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    CERN Document Server

    Kluge, A; Bonacini, S; Jarron, P; Kaplon, J; Morel, M; Noy, M; Perktold, L; Poltorak, K

    2013-01-01

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak fl ow of particles crossing the detector modules reaches 1.27 MHz/mm 2 for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection ef fi ciency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45 40 square pixels of 300 300 μ m 2 and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low...

  2. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  3. Pixel electronics for the ATLAS experiment

    International Nuclear Information System (INIS)

    Fischer, P.

    2001-01-01

    The ATLAS experiment at LHC will use 3 barrel layers and 2x5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mmx60.8 mm which include an n + on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode the pin diode signal and to drive the VCSEL laser diodes of the optical links

  4. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    Science.gov (United States)

    Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

    2016-12-01

    The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  5. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  6. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    International Nuclear Information System (INIS)

    Anderson, J.; Drake, G.; Ryu, S.; Bauer, K.; Guest, D.; Borga, A.; Boterenbrood, H.; Schreuder, F.; Chen, H.; Chen, K.; Lanni, F.; Dönszelmann, M.; Francis, D.; Gorini, B.; Joos, M.; Miotto, G. Lehmann; Levinson, L.; Narevicius, J.; Roich, A.; Vazquez, W. Panduro

    2016-01-01

    The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  7. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  8. Operational Experience with the ATLAS Pixel Detector at LHC

    CERN Document Server

    Keil, M

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus crucial for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via front-end chips bump-bonded to 1744 n-on-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, detector performance and measurements of radiation damage. The detector performance is excellent: more than 95% of the pixels are operational, noise occupancy and hit efficiency exceed the des...

  9. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  10. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

  11. Digital Architecture of the New ATLAS Pixel Chip FE-I4

    CERN Document Server

    "Barbero, M; The ATLAS collaboration

    2009-01-01

    With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is 80×336 pixels wide and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire chip and the pixels organized in regions. Additional features include neighbor hit checking which allows a timewalk-less hit recording.

  12. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Djama, Fares; The ATLAS collaboration

    2017-01-01

    Run 2 of the LHC collider sets new challenges to track and vertex reconstruction because of its higher energy, pileup and luminosity. The ATLAS tracking performance relies critically on the Pixel Detector. Therefore, in view of Run 2, the ATLAS collaboration has constructed the first 4-layer pixel detector in Particle Physics by installing a new pixel layer, called Insertable B-Layer (IBL). Operational experience and performance of the 4-layer Pixel Detector during Run 2 are presented.

  13. Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

    International Nuclear Information System (INIS)

    Kureba, C O; Govender, M; Hofsajer, I; Ruan, X; Sandrock, C; Spoor, M

    2015-01-01

    The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade. (paper)

  14. The ATLAS Planar Pixel Sensor R and D project

    International Nuclear Information System (INIS)

    Beimforde, M.

    2011-01-01

    Within the R and D project on Planar Pixel Sensor Technology for the ATLAS inner detector upgrade, the use of planar pixel sensors for highest fluences as well as large area silicon detectors is investigated. The main research goals are optimizing the signal size after irradiations, reducing the inactive sensor edges, adjusting the readout electronics to the radiation induced decrease of the signal sizes, and reducing the production costs. Planar n-in-p sensors have been irradiated with neutrons and protons up to fluences of 2x10 16 n eq /cm 2 and 1x10 16 n eq /cm 2 , respectively, to study the collected charge as a function of the irradiation dose received. Furthermore comparisons of irradiated standard 300μm and thin 140μm sensors will be presented showing an increase of signal sizes after irradiation in thin sensors. Tuning studies of the present ATLAS front end electronics show possibilities to decrease the discriminator threshold of the present FE-I3 read out chips to less than 1500 electrons. In the present pixel detector upgrade scenarios a flat stave design for the innermost layers requires reduced inactive areas at the sensor edges to ensure low geometric inefficiencies. Investigations towards achieving slim edges presented here show possibilities to reduce the width of the inactive area to less than 500μm. Furthermore, a brief overview of present simulation activities within the Planar Pixel R and D project is given.

  15. Commissioning of the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Golling, Tobias

    2008-01-01

    The ATLAS pixel detector is a high precision silicon tracking device located closest to the LHC interaction point. It belongs to the first generation of its kind in a hadron collider experiment. It will provide crucial pattern recognition information and will largely determine the ability of ATLAS to precisely track particle trajectories and find secondary vertices. It was the last detector to be installed in ATLAS in June 2007, has been fully connected and tested in-situ during spring and summer 2008, and is ready for the imminent LHC turn-on. The highlights of the past and future commissioning activities of the ATLAS pixel system are presented

  16. Operational experience with the ATLAS Pixel Detector

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost element of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  17. Operational experience of the ATLAS Pixel detector

    CERN Document Server

    Hirschbuehl, D; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  18. Operational experience of the ATLAS Pixel Detector

    CERN Document Server

    Marcisovsky, M; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  19. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Rossi, Leonardo Paolo; The ATLAS collaboration

    2018-01-01

    The upgrade of the ATLAS experiment for the operation at the High Luminosity Large Hadron Collider requires a new and more performant inner tracker, the ITk. The innermost part of this tracker will be built using silicon pixel detectors. This paper describes the ITk pixel project, which, after few years of design and test e ort, is now defined in detail.

  20. Study of run time errors of the ATLAS Pixel Detector in the 2012 data taking period

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00339072

    2013-05-16

    The high resolution silicon Pixel detector is critical in event vertex reconstruction and in particle track reconstruction in the ATLAS detector. During the pixel data taking operation, some modules (Silicon Pixel sensor +Front End Chip+ Module Control Chip (MCC)) go to an auto-disable state, where the Modules don’t send the data for storage. Modules become operational again after reconfiguration. The source of the problem is not fully understood. One possible source of the problem is traced to the occurrence of single event upset (SEU) in the MCC. Such a module goes to either a Timeout or Busy state. This report is the study of different types and rates of errors occurring in the Pixel data taking operation. Also, the study includes the error rate dependency on Pixel detector geometry.

  1. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Djama, Fares; The ATLAS collaboration

    2017-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction imposed by the higher collision energy, pileup and luminosity that are being delivered. The ATLAS tracking performance relies critically on the Pixel Detector, therefore, in view of Run-2 of LHC, the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and an additional optical link per module was added to overcome in some layers the readout bandwidth limitation when LHC will exceed the nominal peak luminosity by almost a factor of 3. The key features and challenges met during the IBL project will be presented, as well as its operational experience and Pixel Detector performance in LHC.

  2. Operational Experience with the ATLAS Pixel Detector

    CERN Document Server

    Lantzsch, Kerstin; The ATLAS collaboration

    2016-01-01

    Run 2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). In addition the Pixel detector was refurbished with new service quarter panels to recover about 3% of defective modules lost during run 1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning, operation and performance of the 4-layer Pixel Detector will be presented.

  3. Prototype of the front-end circuit for the GOSSIP (Gas On Slimmed Silicon Pixel) chip in the 0.13 μm CMOS technology

    CERN Document Server

    Gromov, V; van der Graaf, H

    2007-01-01

    The new GOSSIP detector, capable to detect single electrons in gas, has certain advantages with respect silicon (pixel) detectors. It does not require a Si sensor; it has a very low detector parasitic capacitance and a zero bias current at the pixel input. These are attractive features to design a compact, low-noise and low-power integrated input circuit. A prototype of the integrated circuit has been developed in 0.13 μm CMOS technology. It includes a few channels equipped with preamplifier, discriminator and the digital circuit to study the feasibility of the TDC-perpixel concept. The design demonstrates very low input referred noise (60e- RMS) in combination with a fast peaking time (40 ns) and an analog power dissipation as low as 2 μW per channel. Switching activity on the clock bus (up to 100 MHz) in the close vicinity of the pixel input pads does not cause noticeable extra noise.

  4. Gossipo-3 A prototype of a Front-End Pixel Chip for Read-Out of Micro-Pattern Gas Detectors

    CERN Document Server

    Brezina, Christpoh; van der Graaf, Haryy; Gromov, Vladimir; Kluit, Ruud; Kruth, Andre; Zappon, Francesco

    2009-01-01

    In a joint effort of Nikhef (Amsterdam) and the University of Bonn, the Gossipo-3 integrated circuit (IC) has been developed. This circuit is a prototype of a chip dedicated for read-out of various types of position sensitive Micro-Pattern Gas detectors (MPGD). The Gossipo-3 is defined as a set of building blocks to be used in a future highly granulated (60 μm) chip. The pixel circuit can operate in two modes. In Time mode every readout pixel measures the hit arrival time and the charge deposit. For this purpose it has been equipped with a high resolution TDC (1.7 ns) covering dynamic range up to 102 μs. Charge collected by the pixel will be measured using Time-over- Threshold method in the range from 400 e- to 28000 e- with accuracy of 200 e- (standard deviation). In Counting mode every pixel operates as a 24-bit counter, counting the number of incoming hits. The circuit is also optimized to operate at low power consumption (100 mW/cm2) that is required to avoid the need for massive power transport and coo...

  5. Test su fascio di prototipi del rivelatore a pixel per l'esperimento ATLAS

    CERN Document Server

    Matera, Andrea; Andreazza, A

    2005-01-01

    Silicon pixel detectors, developed to meet LHC requirements, were tested within the ATLAS collaboration in the H8 beam at CERN. Different sensor designs were studied using various versions of front end electronics developed during the R&D process. In this thesis a detailed experimental study of the overall performance of both irradiated and unirradiated detectors is presented, with special enphasis on efficiency, charge collection and spatial resolution. For the first time their dependence on timewalk is carefully investigated. Possible solutions to avoid spatial resolution deterioration due to timewalk are presented and discussed.

  6. EXCALIBUR: a small-pixel photon counting area detector for coherent X-ray diffraction - Front-end design, fabrication and characterisation

    Science.gov (United States)

    Marchal, J.; Horswell, I.; Willis, B.; Plackett, R.; Gimenez, E. N.; Spiers, J.; Ballard, D.; Booker, P.; Thompson, J. A.; Gibbons, P.; Burge, S. R.; Nicholls, T.; Lipp, J.; Tartoni, N.

    2013-03-01

    Coherent X-ray diffraction experiments on synchrotron X-ray beamlines require detectors with high spatial resolution and large detection area. The read-out chip developed by the MEDIPIX3 collaboration offers a small pixel size of 55 microns resulting in a very high spatial resolution when coupled to a direct X-ray conversion segmented silicon sensor. MEDIPIX3 assemblies present also the advantages of hybrid pixel detectors working in single photon counting mode: noiseless imaging, large dynamic range, extremely high frame rate. The EXCALIBUR detector is under development for the X-ray Coherence and Imaging Beamline I13 of the Diamond Light Source. This new detector consists of three modules, each with 16 MEDIPIX3 chips which can be read-out at 100 frames per second in continuous mode or 1000 frames per second in burst mode. In each module, the sensor is a large single silicon die covering 2 rows of 8 individual MEDIPIX3 read-out chips and provides a continuous active detection region within a module. Each module includes 1 million solder bumps connecting the 55 microns pixels of the silicon sensor to the 55 microns pixels of the 16 MEDIPIX3 read-out chips. The detection area of the 3-module EXCALIBUR detector is 115 mm × 100 mm with a small 6.8 mm wide inactive region between modules. Each detector module is connected to 2 FPGA read-out boards via a flexi-rigid circuit to allow a fully parallel read-out of the 16 MEDIPIX3 chips. The 6 FPGA read-out boards used in the EXCALIBUR detector are interfaced to 6 computing nodes via 10Gbit/s fibre-optic links to maintain the very high frame-rate capability. The standard suite of EPICS control software is used to operate the detector and to integrate it with the Diamond Light Source beamline software environment. This article describes the design, fabrication and characterisation of the MEDIPIX3-based modules composing the EXCALIBUR detector.

  7. EXCALIBUR: a small-pixel photon counting area detector for coherent X-ray diffraction - Front-end design, fabrication and characterisation

    International Nuclear Information System (INIS)

    Marchal, J; Horswell, I; Willis, B; Plackett, R; Gimenez, E N; Spiers, J; Thompson, J A; Gibbons, P; Tartoni, N; Ballard, D; Booker, P; Burge, S R; Nicholls, T; Lipp, J

    2013-01-01

    Coherent X-ray diffraction experiments on synchrotron X-ray beamlines require detectors with high spatial resolution and large detection area. The read-out chip developed by the MEDIPIX3 collaboration offers a small pixel size of 55 microns resulting in a very high spatial resolution when coupled to a direct X-ray conversion segmented silicon sensor. MEDIPIX3 assemblies present also the advantages of hybrid pixel detectors working in single photon counting mode: noiseless imaging, large dynamic range, extremely high frame rate. The EXCALIBUR detector is under development for the X-ray Coherence and Imaging Beamline I13 of the Diamond Light Source. This new detector consists of three modules, each with 16 MEDIPIX3 chips which can be read-out at 100 frames per second in continuous mode or 1000 frames per second in burst mode. In each module, the sensor is a large single silicon die covering 2 rows of 8 individual MEDIPIX3 read-out chips and provides a continuous active detection region within a module. Each module includes 1 million solder bumps connecting the 55 microns pixels of the silicon sensor to the 55 microns pixels of the 16 MEDIPIX3 read-out chips. The detection area of the 3-module EXCALIBUR detector is 115 mm × 100 mm with a small 6.8 mm wide inactive region between modules. Each detector module is connected to 2 FPGA read-out boards via a flexi-rigid circuit to allow a fully parallel read-out of the 16 MEDIPIX3 chips. The 6 FPGA read-out boards used in the EXCALIBUR detector are interfaced to 6 computing nodes via 10Gbit/s fibre-optic links to maintain the very high frame-rate capability. The standard suite of EPICS control software is used to operate the detector and to integrate it with the Diamond Light Source beamline software environment. This article describes the design, fabrication and characterisation of the MEDIPIX3-based modules composing the EXCALIBUR detector.

  8. ATLAS ITk and new pixel sensors technologies

    CERN Document Server

    Gaudiello, A

    2016-01-01

    During the 2023–2024 shutdown, the Large Hadron Collider (LHC) will be upgraded to reach an instantaneous luminosity up to 7×10$^{34}$ cm$^{−2}$s$^{−1}$. This upgrade of the accelerator is called High-Luminosity LHC (HL-LHC). The ATLAS detector will be changed to meet the challenges of HL-LHC: an average of 200 pile-up events in every bunch crossing, and an integrated luminosity of 3000 fb $^{−1}$ over ten years. The HL-LHC luminosity conditions are too extreme for the current silicon (pixel and strip) detectors and straw tube transition radiation tracker (TRT) of the current ATLAS tracking system. Therefore the ATLAS inner tracker is being completely rebuilt for data-taking and the new system is called Inner Tracker (ITk). During this upgrade the TRT will be removed in favor of an all-new all-silicon tracker composed only by strip and pixel detectors. An overview of new layouts in study will be reported and the new pixel sensor technologies in development will be explained.

  9. Monolithic pixel development in TowerJazz 180 nm CMOS for the outer pixel layers in the ATLAS experiment

    Science.gov (United States)

    Berdalovic, I.; Bates, R.; Buttar, C.; Cardella, R.; Egidos Plaja, N.; Hemperek, T.; Hiti, B.; van Hoorne, J. W.; Kugathasan, T.; Mandic, I.; Maneuski, D.; Marin Tobon, C. A.; Moustakas, K.; Musa, L.; Pernegger, H.; Riedler, P.; Riegel, C.; Schaefer, D.; Schioppa, E. J.; Sharma, A.; Snoeys, W.; Solans Sanchez, C.; Wang, T.; Wermes, N.

    2018-01-01

    The upgrade of the ATLAS tracking detector (ITk) for the High-Luminosity Large Hadron Collider at CERN requires the development of novel radiation hard silicon sensor technologies. Latest developments in CMOS sensor processing offer the possibility of combining high-resistivity substrates with on-chip high-voltage biasing to achieve a large depleted active sensor volume. We have characterised depleted monolithic active pixel sensors (DMAPS), which were produced in a novel modified imaging process implemented in the TowerJazz 180 nm CMOS process in the framework of the monolithic sensor development for the ALICE experiment. Sensors fabricated in this modified process feature full depletion of the sensitive layer, a sensor capacitance of only a few fF and radiation tolerance up to 1015 neq/cm2. This paper summarises the measurements of charge collection properties in beam tests and in the laboratory using radioactive sources and edge TCT. The results of these measurements show significantly improved radiation hardness obtained for sensors manufactured using the modified process. This has opened the way to the design of two large scale demonstrators for the ATLAS ITk. To achieve a design compatible with the requirements of the outer pixel layers of the tracker, a charge sensitive front-end taking 500 nA from a 1.8 V supply is combined with a fast digital readout architecture. The low-power front-end with a 25 ns time resolution exploits the low sensor capacitance to reduce noise and analogue power, while the implemented readout architectures minimise power by reducing the digital activity.

  10. ATLAS rewards two pixel detector suppliers

    CERN Multimedia

    2007-01-01

    Peter Jenni, ATLAS spokesperson, presented the ATLAS supplier award to Herbert Reichl, IZM director, and to Simonetta Di Gioia, from the SELEX company.Two of ATLAS’ suppliers were awarded prizes at a ceremony on Wednesday 13 June attended by representatives of the experiment’s management and of CERN. The prizes went to the Fraunhofer Institut für Zuverlässigkeit und Mikrointegration (IZM) in Berlin and the company SELEX Sistemi Integrati in Rome for the manufacture of modules for the ATLAS pixel detector. SELEX supplied 1500 of the modules for the tracker, while IZM produced a further 1300. The modules, each made up of 46080 channels, form the active part of the ATLAS pixel detector. IZM and SELEX received the awards for the excellent quality of their work: the average number of faulty channels per module was less than 2.10-3. They also stayed within budget and on schedule. The difficulty they faced was designing modules based on electronic components and sensor...

  11. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Macchiolo, Anna; The ATLAS collaboration

    2018-01-01

    The new ATLAS ITk pixel system will be installed during the LHC Phase-II shutdown, to better take advantage of the increased luminosity of the HL-LHC. The detector will consist of 5 layers of stave-like support structures in the most central region and ring-shaped supports in the endcap regions, covering up to |η| < 4. While the outer 3 layers of the Pixel Detector are designed to operate for the full HL-LHC data taking period, the innermost 2 layers of the detector will be replaced around half of the lifetime. The ITk pixel detector will be instrumented with new sensors and readout electronics to provide improved tracking performance and radiation hardness compared to the current detector. Sensors will be read out by new ASICs based on the chip developed by the RD53 Collaboration. The pixel off-detector readout electronics will be implemented in the framework of the general ATLAS trigger and DAQ system with a readout speed of up to 5 Gb/s per data link for the innermost layers. Results of extensive tests...

  12. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  13. The ATLAS Pixel Detector operation and performance

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately $80 imes 10^6$~electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region. The complete Pixel Detector has been taking part in cosmic-ray data-taking since 2008. Since November 2009 it has been operated with LHC colliding beams at $sqrt{s}=900$~GeV, 2.36~TeV and 7 TeV. The detector operated with an active fraction of 97.2% at a threshold of 3500~$e$, showing a noise occupancy rate better than $10^{-9}$~hit/pixel/BC and a track association efficiency of 99%. The Lorentz angle for electrons in silicon is measured to be $ heta_mathrm{L}=12.11^circ pm 0.09^circ$ and its temperature dependence has been verified. The pulse height information from the time-over-threshold technique allows to improve the point resolution using charge sharing and to perform parti...

  14. Align the Front End First.

    Science.gov (United States)

    Perry, Jim

    1995-01-01

    Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

  15. ATLAS Pixel IBL: Stave Quality Assurance

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    For Run 2 of the LHC a fourth innermost Pixel Detector layer on a smaller radius beam pipe has been installed in the ATLAS Detector to add redundancy against radiation damage of the current Pixel Detector and to ensure a high quality tracking and b-tagging performance of the Inner Detector over the coming years until the High Luminosity Upgrade. State of the art components have been produced and assembled onto support structures known as staves over the last two years. In total, 20 staves have been built and qualified in a designated Quality Assurance setup at CERN of which 14 have been integrated onto the beam pipe. Results from the testing are presented.

  16. Survey of the ATLAS Pixel Detector Components

    International Nuclear Information System (INIS)

    Andreazza, A.; Kostyukhim, V.; Madaras, R.

    2008-01-01

    This document provides a description of the survey performed on different components of the ATLAS Pixel Detector at different stages of its assembly. During the production of the ATLAS pixel detector great care was put in the geometrical survey of the location of the sensitive area of modules. This had a double purpose: (1) to provide a check of the quality of the assembly procedure and assure tolerances in the geometrical assembly were met; and (2) to provide an initial point for the alignment (the so called 'as-built detector'), better than the ideal geometry. Since direct access to the sensitive area becomes more and more difficult with the progress of the assembly, the survey needed to be performed at different stages: after module loading on the local supports (sectors and staves) and after assembly of the local supports in disks or halfshells. Different techniques were used, including both optical 2D and 3D surveys and mechanical survey. This document summarizes the survey procedures, the analysis done on the collected data and how survey data are stored in case they will need to be accessed in the future

  17. 3D silicon sensors: Design, large area production and quality assurance for the ATLAS IBL pixel detector upgrade

    Science.gov (United States)

    Da Via, Cinzia; Boscardin, Maurizio; Dalla Betta, Gian-Franco; Darbo, Giovanni; Fleta, Celeste; Gemme, Claudia; Grenier, Philippe; Grinstein, Sebastian; Hansen, Thor-Erik; Hasi, Jasmine; Kenney, Chris; Kok, Angela; Parker, Sherwood; Pellegrini, Giulio; Vianello, Elisa; Zorzi, Nicola

    2012-12-01

    3D silicon sensors, where electrodes penetrate the silicon substrate fully or partially, have successfully been fabricated in different processing facilities in Europe and USA. The key to 3D fabrication is the use of plasma micro-machining to etch narrow deep vertical openings allowing dopants to be diffused in and form electrodes of pin junctions. Similar openings can be used at the sensor's edge to reduce the perimeter's dead volume to as low as ˜4 μm. Since 2009 four industrial partners of the 3D ATLAS R&D Collaboration started a joint effort aimed at one common design and compatible processing strategy for the production of 3D sensors for the LHC Upgrade and in particular for the ATLAS pixel Insertable B-Layer (IBL). In this project, aimed for installation in 2013, a new layer will be inserted as close as 3.4 cm from the proton beams inside the existing pixel layers of the ATLAS experiment. The detector proximity to the interaction point will therefore require new radiation hard technologies for both sensors and front end electronics. The latter, called FE-I4, is processed at IBM and is the biggest front end of this kind ever designed with a surface of ˜4 cm2. The performance of 3D devices from several wafers was evaluated before and after bump-bonding. Key design aspects, device fabrication plans and quality assurance tests during the 3D sensors prototyping phase are discussed in this paper.

  18. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Directory of Open Access Journals (Sweden)

    Senkin Sergey

    2018-01-01

    Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  19. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Science.gov (United States)

    Senkin, Sergey

    2018-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  20. The Phase II ATLAS ITk Pixel Upgrade

    CERN Document Server

    Terzo, Stefano; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the "ITk" (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and and ring-shaped supports in the endcap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m$^2$ , depending on the final layout choice, which is expected to take place in early 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel-endcap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as $|\\eta| < 4$. Supporting structures will be ...

  1. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to |eta| < 3.2 and two to |eta| < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions...

  2. Construction and Tests of Modules for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2068490

    2003-01-01

    The ATLAS Pixel Detector is the innermost layer of the ATLAS tracking system and will contribute significantly to the ATLAS track and vertex reconstruction. The detector consists of identical sensor-chip-hybrid modules, arranged in three barrels in the centre and three disks on either side for the forward region. The position of the pixel detector near the interaction point requires excellent radiation hardness, mechanical and thermal robustness, good long-term stability, all combined with a low material budget. The pre-production phase of such pixel modules has nearly finished, yielding fully functional modules. Results are presented of tests with these modules.

  3. ATLAS SemiConductor Tracker and Pixel Detector: Status and Performance

    CERN Document Server

    Reeves, K; The ATLAS collaboration

    2012-01-01

    The Semi-Conductor Tracker (SCT) and the Pixel Detector are the key precision tracking devices in the Inner Detector of the ATLAS experiment at CERN LHC. The SCT is a silicon strip detector and is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. The Pixel Detector consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In the talk the current status of the SCT and Pixel Detector will be reviewed. We will report on the operation of the detectors including an overview of the issues we encountered and the observation of significant increases in leakage currents (as expected) from bulk ...

  4. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    International Nuclear Information System (INIS)

    Gabrielli, A.; Balbi, G.; Falchieri, D.; Lama, L.; Travaglini, R.; Backhaus, M.; Bindi, M.; Chen, S.P.; Hauck, S.; Hsu, S.C.; Flick, T.; Wensing, M.; Kretz, M.; Kugel, A.

    2015-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called the Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL's off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware, and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ test bench using a realistic front-end chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data path implementation, test on the test bench and ROD prototypes, will be reported. Recent Pixel collaboration efforts focus on finalizing hardware and firmware tests for the IBL. The plan is to approach a complete IBL DAQ hardware-software installation by the end of 2014

  5. The upgraded Tevatron front end

    International Nuclear Information System (INIS)

    Glass, M.; Zagel, J.; Smith, P.; Marsh, W.; Smolucha, J.

    1990-01-01

    We are replacing the computers which support the CAMAC crates in the Fermilab accelerator control system. We want a significant performance increase, but we still want to be able to service scores of different varieties of CAMAC cards in a manner essentially transparent to console applications software. Our new architecture is based on symmetric multiprocessing. Several processors on the same bus, each running identical software, work simultaneously at satisfying different pieces of a console's request for data. We dynamically adjust the load between the processors. We can obtain more processing power by simply plugging in more processor cards and rebooting. We describe in this paper what we believe to be the interesting architectural features of the new front-end computers. We also note how we use some of the advanced features of the Multibus TM II bus and the Intel 80386 processor design to achieve reliability and expandability of both hardware and software. (orig.)

  6. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  7. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Hirschbuehl, D; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.7% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  8. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lapoire, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  9. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lapoire, C; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as B-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures and detector performance. The detector performance is excellent: 96.2% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification.

  10. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Keil, M

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, timing optimization and detector performance. The detector performance is excellent: approximately 97% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  11. Operational experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Ince, T; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 96.8% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  12. Operational experience with the ATLAS Pixel detector at the LHC

    CERN Document Server

    Deluca, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this paper, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5\\% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, ...

  13. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Lange, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump- bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, a...

  14. Operational experience with the ATLAS Pixel detector at the LHC

    CERN Document Server

    Deluca, C; The ATLAS collaboration

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: 97,5% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, an...

  15. Operational Experience with the ATLAS Pixel Detector at the LHC

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including calibration procedures, timing optimization and detector performance. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit efficiency e...

  16. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Rossi, Leonardo Paolo; The ATLAS collaboration

    2018-01-01

    The entire tracking system of the ATLAS experiment will be replaced in 2025 during the LHC Phase-II shutdown by an all-silicon detector called the “ITk” (Inner Tracker). The innermost part of ITk will be a pixel detector containing about 12.5m2 of sensitive silicon. The silicon modules are arranged on 5 layers of stave-like support structures in the most central region and ring-shaped supports in the endcap regions covering out to |η| < 4; a mid-eta region (~1 < |η| < ~2) will be occupied by novel inclined support structures which keep the angle of incidence of high-momentum tracks more closely normal to the sensitive silicon. All supports will be based on low mass, highly stable and highly thermally-conductive carbon-based materials cooled by evaporative carbon dioxide flowing in thin-walled titanium pipes. An extensive prototyping programme, including thermal, mechanical and electrical studies, is being carried out on all the types of support structures. The HL-LHC is expected to deliver up t...

  17. The Phase-2 ATLAS ITk Pixel Upgrade

    CERN Document Server

    Benoit, Mathieu; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the “ITk” (Inner Tracker). The innermost portion of the ITk will consist of a pixel detector with stave-like support structures in the most central region and ring-shaped supports in the endcap regions; there may also be novel inclined support structures in the barrel-endcap overlap regions. The new detector could have as much as 14 m2 of sensitive silicon. Support structures will be based on low mass, highly stable and highly thermally conductive carbon-based materials cooled by evaporative carbon dioxide. The ITk will be instrumented with new sensors and readout electronics to provide improved tracking performance compared to the current detector. All the module components must be performant enough and robust enough to cope with the expected high particle multiplicity and severe radiation background of the High-Luminosity LHC. Readout...

  18. SLHC upgrade plans for the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Sicho, Petr

    2009-01-01

    The ATLAS pixel detector is an 80 million channels silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. An upgrade of the ATLAS pixel detector is presently being considered, enabling to cope with higher luminosity at Super Large Hadron Collider (SLHC). The increased luminosity leads to extremely high radiation doses in the innermost region of the ATLAS tracker. Options considered for a new detector are discussed, as well as some important R and D activities, such as investigations towards novel detector geometries and novel processes.

  19. Radiation damage monitoring in the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Seidel, Sally

    2013-01-01

    We describe the implementation of radiation damage monitoring using measurement of leakage current in the ATLAS silicon pixel sensors. The dependence of the leakage current upon the integrated luminosity is presented. The measurement of the radiation damage corresponding to an integrated luminosity 5.6 fb −1 is presented along with a comparison to a model. -- Highlights: ► Radiation damage monitoring via silicon leakage current is implemented in the ATLAS (LHC) pixel detector. ► Leakage currents measured are consistent with the Hamburg/Dortmund model. ► This information can be used to validate the ATLAS simulation model.

  20. Dynamic Efficiency Measurements for Irradiated ATLAS Pixel Single Chip Modules

    CERN Document Server

    Pfaff, Mike; Grosse-Knetter, Jorn

    2011-01-01

    The ATLAS pixel detector is the innermost subdetector of the ATLAS experiment. Due to this, the pixel detector has to be particularly radiation hard. In this diploma thesis effects on the sensor and the electronics which are caused by irradiation are examined. It is shown how the behaviour changes between an unirradiated sample and a irradiated sample, which was treated with the same radiation dose that is expected at the end of the lifetime of ATLAS. For this study a laser system, which is used for dynamic efficiency measurements was constructed. Furthermore, the behaviour of the noise during the detection of a particle was evaluated studied.

  1. Development of the ATLAS FE-I4 pixel readout IC for b-layer Upgrade and Super-LHC

    CERN Document Server

    Karagounis, M

    2008-01-01

    Motivated by the upcoming upgrade of the ATLAS hybrid pixel detector, a new Front-End (FE) IC is being developed in a 130nm technology to face the tightened requirements of the upgraded pixel system. The main design goals are the reduction of material and a decrease in power consumption combined with the capability to handle the higher hit rates that will result from the upgraded machine. New technology features like the higher integration density for digital circuits, better radiation tolerance and Triple-Well transistors are used for optimization and the implementation of new concepts. A description of the ongoing design work is given, focusing more on the analog part and peripheral design blocks.

  2. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  3. Muon front end for the neutrino factory

    CERN Document Server

    Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

    2013-01-01

    In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  4. SPD very front end electronics

    International Nuclear Information System (INIS)

    Luengo, S.; Gascon, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasis, X.

    2006-01-01

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  5. RPC performance vs. front-end electronics

    International Nuclear Information System (INIS)

    Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

    2012-01-01

    Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

  6. End-Users, Front Ends and Librarians.

    Science.gov (United States)

    Bourne, Donna E.

    1989-01-01

    The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

  7. Vertex measurement at a hadron collider. The ATLAS pixel detector

    International Nuclear Information System (INIS)

    Grosse-Knetter, J.

    2008-03-01

    The ATLAS Pixel Detector is the innermost layer of the ATLAS tracking system and will contribute significantly to the ATLAS track and vertex reconstruction. The detector consists of identical sensor-chip-hybrid modules, arranged in three barrels in the centre and three disks on either side for the forward region. The position of the Pixel Detector near the interaction point requires excellent radiation hardness, fast read-out, mechanical and thermal robustness, good long-term stability, all combined with a low material budget. The new design concepts used to meet the challenging requirements are discussed with their realisation in the Pixel Detector, followed by a description of a refined and extensive set of measurements to assess the detector performance during and after its construction. (orig.)

  8. Studio di Rivelatori a Pixel di nuova generazione per il Sistema di Tracciamento di ATLAS.

    CERN Document Server

    Gaudiello, Andrea; Schiavi, Carlo

    In 2013 the LHC will undergo a long shutdown (Phase 0) in preparation for a an energy and luminosity upgrade. During this period the ATLAS Pixel Detector (that is the tracking detector closest to the beamline) will be upgraded. The new detector, called Insertable B-Layer (IBL), will be installed between the existing pixel detector and a new beam-pipe of smaller radius in order to ensure and maintain excellent performance of tracking, vertexing and jet flavor tagging. To satisfy the new requirements a new electronic front- end (FE-I4) and 2 sensor technologies have been developed: Planar and 3D. Genova is one of two sites dedicated to the assembly of the modules of IBL. The work is then carried out in two parallel directions: on one hand the production and its optimization; on the other the comparison and testing of these new technologies. Chapter 1 gives an overview of the theoretical framework needed to understand the importance and the goals of the experiments operating at the Large Hadron Collider (LHC), w...

  9. Optical data links for the ATLAS SCT and Pixel Detector

    International Nuclear Information System (INIS)

    Gregor, I.M.; Weidberg, A.R.; Lee, S.C.; Chu, M.L.; Teng, P.K.

    2001-01-01

    ATLAS (The ATLAS Technical Proposal, CERN/LHCC 94-33) is one of the large electronic particle detectors at LHC (The LHC Conceptual Design, Report- The Yellow Book, CERN/AC/95-05(LHC)) which will become operational in 2005. It is planned to use radiation tolerant optical links for the data transfer from the SemiConductor Tracker (SCT) (ATLAS Inner Detector Technical Proposal, CERN/LHCC 97-16 and CERN/LHCC 97-17). and Pixel Detector (ATLAS Pixel Detector Technical Proposal, CERN/LHCC 98-13) systems to the acquisition electronics over a distance up to 140m. The overall architecture and the performance of these optical data links are described. One of the three candidate designs for an on-detector Opto-Package is presented

  10. 3D silicon sensors: Design, large area production and quality assurance for the ATLAS IBL pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Da Via, Cinzia [School of Physics and Astronomy, University of Manchester, Oxford Road, Manchester, M13 9PL (United Kingdom); Boscardin, Maurizio [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy); Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [DISI, Universita degli Studi di Trento and INFN, Via Sommarive 14, I-38123 Trento (Italy); Darbo, Giovanni [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Fleta, Celeste [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Gemme, Claudia [INFN Sezione di Genova, Via Dodecaneso 33, I-14146 Genova (Italy); Grenier, Philippe [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Grinstein, Sebastian [Institut de Fisica d' Altes Energies (IFAE) and ICREA, Universitat Autonoma de Barcelona (UAB), E-08193 Bellaterra, Barcelona (Spain); Hansen, Thor-Erik [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Hasi, Jasmine; Kenney, Chris [SLAC National Accelerator Laboratory, 2575 Sand Hill Road, Menlo Park, CA 94025 (United States); Kok, Angela [SINTEF MiNaLab, Blindern, N-0314 Oslo (Norway); Parker, Sherwood [University of Hawaii, c/o Lawrence Berkeley Laboratory, Berkeley, CA 94720 (United States); Pellegrini, Giulio [Centro Nacional de Microelectronica, CNM-IMB (CSIC), Barcelona E-08193 (Spain); Vianello, Elisa; Zorzi, Nicola [Fondazione Bruno Kessler, FBK-CMM, Via Sommarive 18, I-38123 Trento (Italy)

    2012-12-01

    3D silicon sensors, where electrodes penetrate the silicon substrate fully or partially, have successfully been fabricated in different processing facilities in Europe and USA. The key to 3D fabrication is the use of plasma micro-machining to etch narrow deep vertical openings allowing dopants to be diffused in and form electrodes of pin junctions. Similar openings can be used at the sensor's edge to reduce the perimeter's dead volume to as low as {approx}4 {mu}m. Since 2009 four industrial partners of the 3D ATLAS R and D Collaboration started a joint effort aimed at one common design and compatible processing strategy for the production of 3D sensors for the LHC Upgrade and in particular for the ATLAS pixel Insertable B-Layer (IBL). In this project, aimed for installation in 2013, a new layer will be inserted as close as 3.4 cm from the proton beams inside the existing pixel layers of the ATLAS experiment. The detector proximity to the interaction point will therefore require new radiation hard technologies for both sensors and front end electronics. The latter, called FE-I4, is processed at IBM and is the biggest front end of this kind ever designed with a surface of {approx}4 cm{sup 2}. The performance of 3D devices from several wafers was evaluated before and after bump-bonding. Key design aspects, device fabrication plans and quality assurance tests during the 3D sensors prototyping phase are discussed in this paper.

  11. MCC: the Module Controller Chip for the ATLAS Pixel Detector

    International Nuclear Information System (INIS)

    Beccherle, R.; Darbo, G.; Gagliardi, G.; Gemme, C.; Morettini, P.; Musico, P.; Osculati, B.; Oppizzi, P.; Pratolongo, F.; Ruscino, E.; Schiavi, C.; Vernocchi, F.; Blanquart, L.; Einsweiler, K.; Meddeler, G.; Richardson, J.; Comes, G.; Fischer, P.; Calvet, D.; Boyd, R.; Sicho, P.

    2002-01-01

    In this article we describe the architecture of the Module Controller Chip for the ATLAS Pixel Detector. The project started in 1997 with the definition of the system specifications. A first fully-working rad-soft prototype was designed in 1998, while a radiation hard version was submitted in 2000. The 1998 version was used to build pixel detector modules. Results from those modules and from the simulated performance in ATLAS are reported. In the article we also describe the hardware/software tools developed to test the MCC performance at the LHC event rate

  12. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Martin, Christopher Blake; The ATLAS collaboration

    2018-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of $1.3\\times10^{34}\\text{cm}^{{-2}}\\text{s}^{{-1}}$ recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarized, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  13. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Martin, Christopher Blake; The ATLAS collaboration

    2018-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 1.3 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described, with special emphasis to radiation damage experience.

  14. New results on diamond pixel sensors using ATLAS frontend electronics

    International Nuclear Information System (INIS)

    Keil, M.; Adam, W.; Berdermann, E.; Bergonzo, P.; Boer, W. de; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D'Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; Eijk, B. van; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K.K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knoepfle, K.T.; Koeth, T.; Krammer, M.; Logiudice, A.; Mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L.S.; Pernicka, M.; Perera, L.; Riester, J.L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M.

    2003-01-01

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented

  15. New results on diamond pixel sensors using ATLAS frontend electronics

    CERN Document Server

    Keil, Markus; Berdermann, E; Bergonzo, P; de Boer, Wim; Bogani, F; Borchi, E; Brambilla, A; Bruzzi, Mara; Colledani, C; Conway, J; D'Angelo, P; Dabrowski, W; Delpierre, P A; Dulinski, W

    2003-01-01

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

  16. New results on diamond pixel sensors using ATLAS frontend electronics

    Energy Technology Data Exchange (ETDEWEB)

    Keil, M. E-mail: markus.keil@cern.ch; Adam, W.; Berdermann, E.; Bergonzo, P.; Boer, W. de; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D' Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; Eijk, B. van; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K.K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knoepfle, K.T.; Koeth, T.; Krammer, M.; Logiudice, A.; Mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L.S.; Pernicka, M.; Perera, L.; Riester, J.L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M

    2003-03-21

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

  17. New results on diamond pixel sensors using ATLAS frontend electronics

    Science.gov (United States)

    Keil, M.; Adam, W.; Berdermann, E.; Bergonzo, P.; de Boer, W.; Bogani, F.; Borchi, E.; Brambilla, A.; Bruzzi, M.; Colledani, C.; Conway, J.; D'Angelo, P.; Dabrowski, W.; Delpierre, P.; Dulinski, W.; Doroshenko, J.; Doucet, M.; van Eijk, B.; Fallou, A.; Fischer, P.; Fizzotti, F.; Kania, D.; Gan, K. K.; Grigoriev, E.; Hallewell, G.; Han, S.; Hartjes, F.; Hrubec, J.; Husson, D.; Kagan, H.; Kaplon, J.; Kass, R.; Knöpfle, K. T.; Koeth, T.; Krammer, M.; Logiudice, A.; mac Lynne, L.; Manfredotti, C.; Meier, D.; Menichelli, D.; Meuser, S.; Mishina, M.; Moroni, L.; Noomen, J.; Oh, A.; Pan, L. S.; Pernicka, M.; Perera, L.; Riester, J. L.; Roe, S.; Rudge, A.; Russ, J.; Sala, S.; Sampietro, M.; Schnetzer, S.; Sciortino, S.; Stelzer, H.; Stone, R.; Suter, B.; Trischuk, W.; Tromson, D.; Vittone, E.; Weilhammer, P.; Wermes, N.; Wetstein, M.; Zeuner, W.; Zoeller, M.

    2003-03-01

    Diamond is a promising sensor material for future collider experiments due to its radiation hardness. Diamond pixel sensors have been bump bonded to an ATLAS pixel readout chip using PbSn solder bumps. Single chip devices have been characterised by lab measurements and in a high-energy pion beam at CERN. Results on charge collection, spatial resolution, efficiency and the charge carrier lifetime are presented.

  18. Results from the Commissioning of the ATLAS Pixel Detector

    CERN Document Server

    Ibragimov, I

    2008-01-01

    The ATLAS pixel detector is the innermost tracking detector of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. It has a total active area of 1.7 m2 of silicon read out by approximately 80 million electronic channels, which will detect particle tracks and decay vertices with a very high precision. After more than 10 years of development and construction it is the first time ever the whole detector has been operated together. The paper will illustrate the detector performance and give first results from the combined ATLAS cosmics runs.

  19. Irradiation and beam tests qualification for ATLAS IBL Pixel Modules

    International Nuclear Information System (INIS)

    Rubinskiy, Igor

    2013-01-01

    The upgrade for the ATLAS detector will have different steps towards HL-LHC. The first upgrade for the Pixel Detector will consist in the construction of a new pixel layer which will be installed during the first shutdown of the LHC machine (foreseen for 2013–2014). The new detector, called Insertable B-Layer (IBL), will be inserted between the existing Pixel Detector and a new (smaller radius) beam-pipe at a radius of 33 mm. The IBL will require the development of several new technologies to cope with the increase in the radiation damage and the pixel occupancy and also to improve the physics performance, which will be achieved by reduction of the pixel size and of the material budget. Two different promising silicon sensor technologies (Planar n-in-n and 3D) are currently under investigation for the Pixel Detector. An overview of the sensor technologies' qualification with particular emphasis on irradiation and beam tests is presented. -- Highlights: ► The ATLAS inner tracker will be extended with a so called Insertable B-Layer (IBL). ► The IBL modules are required to withstand irradiation up to 5×10 15 n eq /cm 2 . ► Two types of silicon pixel detector technologies (Planar and 3D) were tested in beam. ► The irradiated sensor efficiency exceeds 97% both with and without magnetic field. ► The leakage current, power dissipation, module active area ratio requirements are met.

  20. Radiation Damage Monitoring in the ATLAS Pixel Detector

    CERN Document Server

    Seidel, S

    2013-01-01

    We describe the implementation of radiation damage monitoring using measurement of leakage current in the ATLAS silicon pixel sensors. The dependence of the leakage current upon the integrated luminosity is presented. The measurement of the radiation damage corresponding to integrated luminosity 5.6 fb$^{-1}$ is presented along with a comparison to the theoretical model.

  1. Operational Experience and Performance with the ATLAS Pixel detector

    CERN Document Server

    Yang, Hongtao; The ATLAS collaboration

    2018-01-01

    In this presentation, I will discuss the operation of ATLAS Pixel Detector during Run 2 proton-proton data-taking at √s=13 TeV in 2017. The topics to be covered include 1) the bandwidth issue and how it is mitigated through readout upgrade and threshold adjustment; 2) the auto-corrective actions; 3) monitoring of radiation effects.

  2. Fabrication of ATLAS pixel detector prototypes at IRST

    International Nuclear Information System (INIS)

    Boscardin, M.; Betta, G.-F. Dalla; Gregori, P.; Zen, M.; Zorzi, N.

    2001-01-01

    We report on the development of a fabrication technology for n-on-n silicon pixel detectors oriented to the ATLAS experiment at LHC. The main processing issues and some selected results from the electrical characterization of detector prototypes and related test structures are presented and discussed

  3. Results from the commissioning of the ATLAS Pixel Detector

    CERN Document Server

    Masetti, L

    2008-01-01

    The Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It is an 80 million channel silicon tracking system designed to detect charged tracks and secondary vertices with very high precision. After connection of cooling and services and verification of their operation, the ATLAS Pixel Detector is now in the final stage of its commissioning phase. Calibration of optical connections, verification of the analog performance and special DAQ runs for noise studies have been performed and the first tracks in combined operation with the other subdetectors of the ATLAS Inner Detector were observed. The results from calibration tests on the whole detector and from cosmic muon data are presented.

  4. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is preparing for an extensive modification of its detectors in the course of the planned HL-LHC accelerator upgrade around 2025. The ATLAS upgrade includes the replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will be a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice, which is expected to take place in 2017. In this paper an overview of the ongoing R\\&D activities on modules and electronics for the ATLAS ITk is given including the main developments and achievements in silicon planar and 3D sensor technologies, readout and power challenges.

  5. Results from the Commissioning of the ATLAS Pixel Detector

    CERN Document Server

    Strandberg, S

    2009-01-01

    The ATLAS pixel detector is a high resolution, silicon based, tracking detector with its innermost layer located only 5 cm away from the ATLAS interaction point. It is designed to provide good hit resolution and low noise, both important qualities for pattern recognition and for finding secondary vertices originating from decays of long-lived particles. The pixel detector has 80 million readout channels and is built up of three barrel layers and six disks, three on each side of the barrel. The detector was installed in the center of ATLAS in June 2007 and is currently being calibrated and commissioned. Details from the installation, commissioning and calibration are presented together with the current status.

  6. Online calibrations and performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M; The ATLAS collaboration

    2010-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 M electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. The talk will give an overview of the calibration and performance of both the detector and its optical readout. The most basic parameter to be tuned and calibrated for the detector electronics is the readout threshold of the individual pixel channels. These need to be carefully tuned to optimise position resolution a...

  7. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Nachman, Benjamin Philip; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of $10^{15}$ 1 MeV $n_\\mathrm{eq}/\\mathrm{cm}^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This talk presents a digitization model that includes radiation damage effects to the ATLAS Pixel sensors for the first time. After a thorough description of the setup, predictions for basic Pixel cluster properties are presented alongside first validation studies with Run 2 collision data.

  8. ATLAS Pixel Group - Photo Gallery from Irradiation

    CERN Multimedia

    2001-01-01

    Photos 1,2,3,4,5,6,7 - Photos taken before irradiation of Pixel Test Analog Chip and Pmbars (April 2000) Photos 8,9,10,11 - Irradiation of VDC chips (May 2000) Photos 12, 13 - Irradiation of Passive Components (June 2000) Photos 14,15, 16 - Irradiation of Marebo Chip (November 1999)

  9. High-voltage pixel sensors for ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Perić, I., E-mail: ivan.peric@ziti.uni-heidelberg.de [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Kreidl, C.; Fischer, P. [Heidelberg University, Institute of Computer Engineering, Mannheim (Germany); Bompard, F.; Breugnon, P.; Clemens, J.-C.; Fougeron, D.; Liu, J.; Pangaud, P.; Rozanov, A.; Barbero, M. [CPPM, Marseille (France); Feigl, S.; Capeans, M.; Ferrere, D.; Pernegger, H.; Ristic, B. [CERN, Geneve (Switzerland); Muenstermann, D.; Gonzalez Sevilla, S.; La Rosa, A.; Miucci, A. [University of Geneve (Switzerland); and others

    2014-11-21

    The high-voltage (HV-) CMOS pixel sensors offer several good properties: a fast charge collection by drift, the possibility to implement relatively complex CMOS in-pixel electronics and the compatibility with commercial processes. The sensor element is a deep n-well diode in a p-type substrate. The n-well contains CMOS pixel electronics. The main charge collection mechanism is drift in a shallow, high field region, which leads to a fast charge collection and a high radiation tolerance. We are currently evaluating the use of the high-voltage detectors implemented in 180 nm HV-CMOS technology for the high-luminosity ATLAS upgrade. Our approach is replacing the existing pixel and strip sensors with the CMOS sensors while keeping the presently used readout ASICs. By intelligence we mean the ability of the sensor to recognize a particle hit and generate the address information. In this way we could benefit from the advantages of the HV sensor technology such as lower cost, lower mass, lower operating voltage, smaller pitch, smaller clusters at high incidence angles. Additionally we expect to achieve a radiation hardness necessary for ATLAS upgrade. In order to test the concept, we have designed two HV-CMOS prototypes that can be readout in two ways: using pixel and strip readout chips. In the case of the pixel readout, the connection between HV-CMOS sensor and the readout ASIC can be established capacitively.

  10. Planar slim-edge pixel sensors for the ATLAS upgrades

    International Nuclear Information System (INIS)

    Altenheiner, S; Goessling, C; Jentzsch, J; Klingenberg, R; Lapsien, T; Rummler, A; Troska, G; Wittig, T; Muenstermann, D

    2012-01-01

    The ATLAS detector at CERN is a general-purpose experiment at the Large Hadron Collider (LHC). The ATLAS Pixel Detector is the innermost tracking detector of ATLAS and requires a sufficient level of hermeticity to achieve superb track reconstruction performance. The current planar n-type pixel sensors feature a pixel matrix of n + -implantations which is (on the opposite p-side) surrounded by so-called guard rings to reduce the high voltage stepwise towards the cutting edge and an additional safety margin. Because of the inactive region around the active area, the sensor modules have been shingled on top of each other's edge which limits the thermal performance and adds complexity in the present detector. The first upgrade phase of the ATLAS pixel detector will consist of the insertable b-layer (IBL), an additional b-layer which will be inserted into the present detector in 2013. Several changes in the sensor design with respect to the existing detector had to be applied to comply with the IBL's specifications and are described in detail. A key issue for the ATLAS upgrades is a flat arrangement of the sensors. To maintain the required level of hermeticity in the detector, the inactive sensor edges have to be reduced to minimize the dead space between the adjacent detector modules. Unirradiated and irradiated sensors with the IBL design have been operated in test beams to study the efficiency performance in the sensor edge region and it was found that the inactive edge width could be reduced from 1100 μm to less than 250 μm.

  11. Operational experience of ATLAS SCT and Pixel Detector

    CERN Document Server

    Kocian, Martin; The ATLAS collaboration

    2017-01-01

    The ATLAS Inner Detector based on silicon sensors is consisting of a strip detector (SCT) and a pixel detector. It is the crucial component for vertexing and tracking in the ATLAS experiment. With the excellent performance of the LHC well beyond the original specification the silicon tracking detectors are facing substantial challenges in terms of data acquisition, radiation damage to the sensors, and SEUs in the readout ASICs. The approaches on how the detector systems cope with the demands of high luminosity operation while maintaining excellent performance through hardware upgrades, software and firmware algorithms, and operational settings, are presented.

  12. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. In the ATLAS track reconstruction algorithm, an artificial neural network is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The robustness of the neural network algorithm is presented, probing its sensitivity to uncertainties in the detector conditions. The robustness is studied by evaluating the stability of the algorithm's performance under a range of variations in the inputs to the neural networks. Within reasonable variation magnitudes, the neural networks prove to be robust to most variation types.

  13. Optical Links for the ATLAS Pixel Detector

    CERN Document Server

    Gregor, Ingrid-Maria

    In der vorliegenden Dissertation wird eine strahlentolerante optische Datenstrecke mit hoher Datenrate für den Einsatz in dem Hochenergiephysikexperiment Atlas am Lhc Beschleuniger entwickelt. Da die Lhc-Experimente extremen Strahlenbelastungen ausgesetzt sind, müssen die Komponenten spezielle Ansprüche hinsichtlich der Strahlentoleranz erfüllen. Die Qualifikation der einzelnen Bauteile wurde im Rahmen dieser Arbeit durchgeführt. Die zu erwartenden Fluenzen im Atlas Inner Detector für Silizium und Gallium Arsenid (GaAs) wurden berechnet. Siliziumbauteile werden einer Fluenz von bis zu 1.1.1015neq /cm2 in 1 MeV äquivalenten Neutronen ausgesetzt sein, wohingegen GaAs Bauteile bis zu 7.8.1015neq /cm2 ausgesetzt sein werden. Die Strahlentoleranz der einzelnen benötigten Komponenten wie z.B. der Laserdioden sowie der jeweiligen Treiberchips wurde untersucht. Sowohl die Photo- als auch die Laserdioden haben sich als strahlentolerant für die Fluenzen an dem vorgesehenen Radius erwiesen. Aus de...

  14. The hardware of the ATLAS Pixel Detector Control System

    International Nuclear Information System (INIS)

    Henss, T; Andreani, A; Boek, J; Boyd, G; Citterio, M; Einsweiler, K; Kersten, S; Kind, P; Lantzsch, K; Latorre, S; Maettig, P; Meroni, C; Sabatini, F; Schultes, J

    2007-01-01

    The innermost part of the ATLAS (A Toroidal LHC ApparatuS) experiment, which is currently under construction at the LHC (Large Hadron Collider), will be a silicon pixel detector comprised of 1744 individual detector modules. To operate these modules, the readout electronics, and other detector components, a complex power supply and control system is necessary. The specific powering and control requirements, as well as the custom made components of our power supply and control systems, are described. These include remotely programmable regulator stations, the power supply system for the optical transceivers, several monitoring units, and the Interlock System. In total, this comprises the Pixel Detector Control System (DCS)

  15. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2008-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

  16. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

  17. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  18. THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

    DEFF Research Database (Denmark)

    Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

    2018-01-01

    as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players.......This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...

  19. Online Calibration and Performance of the ATLAS Pixel Detector

    CERN Document Server

    Keil, M

    2011-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. It consists of 1744 silicon sensors equipped with approximately 80 million electronic channels, providing typically three measurement points with high resolution for particles emerging from the beam-interaction region, thus allowing measuring particle tracks and secondary vertices with very high precision. The readout system of the Pixel Detector is based on a bi-directional optical data transmission system between the detector and the data acquisition system with an individual link for each of the 1744 modules. Signal conversion components are located on both ends, approximately 80 m apart. This paper describes the tuning and calibration of the optical links and the detector modules, including measurements of threshold, noise, charge measurement, timing performance and the sensor leakage current.

  20. Design studies on sensors for the ATLAS Pixel Detector

    CERN Document Server

    Hügging, F G

    2002-01-01

    For the ATLAS Pixel Detector, prototype sensors have been successfully developed. For the sensors design, attention was given to survivability of the harsh LHC radiation environment leading to the need to operate them at several hundreds of volts, while maintaining a good charge collection efficiency, small cell size and minimal multiple scattering. For a cost effective mass production, a bias grid is implemented to test the sensors before assembly under full bias. (6 refs).

  1. Monitoring the Radiation Damage of the ATLAS Pixel Detector

    CERN Document Server

    Cooke, M; The ATLAS collaboration

    2012-01-01

    The Pixel Detector is the innermost charged particle tracking component employed by the ATLAS experiment at the CERN Large Hadron Collider (LHC). The instantaneous luminosity delivered by the LHC, now routinely in excess of 5x10^{33} cm^{-2} s^{-1}, results in a rapidly increasing accumulated radiation dose to the detector. Methods based on the sensor depletion properties and leakage current are used to monitor the evolution of the radiation damage, and results from the 2011 run are presented.

  2. Monitoring the radiation damage of the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Cooke, M.

    2013-01-01

    The pixel detector is the innermost charged particle tracking component employed by the ATLAS experiment at the CERN Large Hadron Collider (LHC). The instantaneous luminosity delivered by the LHC, now routinely in excess of 5×10 33 cm −2 s −1 , results in a rapidly increasing accumulated radiation dose to the detector. Methods based on the sensor depletion properties and leakage current are used to monitor the evolution of the radiation damage, and results from the 2011 run are presented

  3. Monitoring radiation damage in the ATLAS pixel detector

    CERN Document Server

    Schorlemmer, André Lukas; Quadt, Arnulf; Große-Knetter, Jörn; Rembser, Christoph; Di Girolamo, Beniamino

    2014-11-05

    Radiation hardness is one of the most important features of the ATLAS pixel detector in order to ensure a good performance and a long lifetime. Monitoring of radiation damage is crucial in order to assess and predict the expected performance of the detector. Key values for the assessment of radiation damage in silicon, such as the depletion voltage and depletion depth in the sensors, are measured on a regular basis during operations. This thesis summarises the monitoring program that is conducted in order to assess the impact of radiation damage and compares it to model predictions. In addition, the physics performance of the ATLAS detector highly depends on the amount of disabled modules in the ATLAS pixel detector. A worrying amount of module failures was observed during run I. Thus it was decided to recover repairable modules during the long shutdown (LS1) by extracting the pixel detector. The impact of the module repairs and module failures on the detector performance is analysed in this thesis.

  4. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Ducourthial, Audrey; The ATLAS collaboration

    2017-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15} n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside...

  5. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    Summary ATLAS is preparing for an extensive modification of its detector in the course of the planned HL‐ LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all‐silicon detector (Inner Tracker, ITk). A revised trigger and data taking system is foreseen with triggers expected at lowest level at an average rate of 1 MHz. The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL‐LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in early 2017. A new on‐detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on‐going R&D within the ATLAS ITK project towards the new pixel modules and the off‐detector electronics. Pla...

  6. Module and electronics developments for the ATLAS ITK pixel system

    CERN Document Server

    Munoz Sanchez, Francisca Javiela; The ATLAS collaboration

    2017-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m2, depending on the final layout choice that is expected to take place in 2017. A new on-detector readout chip is designed in the context of the RD53 collaboration in 65 nm CMOS technology. This paper will present the on-going R&D within the ATLAS ITK project towards the new pixel modules and the off-detector electronics. Planar and 3D sensors are being re-designed with cell sizes of 50x50 or 25x100 μm2, compatible with the RD53 chip. A sensor thickness equal or less th...

  7. Modeling radiation damage to pixel sensors in the ATLAS detector

    CERN Document Server

    Ducourthial, Audrey; The ATLAS collaboration

    2017-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of $10^{15}n_{eq}/cm^2$ and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside ...

  8. Modeling radiation damage to pixel sensors in the ATLAS detector

    Science.gov (United States)

    Ducourthial, A.

    2018-03-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC) . As the closest detector component to the interaction point, these detectors will be subject to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC) [1], the innermost layers will receive a fluence in excess of 1015 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is essential in order to make accurate predictions for current and future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects on the ATLAS pixel sensors for the first time. In addition to thoroughly describing the setup, we present first predictions for basic pixel cluster properties alongside early studies with LHC Run 2 proton-proton collision data.

  9. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  10. Development of a Micro Pixel Chamber for the ATLAS Upgrade

    CERN Document Server

    Ochi, Atsuhiko; Komai, Hidetoshi; Edo, Yuki; Yamaguchi, Takahiro

    2012-01-01

    The Micro Pixel Chamber (μ-PIC) is being developed a sacandidate for the muon system of the ATLAS detector for upgrading in LHC experiments. The μ-PIC is a micro-pattern gaseous detector that doesn’t have floating structure such as wires, mesh, or foil. This detector can be made by printed-circuit-board (PCB) technology, which is commercially available and suited for mass production. Operation tests have been performed under high flux neutrons under similar conditions to the ATLAS cavern. Spark rates are measured using several gas mixtures under 7 MeV neutron irradiation, and good properties were observed using neon, ethane, and CF4 mixture of gases.Using resistive materials as electrodes, we are also developing a new μ-PIC, which is not expected to damage the electrodes in the case of discharge sparks.

  11. Robustness of the ATLAS pixel clustering neural network algorithm

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407780; The ATLAS collaboration

    2016-01-01

    Proton-proton collisions at the energy frontier puts strong constraints on track reconstruction algorithms. The algorithms depend heavily on accurate estimation of the position of particles as they traverse the inner detector elements. An artificial neural network algorithm is utilised to identify and split clusters of neighbouring read-out elements in the ATLAS pixel detector created by multiple charged particles. The method recovers otherwise lost tracks in dense environments where particles are separated by distances comparable to the size of the detector read-out elements. Such environments are highly relevant for LHC run 2, e.g. in searches for heavy resonances. Within the scope of run 2 track reconstruction performance and upgrades, the robustness of the neural network algorithm will be presented. The robustness has been studied by evaluating the stability of the algorithm’s performance under a range of variations in the pixel detector conditions.

  12. ATLAS Phase-II upgrade pixel data transmission development

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00111400; The ATLAS collaboration

    2017-01-01

    The current tracking system of the ATLAS experiment will be replaced by an all-silicon detector (ITk) in the course of the planned HL-LHC accelerator upgrade around 2025. The readout of the ITk pixel system will be most challenging in terms of data rate and readout speed. Simulation of the on-detector electronics indicates that the planned trigger rate of 1 MHz will require readout speeds up to 5.12 Gb/s per data link. The high-radiation environment precludes optical data transmission, so the first part of the data transmission has to be implemented electrically, over a 6-m distance between the pixel modules and the optical transceivers. Several high-speed electrical data transmission solutions involving small-gauge wire cables or flexible circuits have been prototyped and characterized. A combination of carefully-selected physical layers and aggressive signal conditioning are required to achieve the proposed specifications.

  13. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Rummler, Andr{e}; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown around 2025 by an all-silicon detector (Inner Tracker, ITk). The pixel detector will be composed by the five innermost layers, instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m^2, depending on the final layout choice that is expected to take place in early 2017. Different designs of planar, 3D, CMOS sensors are being investigated to identify the optimal technology for the different pixel layers. In parallel sensor-chip interconnection options are evaluated in collaboration with industrial partners to identify reliable technologies when employing 100-150 μm thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off detector read-out electronics will be implemented in the frame...

  14. Module and Electronics Developments for the ATLAS ITK Pixel System

    CERN Document Server

    Nellist, Clara; The ATLAS collaboration

    2016-01-01

    ATLAS is preparing for an extensive modification of its detector in the course of the planned HL-LHC accelerator upgrade around 2025 which includes a replacement of the entire tracking system by an all-silicon detector (Inner Tracker, ITk). The five innermost layers of ITk will comprise of a pixel detector built of new sensor and readout electronics technologies to improve the tracking performance and cope with the severe HL-LHC environment in terms of occupancy and radiation. The total area of the new pixel system could measure up to 14 m$^{2}$, depending on the final layout choice that is expected to take place in early 2017. An intense R\\&D activity is taking place in the field of planar, 3D, CMOS sensors to identify the optimal technology for the different pixel layers. In parallel various sensor-chip interconnection options are explored to identify reliable technologies when employing 100-150~$\\mu$m thin chips. While the new read-out chip is being developed by the RD53 Collaboration, the pixel off de...

  15. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Rossini, Lorenzo; The ATLAS collaboration

    2018-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High-Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of 10^15 neq/cm^2 and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current and future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time and considers both planar and 3D sensor designs. In addition to thoroughly describing the setup, we compare predictions for b...

  16. Pixel-Cluster Counting Luminosity Measurement in ATLAS

    CERN Document Server

    McCormack, William Patrick; The ATLAS collaboration

    2016-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measurements of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster-counting method are ...

  17. Pixel-Cluster Counting Luminosity Measurement In ATLAS

    CERN Document Server

    AUTHOR|(SzGeCERN)782710; The ATLAS collaboration

    2017-01-01

    A precision measurement of the delivered luminosity is a key component of the ATLAS physics program at the Large Hadron Collider (LHC). A fundamental ingredient of the strategy to control the systematic uncertainties affecting the absolute luminosity has been to compare the measure- ments of several luminometers, most of which use more than one counting technique. The level of consistency across the various methods provides valuable cross-checks as well as an estimate of the detector-related systematic uncertainties. This poster describes the development of a luminosity algorithm based on pixel-cluster counting in the recently installed ATLAS inner b-layer (IBL), using data recorded during the 2015 pp run at the LHC. The noise and background contamination of the luminosity-associated cluster count is minimized by a multi-component fit to the measured cluster-size distribution in the forward pixel modules of the IBL. The linearity, long-term stability and statistical precision of the cluster- counting method a...

  18. Modeling Radiation Damage to Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Rossini, Lorenzo; The ATLAS collaboration

    2018-01-01

    Silicon pixel detectors are at the core of the current and planned upgrade of the ATLAS detector at the Large Hadron Collider (LHC). As the closest detector component to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the High- Luminosity LHC (HL-LHC), the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-HLC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. Simulating radiation damage is critical in order to make accurate predictions for current future detector performance that will enable searches for new particles and forces as well as precision measurements of Standard Model particles such as the Higgs boson. We present a digitization model that includes radiation damage effects to the ATLAS pixel sensors for the first time and considers both planar and 3D sensor designs. In addition to thoroughly describing the setup, we compare predictions for basic...

  19. Functional description of APS beamline front ends

    International Nuclear Information System (INIS)

    Kuzay, T.

    1993-02-01

    Traditional synchrotron sources were designed to produce bending magnet radiation and have proven to be an essential scientific tool. Currently, a new generation of synchrotron sources is being built that will be able to accommodate a large number of insertion device (ID) and high quality bending magnet (BM) sources. One example is the 7-GeV Advanced Photon Source (APS) now under construction at Argonne National Laboratory. The research and development effort at the APS is designed to fully develop the potential of this new generation of synchrotron sources. Of the 40 straight sections in the APS storage ring, 34 will be available for IDs. The remaining six sections are reserved for the storage ring hardware and diagnostics. Although the ring incorporates 80 BMs, only 40 of them can be used to extract radiation. The accelerator hardware shadows five of these 40 bending magnets, so the maximum number of BM sources on the lattice is 35. Generally, a photon beamline consists of four functional sections. The first section is the ID or the BM, which provides the radiation source. The second section, which is immediately outside the storage ring but inside a concrete shielding tunnel, is the front end, which is designed to control, define, and/or confine the x-ray beam. In the case of the APS, the front ends are designed to confine the photon beam. The third section, just outside the concrete shielding tunnel and on the experimental floor, is the first optics enclosure, which contains optics to filter and monochromatize the photon beam. The fourth section of a beamline consists of beam transports, additional optics, and experiment stations to do the scientific investigations. This document describes only the front ends of the APS beamlines

  20. Transfer Function and Fluorescence Measurements on New CMOS Pixel Sensor for ATLAS

    CERN Document Server

    Kaemingk, Michael

    2017-01-01

    A new generation of pixel sensors is being designed for the phase II upgrade of the ATLAS Inner Tracker (ITk). These pixel sensors are being tested to ensure that they meet the demands of the ATLAS detector. As a summer student, I was involved in some of the measurements taken for this purpose.

  1. Design of analog pixels front-end active feedback

    Science.gov (United States)

    Kmon, P.; Kadlubowski, L. A.; Kaczmarczyk, P.

    2018-01-01

    The paper presents the design of the active feedback used in a charge-sensitive amplifier. The predominant advantages of the presented circuit are its ability for setting wide range of pulse-time widths, small silicon area occupation and low power consumption. The feedback also allows sensor leakage current compensation and, thanks to an additional DC amplifier, it minimizes the output DC voltage variations, which is especially important in the DC coupled recording chain and for processes with limited supply voltage. The paper provides feedback description and its operation principle. The proposed circuit was designed in the CMOS 130nm technology.

  2. ATLAS Pixel Detector Design For HL-LHC

    CERN Document Server

    Smart, Ben; The ATLAS collaboration

    2016-01-01

    The ATLAS Inner Detector will be replaced for the High-Luminosity LHC (HL-LHC) running in 2026. The new Inner Detector will be called the Inner Tracker (ITk). The ITk will cover an extended eta-range: at least to |eta|<3.2, and likely up to |eta|<4.0. The ITk will be an all-Silicon based detector, consisting of a Silicon strip detector outside of a radius of 362mm, and a Silicon pixel detector inside of this radius. Several novel designs are being considered for the ITk pixel detector, to cope with high-eta charged particle tracks. These designs are grouped into 'extended' and 'inclined' design-types. Extended designs have long pixel staves with sensors parallel to the beamline. High-eta particles will therefore hit these sensors at shallow angles, leaving elongated charge clusters. The length of such a charge cluster can be used to estimate the angle of the passing particle. This information can then be used in track reconstruction to improve tracking efficiency and reduce fake rates. Inclined designs ...

  3. PMF: The front end electronic of the ALFA detector

    Energy Technology Data Exchange (ETDEWEB)

    Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

    2010-11-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  4. PMF: the front end electronic of the ALFA detector

    CERN Document Server

    Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

    2010-01-01

    The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

  5. The ALICE TPC front end electronics

    CERN Document Server

    Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

    2004-01-01

    In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

  6. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    . The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... for new solutions in the unpredictable non-linear processes. The study uses an ethnographic approach using qualitative data from interviews, company documents, external communication and marketing material, minutes of meetings, informal conversations and observations. The analysis of four FFE processes...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

  7. The CMS Tracker Readout Front End Driver

    CERN Document Server

    Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

    2004-01-01

    The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

  8. Implementation and performance of the ATLAS pixel clustering neural networks

    CERN Document Server

    Gagnon, Louis-Guillaume; The ATLAS collaboration

    2018-01-01

    The high particle densities produced by the Large Hadron Collider (LHC) mean that in the ATLAS pixel detector the clusters of deposited charge start to merge. A neural network-based approach is used to estimate the number of particles contributing to each cluster, and to accurately estimate the hit positions even in the presence of multiple particles. This talk thoroughly describes the algorithm and its implementation as well as present a set of benchmark performance measurements. The problem is most acute in the core of high-momentum jets where the average separation between particles becomes comparable to the detector granularity. This is further complicated by the high number of interactions per bunch crossing. Both these issues will become worse as the Run 3 and HL-LHC programme require analysis of higher and higher pT jets, while the interaction multiplicity rises. Future prospects in the context of LHC Run 3 and the upcoming ATLAS inner detector upgrade are also discussed.

  9. Thin and edgeless sensors for ATLAS pixel detector upgrade

    Science.gov (United States)

    Ducourthial, A.; Bomben, M.; Calderini, G.; Marchiori, G.; D'Eramo, L.; Luise, I.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Darbo, G.; Dalla Betta, G.-F.; Giacomini, G.; Meschini, M.; Messineo, A.; Ronchin, S.; Zorzi, N.

    2017-12-01

    To cope with the harsh environment foreseen at the high luminosity conditions of HL-LHC, the ATLAS pixel detector has to be upgraded to be fully efficient with a good granularity, a maximized geometrical acceptance and an high read out rate. LPNHE, FBK and INFN are involved in the development of thin and edgeless planar pixel sensors in which the insensitive area at the border of the sensor is minimized thanks to the active edge technology. In this paper we report on two productions, a first one consisting of 200 μm thick n-on-p sensors with active edge, a second one composed of 100 and 130 μm thick n-on-p sensors. Those sensors have been tested on beam, both at CERN-SPS and at DESY. In terms of hit-efficiency, the first production reaches 99 % before irradiation and the second one reaches 96.3% after a fluence in excess of 1× 1016neq/cm2. The performances of those two productions before and after irradiation will be presented in details.

  10. The Phase II ATLAS Pixel Upgrade: The Inner Tracker (ITk)

    CERN Document Server

    Flick, Tobias; The ATLAS collaboration

    2016-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase II shutdown (foreseen to take place around 2025) by an all-silicon detector called the ITk (Inner Tracker). The pixel detector will comprise the five innermost layers, and will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation. The total surface area of silicon in the new pixel system could measure up to 14 m^2, depending on the final layout choice, which is expected to take place in early 2017. Four layout options are being investigated at the moment, two with forward coverage to eta < 3.2 and two to eta < 4. For each coverage option, a layout with long barrel staves and a layout with novel inclined support structures in the barrel-endcap overlap region are considered. All potential layouts include modules mounted on ring-shaped supports in the endcap regions. Support...

  11. The Phase-II ATLAS ITk Pixel Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00349918; The ATLAS collaboration

    2017-01-01

    The entire tracking system of the ATLAS experiment will be replaced during the LHC Phase~2 shutdown (foreseen to take place around 2025) by an all-silicon detector called the ``ITk'' (Inner Tracker). The innermost portion of ITk will consist of a pixel detector with five layers in the barrel region and ring-shaped supports in the end-cap regions. It will be instrumented with new sensor and readout electronics technologies to improve the tracking performance and cope with the HL-LHC environment, which will be severe in terms of occupancy and radiation levels. The new pixel system could include up to 14 $\\mathrm{m^2}$ of silicon, depending on the final layout, which is expected to be decided in 2017. Several layout options are being investigated at the moment, including some with novel inclined support structures in the barrel end-cap overlap region and others with very long innermost barrel layers. Forward coverage could be as high as |eta| $<4$. Supporting structures will be based on low mass, highly stabl...

  12. Realisation of serial powering of ATLAS pixel modules

    CERN Document Server

    Stockmanns, Tobias; Fischer, P; Hügging, Fabian Georg; Peric, Ivan; Runólfsson, Ogmundur; Wermes, Norbert

    2004-01-01

    Modern hybrid pixel detectors as they will be used for the next generation of high energy collider experiments like LHC avail deep sub micron technology for the readout electronics. To operate chips in this technology low supply voltages of 2.0 V to 2.5 V and high currents to achieve the desired performance are needed. Due to the long and low mass supply cables this high current leads to a significant voltage drop so that voltage fluctuations at the chip result, when the supply current changes. Therefore the parallel connection of the readout electronics with the power supplies imposes severe constraints on a detector with respect to voltage fluctuations and cable mass. To bypass this problem a new concept of serially connecting modules in a supply chain was developed. The basic idea of the concept, the potential risk and ways to minimize these risks are presented. In addition, studies of the implementation of this technology as an alternative for a possible upgrade of the ATLAS pixel detector are shown. In p...

  13. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    Energy Technology Data Exchange (ETDEWEB)

    Mathes, Markus

    2008-12-15

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10{sup 16} particles per cm{sup 2} per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 {mu}m{sup 2} have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm{sup 2} and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm{sup 2}). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  14. Development and characterization of diamond and 3D-silicon pixel detectors with ATLAS-pixel readout electronics

    International Nuclear Information System (INIS)

    Mathes, Markus

    2008-12-01

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10 16 particles per cm 2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 x 50 μm 2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm 2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 x 6 cm 2 ). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection inside a pixel cell as well as the charge sharing between adjacent pixels was studied using a high energy particle beam. (orig.)

  15. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  16. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    International Nuclear Information System (INIS)

    Prele, D.

    2015-01-01

    As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

  17. Iterative local Chi2 alignment algorithm for the ATLAS Pixel detector

    CERN Document Server

    Göttfert, Tobias

    The existing local chi2 alignment approach for the ATLAS SCT detector was extended to the alignment of the ATLAS Pixel detector. This approach is linear, aligns modules separately, and uses distance of closest approach residuals and iterations. The derivation and underlying concepts of the approach are presented. To show the feasibility of the approach for Pixel modules, a simplified, stand-alone track simulation, together with the alignment algorithm, was developed with the ROOT analysis software package. The Pixel alignment software was integrated into Athena, the ATLAS software framework. First results and the achievable accuracy for this approach with a simulated dataset are presented.

  18. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  19. Performance and operation experience of the Atlas Semiconductor Tracker and Pixel Detector at the LHC.

    CERN Document Server

    Stanecka, E; The ATLAS collaboration

    2013-01-01

    After more than 3 years of successful operation at the LHC, we report on the operation and performance of the ATLAS Pixel Detector and Semi-Conductor Tracker (SCT) functioning in a high luminosity, high radiation environment.

  20. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  1. The upgraded CDF front end electronics for calorimetry

    Energy Technology Data Exchange (ETDEWEB)

    Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

    1991-11-01

    The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 {mu}Sec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals.

  2. The upgraded CDF front end electronics for calorimetry

    International Nuclear Information System (INIS)

    Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

    1991-11-01

    The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

  3. Development and Characterization of Diamond and 3D-Silicon Pixel Detectors with ATLAS-Pixel Readout Electronics

    CERN Document Server

    Mathes, Markus

    2008-01-01

    Hybrid pixel detectors are used for particle tracking in the innermost layers of current high energy experiments like ATLAS. After the proposed luminosity upgrade of the LHC, they will have to survive very high radiation fluences of up to 10^16 particles per cm^2 per life time. New sensor concepts and materials are required, which promise to be more radiation tolerant than the currently used planar silicon sensors. Most prominent candidates are so-called 3D-silicon and single crystal or poly-crystalline diamond sensors. Using the ATLAS pixel electronics different detector prototypes with a pixel geometry of 400 × 50 um^2 have been built. In particular three devices have been studied in detail: a 3D-silicon and a single crystal diamond detector with an active area of about 1 cm^2 and a poly-crystalline diamond detector of the same size as a current ATLAS pixel detector module (2 × 6 cm^2). To characterize the devices regarding their particle detection efficiency and spatial resolution, the charge collection ...

  4. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

  5. MMIC tuned front-end for a coherent optical receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

    1993-01-01

    A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

  6. Quality control on planar n-in-n pixel sensors — Recent progress of ATLAS planar pixel sensors

    International Nuclear Information System (INIS)

    Klingenberg, R.

    2013-01-01

    To extend the physics reach of the Large Hadron Collider (LHC), upgrades to the accelerator are planned which will increase the peak luminosity by a factor 5–10. To cope with the increased occupancy and radiation damage, the ATLAS experiment plans to introduce an all-silicon inner tracker with the high luminosity upgrade (HL-LHC). To investigate the suitability of pixel sensors using the proven planar technology for the upgraded tracker, the ATLAS Upgrade Planar Pixel Sensor (PPS) R and D Project was established. Main areas of research are the performance of planar pixel sensors at highest fluences, the exploration of possibilities for cost reduction to enable the instrumentation of large areas, the achievement of slim or active edges to provide low geometric inefficiencies without the need for shingling of modules and the investigation of the operation of highly irradiated sensors at low thresholds to increase the efficiency. The Insertable b-layer (IBL) is the first upgrade project within the ATLAS experiment and will employ a new detector layer consisting of silicon pixel sensors, which were improved and prototyped in the framework of the planar pixel sensor R and D project. A special focus of this paper is the status of the development and testing of planar n-in-n pixel sensors including the quality control of the on-going series production and postprocessing of sensor wafers. A high yield of produced planar sensor wafers and FE-I4 double chip sensors after first steps of post-processing including under bump metallization and dicing is observed. -- Highlights: ► Prototypes of irradiated planar n-in-n sensors have been successfully tested under laboratory conditions. ► A quality assurance programme on the series production of planar sensors for the IBL has started. ► A high yield of double chip sensors during the series production is observed which are compatible to the specifications to this detector component.

  7. Status of the ATLAS Pixel Detector and its performance after three years of operation

    CERN Document Server

    Favareto, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is very important for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, and a good alignment allows high quality track resolution

  8. Status of the ATLAS Pixel Detector and its performance after three years of operation

    CERN Document Server

    Favareto, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is very important for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The detector performance is excellent: ~96% of the pixels are operational, noise occupancy and hit efficiency exceed the design specification, and a good alignment allows high quality track resolution.

  9. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

    International Nuclear Information System (INIS)

    Viel, Simon; Banerjee, Swagato; Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice; Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar; Pranko, Aliaksandr; Rieger, Julia; Wolf, Julian; Wu, Sau Lan; Yang, Hongtao

    2016-01-01

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN. - Highlights: • Extended inner pixel barrel layers are proposed for the ATLAS ITk upgrade. • Test beam results at small track incidence angles validate this ATLAS ITk design. • Long pixel clusters are reconstructed with high efficiency at low threshold values. • Excellent angular resolution is achieved using pixel cluster length information.

  10. Performance of silicon pixel detectors at small track incidence angles for the ATLAS Inner Tracker upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Viel, Simon, E-mail: sviel@lbl.gov [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Banerjee, Swagato [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Brandt, Gerhard; Carney, Rebecca; Garcia-Sciveres, Maurice [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Hard, Andrew Straiton; Kaplan, Laser Seymour; Kashif, Lashkar [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States); Pranko, Aliaksandr [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Rieger, Julia [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); II Physikalisches Institut, Georg-August-Universität, Göttingen (Germany); Wolf, Julian [Physics Division, Lawrence Berkeley National Laboratory and University of California, Berkeley, CA, United States of America (United States); Wu, Sau Lan; Yang, Hongtao [Department of Physics, University of Wisconsin, Madison, WI, United States of America (United States)

    2016-09-21

    In order to enable the ATLAS experiment to successfully track charged particles produced in high-energy collisions at the High-Luminosity Large Hadron Collider, the current ATLAS Inner Detector will be replaced by the Inner Tracker (ITk), entirely composed of silicon pixel and strip detectors. An extension of the tracking coverage of the ITk to very forward pseudorapidity values is proposed, using pixel modules placed in a long cylindrical layer around the beam pipe. The measurement of long pixel clusters, detected when charged particles cross the silicon sensor at small incidence angles, has potential to significantly improve the tracking efficiency, fake track rejection, and resolution of the ITk in the very forward region. The performance of state-of-the-art pixel modules at small track incidence angles is studied using test beam data collected at SLAC and CERN. - Highlights: • Extended inner pixel barrel layers are proposed for the ATLAS ITk upgrade. • Test beam results at small track incidence angles validate this ATLAS ITk design. • Long pixel clusters are reconstructed with high efficiency at low threshold values. • Excellent angular resolution is achieved using pixel cluster length information.

  11. The upgraded Pixel Detector of the ATLAS Experiment for Run 2 at the Large Hadron Collider

    Energy Technology Data Exchange (ETDEWEB)

    Backhaus, M., E-mail: malte.backhaus@cern.ch

    2016-09-21

    During Run 1 of the Large Hadron Collider (LHC), the ATLAS Pixel Detector has shown excellent performance. The ATLAS collaboration took advantage of the first long shutdown of the LHC during 2013 and 2014 and extracted the ATLAS Pixel Detector from the experiment, brought it to surface and maintained the services. This included the installation of new service quarter panels, the repair of cables, and the installation of the new Diamond Beam Monitor (DBM). Additionally, a completely new innermost pixel detector layer, the Insertable B-Layer (IBL), was constructed and installed in May 2014 between a new smaller beam pipe and the existing Pixel Detector. With a radius of 3.3 cm the IBL is located extremely close to the interaction point. Therefore, a new readout chip and two new sensor technologies (planar and 3D) are used in the IBL. In order to achieve best possible physics performance the material budget was improved with respect to the existing Pixel Detector. This is realized using lightweight staves for mechanical support and a CO{sub 2} based cooling system. This paper describes the improvements achieved during the maintenance of the existing Pixel Detector as well as the performance of the IBL during the construction and commissioning phase. Additionally, first results obtained during the LHC Run 2 demonstrating the distinguished tracking performance of the new Four Layer ATLAS Pixel Detector are presented.

  12. Status and future of the ATLAS Pixel Detector at the LHC

    International Nuclear Information System (INIS)

    Rozanov, Alexandre

    2013-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN. The detector provides hermetic coverage with three cylindrical layers and three layers of disks in each forward end-cap. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-on-n silicon substrates. Intensive calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. The record breaking instantaneous luminosities of 7.7×10 33 cm −2 s −1 recently surpassed at the LHC generated a rapidly increasing particle fluence in the ATLAS Pixel Detector. As the radiation dose accumulated, the first effects of radiation damage became observable in the silicon sensors as an increase in the silicon leakage current and the change of the voltage required to fully deplete the sensor. A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014) together with the replacement of pixel services. A letter of intent was submitted for a completely new Pixel Detector after 2023, capable to take data with extremely high leveled luminosities of 5×10 34 cm −2 s −1 at the high luminosity LHC. -- Highlights: •The ATLAS Pixel Detector provides hermetic coverage with three layers with 80 million pixels. •Calibration, tuning, timing optimization and monitoring resulted in the successful five years of operation with good detector performance. •First effects of radiation damage became observable in the silicon sensors. •A fourth pixel layer at a radius of 3.3 cm will be added during the long shutdown (2013–2014). •Replacement of pixel services in 2013–2014. •A letter of intent was submitted for new Pixel Detector after 2023 for high luminosity LHC

  13. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  14. Neural network based cluster creation in the ATLAS silicon Pixel Detector

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2013-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS Pixel Detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  15. Neural network based cluster creation in the ATLAS silicon pixel detector

    CERN Document Server

    Selbach, K E; The ATLAS collaboration

    2012-01-01

    The read-out from individual pixels on planar semi-conductor sensors are grouped into clusters to reconstruct the location where a charged particle passed through the sensor. The resolution given by individual pixel sizes is significantly improved by using the information from the charge sharing between pixels. Such analog cluster creation techniques have been used by the ATLAS experiment for many years to obtain an excellent performance. However, in dense environments, such as those inside high-energy jets, clusters have an increased probability of merging the charge deposited by multiple particles. Recently, a neural network based algorithm which estimates both the cluster position and whether a cluster should be split has been developed for the ATLAS pixel detector. The algorithm significantly reduces ambiguities in the assignment of pixel detector measurement to tracks within jets and improves the position accuracy with respect to standard interpolation techniques by taking into account the 2-dimensional ...

  16. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  17. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  18. Idea management in support of pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

  19. Fast front-end electronics for COMPASS MWPCs

    CERN Document Server

    Colantoni, M L; Ferrero, A; Frolov, V; Grasso, A; Heinz, S; Maggiora, A; Maggiora, M G; Panzieri, D; Popov, A; Tchalyshev, V

    2000-01-01

    In the COMPASS experiment, under construction at CERN, about 23000 channels of MWPCs will be used. The very high rate of the muon and hadron beams, and the consequently high trigger rate, require front- end electronics with innovative conceptual design. A new MWPC front- end electronics that fulfills the main COMPASS requirement to have a fast DAQ with a minimum dead-time has been designed. The general concept of the front-end cards is described; the comparative tests of two front-end chips, and different fast gas mixtures, are also shown. The commissioning of the experiment will start in the summer 2000, and production running, using the muon beam, is foreseen for the year 2001. (8 refs).

  20. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    Levi, M.

    1990-12-01

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  1. An Alternative Front End Analysis Strategy for Complex Systems

    Science.gov (United States)

    2014-12-01

    missile ( ABM ) system . Patriot is employed in the field through a battalion echelon organizational structure. The line battery is the basic building...Research Report 1981 An Alternative Front End Analysis Strategy for Complex Systems M. Glenn Cobb U.S. Army Research Institute...NUMBER W5J9CQ11D0003 An Alternative Front End Analysis Strategy for Complex Systems 5b. PROGRAM ELEMENT NUMBER 633007 6

  2. Radiation hardness on very front-end for SPD

    International Nuclear Information System (INIS)

    Cano, Xavier; Graciani, Ricardo; Gascon, David; Garrido, Lluis; Bota, Sebastia; Herms, Atila; Comerma, Albert; Riera, Jordi

    2005-01-01

    The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available

  3. Indico front-end: From spaghetti to lasagna

    CERN Multimedia

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  4. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages, high resistivity wafers for large depletion depths; radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R$\\&$D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this presentation the challenges for the usage of CMOS pixel...

  5. Radiation Damage Modeling for 3D Pixel Sensors in the ATLAS Detector

    CERN Document Server

    Wallangen, Veronica; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  6. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Giugliarelli, Gilberto; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10^15 neq/cm2 and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  7. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Wallangen, Veronica; The ATLAS collaboration

    2017-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS detector. As the detector in closest proximity to the interaction point, these detectors will be subjected to a significant amount of radiation over their lifetime: prior to the HL-LHC, the innermost layers will receive a fluence in excess of 10$^{15}$ n$_\\mathrm{eq}$/cm$^2$ and the HL-LHC detector upgrades must cope with an order of magnitude higher fluence integrated over their lifetimes. This work presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS detector.

  8. FE-I4 Chip Development for Upgraded ATLAS Pixel Detector at LHC

    CERN Document Server

    Barbero, M; The ATLAS collaboration

    2010-01-01

    A new ATLAS pixel chip FE-I4 has been developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer upgrade. FE-I4 is designed in a 130 nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 0.25 μm CMOS technology used for the current ATLAS pixel IC, FE-I3. FE-I4 architecture is based on an array of 80×336 pixels, each 50×250 μm2, consisting of analog and digital sections. The analog pixel section is designed for low power consumption and compatibility to several sensor candidates. It is based on a two-stage architecture with a pre-amp AC-coupled to a second stage of amplification. It features leakage current compensation circuitry, local 4-bit pre-amp feedback tuning and a discriminator locally adjusted through 5 configuration bits. The digital architecture is based on a 4-pixel unit called Pixel Digital Region (PDR) allowing for local storage of hits in 5-deep data buffers at pixel level for the duratio...

  9. Feedback from operational experience in front-end transportation

    International Nuclear Information System (INIS)

    Mondonel, J.L.; Parison, C.

    1998-01-01

    Transport forms an integral part of the nuclear fuel cycle, representing the strategic link between each stage of the cycle. In a way there is a transport cycle that parallels the nuclear fuel cycle. This concerns particularly the front-end of the cycle whose steps - mining conversion, enrichment and fuel fabrication - require numerous transports. Back-end shipments involve a handful of countries, but front-end transports involve all five continents, and many exotic countries. All over Europe such transports are routinely performed with an excellent safety track record. Transnucleaire dominates the French nuclear transportation market and carries out both front and back-end transports. For instance in 1996 more than 28,400 front-end packages were transported as well as more than 3,600 back-end packages. However front-end transport is now a business undergoing much change. A nuclear transportation company must now cope with an evolving picture including new technical requirements, new transportation schemes and new business conditions. This paper describes the latest evolutions in terms of front-end transportation and the way this activity is carried out by Transnucleaire, and goes on to discuss future prospects. (authors)

  10. MCC:the Module Controller Chip for the ATLAS Pixel Detector

    Czech Academy of Sciences Publication Activity Database

    Beccherle, R.; Darbo, G.; Gagliardi, G.; Šícho, Petr

    2002-01-01

    Roč. 492, 1-2 (2002), s. 117-133 ISSN 0168-9002 R&D Projects: GA MPO RP-4210/69 Institutional research plan: CEZ:AV0Z1010920 Keywords : ASIC * radiation hardness * silicon pixel detectors * ATLAS * LHC Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.167, year: 2002

  11. Monolithic pixel development in 180 nm CMOS for the outer pixel layers in the ATLAS experiment

    CERN Document Server

    Kugathasan, Thanushan; Buttar, Craig; Berdalovic, Ivan; Blochet, Bastien; Cardella, Roberto Calogero; Dalla, Marco; Egidos Plaja, Nuria; Hemperek, Tomasz; Van Hoorne, Jacobus Willem; Maneuski, Dima; Marin Tobon, Cesar Augusto; Moustakas, Konstantinos; Mugnier, Herve; Musa, Luciano; Pernegger, Heinz; Riedler, Petra; Riegel, Christian; Rousset, Jerome; Sbarra, Carla; Schaefer, Douglas Michael; Schioppa, Enrico Junior; Sharma, Abhishek; Snoeys, Walter; Solans Sanchez, Carlos; Wang, Tianyang; Wermes, Norbert

    2017-01-01

    The ATLAS experiment at CERN plans to upgrade its Inner Tracking System for the High-Luminosity LHC in 2026. After the ALPIDE monolithic sensor for the ALICE ITS was successfully implemented in a 180 nm CMOS Imaging Sensor technology, the process was modified to combine full sensor depletion with a low sensor capacitance (≈ 2.5fF), for increased radiation tolerance and low analog power consumption. Efficiency and charge collection time were measured with comparisons before and after irradiation. This paper summarises the measurements and the ATLAS-specific development towards full-reticle size CMOS sensors and modules in this modified technology.

  12. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    International Nuclear Information System (INIS)

    Savic, N.; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-01-01

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm"2). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm"2 pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  13. Thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Savic, N., E-mail: natascha.savic@mpp.mpg.de; Bergbreiter, L.; Breuer, J.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Terzo, S.

    2017-02-11

    The ATLAS experiment will undergo a major upgrade of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) foreseen to start around 2025. Thin planar pixel modules are promising candidates to instrument the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. New designs of the pixel cells, with an optimized biasing structure, have been implemented in n-in-p planar pixel productions with sensor thicknesses of 270 μm. Using beam tests, the gain in hit efficiency is investigated as a function of the received irradiation fluence. The outlook for future thin planar pixel sensor productions will be discussed, with a focus on thin sensors with a thickness of 100 and 150 μm and a novel design with the optimized biasing structure and small pixel cells (50×50 and 25×100 μm{sup 2}). These dimensions are foreseen for the new ATLAS read-out chip in 65 nm CMOS technology and the fine segmentation will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. To predict the performance of 50×50 μm{sup 2} pixels at high η, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle with respect to the short pixel direction. Results on cluster shapes, charge collection- and hit efficiency will be shown.

  14. Modeling Radiation Damage Effects in 3D Pixel Digitization for the ATLAS Detector

    CERN Document Server

    Giugliarelli, Gilberto; The ATLAS collaboration

    2018-01-01

    Silicon Pixel detectors are at the core of the current and planned upgrade of the ATLAS experiment. They constitute the part of ATLAS closest to the interaction point and for this reason they will be exposed – over their lifetime – to a significant amount of radiation: prior to the HL-LHC, the innermost layers will receive a fluence of 10^15 neq/cm2 and their HL–LHC upgrades will have to cope with an order of magnitude higher fluence integrated over their lifetimes. This poster presents the details of a new digitization model that includes radiation damage effects to the 3D Pixel sensors for the ATLAS Detector.

  15. Recent achievements of the ATLAS upgrade Planar Pixel Sensors R and D project

    International Nuclear Information System (INIS)

    Casse, G

    2014-01-01

    The ATLAS upgrade Planar Pixel Sensors (PPS) project aims to prove the suitability of silicon detectors processed with planar technology to equip all layers of the pixel vertex detector proposed for the upgrade of the ATLAS experiment for the future High Luminosity LHC at CERN (HL-LHC). The detectors need to be radiation tolerant to the extreme fluences expected to be received during the experimental lifetime, with optimised geometry for full coverage and high granularity and affordable in term of cost, due to the relatively large area of the upgraded ATLAS detector system. Here several solutions for the detector geometry and results with radiation hard technologies (n-in-n, n-in-p) are discussed

  16. Studies for the detector control system of the ATLAS pixel at the HL-LHC

    International Nuclear Information System (INIS)

    Püllen, L; Becker, K; Boek, J; Kersten, S; Kind, P; Mättig, P; Zeitnitz, C

    2012-01-01

    In the context of the LHC upgrade to the HL-LHC the inner detector of the ATLAS experiment will be replaced completely. As part of this redesign there will also be a new pixel detector. This new pixel detector requires a control system which meets the strict space requirements for electronics in the ATLAS experiment. To accomplish this goal we propose a DCS (Detector Control System) network with the smallest form factor currently available. This network consists of a DCS chip located in close proximity to the interaction point and a DCS controller located in the outer regions of the ATLAS detector. These two types of chips form a star shaped network with several DCS chips being controlled by one DCS controller. Both chips are manufactured in deep sub-micron technology. We present prototypes with emphasis on studies concerning single event upsets.

  17. CMOS pixel development for the ATLAS experiment at HL-LHC

    CERN Document Server

    Risti{c}, Branislav; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  18. A MCM-D-type module for the ATLAS pixel detector

    CERN Document Server

    Becks, K H; Ehrmann, O; Gerlach, P; Gregor, I M; Pieters, P; Topper, M; Truzzi, C; Wolf, J

    1999-01-01

    For the ATLAS experiment at the planned Large Hadron Collider LHC at CERN hybrid pixel detectors are being built as innermost layers of the inner tracking detector system. Modules are the basic building blocks of the ATLAS pixel $9 detector. A module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out IC's, each serving 24*160 pixel unit cells, a module controller chip, an optical transceiver and the local signal interconnection and $9 power distribution busses. The dies are attached by flip-chip assembly to the sensor diodes and the local busses. In the following a module based on MCM-D technology will be discussed and prototype results will be presented.

  19. Application of a new interconnection technology for the ATLAS pixel upgrade at SLHC

    CERN Document Server

    Macchiolo, A; Beimforde, M; Moser, H G; Nisius, R; Richter, R H

    2009-01-01

    We present an R&D activity aiming towards a new detector concept in the framework of the ATLAS pixel detector upgrade exploiting a vertical integration technology developed at the Fraunhofer Institute IZMMunich. The Solid-Liquid InterDiffusion (SLID) technique is investigated as an alternative to the bump-bonding process. We also investigate the extraction of the signals from the back of the read-out chip through Inter-Chip-Vias to achieve a higher fraction of active area with respect to the present ATLAS pixel module. We will present the layout and the first results obtained with a production of test-structures designed to investigate the SLID interconnection efficiency as a function of different parameters, i.e. the pixel size and pitch, as well as the planarity of the underlying layers.

  20. CMOS Pixel Development for the ATLAS Experiment at HL-LHC

    CERN Document Server

    Gaudiello, Andrea; The ATLAS collaboration

    2017-01-01

    To cope with the rate and radiation environment expected at the HL-LHC new approaches are being developed on CMOS pixel detectors, providing charge collection in a depleted layer. They are based on: HV enabling technologies that allow to use high depletion voltages (HV-MAPS), high resistivity wafers for large depletion depths (HR-MAPS); radiation hard processed with multiple nested wells to allow CMOS electronics embedded with sufficient shielding into the sensor substrate and backside processing and thinning for material minimization and backside voltage application. Since 2014, members of more than 20 groups in the ATLAS experiment are actively pursuing CMOS pixel R&D in an ATLAS Demonstrator program pursuing sensor design and characterizations. The goal of this program is to demonstrate that depleted CMOS pixels, with monolithic or hybrid designs, are suited for high rate, fast timing and high radiation operation at LHC. For this a number of technologies have been explored and characterized. In this pr...

  1. Concepts for a Muon Accelerator Front-End

    Energy Technology Data Exchange (ETDEWEB)

    Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

    2017-03-16

    We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

  2. Next generation of optical front-ends for numerical services - 15387

    International Nuclear Information System (INIS)

    Fullenbaum, M.; Durieux, A.; Dubroca, G.; Fuss, P.

    2015-01-01

    Visual Inspection and surveillance technology means in environments exhibiting high levels of gamma and neutron radiation are nowadays fulfilled through the use of analog tubes. The images are thus acquired with analog devices whose vast majority relies on 1 and 2/3 inch imaging formats and deliver native analog images. There is a growing demand for real time image processing and distribution through Ethernet services for quicker and seamless process integration throughout many sectors. This will call for the inception of solid state sensor (CCD, CMOS) to generate numerical native images as the first step and building block towards end to end numerical processing (ICT), assuming these sensors can be hardened or protected in the field of the nuclear industry. On the one hand, these sensor sizes will be significantly reduced (by a factor of 2-3) versus those of the tubes, and on the other hand, one will also be presented with the opportunity of increased spatial resolution, stemming from the high pixel count of the solid state technology, for implementation of new or better services or of enhanced pieces of information for decision making purposes. In order to reap the benefits of such sensors, new optical front-ends will have to be designed. Over and beyond the mere aspects of matching the reduced sensor size to the size of the scenes at stake, optical performances of these front-end will also bear an impact on the whole optical chain applications. As an example, detection and tracking needs will be different from a performance standpoint and the overall performances will have to be balanced out in between the optical front-end, the image format, the image processing software capability, processing speed,...just to name a few. In this paper we will review and explain the missing gaps in order to switch to a full numerical optical chain by focusing on the optical front-end and the associated cost trade-offs. Finally, we will conclude by clearly stating the best

  3. CMOS front-end electronics for radiation sensors

    CERN Document Server

    AUTHOR|(CDS)2071026

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  4. HINS Linac front end focusing system R&D

    Energy Technology Data Exchange (ETDEWEB)

    Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

    2008-08-01

    This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

  5. HINS Linac front end focusing system R and D

    International Nuclear Information System (INIS)

    Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; Fermilab; Argonne

    2008-01-01

    This report summarizes current status of an R and D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process

  6. REASONING IN THE FUZZY FRONT END OF INNOVATION:

    DEFF Research Database (Denmark)

    Haase, Louise Møller; Laursen, Linda Nhu

    2018-01-01

    in the fuzzy front end is the reasoning process: innovation teams are faced with open-ended, ill-defined problems, where they need to make decisions about an unknown future but have only incomplete, ambiguous and contradicting insights available. We study the reasoning of experts, how they frame to make sense...... of all the insights and create a basis for decision-making in relation to a new project. Based on case studies of five innovative products from various industries, we propose a Product DNA model for understanding the reasoning in the fuzzy front end of innovation. The Product DNA Model explains how...... experts reason and what direct their reasoning....

  7. Front-end electronics for the upgraded GMRT

    International Nuclear Information System (INIS)

    Raut, Anil N; Bhalerao, Vilas; Kumar, A Praveen

    2013-01-01

    This paper first describes briefly the existing front-end receiver in use at the GMRT observatory and then details the ongoing development of next generation receiver systems for the upgraded GMRT. It covers the design of the new, two stage, room temperature, low noise amplifiers with better noise performance and matching, and improved dynamic range that are being implemented for the 130–260 MHz, 250–500 MHz and 550–900 MHz bands of the upgraded GMRT front-end systems.

  8. Parallel and pipelined front-end for multi-element silicon detectors in scanning electron microscopy

    International Nuclear Information System (INIS)

    Boulin, C.; Epstein, A.

    1992-01-01

    This paper discusses a silicon quadrant detector (128 elements) implemented as an electron detector in a Scanning Transmission Electron Microscope. As the electron beam scans over the sample, electrons are counted during each pixel. The authors developed an ASIC for the multichannel counting system. The digital front-end carries out the readout of all elements, in four groups, and uses these data to compute linear combinations to generate up to eight simultaneous images. For the preprocessing the authors implemented a parallel and pipelined system. Dedicated software tools were developed to generate the programs for all the processors. These tools are transparently accessed by the user via a user friendly interface

  9. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  10. SEU tolerant memory design for the ATLAS pixel readout chip

    International Nuclear Information System (INIS)

    Menouni, M; Barbero, M; Breugnon, P; Fougeron, D; Gensolen, F; Arutinov, D; Backhaus, M; Gonella, L; Hemperek, T; Karagounis, M; Beccherle, R; Darbo, G; Caminada, L; Dube, S; Fleury, J; Garcia-Sciveres, M; Gnani, D; Jensen, F; Gromov, V; Kluit, R

    2013-01-01

    The FE-I4 chip for the B-layer upgrade is designed in a 130 nm CMOS process. For this design, configuration memories are based on the DICE latches where layout considerations are followed to improve the tolerance to SEU. Tests have shown that DICE latches for which layout approaches are adopted are 30 times more tolerant to SEU than the standard DICE latches. To prepare for the new pixel readout chip planned for the future upgrades, a prototype chip containing 512 pixels has been designed in a 65 nm CMOS process and a new approach is adopted for SEU tolerant latches. Results in terms of SEU and TID tolerance are presented.

  11. The Pixels find their way to the heart of ATLAS

    CERN Multimedia

    Kevin Einsweiler

    Since the last e-news article on the Pixel Detector in December 2006, there has been much progress. At that time, we were just about to receive the Beryllium beampipe, and to integrate the innermost layer of the Pixel Detector around it. This innermost layer is referred to as the B-layer because of the powerful role it plays in finding the secondary vertices that are the key signature for the presence of b-quarks, and with somewhat greater difficulty, c-quarks and tau leptons. The integration of the central 7m long beampipe into the Pixel Detector was completed in December, and the B-layer was successfully integrated around it. In January this year, we had largely completed the central 1.5m long detector, including the three barrel layers and the three disk layers on each end of the barrel. Although this region contains all of the 80 million readout channels, it cannot be integrated into the Inner Detector without additional services and infrastructure. Therefore, the next step was to add the Service Panels...

  12. Study of planar pixel sensors hardener to radiations for the upgrade of the ATLAS vertex detector

    International Nuclear Information System (INIS)

    Benoit, M.

    2011-05-01

    In this work, we present a study, using TCAD (Technology Computer-Assisted Design) simulation, of the possible methods of designing planar pixel sensors by reducing their inactive area and improving their radiation hardness for use in the Insertable B-Layer (IBL) project and for SLHC upgrade phase for the ATLAS experiment. Different physical models available have been studied to develop a coherent model of radiation damage in silicon that can be used to predict silicon pixel sensor behavior after exposure to radiation. The Multi-Guard Ring Structure, a protection structure used in pixel sensor design was studied to obtain guidelines for the reduction of inactive edges detrimental to detector operation while keeping a good sensor behavior through its lifetime in the ATLAS detector. A campaign of measurement of the sensor process parameters and electrical behavior to validate and calibrate the TCAD simulation models and results are also presented. A model for diode charge collection in highly irradiated environment was developed to explain the high charge collection observed in highly irradiated devices. A simple planar pixel sensor digitization model to be used in test beam and full detector system is detailed. It allows for easy comparison between experimental data and prediction by the various radiation damage models available. The digitizer has been validated using test beam data for unirradiated sensors and can be used to produce the first full scale simulation of the ATLAS detector with the IBL that include sensor effects such as slim edge and thinning of the sensor. (author)

  13. Effets de rayonnement sur les detecteurs au silicium a pixels du detecteur ATLAS

    CERN Document Server

    Lebel, Celine

    2007-01-01

    Two detection systems are using pixel silicon detectors in the ATLAS detector: the Pixel, which is the subdetector closest to the interaction point, and the MPX network. The activation of the materials present in the Pixel produced by radiation has been measured in two experiments which we performed at CERF (CERN) and NPI-ASCR (Czech Republic). These experimental studies of activation are com- pared with GEANT4 simulations. The results of these comparisons show that the simulation can predict the activities with a precision of an order of magnitude. They also show that GEANT4 fails to produce certain radioisotopes seen in the experimental activation studies. The contribution to background and the resid- ual doses due to the desintegration of the radioisotopes produced by fast neutrons (category in which falls the expected average neutron energy of 1 MeV in ATLAS) are extrapolated to ATLAS conditions. It is found that this background in the AT- LAS Pixel subdetector will be negligible and that the doses are we...

  14. Evaluation of testing strategies for the radiation tolerant ATLAS n **+-in-n pixel sensor

    CERN Document Server

    Klaiber Lodewigs, Jonas M

    2003-01-01

    The development of particle tracker systems for high fluence environments in new high-energy physics experiments raises new challenges for the development, manufacturing and reliable testing of radiation tolerant components. The ATLAS pixel detector for use at the LHC, CERN, is designed to cover an active sensor area of 1.8 m**2 with 1.1 multiplied by 10 **8 read-out channels usable for a particle fluence up to 10 **1**5 cm**-**2 (1 MeV neutron equivalent) and an ionization dose up to 500 kGy of mainly charged hadron radiation. To cope with such a harsh environment the ATLAS Pixel Collaboration has developed a radiation hard n **+-in-n silicon pixel cell design with a standard cell size of 50 multiplied by 400 mum**2. Using this design on an oxygenated silicon substrate, sensor production has started in 2001. This contribution describes results gained during the development of testing procedures of the ATLAS pixel sensor and evaluates quality assurance procedures regarding their relevance for detector operati...

  15. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  16. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  17. Front End Loader Operator. Open Pit Mining Job Training Series.

    Science.gov (United States)

    Savilow, Bill

    This training outline for front end loader operators, one in a series of eight outlines, is designed primarily for company training foremen or supervisors and for trainers to use as an industry-wide guideline for heavy equipment operator training in open pit mining in British Columbia. Intended as a guide for preparation of lesson plans both for…

  18. Front end readout electronics for the CMS hadron calorimeter

    International Nuclear Information System (INIS)

    Terri M. Shaw et al.

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm 2 . For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes

  19. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  20. A socio-internactive framework for the fuzzy front end

    NARCIS (Netherlands)

    Smulders, Frido E.; van den Broek, Egon; van der Voort, Mascha C.; Fernandes, A.; Teixeira, A.; Natal Jorge, R.

    2007-01-01

    This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary socio-interactive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive

  1. Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

    International Nuclear Information System (INIS)

    Libov, Vladyslav

    2013-08-01

    A measurement of charm and beauty production in Deep Inelastic Scattering at HERA is presented. The analysis is based on the data sample collected by the ZEUS detector in the period from 2003 to 2007 corresponding to an integrated luminosity of 354 pb -1 . The kinematic region of the measurement is given by 5 2 2 and 0.02 2 is the photon virtuality and y is the inelasticity. A lifetime technique is used to tag the production of charm and beauty quarks. Secondary vertices due to decays of charm and beauty hadrons are reconstructed, in association with jets. The jet kinematics is defined by E jet T >4.2(5) GeV for charm (beauty) and -1.6 jet jet T and η jet are the transverse energy and pseudorapidity of the jet, respectively. The significance of the decay length and the invariant mass of charged tracks associated with the secondary vertex are used as discriminating variables to distinguish between signal and background. Differential cross sections of jet production in charm and beauty events as a function of Q 2 , y, E jet T and η jet are measured. Results are compared to Next-to-Leading Order (NLO) predictions from Quantum Chromodynamics (QCD) in the fixed flavour number scheme. Good agreement between data and theory is observed. Contributions of the charm and beauty production to the inclusive proton structure function, F cbar c 2 and F b anti b 2 , are determined by extrapolating the double differential cross sections using NLO QCD predictions. Contributions to the test beam program for the Insertable B-Layer upgrade project of the ATLAS pixel detector are discussed. The test beam data analysis software package EUTelescope was extended, which allowed an efficient analysis of ATLAS pixel sensors. The USBPix DAQ system was integrated into the EUDET telescope allowing test beam measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

  2. Measurement of charm and beauty-production in deep inelastic scattering at HERA and test beam studies of ATLAS pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Libov, Vladyslav

    2013-08-15

    measurements with the front end chip FE-I4. Planar and 3D ATLAS pixel sensors were studied at the first IBL test beam at the CERN SPS.

  3. Operational Experience of the ATLAS SemiConductor Tracker and Pixel Detector

    CERN Document Server

    Robinson, Dave; The ATLAS collaboration

    2016-01-01

    The tracking performance of the ATLAS detector relies critically on the silicon and gaseous tracking subsystems that form the ATLAS Inner Detector. Those subsystems have undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the LHC during Run2. The key status and performance metrics of the Pixel Detector and the Semi Conductor Tracker are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency are described.

  4. ATLAS pixel IBL modules construction experience and developments for future upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gaudiello, A.

    2015-10-01

    The first upgrade of the ATLAS Pixel Detector is the Insertable B-Layer (IBL), installed in May 2014 in the core of ATLAS. Two different silicon sensor technologies, planar n-in-n and 3D, are used. Sensors are connected with the new generation 130 nm IBM CMOS FE-I4 read-out chip via solder bump-bonds. Production quality control tests were set up to verify and rate the performance of the modules before integration into staves. An overview of module design and construction, the quality control results and production yield will be discussed, as well as future developments foreseen for future detector upgrades.

  5. Training and validation of the ATLAS pixel clustering neural networks

    CERN Document Server

    The ATLAS collaboration

    2018-01-01

    The high centre-of-mass energy of the LHC gives rise to dense environments, such as the core of high-pT jets, in which the charge clusters left by ionising particles in the silicon sensors of the pixel detector can merge, compromising the tracking and vertexing efficiency. To recover optimal performance, a neural network-based approach is used to separate clusters originating from single and multiple particles and to estimate all hit positions within clusters. This note presents the training strategy employed and a set of benchmark performance measurements on a Monte Carlo sample of high-pT dijet events.

  6. Radiation Damage Observations in the ATLAS Pixel Detector Using the High Voltage Delivery System

    CERN Document Server

    Toms, K

    2011-01-01

    We describe the implementation of radiation damage monitoring using leakage current measurement of the silicon pixel sensors provided by the circuits of the ATLAS Pixel Detector high voltage delivery (HVPP4) system. The dependence of the leakage current upon the integrated luminosity for several temperature scenarios is presented. Based on the analysis we have determined the sensitivity specifications for a Current Measurement System. The status of the system and the first measurement of the radiation damage corresponding to 2--4 fb$^{-1}$ of integrated luminosity are presented, as well as the comparison with the theoretical model.

  7. Operational Experience and Performance with the ATLAS Pixel Detector at the Large Hadron Collider

    CERN Document Server

    Grummer, Aidan; The ATLAS collaboration

    2018-01-01

    The tracking performance of the ATLAS detector relies critically on its 4-layer Pixel Detector, that has undergone significant hardware and software upgrades to meet the challenges imposed by the higher collision energy, pileup and luminosity that are being delivered by the Large Hadron Collider, with record breaking instantaneous luminosities of 2 x 10^34 cm-2 s-1 recently surpassed. The key status and performance metrics of the ATLAS Pixel Detector are summarised, and the operational experience and requirements to ensure optimum data quality and data taking efficiency will be described, with special emphasis to radiation damage experience. In particular, radiation damage effects will be showed and signs of degradation which are visible but which are not impacting yet the tracking performance (but will): dE/dX, occupancy reduction with integrated luminosity, under-depletion effects with IBL in 2016, effects of annealing that is not insignificant for the inner-most layers. Therefore the offline software strat...

  8. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    International Nuclear Information System (INIS)

    Dalla Betta, Gian-Franco; Boscardin, Maurizio; Darbo, Giovanni; Gemme, Claudia; La Rosa, Alessandro; Pernegger, Heinz; Piemonte, Claudio; Povoli, Marco; Ronchin, Sabina; Zoboli, Andrea; Zorzi, Nicola

    2011-01-01

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

  9. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Dalla Betta, Gian-Franco, E-mail: dallabe@disi.unitn.it [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Boscardin, Maurizio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Darbo, Giovanni; Gemme, Claudia [INFN, Sezione di Genova, Via Dodecaneso 33, 16146 Genova (Italy); La Rosa, Alessandro; Pernegger, Heinz [CERN-PH, CH-1211 Geneve 23 (Switzerland); Piemonte, Claudio [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Povoli, Marco [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Ronchin, Sabina [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy); Zoboli, Andrea [INFN, Sezione di Padova (Gruppo Collegato di Trento), and DISI, Universita di Trento, Via Sommarive 14, 38123 Povo di Trento (Italy); Zorzi, Nicola [Fondazione Bruno Kessler (FBK-irst), Via Sommarive 18, 38123 Povo di Trento (Italy)

    2011-04-21

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are discussed here.

  10. New Technique for Luminosity Measurement Using 3D Pixel Modules in the ATLAS IBL Detector

    CERN Document Server

    Liu, Peilian; The ATLAS collaboration

    2017-01-01

    The Insertable b-Layer ( IBL ) is the innermost layer of the ATLAS tracking system. It consists of planar pixel modules in the central region and 3D modules at two extremities. We use the cluster length distributions in 3D sensor modules of the IBL to determine the number of primary charged particles per event and suppress backgrounds. This Pixel Cluster Counting ( PCC ) algorithm provides a bunch-by-bunch luminosity measurement. An accurate luminosity measurement is a key component for precision measurements at the Large Hadron Collider and one of the largest uncertainties on the luminosity determination in ATLAS arises from the long-term stability of the measurement technique. The comparison of the PCC algorithm with other existing algorithms provides key insights in assessing and reducing such uncertainty.

  11. Development of 3D-DDTC pixel detectors for the ATLAS upgrade

    CERN Document Server

    Betta, G -F Dalla; Darbo, G; Gemme, C; La Rosa, A; Pernegger, H; Piemonte, C; Povoli, M; Ronchin, S; Zoboli, A; Zorzi, N

    2011-01-01

    We report on the development of n-on-p, 3D Double-Side Double Type Column (3D-DDTC) pixel detectors fabricated at FBK-irst (Trento, Italy) and oriented to the ATLAS upgrade. The considered fabrication technology is simpler than that required for full 3D detectors with active edge, but the detector efficiency and radiation hardness critically depend on the columnar electrode overlap and should be carefully evaluated. The first assemblies of these sensors (featuring 2, 3, or 4 columns per pixel) with the ATLAS FEI3 read-out chip have been tested in laboratory. Selected results from the electrical and functional characterization with radioactive sources are here discussed.

  12. Operational Experience with and Performance of the ATLAS Pixel Detector at the Large Hadron Collider

    CERN Document Server

    Grummer, Aidan; The ATLAS collaboration

    2018-01-01

    The operational experience and requirements to ensure optimum data quality and data taking efficiency with the 4-layer ATLAS Pixel Detector are discussed. The detector has undergone significant hardware and software upgrades to meet the challenges imposed by the fact that the Large Hadron Collider is exceeding expectations for instantaneous luminosity by more than a factor of two (more than $2 \\times 10^{34}$ cm$^{-2}$ s$^{-1}$). Emphasizing radiation damage effects, the key status and performance metrics are described.

  13. Status of the ATLAS Pixel Detector at the LHC and its performance after three years of operation

    CERN Document Server

    Andreazza, A; The ATLAS collaboration

    2012-01-01

    The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus vital for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. In this talk, results from the successful operation of the Pixel Detector at the LHC and its status after three years of operation will be presented, including monitoring, calibration procedures, timing optimization and detector performance. The detector performance is excellent: ~96 % of the pixels are operational, noise occupancy and hit ...

  14. Development of n-in-p pixel modules for the ATLAS upgrade at HL-LHC

    Science.gov (United States)

    Macchiolo, A.; Nisius, R.; Savic, N.; Terzo, S.

    2016-09-01

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 μm thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of 14 ×1015 neq /cm2 . The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50×50 and 25×100 μm2) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region after irradiation. For this purpose the performance of different layouts have been compared in FE-I4 compatible sensors at various fluence levels by using beam test data. Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50×50 μm2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angle (80°) with respect to the short pixel direction. Results on cluster shapes, charge collection and hit efficiency will be shown.

  15. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  16. Front-end electronics for multichannel semiconductor detector systems

    CERN Document Server

    Grybos, P

    2010-01-01

    Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

  17. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  18. High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

    Science.gov (United States)

    Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

    2016-07-01

    Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

  19. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  20. Progress with the SNS front-end systems

    International Nuclear Information System (INIS)

    Keller, R.; Abraham, W.; Ayers, J.J.; Cheng, D.W.; Cull, P.; DiGennaro, R.; Doolittle, L.; Gough, R.A.; Greer, J.B.; Hoff, M.D.; Leung, K.N.; Lewis, S.; Lionberger, C.; MacGill, R.; Minamihara, Y.; Monroy, M.; Oshatz, D.; Pruyn, J.; Ratti, A.; Reijonen, J.; Schenkel, T.; Staples, J.W.; Syversrud, D.; Thomae, R.; Virostek, S.; Yourd, R.

    2001-01-01

    The Front-End Systems (FES) of the Spallation Neutron Source (SNS) project have been described in detail elsewhere [1]. They comprise an rf-driven H - ion source, electrostatic LEBT, four-vane RFQ, and an elaborate MEBT. These systems are planned to be delivered to the SNS facility in Oak Ridge in June 2002. This paper discusses the latest design features, the status of development work, component fabrication and procurements, and experimental results with the first commissioned beamline elements

  1. An analog integrated front-end amplifier for neural applications

    OpenAIRE

    Zhou, Zhijun; Warr, Paul

    2017-01-01

    The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated circuit form, alongside signal leakage into the input bias network. Significantly, this loop t...

  2. Front-end data processing the SLD data acquisition system

    International Nuclear Information System (INIS)

    Nielsen, B.S.

    1986-07-01

    The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

  3. A Full Front End Chain for Drift Chambers

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Panareo, M. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Primiceri, P. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Tassielli, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Fermilab, Batavia, Illinois (United States); Università Marconi, Roma (Italy)

    2014-03-01

    We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift tube and represents the outcome of balancing between efficiency and high speed performance.

  4. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  5. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2 at the LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00084948; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130 nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented using collision data.

  6. The Upgraded Pixel Detector of the ATLAS Experiment for Run-2

    CERN Document Server

    Ferrere, Didier; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  7. The upgraded Pixel Detector of the ATLAS experiment for Run-2 at the Large Hadron Collider

    CERN Document Server

    Giordani, MarioPaolo; The ATLAS collaboration

    2016-01-01

    Run-2 of the LHC is providing new challenges to track and vertex reconstruction with higher energies, denser jets and higher rates. Therefore the ATLAS experiment has constructed the first 4-layer Pixel detector in HEP, installing a new Pixel layer, also called Insertable B-Layer (IBL). IBL is a fourth layer of pixel detectors, and has been installed in May 2014 at a radius of 3.3 cm between the existing Pixel Detector and a new smaller radius beam-pipe. The new detector, built to cope with high radiation and expected occupancy, is the first large scale application of 3D detectors and CMOS 130nm technology. In addition the Pixel detector was refurbished with a new service quarter panel to recover about 3% of defective modules lost during run-1 and a new optical readout system to readout the data at higher speed while reducing the occupancy when running with increased luminosity. The commissioning and performance of the 4-layer Pixel Detector, in particular the IBL, will be presented, using collision data.

  8. Redesigned front end for the upgrade at CHESS

    International Nuclear Information System (INIS)

    Headrick, R.L.; Smolenski, K.W.

    1996-01-01

    We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

  9. The control system for the CMS tracker front-end

    CERN Document Server

    Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

    2002-01-01

    The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

  10. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  11. Upgrade of the BOC for the ATLAS Pixel Insertable B-Layer

    CERN Document Server

    Dopke, J; Heima, T; Kugel, A; Mattig, P; Schroer, N; Zeitnitz, C

    2009-01-01

    The phase 1 upgrade of the ATLAS [1] pixel detector will be done by inserting a fourth pixel layer together with a new beampipe into the recent three layer detector. This new detector, the Insertable B-Layer (IBL) should be integrated into the recent pixel system with as few changes in services as possible, but deliver some advantages over the recent system. One of those advantages will be a new data transmission link from the detector modules to the off-detector electronics, requiring a re-design of the electro-optical converters on the off-detector side. First ideas of how to implement those, together with some ideas to reduce cost by increasing the systems throughput are discussed.

  12. Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Bomben, M., E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Bagolini, A.; Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, L. [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, Pisa (Italy); INFN Sez. di Pisa, Pisa (Italy); Chauveau, J. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, G. [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

    2013-12-01

    In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown.

  13. Novel silicon n-on-p edgeless planar pixel sensors for the ATLAS upgrade

    International Nuclear Information System (INIS)

    Bomben, M.; Bagolini, A.; Boscardin, M.; Bosisio, L.; Calderini, G.; Chauveau, J.; Giacomini, G.; La Rosa, A.; Marchiori, G.; Zorzi, N.

    2013-01-01

    In view of the LHC upgrade phases towards HL-LHC, the ATLAS experiment plans to upgrade the inner detector with an all-silicon system. The n-on-p silicon technology is a promising candidate for the pixel upgrade thanks to its radiation hardness and cost effectiveness. The edgeless technology would allow for enlarging the area instrumented with pixel detectors. We report on the development of novel n-on-p edgeless planar pixel sensors fabricated at FBK (Trento, Italy), making use of the active edge concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology and fabrication process, we present device simulations (pre- and post-irradiation) performed for different sensor configurations. First preliminary results obtained with the test-structures of the production are shown

  14. Robustness of the Artificial Neural Networks Used for Clustering in the ATLAS Pixel Detector

    CERN Document Server

    The ATLAS collaboration

    2015-01-01

    A study of the robustness of the ATLAS pixel neural network clustering algorithm is presented. The sensitivity to variations to its input is evaluated. These variations are motivated by potential discrepancies between data and simulation due to uncertainties in the modelling of pixel clusters in simulation, as well as uncertainties from the detector calibration. Within reasonable variation magnitudes, the neural networks prove to be robust to most variations. The neural network used to identify pixel clusters created by multiple charged particles, is most sensitive to variations affecting the total amount of charge collected in the cluster. Modifying the read-out threshold has the biggest effect on the clustering's ability to estimate the position of the particle's intersection with the detector.

  15. The Layer 1 / Layer 2 readout upgrade for the ATLAS Pixel Detector

    CERN Document Server

    Mullier, Geoffrey; The ATLAS collaboration

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the Large Hadron Collider (LHC). The increase of instantaneous luminosity foreseen during the LHC Run 2, will lead to an increased detector occupancy that is expected to saturate the readout links of the outermost layers of the pixel detector: Layers 1 and 2. To ensure a smooth data taking under such conditions, the read out system of the recently installed fourth innermost pixel layer, the Insertable B-Layer, was modified to accomodate the needs of the older detector. The Layer 2 upgrade installation took place during the 2015 winter shutdown, with the Layer 1 installation scheduled for 2016. A report of the successful installation, together with the design of novel dedicated optical to electrical converters and the software and firmware updates will be presented.

  16. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    CERN Document Server

    Rimoldi, Marco; The ATLAS collaboration

    2017-01-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detector based on CMOS pixel techology. Such detectors provide charge collection, analog and digital amplification in the same silicon bulk. The radiation hardness is obtained with multiple nested wells that have embedded the CMOS electronics with sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC. A number of alternative solutions have been explored and characterised, and are presented in this document.

  17. Design of readout drivers for ATLAS pixel detectors using field programmable gate arrays

    CERN Document Server

    Sivasubramaniyan, Sriram

    Microstrip detectors are an integral patt of high energy physics research . Special protocols are used to transmit the data from these detectors . To readout the data from such detectors specialized instrumentation have to be designed . To achieve this task, creative and innovative high speed algorithms were designed simulated and implemented in Field Programmable gate arrays, using CAD/CAE tools. The simulation results indicated that these algorithms would be able to perform all the required tasks quickly and efficiently. This thesis describes the design of data acquisition system called the Readout Drivers (ROD) . It focuses on the ROD data path for ATLAS Pixel detectors. The data path will be an integrated part of Readout Drivers setup to decode the data from the silicon micro strip detectors and pixel detectors. This research also includes the design of Readout Driver controller. This Module is used to control the operation of the ROD. This module is responsible for the operation of the Pixel decoders bas...

  18. Radiationhard components for the control system of a future ATLAS pixel detector

    International Nuclear Information System (INIS)

    Becker, K; Boek, J; Kersten, S; Kind, P; Maettig, P; Puellen, L; Zeitnitz, C

    2011-01-01

    The upgrade of the ATLAS experiment for the High Luminosity LHC (HL-LHC) will include a new pixel detector. A completely new detector control system (DCS) for this pixel detector will be required in order to cope with the substantial increase in radiation at the HL-LHC. The DCS has to have a very high reliability and all components installed within the detector volume have to be radiationhard. This will ensure a safe operation of the pixel detector and the experiment. A further design constraint is the minimization of the used material and cables in order to limit the impact on the tracking performance to a minimum. To meet these requirements we propose a DCS network which consists of a DCS chip and a DCS controller. In the following we present the development of the first prototypes for the DCS chip and the DCS controller with a special focus on the communication interface, radiation hardness and robustness against single event upsets.

  19. Optical readout in a multi-module system test for the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Flick, Tobias; Becks, Karl-Heinz; Gerlach, Peter; Kersten, Susanne; Maettig, Peter; Nderitu Kirichu, Simon; Reeves, Kendall; Richter, Jennifer; Schultes, Joachim

    2006-01-01

    The innermost part of the ATLAS experiment at the LHC, CERN, will be a pixel detector, which is presently under construction. The command messages and the readout data of the detector are transmitted over an optical data path. The readout chain consists of many components which are produced at several locations around the world, and must work together in the pixel detector. To verify that these parts are working together as expected a system test has been built up. It consists of detector modules, optoboards, optical fibres, Back of Crate cards, Readout Drivers, and control computers. In this paper, the system test setup and the operation of the readout chain are described. Also, some results of tests using the final pixel detector readout chain are given

  20. The FE-I4 Pixel Readout Chip and the IBL Module

    Energy Technology Data Exchange (ETDEWEB)

    Barbero, Marlon; Arutinov, David; Backhaus, Malte; Fang, Xiao-Chao; Gonella, Laura; Hemperek, Tomasz; Karagounis, Michael; Hans, Kruger; Kruth, Andre; Wermes, Norbert; /Bonn U.; Breugnon, Patrick; Fougeron, Denis; Gensolen, Fabrice; Menouni, Mohsine; Rozanov, Alexander; /Marseille, CPPM; Beccherle, Roberto; Darbo, Giovanni; /INFN, Genoa; Caminada, Lea; Dube, Sourabh; Fleury, Julien; Gnani, Dario; /LBL, Berkeley /NIKHEF, Amsterdam /Gottingen U. /SLAC

    2012-05-01

    FE-I4 is the new ATLAS pixel readout chip for the upgraded ATLAS pixel detector. Designed in a CMOS 130 nm feature size process, the IC is able to withstand higher radiation levels compared to the present generation of ATLAS pixel Front-End FE-I3, and can also cope with higher hit rate. It is thus suitable for intermediate radii pixel detector layers in the High Luminosity LHC environment, but also for the inserted layer at 3.3 cm known as the 'Insertable B-Layer' project (IBL), at a shorter timescale. In this paper, an introduction to the FE-I4 will be given, focusing on test results from the first full size FE-I4A prototype which has been available since fall 2010. The IBL project will be introduced, with particular emphasis on the FE-I4-based module concept.

  1. Development of n-in-p pixel modules for the ATLAS Upgrade at HL-LHC

    CERN Document Server

    Macchiolo, Anna; Savic, Natascha; Terzo, Stefano

    2016-09-21

    Thin planar pixel modules are promising candidates to instrument the inner layers of the new ATLAS pixel detector for HL-LHC, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. 100-200 $\\mu$m thick sensors, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests at the CERN-SPS and DESY. The results of these measurements are reported for devices before and after irradiation up to a fluence of $14\\times10^{15}$ n$_{eq}$/cm$^2$. The charge collection and tracking efficiency of the different sensor thicknesses are compared. The outlook for future planar pixel sensor production is discussed, with a focus on sensor design with the pixel pitches (50x50 and 25x100 $\\mu$m$^2$) foreseen for the RD53 Collaboration read-out chip in 65 nm CMOS technology. An optimization of the biasing structures in the pixel cells is required to avoid the hit efficiency loss presently observed in the punch-through region...

  2. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Gallrapp, Christian

    2015-07-01

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

  3. Studies on irradiated pixel detectors for the ATLAS IBL and HL-LHC upgrade

    International Nuclear Information System (INIS)

    Gallrapp, Christian

    2015-01-01

    The constant demand for higher luminosity in high energy physics is the reason for the continuous effort to adapt the accelerators and the experiments. The upgrade program for the experiments and the accelerators at CERN already includes several expansion stages of the Large Hadron Collider (LHC) which will increase the luminosity and the energy of the accelerator. Simultaneously the LHC experiments prepare the individual sub-detectors for the increasing demands in the coming years. Especially the tracking detectors have to cope with fluence levels unprecedented for high energy physics experiments. Correspondingly to the fluence increases the impact of the radiation damage which reduces the life time of the detectors by decreasing the detector performance and efficiency. To cope with this effect new and more radiation hard detector concepts become necessary to extend the life time. This work concentrates on the impact of radiation damage on the pixel sensor technologies to be used in the next upgrade of the ATLAS Pixel Detector as well as for applications in the ATLAS Experiment at HL-LHC conditions. The sensors considered in this work include various designs based on silicon and diamond as sensor material. The investigated designs include a planar silicon pixel design currently used in the ATLAS Experiment as well as a 3D pixel design which uses electrodes penetrating the entire sensor material. The diamond designs implement electrodes similar to the design used by the planar technology with diamond sensors made out of single- and poly-crystalline material. To investigate the sensor properties characterization tests are performed before and after irradiation with protons or neutrons. The measurements are used to determine the interaction between the read-out electronics and the sensors to ensure the signal transfer after irradiation. Further tests focus on the sensor performance itself which includes the analysis of the leakage current behavior and the charge

  4. Spectroscopic measurements with the ATLAS FE-I4 pixel readout chip

    Energy Technology Data Exchange (ETDEWEB)

    Pohl, David-Leon; Janssen, Jens; Hemperek, Tomasz; Huegging, Fabian; Wermes, Norbert [Physikalisches Institut der Univeristaet Bonn (Germany)

    2015-07-01

    The ATLAS FE-I4 pixel readout chip is a large (2 x 2 cm{sup 2}) state of the art ASIC used in high energy physics experiments as well as for research and development purposes. While the FE-I4 is optimized for high hit rates it provides very limited charge resolution. Therefore two methods were developed to obtain high resolution single pixel charge spectra with the ATLAS FE-I4. The first method relies on the ability to change the detection threshold in small steps while counting hits from a particle source and has a resolution limited by electronic noise only. The other method uses a FPGA based time-to-digital-converter to digitize the analog charge signal with high precision. The feasibility, performance and challenges of these methods are discussed. First results of sensor characterizations from radioactive sources and test beams with the ATLAS FE-I4 in view of the charge collection efficiency after irradiation are presented.

  5. High bandwidth pixel detector modules for the ATLAS Insertable B-Layer

    International Nuclear Information System (INIS)

    Backhaus, Malte

    2014-01-01

    The investigation of the nature of the recently discovered electro-weak symmetry breaking mechanism of the standard model of particle physics as well as the search for physics beyond the standard model with the LHC require to collect even more data. To achieve this goal, the luminosity of the LHC will be increased in two steps. The increased luminosity results in serious challenges for the inner tracking systems of the experiments at the LHC. The ATLAS pixel detector will also be upgraded in a two stage program. During the shutdown in 2013 and 2014 a fourth hybrid pixel detector layer, the socalled Insertable B-Layer (IBL) is inserted inside the existing pixel detector. This thesis focuses on the characterization, performance measurement, and production quality assurance of the central sensitive elements of the IBL, the modules. This includes a full characterization of the readout chip (FE-I4) and of the assembled modules. A completely new inner tracking system is mandatory in ATLAS after the second luminosity increase in the shutdown of 2022 and 2023. The final chapter of this thesis introduces a new module concept that uses an industrial high voltage CMOS technology as sensor layer, which is capacitively coupled to the FE-I4 readout chip.

  6. SLID-ICV Vertical Integration Technology for the ATLAS Pixel Upgrades

    CERN Document Server

    INSPIRE-00219560; Moser, H.G.; Nisius, R.; Richter, R.H.; Weigell, P.

    We present the results of the characterization of pixel modules composed of 75 μm thick n-in-p sensors and ATLAS FE-I3 chips, interconnected with the SLID (Solid Liquid Inter-Diffusion) technology. This technique, developed at Fraunhofer-EMFT, is explored as an alternative to the bump-bonding process. These modules have been designed to demonstrate the feasibility of a very compact detector to be employed in the future ATLAS pixel upgrades, making use of vertical integration technologies. This module concept also envisages Inter-Chip-Vias (ICV) to extract the signals from the backside of the chips, thereby achieving a higher fraction of active area with respect to the present pixel module design. In the case of the demonstrator module, ICVs are etched over the original wire bonding pads of the FE-I3 chip. In the modules with ICVs the FE-I3 chips will be thinned down to 50 um. The status of the ICV preparation is presented.

  7. CODA : Compact front-end analog ASIC for silicon detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

  8. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  9. Instrument front-ends at Fermilab during Run II

    International Nuclear Information System (INIS)

    Meyer, T; Slimmer, D; Voy, D

    2011-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  10. Instrument Front-Ends at Fermilab During Run II

    International Nuclear Information System (INIS)

    Meyer, Thomas; Slimmer, David; Voy, Duane

    2011-01-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  11. Instrument front-ends at Fermilab during Run II

    Science.gov (United States)

    Meyer, T.; Slimmer, D.; Voy, D.

    2011-11-01

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor. Work supported by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the United States Department of Energy.

  12. A multitasking, multisinked, multiprocessor data acquisition front end

    International Nuclear Information System (INIS)

    Fox, R.; Au, R.; Molen, A.V.

    1989-01-01

    The authors have developed a generalized data acquisition front end system which is based on MC68020 processors running a commercial real time kernel (rhoSOS), and implemented primarily in a high level language (C). This system has been attached to the back end on-line computing system at NSCL via our high performance ETHERNET protocol. Data may be simultaneously sent to any number of back end systems. Fixed fraction sampling along links to back end computing is also supported. A nonprocedural program generator simplifies the development of experiment specific code

  13. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  14. New RPC front-end electronics for hades

    CERN Document Server

    Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

    2007-01-01

    Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

  15. Front-end electronics for the CMS preshower detector

    CERN Document Server

    Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

    2002-01-01

    The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

  16. Performance of Front-End Readout System for PHENIX RICH

    International Nuclear Information System (INIS)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-01-01

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

  17. AiGERM: A logic programming front end for GERM

    Science.gov (United States)

    Hashim, Safaa H.

    1990-01-01

    AiGerm (Artificially Intelligent Graphical Entity Relation Modeler) is a relational data base query and programming language front end for MCC (Mission Control Center)/STP's (Space Test Program) Germ (Graphical Entity Relational Modeling) system. It is intended as an add-on component of the Germ system to be used for navigating very large networks of information. It can also function as an expert system shell for prototyping knowledge-based systems. AiGerm provides an interface between the programming language and Germ.

  18. APPLICATION OF OBJECT ORIENTED PROGRAMMING TECHNIQUES IN FRONT END COMPUTERS

    International Nuclear Information System (INIS)

    SKELLY, J.F.

    1997-01-01

    The Front End Computer (FEC) environment imposes special demands on software, beyond real time performance and robustness. FEC software must manage a diverse inventory of devices with individualistic timing requirements and hardware interfaces. It must implement network services which export device access to the control system at large, interpreting a uniform network communications protocol into the specific control requirements of the individual devices. Object oriented languages provide programming techniques which neatly address these challenges, and also offer benefits in terms of maintainability and flexibility. Applications are discussed which exhibit the use of inheritance, multiple inheritance and inheritance trees, and polymorphism to address the needs of FEC software

  19. Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

    International Nuclear Information System (INIS)

    Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

  20. Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

    International Nuclear Information System (INIS)

    Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

    2010-01-01

    The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

  1. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Ceccucci, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Mazza, G.; Martoiu, S.; Morel, M.; Perktold, L.; Rivetti, A.; Tiuraniemi, S.

    2011-06-01

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16 cm active area made of an assembly of 10 readout ASICs bump bonded to a 200 μm thick pixel silicon sensor, comprising 18000 pixels of 300 μm×300 μm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5 Mhit s mm together with an extreme time resolution of 100 ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4 ns, with a planar silicon sensor operating up to 300 V over depletion. Moreover, the radiation level is severe, 2×10 1 MeV n cm per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130 nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  2. A neural network clustering algorithm for the ATLAS silicon pixel detector

    CERN Document Server

    Aad, Georges; Abdallah, Jalal; Abdel Khalek, Samah; Abdinov, Ovsat; Aben, Rosemarie; Abi, Babak; Abolins, Maris; AbouZeid, Ossama; Abramowicz, Halina; Abreu, Henso; Abreu, Ricardo; Abulaiti, Yiming; Acharya, Bobby Samir; Adamczyk, Leszek; Adams, David; Adelman, Jahred; Adomeit, Stefanie; Adye, Tim; Agatonovic-Jovin, Tatjana; Aguilar-Saavedra, Juan Antonio; Agustoni, Marco; Ahlen, Steven; Ahmadov, Faig; Aielli, Giulio; Akerstedt, Henrik; Åkesson, Torsten Paul Ake; Akimoto, Ginga; Akimov, Andrei; Alberghi, Gian Luigi; Albert, Justin; Albrand, Solveig; Alconada Verzini, Maria Josefina; Aleksa, Martin; Aleksandrov, Igor; Alexa, Calin; Alexander, Gideon; Alexandre, Gauthier; Alexopoulos, Theodoros; Alhroob, Muhammad; Alimonti, Gianluca; Alio, Lion; Alison, John; Allbrooke, Benedict; Allison, Lee John; Allport, Phillip; Almond, John; Aloisio, Alberto; Alonso, Alejandro; Alonso, Francisco; Alpigiani, Cristiano; Altheimer, Andrew David; Alvarez Gonzalez, Barbara; Alviggi, Mariagrazia; Amako, Katsuya; Amaral Coutinho, Yara; Amelung, Christoph; Amidei, Dante; Amor Dos Santos, Susana Patricia; Amorim, Antonio; Amoroso, Simone; Amram, Nir; Amundsen, Glenn; Anastopoulos, Christos; Ancu, Lucian Stefan; Andari, Nansi; Andeen, Timothy; Anders, Christoph Falk; Anders, Gabriel; Anderson, Kelby; Andreazza, Attilio; Andrei, George Victor; Anduaga, Xabier; Angelidakis, Stylianos; Angelozzi, Ivan; Anger, Philipp; Angerami, Aaron; Anghinolfi, Francis; Anisenkov, Alexey; Anjos, Nuno; Annovi, Alberto; Antonaki, Ariadni; Antonelli, Mario; Antonov, Alexey; Antos, Jaroslav; Anulli, Fabio; Aoki, Masato; Aperio Bella, Ludovica; Apolle, Rudi; Arabidze, Giorgi; Aracena, Ignacio; Arai, Yasuo; Araque, Juan Pedro; Arce, Ayana; Arguin, Jean-Francois; Argyropoulos, Spyridon; Arik, Metin; Armbruster, Aaron James; Arnaez, Olivier; Arnal, Vanessa; Arnold, Hannah; Arratia, Miguel; Arslan, Ozan; Artamonov, Andrei; Artoni, Giacomo; Asai, Shoji; Asbah, Nedaa; Ashkenazi, Adi; Åsman, Barbro; Asquith, Lily; Assamagan, Ketevi; Astalos, Robert; Atkinson, Markus; Atlay, Naim Bora; Auerbach, Benjamin; Augsten, Kamil; Aurousseau, Mathieu; Avolio, Giuseppe; Azuelos, Georges; Azuma, Yuya; Baak, Max; Baas, Alessandra; Bacci, Cesare; Bachacou, Henri; Bachas, Konstantinos; Backes, Moritz; Backhaus, Malte; Backus Mayes, John; Badescu, Elisabeta; Bagiacchi, Paolo; Bagnaia, Paolo; Bai, Yu; Bain, Travis; Baines, John; Baker, Oliver Keith; Balek, Petr; Balli, Fabrice; Banas, Elzbieta; Banerjee, Swagato; Bannoura, Arwa A E; Bansal, Vikas; Bansil, Hardeep Singh; Barak, Liron; Baranov, Sergei; Barberio, Elisabetta Luigia; Barberis, Dario; Barbero, Marlon; Barillari, Teresa; Barisonzi, Marcello; Barklow, Timothy; Barlow, Nick; Barnett, Bruce; Barnett, Michael; Barnovska, Zuzana; Baroncelli, Antonio; Barone, Gaetano; Barr, Alan; Barreiro, Fernando; Barreiro Guimarães da Costa, João; Bartoldus, Rainer; Barton, Adam Edward; Bartos, Pavol; Bartsch, Valeria; Bassalat, Ahmed; Basye, Austin; Bates, Richard; Batkova, Lucia; Batley, Richard; Battaglia, Marco; Battistin, Michele; Bauer, Florian; Bawa, Harinder Singh; Beau, Tristan; Beauchemin, Pierre-Hugues; Beccherle, Roberto; Bechtle, Philip; Beck, Hans Peter; Becker, Anne Kathrin; Becker, Sebastian; Beckingham, Matthew; Becot, Cyril; Beddall, Andrew; Beddall, Ayda; Bedikian, Sourpouhi; Bednyakov, Vadim; Bee, Christopher; Beemster, Lars; Beermann, Thomas; Begel, Michael; Behr, Katharina; Belanger-Champagne, Camille; Bell, Paul; Bell, William; Bella, Gideon; Bellagamba, Lorenzo; Bellerive, Alain; Bellomo, Massimiliano; Belotskiy, Konstantin; Beltramello, Olga; Benary, Odette; Benchekroun, Driss; Bendtz, Katarina; Benekos, Nektarios; Benhammou, Yan; Benhar Noccioli, Eleonora; Benitez Garcia, Jorge-Armando; Benjamin, Douglas; Bensinger, James; Benslama, Kamal; Bentvelsen, Stan; Berge, David; Bergeaas Kuutmann, Elin; Berger, Nicolas; Berghaus, Frank; Beringer, Jürg; Bernard, Clare; Bernat, Pauline; Bernius, Catrin; Bernlochner, Florian Urs; Berry, Tracey; Berta, Peter; Bertella, Claudia; Bertoli, Gabriele; Bertolucci, Federico; Bertsche, David; Besana, Maria Ilaria; Besjes, Geert-Jan; Bessidskaia, Olga; Bessner, Martin Florian; Besson, Nathalie; Betancourt, Christopher; Bethke, Siegfried; Bhimji, Wahid; Bianchi, Riccardo-Maria; Bianchini, Louis; Bianco, Michele; Biebel, Otmar; Bieniek, Stephen Paul; Bierwagen, Katharina; Biesiada, Jed; Biglietti, Michela; Bilbao De Mendizabal, Javier; Bilokon, Halina; Bindi, Marcello; Binet, Sebastien; Bingul, Ahmet; Bini, Cesare; Black, Curtis; Black, James; Black, Kevin; Blackburn, Daniel; Blair, Robert; Blanchard, Jean-Baptiste; Blazek, Tomas; Bloch, Ingo; Blocker, Craig; Blum, Walter; Blumenschein, Ulrike; Bobbink, Gerjan; Bobrovnikov, Victor; Bocchetta, Simona Serena; Bocci, Andrea; Bock, Christopher; Boddy, Christopher Richard; Boehler, Michael; Boek, Thorsten Tobias; Bogaerts, Joannes Andreas; Bogdanchikov, Alexander; Bogouch, Andrei; Bohm, Christian; Bohm, Jan; Boisvert, Veronique; Bold, Tomasz; Boldea, Venera; Boldyrev, Alexey; Bomben, Marco; Bona, Marcella; Boonekamp, Maarten; Borisov, Anatoly; Borissov, Guennadi; Borri, Marcello; Borroni, Sara; Bortfeldt, Jonathan; Bortolotto, Valerio; Bos, Kors; Boscherini, Davide; Bosman, Martine; Boterenbrood, Hendrik; Boudreau, Joseph; Bouffard, Julian; Bouhova-Thacker, Evelina Vassileva; Boumediene, Djamel Eddine; Bourdarios, Claire; Bousson, Nicolas; Boutouil, Sara; Boveia, Antonio; Boyd, James; Boyko, Igor; Bracinik, Juraj; Brandt, Andrew; Brandt, Gerhard; Brandt, Oleg; Bratzler, Uwe; Brau, Benjamin; Brau, James; Braun, Helmut; Brazzale, Simone Federico; Brelier, Bertrand; Brendlinger, Kurt; Brennan, Amelia Jean; Brenner, Richard; Bressler, Shikma; Bristow, Kieran; Bristow, Timothy Michael; Britton, Dave; Brochu, Frederic; Brock, Ian; Brock, Raymond; Bromberg, Carl; Bronner, Johanna; Brooijmans, Gustaaf; Brooks, Timothy; Brooks, William; Brosamer, Jacquelyn; Brost, Elizabeth; Brown, Jonathan; Bruckman de Renstrom, Pawel; Bruncko, Dusan; Bruneliere, Renaud; Brunet, Sylvie; Bruni, Alessia; Bruni, Graziano; Bruschi, Marco; Bryngemark, Lene; Buanes, Trygve; Buat, Quentin; Bucci, Francesca; Buchholz, Peter; Buckingham, Ryan; Buckley, Andrew; Buda, Stelian Ioan; Budagov, Ioulian; Buehrer, Felix; Bugge, Lars; Bugge, Magnar Kopangen; Bulekov, Oleg; Bundock, Aaron Colin; Burckhart, Helfried; Burdin, Sergey; Burghgrave, Blake; Burke, Stephen; Burmeister, Ingo; Busato, Emmanuel; Büscher, Daniel; Büscher, Volker; Bussey, Peter; Buszello, Claus-Peter; Butler, Bart; Butler, John; Butt, Aatif Imtiaz; Buttar, Craig; Butterworth, Jonathan; Butti, Pierfrancesco; Buttinger, William; Buzatu, Adrian; Byszewski, Marcin; Cabrera Urbán, Susana; Caforio, Davide; Cakir, Orhan; Calafiura, Paolo; Calandri, Alessandro; Calderini, Giovanni; Calfayan, Philippe; Calkins, Robert; Caloba, Luiz; Calvet, David; Calvet, Samuel; Camacho Toro, Reina; Camarda, Stefano; Cameron, David; Caminada, Lea Michaela; Caminal Armadans, Roger; Campana, Simone; Campanelli, Mario; Campoverde, Angel; Canale, Vincenzo; Canepa, Anadi; Cano Bret, Marc; Cantero, Josu; Cantrill, Robert; Cao, Tingting; Capeans Garrido, Maria Del Mar; Caprini, Irinel; Caprini, Mihai; Capua, Marcella; Caputo, Regina; Cardarelli, Roberto; Carli, Tancredi; Carlino, Gianpaolo; Carminati, Leonardo; Caron, Sascha; Carquin, Edson; Carrillo-Montoya, German D; Carter, Janet; Carvalho, João; Casadei, Diego; Casado, Maria Pilar; Casolino, Mirkoantonio; Castaneda-Miranda, Elizabeth; Castelli, Angelantonio; Castillo Gimenez, Victoria; Castro, Nuno Filipe; Catastini, Pierluigi; Catinaccio, Andrea; Catmore, James; Cattai, Ariella; Cattani, Giordano; Caughron, Seth; Cavaliere, Viviana; Cavalli, Donatella; Cavalli-Sforza, Matteo; Cavasinni, Vincenzo; Ceradini, Filippo; Cerio, Benjamin; Cerny, Karel; Santiago Cerqueira, Augusto; Cerri, Alessandro; Cerrito, Lucio; Cerutti, Fabio; Cerv, Matevz; Cervelli, Alberto; Cetin, Serkant Ali; Chafaq, Aziz; Chakraborty, Dhiman; Chalupkova, Ina; Chang, Philip; Chapleau, Bertrand; Chapman, John Derek; Charfeddine, Driss; Charlton, Dave; Chau, Chav Chhiv; Chavez Barajas, Carlos Alberto; Cheatham, Susan; Chegwidden, Andrew; Chekanov, Sergei; Chekulaev, Sergey; Chelkov, Gueorgui; Chelstowska, Magda Anna; Chen, Chunhui; Chen, Hucheng; Chen, Karen; Chen, Liming; Chen, Shenjian; Chen, Xin; Chen, Yujiao; Cheng, Hok Chuen; Cheng, Yangyang; Cheplakov, Alexander; Cherkaoui El Moursli, Rajaa; Chernyatin, Valeriy; Cheu, Elliott; Chevalier, Laurent; Chiarella, Vitaliano; Chiefari, Giovanni; Childers, John Taylor; Chilingarov, Alexandre; Chiodini, Gabriele; Chisholm, Andrew; Chislett, Rebecca Thalatta; Chitan, Adrian; Chizhov, Mihail; Chouridou, Sofia; Chow, Bonnie Kar Bo; Chromek-Burckhart, Doris; Chu, Ming-Lee; Chudoba, Jiri; Chwastowski, Janusz; Chytka, Ladislav; Ciapetti, Guido; Ciftci, Abbas Kenan; Ciftci, Rena; Cinca, Diane; Cindro, Vladimir; Ciocio, Alessandra; Cirkovic, Predrag; Citron, Zvi Hirsh; Citterio, Mauro; Ciubancan, Mihai; Clark, Allan G; Clark, Philip James; Clarke, Robert; Cleland, Bill; Clemens, Jean-Claude; Clement, Christophe; Coadou, Yann; Cobal, Marina; Coccaro, Andrea; Cochran, James H; Coffey, Laurel; Cogan, Joshua Godfrey; Coggeshall, James; Cole, Brian; Cole, Stephen; Colijn, Auke-Pieter; Collot, Johann; Colombo, Tommaso; Colon, German; Compostella, Gabriele; Conde Muiño, Patricia; Coniavitis, Elias; Conidi, Maria Chiara; Connell, Simon Henry; Connelly, Ian; Consonni, Sofia Maria; Consorti, Valerio; Constantinescu, Serban; Conta, Claudio; Conti, Geraldine; Conventi, Francesco; Cooke, Mark; Cooper, Ben; Cooper-Sarkar, Amanda; Cooper-Smith, Neil; Copic, Katherine; Cornelissen, Thijs; Corradi, Massimo; Corriveau, Francois; Corso-Radu, Alina; Cortes-Gonzalez, Arely; Cortiana, Giorgio; Costa, Giuseppe; Costa, María José; Costanzo, Davide; Côté, David; Cottin, Giovanna; Cowan, Glen; Cox, Brian; Cranmer, Kyle; Cree, Graham; Crépé-Renaudin, Sabine; Crescioli, Francesco; Cribbs, Wayne Allen; Crispin Ortuzar, Mireia; Cristinziani, Markus; Croft, Vince; Crosetti, Giovanni; Cuciuc, Constantin-Mihai; Cuhadar Donszelmann, Tulay; Cummings, Jane; Curatolo, Maria; Cuthbert, Cameron; Czirr, Hendrik; Czodrowski, Patrick; Czyczula, Zofia; D'Auria, Saverio; D'Onofrio, Monica; Da Cunha Sargedas De Sousa, Mario Jose; Da Via, Cinzia; Dabrowski, Wladyslaw; Dafinca, Alexandru; Dai, Tiesheng; Dale, Orjan; Dallaire, Frederick; Dallapiccola, Carlo; Dam, Mogens; Daniells, Andrew Christopher; Dano Hoffmann, Maria; Dao, Valerio; Darbo, Giovanni; Darmora, Smita; Dassoulas, James; Dattagupta, Aparajita; Davey, Will; David, Claire; Davidek, Tomas; Davies, Eleanor; Davies, Merlin; Davignon, Olivier; Davison, Adam; Davison, Peter; Davygora, Yuriy; Dawe, Edmund; Dawson, Ian; Daya-Ishmukhametova, Rozmin; De, Kaushik; de Asmundis, Riccardo; De Castro, Stefano; De Cecco, Sandro; De Groot, Nicolo; de Jong, Paul; De la Torre, Hector; De Lorenzi, Francesco; De Nooij, Lucie; De Pedis, Daniele; De Salvo, Alessandro; De Sanctis, Umberto; De Santo, Antonella; De Vivie De Regie, Jean-Baptiste; Dearnaley, William James; Debbe, Ramiro; Debenedetti, Chiara; Dechenaux, Benjamin; Dedovich, Dmitri; Deigaard, Ingrid; Del Peso, Jose; Del Prete, Tarcisio; Deliot, Frederic; Delitzsch, Chris Malena; Deliyergiyev, Maksym; Dell'Acqua, Andrea; Dell'Asta, Lidia; Dell'Orso, Mauro; Della Pietra, Massimo; della Volpe, Domenico; Delmastro, Marco; Delsart, Pierre-Antoine; Deluca, Carolina; Demers, Sarah; Demichev, Mikhail; Demilly, Aurelien; Denisov, Sergey; Derendarz, Dominik; Derkaoui, Jamal Eddine; Derue, Frederic; Dervan, Paul; Desch, Klaus Kurt; Deterre, Cecile; Deviveiros, Pier-Olivier; Dewhurst, Alastair; Dhaliwal, Saminder; Di Ciaccio, Anna; Di Ciaccio, Lucia; Di Domenico, Antonio; Di Donato, Camilla; Di Girolamo, Alessandro; Di Girolamo, Beniamino; Di Mattia, Alessandro; Di Micco, Biagio; Di Nardo, Roberto; Di Simone, Andrea; Di Sipio, Riccardo; Di Valentino, David; Dias, Flavia; Diaz, Marco Aurelio; Diehl, Edward; Dietrich, Janet; Dietzsch, Thorsten; Diglio, Sara; Dimitrievska, Aleksandra; Dingfelder, Jochen; Dionisi, Carlo; Dita, Petre; Dita, Sanda; Dittus, Fridolin; Djama, Fares; Djobava, Tamar; Barros do Vale, Maria Aline; Do Valle Wemans, André; Doan, Thi Kieu Oanh; Dobos, Daniel; Doglioni, Caterina; Doherty, Tom; Dohmae, Takeshi; Dolejsi, Jiri; Dolezal, Zdenek; Dolgoshein, Boris; Donadelli, Marisilvia; Donati, Simone; Dondero, Paolo; Donini, Julien; Dopke, Jens; Doria, Alessandra; Dova, Maria-Teresa; Doyle, Tony; Dris, Manolis; Dubbert, Jörg; Dube, Sourabh; Dubreuil, Emmanuelle; Duchovni, Ehud; Duckeck, Guenter; Ducu, Otilia Anamaria; Duda, Dominik; Dudarev, Alexey; Dudziak, Fanny; Duflot, Laurent; Duguid, Liam; Dührssen, Michael; Dunford, Monica; Duran Yildiz, Hatice; Düren, Michael; Durglishvili, Archil; Dwuznik, Michal; Dyndal, Mateusz; Ebke, Johannes; Edson, William; Edwards, Nicholas Charles; Ehrenfeld, Wolfgang; Eifert, Till; Eigen, Gerald; Einsweiler, Kevin; Ekelof, Tord; El Kacimi, Mohamed; Ellert, Mattias; Elles, Sabine; Ellinghaus, Frank; Ellis, Nicolas; Elmsheuser, Johannes; Elsing, Markus; Emeliyanov, Dmitry; Enari, Yuji; Endner, Oliver Chris; Endo, Masaki; Engelmann, Roderich; Erdmann, Johannes; Ereditato, Antonio; Eriksson, Daniel; Ernis, Gunar; Ernst, Jesse; Ernst, Michael; Ernwein, Jean; Errede, Deborah; Errede, Steven; Ertel, Eugen; Escalier, Marc; Esch, Hendrik; Escobar, Carlos; Esposito, Bellisario; Etienvre, Anne-Isabelle; Etzion, Erez; Evans, Hal; Ezhilov, Alexey; Fabbri, Laura; Facini, Gabriel; Fakhrutdinov, Rinat; Falciano, Speranza; Falla, Rebecca Jane; Faltova, Jana; Fang, Yaquan; Fanti, Marcello; Farbin, Amir; Farilla, Addolorata; Farooque, Trisha; Farrell, Steven; Farrington, Sinead; Farthouat, Philippe; Fassi, Farida; Fassnacht, Patrick; Fassouliotis, Dimitrios; Favareto, Andrea; Fayard, Louis; Federic, Pavol; Fedin, Oleg; Fedorko, Wojciech; Fehling-Kaschek, Mirjam; Feigl, Simon; Feligioni, Lorenzo; Feng, Cunfeng; Feng, Eric; Feng, Haolu; Fenyuk, Alexander; Fernandez Perez, Sonia; Ferrag, Samir; Ferrando, James; Ferrari, Arnaud; Ferrari, Pamela; Ferrari, Roberto; Ferreira de Lima, Danilo Enoque; Ferrer, Antonio; Ferrere, Didier; Ferretti, Claudio; Ferretto Parodi, Andrea; Fiascaris, Maria; Fiedler, Frank; Filipčič, Andrej; Filipuzzi, Marco; Filthaut, Frank; Fincke-Keeler, Margret; Finelli, Kevin Daniel; Fiolhais, Miguel; Fiorini, Luca; Firan, Ana; Fischer, Adam; Fischer, Julia; Fisher, Wade Cameron; Fitzgerald, Eric Andrew; Flechl, Martin; Fleck, Ivor; Fleischmann, Philipp; Fleischmann, Sebastian; Fletcher, Gareth Thomas; Fletcher, Gregory; Flick, Tobias; Floderus, Anders; Flores Castillo, Luis; Florez Bustos, Andres Carlos; Flowerdew, Michael; Formica, Andrea; Forti, Alessandra; Fortin, Dominique; Fournier, Daniel; Fox, Harald; Fracchia, Silvia; Francavilla, Paolo; Franchini, Matteo; Franchino, Silvia; Francis, David; Franklin, Melissa; Franz, Sebastien; Fraternali, Marco; French, Sky; Friedrich, Conrad; Friedrich, Felix; Froidevaux, Daniel; Frost, James; Fukunaga, Chikara; Fullana Torregrosa, Esteban; Fulsom, Bryan Gregory; Fuster, Juan; Gabaldon, Carolina; Gabizon, Ofir; Gabrielli, Alessandro; Gabrielli, Andrea; Gadatsch, Stefan; Gadomski, Szymon; Gagliardi, Guido; Gagnon, Pauline; Galea, Cristina; Galhardo, Bruno; Gallas, Elizabeth; Gallo, Valentina Santina; Gallop, Bruce; Gallus, Petr; Galster, Gorm Aske Gram Krohn; Gan, KK; Gandrajula, Reddy Pratap; Gao, Jun; Gao, Yongsheng; Garay Walls, Francisca; Garberson, Ford; García, Carmen; García Navarro, José Enrique; Garcia-Sciveres, Maurice; Gardner, Robert; Garelli, Nicoletta; Garonne, Vincent; Gatti, Claudio; Gaudio, Gabriella; Gaur, Bakul; Gauthier, Lea; Gauzzi, Paolo; Gavrilenko, Igor; Gay, Colin; Gaycken, Goetz; Gazis, Evangelos; Ge, Peng; Gecse, Zoltan; Gee, Norman; Geerts, Daniël Alphonsus Adrianus; Geich-Gimbel, Christoph; Gellerstedt, Karl; Gemme, Claudia; Gemmell, Alistair; Genest, Marie-Hélène; Gentile, Simonetta; George, Matthias; George, Simon; Gerbaudo, Davide; Gershon, Avi; Ghazlane, Hamid; Ghodbane, Nabil; Giacobbe, Benedetto; Giagu, Stefano; Giangiobbe, Vincent; Giannetti, Paola; Gianotti, Fabiola; Gibbard, Bruce; Gibson, Stephen; Gilchriese, Murdock; Gillam, Thomas; Gillberg, Dag; Gilles, Geoffrey; Gingrich, Douglas; Giokaris, Nikos; Giordani, MarioPaolo; Giordano, Raffaele; Giorgi, Filippo Maria; Giorgi, Francesco Michelangelo; Giraud, Pierre-Francois; Giugni, Danilo; Giuliani, Claudia; Giulini, Maddalena; Gjelsten, Børge Kile; Gkaitatzis, Stamatios; Gkialas, Ioannis; Gladilin, Leonid; Glasman, Claudia; Glatzer, Julian; Glaysher, Paul; Glazov, Alexandre; Glonti, George; Goblirsch-Kolb, Maximilian; Goddard, Jack Robert; Godfrey, Jennifer; Godlewski, Jan; Goeringer, Christian; Goldfarb, Steven; Golling, Tobias; Golubkov, Dmitry; Gomes, Agostinho; Gomez Fajardo, Luz Stella; Gonçalo, Ricardo; Goncalves Pinto Firmino Da Costa, Joao; Gonella, Laura; González de la Hoz, Santiago; Gonzalez Parra, Garoe; Gonzalez-Sevilla, Sergio; Goossens, Luc; Gorbounov, Petr Andreevich; Gordon, Howard; Gorelov, Igor; Gorini, Benedetto; Gorini, Edoardo; Gorišek, Andrej; Gornicki, Edward; Goshaw, Alfred; Gössling, Claus; Gostkin, Mikhail Ivanovitch; Gouighri, Mohamed; Goujdami, Driss; Goulette, Marc Phillippe; Goussiou, Anna; Goy, Corinne; Gozpinar, Serdar; Grabas, Herve Marie Xavier; Graber, Lars; Grabowska-Bold, Iwona; Grafström, Per; Grahn, Karl-Johan; Gramling, Johanna; Gramstad, Eirik; Grancagnolo, Sergio; Grassi, Valerio; Gratchev, Vadim; Gray, Heather; Graziani, Enrico; Grebenyuk, Oleg; Greenwood, Zeno Dixon; Gregersen, Kristian; Gregor, Ingrid-Maria; Grenier, Philippe; Griffiths, Justin; Grillo, Alexander; Grimm, Kathryn; Grinstein, Sebastian; Gris, Philippe Luc Yves; Grishkevich, Yaroslav; Grivaz, Jean-Francois; Grohs, Johannes Philipp; Grohsjean, Alexander; Gross, Eilam; Grosse-Knetter, Joern; Grossi, Giulio Cornelio; Groth-Jensen, Jacob; Grout, Zara Jane; Guan, Liang; Guescini, Francesco; Guest, Daniel; Gueta, Orel; Guicheney, Christophe; Guido, Elisa; Guillemin, Thibault; Guindon, Stefan; Gul, Umar; Gumpert, Christian; Gunther, Jaroslav; Guo, Jun; Gupta, Shaun; Gutierrez, Phillip; Gutierrez Ortiz, Nicolas Gilberto; Gutschow, Christian; Guttman, Nir; Guyot, Claude; Gwenlan, Claire; Gwilliam, Carl; Haas, Andy; Haber, Carl; Hadavand, Haleh Khani; Haddad, Nacim; Haefner, Petra; Hageböck, Stephan; Hajduk, Zbigniew; Hakobyan, Hrachya; Haleem, Mahsana; Hall, David; Halladjian, Garabed; Hamacher, Klaus; Hamal, Petr; Hamano, Kenji; Hamer, Matthias; Hamilton, Andrew; Hamilton, Samuel; Hamnett, Phillip George; Han, Liang; Hanagaki, Kazunori; Hanawa, Keita; Hance, Michael; Hanke, Paul; Hanna, Remie; Hansen, Jørgen Beck; Hansen, Jorn Dines; Hansen, Peter Henrik; Hara, Kazuhiko; Hard, Andrew; Harenberg, Torsten; Hariri, Faten; Harkusha, Siarhei; Harper, Devin; Harrington, Robert; Harris, Orin; Harrison, Paul Fraser; Hartjes, Fred; Hasegawa, Satoshi; Hasegawa, Yoji; Hasib, A; Hassani, Samira; Haug, Sigve; Hauschild, Michael; Hauser, Reiner; Havranek, Miroslav; Hawkes, Christopher; Hawkings, Richard John; Hawkins, Anthony David; Hayashi, Takayasu; Hayden, Daniel; Hays, Chris; Hayward, Helen; Haywood, Stephen; Head, Simon; Heck, Tobias; Hedberg, Vincent; Heelan, Louise; Heim, Sarah; Heim, Timon; Heinemann, Beate; Heinrich, Lukas; Hejbal, Jiri; Helary, Louis; Heller, Claudio; Heller, Matthieu; Hellman, Sten; Hellmich, Dennis; Helsens, Clement; Henderson, James; Henderson, Robert; Heng, Yang; Hengler, Christopher; Henrichs, Anna; Henriques Correia, Ana Maria; Henrot-Versille, Sophie; Hensel, Carsten; Herbert, Geoffrey Henry; Hernández Jiménez, Yesenia; Herrberg-Schubert, Ruth; Herten, Gregor; Hertenberger, Ralf; Hervas, Luis; Hesketh, Gavin Grant; Hessey, Nigel; Hickling, Robert; Higón-Rodriguez, Emilio; Hill, Ewan; Hill, John; Hiller, Karl Heinz; Hillert, Sonja; Hillier, Stephen; Hinchliffe, Ian; Hines, Elizabeth; Hirose, Minoru; Hirschbuehl, Dominic; Hobbs, John; Hod, Noam; Hodgkinson, Mark; Hodgson, Paul; Hoecker, Andreas; Hoeferkamp, Martin; Hoffman, Julia; Hoffmann, Dirk; Hofmann, Julia Isabell; Hohlfeld, Marc; Holmes, Tova Ray; Hong, Tae Min; Hooft van Huysduynen, Loek; Hostachy, Jean-Yves; Hou, Suen; Hoummada, Abdeslam; Howard, Jacob; Howarth, James; Hrabovsky, Miroslav; Hristova, Ivana; Hrivnac, Julius; Hryn'ova, Tetiana; Hsu, Catherine; Hsu, Pai-hsien Jennifer; Hsu, Shih-Chieh; Hu, Diedi; Hu, Xueye; Huang, Yanping; Hubacek, Zdenek; Hubaut, Fabrice; Huegging, Fabian; Huffman, Todd Brian; Hughes, Emlyn; Hughes, Gareth; Huhtinen, Mika; Hülsing, Tobias Alexander; Hurwitz, Martina; Huseynov, Nazim; Huston, Joey; Huth, John; Iacobucci, Giuseppe; Iakovidis, Georgios; Ibragimov, Iskander; Iconomidou-Fayard, Lydia; Ideal, Emma; Iengo, Paolo; Igonkina, Olga; Iizawa, Tomoya; Ikegami, Yoichi; Ikematsu, Katsumasa; Ikeno, Masahiro; Ilchenko, Iurii; Iliadis, Dimitrios; Ilic, Nikolina; Inamaru, Yuki; Ince, Tayfun; Ioannou, Pavlos; Iodice, Mauro; Iordanidou, Kalliopi; Ippolito, Valerio; Irles Quiles, Adrian; Isaksson, Charlie; Ishino, Masaya; Ishitsuka, Masaki; Ishmukhametov, Renat; Issever, Cigdem; Istin, Serhat; Iturbe Ponce, Julia Mariana; Iuppa, Roberto; Ivarsson, Jenny; Iwanski, Wieslaw; Iwasaki, Hiroyuki; Izen, Joseph; Izzo, Vincenzo; Jackson, Brett; Jackson, Matthew; Jackson, Paul; Jaekel, Martin; Jain, Vivek; Jakobs, Karl; Jakobsen, Sune; Jakoubek, Tomas; Jakubek, Jan; Jamin, David Olivier; Jana, Dilip; Jansen, Eric; Jansen, Hendrik; Janssen, Jens; Janus, Michel; Jarlskog, Göran; Javadov, Namig; Javůrek, Tomáš; Jeanty, Laura; Jejelava, Juansher; Jeng, Geng-yuan; Jennens, David; Jenni, Peter; Jentzsch, Jennifer; Jeske, Carl; Jézéquel, Stéphane; Ji, Haoshuang; Ji, Weina; Jia, Jiangyong; Jiang, Yi; Jimenez Belenguer, Marcos; Jin, Shan; Jinaru, Adam; Jinnouchi, Osamu; Joergensen, Morten Dam; Johansson, Erik; Johansson, Per; Johns, Kenneth; Jon-And, Kerstin; Jones, Graham; Jones, Roger; Jones, Tim; Jongmanns, Jan; Jorge, Pedro; Joshi, Kiran Daniel; Jovicevic, Jelena; Ju, Xiangyang; Jung, Christian; Jungst, Ralph Markus; Jussel, Patrick; Juste Rozas, Aurelio; Kaci, Mohammed; Kaczmarska, Anna; Kado, Marumi; Kagan, Harris; Kagan, Michael; Kajomovitz, Enrique; Kalderon, Charles William; Kama, Sami; Kamenshchikov, Andrey; Kanaya, Naoko; Kaneda, Michiru; Kaneti, Steven; Kantserov, Vadim; Kanzaki, Junichi; Kaplan, Benjamin; Kapliy, Anton; Kar, Deepak; Karakostas, Konstantinos; Karastathis, Nikolaos; Karnevskiy, Mikhail; Karpov, Sergey; Karpova, Zoya; Karthik, Krishnaiyengar; Kartvelishvili, Vakhtang; Karyukhin, Andrey; Kashif, Lashkar; Kasieczka, Gregor; Kass, Richard; Kastanas, Alex; Kataoka, Yousuke; Katre, Akshay; Katzy, Judith; Kaushik, Venkatesh; Kawagoe, Kiyotomo; Kawamoto, Tatsuo; Kawamura, Gen; Kazama, Shingo; Kazanin, Vassili; Kazarinov, Makhail; Keeler, Richard; Kehoe, Robert; Keil, Markus; Keller, John; Kempster, Jacob Julian; Keoshkerian, Houry; Kepka, Oldrich; Kerševan, Borut Paul; Kersten, Susanne; Kessoku, Kohei; Keung, Justin; Khalil-zada, Farkhad; Khandanyan, Hovhannes; Khanov, Alexander; Khodinov, Alexander; Khomich, Andrei; Khoo, Teng Jian; Khoriauli, Gia; Khoroshilov, Andrey; Khovanskiy, Valery; Khramov, Evgeniy; Khubua, Jemal; Kim, Hee Yeun; Kim, Hyeon Jin; Kim, Shinhong; Kimura, Naoki; Kind, Oliver; King, Barry; King, Matthew; King, Robert Steven Beaufoy; King, Samuel Burton; Kirk, Julie; Kiryunin, Andrey; Kishimoto, Tomoe; Kisielewska, Danuta; Kiss, Florian; Kittelmann, Thomas; Kiuchi, Kenji; Kladiva, Eduard; Klein, Max; Klein, Uta; Kleinknecht, Konrad; Klimek, Pawel; Klimentov, Alexei; Klingenberg, Reiner; Klinger, Joel Alexander; Klioutchnikova, Tatiana; Klok, Peter; Kluge, Eike-Erik; Kluit, Peter; Kluth, Stefan; Kneringer, Emmerich; Knoops, Edith; Knue, Andrea; Kobayashi, Dai; Kobayashi, Tomio; Kobel, Michael; Kocian, Martin; Kodys, Peter; Koevesarki, Peter; Koffas, Thomas; Koffeman, Els; Kogan, Lucy Anne; Kohlmann, Simon; Kohout, Zdenek; Kohriki, Takashi; Koi, Tatsumi; Kolanoski, Hermann; Koletsou, Iro; Koll, James; Komar, Aston; Komori, Yuto; Kondo, Takahiko; Kondrashova, Nataliia; Köneke, Karsten; König, Adriaan; König, Sebastian; Kono, Takanori; Konoplich, Rostislav; Konstantinidis, Nikolaos; Kopeliansky, Revital; Koperny, Stefan; Köpke, Lutz; Kopp, Anna Katharina; Korcyl, Krzysztof; Kordas, Kostantinos; Korn, Andreas; Korol, Aleksandr; Korolkov, Ilya; Korolkova, Elena; Korotkov, Vladislav; Kortner, Oliver; Kortner, Sandra; Kostyukhin, Vadim; Kotov, Vladislav; Kotwal, Ashutosh; Kourkoumelis, Christine; Kouskoura, Vasiliki; Koutsman, Alex; Kowalewski, Robert Victor; Kowalski, Tadeusz; Kozanecki, Witold; Kozhin, Anatoly; Kral, Vlastimil; Kramarenko, Viktor; Kramberger, Gregor; Krasnopevtsev, Dimitriy; Krasny, Mieczyslaw Witold; Krasznahorkay, Attila; Kraus, Jana; Kravchenko, Anton; Kreiss, Sven; Kretz, Moritz; Kretzschmar, Jan; Kreutzfeldt, Kristof; Krieger, Peter; Kroeninger, Kevin; Kroha, Hubert; Kroll, Joe; Kroseberg, Juergen; Krstic, Jelena; Kruchonak, Uladzimir; Krüger, Hans; Kruker, Tobias; Krumnack, Nils; Krumshteyn, Zinovii; Kruse, Amanda; Kruse, Mark; Kruskal, Michael; Kubota, Takashi; Kuday, Sinan; Kuehn, Susanne; Kugel, Andreas; Kuhl, Andrew; Kuhl, Thorsten; Kukhtin, Victor; Kulchitsky, Yuri; Kuleshov, Sergey; Kuna, Marine; Kunkle, Joshua; Kupco, Alexander; Kurashige, Hisaya; Kurochkin, Yurii; Kurumida, Rie; Kus, Vlastimil; Kuwertz, Emma Sian; Kuze, Masahiro; Kvita, Jiri; La Rosa, Alessandro; La Rotonda, Laura; Lacasta, Carlos; Lacava, Francesco; Lacey, James; Lacker, Heiko; Lacour, Didier; Lacuesta, Vicente Ramón; Ladygin, Evgueni; Lafaye, Remi; Laforge, Bertrand; Lagouri, Theodota; Lai, Stanley; Laier, Heiko; Lambourne, Luke; Lammers, Sabine; Lampen, Caleb; Lampl, Walter; Lançon, Eric; Landgraf, Ulrich; Landon, Murrough; Lang, Valerie Susanne; Lankford, Andrew; Lanni, Francesco; Lantzsch, Kerstin; Laplace, Sandrine; Lapoire, Cecile; Laporte, Jean-Francois; Lari, Tommaso; Lassnig, Mario; Laurelli, Paolo; Lavrijsen, Wim; Law, Alexander; Laycock, Paul; Le, Bao Tran; Le Dortz, Olivier; Le Guirriec, Emmanuel; Le Menedeu, Eve; LeCompte, Thomas; Ledroit-Guillon, Fabienne Agnes Marie; Lee, Claire Alexandra; Lee, Hurng-Chun; Lee, Jason; Lee, Shih-Chang; Lee, Lawrence; Lefebvre, Guillaume; Lefebvre, Michel; Legger, Federica; Leggett, Charles; Lehan, Allan; Lehmacher, Marc; Lehmann Miotto, Giovanna; Lei, Xiaowen; Leight, William Axel; Leisos, Antonios; Leister, Andrew Gerard; Leite, Marco Aurelio Lisboa; Leitner, Rupert; Lellouch, Daniel; Lemmer, Boris; Leney, Katharine; Lenz, Tatjana; Lenzen, Georg; Lenzi, Bruno; Leone, Robert; Leone, Sandra; Leonhardt, Kathrin; Leonidopoulos, Christos; Leontsinis, Stefanos; Leroy, Claude; Lester, Christopher; Lester, Christopher Michael; Levchenko, Mikhail; Levêque, Jessica; Levin, Daniel; Levinson, Lorne; Levy, Mark; Lewis, Adrian; Lewis, George; Leyko, Agnieszka; Leyton, Michael; Li, Bing; Li, Bo; Li, Haifeng; Li, Ho Ling; Li, Lei; Li, Liang; Li, Shu; Li, Yichen; Liang, Zhijun; Liao, Hongbo; Liberti, Barbara; Lichard, Peter; Lie, Ki; Liebal, Jessica; Liebig, Wolfgang; Limbach, Christian; Limosani, Antonio; Lin, Simon; Lin, Tai-Hua; Linde, Frank; Lindquist, Brian Edward; Linnemann, James; Lipeles, Elliot; Lipniacka, Anna; Lisovyi, Mykhailo; Liss, Tony; Lissauer, David; Lister, Alison; Litke, Alan; Liu, Bo; Liu, Dong; Liu, Jianbei; Liu, Kun; Liu, Lulu; Liu, Miaoyuan; Liu, Minghui; Liu, Yanwen; Livan, Michele; Livermore, Sarah; Lleres, Annick; Llorente Merino, Javier; Lloyd, Stephen; Lo Sterzo, Francesco; Lobodzinska, Ewelina; Loch, Peter; Lockman, William; Loddenkoetter, Thomas; Loebinger, Fred; Loevschall-Jensen, Ask Emil; Loginov, Andrey; Loh, Chang Wei; Lohse, Thomas; Lohwasser, Kristin; Lokajicek, Milos; Lombardo, Vincenzo Paolo; Long, Brian Alexander; Long, Jonathan; Long, Robin Eamonn; Lopes, Lourenco; Lopez Mateos, David; Lopez Paredes, Brais; Lopez Paz, Ivan; Lorenz, Jeanette; Lorenzo Martinez, Narei; Losada, Marta; Loscutoff, Peter; Lou, XinChou; Lounis, Abdenour; Love, Jeremy; Love, Peter; Lowe, Andrew; Lu, Feng; Lubatti, Henry; Luci, Claudio; Lucotte, Arnaud; Luehring, Frederick; Lukas, Wolfgang; Luminari, Lamberto; Lundberg, Olof; Lund-Jensen, Bengt; Lungwitz, Matthias; Lynn, David; Lysak, Roman; Lytken, Else; Ma, Hong; Ma, Lian Liang; Maccarrone, Giovanni; Macchiolo, Anna; Machado Miguens, Joana; Macina, Daniela; Madaffari, Daniele; Madar, Romain; Maddocks, Harvey Jonathan; Mader, Wolfgang; Madsen, Alexander; Maeno, Mayuko; Maeno, Tadashi; Magradze, Erekle; Mahboubi, Kambiz; Mahlstedt, Joern; Mahmoud, Sara; Maiani, Camilla; Maidantchik, Carmen; Maier, Andreas Alexander; Maio, Amélia; Majewski, Stephanie; Makida, Yasuhiro; Makovec, Nikola; Mal, Prolay; Malaescu, Bogdan; Malecki, Pawel; Maleev, Victor; Malek, Fairouz; Mallik, Usha; Malon, David; Malone, Caitlin; Maltezos, Stavros; Malyshev, Vladimir; Malyukov, Sergei; Mamuzic, Judita; Mandelli, Beatrice; Mandelli, Luciano; Mandić, Igor; Mandrysch, Rocco; Maneira, José; Manfredini, Alessandro; Manhaes de Andrade Filho, Luciano; Manjarres Ramos, Joany Andreina; Mann, Alexander; Manning, Peter; Manousakis-Katsikakis, Arkadios; Mansoulie, Bruno; Mantifel, Rodger; Mapelli, Livio; March, Luis; Marchand, Jean-Francois; Marchiori, Giovanni; Marcisovsky, Michal; Marino, Christopher; Marjanovic, Marija; Marques, Carlos; Marroquim, Fernando; Marsden, Stephen Philip; Marshall, Zach; Marti, Lukas Fritz; Marti-Garcia, Salvador; Martin, Brian; Martin, Brian Thomas; Martin, Tim; Martin, Victoria Jane; Martin dit Latour, Bertrand; Martinez, Homero; Martinez, Mario; Martin-Haugh, Stewart; Martyniuk, Alex; Marx, Marilyn; Marzano, Francesco; Marzin, Antoine; Masetti, Lucia; Mashimo, Tetsuro; Mashinistov, Ruslan; Masik, Jiri; Maslennikov, Alexey; Massa, Ignazio; Massol, Nicolas; Mastrandrea, Paolo; Mastroberardino, Anna; Masubuchi, Tatsuya; Mättig, Peter; Mattmann, Johannes; Maurer, Julien; Maxfield, Stephen; Maximov, Dmitriy; Mazini, Rachid; Mazzaferro, Luca; Mc Goldrick, Garrin; Mc Kee, Shawn Patrick; McCarn, Allison; McCarthy, Robert; McCarthy, Tom; McCubbin, Norman; McFarlane, Kenneth; Mcfayden, Josh; Mchedlidze, Gvantsa; McMahon, Steve; McPherson, Robert; Meade, Andrew; Mechnich, Joerg; Medinnis, Michael; Meehan, Samuel; Mehlhase, Sascha; Mehta, Andrew; Meier, Karlheinz; Meineck, Christian; Meirose, Bernhard; Melachrinos, Constantinos; Mellado Garcia, Bruce Rafael; Meloni, Federico; Mengarelli, Alberto; Menke, Sven; Meoni, Evelin; Mercurio, Kevin Michael; Mergelmeyer, Sebastian; Meric, Nicolas; Mermod, Philippe; Merola, Leonardo; Meroni, Chiara; Merritt, Frank; Merritt, Hayes; Messina, Andrea; Metcalfe, Jessica; Mete, Alaettin Serhan; Meyer, Carsten; Meyer, Christopher; Meyer, Jean-Pierre; Meyer, Jochen; Middleton, Robin; Migas, Sylwia; Mijović, Liza; Mikenberg, Giora; Mikestikova, Marcela; Mikuž, Marko; Milic, Adriana; Miller, David; Mills, Corrinne; Milov, Alexander; Milstead, David; Milstein, Dmitry; Minaenko, Andrey; Minashvili, Irakli; Mincer, Allen; Mindur, Bartosz; Mineev, Mikhail; Ming, Yao; Mir, Lluisa-Maria; Mirabelli, Giovanni; Mitani, Takashi; Mitrevski, Jovan; Mitsou, Vasiliki A; Mitsui, Shingo; Miucci, Antonio; Miyagawa, Paul; Mjörnmark, Jan-Ulf; Moa, Torbjoern; Mochizuki, Kazuya; Mohapatra, Soumya; Mohr, Wolfgang; Molander, Simon; Moles-Valls, Regina; Mönig, Klaus; Monini, Caterina; Monk, James; Monnier, Emmanuel; Montejo Berlingen, Javier; Monticelli, Fernando; Monzani, Simone; Moore, Roger; Moraes, Arthur; Morange, Nicolas; Moreno, Deywis; Moreno Llácer, María; Morettini, Paolo; Morgenstern, Marcus; Morii, Masahiro; Moritz, Sebastian; Morley, Anthony Keith; Mornacchi, Giuseppe; Morris, John; Morvaj, Ljiljana; Moser, Hans-Guenther; Mosidze, Maia; Moss, Josh; Motohashi, Kazuki; Mount, Richard; Mountricha, Eleni; Mouraviev, Sergei; Moyse, Edward; Muanza, Steve; Mudd, Richard; Mueller, Felix; Mueller, James; Mueller, Klemens; Mueller, Thibaut; Mueller, Timo; Muenstermann, Daniel; Munwes, Yonathan; Murillo Quijada, Javier Alberto; Murray, Bill; Musheghyan, Haykuhi; Musto, Elisa; Myagkov, Alexey; Myska, Miroslav; Nackenhorst, Olaf; Nadal, Jordi; Nagai, Koichi; Nagai, Ryo; Nagai, Yoshikazu; Nagano, Kunihiro; Nagarkar, Advait; Nagasaka, Yasushi; Nagel, Martin; Nairz, Armin Michael; Nakahama, Yu; Nakamura, Koji; Nakamura, Tomoaki; Nakano, Itsuo; Namasivayam, Harisankar; Nanava, Gizo; Narayan, Rohin; Nattermann, Till; Naumann, Thomas; Navarro, Gabriela; Nayyar, Ruchika; Neal, Homer; Nechaeva, Polina; Neep, Thomas James; Nef, Pascal Daniel; Negri, Andrea; Negri, Guido; Negrini, Matteo; Nektarijevic, Snezana; Nelson, Andrew; Nelson, Timothy Knight; Nemecek, Stanislav; Nemethy, Peter; Nepomuceno, Andre Asevedo; Nessi, Marzio; Neubauer, Mark; Neumann, Manuel; Neves, Ricardo; Nevski, Pavel; Newman, Paul; Nguyen, Duong Hai; Nickerson, Richard; Nicolaidou, Rosy; Nicquevert, Bertrand; Nielsen, Jason; Nikiforou, Nikiforos; Nikiforov, Andriy; Nikolaenko, Vladimir; Nikolic-Audit, Irena; Nikolics, Katalin; Nikolopoulos, Konstantinos; Nilsson, Paul; Ninomiya, Yoichi; Nisati, Aleandro; Nisius, Richard; Nobe, Takuya; Nodulman, Lawrence; Nomachi, Masaharu; Nomidis, Ioannis; Norberg, Scarlet; Nordberg, Markus; Novgorodova, Olga; Nowak, Sebastian; Nozaki, Mitsuaki; Nozka, Libor; Ntekas, Konstantinos; Nunes Hanninger, Guilherme; Nunnemann, Thomas; Nurse, Emily; Nuti, Francesco; O'Brien, Brendan Joseph; O'grady, Fionnbarr; O'Neil, Dugan; O'Shea, Val; Oakham, Gerald; Oberlack, Horst; Obermann, Theresa; Ocariz, Jose; Ochi, Atsuhiko; Ochoa, Ines; Oda, Susumu; Odaka, Shigeru; Ogren, Harold; Oh, Alexander; Oh, Seog; Ohm, Christian; Ohman, Henrik; Ohshima, Takayoshi; Okamura, Wataru; Okawa, Hideki; Okumura, Yasuyuki; Okuyama, Toyonobu; Olariu, Albert; Olchevski, Alexander; Olivares Pino, Sebastian Andres; Oliveira Damazio, Denis; Oliver Garcia, Elena; Olszewski, Andrzej; Olszowska, Jolanta; Onofre, António; Onyisi, Peter; Oram, Christopher; Oreglia, Mark; Oren, Yona; Orestano, Domizia; Orlando, Nicola; Oropeza Barrera, Cristina; Orr, Robert; Osculati, Bianca; Ospanov, Rustem; Otero y Garzon, Gustavo; Otono, Hidetoshi; Ouchrif, Mohamed; Ouellette, Eric; Ould-Saada, Farid; Ouraou, Ahmimed; Oussoren, Koen Pieter; Ouyang, Qun; Ovcharova, Ana; Owen, Mark; Ozcan, Veysi Erkcan; Ozturk, Nurcan; Pachal, Katherine; Pacheco Pages, Andres; Padilla Aranda, Cristobal; Pagáčová, Martina; Pagan Griso, Simone; Paganis, Efstathios; Pahl, Christoph; Paige, Frank; Pais, Preema; Pajchel, Katarina; Palacino, Gabriel; Palestini, Sandro; Palka, Marek; Pallin, Dominique; Palma, Alberto; Palmer, Jody; Pan, Yibin; Panagiotopoulou, Evgenia; Panduro Vazquez, William; Pani, Priscilla; Panikashvili, Natalia; Panitkin, Sergey; Pantea, Dan; Paolozzi, Lorenzo; Papadopoulou, Theodora; Papageorgiou, Konstantinos; Paramonov, Alexander; Paredes Hernandez, Daniela; Parker, Michael Andrew; Parodi, Fabrizio; Parsons, John; Parzefall, Ulrich; Pasqualucci, Enrico; Passaggio, Stefano; Passeri, Antonio; Pastore, Fernanda; Pastore, Francesca; Pásztor, Gabriella; Pataraia, Sophio; Patel, Nikhul; Pater, Joleen; Patricelli, Sergio; Pauly, Thilo; Pearce, James; Pedersen, Maiken; Pedraza Lopez, Sebastian; Pedro, Rute; Peleganchuk, Sergey; Pelikan, Daniel; Peng, Haiping; Penning, Bjoern; Penwell, John; Perepelitsa, Dennis; Perez Codina, Estel; Pérez García-Estañ, María Teresa; Perez Reale, Valeria; Perini, Laura; Pernegger, Heinz; Perrino, Roberto; Peschke, Richard; Peshekhonov, Vladimir; Peters, Krisztian; Peters, Yvonne; Petersen, Brian; Petersen, Troels; Petit, Elisabeth; Petridis, Andreas; Petridou, Chariclia; Petrolo, Emilio; Petrucci, Fabrizio; Pettersson, Nora Emilia; Pezoa, Raquel; Phillips, Peter William; Piacquadio, Giacinto; Pianori, Elisabetta; Picazio, Attilio; Piccaro, Elisa; Piccinini, Maurizio; Piegaia, Ricardo; Pignotti, David; Pilcher, James; Pilkington, Andrew; Pina, João Antonio; Pinamonti, Michele; Pinder, Alex; Pinfold, James; Pingel, Almut; Pinto, Belmiro; Pires, Sylvestre; Pitt, Michael; Pizio, Caterina; Plazak, Lukas; Pleier, Marc-Andre; Pleskot, Vojtech; Plotnikova, Elena; Plucinski, Pawel; Poddar, Sahill; Podlyski, Fabrice; Poettgen, Ruth; Poggioli, Luc; Pohl, David-leon; Pohl, Martin; Polesello, Giacomo; Policicchio, Antonio; Polifka, Richard; Polini, Alessandro; Pollard, Christopher Samuel; Polychronakos, Venetios; Pommès, Kathy; Pontecorvo, Ludovico; Pope, Bernard; Popeneciu, Gabriel Alexandru; Popovic, Dragan; Poppleton, Alan; Portell Bueso, Xavier; Pospisil, Stanislav; Potamianos, Karolos; Potrap, Igor; Potter, Christina; Potter, Christopher; Poulard, Gilbert; Poveda, Joaquin; Pozdnyakov, Valery; Pralavorio, Pascal; Pranko, Aliaksandr; Prasad, Srivas; Pravahan, Rishiraj; Prell, Soeren; Price, Darren; Price, Joe; Price, Lawrence; Prieur, Damien; Primavera, Margherita; Proissl, Manuel; Prokofiev, Kirill; Prokoshin, Fedor; Protopapadaki, Eftychia-sofia; Protopopescu, Serban; Proudfoot, James; Przybycien, Mariusz; Przysiezniak, Helenka; Ptacek, Elizabeth; Puddu, Daniele; Pueschel, Elisa; Puldon, David; Purohit, Milind; Puzo, Patrick; Qian, Jianming; Qin, Gang; Qin, Yang; Quadt, Arnulf; Quarrie, David; Quayle, William; Queitsch-Maitland, Michaela; Quilty, Donnchadha; Qureshi, Anum; Radeka, Veljko; Radescu, Voica; Radhakrishnan, Sooraj Krishnan; Radloff, Peter; Rados, Pere; Ragusa, Francesco; Rahal, Ghita; Rajagopalan, Srinivasan; Rammensee, Michael; Randle-Conde, Aidan Sean; Rangel-Smith, Camila; Rao, Kanury; Rauscher, Felix; Rave, Tobias Christian; Ravenscroft, Thomas; Raymond, Michel; Read, Alexander Lincoln; Readioff, Nathan Peter; Rebuzzi, Daniela; Redelbach, Andreas; Redlinger, George; Reece, Ryan; Reeves, Kendall; Rehnisch, Laura; Reisin, Hernan; Relich, Matthew; Rembser, Christoph; Ren, Huan; Ren, Zhongliang; Renaud, Adrien; Rescigno, Marco; Resconi, Silvia; Rezanova, Olga; Reznicek, Pavel; Rezvani, Reyhaneh; Richter, Robert; Ridel, Melissa; Rieck, Patrick; Rieger, Julia; Rijssenbeek, Michael; Rimoldi, Adele; Rinaldi, Lorenzo; Ritsch, Elmar; Riu, Imma; Rizatdinova, Flera; Rizvi, Eram; Robertson, Steven; Robichaud-Veronneau, Andree; Robinson, Dave; Robinson, James; Robson, Aidan; Roda, Chiara; Rodrigues, Luis; Roe, Shaun; Røhne, Ole; Rolli, Simona; Romaniouk, Anatoli; Romano, Marino; Romero Adam, Elena; Rompotis, Nikolaos; Roos, Lydia; Ros, Eduardo; Rosati, Stefano; Rosbach, Kilian; Rose, Matthew; Rosendahl, Peter Lundgaard; Rosenthal, Oliver; Rossetti, Valerio; Rossi, Elvira; Rossi, Leonardo Paolo; Rosten, Rachel; Rotaru, Marina; Roth, Itamar; Rothberg, Joseph; Rousseau, David; Royon, Christophe; Rozanov, Alexandre; Rozen, Yoram; Ruan, Xifeng; Rubbo, Francesco; Rubinskiy, Igor; Rud, Viacheslav; Rudolph, Christian; Rudolph, Matthew Scott; Rühr, Frederik; Ruiz-Martinez, Aranzazu; Rurikova, Zuzana; Rusakovich, Nikolai; Ruschke, Alexander; Rutherfoord, John; Ruthmann, Nils; Ryabov, Yury; Rybar, Martin; Rybkin, Grigori; Ryder, Nick; Saavedra, Aldo; Sacerdoti, Sabrina; Saddique, Asif; Sadeh, Iftach; Sadrozinski, Hartmut; Sadykov, Renat; Safai Tehrani, Francesco; Sakamoto, Hiroshi; Sakurai, Yuki; Salamanna, Giuseppe; Salamon, Andrea; Saleem, Muhammad; Salek, David; Sales De Bruin, Pedro Henrique; Salihagic, Denis; Salnikov, Andrei; Salt, José; Salvachua Ferrando, Belén; Salvatore, Daniela; Salvatore, Pasquale Fabrizio; Salvucci, Antonio; Salzburger, Andreas; Sampsonidis, Dimitrios; Sanchez, Arturo; Sánchez, Javier; Sanchez Martinez, Victoria; Sandaker, Heidi; Sandbach, Ruth Laura; Sander, Heinz Georg; Sanders, Michiel; Sandhoff, Marisa; Sandoval, Tanya; Sandoval, Carlos; Sandstroem, Rikard; Sankey, Dave; Sansoni, Andrea; Santoni, Claudio; Santonico, Rinaldo; Santos, Helena; Santoyo Castillo, Itzebelt; Sapp, Kevin; Sapronov, Andrey; Saraiva, João; Sarrazin, Bjorn; Sartisohn, Georg; Sasaki, Osamu; Sasaki, Yuichi; Sauvage, Gilles; Sauvan, Emmanuel; Savard, Pierre; Savu, Dan Octavian; Sawyer, Craig; Sawyer, Lee; Saxon, David; Saxon, James; Sbarra, Carla; Sbrizzi, Antonio; Scanlon, Tim; Scannicchio, Diana; Scarcella, Mark; Scarfone, Valerio; Schaarschmidt, Jana; Schacht, Peter; Schaefer, Douglas; Schaefer, Ralph; Schaepe, Steffen; Schaetzel, Sebastian; Schäfer, Uli; Schaffer, Arthur; Schaile, Dorothee; Schamberger, R. Dean; Scharf, Veit; Schegelsky, Valery; Scheirich, Daniel; Schernau, Michael; Scherzer, Max; Schiavi, Carlo; Schieck, Jochen; Schillo, Christian; Schioppa, Marco; Schlenker, Stefan; Schmidt, Evelyn; Schmieden, Kristof; Schmitt, Christian; Schmitt, Christopher; Schmitt, Sebastian; Schneider, Basil; Schnellbach, Yan Jie; Schnoor, Ulrike; Schoeffel, Laurent; Schoening, Andre; Schoenrock, Bradley Daniel; Schorlemmer, Andre Lukas; Schott, Matthias; Schouten, Doug; Schovancova, Jaroslava; Schramm, Steven; Schreyer, Manuel; Schroeder, Christian; Schuh, Natascha; Schultens, Martin Johannes; Schultz-Coulon, Hans-Christian; Schulz, Holger; Schumacher, Markus; Schumm, Bruce; Schune, Philippe; Schwanenberger, Christian; Schwartzman, Ariel; Schwegler, Philipp; Schwemling, Philippe; Schwienhorst, Reinhard; Schwindling, Jerome; Schwindt, Thomas; Schwoerer, Maud; Sciacca, Gianfranco; Scifo, Estelle; Sciolla, Gabriella; Scott, Bill; Scuri, Fabrizio; Scutti, Federico; Searcy, Jacob; Sedov, George; Sedykh, Evgeny; Seidel, Sally; Seiden, Abraham; Seifert, Frank; Seixas, José; Sekhniaidze, Givi; Sekula, Stephen; Selbach, Karoline Elfriede; Seliverstov, Dmitry; Sellers, Graham; Semprini-Cesari, Nicola; Serfon, Cedric; Serin, Laurent; Serkin, Leonid; Serre, Thomas; Seuster, Rolf; Severini, Horst; Sfiligoj, Tina; Sforza, Federico; Sfyrla, Anna; Shabalina, Elizaveta; Shamim, Mansoora; Shan, Lianyou; Shang, Ruo-yu; Shank, James; Shapiro, Marjorie; Shatalov, Pavel; Shaw, Kate; Shehu, Ciwake Yusufu; Sherwood, Peter; Shi, Liaoshan; Shimizu, Shima; Shimmin, Chase Owen; Shimojima, Makoto; Shiyakova, Mariya; Shmeleva, Alevtina; Shochet, Mel; Short, Daniel; Shrestha, Suyog; Shulga, Evgeny; Shupe, Michael; Shushkevich, Stanislav; Sicho, Petr; Sidiropoulou, Ourania; Sidorov, Dmitri; Sidoti, Antonio; Siegert, Frank; Sijacki, Djordje; Silva, José; Silver, Yiftah; Silverstein, Daniel; Silverstein, Samuel; Simak, Vladislav; Simard, Olivier; Simic, Ljiljana; Simion, Stefan; Simioni, Eduard; Simmons, Brinick; Simoniello, Rosa; Simonyan, Margar; Sinervo, Pekka; Sinev, Nikolai; Sipica, Valentin; Siragusa, Giovanni; Sircar, Anirvan; Sisakyan, Alexei; Sivoklokov, Serguei; Sjölin, Jörgen; Sjursen, Therese; Skottowe, Hugh Philip; Skovpen, Kirill; Skubic, Patrick; Slater, Mark; Slavicek, Tomas; Sliwa, Krzysztof; Smakhtin, Vladimir; Smart, Ben; Smestad, Lillian; Smirnov, Sergei; Smirnov, Yury; Smirnova, Lidia; Smirnova, Oxana; Smith, Kenway; Smizanska, Maria; Smolek, Karel; Snesarev, Andrei; Snidero, Giacomo; Snyder, Scott; Sobie, Randall; Socher, Felix; Soffer, Abner; Soh, Dart-yin; Solans, Carlos; Solar, Michael; Solc, Jaroslav; Soldatov, Evgeny; Soldevila, Urmila; Solfaroli Camillocci, Elena; Solodkov, Alexander; Soloshenko, Alexei; Solovyanov, Oleg; Solovyev, Victor; Sommer, Philip; Song, Hong Ye; Soni, Nitesh; Sood, Alexander; Sopczak, Andre; Sopko, Bruno; Sopko, Vit; Sorin, Veronica; Sosebee, Mark; Soualah, Rachik; Soueid, Paul; Soukharev, Andrey; South, David; Spagnolo, Stefania; Spanò, Francesco; Spearman, William Robert; Spettel, Fabian; Spighi, Roberto; Spigo, Giancarlo; Spousta, Martin; Spreitzer, Teresa; Spurlock, Barry; St Denis, Richard Dante; Staerz, Steffen; Stahlman, Jonathan; Stamen, Rainer; Stanecka, Ewa; Stanek, Robert; Stanescu, Cristian; Stanescu-Bellu, Madalina; Stanitzki, Marcel Michael; Stapnes, Steinar; Starchenko, Evgeny; Stark, Jan; Staroba, Pavel; Starovoitov, Pavel; Staszewski, Rafal; Stavina, Pavel; Steinberg, Peter; Stelzer, Bernd; Stelzer, Harald Joerg; Stelzer-Chilton, Oliver; Stenzel, Hasko; Stern, Sebastian; Stewart, Graeme; Stillings, Jan Andre; Stockton, Mark; Stoebe, Michael; Stoicea, Gabriel; Stolte, Philipp; Stonjek, Stefan; Stradling, Alden; Straessner, Arno; Stramaglia, Maria Elena; Strandberg, Jonas; Strandberg, Sara; Strandlie, Are; Strauss, Emanuel; Strauss, Michael; Strizenec, Pavol; Ströhmer, Raimund; Strom, David; Stroynowski, Ryszard; Stucci, Stefania Antonia; Stugu, Bjarne; Styles, Nicholas Adam; Su, Dong; Su, Jun; Subramania, Halasya Siva; Subramaniam, Rajivalochan; Succurro, Antonella; Sugaya, Yorihito; Suhr, Chad; Suk, Michal; Sulin, Vladimir; Sultansoy, Saleh; Sumida, Toshi; Sun, Xiaohu; Sundermann, Jan Erik; Suruliz, Kerim; Susinno, Giancarlo; Sutton, Mark; Suzuki, Yu; Svatos, Michal; Swedish, Stephen; Swiatlowski, Maximilian; Sykora, Ivan; Sykora, Tomas; Ta, Duc; Taccini, Cecilia; Tackmann, Kerstin; Taenzer, Joe; Taffard, Anyes; Tafirout, Reda; Taiblum, Nimrod; Takahashi, Yuta; Takai, Helio; Takashima, Ryuichi; Takeda, Hiroshi; Takeshita, Tohru; Takubo, Yosuke; Talby, Mossadek; Talyshev, Alexey; Tam, Jason; Tan, Kong Guan; Tanaka, Junichi; Tanaka, Reisaburo; Tanaka, Satoshi; Tanaka, Shuji; Tanasijczuk, Andres Jorge; Tannenwald, Benjamin Bordy; Tannoury, Nancy; Tapprogge, Stefan; Tarem, Shlomit; Tarrade, Fabien; Tartarelli, Giuseppe Francesco; Tas, Petr; Tasevsky, Marek; Tashiro, Takuya; Tassi, Enrico; Tavares Delgado, Ademar; Tayalati, Yahya; Taylor, Frank; Taylor, Geoffrey; Taylor, Wendy; Teischinger, Florian Alfred; Teixeira Dias Castanheira, Matilde; Teixeira-Dias, Pedro; Temming, Kim Katrin; Ten Kate, Herman; Teng, Ping-Kun; Teoh, Jia Jian; Terada, Susumu; Terashi, Koji; Terron, Juan; Terzo, Stefano; Testa, Marianna; Teuscher, Richard; Therhaag, Jan; Theveneaux-Pelzer, Timothée; Thomas, Juergen; Thomas-Wilsker, Joshuha; Thompson, Emily; Thompson, Paul; Thompson, Peter; Thompson, Stan; Thomsen, Lotte Ansgaard; Thomson, Evelyn; Thomson, Mark; Thong, Wai Meng; Thun, Rudolf; Tian, Feng; Tibbetts, Mark James; Tikhomirov, Vladimir; Tikhonov, Yury; Timoshenko, Sergey; Tiouchichine, Elodie; Tipton, Paul; Tisserant, Sylvain; Todorov, Theodore; Todorova-Nova, Sharka; Toggerson, Brokk; Tojo, Junji; Tokár, Stanislav; Tokushuku, Katsuo; Tollefson, Kirsten; Tomlinson, Lee; Tomoto, Makoto; Tompkins, Lauren; Toms, Konstantin; Topilin, Nikolai; Torrence, Eric; Torres, Heberth; Torró Pastor, Emma; Toth, Jozsef; Touchard, Francois; Tovey, Daniel; Tran, Huong Lan; Trefzger, Thomas; Tremblet, Louis; Tricoli, Alessandro; Trigger, Isabel Marian; Trincaz-Duvoid, Sophie; Tripiana, Martin; Triplett, Nathan; Trischuk, William; Trocmé, Benjamin; Troncon, Clara; Trottier-McDonald, Michel; Trovatelli, Monica; True, Patrick; Trzebinski, Maciej; Trzupek, Adam; Tsarouchas, Charilaos; Tseng, Jeffrey; Tsiareshka, Pavel; Tsionou, Dimitra; Tsipolitis, Georgios; Tsirintanis, Nikolaos; Tsiskaridze, Shota; Tsiskaridze, Vakhtang; Tskhadadze, Edisher; Tsukerman, Ilya; Tsulaia, Vakhtang; Tsuno, Soshi; Tsybychev, Dmitri; Tudorache, Alexandra; Tudorache, Valentina; Tuna, Alexander Naip; Tupputi, Salvatore; Turchikhin, Semen; Turecek, Daniel; Turk Cakir, Ilkay; Turra, Ruggero; Tuts, Michael; Tykhonov, Andrii; Tylmad, Maja; Tyndel, Mike; Uchida, Kirika; Ueda, Ikuo; Ueno, Ryuichi; Ughetto, Michael; Ugland, Maren; Uhlenbrock, Mathias; Ukegawa, Fumihiko; Unal, Guillaume; Undrus, Alexander; Unel, Gokhan; Ungaro, Francesca; Unno, Yoshinobu; Urbaniec, Dustin; Urquijo, Phillip; Usai, Giulio; Usanova, Anna; Vacavant, Laurent; Vacek, Vaclav; Vachon, Brigitte; Valencic, Nika; Valentinetti, Sara; Valero, Alberto; Valery, Loic; Valkar, Stefan; Valladolid Gallego, Eva; Vallecorsa, Sofia; Valls Ferrer, Juan Antonio; Van Den Wollenberg, Wouter; Van Der Deijl, Pieter; van der Geer, Rogier; van der Graaf, Harry; Van Der Leeuw, Robin; van der Ster, Daniel; van Eldik, Niels; van Gemmeren, Peter; Van Nieuwkoop, Jacobus; van Vulpen, Ivo; van Woerden, Marius Cornelis; Vanadia, Marco; Vandelli, Wainer; Vanguri, Rami; Vaniachine, Alexandre; Vankov, Peter; Vannucci, Francois; Vardanyan, Gagik; Vari, Riccardo; Varnes, Erich; Varol, Tulin; Varouchas, Dimitris; Vartapetian, Armen; Varvell, Kevin; Vazeille, Francois; Vazquez Schroeder, Tamara; Veatch, Jason; Veloso, Filipe; Veneziano, Stefano; Ventura, Andrea; Ventura, Daniel; Venturi, Manuela; Venturi, Nicola; Venturini, Alessio; Vercesi, Valerio; Verducci, Monica; Verkerke, Wouter; Vermeulen, Jos; Vest, Anja; Vetterli, Michel; Viazlo, Oleksandr; Vichou, Irene; Vickey, Trevor; Vickey Boeriu, Oana Elena; Viehhauser, Georg; Viel, Simon; Vigne, Ralph; Villa, Mauro; Villaplana Perez, Miguel; Vilucchi, Elisabetta; Vincter, Manuella; Vinogradov, Vladimir; Virzi, Joseph; Vivarelli, Iacopo; Vives Vaque, Francesc; Vlachos, Sotirios; Vladoiu, Dan; Vlasak, Michal; Vogel, Adrian; Vogel, Marcelo; Vokac, Petr; Volpi, Guido; Volpi, Matteo; von der Schmitt, Hans; von Radziewski, Holger; von Toerne, Eckhard; Vorobel, Vit; Vorobev, Konstantin; Vos, Marcel; Voss, Rudiger; Vossebeld, Joost; Vranjes, Nenad; Vranjes Milosavljevic, Marija; Vrba, Vaclav; Vreeswijk, Marcel; Vu Anh, Tuan; Vuillermet, Raphael; Vukotic, Ilija; Vykydal, Zdenek; Wagner, Peter; Wagner, Wolfgang; Wahlberg, Hernan; Wahrmund, Sebastian; Wakabayashi, Jun; Walder, James; Walker, Rodney; Walkowiak, Wolfgang; Wall, Richard; Waller, Peter; Walsh, Brian; Wang, Chao; Wang, Chiho; Wang, Fuquan; Wang, Haichen; Wang, Hulin; Wang, Jike; Wang, Jin; Wang, Kuhan; Wang, Rui; Wang, Song-Ming; Wang, Tan; Wang, Xiaoxiao; Wanotayaroj, Chaowaroj; Warburton, Andreas; Ward, Patricia; Wardrope, David Robert; Warsinsky, Markus; Washbrook, Andrew; Wasicki, Christoph; Watkins, Peter; Watson, Alan; Watson, Ian; Watson, Miriam; Watts, Gordon; Watts, Stephen; Waugh, Ben; Webb, Samuel; Weber, Michele; Weber, Stefan Wolf; Webster, Jordan S; Weidberg, Anthony; Weigell, Philipp; Weinert, Benjamin; Weingarten, Jens; Weiser, Christian; Weits, Hartger; Wells, Phillippa; Wenaus, Torre; Wendland, Dennis; Weng, Zhili; Wengler, Thorsten; Wenig, Siegfried; Wermes, Norbert; Werner, Matthias; Werner, Per; Wessels, Martin; Wetter, Jeffrey; Whalen, Kathleen; White, Andrew; White, Martin; White, Ryan; White, Sebastian; Whiteson, Daniel; Wicke, Daniel; Wickens, Fred; Wiedenmann, Werner; Wielers, Monika; Wienemann, Peter; Wiglesworth, Craig; Wiik-Fuchs, Liv Antje Mari; Wijeratne, Peter Alexander; Wildauer, Andreas; Wildt, Martin Andre; Wilkens, Henric George; Will, Jonas Zacharias; Williams, Hugh; Williams, Sarah; Willis, Christopher; Willocq, Stephane; Wilson, Alan; Wilson, John; Wingerter-Seez, Isabelle; Winklmeier, Frank; Winter, Benedict Tobias; Wittgen, Matthias; Wittig, Tobias; Wittkowski, Josephine; Wollstadt, Simon Jakob; Wolter, Marcin Wladyslaw; Wolters, Helmut; Wosiek, Barbara; Wotschack, Jorg; Woudstra, Martin; Wozniak, Krzysztof; Wright, Michael; Wu, Mengqing; Wu, Sau Lan; Wu, Xin; Wu, Yusheng; Wulf, Evan; Wyatt, Terry Richard; Wynne, Benjamin; Xella, Stefania; Xiao, Meng; Xu, Da; Xu, Lailin; Yabsley, Bruce; Yacoob, Sahal; Yamada, Miho; Yamaguchi, Hiroshi; Yamaguchi, Yohei; Yamamoto, Akira; Yamamoto, Kyoko; Yamamoto, Shimpei; Yamamura, Taiki; Yamanaka, Takashi; Yamauchi, Katsuya; Yamazaki, Yuji; Yan, Zhen; Yang, Haijun; Yang, Hongtao; Yang, Un-Ki; Yang, Yi; Yanush, Serguei; Yao, Liwen; Yao, Weiming; Yasu, Yoshiji; Yatsenko, Elena; Yau Wong, Kaven Henry; Ye, Jingbo; Ye, Shuwei; Yen, Andy L; Yildirim, Eda; Yilmaz, Metin; Yoosoofmiya, Reza; Yorita, Kohei; Yoshida, Rikutaro; Yoshihara, Keisuke; Young, Charles; Young, Christopher John; Youssef, Saul; Yu, David Ren-Hwa; Yu, Jaehoon; Yu, Jiaming; Yu, Jie; Yuan, Li; Yurkewicz, Adam; Yusuff, Imran; Zabinski, Bartlomiej; Zaidan, Remi; Zaitsev, Alexander; Zaman, Aungshuman; Zambito, Stefano; Zanello, Lucia; Zanzi, Daniele; Zeitnitz, Christian; Zeman, Martin; Zemla, Andrzej; Zengel, Keith; Zenin, Oleg; Ženiš, Tibor; Zerwas, Dirk; Zevi della Porta, Giovanni; Zhang, Dongliang; Zhang, Fangzhou; Zhang, Huaqiao; Zhang, Jinlong; Zhang, Lei; Zhang, Xueyao; Zhang, Zhiqing; Zhao, Zhengguo; Zhemchugov, Alexey; Zhong, Jiahang; Zhou, Bing; Zhou, Lei; Zhou, Ning; Zhu, Cheng Guang; Zhu, Hongbo; Zhu, Junjie; Zhu, Yingchun; Zhuang, Xuai; Zhukov, Konstantin; Zibell, Andre; Zieminska, Daria; Zimine, Nikolai; Zimmermann, Christoph; Zimmermann, Robert; Zimmermann, Simone; Zimmermann, Stephanie; Zinonos, Zinonas; Ziolkowski, Michael; Zobernig, Georg; Zoccoli, Antonio; zur Nedden, Martin; Zurzolo, Giovanni; Zutshi, Vishnu; Zwalinski, Lukasz

    2014-09-15

    A novel technique to identify and split clusters created by multiple charged particles in the ATLAS pixel detector using a set of artificial neural networks is presented. Such merged clusters are a common feature of tracks originating from highly energetic objects, such as jets. Neural networks are trained using Monte Carlo samples produced with a detailed detector simulation. This technique replaces the former clustering approach based on a connected component analysis and charge interpolation. The performance of the neural network splitting technique is quantified using data from proton-proton collisions at the LHC collected by the ATLAS detector in 2011 and from Monte Carlo simulations. This technique reduces the number of clusters shared between tracks in highly energetic jets by up to a factor of three. It also provides more precise position and error estimates of the clusters in both the transverse and longitudinal impact parameter resolution.

  3. Modern design of a fast front-end computer

    Science.gov (United States)

    Šoštarić, Z.; Anic̈ić, D.; Sekolec, L.; Su, J.

    1994-12-01

    Front-end computers (FEC) at Paul Scherrer Institut provide access to accelerator CAMAC-based sensors and actuators by way of a local area network. In the scope of the new generation FEC project, a front-end is regarded as a collection of services. The functionality of one such service is described in terms of Yourdon's environment, behaviour, processor and task models. The computational model (software representation of the environment) of the service is defined separately, using the information model of the Shlaer-Mellor method, and Sather OO language. In parallel with the analysis and later with the design, a suite of test programmes was developed to evaluate the feasibility of different computing platforms for the project and a set of rapid prototypes was produced to resolve different implementation issues. The past and future aspects of the project and its driving forces are presented. Justification of the choice of methodology, platform and requirement, is given. We conclude with a description of the present state, priorities and limitations of our project.

  4. Underwater fiber-wireless communication with a passive front end

    Science.gov (United States)

    Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

    2017-11-01

    We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

  5. Front end support systems for the Advanced Photon Source

    International Nuclear Information System (INIS)

    Barraza, J.; Shu, D.; Kuzay, T.M.

    1993-01-01

    The support system designs for the Advanced Photon Source (APS) front ends are complete and will be installed in 1994. These designs satisfy the positioning and alignment requirements of the front end components installed inside the storage ring tunnel, including the photon beam position monitors, fixed masks, photon and safety shutters, filters, windows, and differential pumps. Other components include beam transport pipes and ion pumps. The designs comprise 3-point kinematic mounts and single axis supports to satisfy various multi-direction positioning requirements from course to ultra-precise. The confined space inside the storage ring tunnel has posed engineering challenges in the design of these devices, considering some components weigh as much as 500 kg. These challenges include designing for mobility during commissioning and initial alignment, mechanical and thermal stability, and precise low profile vertical and horizontal positioning. As a result, novel stages and kinematic mounts have emerged with modular and standard designs. This paper will discuss the diverse group of support systems, including specifications and performance data of the prototypes

  6. TDC for the front end architecture in the PANDA MVD

    Energy Technology Data Exchange (ETDEWEB)

    Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

    2014-07-01

    In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

  7. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  8. CMOS pixel sensor development for the ATLAS experiment at the High Luminosity-LHC

    Science.gov (United States)

    Rimoldi, M.

    2017-12-01

    The current ATLAS Inner Detector will be replaced with a fully silicon based detector called Inner Tracker (ITk) before the start of the High Luminosity-LHC project (HL-LHC) in 2026. To cope with the harsh environment expected at the HL-LHC, new approaches are being developed for pixel detectors based on CMOS technology. Such detectors can provide charge collection, analog amplification and digital processing in the same silicon wafer. The radiation hardness is improved thanks to multiple nested wells which give the embedded CMOS electronics sufficient shielding. The goal of this programme is to demonstrate that depleted CMOS pixels are suitable for high rate, fast timing and high radiation operation at the LHC . A number of alternative solutions have been explored and characterised. In this document, test results of the sensors fabricated in different CMOS processes are reported.

  9. Electrical characterization of thin edgeless N-on-p planar pixel sensors for ATLAS upgrades

    International Nuclear Information System (INIS)

    Bomben, M; Calderini, G; Chauveau, J; Marchiori, G; Bagolini, A; Boscardin, M; Giacomini, G; Zorzi, N; Bosisio, L; Rosa, A La

    2014-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. Because of its radiation hardness and cost effectiveness, the n-on-p silicon technology is a promising candidate for a large area pixel detector. The paper reports on the joint development, by LPNHE and FBK of novel n-on-p edgeless planar pixel sensors, making use of the active trench concept for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, and presenting some sensors' simulation results, a complete overview of the electrical characterization of the produced devices will be given

  10. The phase-II ATLAS pixel tracker upgrade: layout and mechanics.

    CERN Document Server

    Sharma, Abhishek; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment will upgrade its tracking detector during the Phase-II LHC shutdown, to better take advantage of the increased luminosity of the HL-LHC. The upgraded tracker will consist of silicon-strip modules surrounding a pixel detector, and will likely cover an extended eta range, perhaps as far as |eta|<4.0. A number of layout and supporting-structure options are being considered for the pixel detector, with the final choice expected to be made in early 2017. The proposed supporting structures are based on lightweight, highly-thermally-conductive carbon-based materials and are cooled by evaporative carbon dioxide. The various layouts will be described and a description of the supporting structures will be presented, along with results from testing of prototypes.

  11. Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

    Science.gov (United States)

    Vigani, L.; Bortoletto, D.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

    2018-02-01

    Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

  12. Study of prototypes of LFoundry active CMOS pixels sensors for the ATLAS detector

    CERN Document Server

    Vigani, L.; Ambroz, L.; Plackett, R.; Hemperek, T.; Rymaszewski, P.; Wang, T.; Krueger, H.; Hirono, T.; Caicedo Sierra, I.; Wermes, N.; Barbero, M.; Bhat, S.; Breugnon, P.; Chen, Z.; Godiot, S.; Pangaud, P.; Rozanov, A.

    2018-01-01

    Current high energy particle physics experiments at the LHC use hybrid silicon detectors, in both pixel and strip configurations, for their inner trackers. These detectors have proven to be very reliable and performant. Nevertheless, there is great interest in depleted CMOS silicon detectors, which could achieve a similar performance at lower cost of production. We present recent developments of this technology in the framework of the ATLAS CMOS demonstrator project. In particular, studies of two active sensors from LFoundry, CCPD_LF and LFCPIX, are shown.

  13. Slim edge studies, design and quality control of planar ATLAS IBL pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Wittig, Tobias

    2013-05-08

    One of the four large experiments at the LHC at CERN is the ATLAS detector, a multi purpose detector. Its pixel detector, composed of three layers, is the innermost part of the tracker. As it is closest to the interaction point, it represents a basic part of the track reconstruction. Besides the requested high resolution one main requirement is the radiation hardness. In the coming years the radiation damage will cause deteriorations of the detector performance. With the planned increase of the luminosity, especially after the upgrade to the High Luminosity LHC, this radiation damage will be even intensified. This circumstance necessitates a new pixel detector featuring improved radiation hard sensors and read-out chips. The present shutdown of the LHC is already utilized to insert an additional b-layer (IBL) into the existing ATLAS pixel detector. The current n-in-n pixel sensor design had to be adapted to the new read-out chip and the module specifications. The new stave geometry requests a reduction of the inactive sensor edge. In a prototype wafer production all modifications have been implemented. The sensor quality control was supervised which led to the decision of the final sensor thickness. In order to evaluate the performance of the sensor chip assemblies with an innovative slim edge design, they have been operated in test beam setups before and after irradiation. Furthermore, the quality control of the planar IBL sensor wafer production was supervised from the stage of wafer delivery to that before the flip chip process to ensure a sufficient amount of functional sensors for the module production.

  14. Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

    CERN Document Server

    Savic, Natascha

    2016-01-01

    In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023-2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more ra- diation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 {\\mu}m recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of th...

  15. Investigation of thin n-in-p planar pixel modules for the ATLAS upgrade

    International Nuclear Information System (INIS)

    Savic, N.; Beyer, J.; Rosa, A. La; Macchiolo, A.; Nisius, R.

    2016-01-01

    In view of the High Luminosity upgrade of the Large Hadron Collider (HL-LHC), planned to start around 2023–2025, the ATLAS experiment will undergo a replacement of the Inner Detector. A higher luminosity will imply higher irradiation levels and hence will demand more radiation hardness especially in the inner layers of the pixel system. The n-in-p silicon technology is a promising candidate to instrument this region, also thanks to its cost-effectiveness because it only requires a single sided processing in contrast to the n-in-n pixel technology presently employed in the LHC experiments. In addition, thin sensors were found to ensure radiation hardness at high fluences. An overview is given of recent results obtained with not irradiated and irradiated n-in-p planar pixel modules. The focus will be on n-in-p planar pixel sensors with an active thickness of 100 and 150 μm recently produced at ADVACAM. To maximize the active area of the sensors, slim and active edges are implemented. The performance of these modules is investigated at beam tests and the results on edge efficiency will be shown.

  16. Front-end electronics for the readout of CdZnTe sensors

    CERN Document Server

    Moraes, D; Rudge, A

    2006-01-01

    The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.

  17. Optimizing read-out of the NECTAr front-end electronics

    Science.gov (United States)

    Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

    2012-12-01

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  18. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  19. Optimizing read-out of the NECTAr front-end electronics

    International Nuclear Information System (INIS)

    Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C.L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

    2012-01-01

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  20. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

  1. Recent achievements of the ATLAS upgrade Planar Pixel Sensors R and D Project

    International Nuclear Information System (INIS)

    George, M

    2014-01-01

    After the foreseen upgrade of the LHC towards the HL-LHC, coming along with higher beam energies and increased peak luminosities, the experiments have to upgrade their detector systems to cope with the expected higher occupancies and radiation damages. In case of the ATLAS experiment a new Inner Tracker will be installed in this context. The ATLAS Planar Pixel Sensor R and D Project (PPS) is investigating the possibilities to cope with these new requirements, using planar pixel silicon sensors, working in a collaboration of 17 institutions and more than 80 scientists. Since the new Inner Tracker is supposed to have an active area on the order of 8 m 2 on the one side and has to withstand extreme irradiation on the other side, the PPS community is working on several approaches to reduce production costs, while increasing the radiation tolerance of the sensors. Another challenge is to produce sensors in such large quantities. During the production of the Insertable b-Layer (IBL) modules, the PPS community has proven to be able to produce a large scale production of planar silicon sensors with a high yield. For cost reduction reasons, it is desirable to produce larger sensors. There the PPS community is working on so called quad- and hex-modules, which have a size of four, respectively six FE-I4 readout chips. To cope with smaller radii and strict material budget requirements for the new pixel layers, developments towards sensors with small inactive areas are in the focus of research. Different production techniques, which even allow the production of sensors with active edges, have been investigated and the designs were qualified using lab and testbeam measurements. The short distance between the new innermost pixel layers and the interaction point, combined with the increase in luminosity, requires designs which are more radiation tolerant. Since charge collection on the one hand decreases with irradiation and on the other hand is not uniform within the pixel cells

  2. Tracking and b-tagging with pixel vertex detector in ATLAS experiment at LHC

    International Nuclear Information System (INIS)

    Vacavant, L.

    1997-06-01

    The capability of the ATLAS detector to tag b-jets is studied, using the impact parameter of charged tracks. High b-tagging performance is needed at LHC, especially during the first years of running, in order to see evidence of the Higgs boson if its mass lies between 80 and 120 GeV/c 2 . A pattern-recognition algorithm has been developed for this purpose, using a detailed simulation of the ATLAS inner detector. Track-finding starts from the pixel detector layers. A 'hyper-plane' concept allows the use of a simple tracking algorithm though the complex geometry. High track-finding efficiency and reconstruction quality ensure the discrimination of b-jets from other kinds of jets. After full simulation and reconstruction of H → bb-bar, H → gg, H → uu-bar, H → ss-bar and H → cc-bar events (m H = 100 GeV/c 2 ), the mean rejections achieved against non-b-jets for a 50% b-jet tagging efficiency are as follows: R g =39±5 R u = 60 ± 9 R s = 38 ± 5 R c = 9 ± 1 The analysis of data from the first radiation-hard pixel detector prototypes justifies the potential of these detectors for track-finding and high-precision impact parameter measurement at LHC. (author)

  3. Managing Front-End Innovation through Idea Markets at Novozymes

    DEFF Research Database (Denmark)

    Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank

    2013-01-01

    Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in which...... a relatively small number of highly motivated participants screened their colleagues' inventions through an "idea market." The idea competition fulfilled its goals of generating two ideas with high growth potential within a short time, uncovering and recombining old proposals that inventors had not previously...... been able to advance in the organization and focusing managerial attention on the selection process. The campaign is an effective tool to recombine existing knowledge that had not been utilized. The process demonstrated that asking participants to comment on proposals improves idea generation...

  4. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The paper examines...... into realisations. Inputs from different knowledge domains must be grappled with, both in terms of needing to be elucidated as well as synthesized, in the engineering design process. The paper argues that the existing research may be seen as a response to perceived difficulties in dealing with uncertain conditions...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

  5. Front-end readout system for PHENIX RICH

    International Nuclear Information System (INIS)

    Tanaka, Y.; Hara, H.; Ebisu, K.; Hibino, M.; Kametani, S.; Kikuchi, J.; Wintenberg, A.L.; Walker, J.W.; Franck, S.; Moscone, C.; Jones, J.P.; Young, G.R.; Matsumoto, T.; Sakaguchi, T.; Oyama, K.; Hamagaki, H.

    2000-01-01

    A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment

  6. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  7. Front-end electronics for H.E.P

    International Nuclear Information System (INIS)

    Hrisoho, A.

    1990-07-01

    A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

  8. Gravitational Reference Sensor Front-End Electronics Simulator for LISA

    International Nuclear Information System (INIS)

    Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; Zweifel, Peter; Giardini, Domenico; Ten Pierick, Jan

    2017-01-01

    At the ETH Zurich we are developing a modular simulator that provides a realistic simulation of the Front End Electronics (FEE) for LISA Gravitational Reference Sensor (GRS). It is based on the GRS FEE-simulator already implemented for LISA Pathfinder. It considers, in particular, the non-linearity and the critical details of hardware, such as the non-linear multiplicative noise caused by voltage reference instability, test mass charging and detailed actuation and sensing algorithms. We present the simulation modules, considering the above-mentioned features. Based on the ETH GRS FEE-simulator for LISA Pathfinder we aim to develop a modular simulator that provides a realistic simulation of GRS FEE for LISA. (paper)

  9. Electronic front-end for LHCb electromagnetic and hadronic calorimeters

    International Nuclear Information System (INIS)

    Beigbeder, Ch.

    2000-11-01

    The electronic front-end of the LHCb electromagnetic and hadronic calorimeters will be described. It consists of a 9U 32 channel board, each channel including shaper-integrator, 12 bit ADC and look-up tables allowing to code the transverse energy information both for readout and for the Level 0 trigger. The readout information is stored in a fixed latency followed by a derandomizer. The trigger information is processed further on the board by FPGA, performing channel addition and comparison to extract the highest transverse energy local cluster for further processing. The system is fully synchronous and allows to extract candidates for calorimetric trigger at every 40 MHz clock cycle. The operation and characteristics (noise, linearity etc.) of a prototype board will be described. (author)

  10. Cryogenic receiver front-end with sharp skirt characteristics

    Energy Technology Data Exchange (ETDEWEB)

    Narahashi, S [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Satoh, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Kawai, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Koizumi, D [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Nojima, T [Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Hokkaido 060-0808 (Japan)

    2006-05-15

    This paper presents an experimental cryogenic receiver front-end (CRFE) with sharp skirt characteristics for mobile base stations. The CRFE comprises a high-temperature superconducting filter, a cryogenic low-noise amplifier, and a highly reliable cryostat that is very compact. The major characteristics of the proposed CRFE measured at 70 K are a centre frequency of 1.95 GHz, passband width of 20 MHz, sharp selectivity of 20 dB/100 kHz, 1.4 dB ripple, 31.3 dB average passband gain, and average passband equivalent noise temperature of 47.9 K. The CRFE weighs 19 kg and occupies 35 l. Random failure of the cryostat is also evaluated by a continuous operation test using four identical ones simultaneously. The cryostat used in the CRFE has a high reliability level of over five years of continuous maintenance-free operation.

  11. Development of a serial powering scheme and a versatile characterization system for the ATLAS pixel detector upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Filimonov, Viacheslav

    2017-08-15

    In order to increase the probability of new discoveries the LHC will be upgraded to the HL-LHC. The upgrade of the ATLAS detector is an essential part of this program. The entire ATLAS tracking system will be replaced by an all-silicon detector called Inner Tracker (ITk) which should be able to withstand the increased luminosity of 5 x 10{sup 34} cm{sup -2}s{sup -1}. The work presented in this thesis is focused on the ATLAS ITk pixel detector upgrade. Advanced silicon pixel detectors will be an essential part of the ITk pixel detector where they will be used for tracking and vertexing. Characterization of the pixel detectors is one of the required tasks for a successful ATLAS tracker upgrade. Therefore, the work presented in this thesis includes the development of a versatile and modular test system for advanced silicon pixel detectors for the HL-LHC. The performance of the system is verified. Single and quad FE-I4 modules functionalities are characterized with the developed system. The reduction of the material budget of the ATLAS ITk pixel detector is essential for a successful operation at high luminosity. Therefore, a low mass, efficient power distribution scheme to power detector modules (serial powering scheme) is investigated as well in the framework of this thesis. A serially powered pixel detector prototype is built with all the components that are needed for current distribution, data transmission, sensor biasing, bypassing and redundancy in order to prove the feasibility of implementing the serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules are made with the help of the developed readout system.

  12. Development of a serial powering scheme and a versatile characterization system for the ATLAS pixel detector upgrade

    International Nuclear Information System (INIS)

    Filimonov, Viacheslav

    2017-08-01

    In order to increase the probability of new discoveries the LHC will be upgraded to the HL-LHC. The upgrade of the ATLAS detector is an essential part of this program. The entire ATLAS tracking system will be replaced by an all-silicon detector called Inner Tracker (ITk) which should be able to withstand the increased luminosity of 5 x 10 34 cm -2 s -1 . The work presented in this thesis is focused on the ATLAS ITk pixel detector upgrade. Advanced silicon pixel detectors will be an essential part of the ITk pixel detector where they will be used for tracking and vertexing. Characterization of the pixel detectors is one of the required tasks for a successful ATLAS tracker upgrade. Therefore, the work presented in this thesis includes the development of a versatile and modular test system for advanced silicon pixel detectors for the HL-LHC. The performance of the system is verified. Single and quad FE-I4 modules functionalities are characterized with the developed system. The reduction of the material budget of the ATLAS ITk pixel detector is essential for a successful operation at high luminosity. Therefore, a low mass, efficient power distribution scheme to power detector modules (serial powering scheme) is investigated as well in the framework of this thesis. A serially powered pixel detector prototype is built with all the components that are needed for current distribution, data transmission, sensor biasing, bypassing and redundancy in order to prove the feasibility of implementing the serial powering scheme in the ITk. Detailed investigations of the electrical performance of the detector prototype equipped with FE-I4 quad modules are made with the help of the developed readout system.

  13. Highly integrated front-end electronics for spaceborne fluxgate sensors

    International Nuclear Information System (INIS)

    Magnes, W; Valavanoglou, A; Hagen, C; Jernej, I; Baumjohann, W; Oberst, M; Hauer, H; Neubauer, H; Pierce, D; Means, J; Falkner, P

    2008-01-01

    Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm 2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability ( −1 MFA temperature, −1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm 2 mg −1

  14. A software-radio front-end for microwave applications

    Directory of Open Access Journals (Sweden)

    M. Streifinger

    2003-01-01

    Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

  15. 3D silicon pixel detectors for the ATLAS Forward Physics experiment

    International Nuclear Information System (INIS)

    Lange, J.; Cavallaro, E.; Grinstein, S.; Paz, I. López

    2015-01-01

    The ATLAS Forward Physics (AFP) project plans to install 3D silicon pixel detectors about 210 m away from the interaction point and very close to the beamline (2–3 mm). This implies the need of slim edges of about 100–200 μm width for the sensor side facing the beam to minimise the dead area. Another challenge is an expected non-uniform irradiation of the pixel sensors. It is studied if these requirements can be met using slightly-modified FE-I4 3D pixel sensors from the ATLAS Insertable B-Layer production. AFP-compatible slim edges are obtained with a simple diamond-saw cut. Electrical characterisations and beam tests are carried out and no detrimental impact on the leakage current and hit efficiency is observed. For devices without a 3D guard ring a remaining insensitive edge of less than 15 μm width is found. Moreover, 3D detectors are non-uniformly irradiated up to fluences of several 10 15 n eq /cm 2 with either a focussed 23 GeV proton beam or a 23 MeV proton beam through holes in Al masks. The efficiency in the irradiated region is found to be similar to the one in the non-irradiated region and exceeds 97% in case of favourable chip-parameter settings. Only in a narrow transition area at the edge of the hole in the Al mask, a significantly lower efficiency is seen. A follow-up study of this effect using arrays of small pad diodes for position-resolved dosimetry via the leakage current is carried out

  16. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Gabrielli, Alessandro; The ATLAS collaboration; Balbi, Gabriele; Bindi, Marcello; Chen, Shaw-pin; Falchieri, Davide; Flick, Tobias; Hauck, Scott Alan; Hsu, Shih-Chieh; Kretz, Moritz; Kugel, Andreas; Lama, Luca; Travaglini, Riccardo; Wensing, Marius; ATLAS Pixel Collaboration

    2015-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBL ROD firmware development was three-fold: keeping as much of the Pixel ROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBL DAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBL ROD data pat...

  17. Firmware development and testing of the ATLAS Pixel Detector / IBL ROD card

    CERN Document Server

    Balbi, G; The ATLAS collaboration; Gabrielli, A; Lama, L; Travaglini, R; Backhaus, M; Bindi, M; Chen, S-P; Flick, T; Kretz, M; Kugel, A; Wensing, M

    2014-01-01

    The ATLAS Experiment is reworking and upgrading systems during the current LHC shut down. In particular, the Pixel detector has inserted an additional inner layer called Insertable B-Layer (IBL). The Readout-Driver card (ROD), the Back-of-Crate card (BOC), and the S-Link together form the essential frontend data path of the IBL’s off-detector DAQ system. The strategy for IBLROD firmware development was three-fold: keeping as much of the PixelROD datapath firmware logic as possible, employing a complete new scheme of steering and calibration firmware and designing the overall system to prepare for a future unified code version integrating IBL and Pixel layers. Essential features such as data formatting, frontend-specific error handling, and calibration are added to the ROD data path. An IBLDAQ testbench using realistic frontend chip model was created to serve as an initial framework for full offline electronic system simulation. In this document, major firmware achievements concerning the IBLROD data path im...

  18. System test and noise performance studies at the ATLAS pixel detector

    International Nuclear Information System (INIS)

    Weingarten, J.

    2007-09-01

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  19. submitter Development of the readout for the IBL upgrade project of the ATLAS Pixel Detector

    CERN Document Server

    Krieger, Nina

    The LHC luminosity is upgraded in several phases until 2022. The resulting higher occupancy degrades the detector performance of the current Pixel Detector. To provide a good performance during the LHC luminosity upgrade, a fourth pixel layer is inserted into the existing ATLAS Pixel Detector. A new FE-I4 readout chip and a new data acquisition chain are required to cope with the higher track rate and the resulting increased bandwidth. Among others, this includes a new readout board: the IBL ROD. One component of this board is the DSP which creates commands for the FE-I4 chip and has to be upgraded as well. In this thesis, the first tests of the IBL ROD prototype are presented. A correct communication of the DSP to its external memory is verified. Moreover, the implementations for an IBL DSP code are described and tested. This includes the first configuration of the FE-I4 with an IBL ROD. In addition, a working communication with the Histogrammer SDRAM and the Input FIFO on the IBL ROD are demonstrated.

  20. First MCM-D modules for the b-physics layer of the ATLAS Pixel Detector

    CERN Document Server

    Basken, O; Ehrmann, O; Gerlach, P; Grah, C; Gregor, I M; Linder, C; Meuser, S; Richardson, J; Topper, M; Wolf, J

    2000-01-01

    The innermost layer (b-physics layer) of the ATLAS Pixel Detector will consist of modules based on MCM-D technology. Such a module consists of a sensor tile with an active area of 16.4 mm*60.4 mm, 16 read out ICs, each serving 24* 160 pixel unit cells, a module controller chip (MCC), an optical transceiver and the local signal interconnection and power distribution busses. We show a prototype of such a module with additional test pads on both sides. The outer dimensions of the final module will be 21.4 mm*67.8 mm. The extremely high wiring density, which is necessary to interconnect the read-out chips, was achieved using a thin film copper/photo-BCB process on the pixel array. The bumping of the read out chips was done using electroplating PbSn. All dice are then attached by flip-chip assembly to the sensor diodes and the local busses. The focus of this paper is the description of the first results of such MCM-D-type modules. (11 refs).

  1. System test and noise performance studies at the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Weingarten, J.

    2007-09-15

    The central component of the ATLAS Inner Tracker is the pixel detector. It consists of three barrel layers and three disk-layers in the end-caps in both forward directions. The innermost barrel layer is mounted at a distance of about 5 cm from the interaction region. With its very high granularity, truly two-dimensional hit information, and fast readout it is well suited to cope with the high densities of charged tracks, expected this close to the interaction region. The huge number of readout channels necessitates a very complex services infrastructure for powering, readout and safety. After a description of the pixel detector and its services infrastructure, key results from the system test at CERN are presented. Furthermore the noise performance of the pixel detector, crucial for high tracking and vertexing efficiencies, is studied. Measurements of the single-channel random noise are presented together with studies of common mode noise and measurements of the noise occupancy using a random trigger generator. (orig.)

  2. First experiences with the ATLAS pixel detector control system at the combined test beam 2004

    International Nuclear Information System (INIS)

    Imhaeuser, Martin; Becks, Karl-Heinz; Henss, Tobias; Kersten, Susanne; Maettig, Peter; Schultes, Joachim

    2006-01-01

    Detector control systems (DCS) include the readout, control and supervision of hardware devices as well as the monitoring of external systems like cooling system and the processing of control data. The implementation of such a system in the final experiment also has to provide the communication with the trigger and data acquisition system (TDAQ). In addition, conditions data which describe the status of the pixel detector modules and their environment must be logged and stored in a common LHC wide database system. At the combined test beam all ATLAS subdetectors were operated together for the first time over a longer period. To ensure the functionality of the pixel detector, a control system was set up. We describe the architecture chosen for the pixel DCS, the interfaces to hardware devices, the interfaces to the users and the performance of our system. The embedding of the DCS in the common infrastructure of the combined test beam and also its communication with surrounding systems will be discussed in some detail

  3. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  4. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  5. Studio di un algoritmo lineare di ricostruzione analogica della posizione per il rivelatore a pixel di ATLAS

    CERN Document Server

    Arelli-Maffioli, A; Troncon, C; Lari, T

    2007-01-01

    A detailed study of spatial resolution of Atlas pixel sensors prototypes was performed. Charge interpolation was used and allowed for a significant improvement with respect to digital resolution. A simplified algorithm for charge interpolation was developed. Its application to both unirradiated and irradiated sensors is presented and discussed.

  6. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  7. Front-end electronics for the Muon Portal project

    Energy Technology Data Exchange (ETDEWEB)

    Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M.C. [INAF, Osservatorio Astrofisico di Catania, Via S. Sofia 78, I-95123 Catania (Italy); Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D.G. [Università di Catania, Dipartimento di Fisica e Astronomia, and INFN, Sezione di Catania, Via S. Sofia 64, I-95123 Catania (Italy); Fallica, G.; Valvo, G. [ST-Microelectronics, Stradale V Primosole 50, Catania (Italy)

    2016-10-11

    The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

  8. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1992-01-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  9. Results of the SNS front end commissioning at Berkeley Lab

    International Nuclear Information System (INIS)

    Ratti, A.; Ayers, J.J.; Doolittle, L.; Greer, J.B.; Keller, R.; Lewis, S.; Lionberger, C.; Monroy, M.; Pruyn, J.; Staples, J.W.; Syversrude, D.; Thomae, R.; Virostek, S.; Aleksandrov, A.; Shea, T.; SNS Accelerator Physics Group; SNS Beam Diagnostics Collaboration

    2002-01-01

    The Front-End Systems (FES) for the Spallation Neutron Source (SNS) project comprise an rf-driven H - ion source, an electrostatic 2-lens LEBT, a 2.5 MeV RFQ, followed by a 14-quadrupole, 4-rebuncher MEBT including traveling-wave fast choppers. The nominal 2.5 MeV H - beam has a current of 38 mA at a repetition rate of 60 Hz and 1 ms pulse length, for a macro duty-factor of 6%, and is chopped at a rate of approximately 1 MHz with a mini duty-factor of 68%. The normalized rms beam emittance at the MEBT exit, matching the first tank of a 402.5 MHz Alvarez linac, is measured to be approximately 0.3 π mm mrad. Diagnostic elements include wire scanners, BPMs, fast current monitors, a slit-harp emittance device and RFQ field monitoring probes. The results of the beam commissioning and the operation of the RFQ and diagnostic instrumentation are reported. The entire FES was shut down at LBNL at the end of May 2002 and will be recommissioned at ORNL prior to installation of the drift-tube linac

  10. Front-end electronics and trigger systems - status and challenges

    International Nuclear Information System (INIS)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-01-01

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

  11. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  12. Solid-State Photomultiplier with Integrated Front End Electronics

    Science.gov (United States)

    Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

    2009-10-01

    The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

  13. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1991-07-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper we illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. We also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. We outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. We also present some of the difficulties encountered in applying these networks. (author) 13 figs., 9 refs

  14. Front-end electronics for the ALICE calorimeters

    CERN Document Server

    Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

    2010-01-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

  15. The LHCb front-end electronics and data acquisition system

    CERN Document Server

    Jost, B

    2000-01-01

    The LHCb experiment is the most recently approved of the four experiments under construction at CERN's LHC accelerator. It is a special purpose experiment designed to precisely measure the CP violation parameters in the B-B system and to study rare B-decays. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. We therefore decided to implement a four-level triggering scheme. The LHCb data acquisition (DAQ) system will have to cope with an average trigger rate of 40 kHz, after two levels of hardware triggers, and an average event size of 100 kB. Thus, an event-building network which can sustain an average bandwidth of 4 GB /s is required. A powerful software trigger farm will have to be installed to reduce the rate from 40 kHz to 100 Hz of events written for permanent storage. In this paper we will outline the general architectures of the front-end electronics and of the trigger and DAQ system and the readout protocols...

  16. Photodetectors and front-end electronics for the LHCb RICH upgrade

    Science.gov (United States)

    Cassina, L.; LHCb RICH

    2017-12-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

  17. Preliminary Results of 3D-DDTC Pixel Detectors for the ATLAS Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    La Rosa, Alessandro; /CERN; Boscardin, M.; /Fond. Bruno Kessler, Povo; Dalla Betta, G.-F.; /Trento U. /INFN, Trento; Darbo, G.; Gemme, C.; /INFN, Genoa; Pernegger, H.; /CERN; Piemonte, C.; /Fond. Bruno Kessler, Povo; Povoli, M.; /Trento U. /INFN, Trento; Ronchin, S.; /Fond. Bruno Kessler, Povo; Zoboli, A.; /Trento U. /INFN, Trento; Zorzi, N.; /Fond. Bruno Kessler, Povo; Bolle, E.; /Oslo U.; Borri, M.; /INFN, Turin /Turin U.; Da Via, C.; /Manchester U.; Dong, S.; /SLAC; Fazio, S.; /Calabria U.; Grenier, P.; /SLAC; Grinstein, S.; /Barcelona, IFAE; Gjersdal, H.; /Oslo U.; Hansson, P.; /SLAC; Huegging, F.; /Bonn U. /SLAC /INFN, Turin /Turin U. /Oslo U. /Bergen U. /Oslo U. /Prague, Tech. U. /Bonn U. /SUNY, Stony Brook /Bonn U. /SLAC

    2012-04-04

    3D Silicon sensors fabricated at FBK-irst with the Double-side Double Type Column (DDTC) approach and columnar electrodes only partially etched through p-type substrates were tested in laboratory and in a 1.35 Tesla magnetic field with a 180 GeV pion beam at CERN SPS. The substrate thickness of the sensors is about 200 {mu}m, and different column depths are available, with overlaps between junction columns (etched from the front side) and ohmic columns (etched from the back side) in the range from 110 {mu}m to 150 {mu}m. The devices under test were bump bonded to the ATLAS Pixel readout chip (FEI3) at SELEX SI (Rome, Italy). We report leakage current and noise measurements, results of functional tests with Am{sup 241} {gamma}-ray sources, charge collection tests with Sr90 {beta}-source and an overview of preliminary results from the CERN beam test.

  18. Alignment of the Pixel and SCT Modules for the 2004 ATLAS Combined Test Beam

    Energy Technology Data Exchange (ETDEWEB)

    ATLAS Collaboration; Ahmad, A.; Andreazza, A.; Atkinson, T.; Baines, J.; Barr, A.J.; Beccherle, R.; Bell, P.J.; Bernabeu, J.; Broklova, Z.; Bruckman de Renstrom, P.A.; Cauz, D.; Chevalier, L.; Chouridou, S.; Citterio, M.; Clark, A.; Cobal, M.; Cornelissen, T.; Correard, S.; Costa, M.J.; Costanzo, D.; Cuneo, S.; Dameri, M.; Darbo, G.; de Vivie, J.B.; Di Girolamo, B.; Dobos, D.; Drasal, Z.; Drohan, J.; Einsweiler, K.; Elsing, M.; Emelyanov, D.; Escobar, C.; Facius, K.; Ferrari, P.; Fergusson, D.; Ferrere, D.; Flick,, T.; Froidevaux, D.; Gagliardi, G.; Gallas, M.; Gallop, B.J.; Gan, K.K.; Garcia, C.; Gavrilenko, I.L.; Gemme, C.; Gerlach, P.; Golling, T.; Gonzalez-Sevilla, S.; Goodrick, M.J.; Gorfine, G.; Gottfert, T.; Grosse-Knetter, J.; Hansen, P.H.; Hara, K.; Hartel, R.; Harvey, A.; Hawkings, R.J.; Heinemann, F.E.W.; Henss, T.; Hill, J.C.; Huegging, F.; Jansen, E.; Joseph, J.; Unel, M. Karagoz; Kataoka, M.; Kersten, S.; Khomich, A.; Klingenberg, R.; Kodys, P.; Koffas, T.; Konstantinidis, N.; Kostyukhin, V.; Lacasta, C.; Lari, T.; Latorre, S.; Lester, C.G.; Liebig, W.; Lipniacka, A.; Lourerio, K.F.; Mangin-Brinet, M.; Marti i Garcia, S.; Mathes, M.; Meroni, C.; Mikulec, B.; Mindur, B.; Moed, S.; Moorhead, G.; Morettini, P.; Moyse, E.W.J.; Nakamura, K.; Nechaeva, P.; Nikolaev, K.; Parodi, F.; Parzhitskiy, S.; Pater, J.; Petti, R.; Phillips, P.W.; Pinto, B.; Poppleton, A.; Reeves, K.; Reisinger, I.; Reznicek, P.; Risso, P.; Robinson, D.; Roe, S.; Rozanov, A.; Salzburger, A.; Sandaker, H.; Santi, L.; Schiavi, C.; Schieck, J.; Schultes, J.; Sfyrla, A.; Shaw, C.; Tegenfeldt, F.; Timmermans, C.J.W.P.; Toczek, B.; Troncon, C.; Tyndel, M.; Vernocchi, F.; Virzi, J.; Anh, T. Vu; Warren, M.; Weber, J.; Weber, M.; Weidberg, A.R.; Weingarten, J.; Wellsf, P.S.; Zhelezkow, A.

    2008-06-02

    A small set of final prototypes of the ATLAS Inner Detector silicon tracking system(Pixel Detector and SemiConductor Tracker), were used to take data during the 2004 Combined Test Beam. Data were collected from runs with beams of different flavour (electrons, pions, muons and photons) with a momentum range of 2 to 180 GeV/c. Four independent methods were used to align the silicon modules. The corrections obtained were validated using the known momenta of the beam particles and were shown to yield consistent results among the different alignment approaches. From the residual distributions, it is concluded that the precision attained in the alignmentof the silicon modules is of the order of 5 mm in their most precise coordinate.

  19. Ongoing studies for the control system of a serially powered ATLAS pixel detector at the HL-LHC

    International Nuclear Information System (INIS)

    Kersten, S.; Püllen, L.; Zeitnitz, C.

    2016-01-01

    In terms of the phase-2 upgrade of the ATLAS detector, the entire inner tracker (ITk) of ATLAS will be replaced. This includes the pixel detector and the corresponding detector control system (DCS). The current baseline is a serial powering scheme of the detector modules. Therefore a new detector control system is being developed with emphasis on the supervision of serially powered modules. Previous chips had been designed to test the radiation hardness of the technology and the implementation of the modified I2C as well as the implementation of the logic of the CAN protocol. This included tests with triple redundant registers. The described chip is focusing on the implementation in a serial powering scheme. It was designed for laboratory tests, aiming for the proof of principle. The concept of the DCS for ATLAS pixel after the phase-2 upgrade is presented as well as the status of development including tests with the prototype ASIC

  20. Development of edgeless n-on-p planar pixel sensors for future ATLAS upgrades

    Energy Technology Data Exchange (ETDEWEB)

    Bomben, Marco, E-mail: marco.bomben@cern.ch [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Bagolini, Alvise; Boscardin, Maurizio [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); Bosisio, Luciano [Università di Trieste, Dipartimento di Fisica and INFN, Trieste (Italy); Calderini, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Dipartimento di Fisica E. Fermi, Università di Pisa, and INFN Sez. di Pisa, Pisa (Italy); Chauveau, Jacques [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Giacomini, Gabriele [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy); La Rosa, Alessandro [Section de Physique (DPNC), Université de Genève, Genève (Switzerland); Marchiori, Giovanni [Laboratoire de Physique Nucleaire et de Hautes Énergies (LPNHE) Paris (France); Zorzi, Nicola [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM) Povo di Trento (Italy)

    2013-06-01

    The development of n-on-p “edgeless” planar pixel sensors being fabricated at FBK (Trento, Italy), aimed at the upgrade of the ATLAS Inner Detector for the High Luminosity phase of the Large Hadron Collider (HL-LHC), is reported. A characterizing feature of the devices is the reduced dead area at the edge, achieved by adopting the “active edge” technology, based on a deep etched trench, suitably doped to make an ohmic contact to the substrate. The project is presented, along with the active edge process, the sensor design for this first n-on-p production and a selection of simulation results, including the expected charge collection efficiency after radiation fluence of 1×10{sup 15}n{sub eq}/cm{sup 2} comparable to those expected at HL-LHC (about ten years of running, with an integrated luminosity of 3000 fb{sup −1}) for the outer pixel layers. We show that, after irradiation and at a bias voltage of 500 V, more than 50% of the signal should be collected in the edge region; this confirms the validity of the active edge approach. -- Highlights: ► We conceive n-on-p edgeless planar silicon sensors. ► These sensors are aimed at the Phase-II of the ATLAS experiment. ► Simulations show sensors can be operated well in overdepletion. ► Simulations show the sensor capability to collect charge at the periphery. ► Simulations prove the above statements to be true even after irradiation.

  1. Characterization and Performance of Silicon n-in-p Pixel Detectors for the ATLAS Upgrades

    CERN Document Server

    Weigell, Philipp; Gallrapp, Christian; La Rosa, Alessandro; Macchiolo, Anna; Nisius, Richard; Pernegger, Heinz; Richter, Rainer

    2011-01-01

    The existing ATLAS Tracker will be at its functional limit for particle fluences of 10^15 neq/cm^2 (LHC). Thus for the upgrades at smaller radii like in the case of the planned Insertable B-Layer (IBL) and for increased LHC luminosities (super LHC) the development of new structures and materials which can cope with the resulting particle fluences is needed. N-in-p silicon devices are a promising candidate for tracking detectors to achieve these goals, since they are radiation hard, cost efficient and are not type inverted after irradiation. A n-in-p pixel production based on a MPP/HLL design and performed by CiS (Erfurt, Germany) on 300 \\mu m thick Float-Zone material is characterised and the electrical properties of sensors and single chip modules (SCM) are presented, including noise, charge collection efficiencies, and measurements with MIPs as well as an 241Am source. The SCMs are built with sensors connected to the current the ATLAS read-out chip FE-I3. The characterisation has been performed with the ATL...

  2. Simulation of the depletion voltage evolution of the ATLAS Pixel Detector

    CERN Document Server

    Beyer, Julien-christopher; The ATLAS collaboration

    2017-01-01

    The ATLAS Pixel detector has been operating since 2010 and consists of hybrid pixel modules where the sensitive elements are planar n-in-n sensors. In order to investigate and predict the evolution of the depletion voltage and of the leakage current in the different layers, a fully analytical implementation of the Hamburg model was derived. The parameters of the model, describing the dependence of the depletion voltage (U_depl) on fluence, temperature and time were tuned with a fit to the available measurements of Udepl in the last years of operation. A particular emphasis is put on the B-Layer, where the highest fluence has been accumulated up to now. A precise input of temperature and radiation dose is generated from the on-module temperature monitoring and the luminosity data. The analysis is then also extended to the Insertable B-Layer (IBL), installed at the end of Run-1, where we expect the fastest evolution of the radiation damage with luminosity, due to its closer position to the interaction point. Di...

  3. Three Generations of FPGA DAQ Development for the ATLAS Pixel Detector

    CERN Document Server

    AUTHOR|(CDS)2091916; Hsu, Shih-Chieh; Hauck, Scott Alan

    The Large Hadron Collider (LHC) at the European Center for Nuclear Research (CERN) tracks a schedule of long physics runs, followed by periods of inactivity known as Long Shutdowns (LS). During these LS phases both the LHC, and the experiments around its ring, undergo maintenance and upgrades. For the LHC these upgrades improve their ability to create data for physicists; the more data the LHC can create the more opportunities there are for rare events to appear that physicists will be interested in. The experiments upgrade so they can record the data and ensure the event won’t be missed. Currently the LHC is in Run 2 having completed the first LS of three. This thesis focuses on the development of Field-Programmable Gate Array (FPGA)-based readout systems that span across three major tasks of the ATLAS Pixel data acquisition (DAQ) system. The evolution of Pixel DAQ’s Readout Driver (ROD) card is presented. Starting from improvements made to the new Insertable B-Layer (IBL) ROD design, which was part of t...

  4. Fiber laser front end for high energy petawatt laser systems

    International Nuclear Information System (INIS)

    Dawson, J W; Messerly, M J; Phan, H; Mitchell, S; Drobshoff, A; Beach, R J; Siders, C; Lucianetti, A; Crane, J K; Barty, C J

    2006-01-01

    We are developing a fiber laser front end suitable for high energy petawatt laser systems on large glass lasers such as NIF. The front end includes generation of the pulses in a fiber mode-locked oscillator, amplification and pulse cleaning, stretching of the pulses to >3ns, dispersion trimming, timing, fiber transport of the pulses to the main laser bay and amplification of the pulses to an injection energy of 150 (micro)J. We will discuss current status of our work including data from packaged components. Design detail such as how the system addresses pulse contrast, dispersion trimming and pulse width adjustment and impact of B-integral on the pulse amplification will be discussed. A schematic of the fiber laser system we are constructing is shown in figure 1 below. A 40MHz packaged mode-locked fiber oscillator produces ∼1nJ pulses which are phase locked to a 10MHz reference clock. These pulses are down selected to 100kHz and then amplified while still compressed. The amplified compressed pulses are sent through a non-linear polarization rotation based pulse cleaner to remove background amplified spontaneous emission (ASE). The pulses are then stretched by a chirped fiber Bragg grating (CFBG) and then sent through a splitter. The splitter splits the signal into two beams. (From this point we follow only one beam as the other follows an identical path.) The pulses are sent through a pulse tweaker that trims dispersion imbalances between the final large optics compressor and the CFBG. The pulse tweaker also permits the dispersion of the system to be adjusted for the purpose of controlling the final pulse width. Fine scale timing between the two beam lines can also be adjusted in the tweaker. A large mode area photonic crystal single polarization fiber is used to transport the pulses from the master oscillator room to the main laser bay. The pulses are then amplified a two stage fiber amplifier to 150mJ. These pulses are then launched into the main amplifier

  5. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  6. Commissioning of the Atlas pixel detector and search of the Higgs boson in the tt-H, H → bb- channel with the Atlas experiment at the LHC

    International Nuclear Information System (INIS)

    Aad, G.

    2009-09-01

    The global fit of Higgs boson quantum contributions to the electroweak experimental observables, computed within the Standard Model, favors a light Higgs boson with a mass of m H = 90 -27 +36 GeV, on the edge of the 95% Confidence Level region excluded by LEP. Finding a light Higgs boson at LHC is experimentally difficult and several channels with various signatures will be sought for. The associated production of the Higgs boson with a pair of top quarks, with the subsequent decay of the Higgs boson into b-quark pairs (dominant for m H <135 GeV), is one of the channels considered. This channel opens the possibility of measuring the top and b-quark Yukawa couplings. The potential of the ATLAS detector to observe this channel is described. Several ingredients are crucial: the reconstruction of the top-anti-top system with a high-purity, excellent b-tagging capabilities and good knowledge of the tt-bar+jets background. The pixel detector is the most important ATLAS sub-detectors for tagging b -jets. The ATLAS detector was commissioned with cosmic muon rays in autumn 2008. The pixel detector dead channels, calibration constants and slow control informations are described for this period. A detailed study about pixel noise determination and suppression is presented. Finally, the pixel detection efficiency is measured using cosmic muon rays. (author)

  7. Mesure des champs de radiation dans le detecteur ATLAS et sa caverne avec les detecteurs au silicium a pixels ATLAS-MPX

    Science.gov (United States)

    Bouchami, Jihene

    The LHC proton-proton collisions create a hard radiation environment in the ATLAS detector. In order to quantify the effects of this environment on the detector performance and human safety, several Monte Carlo simulations have been performed. However, direct measurement is indispensable to monitor radiation levels in ATLAS and also to verify the simulation predictions. For this purpose, sixteen ATLAS-MPX devices have been installed at various positions in the ATLAS experimental and technical areas. They are composed of a pixelated silicon detector called MPX whose active surface is partially covered with converter layers for the detection of thermal, slow and fast neutrons. The ATLAS-MPX devices perform real-time measurement of radiation fields by recording the detected particle tracks as raster images. The analysis of the acquired images allows the identification of the detected particle types by the shapes of their tracks. For this aim, a pattern recognition software called MAFalda has been conceived. Since the tracks of strongly ionizing particles are influenced by charge sharing between adjacent pixels, a semi-empirical model describing this effect has been developed. Using this model, the energy of strongly ionizing particles can be estimated from the size of their tracks. The converter layers covering each ATLAS-MPX device form six different regions. The efficiency of each region to detect thermal, slow and fast neutrons has been determined by calibration measurements with known sources. The study of the ATLAS-MPX devices response to the radiation produced by proton-proton collisions at a center of mass energy of 7 TeV has demonstrated that the number of recorded tracks is proportional to the LHC luminosity. This result allows the ATLAS-MPX devices to be employed as luminosity monitors. To perform an absolute luminosity measurement and calibration with these devices, the van der Meer method based on the LHC beam parameters has been proposed. Since the ATLAS

  8. Performance of irradiated thin n-in-p planar pixel sensors for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Savić, N.; Beyer, J.; Hiti, B.; Kramberger, G.; La Rosa, A.; Macchiolo, A.; Mandić, I.; Nisius, R.; Petek, M.

    2017-12-01

    The ATLAS collaboration will replace its tracking detector with new all silicon pixel and strip systems. This will allow to cope with the higher radiation and occupancy levels expected after the 5-fold increase in the luminosity of the LHC accelerator complex (HL-LHC). In the new tracking detector (ITk) pixel modules with increased granularity will implement to maintain the occupancy with a higher track density. In addition, both sensors and read-out chips composing the hybrid modules will be produced employing more radiation hard technologies with respect to the present pixel detector. Due to their outstanding performance in terms of radiation hardness, thin n-in-p sensors are promising candidates to instrument a section of the new pixel system. Recently produced and developed sensors of new designs will be presented. To test the sensors before interconnection to chips, a punch-through biasing structure was implemented. Its design was optimized to decrease the possible tracking efficiency losses observed. After irradiation, they were caused by the punch-through biasing structure. A sensor compatible with the ATLAS FE-I4 chip with a pixel size of 50×250 μm2, subdivided into smaller pixel implants of 30×30 μm2 size was designed to investigate the performance of the 50×50 μm2 pixel cells foreseen for the HL-LHC. Results on sensor performance of 50×250 and 50×50 μm2 pixel cells in terms of efficiency, charge collection and electric field properties are obtained with beam tests and the Transient Current Technique.

  9. Front-End Electronics in calorimetry: from LHC to ILC

    International Nuclear Information System (INIS)

    De La Taille, Ch.

    2009-09-01

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

  10. Optimization of thin n-in-p planar pixel modules for the ATLAS upgrade at HL-LHC

    International Nuclear Information System (INIS)

    Macchiolo, A.; Beyer, J.; Rosa, A. La; Nisius, R.; Savic, N.

    2017-01-01

    The ATLAS experiment will undergo around the year 2025 a replacement of the tracker system in view of the high luminosity phase of the LHC (HL-LHC) with a new 5-layer pixel system. Thin planar pixel sensors are promising candidates to instrument the innermost region of the new pixel system, thanks to the reduced contribution to the material budget and their high charge collection efficiency after irradiation. The sensors of 50-150 μm thickness, interconnected to FE-I4 read-out chips, have been characterized with radioactive sources and beam tests. In particular active edge sensors have been investigated. The performance of two different versions of edge designs are compared: the first with a bias ring, and the second one where only a floating guard ring has been implemented. The hit efficiency at the edge has also been studied after irradiation at a fluence of 10 15  n eq /cm 2 . Highly segmented sensors will represent a challenge for the tracking in the forward region of the pixel system at HL-LHC. In order to reproduce the performance of 50x50 μm 2 pixels at high pseudo-rapidity values, FE-I4 compatible planar pixel sensors have been studied before and after irradiation in beam tests at high incidence angles with respect to the short pixel direction. Results on the hit efficiency in this configuration are discussed for different sensor thicknesses.

  11. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

  12. OMEGAPIX 3D integrated circuit prototype dedicated to the ATLAS upgrade Super LHC pixel project

    CERN Document Server

    Thienpont, D; de La Taille, C; Seguin-Moreau, N; Martin-Chassard, G; Guo b, Y

    2009-01-01

    In late 2008, an international consortium for development of vertically integrated (3D) readout electronics was created to explore features available from this technology. In this paper, the OMEGAPIX circuit is presented. It is the first front-end ASIC prototype designed at LAL in 3D technology. It has been submitted on May 2009. At first, a short reminder of 3D technology is presented. Then the IC design is explained: analogue tier, digital tier and testability.

  13. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  14. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    CERN Document Server

    Beimforde, Michael

    To extend the discovery potential of the experiments at the LHC accelerator a luminosity upgrade towards the super LHC (sLHC) with an up to ten-fold peak luminosity is planned. Within this thesis a new module concept was developed and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector.

  15. Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

    OpenAIRE

    Riegel, C; Backhaus, M; Hoorne, J W Van; Kugathasan, T; Musa, L; Pernegger, H; Riedler, P; Schaefer, D; Snoeys, W; Wagner, W

    2017-01-01

    A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS techn...

  16. Atlas pixel opto-board production and analysis and optolink simulation studies

    International Nuclear Information System (INIS)

    Nderitu, Simon Kirichu

    2007-01-01

    At CERN, a Large collider will collide protons at high energies. There are four experiments being built to study the particle properties from the collision. The ATLAS experiment is the largest. It has many sub detectors among which is the Pixel detector which is the innermost part. The Pixel detector has eighty million channels that have to be read out. An optical link is utilized for the read out. It has optical to electronic interfaces both on the detector and off the detector at the counting room. The component on the detector in called the opto-board. This work discusses the production testing of the opto-boards to be installed on the detector. A total of 300 opto-boards including spares have been produced. The production was done in three laboratories among which is the laboratory at the University of Wuppertal which had the responsibility of Post production testing of all the one third of the total opto-boards. The results are discussed in this work. The analysis of the results from the total production process has been done in the scope of this work as well. In addition to the production, a study by simulation of the communication links optical signal has been done. This has enabled an assessment of the sufficiency of the optical signal against the transmission attenuation and irradiation degradation. A System Test set up has been put up at Wuppertal to enhance general studies for better understanding of the Pixel read out system. Among other studies is the study of the timing parameters behavior of the System which has been done in this work and enhanced by a simulation. These parameters are namely the mark to space ratio and the fine delay and their relatedness during the optolink tuning. A bit error rate test based on the System has also been done which enabled assessment of the transmission quality utilizing the tools inbuilt in the System Test. These results have been presented in this work. (orig.)

  17. Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

    Science.gov (United States)

    Riegel, C.; Backhaus, M.; Van Hoorne, J. W.; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

    2017-01-01

    A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 1015 n/cm2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

  18. Radiation hardness and timing studies of a monolithic TowerJazz pixel design for the new ATLAS Inner Tracker

    International Nuclear Information System (INIS)

    Riegel, C.; Backhaus, M.; Hoorne, J.W. Van; Kugathasan, T.; Musa, L.; Pernegger, H.; Riedler, P.; Schaefer, D.; Snoeys, W.; Wagner, W.

    2017-01-01

    A part of the upcoming HL-LHC upgrade of the ATLAS Detector is the construction of a new Inner Tracker. This upgrade opens new possibilities, but also presents challenges in terms of occupancy and radiation tolerance. For the pixel detector inside the inner tracker, hybrid modules containing passive silicon sensors and connected readout chips are presently used, but require expensive assembly techniques like fine-pitch bump bonding. Silicon devices fabricated in standard commercial CMOS technologies, which include part or all of the readout chain, are also investigated offering a reduced cost as they are cheaper per unit area than traditional silicon detectors. If they contain the full readout chain, as for a fully monolithic approach, there is no need for the expensive flip-chip assembly, resulting in a further cost reduction and material savings. In the outer pixel layers of the ATLAS Inner Tracker, the pixel sensors must withstand non-ionising energy losses of up to 10 15 n/cm 2 and offer a timing resolution of 25 ns or less. This paper presents test results obtained on a monolithic test chip, the TowerJazz 180nm Investigator, towards these specifications. The presented program of radiation hardness and timing studies has been launched to investigate this technology's potential for the new ATLAS Inner Tracker.

  19. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    International Nuclear Information System (INIS)

    Püllen, Lukas; Boek, Jennifer; Kersten, Susanne; Kind, Peter; Mättig, Peter; Zeitnitz, Christian

    2013-01-01

    In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerator's instantaneous luminosity by a factor of 5 and the integrated luminosity by a factor of 10. In the context of this upgrade, the inner detector (including the pixel detector) of the ATLAS experiment will be replaced. This new pixel detector requires a specific control system which complies with strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4×4 DCS chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub-micron technology. We present results from reliability measurements under irradiation from new prototypes of components for the DCS network.

  20. Prototypes for components of a control system for the ATLAS pixel detector at the HL-LHC

    International Nuclear Information System (INIS)

    Boek, J; Kersten, S; Kind, P; Mättig, P; Püllen, L; Zeitnitz, C

    2013-01-01

    In the years around 2020 an upgrade of the LHC to the HL-LHC is scheduled, which will increase the accelerators luminosity by a factor of 10. In the context of this upgrade, the inner detector of the ATLAS experiment will be replaced entirely including the pixel detector. This new pixel detector requires a specific control system which complies with the strict requirements in terms of radiation hardness, material budget and space for the electronics in the ATLAS experiment. The University of Wuppertal is developing a concept for a DCS (Detector Control System) network consisting of two kinds of ASICs. The first ASIC is the DCS Chip which is located on the pixel detector, very close to the interaction point. The second ASIC is the DCS Controller which is controlling 4x4 DCS Chips from the outer regions of ATLAS via differential data lines. Both ASICs are manufactured in 130 nm deep sub micron technology. We present results from measurements from new prototypes of components for the DCS network.

  1. Radiation tests of photodiodes for the ATLAS SCT and PIXEL opto- links

    CERN Document Server

    Hou, L S; Lee, S C; Su, D S; Teng, P K

    2005-01-01

    In previous research, epitaxial Si PIN photodiodes produced by Centronic which will be used in the ATLAS semiconductor tracker have been irradiated with 1 MeV neutrons and 24 GeV protons with fluences up to an equivalent of $10^{15}$ 1 MeV neutrons (1,2) . In this work 30 MeV proton beams were used to irradiate Centronic and Truelight epitaxial Si PIN diodes with accumulated fluences of up to 2.1 multiplied by $10^{14}$-30 MeV p $cm^{-2}$, an equivalent of 5.7 multiplied by $10^{14} cm^{-2}$ 1 MeV neutrons, to reach the pixel radiation environment. The responsivity was measured with different levels of fluence in order to study the responsivity behaviour of two different types of photodiodes. The responsivity behaviour of these two photodiodes was similar: a linear degradation at large fluences, greater than $10^{14}$ 30 MeV p $cm^{-2}$, but with different slopes. The response of the Centronic PIN diode showed a degradation to 73% after a proton fluence of $10^{13}$ p $cm^{-2}$ of 30 MeV and a linear degradat...

  2. Submission of the First Full Scale Prototype Chip for Upgraded ATLAS Pixel Detector at LHC, FE-I4A

    CERN Document Server

    Barbero, M; The ATLAS collaboration; Beccherle, R; Darbo, G; Dube, S; Elledge, D; Fleury, J; Fougeron, D; Garcia-Sciveres, M; Gensolen, F; Gnani, D; Gromov, V; Jensen, F; Hemperek, T; Karagounis, M; Kluit, R; Kruth, A; Mekkaoui, A; Menouni, M; Schipper, JD; Wermes, N; Zivkovic, V

    2010-01-01

    A new ATLAS pixel chip FE-I4 is being developed for use in upgraded LHC luminosity environments, including the near-term Insertable B-Layer (IBL) upgrade. FE-I4 is designed in a 130nm CMOS technology, presenting advantages in terms of radiation tolerance and digital logic density compared to the 250nm CMOS technology used for the current ATLAS pixel IC, FE-I3. The FE-I4 architecture is based on an array of 80x336 pixels, each 50x250um^2, consisting of analog and digital sections. In the summer 2010, a first full scale prototype FE-I4A was submitted for an engineering run. This IC features the full scale pixel array as well as the complex periphery of the future full-size FE-I4. The FE-I4A contains also various extra test features which should prove very useful for the chip characterization, but deviate from the needs for standard operation of the final FE-I4 for IBL. In this paper, focus will be brought to the various features implemented in the FE-I4A submission, while also underlining the main differences b...

  3. Active Pixel Sensors in ams H18/H35 HV-CMOS Technology for the ATLAS HL-LHC Upgrade

    CERN Document Server

    Ristic, Branislav

    2016-09-21

    Deep sub micron HV-CMOS processes offer the opportunity for sensors built by industry standard techniques while being HV tolerant, making them good candidates for drift-based, fast collecting, thus radiation-hard pixel detectors. For the upgrade of the ATLAS Pixel Detector towards the HL-LHC requirements, active pixel sensors in HV-CMOS technology were investigated. These implement amplifier and discriminator stages directly in insulating deep n-wells, which also act as collecting electrodes. The deep n-wells allow for bias voltages up to 150V leading to a depletion depth of several 10um. Prototype sensors in the ams H18 180nm and H35 350nm HV-CMOS processes have been manufactured, acting as a potential drop-in replacement for the current ATLAS Pixel sensors, thus leaving higher level processing such as trigger handling to dedicated read-out chips. Sensors were thoroughly tested in lab measurements as well as in testbeam experiments. Irradiation with X-rays and protons revealed a tolerance to ionizing doses o...

  4. Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

    International Nuclear Information System (INIS)

    Nellist, C.; Dinu, N.; Gkougkousis, E.; Lounis, A.

    2015-01-01

    The LHC accelerator complex will be upgraded between 2020–2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented

  5. Measurements and TCAD simulation of novel ATLAS planar pixel detector structures for the HL-LHC upgrade

    CERN Document Server

    INSPIRE-00304438; Gkougkousis, E.; Lounis, A.

    2015-01-01

    The LHC accelerator complex will be upgraded between 2020-2022, to the High-Luminosity-LHC, to considerably increase statistics for the various physics analyses. To operate under these challenging new conditions, and maintain excellent performance in track reconstruction and vertex location, the ATLAS pixel detector must be substantially upgraded and a full replacement is expected. Processing techniques for novel pixel designs are optimised through characterisation of test structures in a clean room and also through simulations with Technology Computer Aided Design (TCAD). A method to study non-perpendicular tracks through a pixel device is discussed. Comparison of TCAD simulations with Secondary Ion Mass Spectrometry (SIMS) measurements to investigate the doping profile of structures and validate the simulation process is also presented.

  6. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    Million, D.L.

    1983-05-01

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  7. 10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

    International Nuclear Information System (INIS)

    Fan Chao; Jiao Shilong; Wu Yunfeng; Ye Yutang; Chen Tangsheng; Yang Lijie; Feng Ou

    2009-01-01

    A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fabricated based on the Φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simulation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50 x 50 μm 2 . The whole chip has an area of 1511 x 666 μm 2 . The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950 x 1910 μm 2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 mVpp.

  8. 10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Fan Chao; Jiao Shilong; Wu Yunfeng; Ye Yutang [School of Opto-Electronic Information, UESTC, Chengdu 610054 (China); Chen Tangsheng; Yang Lijie; Feng Ou, E-mail: fanchao41@126.co [Nanjing Electronic Devices Institute, Nanjing 210016 (China)

    2009-10-15

    A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fabricated based on the {Phi}-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simulation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/{mu}m and a photosensitive area of 50 x 50 {mu}m{sup 2}. The whole chip has an area of 1511 x 666 {mu}m{sup 2}. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950 x 1910 {mu}m{sup 2} and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 mVpp.

  9. Terahertz performance of quasioptical front-ends with a hotelectron bolometer

    International Nuclear Information System (INIS)

    Semenov, A; Richter, H; Guenther, B; Huebers, H-W; Karamarkovic, J

    2006-01-01

    We present terahertz performance of quasioptical front-ends consisting of a hotelectron bolometer imbedded in a planar feed antenna and integrated with an immersion lens. The impedance and radiation pattern of the log-spiral and double-slot planar feeds are evaluated using the method of moments; the collimating action of the lens is modelled using the physical optics. The total efficiency of the front-ends is computed taking into account frequency dependent impedance of the bolometer. Measured performance of the front-ends qualifies the simulation technique as a reliable tool for the design of terahertz receivers

  10. Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

    1994-01-01

    In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

  11. Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

    Science.gov (United States)

    Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

    2017-12-01

    Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

  12. The upgraded Pixel Detector of the ATLAS Experiment for Run-II at the Large Hadron Collider

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00407702

    2016-01-01

    The Pixel Detector of the ATLAS experiment has shown excellent performance during the whole Run-1 of the LHC. Taking advantage of the detector development period 2013 – 2014, the detector was extracted from the experiment and brought to surface to equip it with new service panels and to repair modules furthermore this helped with the installation of the Insertable B-Layer (IBL), fourth layer of pixel, installed in between the existing Pixel Detector and a new beam-pipe at a radius of 3.3 cm. To cope with the high radiation and increased pixel occupancy due to the proximity to the interaction point, two different silicon sensor technologies (planar and 3D) have been used. A new readout chip has been designed with CMOS 130nm technology with larger area, smaller pixel size and faster readout capability. Dedicated design features in combination with a new composite material were considered and used in order to reduce the material budget of the support structure while keeping the optimal thermo-mechanical perfor...

  13. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

  14. Single-current-sensor-based active front-end-converter-fed four ...

    Indian Academy of Sciences (India)

    Joseph Kiran Banda

    Keywords. Field-oriented control; vector control of induction motor; active front end converter; power factor correction .... sinusoidal three-phase input currents applied to the stator. ... with necessary feed-forward terms are employed to control.

  15. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

    1992-01-01

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  16. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  17. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  18. Installation and testing of the 112 boards for the front-end electronics.

    CERN Multimedia

    2006-01-01

    Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

  19. Optical Parametric Chirped-Pulse Amplifier as the Front End for the OMEGA EP Laser Chain

    International Nuclear Information System (INIS)

    Bagnoud, V.; Begishev, I.A.; Guardalben, M.J.; Keegan, J.; Puth, J.; Waxer, L.J.; Zuegel, J.D.

    2004-01-01

    A 145-mJ optical parametric amplifier has been developed as a front-end source prototype for the OEMGA EP laser chain. The system definition is presented together with experimental results that show 30% conversion efficiency

  20. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999,......-oriented longitudinal case study of a Danish pharmaceutical company. The findings and key learnings from the study are presented as propositions of how innovation strategies can be applied to actively facilitate FEI and with measurable results.......Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999...

  1. Silicon sensor technologies for ATLAS IBL upgrade

    CERN Document Server

    Grenier, P; The ATLAS collaboration

    2011-01-01

    New pixel sensors are currently under development for ATLAS Upgrades. The first upgrade stage will consist in the construction of a new pixel layer that will be installed in the detector during the 2013 LHC shutdown. The new layer (Insertable-B-Layer, IBL) will be inserted between the inner most layer of the current pixel detector and the beam pipe at a radius of 3.2cm. The expected high radiation levels require the use of radiation hard technology for both the front-end chip and the sensor. Two different pixel sensor technologies are envisaged for the IBL. The sensor choice will occur in July 2011. One option is developed by the ATLAS Planar Pixel Sensor (PPS) Collaboration and is based on classical n-in-n planar silicon sensors which have been used for the ATLAS Pixel detector. For the IBL, two changes were required: The thickness was reduced from 250 um to 200 um to improve the radiation hardness. In addition, so-called "slim edges" were designed to reduce the inactive edge of the sensors from 1100 um to o...

  2. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  3. Front end embedded microprocessors in the JET computer-based control system, past, present and future

    International Nuclear Information System (INIS)

    Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

    1987-01-01

    A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

  4. A 500μW 5Mbps ULP super-regenerative RF front-end

    NARCIS (Netherlands)

    Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

    2010-01-01

    This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

  5. Integrated X-band FMCW front-end in SiGe BiCMOS

    NARCIS (Netherlands)

    Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

    2010-01-01

    An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

  6. A study on the front-end VME system of BEPC II

    International Nuclear Information System (INIS)

    Wang Chunhong

    2004-01-01

    The front-end VME system is not only the heart of the control system, but also a real-time system. This paper describes the component of the front-end VME (Versa Module Eurocard) system including control computer and some related I/O modules. Particularly, the authors present a best solution for the problems about Vx-Works kernel and BSP running on MVME5100. This is a fundamental setup of the BEPC II control system. (author)

  7. The hybridized front end electronics of the Central Drift Chamber in the Stanford Linear Collider Detector

    International Nuclear Information System (INIS)

    Lo, C.C.; Kirsten, F.A.; Nakamura, M.

    1987-10-01

    In order to accommodate the high packaging density requirements for the front end electronics of the Central Drift Chamber (CDC) in the SLAC Linear Collider Detector (SLD), the CDC front end electronics has been hybridized. The hybrid package contains eight channels of amplifiers together with all the associated circuits for calibration, event recognition and power economy switching functions. A total of 1280 such hybrids are used in the CDC

  8. Radiological and environmental surveillance in front-end fuel cycle facilities

    International Nuclear Information System (INIS)

    Khan, A.H.; Sahoo, S.K.; Tripathi, R.M.

    2004-01-01

    This paper describes the occupational and environmental radiological safety measures associated with the operations of front end nuclear fuel cycle. Radiological monitoring in the facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised

  9. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    International Nuclear Information System (INIS)

    Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

    2016-01-01

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  10. General design of the layout for new undulator-only beamline front ends

    International Nuclear Information System (INIS)

    Shu Deming; Ramanathan, Mohan; Kuzay, Tuncer M.

    2001-01-01

    A great majority of the Advanced Photon Source (APS) users have chosen an undulator as the only source for their insertion device beamline. Compared with a wiggler source, the undulator source has a much smaller horizontal divergence, providing us with an opportunity to optimize the beamline front-end design further. In this paper, the particular designs and specifications, as well as the optical and bremsstrahlung ray-tracing analysis of the new APS front ends for undulator-only operation are presented

  11. Depleted fully monolithic CMOS pixel detectors using a column based readout architecture for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Wang, T.; Barbero, M.; Berdalovic, I.; Bespin, C.; Bhat, S.; Breugnon, P.; Caicedo, I.; Cardella, R.; Chen, Z.; Degerli, Y.; Egidos, N.; Godiot, S.; Guilloux, F.; Hemperek, T.; Hirono, T.; Krüger, H.; Kugathasan, T.; Hügging, F.; Marin Tobon, C. A.; Moustakas, K.; Pangaud, P.; Schwemling, P.; Pernegger, H.; Pohl, D.-L.; Rozanov, A.; Rymaszewski, P.; Snoeys, W.; Wermes, N.

    2018-03-01

    Depleted monolithic active pixel sensors (DMAPS), which exploit high voltage and/or high resistivity add-ons of modern CMOS technologies to achieve substantial depletion in the sensing volume, have proven to have high radiation tolerance towards the requirements of ATLAS in the high-luminosity LHC era. DMAPS integrating fast readout architectures are currently being developed as promising candidates for the outer pixel layers of the future ATLAS Inner Tracker, which will be installed during the phase II upgrade of ATLAS around year 2025. In this work, two DMAPS prototype designs, named LF-Monopix and TJ-Monopix, are presented. LF-Monopix was fabricated in the LFoundry 150 nm CMOS technology, and TJ-Monopix has been designed in the TowerJazz 180 nm CMOS technology. Both chips employ the same readout architecture, i.e. the column drain architecture, whereas different sensor implementation concepts are pursued. The paper makes a joint description of the two prototypes, so that their technical differences and challenges can be addressed in direct comparison. First measurement results for LF-Monopix will also be shown, demonstrating for the first time a fully functional fast readout DMAPS prototype implemented in the LFoundry technology.

  12. Thin n-in-p planar pixel sensors and active edge sensors for the ATLAS upgrade at HL-LHC

    International Nuclear Information System (INIS)

    Terzo, S; Macchiolo, A; Nisius, R; Paschen, B

    2014-01-01

    Silicon pixel modules employing n-in-p planar sensors with an active thickness of 200 μm, produced at CiS, and 100-200 μm thin active/slim edge sensor devices, produced at VTT in Finland have been interconnected to ATLAS FE-I3 and FE-I4 read-out chips. The thin sensors are designed for high energy physics collider experiments to ensure radiation hardness at high fluences. Moreover, the active edge technology of the VTT production maximizes the sensitive region of the assembly, allowing for a reduced overlap of the modules in the pixel layer close to the beam pipe. The CiS production includes also four chip sensors according to the module geometry planned for the outer layers of the upgraded ATLAS pixel detector to be operated at the HL-LHC. The modules have been characterized using radioactive sources in the laboratory and with high precision measurements at beam tests to investigate the hit efficiency and charge collection properties at different bias voltages and particle incidence angles. The performance of the different sensor thicknesses and edge designs are compared before and after irradiation up to a fluence of 1.4 × 10 16 n eq /cm 2

  13. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. ...

  14. A Parallel FPGA Implementation for Real-Time 2D Pixel Clustering for the ATLAS Fast TracKer Processor

    CERN Document Server

    Sotiropoulou, C-L; The ATLAS collaboration; Annovi, A; Beretta, M; Kordas, K; Nikolaidis, S; Petridou, C; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. T...

  15. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    Science.gov (United States)

    Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

    2007-01-01

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

  16. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    International Nuclear Information System (INIS)

    Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

    2007-01-01

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

  17. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  18. High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

    Directory of Open Access Journals (Sweden)

    J.-M. Wu

    2012-06-01

    Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

  19. Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

    International Nuclear Information System (INIS)

    Giacomini, G; Bagolini, A; Boscardin, M; Zorzi, N; Bomben, M; Calderini, G; Chauveau, J; Marchiori, G; Bosisio, L; Rosa, A La

    2014-01-01

    In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch

  20. Development of edgeless silicon pixel sensors on p-type substrate for the ATLAS high-luminosity upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste and INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2014-11-21

    In view of the LHC upgrade for the high luminosity phase (HL-LHC), the ATLAS experiment is planning to replace the inner detector with an all-silicon system. The n-in-p bulk technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. The large area necessary to instrument the outer layers will demand to tile the sensors, a solution for which the inefficient region at the border of each sensor needs to be reduced to the minimum size. This paper reports on a joint R and D project by the ATLAS LPNHE Paris group and FBK Trento on a novel n-in-p edgeless planar pixel design, based on the deep-trench process available at FBK.

  1. Selected results from the static characterization of edgeless n-on-p planar pixel sensors for ATLAS upgrades

    CERN Document Server

    Giacomini, Gabriele; Bomben, Marco; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; La Rosa, Alessandro; Marchiori, Giovanni; Zorzi, Nicola

    2014-01-01

    In view of the LHC upgrade for the High Luminosity Phase (HL-LHC), the ATLAS experiment is planning to replace the Inner Detector with an all-Silicon system. The n-on-p technology represents a valid solution for the modules of most of the layers, given the significant radiation hardness of this option and the reduced cost. There is also the demand to reduce the inactive areas to a minimum. The ATLAS LPNHE Paris group and FBK Trento started a collaboration for the development on a novel n-on-p edgeless planar pixel design, based on the deep-trench process which can cope with all these requirements. This paper reports selected results from the electrical characterization, both before and after irradiation, of test structures from the first production batch.

  2. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, Michael

    2010-07-19

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 10{sup 35}/cm{sup 2}s{sup 1} is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).10{sup 16} 1-MeV-neutrons per square centimeter (n{sub eq}/cm{sup 2}). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 {mu}m and 150 {mu}m proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive

  3. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    Beimforde, Michael

    2010-01-01

    To extend the discovery potential of the experiments at the LHC accelerator a two phase luminosity upgrade towards the super LHC (sLHC) with a maximum instantaneous luminosity of 10 35 /cm 2 s 1 is planned. Retaining the reconstruction efficiency and spatial resolution of the ATLAS tracking detector at the sLHC, new pixel modules have to be developed that have a higher granularity, can be placed closer to the interaction point, and allow for a cost-efficient coverage of a larger pixel detector volume compared to the present one. The reduced distance to the interaction point calls for more compact modules that have to be radiation hard to supply a sufficient charge collection efficiency up to an integrated particle fluence equivalent to that of (1-2).10 16 1-MeV-neutrons per square centimeter (n eq /cm 2 ). Within this thesis a new module concept was partially realised and evaluated for the operation within an ATLAS pixel detector at the sLHC. This module concept utilizes a novel thin sensor production process for thin n-in-p silicon sensors which potentially allow for a higher radiation hardness at a reduced cost. Furthermore, the new 3D-integration technology ICV-SLID is explored which will allow for increasing the active area of the modules from 71% to about 90% and hence, for employing the modules in the innermost layer of the upgraded ATLAS pixel detector. A semiconductor simulation and measurements of irradiated test sensors are used to optimize the implantation parameters for the inter-pixel isolation of the thin sensors. These reduce the crosstalk between the pixel channels and should allow for operating the sensors during the whole runtime of the experiment without causing junction breakdowns. The characterization of the first production of sensors with active thicknesses of 75 μm and 150 μm proved that thin pixel sensors can be successfully produced with the new process technology. Thin pad sensors with a reduced inactive edge demonstrate that the active

  4. Development of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Calderini, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Dipartimento di Fisica E. Fermi, Universitá di Pisa, Pisa (Italy); Bagolini, A. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Beccherle, R. [Istituto Nazionale di Fisica Nucleare, Sez. di Pisa (Italy); Bomben, M. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Boscardin, M. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); Bosisio, L. [Università degli studi di Trieste (Italy); INFN-Trieste (Italy); Chauveau, J. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Giacomini, G. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy); La Rosa, A. [Section de Physique (DPNC), Universitè de Geneve, Geneve (Switzerland); Marchiori, G. [Laboratoire de Physique Nucléaire et des Hautes Energies (LPNHE), Paris (France); Zorzi, N. [Fondazione Bruno Kessler, Centro per i Materiali e i Microsistemi (FBK-CMM), Povo di Trento (Italy)

    2016-09-21

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The presentation describes the performance of novel n-in-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology, some feedback from preliminary results of the first beam test will be discussed.

  5. Performance of Edgeless Silicon Pixel Sensors on p-type substrate for the ATLAS High-Luminosity Upgrade

    CERN Document Server

    INSPIRE-00052711; Boscardin, Maurizio; Bosisio, Luciano; Calderini, Giovanni; Chauveau, Jacques; Ducourthial, Audrey; Giacomini, Gabriele; Marchiori, Giovanni; Zorzi, Nicola

    2016-01-01

    In view of the LHC upgrade phases towards the High Luminosity LHC (HL-LHC), the ATLAS experiment plans to upgrade the Inner Detector with an all-silicon system. The n-on-p silicon technology is a promising candidate to achieve a large area instrumented with pixel sensors, since it is radiation hard and cost effective. The paper reports on the performance of novel n-on-p edgeless planar pixel sensors produced by FBK-CMM, making use of the active trench for the reduction of the dead area at the periphery of the device. After discussing the sensor technology an overview of the first beam test results will be given.

  6. Chip development in 65 nm CMOS technology for the high luminosity upgrade of the ATLAS pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Germic, Leonard; Hemperek, Tomasz; Kishishita, Tetsuichi; Krueger, Hans; Rymaszewski, Piotr; Wermes, Norbert [University of Bonn, Bonn (Germany)

    2016-07-01

    The LHC High Luminosity upgrade will result in a significant change of environment in which particle detectors are going to operate, especially for devices very close to the interaction point like pixel detector electronics. Challenges arising from the increased hit rate will have to be solved by designing faster and more complex readout electronics that will also have to withstand unprecedented radiation doses. Developing such integrated circuit requires a significant R and D effort and resources, therefore a joint development project between several institutes (including ours) was started. This collaboration, named RD53, aims to develop a pixel readout chip suitable for ATLAS' and CMS' upgrades using a 65nm CMOS technology. During this presentation motivations and benefits of using this very deep-submicron technology are discussed. Most of the talk is allocated to presenting some of the circuits designed by our group (focusing on developments connected to RD53 collaboration), along with their performance measurement results.

  7. ATLAS-TPX: a two-layer pixel detector setup for neutron detection and radiation field characterization

    International Nuclear Information System (INIS)

    Bergmann, B.; Caicedo, I.; Pospisil, S.; Vykydal, Z.; Leroy, C.

    2016-01-01

    A two-layer pixel detector setup (ATLAS-TPX), designed for thermal and fast neutron detection and radiation field characterization is presented. It consists of two segmented silicon detectors (256 × 256 pixels, pixel pitch 55 μm, thicknesses 300 μm and 500 μm) facing each other. To enhance the neutron detection efficiency a set of converter layers is inserted in between these detectors. The pixelation and the two-layer design allow a discrimination of neutrons against γs by pattern recognition and against charged particles by using the coincidence and anticoincidence information. The neutron conversion and detection efficiencies are measured in a thermal neutron field and fast neutron fields with energies up to 600 MeV. A Geant4 simulation model is presented, which is validated against the measured detector responses. The reliability of the coincidence and anticoincidence technique is demonstrated and possible applications of the detector setup are briefly outlined.

  8. A parallel FPGA implementation for real-time 2D pixel clustering for the ATLAS Fast Tracker Processor

    International Nuclear Information System (INIS)

    Sotiropoulou, C L; Gkaitatzis, S; Kordas, K; Nikolaidis, S; Petridou, C; Annovi, A; Beretta, M; Volpi, G

    2014-01-01

    The parallel 2D pixel clustering FPGA implementation used for the input system of the ATLAS Fast TracKer (FTK) processor is presented. The input system for the FTK processor will receive data from the Pixel and micro-strip detectors from inner ATLAS read out drivers (RODs) at full rate, for total of 760Gbs, as sent by the RODs after level-1 triggers. Clustering serves two purposes, the first is to reduce the high rate of the received data before further processing, the second is to determine the cluster centroid to obtain the best spatial measurement. For the pixel detectors the clustering is implemented by using a 2D-clustering algorithm that takes advantage of a moving window technique to minimize the logic required for cluster identification. The cluster detection window size can be adjusted for optimizing the cluster identification process. Additionally, the implementation can be parallelized by instantiating multiple cores to identify different clusters independently thus exploiting more FPGA resources. This flexibility makes the implementation suitable for a variety of demanding image processing applications. The implementation is robust against bit errors in the input data stream and drops all data that cannot be identified. In the unlikely event of missing control words, the implementation will ensure stable data processing by inserting the missing control words in the data stream. The 2D pixel clustering implementation is developed and tested in both single flow and parallel versions. The first parallel version with 16 parallel cluster identification engines is presented. The input data from the RODs are received through S-Links and the processing units that follow the clustering implementation also require a single data stream, therefore data parallelizing (demultiplexing) and serializing (multiplexing) modules are introduced in order to accommodate the parallelized version and restore the data stream afterwards. The results of the first hardware tests of

  9. Detector control system of the ATLAS insertable B-Layer

    International Nuclear Information System (INIS)

    Kersten, S.; Kind, P.; Lantzsch, K.; Maettig, P.; Zeitnitz, C.; Gensolen, F.; Citterio, M.; Meroni, C.; Verlaat, B.; Kovalenko, S.

    2012-01-01

    To improve tracking robustness and precision of the ATLAS inner tracker, an additional, fourth pixel layer is foreseen, called Insertable B-Layer (IBL). It will be installed between the innermost present Pixel layer and a new, smaller beam pipe and is presently under construction. As, once installed into the experiment, no access is possible, a highly reliable control system is required. It has to supply the detector with all entities required for operation and protect it at all times. Design constraints are the high power density inside the detector volume, the sensitivity of the sensors against heat-ups, and the protection of the front end electronics against transients. We present the architecture of the control system with an emphasis on the CO 2 cooling system, the power supply system, and protection strategies. As we aim for a common operation of Pixel and IBL detector, the integration of the IBL control system into the Pixel control system will also be discussed. (authors)

  10. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric,I et al.

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 1015 neq=cm2 , nearly 100% detection efficiency and a spatial resolution of about 3 μm were demonstrated. Since 2011 the HV detectors have first applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process.

  11. High-voltage pixel detectors in commercial CMOS technologies for ATLAS, CLIC and Mu3e experiments

    CERN Document Server

    Peric, Ivan; Backhaus, Malte; Barbero, Marlon; Benoit, Mathieu; Berger, Niklaus; Bompard, Frederic; Breugnon, Patrick; Clemens, Jean-Claude; Dannheim, Dominik; Dierlamm, Alexander; Feigl, Simon; Fischer, Peter; Fougeron, Denis; Garcia-Sciveres, Maurice; Heim, Timon; Hügging, Fabian; Kiehn, Moritz; Kreidl, Christian; Krüger, Hans; La Rosa, Alessandro; Liu, Jian; Lütticke, Florian; Mariñas, Carlos; Meng, Lingxin; Miucci, Antonio; Münstermann, Daniel; Nguyen, Hong Hanh; Obermann, Theresa; Pangaud, Patrick; Perrevoort, Ann-Kathrin; Rozanov, Alexandre; Schöning, André; Schwenker, Benjamin; Wiedner, Dirk

    2013-01-01

    High-voltage particle detectors in commercial CMOS technologies are a detector family that allows implementation of low-cost, thin and radiation-tolerant detectors with a high time resolution. In the R/D phase of the development, a radiation tolerance of 10 15 n eq = cm 2 , nearly 100% detection ef fi ciency and a spatial resolution of about 3 μ m were demonstrated. Since 2011 the HV detectors have fi rst applications: the technology is presently the main option for the pixel detector of the planned Mu3e experiment at PSI (Switzerland). Several prototype sensors have been designed in a standard 180 nm HV CMOS process and successfully tested. Thanks to its high radiation tolerance, the HV detectors are also seen at CERN as a promising alternative to the standard options for ATLAS upgrade and CLIC. In order to test the concept, within ATLAS upgrade R/D, we are currently exploring an active pixel detector demonstrator HV2FEI4; also implemented in the 180 nm HV process

  12. Characterisation of novel thin n-in-p planar pixel modules for the ATLAS Inner Tracker upgrade

    Science.gov (United States)

    Beyer, J.-C.; La Rosa, A.; Macchiolo, A.; Nisius, R.; Savic, N.; Taibah, R.

    2018-01-01

    In view of the high luminosity phase of the LHC (HL-LHC) to start operation around 2026, a major upgrade of the tracker system for the ATLAS experiment is in preparation. The expected neutron equivalent fluence of up to 2.4×1016 1 MeV neq./cm2 at the innermost layer of the pixel detector poses the most severe challenge. Thanks to their low material budget and high charge collection efficiency after irradiation, modules made of thin planar pixel sensors are promising candidates to instrument these layers. To optimise the sensor layout for the decreased pixel cell size of 50×50 μm2, TCAD device simulations are being performed to investigate the charge collection efficiency before and after irradiation. In addition, sensors of 100-150 μm thickness, interconnected to FE-I4 read-out chips featuring the previous generation pixel cell size of 50×250 μm2, are characterised with testbeams at the CERN-SPS and DESY facilities. The performance of sensors with various designs, irradiated up to a fluence of 1×1016 neq./cm2, is compared in terms of charge collection and hit efficiency. A replacement of the two innermost pixel layers is foreseen during the lifetime of HL-LHC . The replacement will require several months of intervention, during which the remaining detector modules cannot be cooled. They are kept at room temperature, thus inducing an annealing. The performance of irradiated modules will be investigated with testbeam campaigns and the method of accelerated annealing at higher temperatures.

  13. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    International Nuclear Information System (INIS)

    Carlsen, Brett; Tavrides, Emily; Schneider, Erich

    2010-01-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  14. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  15. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    Kuzay, T.

    1993-01-01

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  16. Trends in the design of front-end systems for room temperature solid state detectors

    International Nuclear Information System (INIS)

    Manfredi, Pier F.; Re, Valerio

    2003-01-01

    The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors

  17. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase...... of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

  18. Analog front end circuit design of CSNS beam loss monitor system

    International Nuclear Information System (INIS)

    Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

    2013-01-01

    The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

  19. Vacuum tests of a beamline front-end mock-up at the Advanced Photon Source

    International Nuclear Information System (INIS)

    Liu, C.; Nielsen, R.W.; Kruy, T.L.; Shu, D.; Kuzay, T.M.

    1994-01-01

    A-mock-up has been constructed to test the functioning and performance of the Advanced Photon Source (APS) front ends. The mock-up consists of all components of the APS insertion-device beamline front end with a differential pumping system. Primary vacuum tests have been performed and compared with finite element vacuum calculations. Pressure distribution measurements using controlled leaks demonstrate a better than four decades of pressure difference between the two ends of the mock-up. The measured pressure profiles are consistent with results of finite element analyses of the system. The safety-control systems are also being tested. A closing time of ∼20 ms for the photon shutter and ∼7 ms for the fast closing valve have been obtained. Experiments on vacuum protection systems indicate that the front end is well protected in case of a vacuum breach

  20. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  1. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

  2. A tunable RF Front-End with Narrowband Antennas for Mobile Devices

    DEFF Research Database (Denmark)

    Bahramzy, Pevand; Olesen, Poul; Madsen, Peter

    2015-01-01

    desensitization due to the Tx signal. The filters and antennas demonstrate tunability across multiple bands. System validation is detailed for LTE band I. Frequency response, as well as linearity measurements of the complete Tx and Rx front-end chains, show that the system requirements are fulfilled.......In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex filters...

  3. MUON POLARIZATION EFFECTS IN THE FRONT END OF THE NEUTRINO FACTORY

    International Nuclear Information System (INIS)

    FERNOW, R.C.; GALLARDO, J.C.; FUKUI, Y.

    2000-01-01

    The authors summarize the methods used for simulation of polarization effects in the front end of a possible neutrino factory. They first discuss the helicity of muons in the pion decay process. They find that, neglecting acceptance considerations, the average helicity asymptotically approaches a magnitude of 0.185 at large pion momenta. Next they describe the methods used for tracking the spin through the complicated electromagnetic field configurations in the front end of the neutrino factory, including rf phase rotation and ionization cooling channels. Various depolarizing effects in matter are then considered, including multiple Coulomb scattering and elastic scattering from atomic electrons. Finally, they include all these effects in a simulation of a 480 m long, double phase rotation front end scenario

  4. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    Energy Technology Data Exchange (ETDEWEB)

    Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P, E-mail: Michael.Beimforde@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, D-80805, Muenchen (Germany)

    2010-12-15

    The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 {mu}m and 150 {mu}m has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10{sup 16}n{sub eq}cm{sup -2} have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

  5. A module concept for the upgrades of the ATLAS pixel system using the novel SLID-ICV vertical integration technology

    International Nuclear Information System (INIS)

    Beimforde, M; Andricek, L; Macchiolo, A; Moser, H-G; Nisius, R; Richter, R H; Weigell, P

    2010-01-01

    The presented R and D activity is focused on the development of a new pixel module concept for the foreseen upgrades of the ATLAS detector towards the Super LHC employing thin n-in-p silicon sensors together with a novel vertical integration technology. A first set of pixel sensors with active thicknesses of 75 μm and 150 μm has been produced using a thinning technique developed at the Max-Planck-Institut fuer Physik (MPP) and the MPI Semiconductor Laboratory (HLL). Charge Collection Efficiency (CCE) measurements of these sensors irradiated with 26 MeV protons up to a particle fluence of 10 16 n eq cm -2 have been performed, yielding higher values than expected from the present radiation damage models. The novel integration technology, developed by the Fraunhofer Institut EMFT, consists of the Solid-Liquid InterDiffusion (SLID) interconnection, being an alternative to the standard solder bump-bonding, and Inter-Chip Vias (ICVs) for routing signals vertically through electronics. This allows for extracting the digitized signals from the back side of the readout chips, avoiding wire-bonding cantilevers at the edge of the devices and thus increases the active area fraction. First interconnections have been performed with wafers containing daisy chains to investigate the efficiency of SLID at wafer-to-wafer and chip-to-wafer level. In a second interconnection process the present ATLAS FE-I3 readout chips were connected to dummy sensor wafers at chip-to-wafer level. Preparations of ICV within the ATLAS readout chips for back side contacting and the future steps towards a full demonstrator module will be presented.

  6. Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

    International Nuclear Information System (INIS)

    Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

    2013-01-01

    New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

  7. Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

    CERN Document Server

    Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

    2015-01-01

    front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

  8. Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A M

    1992-01-01

    Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...... available GaInAs/InP pin photo diode. The procedure for measuring the transimpedance and the equivalent input noise current density is outlined in this paper and demonstrated using one of the MMICs. The MMICs were fabricated using the Plessey F20 process by GEC-Marconi through the ESPRIT programme EUROCHIP...

  9. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not ...... together with a positive-sequence current controller for the front-end rectifier. A gain in the feedforward term can be changed to control the negative-sequence current. Simulation results are presented to verify the theory....

  10. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    International Nuclear Information System (INIS)

    Carlson, R.B.

    1992-01-01

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

  11. Design and development of the IBL-BOC firmware for the ATLAS Pixel IBL optical datalink system

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00356268

    The Insertable $b$-Layer (IBL) is the first upgrade of the ATLAS Pixel detector at the LHC. It will be installed in the Pixel detector in 2013. The IBL will use a new sensor and readout technology, therefore the readout components of the current Pixel detector are redesigned for the readout of the IBL. In this diploma thesis the design and development of the firmware for the new IBL Back-of-Crate card (IBL-BOC) are described. The IBL-BOC is located on the off-detector side of the readout and performs the optical-electrical conversion and vice versa for the optical connection to and from the detector. To process the data transmitted to and received from the detector, the IBL-BOC uses multiple Field Programmable Gate Arrays (FPGA). The transmitted signal is a 40~Mb/s BiPhase Mark (BPM) encoded data stream, providing the timing, trigger and control to the detector. The received signal is a 160~Mb/s 8b10b encoded data stream, containing data from the detector. The IBL-BOC encodes and decodes these data streams. T...

  12. Prototyping of larger structures for the Phase-II upgrade of the pixel detector of the ATLAS experiment

    CERN Document Server

    Alvarez Feito, Diego; The ATLAS collaboration

    2017-01-01

    For the high luminosity era of the Large Hadron Collider (HL-LHC) it is forseen to replace the current inner tracker of the ATLAS experiment with a new detector to cope with the occuring increase in occupancy, bandwidth and radiation damage. It will consist of an inner pixel and outer strip detector aiming to provide tracking coverage up to |η|<4. The layout of the pixel detector is foreseen to consist of five layers of pixel silicon sensor modules in the central region and several ring-shaped layers in the forward region. It results in up to 14 m² of silicon depending on the selected layout. Beside the challenge of radiation hardness and high-rate capable silicon sensors and readout electronics many system aspects have to be considered for a fully functional detector. Both stable and low mass mechanical structures and services are important. Within the collaboration a large effort is started to prototype larger detector structures for both the central and forward region of the detector. The aspect of sy...

  13. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    Energy Technology Data Exchange (ETDEWEB)

    Andricek, L. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany); Beimforde, M., E-mail: mibei@mpp.mpg.de [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Macchiolo, A. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Moser, H.-G. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany); Nisius, R. [Max-Planck-Institut fuer Physik, Foehringer Ring 6, 80805 Muenchen (Germany); Richter, R.H. [Max-Planck-Institut Halbleiterlabor, Otto Hahn Ring 6, 81739 Muenchen (Germany)

    2011-04-21

    A new pixel module concept is presented utilizing thin sensors and a novel vertical integration technique for the ATLAS pixel detector in view of the foreseen LHC luminosity upgrades. A first set of pixel sensors with active thicknesses of 75 and 150{mu}m has been produced from wafers of standard thickness using a thinning process developed at the Max-Planck-Institut Halbleiterlabor (HLL) and the Max-Planck-Institut fuer Physik (MPP). Pre-irradiation characterizations of these sensors show a very good device yield and high break down voltage. First proton irradiations up to a fluence of 10{sup 15} n{sub eq} cm{sup -2} have been carried out and their impact on the electrical properties of thin sensors has been studied. The novel ICV-SLID vertical integration technology will allow for routing signals vertically to the back side of the readout chips. With this, four-side buttable detector devices with an increased active area fraction are made possible. A first production of SLID test structures was performed and showed a high connection efficiency for different pad sizes and a mild sensitivity to disturbances of the surface planarity.

  14. Development of thin sensors and a novel interconnection technology for the upgrade of the ATLAS pixel system

    International Nuclear Information System (INIS)

    Andricek, L.; Beimforde, M.; Macchiolo, A.; Moser, H.-G.; Nisius, R.; Richter, R.H.

    2011-01-01

    A new pixel module concept is presented utilizing thin sensors and a novel vertical integration technique for the ATLAS pixel detector in view of the foreseen LHC luminosity upgrades. A first set of pixel sensors with active thicknesses of 75 and 150μm has been produced from wafers of standard thickness using a thinning process developed at the Max-Planck-Institut Halbleiterlabor (HLL) and the Max-Planck-Institut fuer Physik (MPP). Pre-irradiation characterizations of these sensors show a very good device yield and high break down voltage. First proton irradiations up to a fluence of 10 15 n eq cm -2 have been carried out and their impact on the electrical properties of thin sensors has been studied. The novel ICV-SLID vertical integration technology will allow for routing signals vertically to the back side of the readout chips. With this, four-side buttable detector devices with an increased active area fraction are made possible. A first production of SLID test structures was performed and showed a high connection efficiency for different pad sizes and a mild sensitivity to disturbances of the surface planarity.

  15. Studies of the performance of different front-end systems for flat-panel multi-anode PMTs with CsI(Tl) scintillator arrays

    International Nuclear Information System (INIS)

    Sekiya, H.; Hattori, K.; Kubo, H.; Miuchi, K.; Nagayoshi, T.; Nishimura, H.; Okada, Y.; Orito, R.; Takada, A.; Takeda, A.; Tanimori, T.; Ueno, K.

    2006-01-01

    We have studied the performance of two different types of front-end systems for our gamma camera based on Hamamatsu H8500 (flat-panel 64 channels multi-anode PSPMT) with a CsI(Tl) scintillator array. The array consists of 64 pixels of 6x6x20mm 3 which corresponds to the anode pixels of H8500. One of the system is based on commercial ASIC chips in order to read out every anode. The others are based on resistive charge divider network between anodes to reduce readout channels. In both systems, each pixel (6mm) was clearly resolved by flood field irradiation of 137 Cs. We also investigated the energy resolution of these systems and showed the performance of the cascade connection of resistive network between some PMTs for large area detectors

  16. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

  17. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  18. Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

    CERN Document Server

    Lo Presti, D; Caponetto, L

    2007-01-01

    A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  19. Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

    DEFF Research Database (Denmark)

    Liu, Qing Zhong

    1991-01-01

    Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken...

  20. Performance of the front-end electronics of the ANTARES neutrino telescope

    NARCIS (Netherlands)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

    2010-01-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube