Test system for the production of the Atlas Tile Calorimeter front-end electronics

International Nuclear Information System (INIS)

Calvet, David

2004-01-01

The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

International Nuclear Information System (INIS)

Kureba, C O; Govender, M; Hofsajer, I; Ruan, X; Sandrock, C; Spoor, M

2015-01-01

The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade. (paper)

Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

International Nuclear Information System (INIS)

Wardrope, D

2012-01-01

The Large Hadron Collider will be upgraded to provide instantaneous luminosity L = 5 × 10 34 cm −2 s −1 , leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20 μs in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of p T ∼ 25 GeV, which will be of great benefit to the future physics programme of ATLAS.

Tester of the TRT front-end electronics for the ATLAS-experiment

CERN Document Server

Hajduk, Z; Kisielewski, B; Kotarba, A; Malecki, P; Natkaniec, Z; Olszowska, J; Ostrowicz, W; Krupinska, G

2000-01-01

The VME based tester for front-end electronics of the TRT (Transition Radiation Tracker) detector of the ATLAS-LHC experiment at CERN, Geneva, is described. The TRT read-out electronics for 424576 proportional tubes grouped on many thousands of cards requires stringent quality control after assembly and during installation. The tester provides all required data, pulses, timing and power supplies for tested cards. The essential part of the tester is its software that allows for device handling as well as facilitates functional and statistical tests. The prototype, present design as well as the new design for mass production tests are discussed. (17 refs).

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

CERN Document Server

Chen, Kai; The ATLAS collaboration

2016-01-01

The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

CERN Document Server

Moschovakos, Paris

2018-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

CERN Document Server

La Rosa, Alessandro; The ATLAS collaboration

2016-01-01

The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Hofsajer, I; Govender, M; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is the portable test-bench for the full certification of the front-end electronics of the ATLAS Tile calorimeter designed for the upgrade phase-II. It is a high throughput electronics system designed to simultaneously read-out all the samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read-out and control the front-end boards. The rest of the functionalities of the system are provided by a HV mezzanine board that to turn on the gain of the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog output of the front-end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

CERN Document Server

Cooper, B; The ATLAS collaboration

2012-01-01

Around 2021 the Large Hadron Collider will be upgraded to provide instantaneous luminosities 5x10^34, leading to excessive rates from the ATLAS Level-1 trigger. We describe a double-buffer front-end architecture for the ATLAS tracker replacement which should enable tracking information to be used in the Level-1 decision. This will allow Level-1 rates to be controlled whilst preserving high efficiency for single lepton triggers at relatively low transverse momentum thresholds pT ~25 GeV, enabling ATLAS to remain sensitive to physics at the electroweak scale. In particular, a potential hardware solution for the communication between the upgraded silicon barrel strip detectors and the external processing within this architecture will be described, and discrete event simulations used to demonstrate that this fits within the tight latency constraints.

Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

2016-01-01

The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

CERN Document Server

Drake, Gary; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

Analog lightwave links for detector front-ends at the LHC

International Nuclear Information System (INIS)

Baird, A.; Dowell, J.; Duthie, P.

1995-01-01

Lightwave links are being developed for volume application in the transfer of analog signals from the tracking detector front-ends to the readout electronics. The links are based on electro-optic intensity modulators which are mounted on detectors and connected by optical fibers to remotely located transceivers (lasers and photoreceivers). The modulators are 3--5 semiconductor reflective devices based on multi-quantum well structures. The transceivers will be integrated devices of a novel design. Modulator prototypes have been fabricated and tested. Neutron and γ-ray irradiation studies have been performed on modulators and fibers. The main results achieved so far are reported and key system issues are reviewed. This work is part of the CERN DRDC project RD23 project RD23

Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

CERN Document Server

Drake, G; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

CERN Document Server

Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

2012-01-01

The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

CERN Document Server

Posch, C

2002-01-01

Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

Adaptive RF front-ends for hand-held applications

CERN Document Server

van Bezooijen, Andre; van Roermund, Arthur

2010-01-01

The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

CERN Document Server

Drake, Gary; The ATLAS collaboration

2011-01-01

We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

CERN Document Server

Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

2011-01-01

We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

System tests of radiation hard optical links for the ATLAS semiconductor tracker

International Nuclear Information System (INIS)

Charlton, D.G.; Dowell, J.D.; Homer, R.J.; Jovanovic, P.; Kenyon, I.R.; Mahout, G.; Shaylor, H.R.; Wilson, J.A.; Rudge, A.; Fopma, J.; Mandic, I.; Nickerson, R.B.; Shield, P.; Wastie, R.; Weidberg, A.R.; Eek, L.-O.; Go, A.; Lund-Jensen, B.; Pearce, M.; Soederqvist, J.; Morrissey, M.; White, D.J.

2000-01-01

A prototype optical data and Timing, Trigger and Control transmission system based on LEDs and PIN-diodes has been constructed. The system would be suitable in terms of radiation hardness and radiation length for use in the ATLAS SemiConductor Tracker. Bit error rate measurements were performed for the data links and for the links distributing the Timing, Trigger and Control data from the counting room to the front-end modules. The effects of cross-talk between the emitters and receivers were investigated. The advantages of using Vertical Cavity Surface Emitting Lasers (VCSELs) instead of LEDs are discussed

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

Feedback from operational experience in front-end transportation

International Nuclear Information System (INIS)

Mondonel, J.L.; Parison, C.

1998-01-01

Transport forms an integral part of the nuclear fuel cycle, representing the strategic link between each stage of the cycle. In a way there is a transport cycle that parallels the nuclear fuel cycle. This concerns particularly the front-end of the cycle whose steps - mining conversion, enrichment and fuel fabrication - require numerous transports. Back-end shipments involve a handful of countries, but front-end transports involve all five continents, and many exotic countries. All over Europe such transports are routinely performed with an excellent safety track record. Transnucleaire dominates the French nuclear transportation market and carries out both front and back-end transports. For instance in 1996 more than 28,400 front-end packages were transported as well as more than 3,600 back-end packages. However front-end transport is now a business undergoing much change. A nuclear transportation company must now cope with an evolving picture including new technical requirements, new transportation schemes and new business conditions. This paper describes the latest evolutions in terms of front-end transportation and the way this activity is carried out by Transnucleaire, and goes on to discuss future prospects. (authors)

An automated meta-monitoring mobile application and front-end interface for the ATLAS computing model

Energy Technology Data Exchange (ETDEWEB)

Kawamura, Gen; Quadt, Arnulf [II. Physikalisches Institut, Georg-August-Universitaet Goettingen (Germany)

2016-07-01

Efficient administration of computing centres requires advanced tools for the monitoring and front-end interface of the infrastructure. Providing the large-scale distributed systems as a global grid infrastructure, like the Worldwide LHC Computing Grid (WLCG) and ATLAS computing, is offering many existing web pages and information sources indicating the status of the services, systems and user jobs at grid sites. A meta-monitoring mobile application which automatically collects the information could give every administrator a sophisticated and flexible interface of the infrastructure. We describe such a solution; the MadFace mobile application developed at Goettingen. It is a HappyFace compatible mobile application which has a user-friendly interface. It also becomes very feasible to automatically investigate the status and problem from different sources and provides access of the administration roles for non-experts.

Design of analog front-ends for the RD53 demonstrator chip

CERN Document Server

Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

2017-01-01

The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

International Nuclear Information System (INIS)

CHASE, B.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, S.; RESCIA, S.; TAKAI, H.

1999-01-01

The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

International Nuclear Information System (INIS)

CHASE, R.L.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, V.; RESCIA, S.; TAKAI, H.; BAN, J.; PARSONS, J.; SIPPACH, W.

2000-01-01

The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

FELIX - the new detector readout system for the ATLAS experiment

CERN Document Server

AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

2016-01-01

From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability. Different Front-end data types or different data sources can be routed to different network endpoints that handle that data type or source: e.g. event data, configuration, calibration, detector control, monito...

End-Users, Front Ends and Librarians.

Science.gov (United States)

Bourne, Donna E.

1989-01-01

The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

FELIX: the new detector interface for the ATLAS experiment

CERN Document Server

Wu, Weihao; The ATLAS collaboration

2018-01-01

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC at CERN will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for...

FELIX: the New Detector Interface for the ATLAS Experiment

CERN Document Server

Aggarwal, Anamika; The ATLAS collaboration

2018-01-01

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event f...

The control system for the CMS tracker front-end

CERN Document Server

Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

2002-01-01

The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

Artificial Neural Network based DC-link Capacitance Estimation in a Diode-bridge Front-end Inverter System

DEFF Research Database (Denmark)

Soliman, Hammam Abdelaal Hammam; Abdelsalam, Ibrahim; Wang, Huai

2017-01-01

, a proposed software condition monitoring methodology based on Artificial Neural Network (ANN) algorithm is presented. Matlab software is used to train and generate the proposed ANN. The proposed methodology estimates the capacitance of the DC-link capacitor in a three phase front-end diode bridge AC......In modern design of power electronic converters, reliability of DC-link capacitors is an essential aspect to be considered. The industrial field have been attracted to the monitoring of their health condition and the estimation of their ageing process status. The existing condition monitoring...

FELIX: the New Detector Interface for the ATLAS Experiment arXiv

CERN Document Server

Wu, Weihao

During the next major shutdown (2019-2020), the ATLAS experiment at the LHC will adopt the Front-End Link eXchange (FELIX) system as the interface between the data acquisition, detector control and TTC (Timing, Trigger and Control) systems and new or updated trigger and detector front-end electronics. FELIX will function as a router between custom serial links from front-end ASICs and FPGAs to data collection and processing components via a commodity switched network. Links may aggregate many slower links or be a single high bandwidth link. FELIX will also forward the LHC bunch-crossing clock, fixed latency trigger accepts and resets received from the TTC system to front-end electronics. The FELIX system uses commodity server technology in combination with FPGA-based PCIe I/O cards. The FELIX servers will run a software routing platform serving data to network clients. Commodity servers connected to FELIX systems via the same network will run the new Software Readout Driver (SW ROD) infrastructure for event f...

Front end readout electronics for the CMS hadron calorimeter

CERN Document Server

Shaw, Terri M

2002-01-01

The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

Front end readout electronics for the CMS hadron calorimeter

International Nuclear Information System (INIS)

Terri M. Shaw et al.

2002-01-01

The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm 2 . For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes

FELIX: the new detector readout system for the ATLAS experiment

CERN Document Server

Bauer, Kevin Thomas; The ATLAS collaboration

2017-01-01

Starting in 2018 during the planned shutdown of the LHC, the ATLAS experiment at CERN will be deploying new optical link technology (GigaBit Transceiver links) connecting the front end electronics. The Front-End LInk eXchange (FELIX) will provide an infrastructure for the new GBT links to connect to the rest of the Trigger and Data Acquisition (TDAQ) system. FELIX is a PC-based system designed to route data and commands to and from the GBT links and a Commercial Off-The Shelf (COTS) network. In this paper, the FELIX system is described and the design of the hardware prototype and core software is presented.

An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

CERN Document Server

Porter, Ryan

This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

FELIX: The new detector readout system for the ATLAS experiment

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00370160; The ATLAS collaboration

2017-01-01

After the Phase-I upgrades (2019) of the ATLAS experiment, the Front-End Link eXchange (FELIX) system will be the interface between the data acquisition system and the detector front-end and trigger electronics. FELIX will function as a router between custom serial links and a commodity switch network using standard technologies (Ethernet or Infiniband) to communicate with commercial data collecting and processing components. The system architecture of FELIX will be described and the status of the firmware implementation and hardware development currently in progress will be presented.

FELIX: The new detector readout system for the ATLAS experiment

Science.gov (United States)

Ryu, Soo; ATLAS TDAQ Collaboration

2017-10-01

After the Phase-I upgrades (2019) of the ATLAS experiment, the Front-End Link eXchange (FELIX) system will be the interface between the data acquisition system and the detector front-end and trigger electronics. FELIX will function as a router between custom serial links and a commodity switch network using standard technologies (Ethernet or Infiniband) to communicate with commercial data collecting and processing components. The system architecture of FELIX will be described and the status of the firmware implementation and hardware development currently in progress will be presented.

ATLAS end-cap detector

CERN Multimedia

Maximilien Brice

2003-01-01

Three scientists from the Institute of Nuclear Phyiscs at Novossibirsk with one of the end-caps of the ATLAS detector. The end-caps will be used to detect particles produced in the proton-proton collisions at the heart of the ATLAS experiment that are travelling close to the axis of the two beams.

A multitasking, multisinked, multiprocessor data acquisition front end

International Nuclear Information System (INIS)

Fox, R.; Au, R.; Molen, A.V.

1989-01-01

The authors have developed a generalized data acquisition front end system which is based on MC68020 processors running a commercial real time kernel (rhoSOS), and implemented primarily in a high level language (C). This system has been attached to the back end on-line computing system at NSCL via our high performance ETHERNET protocol. Data may be simultaneously sent to any number of back end systems. Fixed fraction sampling along links to back end computing is also supported. A nonprocedural program generator simplifies the development of experiment specific code

The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

DEFF Research Database (Denmark)

Aagaard, Annabeth

2012-01-01

Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999,......-oriented longitudinal case study of a Danish pharmaceutical company. The findings and key learnings from the study are presented as propositions of how innovation strategies can be applied to actively facilitate FEI and with measurable results.......Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999...

ATLAS End-cap Part II

CERN Multimedia

2007-01-01

The epic journey of the ATLAS magnets is drawing to an end. On Thursday 12 July, the second end-cap of the ATLAS toroid magnet was lowered into the cavern of the experiment with the same degree of precision as the first (see Bulletin No. 26/2007). This spectacular descent of the 240-tonne component, is one of the last transport to be completed for ATLAS.

Front-end DAQ strategy and implementation for the KLOE-2 experiment

Science.gov (United States)

Branchini, P.; Budano, A.; Balla, A.; Beretta, M.; Ciambrone, P.; De Lucia, E.; D'Uffizi, A.; Marciniewski, P.

2013-04-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

Front-end DAQ strategy and implementation for the KLOE-2 experiment

International Nuclear Information System (INIS)

Branchini, P; Budano, A; Balla, A; Beretta, M; Ciambrone, P; Lucia, E De; D'Uffizi, A; Marciniewski, P

2013-01-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2008-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

CERN Document Server

Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

2013-01-01

The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

CERN Document Server

Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

2009-01-01

FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

R&D Studies of the ATLAS LAr Calorimeter Readout Electronics for super-LHC

CERN Document Server

Chen, H

2010-01-01

The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors, total about 180,000 signals are digitized and processed real-time on detector, to provide energy and time deposited in each detector element at every occurrence of the L1-trigger. A luminosity upgrade (x10) of the LHC will occur ~2017, the current readout electronics will have to be upgraded to sustain the higher radiation levels. A completely innovative readout scheme is being developed. The front-end readout will send out data continuously at each bunch crossing through high speed radiation resistant optical links, the data will be processed real-time with the possibility of implementing trigger algorithms. This article is an overview of the R&D activities and architectural studies the ATLAS LAr collaboration is developing: front-end analog and mixed-signal ASIC design, radiation resistance optical-links in SOS, high-speed back-end processing units based on FPGA architectures and power supply d...

PMF: The front end electronic of the ALFA detector

Energy Technology Data Exchange (ETDEWEB)

Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

2010-11-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2010-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

Science.gov (United States)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

International Nuclear Information System (INIS)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

MMIC front-ends for optical communication systems

DEFF Research Database (Denmark)

Petersen, Anders Kongstad

1993-01-01

Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

Fast front-end electronics for COMPASS MWPCs

CERN Document Server

Colantoni, M L; Ferrero, A; Frolov, V; Grasso, A; Heinz, S; Maggiora, A; Maggiora, M G; Panzieri, D; Popov, A; Tchalyshev, V

2000-01-01

In the COMPASS experiment, under construction at CERN, about 23000 channels of MWPCs will be used. The very high rate of the muon and hadron beams, and the consequently high trigger rate, require front- end electronics with innovative conceptual design. A new MWPC front- end electronics that fulfills the main COMPASS requirement to have a fast DAQ with a minimum dead-time has been designed. The general concept of the front-end cards is described; the comparative tests of two front-end chips, and different fast gas mixtures, are also shown. The commissioning of the experiment will start in the summer 2000, and production running, using the muon beam, is foreseen for the year 2001. (8 refs).

RPC performance vs. front-end electronics

International Nuclear Information System (INIS)

Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

2012-01-01

Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

Muon front end for the neutrino factory

CERN Document Server

Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

2013-01-01

In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

Muon front end for the neutrino factory

Directory of Open Access Journals (Sweden)

C. T. Rogers

2013-04-01

Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

2002-01-01

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

Front end data link processor

International Nuclear Information System (INIS)

Wallace, J.J.

1988-01-01

It is possible to expand the data acquisition capabilities of an existing process computer to include other dedicated computer based systems, provided each system has at least minimal data link capabilities. The following paper discusses the addition of three computer based acquisition systems to a Honeywell 4500C (also designated the 45000) running the SEER system. Only one data link port was required to support the link. Each of the three specialized systems implemented data link protocols used by their suppliers in previous projects: none of the three were compatible with Honeywell's protocol. Part one of the following provides a generic overview of the project and would be relevent to the operator of any process system interested in expansion. Part two provides specific details of this project and may serve to provide performance benchmarks to those who wish to consider a similar project

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

Energy Technology Data Exchange (ETDEWEB)

Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

2016-11-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

International Nuclear Information System (INIS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

2016-01-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

The upgraded CDF front end electronics for calorimetry

Energy Technology Data Exchange (ETDEWEB)

Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

1991-11-01

The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 {mu}Sec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals.

The upgraded CDF front end electronics for calorimetry

International Nuclear Information System (INIS)

Drake, G.; Frei, D.; Hahn, S.R.; Nelson, C.A.; Segler, S.L.; Stuermer, W.

1991-11-01

The front end electronics used in the calorimetry of the CDF detector has been upgraded to meet system requirements for higher expected luminosity. A fast digitizer utilizing a 2 μSec, 16 bit ADC has been designed and built. Improvements to the front end trigger circuitry have been implemented, including the production of 900 new front end modules. Operational experience with the previous system is presented, with discussion of the problems and performance goals

Managing Controversies in the Fuzzy Front End

DEFF Research Database (Denmark)

Christiansen, John K.; Gasparin, Marta

2016-01-01

This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

FELIX: the new detector readout system for the ATLAS experiment

CERN Document Server

Zhang, Jinlong; The ATLAS collaboration

2017-01-01

After the Phase-I upgrade and onward, the Front-End Link eXchange (FELIX) system will be the interface between the data handling system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a router between custom serial links and a commodity switch network which will use standard technologies to communicate with data collecting and processing components. The FELIX system is being developed by using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card interfacing to GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. Dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software will provide the required functionality. On the network side, the FELIX unit connects to both Ethernet-based network and Infiniband. The system architecture of FE...

Preparing an ATLAS toroid magnet end-cap for lowering

CERN Multimedia

Claudia Marcelloni

2007-01-01

One of the two 13-m high toroid magnet end-caps for the ATLAS experiment being transported from the construction hall to the experimental area. The end-cap will be lowered into the ATLAS cavern and attached to an end of the detector.

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

International Nuclear Information System (INIS)

Fan Chao; Jiao Shilong; Wu Yunfeng; Ye Yutang; Chen Tangsheng; Yang Lijie; Feng Ou

2009-01-01

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fabricated based on the Φ-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simulation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/μm and a photosensitive area of 50 x 50 μm 2 . The whole chip has an area of 1511 x 666 μm 2 . The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950 x 1910 μm 2 and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 mVpp.

10 Gb/s OEIC optical receiver front-end and 3.125 Gb/s PHEMT limiting amplifier

Energy Technology Data Exchange (ETDEWEB)

Fan Chao; Jiao Shilong; Wu Yunfeng; Ye Yutang [School of Opto-Electronic Information, UESTC, Chengdu 610054 (China); Chen Tangsheng; Yang Lijie; Feng Ou, E-mail: fanchao41@126.co [Nanjing Electronic Devices Institute, Nanjing 210016 (China)

2009-10-15

A 10 Gb/s OEIC (optoelectronic integrated circuit) optical receiver front-end has been studied and fabricated based on the {Phi}-76 mm GaAs PHEMT process; this is the first time that a limiting amplifier (LA) has been designed and realized using depletion mode PHEMT. An OEIC optical receiver front-end mode composed of an MSM photodiode and a current mode transimpedance amplifier (TIA) has been established and optimized by simulation software ATLAS. The photodiode has a bandwidth of 10 GHz, a capacitance of 3 fF/{mu}m and a photosensitive area of 50 x 50 {mu}m{sup 2}. The whole chip has an area of 1511 x 666 {mu}m{sup 2}. The LA bandwidth is expanded by spiral inductance which has been simulated by software HFSS. The chip area is 1950 x 1910 {mu}m{sup 2} and the measured results demonstrate an input dynamic range of 34 dB (10-500 mVpp) with constant output swing of 500 mVpp.

Concepts for a Muon Accelerator Front-End

Energy Technology Data Exchange (ETDEWEB)

Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

2017-03-16

We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

RF front-end world class designs

CERN Document Server

Love, Janine

2009-01-01

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

Front-end electronics development for the SSC

International Nuclear Information System (INIS)

Levi, M.

1990-12-01

This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

Indico front-end: From spaghetti to lasagna

CERN Multimedia

CERN. Geneva

2017-01-01

We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

Idea management in support of pharmaceutical front end innovation

DEFF Research Database (Denmark)

Aagaard, Annabeth

2012-01-01

The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

Front-end electronics for the upgraded GMRT

International Nuclear Information System (INIS)

Raut, Anil N; Bhalerao, Vilas; Kumar, A Praveen

2013-01-01

This paper first describes briefly the existing front-end receiver in use at the GMRT observatory and then details the ongoing development of next generation receiver systems for the upgraded GMRT. It covers the design of the new, two stage, room temperature, low noise amplifiers with better noise performance and matching, and improved dynamic range that are being implemented for the 130–260 MHz, 250–500 MHz and 550–900 MHz bands of the upgraded GMRT front-end systems.

Ultra-wideband wireless receiver front-end for high-speed indoor applications

Directory of Open Access Journals (Sweden)

Zhe-Yang Huang

2014-12-01

Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

Programmer's guide to FFE: a fast front-end data-acquisition program

International Nuclear Information System (INIS)

Million, D.L.

1983-05-01

The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

CERN Document Server

Chen, H; The ATLAS collaboration

2011-01-01

The ATLAS experiment is one of the two general-purpose detectors designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS (and its LAr Calorimeters) has been operating and collecting p-p collisions at LHC since 2009. The on-detector electronics (front-end) part of the current readout electronics of the calorimeters measures the ionization current signals by means of preamplifiers, shapers and digitizers and then transfers the data to the off-detector electronics (back-end) for further elaboration, via optical links. Only the data selected by the level-1 calorimeter trigger system are transferred, achieving a bandwidth reduction to 1.6 Gbps. The analog trigger sum sig...

Readout Electronics Upgrades of the ATLAS Liquid Argon Calorimeter

CERN Document Server

Anelli, Christopher Ryan; The ATLAS collaboration

2018-01-01

The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. First prototypes of the front-end electronics components show good promise to match the stringent specifications. The off-detector electronics will make use of FPGAs connected through high-speed links to perform energy reconstruction, data reduction and buffering. Results of tests of the first prototypes of front-end components will be presented, along with design studies on the performance of the off-detector readout system.

Total dose effects on ATLAS-SCT front-end electronics

CERN Document Server

Ullán, M; Dubbs, T; Grillo, A A; Spencer, E; Seiden, A; Spieler, H; Gilchriese, M G D; Lozano, M

2002-01-01

Low dose rate effects (LDRE) in bipolar technologies complicate the hardness assurance testing for high energy physics applications. The damage produced in the ICs in the real experiment can be underestimated if fast irradiations are carried out, while experiments done at the real dose rate are usually unpractical due to the still high total doses involved. In this work the sensitivity to LDRE of two bipolar technologies proposed for the ATLAS-SCT experiment at CERN is evaluated, finding one of them free of those effects. (12 refs).

Align the Front End First.

Science.gov (United States)

Perry, Jim

1995-01-01

Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

FELIX: the new detector readout system for the ATLAS experiment

CERN Document Server

ATLAS TDAQ Collaboration; The ATLAS collaboration

2017-01-01

Starting during the upcoming major LHC shutdown from 2019-2021, the ATLAS experiment at CERN will move to the the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. The FELIX system is being developed using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card hosting GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. FELIX functions will be implemented with dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software. On the network side, FELIX is able to connect to both Ethernet or Infiniband network a...

FELIX: the new detector readout system for the ATLAS experiment

CERN Document Server

Bauer, Kevin Thomas; The ATLAS collaboration

2018-01-01

Starting during the upcoming major LHC shutdown from 2019-2021, the ATLAS experiment at CERN will move to the the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. The FELIX system is being developed using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card hosting GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. FELIX functions will be implemented with dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software. On the network side, FELIX is able to connect to both Ethernet or Infiniband network a...

FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

DEFF Research Database (Denmark)

Aagaard, Annabeth

2017-01-01

This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

CMOS front-end electronics for radiation sensors

CERN Document Server

AUTHOR|(CDS)2071026

2015-01-01

This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

Upgrading the Atlas Tile Calorimeter Electronics

CERN Document Server

Popeneciu, G; The ATLAS collaboration

2014-01-01

Tile Calorimeter is the central hadronic calorimeter of the ATLAS experiment at LHC. Around 2024, after the upgrade of the LHC the peak luminosity will increase by a factor of 5 compared to the design value, thus requiring an upgrade of the Tile Calorimeter readout electronics. Except the photomultipliers tubes (PMTs), most of the on- and off-detector electronics will be replaced, with the aim of digitizing all PMT pulses at the front-end level and sending them with 10 Gb/s optical links to the back-end electronics. One demonstrator prototype module is planned to be inserted in Tile Calorimeter in 2015 that will include hybrid electronic components able to probe the new design.

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

2004-01-01

A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

Design and implementation of the ATLAS TRT front end electronics

Science.gov (United States)

Newcomer, Mitch; Atlas TRT Collaboration

2006-07-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

Design and implementation of the ATLAS TRT front end electronics

International Nuclear Information System (INIS)

Newcomer, Mitch

2006-01-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

CERN Document Server

The ATLAS collaboration

2014-01-01

This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

Radiation hardness on very front-end for SPD

International Nuclear Information System (INIS)

Cano, Xavier; Graciani, Ricardo; Gascon, David; Garrido, Lluis; Bota, Sebastia; Herms, Atila; Comerma, Albert; Riera, Jordi

2005-01-01

The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available

Two new wheels for ATLAS

CERN Multimedia

2002-01-01

Juergen Zimmer (Max Planck Institute), Roy Langstaff (TRIUMF/Victoria) and Sergej Kakurin (JINR), in front of one of the completed wheels of the ATLAS Hadronic End Cap Calorimeter. A decade of careful preparation and construction by groups in three continents is nearing completion with the assembly of two of the four 4 m diameter wheels required for the ATLAS Hadronic End Cap Calorimeter. The first two wheels have successfully passed all their mechanical and electrical tests, and have been rotated on schedule into the vertical position required in the experiment. 'This is an important milestone in the completion of the ATLAS End Cap Calorimetry' explains Chris Oram, who heads the Hadronic End Cap Calorimeter group. Like most experiments at particle colliders, ATLAS consists of several layers of detectors in the form of a 'barrel' and two 'end caps'. The Hadronic Calorimeter layer, which measures the energies of particles such as protons and pions, uses two techniques. The barrel part (Tile Calorimeter) cons...

Upgrading the ATLAS Tile Calorimeter Electronics

CERN Document Server

Popeneciu, G; The ATLAS collaboration

2014-01-01

The Tile Calorimeter (TileCal) is the central hadronic calorimeter of the ATLAS experiment at LHC. Around 2023, after the upgrade of the LHC (High Luminosity LHC, phase 2) the peak luminosity will increase by a factor of 5 compared to the design value (1034 cm-2 s-1), thus requiring an upgrade of the TileCal readout electronics. Except the 9852 photomultipliers (PMTs), most of the on- and off-detector electronics will be replaced, with the aim of digitizing all PMT pulses at 40 MHz at the front-end level and sending them with 10 Gbps optical links to the back-end electronics. Moreover, to increase reliability, redundancy will be introduced at different levels. Three different options are currently being investigated for the front-end electronics and extensive test beam studies are planned to select the best option. One demonstrator prototype module is also planned to be inserted in TileCal in 2014 that will include hybrid electronic components able to probe the new design, but still compatible with the presen...

Digital front-end electronics for COMPASS Muon-Wall 1 detector

International Nuclear Information System (INIS)

Alekseev, G.D.; Zhuravlev, N.I.; Maggiora, A.

2005-01-01

The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

MMIC tuned front-end for a coherent optical receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

1993-01-01

A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Science.gov (United States)

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

DEFF Research Database (Denmark)

Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

2018-01-01

as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players.......This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...

Single Event Upsets in the ATLAS IBL Front End ASICs

CERN Document Server

Rozanov, Alexandre; The ATLAS collaboration

2018-01-01

During operation at instantaneous luminosities of up to 2.1 1034 cm2 s−1 frontend chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, amongst other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques are presented.

REASONING IN THE FUZZY FRONT END OF INNOVATION:

DEFF Research Database (Denmark)

Haase, Louise Møller; Laursen, Linda Nhu

2018-01-01

in the fuzzy front end is the reasoning process: innovation teams are faced with open-ended, ill-defined problems, where they need to make decisions about an unknown future but have only incomplete, ambiguous and contradicting insights available. We study the reasoning of experts, how they frame to make sense...... of all the insights and create a basis for decision-making in relation to a new project. Based on case studies of five innovative products from various industries, we propose a Product DNA model for understanding the reasoning in the fuzzy front end of innovation. The Product DNA Model explains how...... experts reason and what direct their reasoning....

Terahertz performance of quasioptical front-ends with a hotelectron bolometer

International Nuclear Information System (INIS)

Semenov, A; Richter, H; Guenther, B; Huebers, H-W; Karamarkovic, J

2006-01-01

We present terahertz performance of quasioptical front-ends consisting of a hotelectron bolometer imbedded in a planar feed antenna and integrated with an immersion lens. The impedance and radiation pattern of the log-spiral and double-slot planar feeds are evaluated using the method of moments; the collimating action of the lens is modelled using the physical optics. The total efficiency of the front-ends is computed taking into account frequency dependent impedance of the bolometer. Measured performance of the front-ends qualifies the simulation technique as a reliable tool for the design of terahertz receivers

Decision feedback equalization for radiation hard data link at 5 Gbps

International Nuclear Information System (INIS)

Wallängen, V.; Garcia-Sciveres, M.

2017-01-01

The increased particle collision rate following the upgrade of the Large Hadron Collider (LHC) to an increased luminosity requires an increased readout data speed, especially for the ATLAS pixel detector, located closest to the particle interaction point. For this reason, during the Phase-II upgrade of the ATLAS experiment the output data speed of the pixel front-end chips will be increased from 160 Mbps to 5 Gbps. The increased radiation levels will require a radiation hard data transmission link to be designed to carry this data from the pixel front-end to the off-detector system where it will undergo optical conversion. We propose a receiver utilizing the concept of Decision Feedback Equalization (DFE) to be used in this link, where the number of filter taps can be determined from simulations using S-parameter data from measurements of various customized cable prototypes under characterization as candidates to function as transmission medium between the on-chip data driver and the receiver of the link. A dedicated framework has been set up in Matlab to analyze the S-parameter characteristics for the various cable prototypes and investigate the possibilities for signal recovery and maintained signal integrity using DFE, as well as pre-emphasis and different encoding schemes. The simulation results indicate that DFE could be an excellent choice for expanding the system bandwidth to reach required data speeds with minimal signal distortion.

An Alternative Front End Analysis Strategy for Complex Systems

Science.gov (United States)

2014-12-01

missile ( ABM ) system . Patriot is employed in the field through a battalion echelon organizational structure. The line battery is the basic building...Research Report 1981 An Alternative Front End Analysis Strategy for Complex Systems M. Glenn Cobb U.S. Army Research Institute...NUMBER W5J9CQ11D0003 An Alternative Front End Analysis Strategy for Complex Systems 5b. PROGRAM ELEMENT NUMBER 633007 6

ATLAS end-caps 
on the move

CERN Multimedia

2007-01-01

Two delicate and spectacular transport operations have been performed for ATLAS in recent weeks: the first end-cap tracker was installed in its final position, and one of the huge end-caps of the toroid magnet was moved to the top of the experiment’s shaft.

Optimization on fixed low latency implementation of the GBT core in FPGA

Science.gov (United States)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-07-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Optimization on fixed low latency implementation of the GBT core in FPGA

International Nuclear Information System (INIS)

Chen, K.; Chen, H.; Wu, W.; Xu, H.; Yao, L.

2017-01-01

In the upgrade of ATLAS experiment [1], the front-end electronics components are subjected to a large radiation background. Meanwhile high speed optical links are required for the data transmission between the on-detector and off-detector electronics. The GBT architecture and the Versatile Link (VL) project are designed by CERN to support the 4.8 Gbps line rate bidirectional high-speed data transmission which is called GBT link [2]. In the ATLAS upgrade, besides the link with on-detector, the GBT link is also used between different off-detector systems. The GBTX ASIC is designed for the on-detector front-end, correspondingly for the off-detector electronics, the GBT architecture is implemented in Field Programmable Gate Arrays (FPGA). CERN launches the GBT-FPGA project to provide examples in different types of FPGA [3]. In the ATLAS upgrade framework, the Front-End LInk eXchange (FELIX) system [4, 5] is used to interface the front-end electronics of several ATLAS subsystems. The GBT link is used between them, to transfer the detector data and the timing, trigger, control and monitoring information. The trigger signal distributed in the down-link from FELIX to the front-end requires a fixed and low latency. In this paper, several optimizations on the GBT-FPGA IP core are introduced, to achieve a lower fixed latency. For FELIX, a common firmware will be used to interface different front-ends with support of both GBT modes: the forward error correction mode and the wide mode. The modified GBT-FPGA core has the ability to switch between the GBT modes without FPGA reprogramming. The system clock distribution of the multi-channel FELIX firmware is also discussed in this paper.

Sustainability in the front-end of innovation at design agencies

NARCIS (Netherlands)

Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

2013-01-01

In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

Development of the ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

CERN Document Server

Andeen, Timothy; The ATLAS collaboration

2018-01-01

The high-luminosity LHC will provide 5-7 times higher luminosites than the orignal design. An improved readout system of the ATLAS Liquid Argon Calorimeter is needed to readout the 182,500 calorimeter cells at 40 MHz with 16 bit dynamic range in these conditions. Low-noise, low-power, radiation-tolerant and high-bandwidth electronics components are being developed in 65 and 130 nm CMOS technologies. First prototypes of the front-end electronics components show good promise to match the stringent specifications. The off-detector electronics will make use of FPGAs connected through high-speed links to perform energy reconstruction, data reduction and buffering. Results of tests of the first prototypes of front-end components will be presented, along with design studies on the performance of the off-detector readout system.

Completion of the first TRT End-cap

CERN Multimedia

Catinaccio, A; Rohne, O

On July 1, the first end-cap of the ATLAS Transition Radiation Tracker (TRT) was successfully completed in terms of the integration of the wheels assembled in Russia with their front-end electronics. The two groups of the detector, fully assembled and equipped with front-end electronics, were rotated from their horizontal position during stacking to their nominal vertical position, in which they will be integrated with the corresponding end-cap silicon-strip (SCT) detector towards the end of 2005, before installation into ATLAS in spring 2006. After starting the assembly in the SR building one year ago, the TRT team reached this important milestone, which marks the final realization and validation of the engineering concept developed by the CERN DT1 (ex-TA1) and ATT teams. A TRT end-cap consists of two sets of identical and independent wheels. The first type of wheels (type A, 12 wheels, positioned closest to the primary interaction point) contains 6144 radial straws positioned in eight successive layers s...

Performance of the ATLAS hadronic end-cap calorimeter in beam tests

International Nuclear Information System (INIS)

Dowler, B.; Pinfold, J.; Soukup, J.; Vincter, M.; Cheplakov, A.; Datskov, V.; Fedorov, A.; Javadov, N.; Kalinnikov, V.; Kakurin, S.; Kazarinov, M.; Kukhtin, V.; Ladygin, E.; Lazarev, A.; Neganov, A.; Pisarev, I.; Serochkin, E.; Shilov, S.; Shalyugin, A.; Usov, Yu.; Ban, J.; Bruncko, D.; Chytracek, R.; Jusko, A.; Kladiva, E.; Strizenec, P.; Gaertner, V.; Hiebel, S.; Hohlfeld, M.; Jakobs, K.; Koepke, L.; Marschalkowski, E.; Meder, D.; Othegraven, R.; Schaefer, U.; Thomas, J.; Walkowiak, W.; Zeitnitz, C.; Leroy, C.; Mazini, R.; Mehdiyev, R.; Akimov, A.; Blagov, M.; Komar, A.; Snesarev, A.; Speransky, M.; Sulin, V.; Yakimenko, M.; Aderholz, M.; Brettel, H.; Cwienk, W.; Dulny, B.; Fent, J.; Fischer, A.; Haberer, W.; Huber, J.; Huber, R.; Karev, A.; Kiryunin, A.; Kobler, T.; Kurchaninov, L.; Laskus, H.; Lindenmayer, M.; Mooshofer, P.; Oberlack, H.; Salihagic, D.; Schacht, P.; Stenzel, H.; Striegel, D.; Tribanek, W.; Chekulaev, S.; Denisov, S.; Levitsky, M.; Minaenko, A.; Mitrofanov, G.; Moiseev, A.; Pleskatch, A.; Sytnik, V.; Benoit, P.; Hoyle, K.W.; Honma, A.; Maharaj, R.; Oram, C.J.; Pattyn, E.W.; Rosvick, M.; Sbarra, C.; Wellisch, H-P.; Wielers, M.; Birney, P.S.; Dobbs, M.; Fincke-Keeler, M.; Fortin, D.; Hodges, T.A.; Keeler, R.K.; Langstaff, R.; Lefebvre, M.; Lenckowski, M.; McPherson, R.; O'Neil, D.C.; Forbush, D.; Mockett, P.; Toevs, F.; Braun, H.M.; Thadome, J.

2002-01-01

Modules of the ATLAS liquid argon Hadronic End-cap Calorimeter (HEC) were exposed to beams of electrons, muons and pions in the energy range 6≤E≤200 GeV at the CERN SPS. A description of the HEC and of the beam test setup are given. Results on the energy response and resolution are presented and compared with simulations. The ATLAS energy resolution for jets in the end-cap region is inferred and meets the ATLAS requirements

Evaluation of the Ride-Through Capability of an Active-Front-End Adjustable Speed Drive under Real Grid Conditions

DEFF Research Database (Denmark)

Liserre, Marco; Klumpner, Christian; Blaabjerg, Frede

2004-01-01

Better quality of the input currents, unity power factor and regenerative capability are not the only benefits of equipping an Adjustable Speed Drive (ASD) with an active front-end-stage. Controlling the power inflow may enable also the reduction of the dc-link energy storage, which will then lead...... to the replacement of the electrolytic capacitors with film capacitors, which have lower energy density meaning that the volume is similar, but will increase the ASD lifetime. In these circumstances, operation under unbalanced and distorted supply voltage as well as high dynamic operation of the ASD makes...... the control task more challenging. The aim of this paper is to investigate the ride-through capability of an ASD with active front-end under real grid conditions and in view of the minimum dc-link storage. Experiments validate the theoretical analysis....

The CMS Tracker Readout Front End Driver

CERN Document Server

Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

2004-01-01

The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

Prototype ALICE front-end card

CERN Multimedia

Maximilien Brice

2004-01-01

This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

HINS Linac front end focusing system R&D

Energy Technology Data Exchange (ETDEWEB)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

2008-08-01

This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

Front end designs for the 7-GeV advanced photon source

International Nuclear Information System (INIS)

Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

1992-01-01

The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

A digital Front-End and Readout MIcrosystem for calorimetry at LHC

CERN Multimedia

2002-01-01

% RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

Magnet Misalignment Studies for the Front-end of the Neutrino Factory

CERN Document Server

Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

2013-01-01

In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

Parameters-adjustable front-end controller in digital nuclear measurement system

International Nuclear Information System (INIS)

Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

2013-01-01

Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

Next generation of optical front-ends for numerical services - 15387

International Nuclear Information System (INIS)

Fullenbaum, M.; Durieux, A.; Dubroca, G.; Fuss, P.

2015-01-01

Visual Inspection and surveillance technology means in environments exhibiting high levels of gamma and neutron radiation are nowadays fulfilled through the use of analog tubes. The images are thus acquired with analog devices whose vast majority relies on 1 and 2/3 inch imaging formats and deliver native analog images. There is a growing demand for real time image processing and distribution through Ethernet services for quicker and seamless process integration throughout many sectors. This will call for the inception of solid state sensor (CCD, CMOS) to generate numerical native images as the first step and building block towards end to end numerical processing (ICT), assuming these sensors can be hardened or protected in the field of the nuclear industry. On the one hand, these sensor sizes will be significantly reduced (by a factor of 2-3) versus those of the tubes, and on the other hand, one will also be presented with the opportunity of increased spatial resolution, stemming from the high pixel count of the solid state technology, for implementation of new or better services or of enhanced pieces of information for decision making purposes. In order to reap the benefits of such sensors, new optical front-ends will have to be designed. Over and beyond the mere aspects of matching the reduced sensor size to the size of the scenes at stake, optical performances of these front-end will also bear an impact on the whole optical chain applications. As an example, detection and tracking needs will be different from a performance standpoint and the overall performances will have to be balanced out in between the optical front-end, the image format, the image processing software capability, processing speed,...just to name a few. In this paper we will review and explain the missing gaps in order to switch to a full numerical optical chain by focusing on the optical front-end and the associated cost trade-offs. Finally, we will conclude by clearly stating the best

Measurement of Design Process Front-End – Radical Innovation Approach

DEFF Research Database (Denmark)

Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

2014-01-01

The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase...... of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

Optimized capture section for a muon accelerator front end

Directory of Open Access Journals (Sweden)

Hisham Kamal Sayed

2014-07-01

Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

The Data Acquisition and Calibration System for the ATLAS Semiconductor Tracker

CERN Document Server

Abdesselam, A; Barr, A J; Bell, P; Bernabeu, J; Butterworth, J M; Carter, J R; Carter, A A; Charles, E; Clark, A; Colijn, A P; Costa, M J; Dalmau, J M; Demirkoz, B; Dervan, P J; Donega, M; D'Onifrio, M; Escobar, C; Fasching, D; Ferguson, D P S; Ferrari, P; Ferrère, D; Fuster, J; Gallop, B; García, C; González, S; González-Sevilla, S; Goodrick, M J; Gorisek, A; Greenall, A; Grillo, A A; Hessey, N P; Hill, J C; Jackson, J N; Jared, R C; Johannson, P D C; de Jong, P; Joseph, J; Lacasta, C; Lane, J B; Lester, C G; Limper, M; Lindsay, S W; McKay, R L; Magrath, C A; Mangin-Brinet, M; Martí i García, S; Mellado, B; Meyer, W T; Mikulec, B; Minano, M; Mitsou, V A; Moorhead, G; Morrissey, M; Paganis, E; Palmer, M J; Parker, M A; Pernegger, H; Phillips, A; Phillips, P W; Postranecky, M; Robichaud-Véronneau, A; Robinson, D; Roe, S; Sandaker, H; Sciacca, F; Sfyrla, A; Stanecka, E; Stapnes, S; Stradling, A; Tyndel, M; Tricoli, A; Vickey, T; Vossebeld, J H; Warren, M R M; Weidberg, A R; Wells, P S; Wu, S L

2008-01-01

The SemiConductor Tracker (SCT) data acquisition (DAQ) system will calibrate, configure, and control the approximately six million front-end channels of the ATLAS silicon strip detector. It will provide a synchronized bunch-crossing clock to the front-end modules, communicate first-level triggers to the front-end chips, and transfer information about hit strips to the ATLAS high-level trigger system. The system has been used extensively for calibration and quality assurance during SCT barrel and endcap assembly and for performance confirmation tests after transport of the barrels and endcaps to CERN. Operating in data-taking mode, the DAQ has recorded nearly twenty million synchronously-triggered events during commissioning tests including almost a million cosmic ray triggered events. In this paper we describe the components of the data acquisition system, discuss its operation in calibration and data-taking modes and present some detector performance results from these tests.

The data acquisition and calibration system for the ATLAS Semiconductor Tracker

International Nuclear Information System (INIS)

Abdesselam, A; Barr, A J; Demirkoez, B; Barber, T; Carter, J R; Bell, P; Bernabeu, J; Costa, M J; Escobar, C; Butterworth, J M; Carter, A A; Dalmau, J M; Charles, E; Fasching, D; Ferguson, D P S; Clark, A; Donega, M; D'Onifrio, M; Colijn, A-P; Dervan, P J

2008-01-01

The SemiConductor Tracker (SCT) data acquisition (DAQ) system will calibrate, configure, and control the approximately six million front-end channels of the ATLAS silicon strip detector. It will provide a synchronized bunch-crossing clock to the front-end modules, communicate first-level triggers to the front-end chips, and transfer information about hit strips to the ATLAS high-level trigger system. The system has been used extensively for calibration and quality assurance during SCT barrel and endcap assembly and for performance confirmation tests after transport of the barrels and endcaps to CERN. Operating in data-taking mode, the DAQ has recorded nearly twenty million synchronously-triggered events during commissioning tests including almost a million cosmic ray triggered events. In this paper we describe the components of the data acquisition system, discuss its operation in calibration and data-taking modes and present some detector performance results from these tests

The ALICE TPC front end electronics

CERN Document Server

Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

2004-01-01

In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

A CMOS self-powered front-end architecture for subcutaneous event-detector devices

CERN Document Server

Colomer-Farrarons, Jordi

2011-01-01

A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

Optical data links for the ATLAS SCT and Pixel Detector

International Nuclear Information System (INIS)

Gregor, I.M.; Weidberg, A.R.; Lee, S.C.; Chu, M.L.; Teng, P.K.

2001-01-01

ATLAS (The ATLAS Technical Proposal, CERN/LHCC 94-33) is one of the large electronic particle detectors at LHC (The LHC Conceptual Design, Report- The Yellow Book, CERN/AC/95-05(LHC)) which will become operational in 2005. It is planned to use radiation tolerant optical links for the data transfer from the SemiConductor Tracker (SCT) (ATLAS Inner Detector Technical Proposal, CERN/LHCC 97-16 and CERN/LHCC 97-17). and Pixel Detector (ATLAS Pixel Detector Technical Proposal, CERN/LHCC 98-13) systems to the acquisition electronics over a distance up to 140m. The overall architecture and the performance of these optical data links are described. One of the three candidate designs for an on-detector Opto-Package is presented

Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

1994-01-01

In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

Upgraded readout electronics for the ATLAS LAr Calorimeter at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase [1] in 2018, new digital tower builder boards (sTBB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and identifies sig...

Radiological and environmental surveillance in front-end fuel cycle facilities

International Nuclear Information System (INIS)

Khan, A.H.; Sahoo, S.K.; Tripathi, R.M.

2004-01-01

This paper describes the occupational and environmental radiological safety measures associated with the operations of front end nuclear fuel cycle. Radiological monitoring in the facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised

Analog front end circuit design of CSNS beam loss monitor system

International Nuclear Information System (INIS)

Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

2013-01-01

The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

DEFF Research Database (Denmark)

Aagaard, Annabeth

2013-01-01

to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

Integrated X-band FMCW front-end in SiGe BiCMOS

NARCIS (Netherlands)

Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

2010-01-01

An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

Measuring Single Event Upsets in the ATLAS Inner Tracker

CERN Multimedia

CERN. Geneva

2015-01-01

When the HL-LHC starts collecting data, the electronics inside will be subject to massive amounts of radiation. As a result, single event upsets could pose a threat to the ATLAS readout chain. The ABC130, a prototype front-end ASIC for the ATLAS inner tracker, must be tested for its susceptibility to single event upsets.

MUON POLARIZATION EFFECTS IN THE FRONT END OF THE NEUTRINO FACTORY

International Nuclear Information System (INIS)

FERNOW, R.C.; GALLARDO, J.C.; FUKUI, Y.

2000-01-01

The authors summarize the methods used for simulation of polarization effects in the front end of a possible neutrino factory. They first discuss the helicity of muons in the pion decay process. They find that, neglecting acceptance considerations, the average helicity asymptotically approaches a magnitude of 0.185 at large pion momenta. Next they describe the methods used for tracking the spin through the complicated electromagnetic field configurations in the front end of the neutrino factory, including rf phase rotation and ionization cooling channels. Various depolarizing effects in matter are then considered, including multiple Coulomb scattering and elastic scattering from atomic electrons. Finally, they include all these effects in a simulation of a 480 m long, double phase rotation front end scenario

Upgraded Readout Electronics for the ATLAS Liquid Argon Calorimeters at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase cite{pahse1loi} in 2018, new LAr Trigger Digitizer Boards (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and id...

Redesigned front end for the upgrade at CHESS

International Nuclear Information System (INIS)

Headrick, R.L.; Smolenski, K.W.

1996-01-01

We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

Energy Technology Data Exchange (ETDEWEB)

Peschke, Richard

2017-03-15

As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

Characterisation of the ATLAS ITK strips front-end chip and development of EUDAQ 2.0 for the EUDET-style pixel telescopes

International Nuclear Information System (INIS)

Peschke, Richard

2017-03-01

As part of the ATLAS phase-II upgrade a new, all-silicon tracker will be built. The new tracker will consist of silicon pixel sensors and silicon microstrip sensors. For the readout of the microstrip sensor a new readout chip was designed; the so called ATLAS Binary Converter 130 (ABC130) which is based on a 130 nm CMOS technology. The chip consists of an analog Front End built up of 256 channels, each with a preamplifier and a discriminator for converting the analog sensor readout into a binary response. The preamplifier of the ABC130 was designed to have a gain of 90-95 (mV)/(fC). First laboratory measurements with the built-in control circuits have shown a gain of <75 (mV)/(fC). In the course of this thesis a test beam campaign was undertaken to measure the gain in an unbiased system under realistic conditions. The obtained gain varied from ∼90 (mV)/(fC) to ∼100 (mV)/(fC). With this, the values obtained by the test beam campaign are within the specifications. In order to perform the test beam campaign with optimal efficiency, a complete overhaul of the data acquisition framework used for the EUDET type test beam telescopes was necessary. The new version is called EUDAQ 2.0. It is designed to accommodate devices with different integration times such as LHC-type devices with an integration time of only 25 ns, and devices with long integration times such as the MIMOSA26 with an integration time of 114.5 μs. To accomplish this a new synchronization algorithm has been developed. It gives the user full flexibility on the means of synchronizing their own data stream with the system. Beyond this, EUDAQ 2.0 also allows user specific encoding and decoding of data packets. This enables the user to minimize the data overhead and to shift more computation time to the offline stage. To reduce the network overhead EUDAQ 2.0 allows the user to store data locally. The merging is then postponed to the offline stage.

HINS Linac front end focusing system R and D

International Nuclear Information System (INIS)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; Fermilab; Argonne

2008-01-01

This report summarizes current status of an R and D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process

High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

Directory of Open Access Journals (Sweden)

J.-M. Wu

2012-06-01

Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

Electrical performance of ATLAS-SCT KB end-cap modules

CERN Document Server

D'Onofrio, M; Donegà, M; Ferrère, D; Mangin-Brinet, M; Mikulec, B; Weber, M; Ikegami, Y; Kohriki, T; Kondo, T; Terada, S; Unno, Y; Pernegger, H; Roe, S; Wallny, R; Moorhead, G F; Taylor, G; García, J E; Gonzáles, S; Vos, M A; Toczek, B

2003-01-01

The Semiconductor Tracker (SCT) is one of the ATLAS Inner Detector elements which aims to track charged particles in the ATLAS experiment. It consists of four cylindrical layers (barrels) of silicon strip detectors, with nine disks in each of the forward and backward directions. Carbon fibre structures will support a total of 4088 modules, which are the basic functional sub-unit of the SCT. Each module consists of single sided silicon micro-strip detectors glued back to back with a 40 mrad stereo-angle, and attached to a hybrid. The scope of this document is to present the electrical performances of prototype end-cap modules proposed for the ATLAS-SCT, as an alternative to the baseline. The layout of these modules is based on the implementation of the barrel module hybrid in the end-cap geometry. A complete set of electrical measurements is summarized in this paper, including irradiated module tests and beam tests.

Upgrade readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

Data acquisition at the front-end of the Mu3e pixel detector

Energy Technology Data Exchange (ETDEWEB)

Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

2016-07-01

The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

Fast CMOS binary front-end for silicon strip detectors at LHC experiments

CERN Document Server

Kaplon, Jan

2004-01-01

We present the design and the test results of a front-end circuit developed in a 0.25 mu m CMOS technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front-end for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time and two-stage differential discriminator. Particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e/sup -/ ENC has been achieved for 300 mu A bias current in the input transistor, which is comparable with levels achieved in the past for a front-end using bipolar input transistor. The total supply current of the front-end is 600 mu A and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms.

Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

Directory of Open Access Journals (Sweden)

Rendy Setiawan

2017-01-01

Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

A tunable RF Front-End with Narrowband Antennas for Mobile Devices

DEFF Research Database (Denmark)

Bahramzy, Pevand; Olesen, Poul; Madsen, Peter

2015-01-01

desensitization due to the Tx signal. The filters and antennas demonstrate tunability across multiple bands. System validation is detailed for LTE band I. Frequency response, as well as linearity measurements of the complete Tx and Rx front-end chains, show that the system requirements are fulfilled.......In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex filters...

A study on the front-end VME system of BEPC II

International Nuclear Information System (INIS)

Wang Chunhong

2004-01-01

The front-end VME system is not only the heart of the control system, but also a real-time system. This paper describes the component of the front-end VME (Versa Module Eurocard) system including control computer and some related I/O modules. Particularly, the authors present a best solution for the problems about Vx-Works kernel and BSP running on MVME5100. This is a fundamental setup of the BEPC II control system. (author)

A 500μW 5Mbps ULP super-regenerative RF front-end

NARCIS (Netherlands)

Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

2010-01-01

This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

Functional description of APS beamline front ends

International Nuclear Information System (INIS)

Kuzay, T.

1993-02-01

Traditional synchrotron sources were designed to produce bending magnet radiation and have proven to be an essential scientific tool. Currently, a new generation of synchrotron sources is being built that will be able to accommodate a large number of insertion device (ID) and high quality bending magnet (BM) sources. One example is the 7-GeV Advanced Photon Source (APS) now under construction at Argonne National Laboratory. The research and development effort at the APS is designed to fully develop the potential of this new generation of synchrotron sources. Of the 40 straight sections in the APS storage ring, 34 will be available for IDs. The remaining six sections are reserved for the storage ring hardware and diagnostics. Although the ring incorporates 80 BMs, only 40 of them can be used to extract radiation. The accelerator hardware shadows five of these 40 bending magnets, so the maximum number of BM sources on the lattice is 35. Generally, a photon beamline consists of four functional sections. The first section is the ID or the BM, which provides the radiation source. The second section, which is immediately outside the storage ring but inside a concrete shielding tunnel, is the front end, which is designed to control, define, and/or confine the x-ray beam. In the case of the APS, the front ends are designed to confine the photon beam. The third section, just outside the concrete shielding tunnel and on the experimental floor, is the first optics enclosure, which contains optics to filter and monochromatize the photon beam. The fourth section of a beamline consists of beam transports, additional optics, and experiment stations to do the scientific investigations. This document describes only the front ends of the APS beamlines

Radiological and environmental safety in front-end fuel cycle facilities

International Nuclear Information System (INIS)

Puranik, V.D.

2011-01-01

The front end nuclear fuel cycle comprises of mining and processing of beach mineral sands along the southern coast of Kerala, Tamilnadu and Orissa, mining and processing of uranium ore in Singhbhum-East in Jharkhand and refining and fuel fabrication at Hyderabad. The Health Physics Units (HPUs)/Environmental Survey Laboratories (ESLs) set up at each site from inception of operation to carry out regular in-plant, personnel monitoring and environmental surveillance to ensure safe working conditions, evaluate radiation exposure of workers, ensure compliance with statutory norms, help in keeping the environmental releases well within the limits and advise appropriate control measures. This paper describes the occupational and environmental radiological safety measures associated with the operations of front end of nuclear fuel cycle. Radiological monitoring in these facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised in this paper

Front-end electronics for multichannel semiconductor detector systems

CERN Document Server

Grybos, P

2010-01-01

Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

Commissioning Test of ATLAS End-Cap Toroidal Magnets

CERN Document Server

Dudarev, A; Foussat, A; Benoit, P; Jeckel, M; Olyunin, A; Kopeykin, N; Stepanov, V; Deront, L; Olesen, G; Ponts, X; Ravat, S; Sbrissa, K; Barth, J; Bremer, J; Delruelle, J; Metselaar, J; Pengo, R; Pirotte, O; Buskop, J; Baynham, D E; Carr, F S; Holtom, E

2009-01-01

The system of superconducting toroids in the ATLAS experiment at CERN consists of three magnets. The Barrel Toroid was assembled and successfully tested in 2006. Next, two End-Cap Toroids have been tested on surface at 77 K and installed in the cavern, 100-m underground. The End Cap Toroids are based on Al stabilized Nb-Ti/Cu Rutherford cables, arranged in double pancake coils and conduction cooled at 4.6 K. The nominal current is 20.5 kA at 4.1 T peak field in the windings and the stored energy is 250 MJ per toroid. Prior to final testing of the entire ATLAS Toroidal system, each End Cap Toroid passed a commissioning test up to 21 kA to guarantee a reliable performance in the final assembly. In this paper the test results are described. It includes the stages of test preparation, isolation vacuum pumping and leak testing, cooling down, step-by-step charging to full current, training quenches and quench recovery. By fast discharges the quench detection and protection system was checked to demonstrate a safe e...

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

Science.gov (United States)

Prele, D.

2015-08-01

As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

International Nuclear Information System (INIS)

Prele, D.

2015-01-01

As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

Resource intensities of the front end of the nuclear fuel cycle

International Nuclear Information System (INIS)

Schneider, E.; Phathanapirom, U.; Eggert, R.; Collins, J.

2013-01-01

This paper presents resource intensities, including direct and embodied energy consumption, land and water use, associated with the processes comprising the front end of the nuclear fuel cycle. These processes include uranium extraction, conversion, enrichment, fuel fabrication and depleted uranium de-conversion. To the extent feasible, these impacts are calculated based on data reported by operating facilities, with preference given to more recent data based on current technologies and regulations. All impacts are normalized per GWh of electricity produced. Uranium extraction is seen to be the most resource intensive front end process. Combined, the energy consumed by all front end processes is equal to less than 1% of the electricity produced by the uranium in a nuclear reactor. Land transformation and water withdrawals are calculated at 8.07 m 2 /GWh(e) and 1.37x10 5 l/GWh(e), respectively. Both are dominated by the requirements of uranium extraction, which accounts for over 70% of land use and nearly 90% of water use

Report on the value engineering workshop on APS beamline front ends

International Nuclear Information System (INIS)

Kuzay, T.

1993-01-01

A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

Front-end electronics for accurate energy measurement of double beta decays

International Nuclear Information System (INIS)

Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

2012-01-01

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

Upgrading the ATLAS Tile Calorimeter electronics

CERN Document Server

Oreglia, M; The ATLAS collaboration

2013-01-01

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the most central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The main upgrade will occur for the High Luminosity LHC phase (phase 2) which is scheduled around 2022. The upgrade aims at replacing the majority of the on- and off- detector electronics so that all calorimeter signals are directly digitized and sent to the off-detector electronics in the counting room. An ambitious upgrade development program is pursued studying different electronics options. Three different options are presently being investigated for the front-end electronic upgrade. Which one to use will be decided after extensive test beam studies. High speed optical links are used to read out all digitized data to the counting room. For the off-detector electronics a new back-end architecture is being developed, including the initial trigger processing and pipeline memories. A demonstrator prototype read-out for a slice of the ...

Digital front-end module (DFEM) series; Digital front end module (DFEM) series

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

Directory of Open Access Journals (Sweden)

Carey-Smith Bruce E

2005-01-01

Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

Front end of the nuclear fuel cycle: options to reduce the risks of terrorism and proliferation

International Nuclear Information System (INIS)

Greenberg, E.V.C.; Hoenig, M.M.

1987-01-01

The authors' assessment of the prospects for advanced front end technologies and fuel assurances becoming effective mechanisms for achieving nonproliferation and antiterrorism objectives is relatively pessimistic unless they are integrated with back end accommodations such as the return of spent fuel. They recommend that further examination of front end assurances be linked to that accommodation. To be sure, certain real technological improvements may postpone the day when commercial use of nuclear explosive fuels, with all their attendant terrorism and proliferation risks, is justified. Indeed, improvements in LWRs, using well-understood technology combined with advanced enrichment techniques, could reduce uranium requirements up to 45% at the beginning of the next century and up to 30% a decade earlier, provided the economic and security incentives are present. On the institutional side, existing supply conditions put little pressure on importing countries to seek long-term supply assurances. Moreover, the political obstacles to creating new international institutions or arrangements are exceedingly difficult to overcome, especially without a heightened consciousness of the growing risks of civilian explosive nuclear materials and the political will to make these risks a high priority. 2 tables

The ATLAS Liquid Argon Calorimeter: Construction, Integration, Commissioning

International Nuclear Information System (INIS)

Aleksa, Martin

2006-01-01

The ATLAS liquid argon (LAr) calorimeter system consists of an electromagnetic barrel calorimeter and two end caps with electromagnetic, hadronic and forward calorimeters. The liquid argon sampling technique, with an accordion geometry was chosen for the barrel electromagnetic calorimeter (EMB) and adapted to the end cap (EMEC). The hadronic end cap calorimeter (HEC) uses a copper-liquid argon sampling technique with flat plate geometry and is subdivided in depth in two wheels per end-cap. Finally, the forward calorimeter (FCAL) is composed of three modules employing cylindrical electrodes with thin liquid argon gaps.The construction of the full calorimeter system is complete since mid-2004. Production modules constructed in the home institutes were integrated into wheels at CERN in 2003-2004, and inserted into the three cryostats. They passed their first complete cold test before the lowering into the ATLAS cavern. Results of quality checks (e.g. electrical, mechanical, ...) performed on all the 190304 read-out channels after cool down will be reported. End 2004 the ATLAS barrel electromagnetic (EM) calorimeter was installed in the ATLAS cavern and since summer 2005 the front-end electronics are being connected and tested. Results of this first commissioning phase will be shown to demonstrate the high standards of quality control for our detectors

A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

CERN Document Server

Liu, T; The ATLAS collaboration

2011-01-01

The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. This upgrade calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. In this paper, we present the design and test results of a single channel 16:1 serializer and the design of a double-channel 16:1 serializer. Both designs are based on a commercial 0.25 μm silicon-on-sapphire CMOS technology. The single channel serializer consists of a serializing unit, a PLL clock generator and a line driver implemented in current mode logic (CML). The serializing unit multiplexes 16 bit parallel LVDS data into 1-bit width serial CMOS data. The serializing unit is composed of a cascade of 2:1 multiplexing circuits based on static D-flip-fl...

Managing Controversies in the Fuzzy Front End

DEFF Research Database (Denmark)

Christiansen, John K.; Gasparin, Marta

2016-01-01

. The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... for new solutions in the unpredictable non-linear processes. The study uses an ethnographic approach using qualitative data from interviews, company documents, external communication and marketing material, minutes of meetings, informal conversations and observations. The analysis of four FFE processes...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

Upgraded Readout and Trigger Electronics for the ATLAS Liquid Argon Calorimeter at the LHC at the Horizons 2018-2022

CERN Document Server

Oliveira Damazio, Denis; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

Upgraded Readout and Trigger Electronics for the ATLAS Liquid-Argon Calorimeters at the LHC at the Horizons 2018-2022

CERN Document Server

Damazio, D O; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

International Nuclear Information System (INIS)

Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

2012-01-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

Web-based DAQ systems: connecting the user and electronics front-ends

International Nuclear Information System (INIS)

Lenzi, Thomas

2016-01-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Web-based DAQ systems: connecting the user and electronics front-ends

Science.gov (United States)

Lenzi, Thomas

2016-12-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Calibration method for direct conversion receiver front-ends

Directory of Open Access Journals (Sweden)

R. Müller

2008-05-01

Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

Modern design of a fast front-end computer

Science.gov (United States)

Šoštarić, Z.; Anic̈ić, D.; Sekolec, L.; Su, J.

1994-12-01

Front-end computers (FEC) at Paul Scherrer Institut provide access to accelerator CAMAC-based sensors and actuators by way of a local area network. In the scope of the new generation FEC project, a front-end is regarded as a collection of services. The functionality of one such service is described in terms of Yourdon's environment, behaviour, processor and task models. The computational model (software representation of the environment) of the service is defined separately, using the information model of the Shlaer-Mellor method, and Sather OO language. In parallel with the analysis and later with the design, a suite of test programmes was developed to evaluate the feasibility of different computing platforms for the project and a set of rapid prototypes was produced to resolve different implementation issues. The past and future aspects of the project and its driving forces are presented. Justification of the choice of methodology, platform and requirement, is given. We conclude with a description of the present state, priorities and limitations of our project.

FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

Energy Technology Data Exchange (ETDEWEB)

DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

2007-10-27

We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

An ATLAS inner detector end-cap is placed in its cryostat

CERN Multimedia

2007-01-01

The instrumentation housed inside the inner end-cap must be kept cool to avoid thermal noise. This cooling is achieved on ATLAS by placing the end-cap inside a liquid argon cryostat. The end-cap measures particles that are produced close to the direction of the beam pipe and would otherwise be missed.

High-density digital links optimization of signal integrity and noise performance of the high-density digital links of the ATLAS-TRT readout system

International Nuclear Information System (INIS)

Mandl, M.

2000-02-01

The TRT - Transition Radiation Tracker - is a sub detector of the particle detector ATLAS - A Toroidal LHC ApparatuS. About 420,000 detecting elements are distributed over 22 m3. They produce each second approximately 20 Tbit of data, which has to be transferred from the front-end electronics inside the detector to the back-end electronics outside the detector for further processing. The task of this thesis is to guarantee the integrity of the signals and the electromagnetic compatibility inside the TRT as well as to the aggressive surroundings. The electromagnetic environment of particle detectors in high-energy physics adds special constraints to the high data rates and the high complexity: high sensibility of the detecting elements and their pre amplifiers, confined space, limited material budget, a radioactive environment, and high static magnetic fields. Thus many industrial standard measures have to be abandoned. Special design is essential to compensate this disadvantage. (author)

High-Density Digital Links Optimization of Signal Integrity and Noise Performance of the High-Density Digital Links of the ATLAS-TRT Readout System

CERN Document Server

Mandl, M

2000-01-01

The Transition Radiation Tracker (TRT) is a sub detector of the particle detector ATLAS (A Toroidal LHC ApparatuS). About 420,000 detecting elements are distributed over 22 m3. They produce each second approximately 20 Tbit of data which has to be transferred from the front-end electronics inside the detector to the back-end electronics outside the detector for further processing. The task of this thesis is to guarantee the integrity of the signals and the electromagnetic compatibility inside the TRT as well as to the aggressive surroundings. The electromagnetic environment of particle detectors in high-energy physics adds special constraints to the high data rates and the high complexity: high sensibility of the detecting elements and their pre amplifiers, confined space, limited material budget, a radioactive environment, and high static magnetic fields. Thus many industrial standard measures have to be abandoned. Special design is essential to compensate this disadvantage.

New Persistent Back-End for the ATLAS Online Information Service

CERN Document Server

Soloviev, I; The ATLAS collaboration

2014-01-01

The Trigger and Data Acquisition (TDAQ) and detector systems of the ATLAS experiment deploy more than 3000 computers, running more than 15000 concurrent processes, to perform the selection, recording and monitoring of the proton collisions data in ATLAS. Most of these processes produce and share operational monitoring data used for inter-process communication and analysis of the systems. Few of these data are archived by dedicated applications into conditions and histogram databases. The rest of the data remained transient and lost at the end of a data taking session. To save these data for later, offline analysis of the quality of data taking and to help investigating the behavior of the system by experts, the first prototype of a new Persistent Back-End for the Atlas Information System of TDAQ (P-BEAST) was developed and deployed in the second half of 2012. The modern, distributed, and Java-based Cassandra database has been used as the storage technology and the CERN EOS for long-term storage. This paper pr...

General design of the layout for new undulator-only beamline front ends

International Nuclear Information System (INIS)

Shu Deming; Ramanathan, Mohan; Kuzay, Tuncer M.

2001-01-01

A great majority of the Advanced Photon Source (APS) users have chosen an undulator as the only source for their insertion device beamline. Compared with a wiggler source, the undulator source has a much smaller horizontal divergence, providing us with an opportunity to optimize the beamline front-end design further. In this paper, the particular designs and specifications, as well as the optical and bremsstrahlung ray-tracing analysis of the new APS front ends for undulator-only operation are presented

A socio-internactive framework for the fuzzy front end

NARCIS (Netherlands)

Smulders, Frido E.; van den Broek, Egon; van der Voort, Mascha C.; Fernandes, A.; Teixeira, A.; Natal Jorge, R.

2007-01-01

This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary socio-interactive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive

Hierarchical Control of the ATLAS Experiment

CERN Document Server

Barriuso-Poy, Alex; Llobet-Valero, E

2007-01-01

Control systems at High Energy Physics (HEP) experiments are becoming increasingly complex mainly due to the size, complexity and data volume associated to the front-end instrumentation. In particular, this becomes visible for the ATLAS experiment at the LHC accelerator at CERN. ATLAS will be the largest particle detector ever built, result of an international collaboration of more than 150 institutes. The experiment is composed of 9 different specialized sub-detectors that perform different tasks and have different requirements for operation. The system in charge of the safe and coherent operation of the whole experiment is called Detector Control System (DCS). This thesis presents the integration of the ATLAS DCS into a global control tree following the natural segmentation of the experiment into sub-detectors and smaller sub-systems. The integration of the many different systems composing the DCS includes issues such as: back-end organization, process model identification, fault detection, synchronization ...

Level-1 Data Driver Card of the ATLAS New Small Wheel upgrade compatible with the Phase II 1 MHz readout scheme

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00549793; The ATLAS collaboration

2016-01-01

The Level-1 Data Driver Card (L1DDC) will be designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 data along with monitoring data and transmits them to a network interface through a single bidirectional fiber link. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach 1 MHz. This paper describes the overall scheme of the data acquisition process and especially the three different L1DDC boards that will be fabricated. Moreover the L1DDC prototype-1 is also described.

A Readout Driver for the ATLAS LAr Calorimeter at a High Luminosity LHC

CERN Document Server

Kielburg-Jeka, A; The ATLAS collaboration

2010-01-01

A new readout driver (ROD) is being developed as a central part of the signal processing of the ATLAS liquid-argon calorimeters for operation at the sLHC. In the architecture of the upgraded readout system, the ROD modules will have several challenging tasks: receiving of up to 1.4 Tb/s of data per board from the detector front-end on multiple high-speed serial links, low-latency data processing, data buffering, and data transmission to the ATLAS trigger and DAQ systems. In order to evaluate the different components, prototype boards in ATCA format equipped with modern Xilinx and Altera FPGAs have been built. We will report on the measured performance of the SERDES devices, the parallel signal processing using DSP slices, the implementation of trigger interfaces, using e.g. multi-Gb Ethernet, as well as the development of the ATCA infrastructure on the ROD prototype modules.

A Readout Driver for the ATLAS LAr Calorimeter at a High Luminosity LHC

CERN Document Server

Kielburg-Jeka, A

2011-01-01

A new readout driver (ROD) is being developed as a central part of the signal processing of the ATLAS liquid-argon calorimeters for operation at the High Luminosity LHC (HL-LHC). In the architecture of the upgraded readout system, the ROD modules will have several challenging tasks: receiving of up to 1.4 Tb/s of data per board from the detector front-end on multiple high-speed serial links, low-latency data processing, data buffering, and data transmission to the ATLAS trigger and DAQ systems. In order to evaluate the different components, prototype boards in ATCA format equipped with modern Xilinx and Altera FPGAs have been built. We will report on the measured performance of the SERDES devices, the parallel signal processing using DSP slices, the implementation of trigger interfaces, using e.g. multi-Gb Ethernet, as well as the development of the ATCA infrastructure on the ROD prototype modules.

Moving one of the ATLAS end-cap calorimeters

CERN Multimedia

Claudia Marcelloni

2007-01-01

One of the end-cap calorimeters for the ATLAS experiment is moved using a set of rails. This calorimeter will measure the energy of particles that are produced close to the axis of the beam when two protons collide. It is kept cool inside a cryostat to allow the detector to work at maximum efficiency.

Progress with the SNS front-end systems

International Nuclear Information System (INIS)

Keller, R.; Abraham, W.; Ayers, J.J.; Cheng, D.W.; Cull, P.; DiGennaro, R.; Doolittle, L.; Gough, R.A.; Greer, J.B.; Hoff, M.D.; Leung, K.N.; Lewis, S.; Lionberger, C.; MacGill, R.; Minamihara, Y.; Monroy, M.; Oshatz, D.; Pruyn, J.; Ratti, A.; Reijonen, J.; Schenkel, T.; Staples, J.W.; Syversrud, D.; Thomae, R.; Virostek, S.; Yourd, R.

2001-01-01

The Front-End Systems (FES) of the Spallation Neutron Source (SNS) project have been described in detail elsewhere [1]. They comprise an rf-driven H - ion source, electrostatic LEBT, four-vane RFQ, and an elaborate MEBT. These systems are planned to be delivered to the SNS facility in Oak Ridge in June 2002. This paper discusses the latest design features, the status of development work, component fabrication and procurements, and experimental results with the first commissioned beamline elements

Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A M

1992-01-01

Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...... available GaInAs/InP pin photo diode. The procedure for measuring the transimpedance and the equivalent input noise current density is outlined in this paper and demonstrated using one of the MMICs. The MMICs were fabricated using the Plessey F20 process by GEC-Marconi through the ESPRIT programme EUROCHIP...

Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

International Nuclear Information System (INIS)

Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

2013-01-01

New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

Development of ATLAS Liquid Argon Calorimeter Readout Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00567140; The ATLAS collaboration

2017-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. To be able to retain interesting physics events even at rather low transverse energy scales, increased trigger rates are foreseen for the ATLAS detector. At the hardware selection stage acceptance rates of 1 MHz are planned, combined with longer latencies up to 60 micro-seconds in order to read out the necessary data from all detector channels. Under these conditions, the current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons a replacement of the LAr front-end and back-end readout system is foreseen for all 182,500 readout channels, with the exception of t...

VME as a front-end electronics system in high energy physics experiments

International Nuclear Information System (INIS)

Ohska, T.K.

1990-01-01

It is only a few years since the VME became a standard system, yet the VME system is already so much more popular than other systems. The VME system was developed for industrial applications and not for the scientific research, and high energy physics field is a tiny market when compared with the industrial market. Considerations made here indicate that the VME system would be a good one for a rear-end system, but would not be a good candidate for front-end electronics in physics experiments. Furthermore, there is a fear that the VXI bus could become popular in this field of instrumentation since the VXI system is backed up by major suppliers of instrumentation in the high energy physics field. VXI would not be an adequate system for front-end electronics, yet advertised to be one. It would be worse to see the VXI system to become a standard system for high energy physics instrumentation than the VME system to be one. The VXI system would do a mediocre job so that people might be misled to think that the VXI system can be used as front-end system. (N.K.)

Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

Energy Technology Data Exchange (ETDEWEB)

Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

2015-09-01

This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

2015-07-01

The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

International Nuclear Information System (INIS)

Havranek, Miroslav

2014-09-01

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Havranek, Miroslav

2014-09-15

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

InP DHBT MMICs for millimeter-wave front-ends

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

2009-01-01

In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

CERN Document Server

Cadeddu, S; Lai, A

2004-01-01

We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

ATLAS Transition Region Upgrade at Phase-1

CERN Document Server

Song, H; The ATLAS collaboration

2014-01-01

This report presents the L1 Muon trigger transition region (1.0<|ƞ|<1.3) upgrade of ATLAS Detector at phase-1. The high fake trigger rate in the Endcap region 1.0<|ƞ|<2.4 would become a serious problem for the ATLAS L1 Muon trigger system at high luminosity. For the region 1.3<|ƞ|<2.4, covered by the Small Wheel, ATLAS is enhancing the present muon trigger by adding local fake rejection and track angle measurement capabilities. To reduce the rate in the remaining ƞ interval it has been proposed a similar enhancement by adding at the edge of the inner barrel a structure of 3-layers RPCs of a new generation. These RPCs will be based on a thinner gas gap and electrodes with respect to the ATLAS standards, a new high performance Front End, integrating fast TDC capabilities, and a new low profile and light mechanical structure allowing the installation in the tiny space available.This design effectively suppresses fake triggers by making the coincidence with both end-cap and interaction point...

Single-current-sensor-based active front-end-converter-fed four ...

Indian Academy of Sciences (India)

Joseph Kiran Banda

Keywords. Field-oriented control; vector control of induction motor; active front end converter; power factor correction .... sinusoidal three-phase input currents applied to the stator. ... with necessary feed-forward terms are employed to control.

Novel Front-end Electronics for Time Projection Chamber Detectors

CERN Document Server

García García, Eduardo José

This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

DEFF Research Database (Denmark)

Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

2015-01-01

A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not ...... together with a positive-sequence current controller for the front-end rectifier. A gain in the feedforward term can be changed to control the negative-sequence current. Simulation results are presented to verify the theory....

ATLAS DataFlow Infrastructure recent results from ATLAS cosmic and first-beam data-taking

CERN Document Server

Vandelli, W

2010-01-01

The ATLAS DataFlow infrastructure is responsible for the collection and conveyance of event data from the detector front-end electronics to the mass storage. Several optimized and multi-threaded applications fulfill this purpose operating over a multi-stage Gigabit Ethernet network which is the backbone of the ATLAS Trigger and Data Acquisition System. The system must be able to efficiently transport event-data with high reliability, while providing aggregated bandwidths larger than 5 GByte/s and coping with many thousands network connections. Nevertheless, routing and streaming capabilities and monitoring and data accounting functionalities are also fundamental requirements. During 2008, a few months of ATLAS cosmic data-taking and the first experience with the LHC beams provided an unprecedented testbed for the evaluation of the performance of the ATLAS DataFlow, in terms of functionality, robustness and stability. Besides, operating the system far from its design specifications helped in exercising its fle...

Vacuum tests of a beamline front-end mock-up at the Advanced Photon Source

International Nuclear Information System (INIS)

Liu, C.; Nielsen, R.W.; Kruy, T.L.; Shu, D.; Kuzay, T.M.

1994-01-01

A-mock-up has been constructed to test the functioning and performance of the Advanced Photon Source (APS) front ends. The mock-up consists of all components of the APS insertion-device beamline front end with a differential pumping system. Primary vacuum tests have been performed and compared with finite element vacuum calculations. Pressure distribution measurements using controlled leaks demonstrate a better than four decades of pressure difference between the two ends of the mock-up. The measured pressure profiles are consistent with results of finite element analyses of the system. The safety-control systems are also being tested. A closing time of ∼20 ms for the photon shutter and ∼7 ms for the fast closing valve have been obtained. Experiments on vacuum protection systems indicate that the front end is well protected in case of a vacuum breach

A High-Frequency Isolation (HFI Charging DC Port Combining a Front-End Three-Level Converter with a Back-End LLC Resonant Converter

Directory of Open Access Journals (Sweden)

Guowei Cai

2017-09-01

Full Text Available The high-frequency isolation (HFI charging DC port can serve as the interface between unipolar/bipolar DC buses and electric vehicles (EVs through the two-power-stage system structure that combines the front-end three-level converter with the back-end logical link control (LLC resonant converter. The DC output voltage can be maintained within the desired voltage range by the front-end converter. The electrical isolation can be realized by the back-end LLC converter, which has the bus converter function. According to the three-level topology, the low-voltage rating power devices can be adapted for half-voltage stress of the total DC grid, and the PWM phase-shift control can double the equivalent switching frequency to greatly reduce the filter volume. LLC resonant converters have advance characteristics of inverter-side zero-voltage-switching (ZVS and rectifier-side zero-current switching (ZCS. In particular, it can achieve better performance under quasi-resonant frequency mode. Additionally, the magnetizing current can be modified following different DC output voltages, which have the self-adaptation ZVS condition for decreasing the circulating current. Here, the principles of the proposed topology are analyzed in detail, and the design conditions of the three-level output filter and high-frequency isolation transformer are explored. Finally, a 20 kW prototype with the 760 V input and 200–500 V output are designed and tested. The experimental results are demonstrated to verify the validity and performance of this charging DC port system structure.

An IPMI-compliant control system for the ATLAS TileCal Phase-II Upgrade PreProcessor module

CERN Document Server

Zuccarello, Pedro Diego; The ATLAS collaboration

2016-01-01

Abstract–The electronics of the hadronic calorimeter of the ATLAS detector (TileCal) is being redesigned as part of the works that will lead to the High Luminosity Large Hadron Collider (HL-LHC). TileCal electronics is divided in front and back-end subsystems. While the front-end is inside the detector, the back-end is located off-detector inserted in an ATCA shelf. The main objective of this paper is to describe the work being carried out in the hardware management aspects of the back-end electronics of TileCal.

11 August 2008 - Member of the House of Councillors M. Naito (The National Diet of Japan, The Democratic Party of Japan) visiting the ATLAS experiment control room with Collaboration Spokesperson P. Jenni and ATLAS Muon Project Leader G. Mikenberg. Family photograph with CERN Japanese scientists in front of the ATLAS surface building.

CERN Multimedia

Maximilien Brice

2008-01-01

11 August 2008 - Member of the House of Councillors M. Naito (The National Diet of Japan, The Democratic Party of Japan) visiting the ATLAS experiment control room with Collaboration Spokesperson P. Jenni and ATLAS Muon Project Leader G. Mikenberg. Family photograph with CERN Japanese scientists in front of the ATLAS surface building.

On-Detector Electronics for the ATLAS TileCal Demonstrator

CERN Document Server

Muschter, Steffen Lothar; The ATLAS collaboration; Anderson, Kelby; Bohm, Christian; Drake, Gary; Oreglia, Mark; Paramonov, Alexander; Tang, Fukun

2014-01-01

In the major upgrade of the LHC and its detectors around year 2023 the beam energy and luminosity will increase significantly. For TileCal, the hadron calorimeter in ATLAS, most of the on-detector and off-detector electronics will be replaced. A new design has been proposed with some alternative solutions for some of the parts. To gain experience with this design, a demonstrator project is on-going aiming at inserting a prototype module in ATLAS this summer or in the next possible shut-down. A caveat is that it must be able to operate seamlessly with the present system. This together with test beam studies will help to finalize the design. The on-detector part of the demonstrator electronics contains five parts: new front-end boards, digitizer boards with a link daughter board, a programmable high voltage power supply and a redundant low voltage power supply. Apart from improved performance reliability is a main concern. This will be achieved by increased modularity so that the consequences of a complete fail...

On-Detector Electronics for the ATLAS TileCal Demonstrator

CERN Document Server

Muschter, Steffen Lothar; The ATLAS collaboration; Akerstedt, Henrik; Anderson, Kelby; Bohm, Christian; Drake, Gary; Oreglia, Mark; Paramonov, Alexander; Tang, Fukun

2016-01-01

In the major upgrade of the LHC and its detectors around year 2023 the beam energy and luminosity will increase significantly. For TileCal, the hadron calorimeter in ATLAS, most of the on-detector and off-detector electronics will be replaced. A new design has been proposed with some alternative solutions for some of the parts. To gain experience with this design, a demonstrator project is on-going aiming at inserting a prototype module in ATLAS this summer or in the next possible shut-down. A caveat is that it must be able to operate seamlessly with the present system. This together with test beam studies will help to finalize the design. The on-detector part of the demonstrator electronics contains five parts: new front-end boards, digitizer boards with a link daughter board, a programmable high voltage power supply and a redundant low voltage power supply. Apart from improved performance reliability is a main concern. This will be achieved by increased modularity so that the consequences of a complete fail...

Prototype ATLAS IBL modules using the FE-I4A front-end readout chip

Czech Academy of Sciences Publication Activity Database

Albert, J.; Alex, M.; Alimonti, G.; Hejtmánek, Martin; Janoška, Zdenko; Korchak, Oleksandr; Popule, Jiří; Šícho, Petr; Sloboda, Michal; Tomášek, Michal; Vrba, Václav

2012-01-01

Roč. 7, NOV (2012), 1-45 ISSN 1748-0221 R&D Projects: GA MŠk LA08032 Institutional research plan: CEZ:AV0Z10100502 Keywords : ATLAS * upgrade * tracker * silicon * FE-I4 * planar sensors * test beam Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.869, year: 2011 http://arxiv.org/abs/arXiv:1209.1906

Pixel electronics for the ATLAS experiment

International Nuclear Information System (INIS)

Fischer, P.

2001-01-01

The ATLAS experiment at LHC will use 3 barrel layers and 2x5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mmx60.8 mm which include an n + on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode the pin diode signal and to drive the VCSEL laser diodes of the optical links

A TTC to Data Acquisition interface for the ATLAS Tile Hadronic calorimeter at the LHC

CERN Document Server

Valero, Alberto; The ATLAS collaboration; Torres Pais, Jose Gabriel; Soret Medel, Jesús

2017-01-01

TileCal is the central tile hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. It is a sampling calorimeter where scintillating tiles are embedded in steel absorber plates. The tiles are read-out using almost 10,000 photomultipliers which convert the light into an electrical signal. These signals are digitized and stored in pipelines memories in the front-end electronics. Upon the reception of a trigger signal, the PMT data is transferred to the Read-Out Drivers in the back-end electronics which process and transmits the processed data to the ATLAS Data AcQuisition (DAQ) system. The Timing, Trigger and Control (TTC) system is an optical network used to distribute the clock synchronized with the accelerator, the trigger signals and configuration commands to both the front-end and back-end electronics components. During physics operation, the TTC system is used to configure the electronics and to distribute trigger information used to synchronize the different parts of the ...

Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

Science.gov (United States)

Spignesi, B.

This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

Upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Moreno, P; The ATLAS collaboration

2016-01-01

The Tile Calorimeter (TileCal) is the central hadronic calorimeter covering the central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC phase (Phase 2) where the peak luminosity will increase 5$\\times$ compared to the design luminosity ($10^{34} cm^{-2}s^{-1}$) but with maintained energy (i.e. 7+7 TeV). The TileCal upgrade aims at replacing the majority of the on- and off-detector electronics to the extent that all calorimeter signals will be digitized and sent to the off-detector electronics in the counting room. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to the counting room while 5 Gbps down-links are used for synchronization, c...

Engineering for the ATLAS SemiConductor Tracker (SCT) End-cap

Energy Technology Data Exchange (ETDEWEB)

Abdesselam, A; Barr, A [Department of Physics, Oxford University, Oxford (United Kingdom); Allport, P P [Department of Physics, Oliver Lodge Laboratory, University of Liverpool, Liverpool (United Kingdom); Anderson, B [Department of Physics, University College, University of London, London (United Kingdom); Andricek, L; Becker, H [Max-Planck-Institut fuer Physik, Muenchen (Germany); Anghinolfi, F [European Laboratory for Particle Physics (CERN), Geneva (Switzerland); Apsimon, R J; Austin, A; Barclay, P; Batchelor, L E; Benes, J [Centro Nacional de Microelectronica de Barcelona, CNM-IMB, CSIC, Barcelona (Spain); Atkinson, T [University of Melbourne, Parkville, Victoria 3052 (Australia); Band, H [NIKHEF, Amsterdam (Netherlands); Bates, R L; Bell, W H [Department of Physics and Astronomy, University of Glasgow, Glasgow (United Kingdom); Batley, J R [Cavendish Laboratory, Cambridge University, Cambridge (United Kingdom); Beck, G; Belymam, A [Department of Physics, Queen Mary and Westfield College, University of London, London (United Kingdom); Bell, P [School of Physics and Astronomy, University of Manchester, Manchester (United Kingdom)], E-mail: S.J.Haywood@rl.ac.uk (and others)

2008-05-15

The ATLAS SemiConductor Tracker (SCT) is a silicon-strip tracking detector which forms part of the ATLAS inner detector. The SCT is designed to track charged particles produced in proton-proton collisions at the Large Hadron Collider (LHC) at CERN at an energy of 14 TeV. The tracker is made up of a central barrel and two identical end-caps. The barrel contains 2112 silicon modules, while each end-cap contains 988 modules. The overall tracking performance depends not only on the intrinsic measurement precision of the modules but also on the characteristics of the whole assembly, in particular, the stability and the total material budget. This paper describes the engineering design and construction of the SCT end-caps, which are required to support mechanically the silicon modules, supply services to them and provide a suitable environment within the inner detector. Critical engineering choices are highlighted and innovative solutions are presented - these will be of interest to other builders of large-scale tracking detectors. The SCT end-caps will be fully connected at the start of 2008. Further commissioning will continue, to be ready for proton-proton collision data in 2008.

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

Science.gov (United States)

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

Energy Technology Data Exchange (ETDEWEB)

Brett Carlsen; Emily Tavrides; Erich Schneider

2010-08-01

Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

International Nuclear Information System (INIS)

Carlsen, Brett; Tavrides, Emily; Schneider, Erich

2010-01-01

Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

The front-end data conversion and readout electronics for the CMS ECAL upgrade

CERN Document Server

Mazza, Gianni

2017-01-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with 13 bit resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed; Ghazzai, Hakim; Kadri, Abdullah; Alouini, Mohamed-Slim

2016-01-01

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed

2016-06-14

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

Front end support systems for the Advanced Photon Source

International Nuclear Information System (INIS)

Barraza, J.; Shu, D.; Kuzay, T.M.

1993-01-01

The support system designs for the Advanced Photon Source (APS) front ends are complete and will be installed in 1994. These designs satisfy the positioning and alignment requirements of the front end components installed inside the storage ring tunnel, including the photon beam position monitors, fixed masks, photon and safety shutters, filters, windows, and differential pumps. Other components include beam transport pipes and ion pumps. The designs comprise 3-point kinematic mounts and single axis supports to satisfy various multi-direction positioning requirements from course to ultra-precise. The confined space inside the storage ring tunnel has posed engineering challenges in the design of these devices, considering some components weigh as much as 500 kg. These challenges include designing for mobility during commissioning and initial alignment, mechanical and thermal stability, and precise low profile vertical and horizontal positioning. As a result, novel stages and kinematic mounts have emerged with modular and standard designs. This paper will discuss the diverse group of support systems, including specifications and performance data of the prototypes

Receiver Front-End Circuits for Future Generations of Wireless Communications

NARCIS (Netherlands)

Sanduleanu, M.A.T.; Vidojkovic - Andjelovic, M.; Vidojkovic, V.; Roermund, van A.H.M.; Tasic, A.

2007-01-01

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in

Beamtest results of ATLAS SCT Modules in 2002

CERN Document Server

Barr, A J; Dolezal, Z; Donega, M; D'Onofrio, M; García, J E; González, S; Horazdovsky, T; Kazi, S; Kodys, P; Moorhead, G F; Reznicek, P; Solar, M; Vos, M; Wallny, R

2004-01-01

Beamtests of ATLAS Semiconductor Tracker (SCT) modules carried out at the ATLAS testbeam facility at the CERN SPS H8. During 2002, three beam runs were carried out in May/June, July and August. In the August 2002 beam test period four irradiated modules, two ``K5'' end-cap and two barrel, with the final design were tested. Module propierties (efficiency, charge collection, signal/noise, pulse shape) and the dependence of them for a particle high incidence angle was studied. A comparison with previous testbeam results was also performed. Time-stamping performance of SCT modules and specially, the effect of irradiation on the time characteristics of the Front End was investigated more closely. On this note we show a summary of these studies.

ATLAS looks forward to having beams!

CERN Multimedia

Hans von der Schmitt

Lyn Evans, head of the LHC project at CERN, brought very good news: all problems are now solved or understood, and barring a disaster, the LHC should see beams in July 2008. The ATLAS overview week (8-12 October) showed impressively that the experiment is getting ready for beams on all fronts. Perhaps that is best seen in the recent runs with cosmic events, which are integrating all ATLAS subsystems. The integration milestone M4 ended just a month ago (see the article in the September issue of ATLAS e-news), exercising for one week the complete chain from detectors - trigger and data acquisition - reconstruction at Tier0 - shipment of data worldwide to Tier1s. Event displays and histograms, available both online and offline, were shown throughout the overview week and are proof that the entire chain is actually working. The integration milestones give an enormous boost to the experiment - next time during M5 end of October. During the week we learned about successes and remaining issues along this ent...

A differential low-voltage high gain current-mode integrated RF receiver front-end

Energy Technology Data Exchange (ETDEWEB)

Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

2011-02-15

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

A Full Front End Chain for Drift Chambers

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Panareo, M. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Primiceri, P. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Tassielli, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Fermilab, Batavia, Illinois (United States); Università Marconi, Roma (Italy)

2014-03-01

We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift tube and represents the outcome of balancing between efficiency and high speed performance.

Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

2015-09-16

The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

International Nuclear Information System (INIS)

Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

1989-05-01

The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs

Design of a low-power 433/915-MHz RF front-end with a current-reuse common-gate LNA

International Nuclear Information System (INIS)

Jing Yiou; Lu Huaxiang

2013-01-01

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier (LNA), current-reuse V—I converter, active double balanced mixer and transimpedance amplifier for short range device (SRD) applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm 2 . Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of −24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption. (semiconductor integrated circuits)

Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

International Nuclear Information System (INIS)

Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

2011-01-01

A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

Energy Technology Data Exchange (ETDEWEB)

Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

2016-07-01

This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

Characterisation of the VMM3 Front-end read-out ASIC

CERN Document Server

Bartels, Lara Maria

2018-01-01

This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

Science.gov (United States)

Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

2016-07-01

Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

PACE3 - front-end chip for the CMS Preshower

CERN Multimedia

Aspel, Paul

2003-01-01

This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

Deep sub-micron FD-SOI for front-end application

International Nuclear Information System (INIS)

Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

2007-01-01

In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

Trends in the design of front-end systems for room temperature solid state detectors

International Nuclear Information System (INIS)

Manfredi, Pier F.; Re, Valerio

2003-01-01

The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors

A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

Front-end and back-end electrochemistry of molten salt in accelerator-driven transmutation systems

International Nuclear Information System (INIS)

Williamson, M.A.; Venneri, F.

1995-01-01

The objective of this work is to develop preparation and clean-up processes for the fuel and carrier salt in the Los Alamos Accelerator-Driven Transmutation Technology molten salt nuclear system. The front-end or fuel preparation process focuses on the removal of fission products, uranium, and zirconium from spent nuclear fuel by utilizing electrochemical methods (i.e., electrowinning). The same method provides the separation of the so-called noble metal fission products at the back-end of the fuel cycle. Both implementations would have important diversion safeguards. The proposed separation processes and a thermodynamic analysis of the electrochemical separation method are presented

The front-end data conversion and readout electronics for the CMS ECAL upgrade

Science.gov (United States)

Mazza, G.; Cometti, S.

2018-03-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with a 13 bits resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring a fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

New RPC front-end electronics for hades

CERN Document Server

Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

2007-01-01

Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

The Majorana Low-noise Low-background Front-end Electronics

Science.gov (United States)

Abgrall, N.; Aguayo, E.; Avignone, F. T.; Barabash, A. S.; Bertrand, F. E.; Boswell, M.; Brudanin, V.; Busch, M.; Byram, D.; Caldwell, A. S.; Chan, Y.-D.; Christofferson, C. D.; Combs, D. C.; Cuesta, C.; Detwiler, J. A.; Doe, P. J.; Efremenko, Yu.; Egorov, V.; Ejiri, H.; Elliott, S. R.; Fast, J. E.; Finnerty, P.; Fraenkle, F. M.; Galindo-Uribarri, A.; Giovanetti, G. K.; Goett, J.; Green, M. P.; Gruszko, J.; Guiseppe, V. E.; Gusev, K.; Hallin, A. L.; Hazama, R.; Hegai, A.; Henning, R.; Hoppe, E. W.; Howard, S.; Howe, M. A.; Keeter, K. J.; Kidd, M. F.; Kochetov, O.; Konovalov, S. I.; Kouzes, R. T.; LaFerriere, B. D.; Leon, J.; Leviner, L. E.; Loach, J. C.; MacMullin, J.; MacMullin, S.; Martin, R. D.; Meijer, S.; Mertens, S.; Nomachi, M.; Orrell, J. L.; O'Shaughnessy, C.; Overman, N. R.; Phillips, D. G.; Poon, A. W. P.; Pushkin, K.; Radford, D. C.; Rager, J.; Rielage, K.; Robertson, R. G. H.; Romero-Romero, E.; Ronquest, M. C.; Schubert, A. G.; Shanks, B.; Shima, T.; Shirchenko, M.; Snavely, K. J.; Snyder, N.; Suriano, A. M.; Thompson, J.; Timkin, V.; Tornow, W.; Trimble, J. E.; Varner, R. L.; Vasilyev, S.; Vetter, K.; Vorren, K.; White, B. R.; Wilkerson, J. F.; Wiseman, C.; Xu, W.; Yakushev, E.; Young, A. R.; Yu, C.-H.; Yumatov, V.

The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope 76Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolution performances. We present here the low-noise low- background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.

Underwater fiber-wireless communication with a passive front end

Science.gov (United States)

Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

2017-11-01

We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

2016-07-11

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

International Nuclear Information System (INIS)

Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

2016-01-01

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

A wideband high-linearity RF receiver front-end in CMOS

NARCIS (Netherlands)

Arkesteijn, V.J.; Klumperink, Eric A.M.; Nauta, Bram

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 μm CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise

Instrument Front-Ends at Fermilab During Run II

Energy Technology Data Exchange (ETDEWEB)

Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

2011-07-13

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Frequency to Voltage Converter Analog Front-End Prototype

Science.gov (United States)

Mata, Carlos; Raines, Matthew

2012-01-01

The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

Instrument front-ends at Fermilab during Run II

International Nuclear Information System (INIS)

Meyer, T; Slimmer, D; Voy, D

2011-01-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Instrument Front-Ends at Fermilab During Run II

International Nuclear Information System (INIS)

Meyer, Thomas; Slimmer, David; Voy, Duane

2011-01-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Front-end data processing using the bit-sliced microprocessor

International Nuclear Information System (INIS)

Machen, D.R.

1979-01-01

A state-of-the-art computing device, based upon the high-speed bit-sliced microprocessor, was developed into hardware for front-end data processing in both control and experiment applications at the Los Alamos Scientific Laboratory. The CAMAC Instrumentation Standard provides the framework for the high-speed hardware, allowing data acquisition and processing to take place at the data source in a CAMAC crate. 5 figures

The upgraded Tevatron front end

International Nuclear Information System (INIS)

Glass, M.; Zagel, J.; Smith, P.; Marsh, W.; Smolucha, J.

1990-01-01

We are replacing the computers which support the CAMAC crates in the Fermilab accelerator control system. We want a significant performance increase, but we still want to be able to service scores of different varieties of CAMAC cards in a manner essentially transparent to console applications software. Our new architecture is based on symmetric multiprocessing. Several processors on the same bus, each running identical software, work simultaneously at satisfying different pieces of a console's request for data. We dynamically adjust the load between the processors. We can obtain more processing power by simply plugging in more processor cards and rebooting. We describe in this paper what we believe to be the interesting architectural features of the new front-end computers. We also note how we use some of the advanced features of the Multibus TM II bus and the Intel 80386 processor design to achieve reliability and expandability of both hardware and software. (orig.)

Initial Measurements On Pixel Detector Modules For The ATLAS Upgrades

CERN Document Server

Gallrapp, C; The ATLAS collaboration

2011-01-01

Sophisticated conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming pixel detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation, which give a first impression on the charge collection properties of the different sensor technologies are presented.

Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

International Nuclear Information System (INIS)

Zhang Meng; Li Zhiqun; Wang Zengqi; Wu Chenjian; Chen Liang

2014-01-01

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about −6 dBm and −3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology. (semiconductor integrated circuits)

BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

DEFF Research Database (Denmark)

Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

2012-01-01

This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...... for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives...... it a significantly higher rate capability than what has been achieved in other instruments used in the study of terrestrial gamma flashes. The front-end electronics for the BGO detector layer in MXGS system also uses fewer components compared to conventional analog front-ends for BGO detectors, thereby increasing...

An inquiry on managers use of decision-making tools in the core front end of the innovation process

DEFF Research Database (Denmark)

Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.

2013-01-01

This paper focuses on the Core Front End (CFE) activities of the innovation process to say, Opportunity Identification and Opportunity Analysis. In the CFE of innovation, several tools are used to facilitate and optimise decisions. To select them, managers of the product development team have...... is chosen and how those tools impact specific performance metrics. From the analyses and hypotheses testing performed, it clearly emerges that there is no link between being aware of basic requirements (inputs/outputs) to appropriately use a certain tool and dimensions such as tools’ effectiveness...

45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

Science.gov (United States)

Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

2012-07-30

In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

The ICARUS Front-end Preamplifier Working at Liquid Argon Temperature

CERN Document Server

Baibussinov, B; Casagrande, F; Cennini, P; Centro, S; Curioni, A; Meng, G; Picchi, P; Pietropaolo, F; Rubbia, C; Sergiampietri, F; Ventura, S

2011-01-01

We describe characteristics and performance of the low-noise front-end preamplifier used in the ICARUS 50-litre liquid Argon Time Projection Chamber installed in the CERN West Area Neutrino Facility during the 1997-98 neutrino runs. The preamplifiers were designed to work immersed in ultra-pure liquid Argon at a temperature of 87K.

Front-End ASICs for 3-D Ultrasound : From Beamforming to Digitization

NARCIS (Netherlands)

Chen, C.

2018-01-01

This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as

Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

DEFF Research Database (Denmark)

Song, Zhanfeng; Tian, Yanjun; Chen, Wei

2016-01-01

This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...

A front-end electronic system for large arrays of bolometers

Science.gov (United States)

Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

2018-02-01

CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

Front-end electronics and readout system for the ILD TPC

CERN Document Server

Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

2015-01-01

A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

Directory of Open Access Journals (Sweden)

Daniele Borio

2015-01-01

Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

Energy Technology Data Exchange (ETDEWEB)

Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

2015-05-15

A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

International Nuclear Information System (INIS)

Nguyen, Viet Phuong; Yim, Man-Sung

2015-01-01

A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities

Front End Loader Operator. Open Pit Mining Job Training Series.

Science.gov (United States)

Savilow, Bill

This training outline for front end loader operators, one in a series of eight outlines, is designed primarily for company training foremen or supervisors and for trainers to use as an industry-wide guideline for heavy equipment operator training in open pit mining in British Columbia. Intended as a guide for preparation of lesson plans both for…

Front end embedded microprocessors in the JET computer-based control system, past, present and future

International Nuclear Information System (INIS)

Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

1987-01-01

A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

Front-End Electronics in calorimetry: from LHC to ILC

International Nuclear Information System (INIS)

De La Taille, Ch.

2009-09-01

This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

An analog integrated front-end amplifier for neural applications

OpenAIRE

Zhou, Zhijun; Warr, Paul

2017-01-01

The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated circuit form, alongside signal leakage into the input bias network. Significantly, this loop t...

High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

Science.gov (United States)

Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

2010-01-01

In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

ATLAS Silicon Microstrip Tracker

CERN Document Server

Haefner, Petra; The ATLAS collaboration

2010-01-01

The SemiConductor Tracker (SCT), made up from silicon micro-strip detectors is the key precision tracking device in ATLAS, one of the experiments at CERN LHC. The completed SCT is in very good shape: 99.3% of the SCT strips are operational, noise occupancy and hit efficiency exceed the design specifications. In the talk the current status of the SCT will be reviewed. We will report on the operation of the detector and observed problems, with stress on the sensor and electronics performance. TWEPP Summary In December 2009 the ATLAS experiment at the CERN Large Hadron Collider (LHC) recorded the first proton- proton collisions at a centre-of-mass energy of 900 GeV and this was followed by the unprecedented energy of 7 TeV in March 2010. The SemiConductor Tracker (SCT) is the key precision tracking device in ATLAS, made up from silicon micro-strip detectors processed in the planar p-in-n technology. The signal from the strips is processed in the front-end ASICS ABCD3TA, working in the binary readout mode. Data i...

Development of Trigger and Readout Electronics for the ATLAS New Small Wheel Detector Upgrade

CERN Document Server

Zhu, Junjie; The ATLAS collaboration

2017-01-01

The planned Phase-I and Phase-II upgrades of the LHC accelerator drastically impacts the ATLAS trigger and trigger rates. A replacement of the ATLAS innermost endcap muon station with a new small wheel (NSW) detector is planned for the second long shutdown period of 2019 - 2020. This upgrade will allow us to maintain a low pT threshold for single muon and excellent tracking capability even after the High-Luminosity LHC upgrade. The NSW detector will feature two new detector technologies, Resistive Micromegas and small-strip Thin Gap Chambers. Both detector technologies will provide trigger and tracking primitives. The total number of trigger and readout channels is about 2.4 millions, and the overall power consumption is expected to be about 75 kW. The electronics design will be implemented in some 8000 front-end boards including the design of four custom front-end ASICs capable to drive trigger and tracking primitives with high speed sterilizers to drive trigger candidates to the backend trigger processor sy...

Developments of the ATLAS pixel detector

International Nuclear Information System (INIS)

Andreazza, Attilio

2004-01-01

The ATLAS silicon pixel detector is the innermost tracking device of the ATLAS experiment at the Large Hardon Collider, consisting of more than 1700 modules for a total sensitive area of about 1.7m2 and over 80 million pixel cells. The concept is a hybrid of front-end chips bump bonded to the pixel sensor. The elementary pixel cell has 50μmx400μm size, providing pulse height information via the time over threshold technique. Prototype devices with oxygenated silicon sensor and rad-hard electronics built in the IBM 0.25μm process have been tested and maintain good resolution, efficiency and timing performances even after receiving the design radiation damage of 1015neq/cm2

Upgrade of ATLAS ITk Pixel Detector

CERN Document Server

Huegging, Fabian; The ATLAS collaboration

2017-01-01

The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenges to the ATLAS tracker. The current inner detector will be replaced with an entirely-silicon inner tracker (ITk) which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation levels are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors and low mass global and local support structures. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the ITk ATLAS Pixel detector developments as well as different layout options will be reviewed.

Status of the Warm Front End of PIP-II Injector Test

Energy Technology Data Exchange (ETDEWEB)

Shemyakin, Alexander [Fermilab; Alvarez, Matthew [Fermilab; Andrews, Richard [Fermilab; Baffes, Curtis [Fermilab; Carneiro, Jean-Paul [Fermilab; Chen, Alex [Fermilab; Derwent, Paul [Fermilab; Edelen, Jonathan [Fermilab; Frolov, Daniil [Fermilab; Hanna, Bruce [Fermilab; Prost, Lionel [Fermilab; Saewert, Gregory [Fermilab; Saini, Arun [Fermilab; Scarpine, Victor [Fermilab; Sista, V. Lalitha [Fermilab; Steimel, Jim [Fermilab; Sun, Ding [Fermilab; Warner, Arden [Fermilab

2017-05-01

The Proton Improvement Plan II (PIP-II) at Fermilab is a program of upgrades to the injection complex. At its core is the design and construction of a CW-compatible, pulsed H⁻ SRF linac. To validate the concept of the front-end of such machine, a test accelerator known as PIP-II Injector Test is under construction. It includes a 10 mA DC, 30 keV H⁻ ion source, a 2 m-long Low Energy Beam Transport (LEBT), a 2.1 MeV CW RFQ, followed by a Medium Energy Beam Transport (MEBT) that feeds the first of 2 cryomodules increasing the beam energy to about 25 MeV, and a High Energy Beam Transport section (HEBT) that takes the beam to a dump. The ion source, LEBT, RFQ, and initial version of the MEBT have been built, installed, and commissioned. This report presents the overall status of the warm front end.

ATLAS DataFlow Infrastructure: Recent results from ATLAS cosmic and first-beam data-taking

Energy Technology Data Exchange (ETDEWEB)

Vandelli, Wainer, E-mail: wainer.vandelli@cern.c

2010-04-01

The ATLAS DataFlow infrastructure is responsible for the collection and conveyance of event data from the detector front-end electronics to the mass storage. Several optimized and multi-threaded applications fulfill this purpose operating over a multi-stage Gigabit Ethernet network which is the backbone of the ATLAS Trigger and Data Acquisition System. The system must be able to efficiently transport event-data with high reliability, while providing aggregated bandwidths larger than 5 GByte/s and coping with many thousands network connections. Nevertheless, routing and streaming capabilities and monitoring and data accounting functionalities are also fundamental requirements. During 2008, a few months of ATLAS cosmic data-taking and the first experience with the LHC beams provided an unprecedented test-bed for the evaluation of the performance of the ATLAS DataFlow, in terms of functionality, robustness and stability. Besides, operating the system far from its design specifications helped in exercising its flexibility and contributed in understanding its limitations. Moreover, the integration with the detector and the interfacing with the off-line data processing and management have been able to take advantage of this extended data taking-period as well. In this paper we report on the usage of the DataFlow infrastructure during the ATLAS data-taking. These results, backed-up by complementary performance tests, validate the architecture of the ATLAS DataFlow and prove that the system is robust, flexible and scalable enough to cope with the final requirements of the ATLAS experiment.

ATLAS DataFlow Infrastructure: Recent results from ATLAS cosmic and first-beam data-taking

International Nuclear Information System (INIS)

Vandelli, Wainer

2010-01-01

The ATLAS DataFlow infrastructure is responsible for the collection and conveyance of event data from the detector front-end electronics to the mass storage. Several optimized and multi-threaded applications fulfill this purpose operating over a multi-stage Gigabit Ethernet network which is the backbone of the ATLAS Trigger and Data Acquisition System. The system must be able to efficiently transport event-data with high reliability, while providing aggregated bandwidths larger than 5 GByte/s and coping with many thousands network connections. Nevertheless, routing and streaming capabilities and monitoring and data accounting functionalities are also fundamental requirements. During 2008, a few months of ATLAS cosmic data-taking and the first experience with the LHC beams provided an unprecedented test-bed for the evaluation of the performance of the ATLAS DataFlow, in terms of functionality, robustness and stability. Besides, operating the system far from its design specifications helped in exercising its flexibility and contributed in understanding its limitations. Moreover, the integration with the detector and the interfacing with the off-line data processing and management have been able to take advantage of this extended data taking-period as well. In this paper we report on the usage of the DataFlow infrastructure during the ATLAS data-taking. These results, backed-up by complementary performance tests, validate the architecture of the ATLAS DataFlow and prove that the system is robust, flexible and scalable enough to cope with the final requirements of the ATLAS experiment.

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

CERN Document Server

Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

2015-01-01

front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

Initial Measurements on Pixel Detector Modules for the ATLAS Upgrades

CERN Document Server

Gallrapp, C; The ATLAS collaboration

2011-01-01

Delicate conditions in terms of peak and integrated luminosity in the Large Hadron Collider (LHC) will raise the ATLAS Pixel Detector to its performance limits. Silicon planar, silicon 3D and diamond pixel sensors are three possible sensor technologies which could be implemented in the upcoming Pixel Detector upgrades of the ATLAS experiment. Measurements of the IV-behavior and measurements with radioactive Americium-241 and Strontium-90 are used to characterize the sensor properties and to understand the interaction between the ATLAS FE-I4 front-end chip and the sensor. Comparisons of results from before and after irradiation for silicon planar and 3D pixel sensors, which give a first impression on the charge collection properties of the different sensor technologies, are presented.

Contribution to the ATLAS B-field 3D model

International Nuclear Information System (INIS)

Vorozhtsov, S.B.; Titkova, I.V.; Nessi, M.

1996-01-01

The results from the simplified Tile-Cal B-field models calculations are presented. The effects of glue gaps, end plates, front plates, laminated iron layer near girder, 2 mm iron layers between tiles have been estimated. An interpretation of the existing field measurements of the TileCal segments is fulfilled. Some proposals for the general ATLAS B-field map calculation are given. 12 refs., 10 figs

The hybridized front end electronics of the Central Drift Chamber in the Stanford Linear Collider Detector

International Nuclear Information System (INIS)

Lo, C.C.; Kirsten, F.A.; Nakamura, M.

1987-10-01

In order to accommodate the high packaging density requirements for the front end electronics of the Central Drift Chamber (CDC) in the SLAC Linear Collider Detector (SLD), the CDC front end electronics has been hybridized. The hybrid package contains eight channels of amplifiers together with all the associated circuits for calibration, event recognition and power economy switching functions. A total of 1280 such hybrids are used in the CDC

Linear Modeling of the Three-Phase Diode Front-Ends with Reduced Capacitance Considering the Continuous Conduction Mode

DEFF Research Database (Denmark)

Máthé, Lászlo; Yang, Feng; Wang, Dong

2016-01-01

for the entire drive systems have to be designed. A linearization and simplification to single phase model can be performed; however, when inductance is present at the grid side its performance is not satisfactory. The problem is mainly caused by neglecting the continuous conduction mode of the rectifier......Reducing the DC-link capacitance considerably is a new trend in many applications, such as: motor drives, electrolysers etc.. A straight forward method for modelling the diode front-end is to build a non-linear diode based model. This non-linear model gives difficulties when the controllers...... in the simplified model. This article proposes a simplified linear model where the continuous conduction mode is also considered. The DC-link voltage and current waveforms obtained through the proposed simplified model matches very well the waveforms obtained with the three phase diode based model and also...

Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

Science.gov (United States)

2016-09-01

into two parts. The design, development, and testing efforts of the front-end microwave photonics circuit design and the system integration with the...miniature microwave - photonic phase-sampling DF technique is investigated in this thesis. This front-end design uses a combination of integrated optical...NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release. Distribution is unlimited. MICROWAVE

Installation and testing of the 112 boards for the front-end electronics.

CERN Multimedia

2006-01-01

Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

Performance of the front-end electronics of the ANTARES neutrino telescope

NARCIS (Netherlands)

Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

2010-01-01

ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube

Using intuition in fuzzy front-end decision-making : a conceptual framework

NARCIS (Netherlands)

Eling, K.; Griffin, A.; Langerak, F.

2014-01-01

The goal of decision-making during the execution of the fuzzy front end (FFE) is to develop a creative new product concept. Although intuitive decision-making has been found to increase new product creativity, the theoretical knowledge base as to why and under which conditions intuition use during

Radiation tolerant optical links for the readout of the ATLAS experiment

CERN Document Server

Pearce, M

2000-01-01

The ATLAS experiment will use radiation tolerant optical links to transfer data to and from sub-detector systems. The link specifications can be broadly divided into two classes, represented by the inner tracking detectors and the electromagnetic calorimeter. A feature common to all the readout links is the use of vertical cavity surface emitting laser diodes coupled to multimode optical fibres. Results from the development for both of these environments are reviewed with particular attention bring paid to irradiation studies. (8 refs).

Front-end data processing the SLD data acquisition system

International Nuclear Information System (INIS)

Nielsen, B.S.

1986-07-01

The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber

KAUST Repository

Shi, Xian

2017-01-05

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber are numerically investigated using an 1-D unsteady, shock-capturing, compressible and reacting flow solver. Different combinations of reaction front propagation and end-gas combustion modes are observed, i.e., 1) deflagration without end-gas combustion, 2) deflagration to end-gas autoignition, 3) deflagration to end-gas detonation, 4) developing or developed detonation, occurring in the sequence of increasing initial temperatures. Effects of ignition location and chamber size are evaluated: the asymmetric ignition is found to promote the reactivity of unburnt mixture compared to ignitions at center/wall, due to additional heating from asymmetric pressure waves. End-gas combustion occurs earlier in smaller chambers, where end-gas temperature rise due to compression heating from the deflagration is faster. According to the ξ−ε regime diagram based on Zeldovich theory, modes of reaction front propagation are primarily determined by reactivity gradients introduced by initial ignition, while modes of end-gas combustion are influenced by the total amount of unburnt mixture at the time when autoignition occurs. A transient reactivity gradient method is provided and able to capture the occurrence of detonation.

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber

KAUST Repository

Shi, Xian; Ryu, Je Ir; Chen, Jyh-Yuan; Dibble, Robert W.

2017-01-01

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber are numerically investigated using an 1-D unsteady, shock-capturing, compressible and reacting flow solver. Different combinations of reaction front propagation and end-gas combustion modes are observed, i.e., 1) deflagration without end-gas combustion, 2) deflagration to end-gas autoignition, 3) deflagration to end-gas detonation, 4) developing or developed detonation, occurring in the sequence of increasing initial temperatures. Effects of ignition location and chamber size are evaluated: the asymmetric ignition is found to promote the reactivity of unburnt mixture compared to ignitions at center/wall, due to additional heating from asymmetric pressure waves. End-gas combustion occurs earlier in smaller chambers, where end-gas temperature rise due to compression heating from the deflagration is faster. According to the ξ−ε regime diagram based on Zeldovich theory, modes of reaction front propagation are primarily determined by reactivity gradients introduced by initial ignition, while modes of end-gas combustion are influenced by the total amount of unburnt mixture at the time when autoignition occurs. A transient reactivity gradient method is provided and able to capture the occurrence of detonation.

Firmware Development for the ATLAS TileCal sROD

CERN Document Server

Moreno Marti, Pablo; The ATLAS collaboration; Valero, Alberto

2015-01-01

TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. A main upgrade of the LHC (also called Phase-II) is planned in order to increase the instantaneous luminosity in 2022. At the TileCal level, the upgrade involves the redesign of the complete read-out architecture, affecting both the front-end and the back-end electronics. In the new read-out architecture, the front-end electronics will transmit digitized information of the full detector to the back-end system every single bunch-crossing. Thus, the back-end system must provide digital calibrated information to the first level of trigger. Having all detector data per bunch crossing in the back-end will increase the precision and granularity of the trigger information, improving this way the trigger efficiencies. A reduced part of the detector, 1/256 of the total, will be equipped with the new electronics during 2015 to evaluate the proposed architecture in real conditions in the so-called “demonstra...

Firmware Development for the ATLAS TileCal sROD

CERN Document Server

Moreno Marti, Pablo; The ATLAS collaboration; Valero, Alberto

2015-01-01

TileCal is the central hadronic calorimeter of the ATLAS experiment at the Large Hadron Collider (LHC) at CERN. A main upgrade of the LHC (also called Phase-II) is planned in order to increase the instantaneous luminosity in 2022. For TileCal, the upgrade involves the redesign of the complete read-out architecture, affecting both the front-end and the back-end electronics. In the new read-out architecture, the front-end electronics will transmit digitized information of the full detector to the back-end system every single bunch-crossing. Thus, the back-end system must provide digital calibrated information to the first level of trigger. Having all detector data per bunch crossing in the back-end will increase the precision and granularity of the trigger information, improving this way the trigger efficiencies. A reduced part of the detector, 1/256 of the total, will be equipped with the new electronics during 2016 to evaluate the proposed architecture in real conditions in the so-called “demonstrator proje...

Microwave integrated circuit radiometer front-ends for the Push Broom Microwave Radiometer

Science.gov (United States)

Harrington, R. F.; Hearn, C. P.

1982-01-01

Microwave integrated circuit front-ends for the L-band, S-band and C-band stepped frequency null-balanced noise-injection Dicke-switched radiometer to be installed in the NASA Langley airborne prototype Push Broom Microwave Radiometer (PBMR) are described. These front-ends were developed for the fixed frequency of 1.413 GHz and the variable frequencies of 1.8-2.8 GHz and 3.8-5.8 GHz. Measurements of the noise temperature of these units were made at 55.8 C, and the results of these tests are given. While the overall performance was reasonable, improvements need to be made in circuit losses and noise temperatures, which in the case of the C-band were from 1000 to 1850 K instead of the 500 K specified. Further development of the prototypes is underway to improve performance and extend the frequency range.

Upgrade of the ATLAS Tile Calorimeter Electronics

International Nuclear Information System (INIS)

Carrió, F

2015-01-01

The Tile Calorimeter (TileCal) is the hadronic calorimeter covering the central region of the ATLAS experiment at LHC. The TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC phase (Phase-II) where the peak luminosity will increase 5 times compared to the design luminosity (10 34 cm −2 s −1 ) but with maintained energy (i.e. 7+7 TeV). An additional increase of the average luminosity with a factor of 2 can be achieved by luminosity levelling. This upgrade is expected to happen around 2024. The TileCal upgrade aims at replacing the majority of the on- and off- detector electronics to the extent that all calorimeter signals will be digitized and sent to the off-detector electronics in the counting room. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to the counting room while 5 Gbps down-links are used for synchronization, configuration and detector control. For the off-detector electronics a pre-processor (sROD) is being developed, which takes care of the initial trigger processing while temporarily storing the main data flow in pipeline and derandomizer memories. One demonstrator prototype module with the new calorimeter module electronics, but still compatible with the present system, is planned to be inserted in ATLAS this year

A new sub-detector for ATLAS

CERN Multimedia

Marco Bruschi

Since last August, the ATLAS detector family has been joined by a new little member named LUCID, from the acronym "LUminosity Cerenkov Integrating Detector". This may well surprise you if you are already aware that LUCID construction started only in February after its approval by an ATLAS-management mandated review committee. The rapid progress from approval to installation is the result of the close collaboration between groups from Alberta (Canada), INFN Bologna (Italy), Lund (Sweden) and CERN. LUCID is primarily intended to measure the luminosity delivered by the LHC to ATLAS with a systematic uncertainty in the range of a few percent. To achieve such a precision and still meet the demanding installation schedule, the LUCID developers prized simplicity and robustness above all. One of the LUCID vessels while under construction. One can see the aluminum Cerenkov tubes and the photomultiplier mount (plugged into the upper flange). The two fully assembled LUCID vessels seen from the front end elect...

Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

CERN Document Server

Lo Presti, D; Caponetto, L

2007-01-01

A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr

CERN Document Server

Rescia, S; Newcomer, F M; Dressnandt, N

2009-01-01

We have designed and fabricated a very low noise preamplifier and shaper with a (RC)2 – CR response to replace the existing ATLAS Liquid Argon readout for use at SLHC. IBM’s 8WL 130nm SiGe process was chosen for its radiation tolerance wide voltage range and potential for use in other LHC detector subsystems. The required dynamic range of 15 bits is accomplished by utilization of a single stage, low noise, wide dynamic range preamp connected to a dual range shaper. The low noise of the preamp (~.01nA / √Hz) is achieved by utilizing the process Silicon Germanium bipolar transistors. The relatively high voltage rating of the npn transistors is exploited to allow a gain of 650V/A. With this gain the equivalent input voltage noise requirement on the shaper to about 2.2nV/ √Hz. Each shaper stage is designed as a cascaded differential op amp doublet with a common mode operating point regulated by an internal feedback loop. The shaper outputs are designed to be compatible with the 130nm CMOS ADC being develo...

ATLAS Silicon Microstrip Tracker Operation and Performance

CERN Document Server

Chalupkova, I; The ATLAS collaboration

2012-01-01

The Semi-Conductor Tracker (SCT) is a silicon strip detector and one of the key precision tracking devices in the Inner Detector of the ATLAS experiment at CERN LHC. The SCT is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The modules are mounted into two types of structures: one barrel (4 cylinders) and two end-cap systems (9 disks on each end of the barrel). The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. Data is transferred to the off-detector readout electronics via optical fibers. The completed SCT has been installed inside the ATLAS experimental cavern since 2007 and has been operational since then. Calibration data has been taken regularly and analyzed to determine the noise performance of the ...

ATLAS Silicon Microstrip Tracker Operation and Performance

CERN Document Server

NAGAI, K; The ATLAS collaboration

2012-01-01

The Semi-Conductor Tracker (SCT) is a silicon strip detector and one of the key precision tracking devices in the Inner Detector of the ATLAS experiment at CERN LHC. The SCT is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The modules are mounted into two types of structures: one barrel (4 cylinders) and two end-cap systems (9 disks on each end of the barrel). The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. Data is transferred to the off-detector readout electronics via optical fibres. The completed SCT has been installed inside the ATLAS experimental cavern since 2007 and has been operational since then. Calibration data has been taken regularly and analysed to determine the noise performance of the ...

Front-end electronics for the CMS preshower detector

CERN Document Server

Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

2002-01-01

The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

Design and simulation of front end power converter for a microgrid with fuel cells and solar power sources

Science.gov (United States)

Jeevargi, Chetankumar; Lodhi, Anuj; Sateeshkumar, Allu; Elangovan, D.; Arunkumar, G.

2017-11-01

The need for Renewable Energy Sources (RES) is increasing due to increased demand for the supply of power and it is also environment friendly.In the recent few years, the cost of generation of the power from the RES has been decreased. This paper aims to design the front end power converter which is required for integrating the fuel cells and solar power sources to the micro grid. The simulation of the designed front end converter is carried out in the PSIM 9.1.1 software. The results show that the designed front end power converter is sufficient for integrating the micro grid with fuel cells and solar power sources.

The ATLAS Detector Safety System

CERN Multimedia

Helfried Burckhart; Kathy Pommes; Heidi Sandaker

The ATLAS Detector Safety System (DSS) has the mandate to put the detector in a safe state in case an abnormal situation arises which could be potentially dangerous for the detector. It covers the CERN alarm severity levels 1 and 2, which address serious risks for the equipment. The highest level 3, which also includes danger for persons, is the responsibility of the CERN-wide system CSAM, which always triggers an intervention by the CERN fire brigade. DSS works independently from and hence complements the Detector Control System, which is the tool to operate the experiment. The DSS is organized in a Front- End (FE), which fulfills autonomously the safety functions and a Back-End (BE) for interaction and configuration. The overall layout is shown in the picture below. ATLAS DSS configuration The FE implementation is based on a redundant Programmable Logical Crate (PLC) system which is used also in industry for such safety applications. Each of the two PLCs alone, one located underground and one at the s...

Design and Optimization of Multi-bit Front-end Stage and Scaled Back-end Stages of Pipelined ADCs

NARCIS (Netherlands)

Quinn, P.J.; Roermund, van A.H.M.

2005-01-01

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADCs. The paper continues by analyzing the optimal design for low power of the

ONE SIZE DOES NOT FIT ALL — UNDERSTANDING THE FRONT-END AND BACK-END OF BUSINESS MODEL INNOVATION

OpenAIRE

FRANZISKA GÜNZEL; ANNA B. HOLM

2013-01-01

Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovatio...

Design of a Modular Multilevel Converter as an Active Front-End for a magnet supply application

CERN Document Server

Panagiotis, Asimakopoulos; Massimo, Bongiorno

2015-01-01

The aim of this work is to describe the general design procedure of a Modular Multilevel Converter (MMC) applied as an Active Front-End (AFE) for a magnet supply for beam accelerators. The dimensioning criteria for the converter and the dc-link capacitance are presented and the grid transformer requirements are set. Considering the converter design, the arm inductance calculation is based on the specifications for the arm-current ripple and the DC-link fault tolerance, but, also, on the limitation of the second harmonic and the second-order LC resonance of the arm current. The module capacitance value is evaluated by focusing on the required switching dynamics and the capacitor-voltage ripple according to a newly proposed graphical method. The loading of each semiconductor in the half bridge is calculated via simulation, indicating the unsymmetrical current distribution. It is concluded that the current distribution for each semiconductor depends on the mode of operation of the converter. The different criter...

AiGERM: A logic programming front end for GERM

Science.gov (United States)

Hashim, Safaa H.

1990-01-01

AiGerm (Artificially Intelligent Graphical Entity Relation Modeler) is a relational data base query and programming language front end for MCC (Mission Control Center)/STP's (Space Test Program) Germ (Graphical Entity Relational Modeling) system. It is intended as an add-on component of the Germ system to be used for navigating very large networks of information. It can also function as an expert system shell for prototyping knowledge-based systems. AiGerm provides an interface between the programming language and Germ.

EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

International Nuclear Information System (INIS)

Carlson, R.B.

1992-01-01

The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

Calibration Analysis Software for the ATLAS Pixel Detector

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00372086; The ATLAS collaboration

2016-01-01

The calibration of the ATLAS Pixel detector at LHC fulfils two main purposes: to tune the front-end configuration parameters for establishing the best operational settings and to measure the tuning performance through a subset of scans. An analysis framework has been set up in order to take actions on the detector given the outcome of a calibration scan (e.g. to create a mask for disabling noisy pixels). The software framework to control all aspects of the Pixel detector scans and analyses is called Calibration Console. The introduction of a new layer, equipped with new Front End-I4 Chips, required an update the Console architecture. It now handles scans and scans analyses applied together to chips with different characteristics. An overview of the newly developed Calibration Analysis Software will be presented, together with some preliminary result.

Front-end electronics for H.E.P

International Nuclear Information System (INIS)

Hrisoho, A.

1990-07-01

A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

Chairman of the DELL Board of Directors and Chief Executive Officer Michael S. Dell with CERN Director-General R. Heuer and in front of the ATLAS detector (centre) with ATLAS Deputy Spokesperson A. Lankford (left) and Information Technology Department Head F. Hemmer on 26th January 2010.

CERN Multimedia

Maximilien Brice

2010-01-01

Chairman of the DELL Board of Directors and Chief Executive Officer Michael S. Dell with CERN Director-General R. Heuer and in front of the ATLAS detector (centre) with ATLAS Deputy Spokesperson A. Lankford (left) and Information Technology Department Head F. Hemmer on 26th January 2010.

Planetary Data Systems (PDS) Imaging Node Atlas II

Science.gov (United States)

Stanboli, Alice; McAuley, James M.

2013-01-01

The Planetary Image Atlas (PIA) is a Rich Internet Application (RIA) that serves planetary imaging data to the science community and the general public. PIA also utilizes the USGS Unified Planetary Coordinate system (UPC) and the on-Mars map server. The Atlas was designed to provide the ability to search and filter through greater than 8 million planetary image files. This software is a three-tier Web application that contains a search engine backend (MySQL, JAVA), Web service interface (SOAP) between server and client, and a GWT Google Maps API client front end. This application allows for the search, retrieval, and download of planetary images and associated meta-data from the following missions: 2001 Mars Odyssey, Cassini, Galileo, LCROSS, Lunar Reconnaissance Orbiter, Mars Exploration Rover, Mars Express, Magellan, Mars Global Surveyor, Mars Pathfinder, Mars Reconnaissance Orbiter, MESSENGER, Phoe nix, Viking Lander, Viking Orbiter, and Voyager. The Atlas utilizes the UPC to translate mission-specific coordinate systems into a unified coordinate system, allowing the end user to query across missions of similar targets. If desired, the end user can also use a mission-specific view of the Atlas. The mission-specific views rely on the same code base. This application is a major improvement over the initial version of the Planetary Image Atlas. It is a multi-mission search engine. This tool includes both basic and advanced search capabilities, providing a product search tool to interrogate the collection of planetary images. This tool lets the end user query information about each image, and ignores the data that the user has no interest in. Users can reduce the number of images to look at by defining an area of interest with latitude and longitude ranges.

Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2015-07-01

The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

Development of a multi-channel front-end electronics module based on ASIC for silicon strip array detectors

International Nuclear Information System (INIS)

Zhao Xingwen; Yan Duo; Su Hong; Qian Yi; Kong Jie; Zhang Xueheng; Li Zhankui; Li Haixia

2014-01-01

The silicon strip array detector is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou (HIRFL-CSR). Using the ASICs, the front-end electronics module has been developed for the silicon strip array detectors and can implement measurement of energy of 96 channels. The performance of the front-end electronics module has been tested. The energy linearity of the front-end electronics module is better than 0.3% for the dynamic range of 0.1∼0.7 V. The energy resolution is better than 0.45%. The maximum channel crosstalk is better than 10%. The channel consistency is better than 1.3%. After continuously working for 24 h at room temperature, the maximum drift of the zero-peak is 1.48 mV. (authors)

Upgrading the ATLAS Tile Calorimeter Electronics

CERN Document Server

Carrio, F

2013-01-01

This work summarizes the status of the on-detector and off-detector electronics developments for the Phase II Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in middle 2014 during the Long Shutdown. For the on-detector readout, three different front-end boards (FEB) alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The MainBoard will provide communication and control to the FEBs and the DaughterBoard will transmit the digitized data to the off-detector electronics in the counting room, where the sROD will perform processing tasks on them.

The ATLAS Silicon Microstrip Tracker

CERN Document Server

Haefner, Petra

2010-01-01

In December 2009 the ATLAS experiment at the CERN Large Hadron Collider (LHC) recorded the first proton-proton collisions at a centre-of-mass energy of 900 GeV. This was followed by collisions at the unprecedented energy of 7 TeV in March 2010. The SemiConductor Tracker (SCT) is a precision tracking device in ATLAS made up from silicon micro-strip detectors processed in the planar p-in-n technology. The signal from the strips is processed in the front-end ASICs working in binary readout mode. Data is transferred to the off-detector readout electronics via optical fibers. The completed SCT has been installed inside the ATLAS experiment. Since then the detector was operated for two years under realistic conditions. Calibration data has been taken and analysed to determine the performance of the system. In addition, extensive commissioning with cosmic ray events has been performed both with and without magnetic field. The sensor behaviour in magnetic field was studied by measurements of the Lorentz angle. After ...

Front end power dissipation minimization and optimal transmission rate for wireless receivers

NARCIS (Netherlands)

Heuvel, van den J.H.C.; Wu, Y.; Baltus, P.G.M.; Linnartz, J.P.M.G.; Roermund, van A.H.M.

2014-01-01

Most wireless battery-operated devices spend more energy receiving than transmitting. Hence, minimizing the power dissipation in the receiver front end, which, in many cases, is the prominent power consuming part of the receiver, is an important challenge. This paper addresses this challenge by

Testing and development of an OWC MRI compatible PET insert front-end

Energy Technology Data Exchange (ETDEWEB)

Konstantinou, G.; Ali, W.; Chil, R.; Cossu, G.; Ciaramella, E.; Vaquero, J.J.

2016-07-01

We present the design and development of a positron emission tomography (PET) detector module that could be used inside magnetic resonance imager (MRI). Critical factors compromising this combination have been studied and different solutions have been offered. Our design divides the detector module in two sections: one is the insert front-end that is placed inside the MRI and that comprises of a scintillator, a silicon photomultiplier and minimum analog electronics. The analog pulses are sent to the second section, the back-end digitalization and reconstruction module. The analog link is implemented using optical wireless communication (OWC) techniques. In this work we study how such a setting retains all the necessary characteristics for the detection and characterization of gamma scintillation events, providing sufficient communication quality with low consumption and minimizing the need for space. Possible multiplexing schemes for achieving the necessary transmission with less communication channels are also proposed and studied. A series of tests and measurements on different settings demonstrate the viability of this technique. When fully developed, it can provide a cost effective alternative for the industrial production of a flexible and customizable modular PET detector insert that can be applied to pre-existing small animal or human MRI settings, only minimally affecting the size of the MRI bore, without compromising the PET signal quality. (Author)

Instrument front-ends at Fermilab during Run II

Science.gov (United States)

Meyer, T.; Slimmer, D.; Voy, D.

2011-11-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor. Work supported by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the United States Department of Energy.

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Document Server

Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

International Nuclear Information System (INIS)

Alessio, F.; Gaspar, C.; Jacobsson, R.; Wyllie, K.; Caplan, C.

2015-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

TDC for the front end architecture in the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

CPRF/ZTH front-end torus design and fabrication status

International Nuclear Information System (INIS)

Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

1989-01-01

Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

CPRF/ZTH front-end torus design and fabrication status

International Nuclear Information System (INIS)

Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

1989-01-01

Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end torus. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

Social Networks in the Front End: The Organizational Life of an Idea

NARCIS (Netherlands)

R.C. Kijkuit (Bob)

2007-01-01

textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study

Upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Reed, Robert; The ATLAS collaboration

2014-01-01

The Tile Calorimeter (TileCal) is the main hadronic calorimeter covering the central region of the ATLAS experiment at LHC. TileCal readout consists of about 10000 channels. The bulk of its upgrade will occur for the High Luminosity LHC operation (Phase 2 around 2023) where the peak luminosity will increase 5x compared to the design luminosity (10^{34} cm^{-2}s^{-1}) but with maintained energy (i.e. 7+7 TeV). The TileCal upgrade aims to replace the majority of the on- and off-detector electronics so that all calorimeter signals can be digitized and directly sent to the off-detector electronics in the counting room. This will reduce pile-up problems and allow more complex trigger algorithms. To achieve the required reliability, redundancy has been introduced at different levels. Three different options are presently being investigated for the front-end electronic upgrade. Extensive test beam studies will determine which option will be selected. 10 Gbps optical links are used to read out all digitized data to t...

Front-end readout system for PHENIX RICH

International Nuclear Information System (INIS)

Tanaka, Y.; Hara, H.; Ebisu, K.; Hibino, M.; Kametani, S.; Kikuchi, J.; Wintenberg, A.L.; Walker, J.W.; Franck, S.; Moscone, C.; Jones, J.P.; Young, G.R.; Matsumoto, T.; Sakaguchi, T.; Oyama, K.; Hamagaki, H.

2000-01-01

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment

Instrumentation of a Level-1 Track Trigger at ATLAS with Double Buffer Front-End Architecture

CERN Document Server

Cooper, B; The ATLAS collaboration

2012-01-01

The increased collision rate and pile-up produced at the HLLHC requires a substantial upgrade of the ATLAS level-1 trigger in order to maintain a broad physics reach. We show that tracking information can be used to control trigger rates, and describe a proposal for how this information can be extracted within a two-stage level-1 trigger design that has become the baseline for the HLLHC upgrade. We demonstrate that, in terms of the communication between the external processing and the tracking detector frontends, a hardware solution is possible that fits within the latency constraints of level-1.

The ATLAS Liquid Argon Electromagnetic EndCap Calorimeter Construction and tests

CERN Document Server

Rodier, S; Del Peso, J

2003-01-01

This thesis has been carried out within the ATLAS collaboration. ATLAS is one of the two multipurpose experiments approved for data taking at the Large Hadron Collider (LHC) at CERN. The main goals of this experiment are, to find the Higgs boson, the missing piece in the otherwise so succesful Standard Model of Particle Physics, and to look for physics beyond the Standard Model up to a scale of 1TeV. For this purpose, electromagnetic (EM) calorimetry play a key role. The ATLAS Collaboration has chosen a Liquid Argon (LAr) option with lead as passive material. The liquid Argon Calorimeter is divided into two main subdetectors, the barrel and the end caps (EC). The design and construction of the LAr EM EC calorimeter is the responsability of the groups at Centre de Physique de Marseille (CPPM) and the Universidad Autonoma de Madrid (UAM)following the guideline developed by the research and development working, group 3 for LHC detectors (RD3). The sharing of responsabilities is such that CPPM provides spacers an...

Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

International Nuclear Information System (INIS)

Ericson, M.N.; Allen, M.D.; Boissevain, J.

1997-11-01

Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

International Nuclear Information System (INIS)

Beccherle, R.; Cisternino, A.; Guerra, A. Del; Folli, M.; Marchesini, R.; Bisogni, M.G.; Ceccopieri, A.; Rosso, V.; Stefanini, A.; Tripiccione, R.; Kipnis, I.

1999-01-01

An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 μm CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution

The ALICE detector data link

CERN Document Server

Rubin, G; Csató, P; Dénes, E; Kiss, T; Meggyesi, Z; Sulyán, J; Vesztergombi, G; Eged, B; Gerencsér, I; Novák, I; Soós, C; Tarján, D; Telegdy, A; Tóth, N

1999-01-01

The ALICE detector data link has been designed to cover all the needs for data transfer between the detector and the data-acquisition system. It is a 1 Gbit/s, full-duplex, multi-purpose fibre optic link that can be used as a medium for the bi-directional transmission of data blocks between the front-end electronics and the data- acquisition system and also for the remote control and test of the front-end electronics, In this paper the concept, the protocol, the specific test tools, the prototypes of the detector data link and the read-out receiver card, their application in the ALICE-TPC test system and the integration with the DATE software are presented. The test results on the performance are also shown. (14 refs).

LAPAS: A SiGe Front End Prototype for the Upgraded ATLAS LAr Calorimeter

CERN Document Server

Dressnandt, N; Rescia, S; Vernon, E

2009-01-01

We have designed and fabricated a very low noise preamplifier and shaper to replace the existing ATLAS Liquid Argon readout for use at the Large Hadron Collider upgrade (sLHC). IBM’s 8WL 130nm SiGe process was chosen for it’s radiation tolerance, low noise bipolar NPN devices, wide voltage rand and potential use in other sLHC detector subsystems. Although the requirements for the final design can not be set at this time, the prototype was designed to accommodate a 16 bit dynamic range. This was accomplished by using a single stage, low noise, wide dynamic range preamp followed by a dual range shaper. The low noise of the preamp is made possible by the low base spreading resistance of the Silicon Germanium NPN bipolar transistors. The relatively high voltage rating of the NPN transistors is exploited to allow a gain of 650V/A in the preamplifier which eases the input voltage noise requirement on the shaper. Each shaper stage is designed as a cascaded differential operational amplifier doublet with a common...

Influence Of Tools Input/Output Requirements On Managers Core Front End Activities In New Product Development

DEFF Research Database (Denmark)

Appio, Francesco P.; Achiche, Sofiane; Minin, Alberto Di

2011-01-01

opportunities; make this early phase of the innovation process uncertain and extremely risky. Literature suggests that the understanding, selection and use of appropriate tools/techniques to support decision making are instrumental for a less fuzzy front end of innovation. This paper considers the adoption......The object of analysis of this explorative research is the Fuzzy Front End of Innovation in Product Development, described by those activities going from the opportunity identification to the concept definition. Business scholars have shown that confusion in terms of goals and different ideas about...

A software-radio front-end for microwave applications

Directory of Open Access Journals (Sweden)

M. Streifinger

2003-01-01

Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

Performance and scalability of the back-end sub-system in the ATLAS DAQ/EF prototype

CERN Document Server

Alexandrov, I N; Badescu, E; Burckhart, Doris; Caprini, M; Cohen, L; Duval, P Y; Hart, R; Jones, R; Kazarov, A; Kolos, S; Kotov, V; Laugier, D; Mapelli, Livio P; Moneta, L; Qian, Z; Radu, A A; Ribeiro, C A; Roumiantsev, V; Ryabov, Yu; Schweiger, D; Soloviev, I V

2000-01-01

The DAQ group of the future ATLAS experiment has developed a prototype system based on the trigger/DAQ architecture described in the ATLAS Technical Proposal to support studies of the full system functionality, architecture as well as available hardware and software technologies. One sub-system of this prototype is the back- end which encompasses the software needed to configure, control and monitor the DAQ, but excludes the processing and transportation of physics data. The back-end consists of a number of components including run control, configuration databases and message reporting system. The software has been developed using standard, external software technologies such as OO databases and CORBA. It has been ported to several C++ compilers and operating systems including Solaris, Linux, WNT and LynxOS. This paper gives an overview of the back-end software, its performance, scalability and current status. (17 refs).

Status report on front end electronics for the EUSO photon detector

International Nuclear Information System (INIS)

Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P.

2002-01-01

In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions

Status report on front end electronics for the EUSO photon detector

Energy Technology Data Exchange (ETDEWEB)

Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P

2002-12-01

In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

Energy Technology Data Exchange (ETDEWEB)

Rivetti, Angelo

2014-11-21

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

Upgrade of the ATLAS Tile Calorimeter Electronics

CERN Document Server

Carrio, F; The ATLAS collaboration

2014-01-01

This presentation summarizes the status of the on-detector and off-detector electronics developments for the Phase II Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2024. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in middle 2014 during the Long Shutdown. For the on-detector readout, three different front-end boards (FEB) alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The MainBoard will provide communication and control to the FEBs and the DaughterBoard will transmit the digitized data to the off-detector electronics in the counting room, where the sROD will perform processing tasks on them.

ATLAS TRT Barrel in Test Beam

CERN Multimedia

Luehring, F

In July, the TRT group made a highly successful test of 6 Barrel TRT modules in the ATLAS H8 testbeam. Over 3000 TRT straw tubes (4 mm diameter gas drift tubes) were instrumented and found to operate well. The prototype represents 1/16 of the ATLAS TRT barrel and was assembled from TRT modules produced as spares. This was the largest scale test of the TRT to this date and the measured detector performance was as good as or better than what was expected in all cases. The 2004 TRT testbeam setup before final cabling was attached. The readout chain and central DAQ system used in the TRT testbeam is a final prototype for the ATLAS experiment. The TRT electronics used to read out the data were: The Amplifier/Shaper/Discriminator with Baseline Restoration (ASDBLR) chip is the front-end analog chip that shapes and discriminates the electronic pulses generated by the TRT straws. The Digital Time Measurement Read Out Chip (DTMROC) measures the time of the pulse relative to the beam crossing time. The TRT-ROD ...

Research and Development for a Free-Running Readout System for the ATLAS LAr Calorimeters at the High Luminosity LHC

CERN Document Server

Hils, Maximilian; The ATLAS collaboration

2015-01-01

The ATLAS Liquid Argon (LAr) Calorimeters were designed and built to measure electromagnetic and hadronic energy in proton-proton collisions produced at the LHC at centre-of-mass energies up to 14 TeV and instantaneous luminosities up to $10^{34} \\text{cm}^{-2} \\text{s}^{-1}$. The High Luminosity LHC (HL-LHC) programme is now developed for up to 5-7 times the design luminosity, with the goal of accumulating an integrated luminosity of $3000~\\text{fb}^{-1}$. In the HL-LHC phase, the increased radiation levels require a replacement of the front-end electronics of the LAr Calorimeters. Furthermore, the ATLAS trigger system is foreseen to increase the trigger accept rate by a factor 10 to 1 MHz and the trigger latency by a factor of 20 which requires a larger data volume to be buffered. Therefore, the LAr Calorimeter read-out will be exchanged with a new front-end and a high bandwidth back-end system for receiving data from all 186.000 channels at 40 MHz LHC bunch-crossing frequency and for off-detector buffering...

Production of the front-end boards of the LHCb muon system

CERN Document Server

Bonivento, W; Auriemma, G

2008-01-01

This note describes the production of the front end boards CARDIAC, for the 1368 MWPC, and CARDIAC-GEM, for the 12 triple-GEM chambers, of the LHCb muon system. The PCB structure and component layout and the production issues, such as component soldering, quality assurance at the company and delivery rates, are described. The performance of these boards will be the subject of a future publication.

Highly integrated front-end electronics for spaceborne fluxgate sensors

International Nuclear Information System (INIS)

Magnes, W; Valavanoglou, A; Hagen, C; Jernej, I; Baumjohann, W; Oberst, M; Hauer, H; Neubauer, H; Pierce, D; Means, J; Falkner, P

2008-01-01

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm 2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability ( −1 MFA temperature, −1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm 2 mg −1

Optimizing read-out of the NECTAr front-end electronics

Energy Technology Data Exchange (ETDEWEB)

Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

2012-12-11

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Optimizing read-out of the NECTAr front-end electronics

International Nuclear Information System (INIS)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C.L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-01-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Optimizing read-out of the NECTAr front-end electronics

Science.gov (United States)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-12-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Design and performance Assessment of an Airborne Ice Sounding Radar Front-End

DEFF Research Database (Denmark)

Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens

2008-01-01

The paper describes the design and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design features newly developed components at a centre frequency of 435 MHz, such as, antenna 20% bandwidth at RL ≪ 13 dB, compact high power in...

Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

Science.gov (United States)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

2016-08-01

The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

The ATLAS beam pick-up based timing system

International Nuclear Information System (INIS)

Ohm, C.; Pauly, T.

2010-01-01

The ATLAS BPTX stations are composed of electrostatic button pick-up detectors, located 175 m away along the beam pipe on both sides of ATLAS. The pick-ups are installed as a part of the LHC beam instrumentation and used by ATLAS for timing purposes. The usage of the BPTX signals in ATLAS is twofold: they are used both in the trigger system and for LHC beam monitoring. The BPTX signals are discriminated with a constant-fraction discriminator to provide a Level-1 trigger when a bunch passes through ATLAS. Furthermore, the BPTX detectors are used by a stand-alone monitoring system for the LHC bunches and timing signals. The BPTX monitoring system measures the phase between collisions and clock with a precision better than 100 ps in order to guarantee a stable phase relationship for optimal signal sampling in the sub-detector front-end electronics. In addition to monitoring this phase, the properties of the individual bunches are measured and the structure of the beams is determined. On September 10, 2008, the first LHC beams reached the ATLAS experiment. During this period with beam, the ATLAS BPTX system was used extensively to time in the read-out of the sub-detectors. In this paper, we present the performance of the BPTX system and its measurements of the first LHC beams.

Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

Directory of Open Access Journals (Sweden)

Umit H. Yapanel

2008-08-01

Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

Directory of Open Access Journals (Sweden)

Yapanel UmitH

2008-01-01

Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

Task Management in the New ATLAS Production System

CERN Document Server

De, K; The ATLAS collaboration; Klimentov, A; Potekhin, M; Vaniachine, A

2013-01-01

The ATLAS Production System is the top level workflow manager which translates physicists' needs for production level processing into actual workflows executed across about a hundred processing sites used globally by ATLAS. As the production workload increased in volume and complexity in recent years (the ATLAS production tasks count is above one million, with each task containing hundreds or thousands of jobs) there is a need to upgrade the Production System to meet the challenging requirements of the next LHC run while minimizing the operating costs. Providing a front-end and a management layer for petascale data processing and analysis, the new Production System contains generic subsystems that can be used in a wider range of applications. The main subsystems are the Database Engine for Tasks (DEFT) and the Job Execution and Definition Interface (JEDI). Based on users' requests, the DEFT subsystem manages inter-dependent groups of tasks (Meta-Tasks) and generates corresponding data processing workflows. Th...

Task Management in the New ATLAS Production System

CERN Document Server

De, K; The ATLAS collaboration; Klimentov, A; Potekhin, M; Vaniachine, A

2014-01-01

The ATLAS Production System is the top level workflow manager which translates physicists' needs for production level processing into actual workflows executed across about a hundred processing sites used globally by ATLAS. As the production workload increased in volume and complexity in recent years (the ATLAS production tasks count is above one million, with each task containing hundreds or thousands of jobs) there is a need to upgrade the Production System to meet the challenging requirements of the next LHC run while minimizing the operating costs. Providing a front-end and a management layer for petascale data processing and analysis, the new Production System contains generic subsystems that can be used in a wider range of applications. The main subsystems are the Database Engine for Tasks (DEFT) and the Job Execution and Definition Interface (JEDI). Based on users' requests, the DEFT subsystem manages inter-dependent groups of tasks (Meta-Tasks) and generates corresponding data processing workflows. Th...

RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

CODA : Compact front-end analog ASIC for silicon detectors

International Nuclear Information System (INIS)

Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

2004-01-01

The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

Structuring front-end innovation activities throughout strategic product planning

Directory of Open Access Journals (Sweden)

Thaisa Rodrigues

Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

The Phase-2 Electronics Upgrade of the ATLAS Liquid Argon Calorimeter System

CERN Document Server

Vachon, Brigitte; The ATLAS collaboration

2018-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile- up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS liquid argon calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the front-end and back- end readout system is foreseen for the 182,468 readout channels. The new readout system will be based on a free-running architecture, where calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40 MHz to the back-end for further processing. Results from the design studies on the performance of the components of the readou...

CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

CERN Multimedia

J.Coughlan

1998-01-01

The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

International Nuclear Information System (INIS)

Alexanian, H.; Appelquist, G.; Bailly, P.

1995-01-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

IT Infrastructure Design and Implementation Considerations for the ATLAS TDAQ System

CERN Document Server

Dobson, M; The ATLAS collaboration; Caramarcu, C; Dumitru, I; Valsan, L; Darlea, G L; Bujor, F; Bogdanchikov, A G; Korol, A A; Zaytsev, A S; Ballestrero, S

2013-01-01

This paper gives a thorough overview of the ATLAS TDAQ SysAdmin group activities which deals with administration of the TDAQ computing environment supporting Front End detector hardware, Data Flow, Event Filter and other subsystems of the ATLAS detector operating on the LHC accelerator at CERN. The current installation consists of approximately 1500 netbooted nodes managed by more than 60 dedicated servers, a high performance centralized storage system, about 50 multi-screen user interface systems installed in the control rooms and various hardware and critical service monitoring machines. In the final configuration, the online computer farm will be capable of hosting tens of thousands applications running simultaneously. The ATLAS TDAQ computing environment is now serving more than 3000 users subdivided into approximately 300 categories in correspondence with their roles in the system. The access and role management system is custom built on top of an LDAP schema. The engineering infrastructure of the ATLAS ...

LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Multimedia

Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

A −3 dBm RF transmitter front-end for 802.11g application

International Nuclear Information System (INIS)

Zhao Jinxin; Yan Jun; Shi Yin

2013-01-01

A 2.4 GHz, direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals. The front-end output power is −3 dBm while the corresponding EVM is −27 dB which is necessary for the 802.11g standard of EVM at −25 dB. With the adopted gain control strategy the output power changes from −14.3 to −3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process. A power detector indicates the output power and delivers a voltage to the baseband to control the output power. (semiconductor integrated circuits)

ATLAS Silicon Microstrip Tracker Operation and Performance

CERN Document Server

Chalupkova, I; The ATLAS collaboration

2012-01-01

The Semi-Conductor Tracker (SCT) is a silicon strip detector and one of the key precision tracking devices in the Inner Detector (ID) of the ATLAS experiment at CERN LHC. The SCT is constructed of 4088 silicon detector modules with a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The modules are mounted into two types of structures: one barrel (4 cylinders) and two end-cap systems (9 disks on each side of the barrel). The SCT silicon microstrip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICs ABCD3TA, working in the binary readout mode. Data is transferred to the off-detector readout electronics via optical fibres. SCT has been installed inside the ATLAS experimental cavern since 2007 and has been operational ever since. Calibration data has been taken regularly and analysed to determine the noise performance of the system. ...

ATLAS Thesis Awards 2015

CERN Multimedia

Biondi, Silvia

2016-01-01

Winners of the ATLAS Thesis Award were presented with certificates and glass cubes during a ceremony on Thursday 25 February. The winners also presented their work in front of members of the ATLAS Collaboration. Winners: Javier Montejo Berlingen, Barcelona (Spain), Ruth Pöttgen, Mainz (Germany), Nils Ruthmann, Freiburg (Germany), and Steven Schramm, Toronto (Canada).

Demonstration of an RF front-end based on GaN HEMT technology

Science.gov (United States)

Ture, Erdin; Musser, Markus; Hülsmann, Axel; Quay, Rüdiger; Ambacher, Oliver

2017-05-01

The effectiveness of the developed front-end on blocking the communication link of a commercial drone vehicle has been demonstrated in this work. A jamming approach has been taken in a broadband fashion by using GaN HEMT technology. Equipped with a modulated-signal generator, a broadband power amplifier, and an omni-directional antenna, the proposed system is capable of producing jamming signals in a very wide frequency range between 0.1 - 3 GHz. The maximum RF output power of the amplifier module has been software-limited to 27 dBm (500 mW), complying to the legal spectral regulations of the 2.4 GHz ISM band. In order to test the proof of concept, a real-world scenario has been prepared in which a commercially-available quadcopter UAV is flown in a controlled environment while the jammer system has been placed in a distance of about 10 m from the drone. It has been proven that the drone of interest can be neutralized as soon as it falls within the range of coverage (˜3 m) which endorses the promising potential of the broadband jamming approach.

Detector and front-end electronics of a fissile mass flow monitoring system

International Nuclear Information System (INIS)

Paulus, M.J.; Uckan, T.; Lenarduzzi, R.; Mullens, J.A.; Castleberry, K.N.; McMillan, D.E.; Mihalczo, J.T.

1997-01-01

A detector and front-end electronics unit with secure data transmission has been designed and implemented for a fissile mass flow monitoring system for fissile mass flow of gases and liquids in a pipe. The unit consists of 4 bismuth germanate (BGO) scintillation detectors, pulse-shaping and counting electronics, local temperature sensors, and on-board local area network nodes which locally acquire data and report to the master computer via a secure network link. The signal gain of the pulse-shaping circuitry and energy windows of the pulse-counting circuitry are periodicially self calibrated and self adjusted in situ using a characteristic line in the fissile material pulse height spectrum as a reference point to compensate for drift such as in the detector gain due to PM tube aging. The temperature- dependent signal amplitude variations due to the intrinsic temperature coefficients of the PM tube gain and BGO scintillation efficiency have been characterized and real-time gain corrections introduced. The detector and electronics design, measured intrinsic performance of the detectors and electronics, and the performance of the detector and electronics within the fissile mass flow monitoring system are described

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

Science.gov (United States)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

OLS Dialog: An open-source front end to the Ontology Lookup Service

Directory of Open Access Journals (Sweden)

Eidhammer Ingvar

2010-01-01

Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

De l'expérience ALEPH au LEP à la construction du détecteur ATLAS auprès du LHC

CERN Document Server

Martin, Franck

This document summarizes ten years of activities in the field of experimental particle physics, which I have done just after my PhD defense in 1999. After a short introduction describing my PhD work and my activities during these ten years, the first chapter describes an analysis made in the ALEPH experiment about the measurement of the Bose-Einstein correlations in W pair decays, using an event mixing method. Nevertheless, the main part of the text is dedicated to the work I have done in the ATLAS experiment at the LHC, between the years 2000 and 2010. Four parts are distinguished. First, an analysis concerning some searches for possible supersymmetric top decays with R-parity violation is described. Then a second part is written about the test bench of the tile calorimeter front-end electronics, and its installation in the ATLAS experiment. Third, the work done in the transition radiation tracker concerning the validation and the installation of the endcap front-end electronics is fully explained. End, the ...

Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

DEFF Research Database (Denmark)

Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

2009-01-01

Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

The fuzziness of the fuzzy front end : the influence of non-technical factors

NARCIS (Netherlands)

Kiewiet, Derk Jan; van Engelen, Jo; Achterkamp, Marjolein; Chen, J; Xu, QR; Wu, XB

2007-01-01

The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to

Design of a deterministic link initialization mechanism for serial LVDS interconnects

International Nuclear Information System (INIS)

Schatral, S; Lemke, F; Bruening, U

2014-01-01

The Compressed Baryonic Matter experiment at FAIR in Darmstadt has special requirements for the Data Acquisition Network. One of them is deterministic latency for all the links from the back-end to the front-end, which enables synchronization in the whole read-out tree. Since the front-end electronics (FEE) contain mixed-signal circuits for processing the raw detector data, special ASICs were developed. DDR LVDS links are used to interconnect the FEEs and readout controllers. An adapted link initialization mechanism ensures determinism for them by balancing cable lengths, adjusting for phase differences, and handling environmental behavior. After re-initialization, timing must be accurate to the bit-clock level

Performance of Front-End Readout System for PHENIX RICH

International Nuclear Information System (INIS)

Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

1999-01-01

A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

Silicon sensor technologies for ATLAS IBL upgrade

CERN Document Server

Grenier, P; The ATLAS collaboration

2011-01-01

New pixel sensors are currently under development for ATLAS Upgrades. The first upgrade stage will consist in the construction of a new pixel layer that will be installed in the detector during the 2013 LHC shutdown. The new layer (Insertable-B-Layer, IBL) will be inserted between the inner most layer of the current pixel detector and the beam pipe at a radius of 3.2cm. The expected high radiation levels require the use of radiation hard technology for both the front-end chip and the sensor. Two different pixel sensor technologies are envisaged for the IBL. The sensor choice will occur in July 2011. One option is developed by the ATLAS Planar Pixel Sensor (PPS) Collaboration and is based on classical n-in-n planar silicon sensors which have been used for the ATLAS Pixel detector. For the IBL, two changes were required: The thickness was reduced from 250 um to 200 um to improve the radiation hardness. In addition, so-called "slim edges" were designed to reduce the inactive edge of the sensors from 1100 um to o...

Operational Experience with the ATLAS Pixel Detector at LHC

CERN Document Server

Keil, M

2013-01-01

The ATLAS Pixel Detector is the innermost detector of the ATLAS experiment at the Large Hadron Collider at CERN, providing high-resolution measurements of charged particle tracks in the high radiation environment close to the collision region. This capability is vital for the identification and measurement of proper decay times of long-lived particles such as b-hadrons, and thus crucial for the ATLAS physics program. The detector provides hermetic coverage with three cylindrical layers and three layers of forward and backward pixel detectors. It consists of approximately 80 million pixels that are individually read out via front-end chips bump-bonded to 1744 n-on-n silicon substrates. In this paper results from the successful operation of the Pixel Detector at the LHC will be presented, including calibration procedures, detector performance and measurements of radiation damage. The detector performance is excellent: more than 95% of the pixels are operational, noise occupancy and hit efficiency exceed the des...

SIGNAL RECONSTRUCTION PERFORMANCE OF THE ATLAS HADRONIC TILE CALORIMETER

CERN Document Server

Do Amaral Coutinho, Y; The ATLAS collaboration

2013-01-01

"The Tile Calorimeter for the ATLAS experiment at the CERN Large Hadron Collider (LHC) is a sampling calorimeter with steel as absorber and scintillators as active medium. The scintillators are readout by wavelength shifting fibers coupled to photomultiplier tubes (PMT). The analogue signals from the PMTs are amplified, shaped and digitized by sampling the signal every 25 ns. The TileCal front-end electronics allows to read out the signals produced by about 10000 channels measuring energies ranging from ~30 MeV to ~2 TeV. The read-out system is responsible for reconstructing the data in real-time fulfilling the tight time constraint imposed by the ATLAS first level trigger rate (100 kHz). The main component of the read-out system is the Digital Signal Processor (DSP) which, using an Optimal Filtering reconstruction algorithm, allows to compute for each channel the signal amplitude, time and quality factor at the required high rate. Currently the ATLAS detector and the LHC are undergoing an upgrade program tha...

The design of an optical link for the ATLAS Liquid Argon Calorimeter upgrade

CERN Document Server

Liu, T; The ATLAS collaboration

2012-01-01

We present the design of an optical link for the ATLAS liquid argon calorimeter upgrade. Challenging requirements are high data bandwidth (over 150 Gb/s raw data rate per board), radiation tolerance, low power consumption, high reliability, and low transmission latency. We discuss the link system design and component developments, especially those for the transmitting side that has to operate in the radiation environment. This presentation also serves as a summary of a few other presentations that detail in a particular function block of this link.

Digital Architecture of the New ATLAS Pixel Chip FE-I4

CERN Document Server

"Barbero, M; The ATLAS collaboration

2009-01-01

With the high hit rate foreseen for the innermost layers at an upgraded LHC, the current ATLAS Front-End pixel chip FE-I3 would start being inefficient. The main source of inefficiency comes from the copying mechanism of the pixel hits from the pixel array to the end of column buffers. A new ATLAS pixel chip FE-I4 is being developed in a 130 nm technology for use both in the framework of the Insertable B-Layer (IBL) project and for the outer layers of Super-LHC. FE-I4 is 80×336 pixels wide and features a reduced pixel size of 50×250 μm2. In the current design, a new digital architecture is introduced in which hit memories are distributed across the entire chip and the pixels organized in regions. Additional features include neighbor hit checking which allows a timewalk-less hit recording.

Compact Receiver Front Ends for Submillimeter-Wave Applications

Science.gov (United States)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

Development of a dedicated front-end electronics for straw tube trackers in the P-bar ANDA experiment

International Nuclear Information System (INIS)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Swientek, K.; Terlecki, P.; Tokarz, J.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.

2016-01-01

The design and tests of front-end electronics for straw tube trackers in the P-bar ANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

DEFF Research Database (Denmark)

Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

2013-01-01

be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

One size does not fit all - understanding the front-end and back-ens of business model innovation

DEFF Research Database (Denmark)

Günzel, Franziska; Holm, Anna B.

2013-01-01

Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed...... understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...... production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance...

High performance message passing for the ATLAS DAQ/EF-1 project

CERN Document Server

Mornacchi, Giuseppe

1999-01-01

Summary form only. A message passing library has been developed in the context of the ATLAS DAQ/EF-1 project. It is used for time critical applications within the front-end part of the DAQ system, mainly to exchange data control messages between I/O processors. Key objectives of the design were low message overheads, efficient use of the data transfer buses, provision of broadcast functionality and a hardware and operating system independent implementation of the application interface. The design and implementation of the message passing library are presented. As required by the project, the implementation is based on commercial components, namely VMEbus, PCI, the Lynx-OS real-time operating system and an additional inter- processor link, PVIC. The latter offers broadcast functionality identified as being important to the overall performance of the message passing. In addition, performance benchmarks for all implementing buses are presented for both simple test programs and the full DAQ applications. (0 refs)...

A new strips tracker for the upgraded ATLAS ITk detector

CERN Document Server

David, Claire; The ATLAS collaboration

2017-01-01

The inner detector of the present ATLAS detector has been designed and developed to function in the environment of the present Large Hadron Collider (LHC). At the next-generation tracking detector proposed for the High Luminosity LHC (HL-LHC), the so-called ATLAS Phase-II Upgrade, the particle densities and radiation levels will be higher by as much as a factor of ten. The new detectors must be faster, they need to be more highly segmented, and covering more area. They also need to be more resistant to radiation, and they require much greater power delivery to the front-end systems. At the same time, they cannot introduce excess material which could undermine performance. For those reasons, the inner tracker of the ATLAS detector must be redesigned and rebuilt completely. The design of the ATLAS Upgrade inner tracker (ITk) has already been defined. It consists of several layers of silicon particle detectors. The innermost layers will be composed of silicon pixel sensors, and the outer layers will consist of s...

Anode front-end electronics for the cathode strip chambers of the CMS Endcap Muon detector

International Nuclear Information System (INIS)

Ferguson, T.; Bondar, N.; Golyash, A.; Sedov, V.; Terentiev, N.; Vorobiev, I.

2005-01-01

The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183,000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3x2.5 m 2 ) and for the large input capacitance (up to 200 pF). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2-3 ns). The delay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This paper presents the anode front-end electronics structure and results of the preproduction and the mass production tests, including radiation resistance and reliability tests. The special set of test equipment, techniques, and corresponding software developed and used in the test procedures are also described

ATLAS ITk Pixel detector

CERN Document Server

Gemme, Claudia; The ATLAS collaboration

2016-01-01

The high luminosity upgrade of the LHC (HL-LHC) in 2026 will provide new challenge to the ATLAS tracker. The current inner detector will be replaced with a whole silicon tracker which will consist of a five barrel layer Pixel detector surrounded by a four barrel layer Strip detector. The expected high radiation level are requiring the development of upgraded silicon sensors as well as new a front-end chip. The dense tracking environment will require finer granularity detectors. The data rates will require new technologies for high bandwidth data transmission and handling. The current status of the HL-LHC ATLA Pixel detector developments as well as the various layout options will be reviewed.

An Analysis of the Radiation Damage to the ATLAS Semiconductor Tracker End-Caps

CERN Document Server

Millar, Declan; Moretti, Stefano

The motivation, theoretical principles and analytical procedure for an assessment of the radiation damage to the ATLAS SCT end-caps is presented. An analysis of the leakage current across end-cap modules is performed for 2011 and 2012 data. A comparison between the observed and expected leakage current is made, with measurements favouring the shape of the theoretical evolution. Measured data is found to be systematically lower than predicted for a large subset of end-cap modules, while the remainder show surface current effects which interfere with bulk current observation. Uniform differences for modules at different radial distances suggest a radial temperature distribution in the end-caps, with absolute silicon sensor temperature to be established in further analysis.

Performance of the Tile PreProcessor Demonstrator for the ATLAS Tile Calorimeter Phase II Upgrade

OpenAIRE

Carrio Argos, Fernando; Valero, Alberto

2015-01-01

The Tile Calorimeter PreProcessor (TilePPr) demonstrator is a high performance double AMC board based on FPGA resources and QSFP modules. This board has been designed in the framework of the ATLAS Tile Calorimeter (TileCal) Demonstrator Project for the Phase II Upgrade as the first stage of the back-end electronics. The TilePPr demonstrator has been conceived for receiving and processing the data coming from the front-end electronics of the TileCal Demonstrator module, as well as for configur...

An ASIC implementation of digital front-end electronics for a high resolution PET scanner

International Nuclear Information System (INIS)

Newport, D.F.; Young, J.W.

1993-01-01

AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

The Phase-I Trigger Readout Electronics Upgrade for the ATLAS Liquid-Argon Calorimeters

CERN Document Server

Ochoa, Ines; The ATLAS collaboration

2017-01-01

Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, and performances on prototypes will presented with the overall system design.

The Phase-2 Electronics Upgrade of the ATLAS Liquid Argon Calorimeter System

CERN Document Server

Vachon, Brigitte; The ATLAS collaboration

2018-01-01

The LHC high-luminosity upgrade in 2024-2026 requires the associated detectors to operate at luminosities about 5-7 times larger than assumed in their original design. The pile-up is expected to increase to up to 200 events per proton bunch-crossing. The current readout of the ATLAS Liquid Argon (LAr) Calorimeters does not provide sufficient buffering and bandwidth capabilities to accommodate the hardware triggers requirements imposed by these harsh conditions. Furthermore, the expected total radiation doses are beyond the qualification range of the current front-end electronics. For these reasons an almost complete replacement of the LAr front-end and back-end readout system is foreseen for the 182,500 readout channels. The system will follow a free-running architecture, where the calorimeter signals are amplified, shaped and digitized by on-detector electronics, then sent at 40MHz to the backend, which performs the energy and time reconstruction, send inputs to the trigger, and buffers the data until trigge...

Utilizing a Novel Approach at the Fuzzy Front-End of New Product Development: A Case Study in a Flexible Fabric Supercapacitor

Directory of Open Access Journals (Sweden)

Gwo-Tsuen Jou

2016-08-01

Full Text Available The fuzzy front-end plays a most crucial part in new product development (NPD, leading to the success of product development and product launch in the market. This study proposes a novel method, TTRI_MP, by combining Crawford and Di Benedetto’s model and Cooper’s model, to strengthen the management of the fuzzy front-end. The proposed method comprises four stages: market exploration and technology forecasting, idea generation and segmentation, portfolio analysis and technology roadmapping (TRM. In the first stage, SWOT was utilized to identify the key strategic areas, and the technology readiness level (TRL was adopted to position the level of developed technologies. In the second stage, the business concepts were required to go through the viability test and customers, collaborators, competitors and company (4C. In the third stage, the Strategic Position Analysis (SPAN and Financial Analysis (FAN developed by IBM were employed in the portfolio analysis to screen out potential NPD projects. In the last stage, the selected NPD projects were linked with their functions and technologies in the TRM chart. The method was successfully implemented by a research team working on a flexible fabric supercapacitor at the Taiwan Textile Research Institute (TTRI.

Gravitational Reference Sensor Front-End Electronics Simulator for LISA

International Nuclear Information System (INIS)

Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; Zweifel, Peter; Giardini, Domenico; Ten Pierick, Jan

2017-01-01

At the ETH Zurich we are developing a modular simulator that provides a realistic simulation of the Front End Electronics (FEE) for LISA Gravitational Reference Sensor (GRS). It is based on the GRS FEE-simulator already implemented for LISA Pathfinder. It considers, in particular, the non-linearity and the critical details of hardware, such as the non-linear multiplicative noise caused by voltage reference instability, test mass charging and detailed actuation and sensing algorithms. We present the simulation modules, considering the above-mentioned features. Based on the ETH GRS FEE-simulator for LISA Pathfinder we aim to develop a modular simulator that provides a realistic simulation of GRS FEE for LISA. (paper)

2 MV injector as the Elise front-end and as an experimental facility

International Nuclear Information System (INIS)

Yu, S.S.; Eylon, S.; Henestroza, E.; Peters, C.; Reginato, L.; Tauschwitz, A.; Grote, D.; Deadrick, F.

1996-01-01

We report on progress in the preparation of the 2 MV injector at LBNL as the front end of Elise and as a multipurpose experimental facility for heavy ion fusion beam dynamics studies. Recent advances in the performance and understanding of the injector are described, and some of the ongoing experimental activities are summarized. (orig.)

A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

DEFF Research Database (Denmark)

Jensen, Brian Sveistrup; Johansen, Tom K.; Zhurbenko, Vitaliy

2013-01-01

In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured...

Using Micromegas in ATLAS to Monitor the Luminosity

CERN Document Server

The ATLAS collaboration

2013-01-01

Five small prototype micromegas detectors were positioned in the ATLAS detector during LHC running at $\\sqrt{s} = 8\\, \\mathrm{TeV}$. A $9\\times 4.5\\, \\mathrm{cm^2}$ two-gap detector was placed in front of the electromagnetic calorimeter and four $9\\times 10\\, \\mathrm{cm^2}$ detectors on the ATLAS Small Wheels, the first station of the forward muon spectrometer. The one attached to the calorimeter was exposed to interaction rates of about $70\\,\\mathrm{kHz/cm^2}$ at ATLAS luminosity $\\mathcal{L}=5\\times 10^{33}\\,\\mathrm{cm^{-2}s^{-1}}$ two orders of magnitude higher than the rates in the Small Wheel. We compare the currents drawn by the detector installed in front of the electromagnetic calorimeter with the luminosity measurement in ATLAS experiment.

Performance And Radiation Hardness Of The Atlas/sct Detector Module

CERN Document Server

Eklund, L

2003-01-01

The ATLAS experiment is a general purpose experiment being constructed at the Large Hadron Collider (LHC) at FERN, Geneva. ATLAS is designed to exploit the full physics potential of LHC, in particular to study topics concerning the Higgs mechanism, Super-symmetry and CP violation. The cross sections for the processes under study are extremely small, requiring very high luminosity colliding beams. The Semiconductor Tracker (SCT) is an essential part of the Inner Detector tracking system of ATLAS. The active elements of the SCT is 4088 detector modules, tiled on four barrel cylinders and eighteen endcap disks. As a consequence of the high luminosity, the detector modules will operate in a harsh radiation environment. This thesis describes work concerning radiation hardness, beam test performance and methods for production testing of detector modules. The radiation hardness studies have been focused on the electrical performance of the front-end ASIC and the detector module. The results have identified features ...

Integration of the Chinese HPC Grid in ATLAS Distributed Computing

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00081160; The ATLAS collaboration

2016-01-01

Fifteen Chinese High Performance Computing sites, many of them on the TOP500 list of most powerful supercomputers, are integrated into a common infrastructure providing coherent access to a user through an interface based on a RESTful interface called SCEAPI. These resources have been integrated into the ATLAS Grid production system using a bridge between ATLAS and SCEAPI which translates the authorization and job submission protocols between the two environments. The ARC Computing Element (ARC CE) forms the bridge using an extended batch system interface to allow job submission to SCEAPI. The ARC CE was setup at the Institute for High Energy Physics, Beijing, in order to be as close as possible to the SCEAPI front-end interface at the Computing Network Information Center, also in Beijing. This paper describes the technical details of the integration between ARC CE and SCEAPI and presents results so far with two supercomputer centers, Tianhe-IA and ERA. These two centers have been the pilots for ATLAS Monte C...

Integration of the Chinese HPC Grid in ATLAS Distributed Computing

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00081160

2017-01-01

Fifteen Chinese High-Performance Computing sites, many of them on the TOP500 list of most powerful supercomputers, are integrated into a common infrastructure providing coherent access to a user through an interface based on a RESTful interface called SCEAPI. These resources have been integrated into the ATLAS Grid production system using a bridge between ATLAS and SCEAPI which translates the authorization and job submission protocols between the two environments. The ARC Computing Element (ARC-CE) forms the bridge using an extended batch system interface to allow job submission to SCEAPI. The ARC-CE was setup at the Institute for High Energy Physics, Beijing, in order to be as close as possible to the SCEAPI front-end interface at the Computing Network Information Center, also in Beijing. This paper describes the technical details of the integration between ARC-CE and SCEAPI and presents results so far with two supercomputer centers, Tianhe-IA and ERA. These two centers have been the pilots for ATLAS Monte C...

Optical Parametric Chirped-Pulse Amplifier as the Front End for the OMEGA EP Laser Chain

International Nuclear Information System (INIS)

Bagnoud, V.; Begishev, I.A.; Guardalben, M.J.; Keegan, J.; Puth, J.; Waxer, L.J.; Zuegel, J.D.

2004-01-01

A 145-mJ optical parametric amplifier has been developed as a front-end source prototype for the OEMGA EP laser chain. The system definition is presented together with experimental results that show 30% conversion efficiency

Upgrading the ATLAS Tile Calorimeter Electronics

Directory of Open Access Journals (Sweden)

Carrió Fernando

2013-11-01

Full Text Available This work summarizes the status of the on-detector and off-detector electronics developments for the Phase 2 Upgrade of the ATLAS Tile Calorimeter at the LHC scheduled around 2022. A demonstrator prototype for a slice of the calorimeter including most of the new electronics is planned to be installed in ATLAS in the middle of 2014 during the first Long Shutdown. For the on-detector readout, three different front-end boards (FEB alternatives are being studied: a new version of the 3-in-1 card, the QIE chip and a dedicated ASIC called FATALIC. The Main Board will provide communication and control to the FEBs and the Daughter Board will transmit the digitized data to the off-detector electronics in the counting room, where the super Read-Out Driver (sROD will perform processing tasks on them and will be the interface to the trigger levels 0, 1 and 2.

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

Energy Technology Data Exchange (ETDEWEB)

Knopf, Jan

2009-07-08

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

Cryogenic receiver front-end with sharp skirt characteristics

Energy Technology Data Exchange (ETDEWEB)

Narahashi, S [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Satoh, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Kawai, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Koizumi, D [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Nojima, T [Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Hokkaido 060-0808 (Japan)

2006-05-15

This paper presents an experimental cryogenic receiver front-end (CRFE) with sharp skirt characteristics for mobile base stations. The CRFE comprises a high-temperature superconducting filter, a cryogenic low-noise amplifier, and a highly reliable cryostat that is very compact. The major characteristics of the proposed CRFE measured at 70 K are a centre frequency of 1.95 GHz, passband width of 20 MHz, sharp selectivity of 20 dB/100 kHz, 1.4 dB ripple, 31.3 dB average passband gain, and average passband equivalent noise temperature of 47.9 K. The CRFE weighs 19 kg and occupies 35 l. Random failure of the cryostat is also evaluated by a continuous operation test using four identical ones simultaneously. The cryostat used in the CRFE has a high reliability level of over five years of continuous maintenance-free operation.

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

Science.gov (United States)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

Structure and thermal analysis of the water cooling mask at NSRL front end

International Nuclear Information System (INIS)

Zhao Feiyun; Xu Chaoyin; Wang Qiuping; Wang Naxiu

2003-01-01

A water cooling mask is an important part of the front end, usually used for absorbing high power density synchrotron radiation to protect the apparatus from being destroyed by heat load. This paper presents the structure of the water cooling mask and the thermal analysis results of the mask block at NSRL using Program ANSYS5.5

System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

DEFF Research Database (Denmark)

di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere

2016-01-01

In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point...

AMIC: an expandable integrated analog front-end for light distribution moments analysis

OpenAIRE

SPAGGIARI, MICHELE; Herrero Bosch, Vicente; Lerche, Christoph Werner; Aliaga Varea, Ramón José; Monzó Ferrer, José María; Gadea Gironés, Rafael

2011-01-01

In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a cop...

Silicon Strip detectors for the ATLAS End-Cap Tracker at the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00232570

Inside physics programme of the LHC different experiment upgrades are foreseen. After the phase-II upgrade of the ATLAS detector the luminosity will be increased up to 5-7.5x10E34 cm-2s-1. This will mean a considerable increase in the radiation levels, above 10E16 neq/cm2 in the inner regions. This thesis is focused on the development of silicon microstrip detectors enough radiation hard to cope with the particle fluence expected at the ATLAS detector during HL-LHC experiment. In particular on the electrical characterization of silicon sensors for the ATLAS End-Caps. Different mechanical and thermal tests are shown using a Petal core as well as the electrical characterization of the silicon sensors that will be used with the Petal structure. Charge collection efficiency studies are carried out on sensors with different irradiation fluences using the ALiBaVa system and two kinds of strips connection are also analized (DC and AC ganging) with a laser system. The Petalet project is presented and the electrical c...

Front-end electronics for the ALICE calorimeters

CERN Document Server

Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

2010-01-01

The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

A Real Time Electronics Emulator with Realistic Data Generation for Reception Tests of the CMS ECAL Front-End Boards

CERN Document Server

Romanteau, T; Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N

2005-01-01

The CMS [1] electromagnetic calorimeter (ECAL) [2] uses 3 132 Front-End boards (FE) performing both trigger and data readout functions. Prior to their integration at CERN, the FE boards have to be validated by dedicated test bench systems. The final one, called "XFEST" (eXtended Front-End System Test) and for which the present developments have been performed, is located at Laboratoire Leprince-Ringuet. In this contribution, a solution is described to efficiently test a large set of complex electronics boards characterized by a large number of input ports and a high throughput data rate. To perform it, an algorithm to simulate the Very Front End signals has been emulated. The project firmwares use VHDL embedded into XILINX Field Programmable Gate Array circuits (FPGA). This contribution describes the solutions developed in order to create a realistic digital input patterns real-time emul ator working at 40 MHz. The implementation of a real time comparison of the FE output streams as well as the test bench wil...

Cross-compilation of ATLAS online software to the power PC-Vx works system

International Nuclear Information System (INIS)

Tian Yuren; Li Jin; Ren Zhengyu; Zhu Kejun

2005-01-01

BES III, selected ATLAS online software as a framework of its run-control system. BES III applied Power PC-VxWorks system on its front-end readout system, so it is necessary to cross-compile this software to PowerPC-VxWorks system. The article demonstrates several aspects related to this project, such as the structure and organization of the ATLAS online software, the application of CMT tool while cross-compiling, the selection and configuration of the cross-compiler, methods to solve various problems due to the difference of compiler and operating system etc. The software, after cross-compiling, can normally run, and makes up a complete run-control system with the software running on Linux system. (authors)

The Role of Devices in Staging Front End Innovation

DEFF Research Database (Denmark)

Clausen, Christian; Yoshinaka, Yutaka

2009-01-01

and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The paper examines...... into realisations. Inputs from different knowledge domains must be grappled with, both in terms of needing to be elucidated as well as synthesized, in the engineering design process. The paper argues that the existing research may be seen as a response to perceived difficulties in dealing with uncertain conditions...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

Electronic front-end for LHCb electromagnetic and hadronic calorimeters

International Nuclear Information System (INIS)

Beigbeder, Ch.

2000-11-01

The electronic front-end of the LHCb electromagnetic and hadronic calorimeters will be described. It consists of a 9U 32 channel board, each channel including shaper-integrator, 12 bit ADC and look-up tables allowing to code the transverse energy information both for readout and for the Level 0 trigger. The readout information is stored in a fixed latency followed by a derandomizer. The trigger information is processed further on the board by FPGA, performing channel addition and comparison to extract the highest transverse energy local cluster for further processing. The system is fully synchronous and allows to extract candidates for calorimetric trigger at every 40 MHz clock cycle. The operation and characteristics (noise, linearity etc.) of a prototype board will be described. (author)

Putting the use of intuition for fuzzy front end decision making on the research agenda

NARCIS (Netherlands)

Eling, K.; Langerak, F.

2011-01-01

Decision making literature suggests that intuitive decision making is more appropriate than the established rational decision making approaches to handle the specific information processing needs of the fuzzy front end (FFE) of new product development. However, these earlier studies cannot be

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B0s → J/ψ Φ

International Nuclear Information System (INIS)

Knopf, Jan

2009-01-01

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Φ s . It can be measured by using the golden decay mode B 0 s → J/ψ Φ. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

Testbeam studies of production modules of the ATLAS Tile Calorimeter

OpenAIRE

Adragna, P.; Alexa, C.; Anderson, K.; Antonaki, A.; Arabidze, A.; Batkova, L.; Batusov, V.; Beck, H.P.; Bednar, P.; Bergeaas Kuutmann, E.; Biscarat, C.; Blanchot, G.; Bogush, A.; Bohm, C.; Boldea, V.

2009-01-01

We report test beam studies of {11\\,\\%} of the production ATLAS Tile Calorimeter modules. The modules were equipped with production front-end electronics and all the calibration systems planned for the final detector. The studies used muon, electron and hadron beams ranging in energy from 3~GeV to 350~GeV. Two independent studies showed that the light yield of the calorimeter was $\\sim 70$~pe/GeV, exceeding the design goal by {40\\,\\%}. Electron beams provided a calibration of the modules at t...

Data acquisition and processing in the ATLAS tile calorimeter phase-II upgrade demonstrator

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00306349; The ATLAS collaboration

2017-01-01

The LHC has planned a series of upgrades culminating in the High Luminosity LHC which will have an average luminosity 5-7 times larger than the nominal Run 2 value. The ATLAS Tile Calorimeter will undergo an upgrade to accommodate the HL-LHC parameters. The TileCal readout electronics will be redesigned, introducing a new readout strategy. A Demonstrator program has been developed to evaluate the new proposed readout architecture and prototypes of all the components. In the Demonstrator, the detector data received in the Tile PreProcessors (PPr) are stored in pipeline buffers and upon the reception of an external trigger signal the data events are processed, packed and readout in parallel through the legacy ROD system, the new Front-End Link eXchange system and an ethernet connection for monitoring purposes. This contribution describes in detail the data processing and the hardware, firmware and software components of the TileCal Demonstrator readout system.

Construction of monitored drift tube chambers for ATLAS end-cap muon spectrometer at IHEP (Protvino)

CERN Document Server

Bensinger, J; Borisov, A; Fakhrutdinov, R M; Goryatchev, S; Goryachev, V N; Gushchin, V; Hashemi, K S; Kojine, A; Kononov, A I; Larionov, A; Paramoshkina, E; Pilaev, A; Skvorodnev, N; Tchougouev, A; Wellenstein, H

2002-01-01

Trapezoidal-shaped Monitored Drift Tube (MDT) chambers will be used in end-caps of ATLAS muon spectrometer. Design and construction technology of such chambers in IHEP (Protvino) is presented. X-ray tomography results confirm desirable 20 mum precision of wire location in the chamber.

LHCb: Test Station for the LHCb Muon Front-End Electronic

CERN Multimedia

Polycarpo, E

2005-01-01

The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

APPLICATION OF OBJECT ORIENTED PROGRAMMING TECHNIQUES IN FRONT END COMPUTERS

International Nuclear Information System (INIS)

SKELLY, J.F.

1997-01-01

The Front End Computer (FEC) environment imposes special demands on software, beyond real time performance and robustness. FEC software must manage a diverse inventory of devices with individualistic timing requirements and hardware interfaces. It must implement network services which export device access to the control system at large, interpreting a uniform network communications protocol into the specific control requirements of the individual devices. Object oriented languages provide programming techniques which neatly address these challenges, and also offer benefits in terms of maintainability and flexibility. Applications are discussed which exhibit the use of inheritance, multiple inheritance and inheritance trees, and polymorphism to address the needs of FEC software

Distributed Data Analysis in ATLAS

CERN Document Server

Nilsson, P; The ATLAS collaboration

2012-01-01

Data analysis using grid resources is one of the fundamental challenges to be addressed before the start of LHC data taking. The ATLAS detector will produce petabytes of data per year, and roughly one thousand users will need to run physics analyses on this data. Appropriate user interfaces and helper applications have been made available to ensure that the grid resources can be used without requiring expertise in grid technology. These tools enlarge the number of grid users from a few production administrators to potentially all participating physicists. ATLAS makes use of three grid infrastructures for the distributed analysis: the EGEE sites, the Open Science Grid, and NorduGrid. These grids are managed by the gLite workload management system, the PanDA workload management system, and ARC middleware; many sites can be accessed via both the gLite WMS and PanDA. Users can choose between two front-end tools to access the distributed resources. Ganga is a tool co-developed with LHCb to provide a common interfa...

Characterization of front-end electronics for CZT based handheld radioisotope identifier

Energy Technology Data Exchange (ETDEWEB)

Lombigit, L., E-mail: lojius@nm.gov.my [Malaysian Nuclear Agency, Bangi, 43000 Kajang, Selangor (Malaysia); Rahman, Nur Aira Abd; Mohamad, Glam Hadzir Patai; Ibrahim, Maslina Mohd; Yussup, Nolida; Yazid, Khairiah; Jaafar, Zainudin

2016-01-22

A radioisotope identifier device based on large volume Co-planar grid CZT detector is current under development at Malaysian Nuclear Agency. This device is planned to be used for in-situ identification of radioisotopes based on their unique energies. This work reports on electronics testing performed on the front-end electronics (FEE) analog section comprising charge sensitive preamplifier-pulse shaping amplifier chain. This test involves measurement of charge sensitivity, pulse parameters and electronics noise. This report also present some preliminary results on the spectral measurement obtained from gamma emitting radioisotopes.

A new design for SLAM front-end based on recursive SOM

Science.gov (United States)

Yang, Xuesi; Xia, Shengping

2015-12-01

Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

Science.gov (United States)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Enari, Yuji; The ATLAS collaboration

2018-01-01

Electronics developments are pursued for the trigger readout of the ATLAS Liquid-Argon Calorimeter towards the Phase-I upgrade scheduled in the LHC shut-down period of 2019-2020. The LAr Trigger Digitizer system will digitize 34000 channels at a 40 MHz sampling with 12 bit precision after the bipolar shaper at the front-end system, and transmit to the LAr Digital Processing system in the back-end to extract the transverse energies. Results of ASIC developments including QA and radiation hardness evaluations, performances of the final prototypes and results of the system integration tests will presented along with the overall system design.

Study of the 2004 End-Cap beam tests of the ATLAS detector

CERN Document Server

Bieri, Marco

The ATLAS detector is an all-purpose detector to study high-ener gy proton–proton colli- sions. ATLAS is located at the LHC (Lar ge Hadron Collider) at CERN in Gene va, Switzer - land. Before first data taking, man y beam tests have been carried out in order to fully understand each detector component. The studies in this thesis will concentrate on the 2004 beam test of the entire combined end-cap calorimeter system. The first section of this thesis outlines particle selection in the incoming test beam, eliminating contamination in order to have an accurate calibration environment. The remainder of the thesis focuses on detector calibration and performance studies, including signal-to-ener gy calibration con- stant determination, and various detector ener gy summation methods studying their effect on response. Ov erall detector ener gy sharing characteristics including the response of dead detector regions is also presented.

Performance of the ATLAS hadronic Tile calorimeter

CERN Document Server

Van Daalen, Tal Roelof; The ATLAS collaboration

2018-01-01

Performance of the ATLAS hadronic Tile calorimeter The Tile Calorimeter (TileCal) of the ATLAS experiment at the LHC is the central hadronic calorimeter designed for the reconstruction of hadrons, jets, tau-particles and missing transverse energy. TileCal is a scintillator-steel sampling calorimeter and it covers the region of pseudorapidity < 1.7. The scintillation light produced in the scintillator tiles is transmitted by wavelength shifting fibers to photomultiplier tubes (PMTs). The analog signals from the PMTs are amplified, shaped and digitized every 25 ns by sampling the signal. About 10000 channels of the front-end electronics measure the signals of the calorimeter with energies ranging from ~30 MeV to ~2 TeV. Each step of the signal reconstruction from scintillation light to the digital pulse reconstruction is monitored and calibrated. The performance of the calorimeter has been studied in-situ employing cosmic ray muons and a large sample of proton-proton collisions acquired during the operations...

Performance of the ATLAS Zero Degree Calorimeter

CERN Document Server

Leite, M; The ATLAS collaboration

2013-01-01

The ATLAS Zero Degree Calorimeter (ZDC) at the Large Hadron Collider (LHC) is a set of two sampling calorimeters modules symmetrically located at 140m from the ATLAS interaction point. The ZDC covers a pseudorapidity range of |eta| > 8.3 and it is both longitudinally and transversely segmented, thus providing energy and position information of the incident particles. The ZDC is installed between the two LHC beam pipes, in a configuration such that only the neutral particles produced at the interaction region can reach this calorimeter. The ZDC uses Tungsten plates as absorber material and rods made of quartz interspersed in the absorber as active media. The energetic charged particles crossing the quartz rods produces Cherenkov light which is then detected by photomultipliers and sent to the front end electronics for processing, in a total of 120 individual electronic channels. The Tungsten plates and quartz rods are arranged in a way to segment the calorimeters in 4 longitudinal sections. The first section (...

Development of telescope readout system based on FELIX for testbeam experiments

CERN Document Server

Wu, Weihao; Chen, Hucheng; Chen, Kai; Lacobucci, Giuseppe; Lanni, Francessco; Liu, Hongbin; Barrero Pinto, Mateus Vicente; Xu, Lailin

2017-01-01

The High Voltage CMOS (HV-CMOS) sensors are extensively investigated by the ATLAS collaboration in the High-Luminosity LHC (HL-LHC) upgrade of the Inner Tracker (ITk) detector. A testbeam telescope, based on the ATLAS IBL (Insertable B-Layer) silicon pixel modules, has been built to characterize the HV-CMOS sensor prototypes. The Front-End LInk eXchange (FELIX) system is a new approach to function as the gateway between front-ends and the commodity switched network in the different detectors of the ATLAS upgrade. A FELIX based readout system has been developed for the readout of the testbeam telescope, which includes a Telescope Readout FMC Card as interface between the IBL DC (double-chip) modules and a Xilinx ZC706 evaluation board. The test results show that the FELIX based telescope readout system is capable of sensor calibration and readout of a high-density pixel detector in test beam experiments in an effective way.

The nuclear fuel cycle desperately in need of front end alignment

International Nuclear Information System (INIS)

White, G.; Reaves, J.

1983-01-01

The front end of the nuclear fuel cycle which includes uranium supply, conversion of U308 to UF6 and enrichment of UF6, is characterized by excess capacity, excess production, growing inventories and price weakness. Excess capacity resulted from uncritical acceptance by suppliers of overly optimistic utility plans for nuclear growth. Cancellation and deferrals of nuclear plans led to reductions in forecast demand just as the new production capacity was coming on line to meet the high levels of demand forecast earlier. The unique and conservative nature of the utilities as business entities and the unique, sole-end-use character of uranium and its related fuel cycle services suggest that the markets for these materials and services will differ from those of other fuels. An international market is foreseen, marked by continuing boom-bust cycles

The first photon shutter development for APS insertion device beamline front ends

International Nuclear Information System (INIS)

Shu, Deming; Nian, H.L.T.; Wang, Zhibi; Collins, J.T.; Ryding, D.G.; Kuzay, T.M.

1992-01-01

One of the most critical components on the Advanced Photon Source (APS) insertion device (ID) beamline front ends is the first photon shutter. It operates in two modes to fully intercept the high total power and high-heat flux ID photon beam in seconds (normal mode) or in less than 100 ms (emergency fast mode). It is designed to operate in ultra high vacuum (UHV). The design incorporates a multi-channel rectangular bar, bent in a ''hockey stick'' configuration, with two-point suspension. The flanged end is an articulated bellows with rolling hinges. The actuation end is a spring-assisted, pneumatic fail-safe flexural pivot type. The coolant (water) channels incorporate brazed copper foam to enhance the heat transfer, a tube technology particular to the APS. The design development, and material aspects, as well as the extensive thermal and vibrational analyses in support of the design, are presented in this paper

Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

International Nuclear Information System (INIS)

Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

2008-01-01

The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

Managing Front-End Innovation through Idea Markets at Novozymes

DEFF Research Database (Denmark)

Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank

2013-01-01

Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in which...... a relatively small number of highly motivated participants screened their colleagues' inventions through an "idea market." The idea competition fulfilled its goals of generating two ideas with high growth potential within a short time, uncovering and recombining old proposals that inventors had not previously...... been able to advance in the organization and focusing managerial attention on the selection process. The campaign is an effective tool to recombine existing knowledge that had not been utilized. The process demonstrated that asking participants to comment on proposals improves idea generation...

Insulating electrodes: a review on biopotential front ends for dielectric skin–electrode interfaces

International Nuclear Information System (INIS)

Spinelli, Enrique; Haberman, Marcelo

2010-01-01

Insulating electrodes, also known as capacitive electrodes, allow acquiring biopotentials without galvanic contact with the body. They operate with displacement currents instead of real charge currents, and the electrolytic electrode–skin interface is replaced by a dielectric film. The use of insulating electrodes is not the end of electrode interface problems but the beginning of new ones: coupling capacitances are of the order of pF calling for ultra-high input impedance amplifiers and careful biasing, guarding and shielding techniques. In this work, the general requirements of front ends for capacitive electrodes are presented and the different contributions to the overall noise are discussed and estimated. This analysis yields that noise bounds depend on features of the available devices as current and voltage noise, but the final noise level also depends on parasitic capacitances, requiring a careful shield and printed circuit design. When the dielectric layer is placed on the skin, the present-day amplifiers allow achieving noise levels similar to those provided by wet electrodes. Furthermore, capacitive electrode technology allows acquiring high quality ECG signals through thin clothes. A prototype front end for capacitive electrodes was built and tested. ECG signals were acquired with these electrodes in direct contact with the skin and also through cotton clothes 350 µm thick. They were compared with simultaneously acquired signals by means of wet electrodes and no significant differences were observed between both output signals

The alignment system of the ATLAS muon end-cap spectrometer

International Nuclear Information System (INIS)

Schricker, A.

2002-08-01

The Large Hadron Collider at CERN will offer an unparalleled opportunity to probe fundamental physics at an energy scale well beyond that reached by current experiments. The ATLAS detector is being designed to fully exploit the potential of the LHC for revealing new aspects of the fundamental structure of nature. The muon spectrometer itself must measure with a momentum resolution of s10 % for muons with a transverse momentum of p T =1TeV, to fully exploit the advantages offered by the open superconducting air core muon toroid magnet system. At this level of momentum resolution the muon spectrometer relies heavily on the ability to master the alignment of the large muon chambers spaced far apart. The overall contribution of the alignment to the total sagitta error must be less than 30 μm r.m.s. In order to meet the stringent alignment requirements the positions of the muon chambers are constantly monitored with optical alignment technologies. The end-caps of this spectrometer are therefore embedded in an alignment grid that must allow for an absolute position measurement of the chambers. This alignment grid employs up to 9.6m long precision rulers (alignment bars) which have to provide the position and orientation of all alignment sensors permeating the end-caps. Simulation studies have shown that the shape of these bars must be known to 30 μm r.m.s. and the length must be known to 20 μm r.m.s. The principles of alignment and survey techniques used to do this are introduced and the current activities concerning the alignment strategy for the ATLAS muon end-cap spectrometer are presented. After consideration of the motivation and requirements, the measurement strategy and the design of the alignment bars is given. An optical and thermal in-bar instrumentation is used to provide shape information of discrete points on the bar. The strategy to calibrate the in-bar instrumentation and to measure an initial bar shape with a large coordinate measuring machine, leads

Front-end electronics for the Muon Portal project

Energy Technology Data Exchange (ETDEWEB)

Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M.C. [INAF, Osservatorio Astrofisico di Catania, Via S. Sofia 78, I-95123 Catania (Italy); Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D.G. [Università di Catania, Dipartimento di Fisica e Astronomia, and INFN, Sezione di Catania, Via S. Sofia 64, I-95123 Catania (Italy); Fallica, G.; Valvo, G. [ST-Microelectronics, Stradale V Primosole 50, Catania (Italy)

2016-10-11

The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

Development of new readout electronics for the ATLAS LAr Calorimeter at the sLHC

CERN Document Server

Strässner, A

2009-01-01

The readout of the ATLAS Liquid Argon (LAr) calorimeter is a complex multi-channel system to amplify, shape, digitize and process signals of the detector cells. The current on-detector electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2019/2020, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gb/s per front-end board. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system is given. The current R&D activities and architectural studies of the LAr Calorimeter group...

Development of new readout electronics for the ATLAS LAr calorimeter at the sLHC

CERN Document Server

Strässner, A

2009-01-01

The ATLAS Liquid Argon (LAr) calorimeter consists of 182,486 detector cells whose signals need to be read out, digitized and processed, in order to provide signal timing and the energy deposited in each detector element. The current readout electronics is not designed to sustain the ten times higher radiation levels expected at sLHC in the years beyond 2017, and will be replaced by new electronics with a completely different readout scheme. The future on-detector electronics is planned to send out all data continuously at each bunch crossing, as opposed to the current system which only transfers data at a trigger-accept signal. Multiple high-speed and radiation-resistant optical links will transmit 100 Gbps per front-end board, each covering 128 readout channels. The off-detector processing units will not only process the data in real-time and provide digital data buffering, but will also implement trigger algorithms. An overview about the various components necessary to develop such a complex system will be ...

Calculation Of Radon Gas Inhaled By A Front End Worker Of The Nuclear Fuel Cycles

International Nuclear Information System (INIS)

Soedardjo

1996-01-01

The calculation of Radon gas inhaled by workers in a front end nuclear fuel cycle has been studied. The cycle of front end nuclear fuel is underground uranium exploration on Remaja tunnel West Kalimantan. The activities of mining consider of drilling, blasting, transporting mineral and tunnel supporting were chosen, It is assumed that in one month, for a worker has four assignments namely in tunnel I, tunnel II, tunnel III and tunnel IV, The activities in the mine are divided into some categories, namely 12 hours of drilling, 2 hours of after blasting, 9 hours of mineral transportation and 8 hours of tunnel support construction. The result of calculation shows that the average Radon gas concentration on each particular location is still less than maximum permissible concentration 300 pCi/l. The prediction of maximum dose inhaled by one uranium miner during a year is 2.3 x 10 2 μCi which is less than BATAN regulation 7.3 x 10 2 μCi

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

International Nuclear Information System (INIS)

Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

2010-01-01

The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

Science.gov (United States)

Zhu, Tiezhu; Mo, Taishan; Ye, Tianchun

2017-12-01

An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor's transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of -28 dBm for a bit error rate of 10-10 at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm2 and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

The SSC field bus: A high-performance control system front end concentrator for 'slow' accelerator controls

International Nuclear Information System (INIS)

Haenni, D.R.; Saltmarsh, C.G.; Lue, H.C.; Hunt, S.M.

1991-01-01

The SSC control system must support a large number of 'slow' or industrial type control points. A front-end system is described which could serve as both a data concentrator and a distributed process controller for these points. Unlike many distributed control systems, this front end is designed to provide strong support for centralized controls. The live parameter data base in the central system can be updated at a rate which is fast compared to that usually needed for process control loops. Portions of this data base can be optionally replicated in regional computers to provide both local control stations and distributed control loops. In addition to the global and regional levels the system also allows the distribution of loops to the local I/O crate level. A possible implementation of this system is under development which is based on industrial standard STD-Bus for accelerator hardware interfacing, time domain multiplexing (TDM) for communications transport, and a form of reflective memory for the back-end interface to the rest of the control system

Construction of the new silicon microstrips tracker for the Phase-II ATLAS detector

CERN Document Server

Liang, Zhijun; The ATLAS collaboration

2018-01-01

The inner detector of the present ATLAS detector has been designed and developed to function in the environment of the present Large Hadron Collider (LHC). At the next-generation tracking detector proposed for the High Luminosity LHC (HL-LHC), the so-called ATLAS Phase-II Upgrade, the particle densities and radiation levels will be higher by as much as a factor of ten. The new detectors must be faster, they need to be more highly segmented, and covering more area. They also need to be more resistant to radiation, and they require much greater power delivery to the front-end systems. For those reasons, the inner tracker of the ATLAS detector must be redesigned and rebuilt completely. The design of the ATLAS Upgrade inner tracker (ITk) has already been defined. It consists of several layers of silicon particle detectors. The innermost layers will be composed of silicon pixel sensors, and the outer layers will consist of silicon microstrip sensors. This paper will focus on the latest research and development act...

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Science.gov (United States)

Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

2016-07-01

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Energy Technology Data Exchange (ETDEWEB)

Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

2016-07-11

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

S-LINK, a data link interface specification for the LHC era

International Nuclear Information System (INIS)

Bij, H.C. van der; McLaren, R.A.; Boyle, O.

1996-01-01

In the Technical Proposals for ATLAS, CMS and ALICE there is a requirement for several thousand data links. Although there is an obvious need for standardization, this seems difficult to achieve as the links run at different speeds, over different distances and have various constraints of power consumption, size and radiation hardness. An additional complication is that today we cannot decide which will be the most cost effective technology for the implementation of the final links. Furthermore, we must allow designers of boards at each end of the link, for example readout electronics and input buffers, to work in parallel with the development of the links. The S-LINK is a new concept which should provide the benefits of standardization without the limitations. The S-LINK specification defines, at both ends of the link, a simple FIFO-like user interface which remains independent of the technology used to implement the physical link. The physical link provides transfer of event data and control words, error detection, optional flow control and test facilities. This paper describes the S-LINK specification and gives examples of the use of the S-LINK, the physical links being designed, and the test equipment that is being developed

Analysis and design of a high-linearity receiver RF front-end with an improved 25%-duty-cycle LO generator for WCDMA/GSM applications

International Nuclear Information System (INIS)

Hu Song; Li Weinan; Huang Yumei; Hong Zhiliang

2012-01-01

A fully integrated receiver RF front-end that meets WCDMA/GSM system requirements is presented. It supports SAW-less operation for WCDMA. To improve the linearity in terms of both IP3 and IP2, the RF front-end is comprised of multiple-gated LNAs with capacitive desensitization, current-mode passive mixers with the proposed IP2 calibration circuit and reconfigurable Tow-Thomas-like biquad TIAs. A new power-saving multi-mode divider with low phase noise is proposed to provide the 4-phase 25%-duty-cycle LO. In addition, a constant-g m biasing with a non-chip resistor is adopted to make the conversion gain invulnerable to the process and temperature variations of the transimpedance. This RF front-end is integrated in a receiver with an on-chip frequency synthesizer in 0.13 μm CMOS. The measurement results show that owing to this high-linearity RF front-end, the receiver achieves −6 dBm IIP3 and better than +60 dBm IIP2 for all modes and bands. (semiconductor integrated circuits)

Integration of the Chinese HPC Grid in ATLAS Distributed Computing

Science.gov (United States)

Filipčič, A.; ATLAS Collaboration

2017-10-01

Fifteen Chinese High-Performance Computing sites, many of them on the TOP500 list of most powerful supercomputers, are integrated into a common infrastructure providing coherent access to a user through an interface based on a RESTful interface called SCEAPI. These resources have been integrated into the ATLAS Grid production system using a bridge between ATLAS and SCEAPI which translates the authorization and job submission protocols between the two environments. The ARC Computing Element (ARC-CE) forms the bridge using an extended batch system interface to allow job submission to SCEAPI. The ARC-CE was setup at the Institute for High Energy Physics, Beijing, in order to be as close as possible to the SCEAPI front-end interface at the Computing Network Information Center, also in Beijing. This paper describes the technical details of the integration between ARC-CE and SCEAPI and presents results so far with two supercomputer centers, Tianhe-IA and ERA. These two centers have been the pilots for ATLAS Monte Carlo Simulation in SCEAPI and have been providing CPU power since fall 2015.

The ATLAS Inner Detector operation,data quality and tracking performance.

CERN Document Server

Stanecka, E; The ATLAS collaboration

2012-01-01

The ATLAS Inner Detector comprises silicon and gas based detectors. The Semi-Conductor Tracker (SCT) and the Pixel Detector are the key precision tracking silicon devices in the Inner Detector of the ATLAS experiment at CERN LHC. And the the Transition Radiation Tracker (TRT), the outermost of the three subsystems of the ATLAS Inner Detector is made of thin-walled proportional-mode drift tubes (straws). The Pixel Detector consists of approximately 80 million pixels that are individually read out via chips bump-bonded to 1744 n-in-n silicon substrates. The SCT is a silicon strip detector and is constructed of 4088 silicon detector modules for a total of 6.3 million strips. Each module is designed, constructed and tested to operate as a stand-alone unit, mechanically, electrically, optically and thermally. The SCT silicon micro-strip sensors are processed in the planar p-in-n technology. The signals from the strips are processed in the front-end ASICS ABCD3TA, working in the binary readout mode. The TRT is made...

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Directory of Open Access Journals (Sweden)

Senkin Sergey

2018-01-01

Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

Science.gov (United States)

Senkin, Sergey

2018-01-01

The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

International Nuclear Information System (INIS)

Luo Yanbin; Ma Chengyan; Gan Yebing; Qian Min; Ye Tianchun

2015-01-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than −26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is −43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm 2 . (paper)

Numerical study of a magnetically insulated front-end channel for a neutrino factory

Directory of Open Access Journals (Sweden)

Diktys Stratakis

2011-01-01

Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

Design, development, installation and commissioning of water-cooled pre-masks for undulator front-ends of Indus-2

International Nuclear Information System (INIS)

Raghuvanshi, V.K.; Prasad, Vijendra; Garg, S.R.; Jain, Vikas

2015-01-01

Recently two undulators U1 and U2 are installed in Indus-2 storage ring at RRCAT, Indore. When U1 and U2 are put in operation, a bright synchrotron radiation (SR) is produced which is transmitted through the zero degree port of the dipole vacuum chamber. In addition, a part of SR beam from the bending magnets, at the upstream and downstream of the undulator, is also overlapped with the undulator SR beam and transmitted in to the front-end through the same port. The front-end is a long ultra high vacuum (UHV) assembly consisting of water-cooled pre-mask, water-cooled shutters, UHV valves, diagnostic devices, safety shutter, vacuum pumps etc which acts as an interface between Indus-2 ring and beamline. Water-cooled pre- masks have been designed to cut a part of unwanted SR beam from the bending magnets. The pre-mask is a first active component in the undulator front-end which is also capable of absorbing high thermal load due to mis-steering of the SR beam from the undulator in the worst case scenario. The watercooled pre-mask consists of a copper block which has fixed aperture with slant faces to distribute the heat flux over a large surface area. The cooling channels are made on outer periphery of the block. The copper block is vacuum brazed with two conflat flanges of stainless steel at the two ends. The pre-mask is designed to absorb thermal load of 3 kW of synchrotron beam from undulator U1 and 2 kW of synchrotron beam from undulator U2. The thermal analysis of the pre-masks was carried out with the help of ANSYS® and the design was optimized with different cooling configurations. The main design criteria was to limit the maximum temperature of the mask less than 60 °C. This is to avoid substantial thermal outgassing from the heated portion which may deteriorate the ultra high vacuum. Pre-masks have been successfully tested, installed and commissioned with synchrotron beam in the undulator front-ends and are operating under vacuum of 5x10 -10 mbar. (author)

The new version of the LHCb SOL40-SCA core to drive front-end GBT-SCAs for the LHCb upgrade

CERN Document Server

Viana Barbosa, Joao Vitor; Gaspar, Clara

2018-01-01

The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

Energy Technology Data Exchange (ETDEWEB)

Adinolfi, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Bibby, J.H. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Brisbane, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Gibson, V. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Harnew, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Jones, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Libby, J. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom)]. E-mail: j.libby1@physics.ox.ac.uk; Powell, A. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Newby, C. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Rotolo, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Smale, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Somerville, L.; Sullivan, P.; Topp-Jorgensen, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Wotton, S. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Wyllie, K. [CERN, CH-1211, Geneva 23 (Switzerland)

2007-03-11

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests.

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

International Nuclear Information System (INIS)

Adinolfi, M.; Bibby, J.H.; Brisbane, S.; Gibson, V.; Harnew, N.; Jones, M.; Libby, J.; Powell, A.; Newby, C.; Rotolo, N.; Smale, N.; Somerville, L.; Sullivan, P.; Topp-Jorgensen, S.; Wotton, S.; Wyllie, K.

2007-01-01

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests

Accurate Prediction of Transimpedances and Equivalent Input Noise Current Densities of Tuned Optical Receiver Front Ends

DEFF Research Database (Denmark)

Liu, Qing Zhong

1991-01-01

Novel analytical expressions have been derived for calculating transimpedances and equivalent input noise current densities of five tuned optical receiver front ends based on PIN diode and MESFETs or HEMTs. Miller's capacitance, which has been omitted in previous studies, has been taken...

The Versatile Link Demo Board (VLDB)

International Nuclear Information System (INIS)

Lesma, R. Martín; Alessio, F.; Barbosa, J.; Baron, S.; Caplan, C.; Leitao, P.; Porret, D.; Wyllie, K.; Pecoraro, C.

2017-01-01

The Versatile Link Demonstrator Board (VLDB) is the evaluation kit for the radiation-hard Optical Link ecosystem, which provides a 4.8 Gbps data transfer link for communication between front-end (FE) and back-end (BE) of the High Energy Physics experiments. It gathers the Versatile link main radiation-hard custom Application-Specific Integrated Circuits (ASICs) and modules: GBTx, GBT-SCA and VTRx/VTTx plus the FeastMP, a radiation-hard in-house designed DC-DC converter. This board is the first design allowing system-level tests of the Link with a complete interconnection of the constitutive components, allowing data acquisition, control and monitoring of FE devices with the GBT-SCA pair.

The Tilecal/ATLAS detector control system

CERN Document Server

Tomasio Pina, João Antonio

2004-01-01

Tilecal is the barrel hadronic calorimeter of the ATLAS detector that is presently being built at CERN to operate at the LHC accelerator. The main task of the Tilecal detector control system (DCS) is to enable the coherent and safe operation of the detector. All actions initiated by the operator and all errors, warnings, and alarms concerning the hardware of the detector are handled by DCS. The DCS has to continuously monitor all operational parameters, give warnings and alarms concerning the hardware of the detector. The DCS architecture consists of a distributed back-end (BE) system running on PC's and different front-end (FE) systems. The implementation of the BE will he achieved with a commercial supervisory control and data acquisition system (SCADA) and the FE instrumentation will consist on a wide variety of equipment. The connection between the FE and BE is provided by fieldbus or L

Prof. Manuel Trajtenberg, Chair of the Planning and Budget Committee, Council for Higher Education in Israel with CERN Director-General R. Heuer and in front of the ATLAS detector on Thursday 14th January.

CERN Multimedia

Maximilien Brice; Point 1

2010-01-01

Prof. Manuel Trajtenberg, Chair of the Planning and Budget Committee, Council for Higher Education in Israel with CERN Director-General R. Heuer and in front of the ATLAS detector on Thursday 14th January.

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

International Nuclear Information System (INIS)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

2015-01-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

Energy Technology Data Exchange (ETDEWEB)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

2015-07-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

A Programmable Biopotential Aquisition Front-end with a Resistance-free Current-balancing Instrumentation Amplifier

Directory of Open Access Journals (Sweden)

FARAGO, P.

2018-05-01

Full Text Available The development of wearable biomedical equipment benefits from low-power and low-voltage circuit techniques for reduced battery size and battery, or even battery-less, operation. This paper proposes a fully-differential low-power resistance-free programmable instrumentation amplifier for the analog front-end of biopotential monitoring systems. The proposed instrumentation amplifier implements the current balancing technique. Low power consumption is achieved with subthreshold biasing. To reduce chip area and enable integration, passive resistances have been replaced with active equivalents. Accordingly, the instrumentation amplifier gain is expressed as the ratio of two transconductance values. The proposed instrumentation amplifier exhibits two degrees of freedom: one to set the desired range and the other for fine-tuning of the voltage gain. The proposed IA is employed in a programmable biopotential acquisition front-end. The programmable frequency-selective behavior is achieved by having the lower cutoff frequency of a Gm-C Tow-Thomas biquad varied in a constant-C tuning approach. The proposed solutions and the programmability of the operation parameters to the specifications of particular bio-medical signals are validated on a 350nm CMOS process.

The Study of Fault Location for Front-End Electronics System

International Nuclear Information System (INIS)

Zhang Fan; Wang Dong; Huang Guangming; Zhou Daicui

2009-01-01

Since some devices on the latest developed 250 ALICE/PHOS Front-end electronics (FEE) system cards had been partly or completely damaged during lead-free soldering. To alleviate the influence on the performance of FEE system and to locate fault related FPGA accurately, we should find a method for locating fault of FEE system based on the deep study of FPGA configuration scheme. It emphasized on the problems such as JTAG configuration of multi-devices, PS configuration based on EPC series configuration devices and auto re-configuration of FPGA. The result of the massive FEE system cards testing and repairing show that that location method can accurately and quickly target the fault point related FPGA on FEE system cards. (authors)

A CMOS analog front-end chip for amperometric electrochemical sensors

International Nuclear Information System (INIS)

Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

2015-01-01

This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

ATLAS End Cap Toroid Magnets cold mass design and manufacturing status

CERN Document Server

Baynham, D Elwyn; Carr, F S; Densham, C J; Holtom, E; Morrow, D; Towndrow, E F; Luijckx, G; Geerinck, J

2004-01-01

The End Cap Toroid Magnets for the ATLAS experiment at LHC, CERN will contain eight racetrack coils mounted as a single cold mass in a cryostat vessel of approximately 10 m diameter. This paper presents the engineering design of the cold mass and gives the status of the industrial production. The cold mass mechanical structure consisting of 8 coils and keystone boxes is described. Coil fabrication from component assembly, coil winding to final impregnation will be reviewed. The design and industrial manufacture of the keystone box elements is given. The cold mass assembly methods and status are described. 3 Refs.

Controller design and implementation of a three-phase Active Front End using SiC based MOSFETs

DEFF Research Database (Denmark)

Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

2015-01-01

The design and implementation of a three phase Active Front End for power factor correction purposes using fast switching SiC based MOSFETs is presented. Possible applications are within the drives- and renewable energy sector. The controller is designed and implemented in the synchronous rotating...

A front-end ASIC for ionising radiation monitoring with femto-amp capabilities

International Nuclear Information System (INIS)

Voulgari, E.; Noy, M.; Anghinolfi, F.; Perrin, D.; Krummenacher, F.; Kayal, M.

2016-01-01

An ultra-low leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 μm CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) through charge balancing and demonstrates a wide dynamic range of 8.5 decades without range changing. Due to a design aimed at minimising input leakage currents, input currents as low as 01 fA can be measured

Rabbit System. Low cost, high reliability front end electronics featuring 16 bit dynamic range

International Nuclear Information System (INIS)

Drake, G.; Droege, T.F.; Nelson, C.A. Jr.; Turner, K.J.; Ohska, T.K.

1985-10-01

A new crate-based front end system has been built which features low cost, compact packaging, command capability, 16 bit dynamic range digitization, and a high degree of redundancy. The crate can contain a variety of instrumentation modules, and is designed to be situated close to the detector. The system is suitable for readout of a large number of channels via parallel multiprocessor data acquisition

Solid-State Photomultiplier with Integrated Front End Electronics

Science.gov (United States)

Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

2009-10-01

The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

A front-end system for industrial type controls at the SSC

International Nuclear Information System (INIS)

Haenni, D.R.

1992-01-01

The SSC control system is tasked with coordinating the operation of many different accelerator subsystems, a number of which use industrial type process controls. The design of a high-performance control system front end is presented which serves both as a data concentrator and a distributed process controller. In addition it provides strong support for a centralized control system architecture, allows for regional control systems, and simplifies the construction of inter-subsystem controls. An implementation of this design will be discussed which uses STD-Bus for accelerator hardware interfacing, a time domain multiplexing (TDM) communications transport system, and a modified reflective memory interface to the rest of the control system. (author)

A new strips tracker for the upgraded ATLAS ITk detector

Science.gov (United States)

David, C.

2018-01-01

The ATLAS detector has been designed and developed to function in the environment of the present Large Hadron Collider (LHC). At the next-generation tracking detector proposed for the High Luminosity LHC (HL-LHC), the so-called ATLAS Phase-II Upgrade, the fluences and radiation levels will be higher by as much as a factor of ten. The new sub-detectors must thus be faster, of larger area, more segmented and more radiation hard while the amount of inactive material should be minimized and the power supply to the front-end systems should be increased. For those reasons, the current inner tracker of the ATLAS detector will be fully replaced by an all-silicon tracking system that consists of a pixel detector at small radius close to the beam line and a large area strip tracker surrounding it. This document gives an overview of the design of the strip inner tracker (Strip ITk) and summarises the intensive R&D activities performed over the last years by the numerous institutes within the Strips ITk collaboration. These studies are accompanied with a strong prototyping effort to contribute to the optimisation of the Strip ITk's structure and components. This effort culminated recently in the release of the ATLAS Strips ITk Technical Design Report (TDR).