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Sample records for atlas front-end links

  1. Irradiation studies of multimode optical fibres for use in ATLAS front-end links

    CERN Document Server

    Mahout, G; Andrieux, M L; Arvidsson, C B; Charlton, D G; Dinkespiler, B; Dowell, John D; Gallin-Martel, L; Homer, R James; Jovanovic, P; Kenyon, Ian Richard; Kuyt, G; Lundqvist, J M; Mandic, I; Martin, O; Shaylor, H R; Stroynowski, R; Troska, Jan K; Wastie, R L; Weidberg, A R; Wilson, J A; Ye, J

    2000-01-01

    The radiation tolerance of three multimode optical fibres has been investigated to establish their suitability for the use in the front- end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of ~0.05 dB/m at 330 kGy (Si) and 1*10/sup 15/ n(1 MeV Si)/cm/sup 2/ and is suitable for use with the inner detector links which operate at 40-80 Mb/s. A graded- index fibre with a predominantly germanium-doped core exhibits an induced attenuation of ~0.1 dB/m at 800 Gy(Si) and 2*10/sup 13/ n(1 MeV Si)/cm/sup 2/ and is suitable for the calorimeter links which operate at 1.6 Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower. (30 refs).

  2. Irradiation studies of multimode optical fibres for use in ATLAS front-end links

    International Nuclear Information System (INIS)

    Mahout, G.; Pearce, M.; Andrieux, M-L.; Arvidsson, C-B.; Charlton, D.G.; Dinkespiler, B.; Dowell, J.D.; Gallin-Martel, L.; Homer, R.J.; Jovanovic, P.; Kenyon, I.R.; Kuyt, G.; Lundquist, J.; Mandic, I.; Martin, O.; Shaylor, H.R.; Stroynowski, R.; Troska, J.; Wastie, R.L.; Weidberg, A.R.; Wilson, J.A.; Ye, J.

    2000-01-01

    The radiation tolerance of three multimode optical fibres has been investigated to establish their suitability for the use in the front-end data links of the ATLAS experiment. Both gamma and neutron irradiation studies are reported. A step-index fibre with a pure silica core showed an induced attenuation of ∼0.05 dB/m at 330 kGy(Si) and 1x10 15 n(1 MeV Si)/cm 2 and is suitable for use with the inner detector links which operate at 40-80 Mb/s. A graded-index fibre with a predominantly germanium-doped core exhibits an induced attenuation of ∼0.1 dB/m at 800 Gy(Si) and 2x10 13 n(1 MeV Si)/cm 2 and is suitable for the calorimeter links which operate at 1.6 Gb/s. Measurements of the dose rate dependence of the induced attenuation indicate that the attenuation in ATLAS will be lower

  3. An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

  4. An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Silverstein, Samuel; The ATLAS collaboration

    2017-01-01

    We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

  5. The ATLAS tile calorimeter front end electronics

    CERN Document Server

    Martin, F

    2002-01-01

    After a short description of the ATLAS (1999) tile calorimeter front end electronics, the quality control procedure is presented. It is required both to ensure that the electronics match the ATLAS requirements and to face the complexity of any maintenance access in ATLAS. The test benches dedicated to tests of more than 10000 photomultipliers and all 256 entire electronics modules are described, and some results about the radiation hardness are given. (17 refs).

  6. Front end data link processor

    International Nuclear Information System (INIS)

    Wallace, J.J.

    1988-01-01

    It is possible to expand the data acquisition capabilities of an existing process computer to include other dedicated computer based systems, provided each system has at least minimal data link capabilities. The following paper discusses the addition of three computer based acquisition systems to a Honeywell 4500C (also designated the 45000) running the SEER system. Only one data link port was required to support the link. Each of the three specialized systems implemented data link protocols used by their suppliers in previous projects: none of the three were compatible with Honeywell's protocol. Part one of the following provides a generic overview of the project and would be relevent to the operator of any process system interested in expansion. Part two provides specific details of this project and may serve to provide performance benchmarks to those who wish to consider a similar project

  7. ATLAS LAr Phase upgrade of the Front End Electronics

    CERN Document Server

    Newcomer, Mitchel; The ATLAS collaboration

    2016-01-01

    The Phase II upgrade of the ATLAS Liquid Argon detector includes a 17 bit dynamic range front end amplifier with a two or three gain multi‐pole shaper employing CR‐(RC)n shaping. Each gain stage of the shaper will be followed by a 40Msps, 14b dynamic range, 12‐13b ENOB digitizer, serializer and fiber optic driver. A study is underway to see if a single technology (65nm or 130nm CMOS) will be suitable for all blocks up to the optical Link, enabling consideration of the development a Front End System On a Chip (FESOC).

  8. Development of an analogue optical link for the front-end read-out of the ATLAS electromagnetic calorimeter

    CERN Document Server

    Dinkespiler, B; Olivetto, C; Martin, O; Mirea, A; Monnier, E; Tisserant, S; Wielers, M; Andrieux, M L; Ballon, J; Collot, J; Patti, A; Eek, L O; Go, A; Lund-Jensen, B; Pearce, M; Söderqvist, J; Coulon, J P

    1999-01-01

    We have developed an analogue optical data transmission system intended to meet the read-out requirements of the ATLAS liquid argon electromagnetic calorimeter. Eight-way demonstrators have been built and tested. The link uses arrays of VCSEL diodes as the optical emitters, coupled to a 70 m long fibre ribbon to simulate the distance between the detector and the control room. The receiver is based around a custom-designed PIN photodiode array. We describe here the final results of laboratory tests on a demonstrator, laying stress on the VCSEL-to-fibre coupling issues, and the overall performance of the full link. A 9-bit dynamic range is achieved, with a 5on-linearity.

  9. Radiation hardness studies of the front-end ASICs for the optical links of the ATLAS semiconductor tracker

    CERN Document Server

    White, D J; Mahout, G; Jovanovic, P; Mandic, I; Weidberg, A R

    2001-01-01

    Studies have been performed on the effects of radiation on ASICs incorporating bipolar npn transistors in the AMS 0.8 mu m BiCMOS process. Radiation effects are reviewed and the approach used to achieve radiation tolerant ASICs is described. The radiation tests required to validate the ASICs for use in the ATLAS detector at the CERN Large Hadron Collider are discussed. The results demonstrate that they are sufficiently radiation tolerant for use in the ATLAS semiconductor tracker. (20 refs).

  10. MDT-ASD, CMOS front-end for ATLAS MDT

    CERN Document Server

    Posch, C; Oliver, J

    2007-01-01

    This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

  11. FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    NARCIS (Netherlands)

    Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Plessl, C.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Zhang, J.

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will

  12. A new approach to front-end electronics interfacing in the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2, a new approach will be followed for Front-End electronics interfacing. The FELIX (Front-End LInk eXchange) system will function as gateway connecting: on one side to detector and trigger electronics links, as well as providing timing and trigger (TTC) information; and on the other side a commodity switched network built using standard technology (either Ethernet or Infiniband). The new approach is described in this paper, and results achieved so far are presented.

  13. FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

  14. FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Plessl, Christian; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24~Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented, and hardware and ...

  15. The new Front End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00226662; The ATLAS collaboration

    2016-01-01

    We present the plans, design, and performance results to date for the new front end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  16. The New Front End Electronics For the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Gomes, Agostinho; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be describ...

  17. The new front-end electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    Science.gov (United States)

    Gomes, A.

    2016-02-01

    We present the plans, design, and performance results to date for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increased luminosity at the HL-LHC around 2025, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector. The new on-detector electronics contains five main parts: the front-end boards that connect directly to the photomultiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low voltage power supply. There are different options for implementing these subcomponents, which will be described. The new system contains new features that in the current version include power system redundancy, data collection redundancy, data transmission redundancy with 2 QSFP optical transceivers and Kintex-7 FPGAs with firmware enhanced scheme for single event upset mitigation. To date, we have built a Demonstrator—a fully functional prototype of the new system. Performance results and plans are presented.

  18. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2015-01-01

    We present the plans, design, and performance results to date ofor the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the front-end boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcompone...

  19. The New Front-End Electronics for the ATLAS Tile Calorimeter Phase 2 Upgrade

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00029377; The ATLAS collaboration

    2015-01-01

    We present the design for the new front-end electronics being developed for the Phase 2 Upgrade of the ATLAS Tile Calorimeter. The front-end electronics will be replaced to address the increase in beam energy and luminosity planned for the LHC around 2023, as well as to upgrade to faster, more modern components with higher radiation tolerance. The new electronics will operate dead-timelessly, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room. The new electronics contains five main parts: the Front End Boards that connect directly to the photo-multiplier tubes; the Main Boards that digitize the data; the Daughter Boards that collect the data streams and contain the high-speed optical communication links for writing data to the data acquisition system; a programmable high voltage control system; and a new low-voltage power supply. There are different options for implementing these subcomponents, which will be described. The new sys...

  20. Dead-time free pixel readout architecture for ATLAS front-end IC

    CERN Document Server

    Einsweiler, Kevin F; Kleinfelder, S A; Luo, L; Marchesini, R; Milgrome, O; Pengg, F X

    1999-01-01

    A low power sparse scan readout architecture has been developed for the ATLAS pixel front-end IC. The architecture supports a dual discriminator and extracts the time over threshold (TOT) information along with a 2-D spatial address $9 of the hits associating them with a unique 7-bit beam crossing number. The IC implements level-1 trigger filtering along with event building (grouping together all hits in a beam crossing) in the end of column (EOC) buffer. The $9 events are transmitted over a 40 MHz serial data link with the protocol supporting buffer overflow handling by appending error flags to events. This mixed-mode full custom IC is implemented in 0.8 mu HP process to meet the $9 requirements for the pixel readout in the ATLAS inner detector. The circuits have been tested and the IC provides dead-time-less ambiguity free readout at 40 MHz data rate.

  1. Computing challenges in the certification of ATLAS Tile Calorimeter front-end electronics during maintenance periods

    International Nuclear Information System (INIS)

    Solans, C; Carrió, F; Valero, A; Kim, H Y; Usai, G; Moreno, P; Reed, R; Sandrock, C; Ruan, X; Shalyugin, A; Schettino, V; Souza, J

    2014-01-01

    After two years of operation of the LHC, the ATLAS Tile calorimeter is undergoing a consolidation process of its front-end electronics. The certification is performed in the experimental area with a portable test-bench which is capable of controlling and reading out one front-end module through dedicated cables. This test-bench has been redesigned to improve the tests of the electronics functionality quality assessment of the data until the end of Phase I.

  2. Design of the Front-End Detector Control System of the ATLAS New Small Wheels

    CERN Document Server

    Koulouris, Aimilianos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

  3. Design and implementation of the ATLAS TRT front end electronics

    Science.gov (United States)

    Newcomer, Mitch; Atlas TRT Collaboration

    2006-07-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

  4. Design and implementation of the ATLAS TRT front end electronics

    International Nuclear Information System (INIS)

    Newcomer, Mitch

    2006-01-01

    The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

  5. FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

    CERN Document Server

    Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

    2015-01-01

    The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

  6. Development of front-end electronics and TDC LSI for the ATLAS MDT

    CERN Document Server

    Arai, Y

    2000-01-01

    Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

  7. Test system for the production of the Atlas Tile Calorimeter front-end electronics

    International Nuclear Information System (INIS)

    Calvet, David

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

  8. Test system for the production of the ATLAS Tile Calorimeter front- end electronics

    CERN Document Server

    Calvet, D

    2004-01-01

    The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called "super-drawers". The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion.

  9. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    International Nuclear Information System (INIS)

    Carrió, F; Valero, A; Kim, H Y; Usai, G; Moreno, P; Reed, R; Sandrock, C; Schettino, V; Souza, J; Shalyugin, A; Solans, C

    2014-01-01

    The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception

  10. Overview of the front end electronics for the Atlas LAR calorimeter

    International Nuclear Information System (INIS)

    Rescia, S.

    1997-11-01

    Proposed experiments for the Large Hadron Collider (LHC) set new demands on calorimeter readout electronics. The very high energy and large luminosity of the collider call for a large number of high speed, large dynamic range readout channels which have to be carefully synchronized. The ATLAS liquid argon collaboration, after more than 5 years of R and D developments has now finalized the architecture of its front end and read-out electronics, which have been written down in its Technical Design Report (TDR). An overview is presented

  11. Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

    2016-01-01

    The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

  12. FATALIC: A Dedicated Front-End ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Royer, Laurent; The ATLAS collaboration

    2015-01-01

    A front-end ASIC (FATALIC) has been developed to fulfil the requirements of the Phase 2 upgrade of the ATLAS Tile Calorimeter. This electronics performs the complete processing of the signal delivered by each PM tube. The first stage is a current conveyor which splits the 17-bit dynamic range of the input signal into three ranges. Each channel is followed by a shaper and a dedicated pipeline 12-bit ADC operating at 40MHz. The chip is developed using a 130nm CMOS technology. Measurements show a linearity better than 0.5% for low energy particles, and an ENC limited to 10 fC.

  13. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Schreuder, Frans Philip; The ATLAS collaboration

    2018-01-01

    Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

  14. A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

    International Nuclear Information System (INIS)

    Alves, J.; Carrio, F.; Moreno, P.; Usai, G.; Valero, A.; Kim, H.Y.; Minashvili, I.; Shalyugin, A.; Reed, R.; Schettino, V.; Souza, J.; Solans, C.

    2013-06-01

    This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

  15. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    Energy Technology Data Exchange (ETDEWEB)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-03-19

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented.

  16. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  17. SEU rate estimates for the ATLAS/SCT front-end ASIC

    CERN Document Server

    Eklund, L; Grigson, C; Kramberger, G; Mandic, I; Mikuz, M; Phillips, P

    2003-01-01

    We present a method of estimating the sensitivity to radiation- induced Single Event Upset (SEU) in the front-end ASICs for the ATLAS Semiconductor Tracker. The method is using ASICs of the final design with limited read-back possibilities of internal registers. Hence the measurement is adapted to utilise the event-data flow in the digital part of the ASIC to detect bit-flips. Furthermore, we report on the application of this method to estimate the SEU sensitivity. The results presented are based on data from three irradiation periods using prototype electronics hybrids and detector modules. The measurements were done with 24 GeV/c protons and 200 MeV/c pions.

  18. Digital column readout architecture for the ATLAS pixel 025 mum front end IC

    CERN Document Server

    Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

    2002-01-01

    A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

  19. Prototype ATLAS IBL Modules using the FE-I4A Front-End Readout Chip

    CERN Document Server

    Albert, J; Alimonti, Gianluca; Allport, Phil; Altenheiner, Silke; Ancu, Lucian; Andreazza, Attilio; Arguin, Jean-Francois; Arutinov, David; Backhaus, Malte; Bagolini, Alvise; Ballansat, Jacques; Barbero, Marlon; Barbier, Gérard; Bates, Richard; Battistin, Michele; Baudin, Patrick; Beau, Tristan; Beccherle, Roberto; Beck, Hans Peter; Benoit, Mathieu; Bensinger, Jim; Bomben, Marco; Borri, Marcello; Boscardin, Maurizio; Botelho Direito, Jose Antonio; Bousson, Nicolas; Boyd, George Russell Jr; Breugnon, Patrick; Bruni, Graziano; Bruschi, Marco; Buchholz, Peter; Buttar, Craig; Cadoux, Franck; Calderini, Giovanni; Caminada, Leah; Capeans, Mar; Casse, Gianluigi; Catinaccio, Andrea; Cavalli-Sforza, Matteo; Chauveau, Jacques; Chu, Ming-Lee; Ciapetti, Marco; Cindro, Vladimir; Citterio, Mauro; Clark, Allan; Cobal, Marina; Coelli, Simone; Colijn, Auke-Pieter; Colin, Daly; Collot, Johann; Crespo-Lopez, Olivier; Dalla Betta, Gian-Franco; Darbo, Giovanni; DaVia, Cinzia; David, Pierre-Yves; Debieux, Stéphane; Delebecque, Pierre; Devetak, Erik; DeWilde, Burton; Di Girolamo, Beniamino; Dinu, Nicoleta; Dittus, Fridolin; Diyakov, Denis; Djama, Fares; Dobos, Daniel Adam; Doonan, Kate; Dopke, Jens; Dorholt, Ole; Dube, Sourabh; Dushkin, Andrey; Dzahini, Daniel; Egorov, Kirill; Ehrmann, Oswin; Elldge, David; Elles, Sabine; Elsing, Markus; Eraud, Ludovic; Ereditato, Antonio; Eyring, Andreas; Falchieri, Davide; Falou, Aboud; Fang, Xiaochao; Fausten, Camille; Favre, Yannick; Ferrere, Didier; Fleta, Celeste; Fleury, Julien; Flick, Tobias; Forshaw, Dean; Fougeron, Denis; Fritzsch, Thomas; Gabrielli, Alessandro; Gaglione, Renaud; Gallrapp, Christian; Gan, K; Garcia-Sciveres, Maurice; Gariano, Giuseppe; Gastaldi, Thibaut; Gemme, Claudia; Gensolen, Fabrice; George, Matthias; Ghislain, Patrick; Giacomini, Gabriele; Gibson, Stephen; Giordani, Mario Paolo; Giugni, Danilo; Gjersdal, Håvard; Glitza, Karl Walter; Gnani, Dario; Godlewski, Jan; Gonella, Laura; Gorelov, Igor; Gorišek, Andrej; Gössling, Claus; Grancagnolo, Sergio; Gray, Heather; Gregor, Ingrid-Maria; Grenier, Philippe; Grinstein, Sebastian; Gromov, Vladimir; Grondin, Denis; Grosse-Knetter, Jörn; Hansen, Thor-Erik; Hansson, Per; Harb, Ali; Hartman, Neal; Hasi, Jasmine; Hegner, Franziska; Heim, Timon; Heinemann, Beate; Hemperek, Tomasz; Hessey, Nigel; Hetmánek, Martin; Hoeferkamp, Martin; Hostachy, Jean-Yves; Hügging, Fabian; Husi, Coralie; Iacobucci, Giuseppe; Idarraga, John; Ikegami, Yoichi; Janoška, Zdenko; Jansen, Jens; Jansen, Luc; Jensen, Frank; Jentzsch, Jennifer; Joseph, John; Kagan, Harris; Karagounis, Michael; Kass, Richard; Kenney, Christopher J; Kersten, Susanne; Kind, Peter; Klingenberg, Reiner; Kluit, Ruud; Kocian, Martin; Koffeman, Els; Kok, Angela; Korchak, Oleksandr; Korolkov, Ilya; Kostyukhin, Vadim; Krieger, Nina; Krüger, Hans; Kruth, Andre; Kugel, Andreas; Kuykendall, William; La Rosa, Alessandro; Lai, Chung-Hang; Lantzsch, Kerstin; Laporte, Didier; Lapsien, Tobias; Lounis, abdenour; Lozano, Manuel; Lu, Yunpeng; Lubatti, Henry; Macchiolo, Anna; Mallik, Usha; Mandić, Igor; Marchand, Denis; Marchiori, Giovanni; Massol, Nicolas; Matthias, Wittgen; Mättig, Peter; Mekkaoui, Abderrazak; Menouni, Mohsine; Menu, Johann; Meroni, Chiara; Mesa, Javier; Micelli, Andrea; Michal, Sébastien; Miglioranzi, Silvia; Mikuž, Marko; Mitsui, Shingo; Monti, Mauro; Moore, J; Morettini, Paolo; Muenstermann, Daniel; Murray, Peyton; Nellist, Clara; Nelson, David J; Nessi, Marzio; Neumann, Manuel; Nisius, Richard; Nordberg, Markus; Nuiry, Francois-Xavier; Oppermann, Hermann; Oriunno, Marco; Padilla, Cristobal; Parker, Sherwood; Pellegrini, Giulio; Pelleriti, Gabriel; Pernegger, Heinz; Piacquadio, Nicola Giacinto; Picazio, Attilio; Pohl, David; Polini, Alessandro; Popule, Jiří; Portell Bueso, Xavier; Povoli, Marco; Puldon, David; Pylypchenko, Yuriy; Quadt, Arnulf; Quirion, David; Ragusa, Francesco; Rambure, Thibaut; Richards, Erik; Ristic, Branislav; Røhne, Ole; Rothermund, Mario; Rovani, Alessandro; Rozanov, Alexandre; Rubinskiy, Igor; Rudolph, Matthew Scott; Rummler, André; Ruscino, Ettore; Salek, David; Salzburger, Andreas; Sandaker, Heidi; Schipper, Jan-David; Schneider, Basil; Schorlemmer, Andre; Schroer, Nicolai; Schwemling, Philippe; Seidel, Sally; Seiden, Abraham; Šícho, Petr; Skubic, Patrick; Sloboda, Michal; Smith, D; Sood, Alex; Spencer, Edwin; Strang, Michael; Stugu, Bjarne; Stupak, John; Su, Dong; Takubo, Yosuke; Tassan, Jean; Teng, Ping-Kun; Terada, Susumu; Todorov, Theodore; Tomášek, Michal; Toms, Konstantin; Travaglini, Riccardo; Trischuk, William; Troncon, Clara; Troska, Georg; Tsiskaridze, Shota; Tsurin, Ilya; Tsybychev, Dmitri; Unno, Yoshinobu; Vacavant, Laurent; Verlaat, Bart; Vianello, Elisa; Vigeolas, Eric; von Kleist, Stephan; Vrba, Václav; Vuillermet, Raphaël; Wang, Rui; Watts, Stephen; Weber, Michele; Weber, Marteen; Weigell, Philipp; Weingarten, Jens; Welch, Steven David; Wenig, Siegfried; Wermes, Norbert; Wiese, Andreas; Wittig, Tobias; Yildizkaya, Tamer; Zeitnitz, Christian; Ziolkowski, Michal; Zivkovic, Vladimir; Zoccoli, Antonio; Zorzi, Nicola; Zwalinski, Lukasz

    2012-01-01

    The ATLAS Collaboration will upgrade its semiconductor pixel tracking detector with a new Insertable B-layer (IBL) between the existing pixel detector and the vacuum pipe of the Large Hadron Collider. The extreme operating conditions at this location have necessitated the development of new radiation hard pixel sensor technologies and a new front-end readout chip, called the FE-I4. Planar pixel sensors and 3D pixel sensors have been investigated to equip this new pixel layer, and prototype modules using the FE-I4A have been fabricated and characterized using 120 GeV pions at the CERN SPS and 4 GeV positrons at DESY, before and after module irradiation. Beam test results are presented, including charge collection efficiency, tracking efficiency and charge sharing.

  20. JACoW Design of the front-end detector control system of the ATLAS New Small Wheels

    CERN Document Server

    Moschovakos, Paris

    2018-01-01

    The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW) [1], which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the Gigabit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department [2,3], which will be used at the NSW upgrade. The SCA offers several interfaces to read analogue and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. The design of the NSW Detector Control System (DCS) takes advantage of this functionality, as described in this paper.

  1. Fatalic, a very-front-end Asic for the ATLAS Tile Calorimeter

    CERN Document Server

    Manen, Samuel Pierre; The ATLAS collaboration

    2016-01-01

    Abstract—The ATLAS Collaboration has started a vast program of upgrades in the context of high-luminosity LHC (HLLHC) forseen in 2024. The current readout electronics of every subdetector, including the Tile Calorimeter (TileCal), must be upgraded to comply with the new specifications aiming for the future operating conditions. The ASIC described in this document, named Front-end ATlAs tiLe Integrated Circuit (FATALIC), has been developed to fulfil the requirements of the TileCal upgrade. FATALIC is based on a 130 nm CMOS technology and performs the complete processing of the signal, including amplification, shaping and digitization. The first stage is a current conveyor which splits the input signal into three ranges, allowing to deal with a large dynamic range (from 25 fC up to 1.2 nC). Each current conveyor output is followed by a shaper and a dedicated pipeline 12 bit ADC operating at 40 MHz. Measurements show a non-linearity at the percent level for a typical input charge of interest. The noise of the ...

  2. Radiation induced Single Event Effects in the ATLAS MDT-ASD front-end chip

    CERN Document Server

    Posch, C

    2002-01-01

    Single Event Effect (SEE) tests of the MDT-ASD, the ATLAS MDT front-end chip have been performed at the Harvard Cyclotron Lab. The MDT-ASD is an 8-channel drift tube read-out ASIC fabricated in a commercial 0.5um CMOS process (AMOS14TB). The chip contains a 53 bit register which holds the setup information and an associated shift register of the same length plus some additional control logic. 10 test devices were exposed to a 160 MeV proton beam with a fluence of 1.05E9 p.cm-2.s-1 up to >4.4E p.cm-2 per device. After a total fluence of 4.46E13 p.cm-2, 7 soft SEEs (non-permanent bit flips in the registers) and 0 hard/destructive SEE (e.g. latch-ups, SEL) had occurred. The simulated fluence for 10 years of LHC operation at nominal luminosity for worst case location MDT components is 2.67E11 h.cm-2. The rate of SEUs in the ASD setup register for all of ATLAS, derived from these numbers, is 2.4 per day. It is foreseen to update the active registers of the on-detector electronics at regular intervals. Depending on...

  3. Instrumentation of the upgraded ATLAS tracker with a double buffer front-end architecture for track triggering

    International Nuclear Information System (INIS)

    Wardrope, D

    2012-01-01

    The Large Hadron Collider will be upgraded to provide instantaneous luminosity L = 5 × 10 34 cm −2 s −1 , leading to excessive rates from the ATLAS Level-1 trigger. A double buffer front-end architecture for the ATLAS tracker replacement is proposed, that will enable the use of track information in trigger decisions within 20 μs in order to reduce the high trigger rates. Analysis of ATLAS simulations have found that using track information will enable the use of single lepton triggers with transverse momentum thresholds of p T ∼ 25 GeV, which will be of great benefit to the future physics programme of ATLAS.

  4. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the Atlas Tile Calorimeter

    CERN Document Server

    Drake, G; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Mellado, B; Proudfoot, J

    2012-01-01

    –We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. This may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present conclusions for improvements to the power distribution system for the LHC Phase 2 upgrade.

  5. Reliability Analysis of a Low Voltage Power Supply Design for the Front-End Electronics of the ATLAS Tile Calorimeter

    CERN Document Server

    Senthilkumaran, A; The ATLAS collaboration; Gopalakrishnan, A; Mahadik, S; Drake, G; Proudfoot, J

    2012-01-01

    We present a reliability study on a new low voltage power supply design for the front-end electronics of the ATLAS Tile Calorimeter. Using the reliability data from the manufacturers of the components, we derive an estimate of the expected number of failures per year during the normal operating lifetime of the power supply bricks. We will illustrate the technique, which may be useful for other power supply designs or front-end electronics designs where high reliability is required. We discuss the factors in the design that limit reliability, and present our preliminary design work for improvements in the power distribution system for the LHC Phase 2 upgrade.

  6. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

  7. Analog lightwave links for detector front-ends at the LHC

    International Nuclear Information System (INIS)

    Baird, A.; Dowell, J.; Duthie, P.

    1995-01-01

    Lightwave links are being developed for volume application in the transfer of analog signals from the tracking detector front-ends to the readout electronics. The links are based on electro-optic intensity modulators which are mounted on detectors and connected by optical fibers to remotely located transceivers (lasers and photoreceivers). The modulators are 3--5 semiconductor reflective devices based on multi-quantum well structures. The transceivers will be integrated devices of a novel design. Modulator prototypes have been fabricated and tested. Neutron and γ-ray irradiation studies have been performed on modulators and fibers. The main results achieved so far are reported and key system issues are reviewed. This work is part of the CERN DRDC project RD23 project RD23

  8. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents produced by the FE-I4 front-end chip was observed and this increase was traced back to the radiation damage in the chip. The dependence of the current on the total-ionising dose and temperature has been tested with Xray and proton irradiations and will be presented in this paper together with the detector operation guidelines.

  9. FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

    CERN Document Server

    Chen, Kai; The ATLAS collaboration

    2016-01-01

    The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

  10. Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

    CERN Document Server

    Drake, G; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

  11. Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2012-01-01

    We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

  12. An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  13. An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

    CERN Document Server

    Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

    2011-01-01

    We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

  14. Artificial Neural Network based DC-link Capacitance Estimation in a Diode-bridge Front-end Inverter System

    DEFF Research Database (Denmark)

    Soliman, Hammam Abdelaal Hammam; Abdelsalam, Ibrahim; Wang, Huai

    2017-01-01

    , a proposed software condition monitoring methodology based on Artificial Neural Network (ANN) algorithm is presented. Matlab software is used to train and generate the proposed ANN. The proposed methodology estimates the capacitance of the DC-link capacitor in a three phase front-end diode bridge AC...

  15. Irradiation induced effects in the FE-I4 front-end chip of the ATLAS IBL detector

    CERN Document Server

    La Rosa, Alessandro; The ATLAS collaboration

    2016-01-01

    The ATLAS Insertable B-Layer (IBL) detector was installed into the ATLAS experiment in 2014 and has been in operation since 2015. During the first year of IBL data taking an increase of the low voltage currents associated with the FE-I4 During the first year of the IBL operation in 2015 a significant increase of the LV current of the front-end chip and the detuning of its parameters (threshold and time-over- threshold) have been observed in relation to the received TID. In this talk , the TID effects in the FE-I4 chip are reported based on studies performed in the laboratory using X-ray and proton irradiation sources for various temperature and irradiation intensity conditions. Based on these results, an operation guideline of the IBL detector is presented.

  16. A Front-End Electronics Prototype Based on Gigabit Ethernet for the ATLAS Small-Strip Thin Gap Chamber

    Science.gov (United States)

    Hu, Kun; Lu, Houbing; Wang, Xu; Li, Feng; Wang, Xinxin; Geng, Tianru; Yang, Hang; Liu, Shengquan; Han, Liang; Jin, Ge

    2017-06-01

    A front-end electronics prototype for the ATLAS small-strip Thin Gap Chamber (sTGC) based on gigabit Ethernet has been developed. The prototype is designed to read out signals of pads, wires, and strips of the sTGC detector. The prototype includes two VMM2 chips developed to read out the signals of the sTGC, a Xilinx Kintex-7 field-programmable gate array (FPGA) used for the VMM2 configuration and the events storage, and a gigabit Ethernet transceiver PHY chip for interfacing with a computer. The VMM2 chip is designed for the readout of the Micromegas detector and sTGC detector, which is composed of 64 linear front-end channels. Each channel integrates a charge-sensitive amplifier, a shaper, several analog-to-digital converters, and other digital functions. For a bunch-crossing interval of 25 ns, events are continuously read out by the FPGA and forwarded to the computer. The interface between the computer and the prototype has been measured to reach an error-free rate of 900 Mb/s, therefore making a very effective use of the available bandwidth. Additionally, the computer can control several prototypes of this kind simultaneously via the Ethernet interface. At present, the prototype will be used for the sTGC performance test. The features of the prototype are described in detail.

  17. Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

    CERN Document Server

    Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

    2013-01-01

    The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

  18. Prototype ATLAS IBL modules using the FE-I4A front-end readout chip

    Czech Academy of Sciences Publication Activity Database

    Albert, J.; Alex, M.; Alimonti, G.; Hejtmánek, Martin; Janoška, Zdenko; Korchak, Oleksandr; Popule, Jiří; Šícho, Petr; Sloboda, Michal; Tomášek, Michal; Vrba, Václav

    2012-01-01

    Roč. 7, NOV (2012), 1-45 ISSN 1748-0221 R&D Projects: GA MŠk LA08032 Institutional research plan: CEZ:AV0Z10100502 Keywords : ATLAS * upgrade * tracker * silicon * FE-I4 * planar sensors * test beam Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.869, year: 2011 http://arxiv.org/abs/arXiv:1209.1906

  19. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

  20. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  1. Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

    CERN Document Server

    Garcia-Argos, Carlos; The ATLAS collaboration

    2017-01-01

    The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

  2. Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

    2002-01-01

    A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

  3. The Development of High-Performance Front-End Electronics Based Upon the QIE12 Custom ASIC for the ATLAS TileCal Upgrade

    CERN Document Server

    Drake, Gary; The ATLAS collaboration

    2016-01-01

    We present the design of a new candidate front-end electronic readout system being developed for the ATLAS TileCal Phase 2 Upgrade. The system is based upon the QIE12 custom Application Specific Integrated Circuit. The chip features a least count sensitivity of 1.5 fC, more than 17 bits of dynamic range with logarithmic response, and an on-chip TDC with one nanosecond resolution. The design incorporates an on-board current integrator, and has several calibration systems. The new electronics will operate dead-timelessly at 40 MHz, pushing full data sets from each beam crossing to the data acquisition system that resides off-detector in the USA15 counting room using high-speed optical links. The system is one of three candidate systems for the Phase 2 Upgrade. We have built a “Demonstrator” – a fully functional prototype of the new system. Performance results from bench measurements and from a recent test beam campaign will be presented.

  4. Total Ionization Dose effects in the FE-I4 front-end chip of the ATLAS Pixel IBL detector

    CERN Document Server

    ATLAS Pixel Collaboration; The ATLAS collaboration

    2016-01-01

    During the first year of operation, a drift of the IBL calibration parameters (Threshold and ToT) and a low voltage current increase was observed. It was assumed that both observations were related to radiation damage effects depending on the Total Ionizing Dose (TID) in the NMOS transistors of which each Front End chip holds around 80 million. The effect of radiation on those transistors was investigated in lab measurements and the results will be presented in this talk.

  5. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    CERN Document Server

    Senkin, Sergey; The ATLAS collaboration

    2017-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the front-end readout options, an ASIC called FATALIC, which is proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. Hereby we describe the full characterisation of FATALIC and also the signal reconstruction up to the observables of interest for physics: the energy and the arrival time of the particle. The Optimal Filtering signal reconstruction method is adapted to fully exploit the FATALIC three-range layout. Additionally, we present the performance in terms of resolution of the whole chain measured using the charge injection system designed for calibration. Finally, the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN are discussed.

  6. Charge Pump Clock Generation PLL for the Data Output Block of the Upgraded ATLAS Pixel Front-End in 130 nm CMOS

    CERN Document Server

    Kruth, A; Arutinov, D; Barbero, M; Gronewald, M; Hemperek, T; Karagounis, M; Krueger, H; Wermes, N; Fougeron, D; Menouni, M; Beccherle, R; Dube, S; Ellege, D; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gromov, V; Kluit, R; Schipper, J

    2009-01-01

    FE-I4 is the 130 nm ATLAS pixel IC currently under development for upgraded Large Hadron Collider (LHC) luminosities. FE-I4 is based on a low-power analog pixel array and digital architecture concepts tuned to higher hit rates [1]. An integrated Phase Locked Loop (PLL) has been developed that locally generates a clock signal for the 160 Mbit/s output data stream from the 40 MHz bunch crossing reference clock. This block is designed for low power, low area consumption and recovers quickly from loss of lock related to single-event transients in the high radiation environment of the ATLAS pixel detector. After a general introduction to the new FE-I4 pixel front-end chip, this work focuses on the FE-I4 output blocks and on a first PLL prototype test chip submitted in early 2009. The PLL is nominally operated from a 1.2V supply and consumes 3.84mW of DC power. Under nominal operating conditions, the control voltage settles to within 2% of its nominal value in less than 700 ns. The nominal operating frequency for t...

  7. Improved Control of an Active-Front-End Adjustable Speed Drive with a Small dc-link Capacitor under Real Grid Conditions

    DEFF Research Database (Denmark)

    Klumpner, Christian; Liserre, Marco; Blaabjerg, Frede

    2004-01-01

    Active front-end topologies will be widely used in the future and among them especially the two-level PWM rectifier, due to the need to improve the quality of the input currents and the robustness against grid disturbances of Adjustable Speed Drives (ASDs). Another expectation is that electrolytic...... capacitors will be replaced by film capacitors in order to increase the ASD lifetime, but as this has lower energy density, the dc-link capacitance is expected to decrease. In these circumstances, operation under unbalanced and distorted supply voltage as well as high dynamic operation of the ASD makes...

  8. FE-I2 a front-end readout chip designed in a commercial 025- mu m process for the ATLAS pixel detector at LHC

    CERN Document Server

    Blanquart, L; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I

    2004-01-01

    A new front-end chip (FE-I2) has been developed for the ATLAS pixel detector at the future Large Hadron Collider (LHC) accelerator facility of the European Laboratory for Particle Physics (CERN). This chip has been submitted in a commercial 0.25- mu m CMOS process using special layout techniques for radiation tolerance. It comprises 2880 pixels arranged into 18 columns of 160 channels. Each pixel element of dimension 50 mu m * 400 mu m is composed of a charge- sensitive amplifier followed by a fast discriminator with a detection threshold adjustable within a range of 0-6000 electrons and slow control logic incorporating a wired-hit-Or, preamplifier-kill, readout mask, and automatic threshold tuning circuitry. There are two single-event- upset (SEU)-tolerant DACs for reducing threshold (7-b) and recovery- time (3-b) mismatches from pixel to pixel along with digital hit emulation and a differential readout circuit aimed at transporting time-stamped data from each pixel to buffers at the bottom of the chip. In c...

  9. Front-end conceptual platform modeling

    DEFF Research Database (Denmark)

    Guðlaugsson, Tómas Vignir; Ravn, Poul Martin; Mortensen, Niels Henrik

    2014-01-01

    Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development. This con......Platform thinking has been the subject of investigation and deployment in many projects in both academia and industry. Most contributions involve the restructuring of product programs, and only a few support front-end development of a new platform in parallel with technology development....... The conclusion is that the Conceptual Product Platform model supports stakeholders in achieving an overview of the development tasks and communicating these across multidisciplinary development teams, as well as making decisions on the contents of the platform and providing a link between technical solutions...

  10. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Science.gov (United States)

    Senkin, Sergey

    2018-01-01

    The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC) foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  11. A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

    Directory of Open Access Journals (Sweden)

    Senkin Sergey

    2018-01-01

    Full Text Available The ATLAS Collaboration has started a vast programme of upgrades in the context of high-luminosity LHC (HL-LHC foreseen in 2024. We present here one of the frontend readout options, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on a 130 nm CMOS technology, FATALIC performs the complete signal processing, including amplification, shaping and digitisation. We describe the full characterisation of FATALIC and also the Optimal Filtering signal reconstruction method adapted to fully exploit the FATALIC three-range layout. Additionally we present the resolution performance of the whole chain measured using the charge injection system designed for calibration. Finally we discuss the results of the signal reconstruction used on real data collected during a preliminary beam test at CERN.

  12. Adaptive RF front-ends for hand-held applications

    CERN Document Server

    van Bezooijen, Andre; van Roermund, Arthur

    2010-01-01

    The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

  13. The LHCb Outer Tracker Front End Electronics

    CERN Document Server

    Berkien, A; Hommels, B; Knopf, J; Nedos, M; Pellegrino, A; Sluijk, T; Spelt, J; Stange, U; Trunk, U; Uwer, U; Wiedner, D; Zwart, A

    2008-01-01

    This note provides an overview of the front-end electronics used to readout the drift-times of the LHCb Outer Tracker straw tube chambers. The main functional components of the readout are the ASDBLR ASIC for amplification and signal digitization, the OTIS ASIC for the time measurement and for the L0 buffering, and the GOL ASIC to serialize the digital data for the optical data transmission. The L1 buffer board used to receive the data which is sent via the optical link is a common LHCb development and is not described here. This note supersedes an earlier document [1].

  14. Supporting radical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth; Gertsen, Frank

    2011-01-01

    An organization benefits substantially by improving front end innovation (FEI) actively and may thereby enhance the chances of developing innovations, as emphasized by several authors e.g. Reinertsen (1999), Dahl & Moreau (2002), Boeddrich (2004), Williams et al. (2007) and Vernorn et al. (2008......). Pharmaceutical innovation is unique, as it opposed to most other industries’ product development is science-driven and not customer-driven. In addition, the pharmaceutical FEI, as represented by research, lasts up to 5 years and the entire R&D process constitutes a period of 10-12 years, which is highly...... regulated by external authorities, e.g. The American Food and Drug Administration (FDA). The research aim of this paper is: to contribute to the field of FEI by studying how FEI can be actively supported within the industry specific context of the pharmaceutical industry, and through a conceptual discussion...

  15. Muon front end for the neutrino factory

    Directory of Open Access Journals (Sweden)

    C. T. Rogers

    2013-04-01

    Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

  16. The CMS Tracker Readout Front End Driver

    CERN Document Server

    Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

    2004-01-01

    The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

  17. SPD very front end electronics

    International Nuclear Information System (INIS)

    Luengo, S.; Gascon, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasis, X.

    2006-01-01

    The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

  18. End-Users, Front Ends and Librarians.

    Science.gov (United States)

    Bourne, Donna E.

    1989-01-01

    The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

  19. RPC performance vs. front-end electronics

    International Nuclear Information System (INIS)

    Cardarelli, R.; Aielli, G.; Camarri, P.; Di Ciaccio, A.; Di Stante, L.; Liberti, B.; Pastori, E.; Santonico, R.; Zerbini, A.

    2012-01-01

    Moving the amplification from the gas to the front-end electronics was a milestone in the development of Resistive Plate Chambers. Here we discuss the historical evolution of RPCs and we show the results obtained with newly developed front-end electronics with threshold in the fC range.

  20. The front end of the fuel cycle

    International Nuclear Information System (INIS)

    Cohen, K.P.

    1985-01-01

    The purpose of this paper is to examine the front end of the fuel cycle as it relates to nuclear power and proliferation, with the ultimate purpose of recommending policies that foster widespread use of nuclear power without contributing to the risk of proliferation of nuclear weapons. Reactor design and construction, the production of reactor materials such as D/sub 2/O and zirconium, uranium mining, and uranium enrichment--all are characteristic front end activities. To keep the scope manageable, the first and fourth topics are the focus. There is, of course, no clear distinction between the front end and the back end of the fuel cycle, since the back of one fuel cycle can well be the front end of another. Even when fuel is not recycled, the choice of the front end often depends on the products one desires from the back end

  1. Front end readout electronics for the CMS hadron calorimeter

    CERN Document Server

    Shaw, Terri M

    2002-01-01

    The front-end electronics for the CMS Hadron Calorimeter provides digitized data at the beam interaction rate of 40 MHz. Analog signals provided by hybrid photodiodes (HPDs) or photomultiplier tubes (PMTs) are digitized and the data is sent off board through serialized fiber optic links running at 1600 Mbps. In order to maximize the input signal, the front-end electronics are housed on the detector in close proximity to the scintillating fibers or phototubes. To fit the electronics into available space, custom crates, backplanes and cooling methods have had to be developed. During the expected ten-year lifetime, the front-end readout electronics will exist in an environment where radiation levels approach 330 rads and the neutron fluence will be 1.3E11 n/cm sup 2. For this reason, the design approach relies heavily upon custom radiation tolerant ASICs. This paper will present the system architecture of the front-end readout crates and describe their results with early prototypes.

  2. THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

    DEFF Research Database (Denmark)

    Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

    2018-01-01

    This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...... as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players....

  3. RF front-end world class designs

    CERN Document Server

    Love, Janine

    2009-01-01

    All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

  4. The control system for the CMS tracker front-end

    CERN Document Server

    Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

    2002-01-01

    The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

  5. Dispersion management of the SULF front end

    Science.gov (United States)

    Li, Shuai; Wang, Cheng; Liu, Yanqi; Xu, Yi; Liu, Zhengzheng; Lu, Jun; Li, Yanyan; Liu, Xingyan; Li, Zhaoyang; Leng, Yuxin; Li, Ruxin

    2017-04-01

    To manage dispersion of the front end in the Shanghai Superintense Ultrafast Laser Facility (SULF), which is a large-scale project aimed at delivering 10 PW laser pulses, a stretcher based on a combination of a grating and a prism (grism) pair is inserted between an Öffner-triplet-type stretcher and a regenerative amplifier to reduce high-order dispersion introduced by optical materials at the amplification stage. The alignment of the grism pair is implemented by controlling the far-field pattern of the output beam of the grism pair. The energy of the front end reaches up to 7 J at a 1-Hz repetition rate. Experimental results show that the pulse duration can be compressed to 22.4 fs and the spectral distortion over the spectrum is less than 2.25 rad.

  6. Managing Controversies in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Christiansen, John K.; Gasparin, Marta

    2016-01-01

    This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

  7. Prototype ALICE front-end card

    CERN Multimedia

    Maximilien Brice

    2004-01-01

    This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

  8. System tests of radiation hard optical links for the ATLAS semiconductor tracker

    International Nuclear Information System (INIS)

    Charlton, D.G.; Dowell, J.D.; Homer, R.J.; Jovanovic, P.; Kenyon, I.R.; Mahout, G.; Shaylor, H.R.; Wilson, J.A.; Rudge, A.; Fopma, J.; Mandic, I.; Nickerson, R.B.; Shield, P.; Wastie, R.; Weidberg, A.R.; Eek, L.-O.; Go, A.; Lund-Jensen, B.; Pearce, M.; Soederqvist, J.; Morrissey, M.; White, D.J.

    2000-01-01

    A prototype optical data and Timing, Trigger and Control transmission system based on LEDs and PIN-diodes has been constructed. The system would be suitable in terms of radiation hardness and radiation length for use in the ATLAS SemiConductor Tracker. Bit error rate measurements were performed for the data links and for the links distributing the Timing, Trigger and Control data from the counting room to the front-end modules. The effects of cross-talk between the emitters and receivers were investigated. The advantages of using Vertical Cavity Surface Emitting Lasers (VCSELs) instead of LEDs are discussed

  9. AFEII Analog Front End Board Design Specifications

    Energy Technology Data Exchange (ETDEWEB)

    Rubinov, Paul; /Fermilab

    2005-04-01

    This document describes the design of the 2nd iteration of the Analog Front End Board (AFEII), which has the function of receiving charge signals from the Central Fiber Tracker (CFT) and providing digital hit pattern and charge amplitude information from those charge signals. This second iteration is intended to address limitations of the current AFE (referred to as AFEI in this document). These limitations become increasingly deleterious to the performance of the Central Fiber Tracker as instantaneous luminosity increases. The limitations are inherent in the design of the key front end chips on the AFEI board (the SVXIIe and the SIFT) and the architecture of the board itself. The key limitations of the AFEI are: (1) SVX saturation; (2) Discriminator to analog readout cross talk; (3) Tick to tick pedestal variation; and (4) Channel to channel pedestal variation. The new version of the AFE board, AFEII, addresses these limitations by use of a new chip, the TriP-t and by architectural changes, while retaining the well understood and desirable features of the AFEI board.

  10. The ALICE TPC front end electronics

    CERN Document Server

    Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

    2004-01-01

    In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

  11. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-μm technology as well as development and realization of a serial power concept

    International Nuclear Information System (INIS)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 μm technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  12. Control and Interlocking System for Bending Magnet Front-end at Indus-2

    Science.gov (United States)

    Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

    2007-01-01

    We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

  13. The PHENIX Drift Chamber Front End Electroncs

    Science.gov (United States)

    Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

    1998-04-01

    The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

  14. Multi-chip module development for the ATLAS pixel detector. Analysis of the front-end chip electronics in radiation hard 0.25-{mu}m technology as well as development and realization of a serial power concept; Multi-Chip-Modul-Entwicklung fuer den ATLAS-Pixeldetektor. Analyse der Front-End-Chip-Elektronik in strahlenharter0,25-{mu}m-Technologie sowie Entwicklung und Realisierung eines Serial-Powering-Konzeptes

    Energy Technology Data Exchange (ETDEWEB)

    Stockmanns, T.

    2004-08-01

    The innermost layer of the ATLAS tracking system is a silicon pixel detector. The use of radiation tolerant components is mandatory due to the harsh radiation environment. The smallest independent component of the pixel detector is a hybride pixel module consisting of a large oxygen enriched silicon sensor and 16 specifically developed ASICs. To achieve the necessary radiation tolerance the ASICs are produced in a 0.25 {mu}m technology in combination with special design techniques. The measurements of the readout electronics during all stages of production of a full module are presented and the performance of the modules is compared with the strict requirements of the ATLAS pixel detector. Furthermore a new powering scheme for pixel detectors is presented, aiming at reducing the total power consumption, the material for the electrical services and the amount of power cables. The advantages and disadvantages of this concept are discussed on the example of the ATLAS pixel detector with pixel modules modified accounting to the new powering scheme. The performance of six of those modules operating at the same time in a small system test is compared to that of normal ATLAS pixel modules. (orig.)

  15. MMIC front-ends for optical communication systems

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad

    1993-01-01

    Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

  16. The front-end electronics for LHCb calorimeters

    CERN Document Server

    Breton, D

    2002-01-01

    For the readout of the calorimeters of the LHCb experiment at CERN, specific front-end electronics have been designed. In particular, three different front-end analog chips were studied respectively for the ECAL/HCAL, preshower and scintillator pad detector. We will present the three front-end electronic chains, point out their specific requirements together with their common purpose, and describe the corresponding ASICs. (6 refs).

  17. Front End Spectroscopy ASIC for Germanium Detectors

    Science.gov (United States)

    Wulf, Eric

    Large-area, tracking, semiconductor detectors with excellent spatial and spectral resolution enable exciting new access to soft (0.2-5 MeV) gamma-ray astrophysics. The improvements from semiconductor tracking detectors come with the burden of high density of strips and/or pixels that require high-density, low-power, spectroscopy quality readout electronics. CMOS ASIC technologies are a natural fit to this requirement and have led to high-quality readout systems for all current semiconducting tracking detectors except for germanium detectors. The Compton Spectrometer and Imager (COSI), formerly NCT, at University of California Berkeley and the Gamma-Ray Imager/Polarimeter for Solar flares (GRIPS) at Goddard Space Flight Center utilize germanium cross-strip detectors and are on the forefront of NASA's Compton telescope research with funded missions of long duration balloon flights. The development of a readout ASIC for germanium detectors would allow COSI to replace their discrete electronics readout and would enable the proposed Gamma-Ray Explorer (GRX) mission utilizing germanium strip-detectors. We propose a 3-year program to develop and test a germanium readout ASIC to TRL 5 and to integrate the ASIC readout onto a COSI detector allowing a TRL 6 demonstration for the following COSI balloon flight. Our group at NRL led a program, sponsored by another government agency, to produce and integrate a cross-strip silicon detector ASIC, designed and fabricated by Dr. De Geronimo at Brookhaven National Laboratory. The ASIC was designed to handle the large (>30 pF) capacitance of three 10 cm^2 detectors daisy-chained together. The front-end preamplifier, selectable inverter, shaping times, and gains make this ASIC compatible with a germanium cross-strip detector as well. We therefore have the opportunity and expertise to leverage the previous investment in the silicon ASIC for a new mission. A germanium strip detector ASIC will also require precise timing of the signals at

  18. Bringing the Fuzzy Front End into Focus

    Energy Technology Data Exchange (ETDEWEB)

    Beck, D.F.; Boyack, K.W.; Bray, O.H.; Siemens, W.D.

    1999-03-03

    Technology planning is relatively straightforward for well-established research and development (R and D) areas--those areas in which an organization has a history, the competitors are well understood, and the organization clearly knows where it is going with that technology. What we are calling the fuzzy front-end in this paper is that condition in which these factors are not well understood--such as for new corporate thrusts or emerging areas where the applications are embryonic. While strategic business planning exercises are generally good at identifying technology areas that are key to future success, they often lack substance in answering questions like: (1) Where are we now with respect to these key technologies? ... with respect to our competitors? (2) Where do we want or need to be? ... by when? (3) What is the best way to get there? In response to its own needs in answering such questions, Sandia National Laboratories is developing and implementing several planning tools. These tools include knowledge mapping (or visualization), PROSPERITY GAMES and technology roadmapping--all three of which are the subject of this paper. Knowledge mapping utilizes computer-based tools to help answer Question 1 by graphically representing the knowledge landscape that we populate as compared with other corporate and government entities. The knowledge landscape explored in this way can be based on any one of a number of information sets such as citation or patent databases. PROSPERITY GAMES are high-level interactive simulations, similar to seminar war games, which help address Question 2 by allowing us to explore consequences of various optional goals and strategies with all of the relevant stakeholders in a risk-free environment. Technology roadmapping is a strategic planning process that helps answer Question 3 by collaboratively identifying product and process performance targets and obstacles, and the technology alternatives available to reach those targets.

  19. The "fuzzy front end" of product development: An exploratory study

    OpenAIRE

    Verworn, Birgit

    2002-01-01

    The aim of this paper is to describe front-end activities in practice and get first hints for effects of the front end on project outcome and the meaning of contextual factors. The results of an exploratory study of fourteen product development projects are contrary to the wide-spread opinion that the quality of execution of front-end activities in practice is low. Although, due to the small sample size, our findings are limited, there seems to be an indirect impact of the fuzzy front end ...

  20. UWB front-end for SAR-based imaging system

    NARCIS (Netherlands)

    Monni, S.; Grooters, R.; Neto, A.; Nennie, F.A.

    2010-01-01

    A planarly fed UWB leaky lens antenna is presented integrated with wide band transmit and receive front-end electronics, to be used in a SAR-based imaging system. The unique non-dispersive characteristics of this antenna over a very wide bandwidth, together with the dual band front-end electronics

  1. Cost of pedestrian and bicycle accidents involving car front ends.

    NARCIS (Netherlands)

    Kampen, L.T.B. van & Huijbers, J.J.W.

    1995-01-01

    A cost study has been carried out, based on Dutch insurance data of payments to victims (pedestrians and cyclists) of collisions against car front ends. The results of this study will be used for a cost-benefit analysis of a proposed amendment (a series of car front end crash tests) to the existing

  2. Idea management in support of pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    , which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...... is applied in facilitation of front end innovation in practice. In order for a pharmaceutical company to support FEI, I present propositions of effective facilitation of pharmaceutical FEI and idea management....

  3. Design of analog front-ends for the RD53 demonstrator chip

    CERN Document Server

    Gaioni, L; Nodari, B; Manghisoni, M; Re, V; Traversi, G; Barbero, M B; Fougeron, D; Gensolen, F; Godiot, S; Menouni, M; Pangaud, P; Rozanov, A; Wang, A; Bomben, M; Calderini, G; Crescioli, F; Le Dortz, O; Marchiori, G; Dzahini, D; Rarbi, F E; Gaglione, R; Gonella, L; Hemperek, T; Huegging, F; Karagounis, M; Kishishita, T; Krueger, H; Rymaszewski, P; Wermes, N; Ciciriello, F; Corsi, F; Marzocca, C; De Robertis, G; Loddo, F; Licciulli, F; Andreazza, A; Liberali, V; Shojaii, S; Stabile, A; Bagatin, M; Bisello, D; Mattiazzo, S; Ding, L; Gerardin, S; Giubilato, P; Neviani, A; Paccagnella, A; Vogrig, D; Wyss, J; Bacchetta, N; Della Casa, G; Demaria, N; Mazza, G; Rivetti, A; Da Rocha Rolo, M D; Comotti, D; Ratti, L; Vacchi, C; Beccherle, R; Bellazzini, R; Magazzu, G; Minuti, M; Morsani, F; Palla, F; Poulios, S; Fanucci, L; Rizzi, A; Saponara, S; Androsov, K; Bilei, G M; Menichelli, M; Conti, E; Marconi, S; Passeri, D; Placidi, P; Monteil, E; Pacher, L; Paternò, A; Gajanana, D; Gromov, V; Hessey, N; Kluit, R; Zivkovic, V; Havranek, M; Janoska, Z; Marcisovsky, M; Neue, G; Tomasek, L; Kafka, V; Sicho, P; Vrba, V; Vila, I; Lopez-Morillo, E; Aguirre, M A; Palomo, F R; Muñoz, F; Abbaneo, D; Christiansen, J; Dannheim, D; Dobos, D; Linssen, L; Pernegger, H; Valerio, P; Alipour Tehrani, N; Bell, S; Prydderch, M L; Thomas, S; Christian, D C; Fahim, F; Hoff, J; Lipton, R; Liu, T; Zimmerman, T; Garcia-Sciveres, M; Gnani, D; Mekkaoui, A; Gorelov, I; Hoeferkamp, M; Seidel, S; Toms, K; De Witt, J N; Grillo, A

    2017-01-01

    The RD53 collaboration is developing a large scale pixel front-end chip, which will be a tool to evaluate the performance of 65 nm CMOS technology in view of its application to the readout of the innermost detector layers of ATLAS and CMS at the HL-LHC. Experimental results of the characterization of small prototypes will be discussed in the frame of the design work that is currently leading to the development of the large scale demonstrator chip RD53A to be submitted in early 2017. The paper is focused on the analog processors developed in the framework of the RD53 collaboration, including three time over threshold front-ends, designed by INFN Torino and Pavia, University of Bergamo and LBNL and a zero dead time front-end based on flash ADC designed by a joint collaboration between the Fermilab and INFN. The paper will also discuss the radiation tolerance features of the front-end channels, which were exposed to up to 800 Mrad of total ionizing dose to reproduce the system operation in the actual experiment.

  4. Digital front-end module (DFEM) series; Digital front end module (DFEM) series

    Energy Technology Data Exchange (ETDEWEB)

    NONE

    2000-03-01

    The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

  5. Development of a DMILL radhard multiplexer for the ATLAS Glink optical link and radiation test with a custom Bit ERror Tester

    CERN Document Server

    Dzahini, D

    2001-01-01

    A high speed digital optical data link has been developed for the front-end readout of the ATLAS electromagnetic calorimeter. It is based on a commercial serialiser commonly known as Glink, and a vertical cavity surface emitting laser. To be compatible with the data interface requirements, the Glink must be coupled to a radhard multiplexer that has been designed in DMILL technology to reduce the impact of neutron and gamma radiation on the link performance. This multiplexer features a very severe timing constraints related both to the front-end board output data and the Glink control and input signals. The full link has been successfully neutron and proton radiation tested by means of a custom bit error tester. (7 refs).

  6. Muon capture for the front end of a muon collider

    Energy Technology Data Exchange (ETDEWEB)

    Neuffer, D.; /Fermilab; Yoshikawa, C.; /MUONS Inc., Batavia

    2011-03-01

    We discuss the design of the muon capture front end for a {mu}{sup +}-{mu}{sup -} Collider. In the front end, a proton bunch on a target creates secondary pions that drift into a capture transport channel, decaying into muons. A sequence of rf cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. The muons are then cooled and accelerated to high energy into a storage ring for high-energy high luminosity collisions. Our initial design is based on the somewhat similar front end of the International Design Study (IDS) neutrino factory.

  7. Noise Susceptibility Measurements of Front-End Electronics Systems

    CERN Document Server

    Allongue, B; Blanchot, G; Faccio, F; Fuentes, C; Michelis, S; Orlandi, S; Toro, A

    2008-01-01

    The conducted and radiated noise that is emitted by a power supply constrains the noise performance of the frontend electronics system that it powers. The characterization of the noise susceptibility of the front-end electronics allows setting proper requirements for the back-end power supply in order to achieve the expected system performance. A method to measure the common mode current susceptibility using current probes is presented. The compatibility between power supplies and various front-end systems is explored.

  8. Indico front-end: From spaghetti to lasagna

    CERN Multimedia

    CERN. Geneva

    2017-01-01

    We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

  9. Front-end electronics development for the SSC

    International Nuclear Information System (INIS)

    Levi, M.

    1990-12-01

    This is a status report on electronics development undertaken by the Front-End Electronics Collaboration. The overall goal of the collaboration remains the development by 1992 of complete, architecturally compatible, front end electronic systems for calorimeter, wire drift chamber, and silicon strip readout. We report here a few highlights to give a brief overview of the work underway. Performance requirements and capabilities, selected architectures, circuit designs and test results are presented. 13 refs., 21 figs., 1 tab

  10. Concepts for a Muon Accelerator Front-End

    Energy Technology Data Exchange (ETDEWEB)

    Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

    2017-03-16

    We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

  11. CMOS front-end electronics for radiation sensors

    CERN Document Server

    AUTHOR|(CDS)2071026

    2015-01-01

    This book offers a comprehensive treatment of front-end electronics for radiation detection. It discusses the fundamental principles of signal processing for radiation detectors and describes circuits at the level of functional building blocks, omitting transistor-level implementation. It also covers important system-level topics commonly found in the world of front-end electronics for radiation sensors. The book develops the topics in detail, with a constant focus on practical problems. It also provides real implementation examples that offer insights and stimuli for more experienced engineers already working in the field.

  12. Self-calibrating quadrature mixing front-end for SDR

    CSIR Research Space (South Africa)

    De Witt, JJ

    2008-01-01

    Full Text Available ]. True SDR, however, implies a hardware radio front-end that is able to cope with different carrier frequencies and bandwidth requirements of various communication standards. The quadrature mixing front-end of zero-IF and digital low-IF transceivers... complex baseband message signal m(t) = mI(t) + jmQ(t), with frequency- domain representation M(f), are passed through these filters, the resulting signal, M ′(f), is given by M ′(f) = MI(f)HI,M (f) + jMQ(f)HQ,M (f). (1) After some algebraic...

  13. A new approach to front-­‐end electronics interfacing in the ATLAS experiment

    CERN Document Server

    Borga, Andrea; The ATLAS collaboration; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Ryu, Soo; Zhang, Jinlong; Anderson, John Thomas; Boterenbrood, Hendrik; Chen, Kai; Chen, Hucheng; Drake, Gary; Donszelmann, Mark; Francis, David

    2015-01-01

    For new detector and trigger systems to be installed in the ATLAS experiment after LHC Run 2 a new approach will be followed for front-end electronics interfacing. The FELIX (Front-End Link eXchange) system will interface to links connecting to front-end detector and trigger electronics instead of the RODs (ReadOut Drivers) currently used. FELIX will function as a gateway to a commodity switched network built using standard technology (either Ethernet or Infiniband). In the paper the new approach will be described and results of the demonstrator program currently in progress will be presented.

  14. Business modelling in the fuzzy front end of innovation

    NARCIS (Netherlands)

    Limonard, A.J.P.; Berkers, F.T.H.M.; Niamut, O.A.; Bachet, T.T.; Reuver, M. de

    2011-01-01

    In this paper we address the techno-economic dilemma in the fuzzy front end of R&D consortia: how to bridge the gap between the lack of knowledge on future demand for a technology and the need to make design decisions. The problem in these types of collaborations that the business interests to

  15. PACE3 - front-end chip for the CMS Preshower

    CERN Multimedia

    Aspel, Paul

    2003-01-01

    This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

  16. Calibration method for direct conversion receiver front-ends

    Directory of Open Access Journals (Sweden)

    R. Müller

    2008-05-01

    Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

  17. FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2017-01-01

    study of the Danish pharmaceutical company, H. Lundbeck A/S, and explorative studies of seven European and American pharmaceutical and biotech companies. The study aims to show how companies can apply HR practices in ways that actively supports the development of radical front end innovation. The value...

  18. Managing Front-End Innovation through Idea Markets at Novozymes

    DEFF Research Database (Denmark)

    Lauto, Giancarlo; Valentin, Finn; Hatzack, Frank

    2013-01-01

    Online collaboration is a powerful tool for boosting idea generation in large corporations. However, management may experience an overload of proposals from employees. To improve front-end innovation, the Danish industrial biotech company Novozymes implemented an internal idea competition in whic...

  19. Instrumentation of a Track Trigger with Double Buffer Front-End Architecture

    CERN Document Server

    Wardrope, DR; The ATLAS collaboration

    2012-01-01

    The planned high luminosity upgrade for the LHC (SLHC), will increase the collision rate in the ATLAS detector by approximately a factor 5 beyond the present LHC design goal, while also increasing the number of pile-up collisions in each event by a similar factor. This means that the level-1 trigger must achieve a higher rejection factor in a more difficult environment. We describe a possible design which splits the level-1 trigger into a two-level system, where the first level, using only calorimetry and muon chambers, defines regions of interest in the tracker from which to extract information for a second, refined trigger. The use of a two-buffer front-end architecture will allow a significantly longer decision time to move data off the detector keeping the data bandwidth and buffer sizes moderate. We will describe the implementation of the scheme in the ATLAS tracker front-end electronics and the simulated performance of the system. Results on thresholds, rejection, bandwidth and trigger latency will be s...

  20. 40 CFR 63.492 - Batch front-end process vents-reporting requirements.

    Science.gov (United States)

    2010-07-01

    ... recorded under § 63.491(e)(3) when the batch front-end process vent is diverted away from the control... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reporting... Batch front-end process vents—reporting requirements. (a) The owner or operator of a batch front-end...

  1. FELIX: the new detector readout system for the ATLAS experiment

    CERN Document Server

    Bauer, Kevin Thomas; The ATLAS collaboration

    2017-01-01

    Starting in 2018 during the planned shutdown of the LHC, the ATLAS experiment at CERN will be deploying new optical link technology (GigaBit Transceiver links) connecting the front end electronics. The Front-End LInk eXchange (FELIX) will provide an infrastructure for the new GBT links to connect to the rest of the Trigger and Data Acquisition (TDAQ) system. FELIX is a PC-based system designed to route data and commands to and from the GBT links and a Commercial Off-The Shelf (COTS) network. In this paper, the FELIX system is described and the design of the hardware prototype and core software is presented.

  2. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    International Nuclear Information System (INIS)

    Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

    2016-01-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  3. A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

    2016-11-01

    The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

  4. The Role of Devices in Staging Front End Innovation

    DEFF Research Database (Denmark)

    Clausen, Christian; Yoshinaka, Yutaka

    2009-01-01

    in the innovative process of product development. The sole reliance on formalised models of planning, and rigid Stage-Gate models for product-based innovations in industry is seen to be wanting in this pursuit. What remains unaddressed is the role of models and other devices such as representations of users...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices.......This paper addresses Front End Innovation as an object for the management and staging of innovation processes. We examine the role which devices play in the managing of Front End Innovation, with inspiration from Science and Technology Studies (STS). The paper contributes to a new understanding...

  5. Novel Front-end Electronics for Time Projection Chamber Detectors

    CERN Document Server

    García García, Eduardo José

    This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

  6. Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

    Directory of Open Access Journals (Sweden)

    Carey-Smith Bruce E

    2005-01-01

    Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

  7. Front-end IC design for intravascular ultrasound imaging

    OpenAIRE

    Yamaner, Yalçın Feysel; Yamaner, Yalcin Feysel; Cenkeramaddi, Linga Reddy; Bozkurt, Ayhan

    2008-01-01

    Capacitive micromachined ultrasonic transducers(cMUT) technology is a new trend for intravascular ultrasound (IVUS) imaging. Large bandwidth, high sensitivity and compatibility to CMOS processes makes the cMUT a better choice compared to the conventional piezoelectric transducer. To exploit the merits of cMUT technology, an accurately designed front end circuit is required. The circuit functions as an output pulse driver for the generation of the acoustic signal and buffers the return echo. F...

  8. Exploring the front-end of project management

    OpenAIRE

    Edkins, A. J.; Geraldi, J.; Morris, P.; Smith, A.

    2013-01-01

    This paper is a multi-case study exploratory investigation into the earliest stages of projects and their management. We refer to this throughout the paper as the ‘front-end’. We provide a definition of this phase of the project life cycle and conduct a literature review of the various topics that would suggest themselves to be apposite to the front-end. This includes governance and strategy; requirements and technology; estimating; risk and value; people and learning and development. Followi...

  9. Spike timing precision in the visual front-end

    OpenAIRE

    Borghuis, B.G. (Bart Gerard)

    2003-01-01

    This thesis describes a series of investigations into the reliability of neural responses in the primary visual pathway. The results described in subsequent chapters are primarily based on extracellular recordings from single neurons in anaesthetized cats and area MT of an awake monkey, and computational model analysis. Comparison of spike timing precision in recorded and Poisson-simulated spike trains shows that spike timing in the front-end visual system is considerably more precise than on...

  10. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  11. Front-end data processing the SLD data acquisition system

    International Nuclear Information System (INIS)

    Nielsen, B.S.

    1986-07-01

    The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

  12. Optimized capture section for a muon accelerator front end

    Directory of Open Access Journals (Sweden)

    Hisham Kamal Sayed

    2014-07-01

    Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

  13. Redesigned front end for the upgrade at CHESS

    International Nuclear Information System (INIS)

    Headrick, R.L.; Smolenski, K.W.

    1996-01-01

    We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

  14. Structuring front-end innovation activities throughout strategic product planning

    Directory of Open Access Journals (Sweden)

    Thaisa Rodrigues

    Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

  15. Instrument Front-Ends at Fermilab During Run II

    Energy Technology Data Exchange (ETDEWEB)

    Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

    2011-07-13

    The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

  16. CODA : Compact front-end analog ASIC for silicon detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

  17. Performance of Front-End Readout System for PHENIX RICH

    International Nuclear Information System (INIS)

    Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

    1999-01-01

    A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

  18. Trigger/front end electronics and data collection

    International Nuclear Information System (INIS)

    Ikeda, Hirokazu

    1989-01-01

    The data collection system in the B factory at KEK is planned to have the features that the beam cross intervals will be small (15-30 necs), that the first-step trigger frequency will be 1 kHz, that the frequency of data transfer from the mass storage will be around 10 Hz, and that the data capacity will be 256 kilobyte/sec at most. A possible approach to meet these requirements is to use a trigger system of a pipeline mechanism, a multiple front end system, a high-speed data scanning module and a large-scale processor farm. The trigger system is intended to extract high-speed signals from the detector and to start and control the entire data collection system. The start signals and control signals should synchronize with the beam cross. The front end electronics comprises high-sensitivity analog electronics, including front amplifier, and an analog/digital converter. The data collection system has a tree structure. Its lowest layer comprises a multiple buffered memory. Required data are extracted by the high-speed data scanning module, stored in a memory incorporated in the scanning module, and then transferred to the processor farm. (N.K.)

  19. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  20. High-linearity CMOS RF front-end circuits

    CERN Document Server

    Ding, Yongwang

    2005-01-01

    This monograph presents techniques to improve the performance of linear integrated circuits (IC) in CMOS at high frequencies. Those circuits are primarily used in radio-frequency (RF) front-ends of wireless communication systems, such as low noise amplifiers (LNA) and mixers in a receiver and power amplifiers (PA) in a transmitter. A novel linearization technique is presented. With a small trade-off of gain and power consumption this technique can improve the linearity of the majority of circuits by tens of dB. Particularly, for modern CMOS processes, most of which has device matching better than 1%, the distortion can be compressed by up to 40 dB at the output. A prototype LNA has been fabricated in a 0.25um CMOS process, with a measured +18 dBm IIP3. This technique improves the dynamic range of a receiver RF front-end by 12 dB. A new class of power amplifier (parallel class A&B) is also presented to extend the linear operation range and save the DC power consumption. It has been shown by both simulation...

  1. Underwater fiber-wireless communication with a passive front end

    Science.gov (United States)

    Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

    2017-11-01

    We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

  2. Digital front-end electronics for COMPASS Muon-Wall 1 detector

    International Nuclear Information System (INIS)

    Alekseev, G.D.; Zhuravlev, N.I.; Maggiora, A.

    2005-01-01

    The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

  3. A CMOS self-powered front-end architecture for subcutaneous event-detector devices

    CERN Document Server

    Colomer-Farrarons, Jordi

    2011-01-01

    A CMOS Self-Powered Front-End Architecture for Subcutaneous Event-Detector Devices presents the conception and prototype realization of a Self-Powered architecture for subcutaneous detector devices. The architecture is designed to work as a true/false (event detector) or threshold level alarm of some substances, ions, etc. that are detected through a three-electrodes amperometric BioSensor approach. The device is conceived as a Low-Power subcutaneous implantable application powered by an inductive link, one emitter antenna at the external side of the skin and the receiver antenna under the ski

  4. 40 CFR 63.487 - Batch front-end process vents-reference control technology.

    Science.gov (United States)

    2010-07-01

    ... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... process vent, reduce organic HAP emissions for the batch cycle by 90 weight percent using a control device... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference...

  5. 40 CFR 63.489 - Batch front-end process vents-monitoring equipment.

    Science.gov (United States)

    2010-07-01

    ... operator of a batch front-end process vent or aggregate batch vent stream that uses a control device to... meets the conditions of § 63.490(b)(3). (i) For batch front-end process vents using a control device to... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents...

  6. 40 CFR 63.486 - Batch front-end process vent provisions.

    Science.gov (United States)

    2010-07-01

    ... sources with batch front-end process vents classified as Group 1 shall comply with the reference control... Group 2 batch front-end process vents shall comply with the applicable reference control technology... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vent provisions...

  7. Shielding design for the front end of the CERN SPL.

    Science.gov (United States)

    Magistris, Matteo; Silari, Marco; Vincke, Helmut

    2005-01-01

    CERN is designing a 2.2-GeV Superconducting Proton Linac (SPL) with a beam power of 4 MW, to be used for the production of a neutrino superbeam. The SPL front end will initially accelerate 2 x 10(14) negative hydrogen ions per second up to an energy of 120 MeV. The FLUKA Monte Carlo code was employed for shielding design. The proposed shielding is a combined iron-concrete structure, which also takes into consideration the required RF wave-guide ducts and access labyrinths to the machine. Two beam-loss scenarios were investigated: (1) constant beam loss of 1 Wm(-1) over the whole accelerator length and (2) full beam loss occurring at various locations. A comparison with results based on simplified approaches is also presented.

  8. The hybrid front end PCBs production for the CMS preshower

    CERN Document Server

    Soukoulias, P

    2009-01-01

    The High Energy Physics Detector CMS (Compact Muon Solenoid),installed at the Large Hadron Collider(LHC) at CERN,Geneva,has been built by an International Collaboration;CMS will measure and identify the particles from proton-proton collisions.One of the CMS component is the Preshower sub-detector,comprising 5000 silicon strip sensors connected to Hybrid Front End Boards for the readout.This paper focuses on an in-kind contibution of Greece.This work was carried out by researches,engineers and managers from a medium size Company,Prisma Electronics,located in Alexandropolis and researchers from CERN in Geneva,Demokritos in Athens and the University of Ioannina.The number of pieces fitting the technical specifications was close to 100%.Because of that,in March 2009,Prisma received as recognition a CERN CMS gold award.

  9. Front-end electronics for H.E.P

    International Nuclear Information System (INIS)

    Hrisoho, A.

    1990-07-01

    A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

  10. Evolutionary algorithm for the neutrino factory front end design

    Energy Technology Data Exchange (ETDEWEB)

    Poklonskiy, Alexey A.; /Michigan State U.; Neuffer, David; /Fermilab

    2009-01-01

    The Neutrino Factory is an important tool in the long-term neutrino physics program. Substantial effort is put internationally into designing this facility in order to achieve desired performance within the allotted budget. This accelerator is a secondary beam machine: neutrinos are produced by means of the decay of muons. Muons, in turn, are produced by the decay of pions, produced by hitting the target by a beam of accelerated protons suitable for acceleration. Due to the physics of this process, extra conditioning of the pion beam coming from the target is needed in order to effectively perform subsequent acceleration. The subsystem of the Neutrino Factory that performs this conditioning is called Front End, its main performance characteristic is the number of the produced muons.

  11. FELIX : The new detector readout system for the ATLAS experiment

    CERN Document Server

    Ryu, Soo; The ATLAS collaboration

    2016-01-01

    After the Phase-I upgrade and onward, the Front-End Link eXchange (FELIX) system will be the interface between the data handling system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a router between custom serial links and a commodity switch network which will use standard technologies (Ethernet or Infiniband) to communicate with data collecting and processing components. The system architecture of FELIX will be described and the results of the demonstrator program currently in progress will be presented.

  12. FELIX: The new detector readout system for the ATLAS experiment

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00370160; The ATLAS collaboration

    2017-01-01

    After the Phase-I upgrades (2019) of the ATLAS experiment, the Front-End Link eXchange (FELIX) system will be the interface between the data acquisition system and the detector front-end and trigger electronics. FELIX will function as a router between custom serial links and a commodity switch network using standard technologies (Ethernet or Infiniband) to communicate with commercial data collecting and processing components. The system architecture of FELIX will be described and the status of the firmware implementation and hardware development currently in progress will be presented.

  13. Compact Receiver Front Ends for Submillimeter-Wave Applications

    Science.gov (United States)

    Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

    2012-01-01

    The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

  14. Front-end electronics for the ALICE calorimeters

    Science.gov (United States)

    Wang, Yaping; Ma, Ke; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhongbao; Awes, Terry C.; Wang, Dong

    2010-05-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is ˜7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  15. Front-end Electronics for the ALICE Calorimeters

    Energy Technology Data Exchange (ETDEWEB)

    Aamodt, K. [University of Oslo, Norway; Awes, Terry C [ORNL; Enokizono, Akitomo [Oak Ridge National Laboratory (ORNL); Silvermyr, David O [ORNL; Zhang, Chun [University of Tennessee, Knoxville (UTK) & Oak Ridge National Laboratory (ORNL); Young, Glenn R [ORNL; The, ALICE [Collaboration affiliations

    2010-05-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2 x 2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is {approx}7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  16. Front-end electronics for the ALICE calorimeters

    CERN Document Server

    Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

    2010-01-01

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

  17. Front-end electronics for the ALICE calorimeters

    Energy Technology Data Exchange (ETDEWEB)

    Wang Yaping, E-mail: wangyaping@mail.ccnu.edu.c [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Ma Ke [Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Huazhong University of Science and Technology, Wuhan 430079 (China); Muller, Hans [CERN, PH-AID-DT, 1211 Geneva 23 (Switzerland); Cai Xu; Zhou Daicui; Yin Zhongbao [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China); Awes, Terry C. [Oak Ridge National Laboratory, Oak Ridge, TN 37831 (United States); Wang Dong [Key Laboratory of Quark and Lepton Physics (Huazhong Normal University, CCNU), Ministry of Education, Wuhan 43079 (China); Institute of Particle Physics, Huazhong Normal University, Wuhan 430079 (China)

    2010-05-21

    The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2x2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is {approx}7 per channel with a noise level of 30 MeV at room temperature for a dynamic range of 80 GeV for PHOS, and the fast-OR RMS noise level is about 75 MeV for a dynamic range of 250 GeV for EMCal.

  18. Results of the SNS front end commissioning at Berkeley Lab

    International Nuclear Information System (INIS)

    Ratti, A.; Ayers, J.J.; Doolittle, L.; Greer, J.B.; Keller, R.; Lewis, S.; Lionberger, C.; Monroy, M.; Pruyn, J.; Staples, J.W.; Syversrude, D.; Thomae, R.; Virostek, S.; Aleksandrov, A.; Shea, T.; SNS Accelerator Physics Group; SNS Beam Diagnostics Collaboration

    2002-01-01

    The Front-End Systems (FES) for the Spallation Neutron Source (SNS) project comprise an rf-driven H - ion source, an electrostatic 2-lens LEBT, a 2.5 MeV RFQ, followed by a 14-quadrupole, 4-rebuncher MEBT including traveling-wave fast choppers. The nominal 2.5 MeV H - beam has a current of 38 mA at a repetition rate of 60 Hz and 1 ms pulse length, for a macro duty-factor of 6%, and is chopped at a rate of approximately 1 MHz with a mini duty-factor of 68%. The normalized rms beam emittance at the MEBT exit, matching the first tank of a 402.5 MHz Alvarez linac, is measured to be approximately 0.3 π mm mrad. Diagnostic elements include wire scanners, BPMs, fast current monitors, a slit-harp emittance device and RFQ field monitoring probes. The results of the beam commissioning and the operation of the RFQ and diagnostic instrumentation are reported. The entire FES was shut down at LBNL at the end of May 2002 and will be recommissioned at ORNL prior to installation of the drift-tube linac

  19. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1991-07-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper we illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. We also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. We outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. We also present some of the difficulties encountered in applying these networks. (author) 13 figs., 9 refs

  20. Neural networks in front-end processing and control

    International Nuclear Information System (INIS)

    Lister, J.B.; Schnurrenberger, H.; Staeheli, N.; Stockhammer, N.; Duperrex, P.A.; Moret, J.M.

    1992-01-01

    Research into neural networks has gained a large following in recent years. In spite of the long term timescale of this Artificial Intelligence research, the tools which the community is developing can already find useful applications to real practical problems in experimental research. One of the main advantages of the parallel algorithms being developed in AI is the structural simplicity of the required hardware implementation, and the simple nature of the calculations involved. This makes these techniques ideal for problems in which both speed and data volume reduction are important, the case for most front-end processing tasks. In this paper the authors illustrate the use of a particular neural network known as the Multi-Layer Perceptron as a method for solving several different tasks, all drawn from the field of Tokamak research. The authors also briefly discuss the use of the Multi-Layer Perceptron as a non-linear controller in a feedback loop. The authors outline the type of problem which can be usefully addressed by these techniques, even before the large-scale parallel processing hardware currently under development becomes cheaply available. The authors also present some of the difficulties encountered in applying these networks

  1. AC-coupled front-end for biopotential measurements.

    Science.gov (United States)

    Spinelli, Enrique Mario; Pallàs-Areny, Ramon; Mayosky, Miguel Angel

    2003-03-01

    AC coupling is essential in biopotential measurements. Electrode offset potentials can be several orders of magnitude larger than the amplitudes of the biological signals of interest, thus limiting the admissible gain of a dc-coupled front end to prevent amplifier saturation. A high-gain input stage needs ac input coupling. This can be achieved by series capacitors, but in order to provide a bias path, grounded resistors are usually included, which degrade the common mode rejection ratio (CMRR). This paper proposes a novel balanced input ac-coupling network that provides a bias path without any connection to ground, thus resulting in a high CMRR. The circuit being passive, it does not limit the differential dc input voltage. Furthermore, differential signals are ac coupled, whereas common-mode voltages are dc coupled, thus allowing the closed-loop control of the dc common mode voltage by means of a driven-right-leg circuit. This makes the circuit compatible with common-mode dc shifting strategies intended for single-supply biopotential amplifiers. The proposed circuit allows the implementation of high-gain biopotential amplifiers with a reduced number of parts, thus resulting in low power consumption. An electrocardiogram amplifier built according to the proposed design achieves a CMRR of 123 dB at 50 Hz.

  2. Front-End electronics configuration system for CMS

    CERN Document Server

    Gras, P; Funk, W; Gross, L; Vintache, D

    2001-01-01

    The four LHC experiments at CERN have decided to use a commercial SCADA (Supervisory Control And Data Acquisition) product for the supervision of their DCS (Detector Control System). The selected SCADA, which is therefore used for the CMS DCS, is PVSS II from the company ETM. This SCADA has its own database, which is suitable for storing conventional controls data such as voltages, temperatures and pressures. In addition, calibration data and FE (Front-End) electronics configuration need to be stored. The amount of these data is too large to be stored in the SCADA database [1]. Therefore an external database will be used for managing such data. However, this database should be completely integrated into the SCADA framework, it should be accessible from the SCADA and the SCADA features, e.g. alarming, logging should be benefited from. For prototyping, Oracle 8i was selected as the external database manager. The development of the control system for calibration constants and FE electronics configuration has bee...

  3. Front end design of smartphone-based mobile health

    Science.gov (United States)

    Zhang, Changfan; He, Lingsong; Gao, Zhiqiang; Ling, Cong; Du, Jianhao

    2015-02-01

    Mobile health has been a new trend all over the world with the rapid development of intelligent terminals and mobile internet. It can help patients monitor health in-house and is convenient for doctors to diagnose remotely. Smart-phone-based mobile health has big advantages in cost and data sharing. Front end design of it mainly focuses on two points: one is implementation of medical sensors aimed at measuring kinds of medical signal; another is acquisition of medical signal from sensors to smart phone. In this paper, the above two aspects were both discussed. First, medical sensor implementation was proposed to refer to mature measurement solutions with ECG (electrocardiograph) sensor design taken for example. And integrated chip using can simplify design. Then second, typical data acquisition architecture of smart phones, namely Bluetooth and MIC (microphone)-based architecture, were compared. Bluetooth architecture should be equipped with an acquisition card; MIC design uses sound card of smart phone instead. Smartphone-based virtual instrument app design corresponding to above acquisition architecture was discussed. In experiments, Bluetooth and MIC architecture were used to acquire blood pressure and ECG data respectively. The results showed that Bluetooth design can guarantee high accuracy during the acquisition and transmission process, and MIC design is competitive because of low cost and convenience.

  4. Toward 5G software defined radio receiver front-ends

    CERN Document Server

    Spiridon, Silvian

    2016-01-01

    This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

  5. Front-end electronics and trigger systems - status and challenges

    International Nuclear Information System (INIS)

    Spieler, Helmuth G; Spieler, Helmuth G

    2007-01-01

    The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

  6. Simple Front-End Concept for the Complex Challenges of Multi-Band Communications

    DEFF Research Database (Denmark)

    Buskgaard, Emil Feldborg; Tatomirescu, Alexandru; Barrio, Samantha Caporal Del

    2015-01-01

    This paper proposes a new architecture for mobile phone front-ends that dramatically reduces the complexity of multi-band smart phones. Traditional smart phone front-ends consist of many parallel transmit (Tx) and receive (Rx) chains each dedicated to a single band. The proposed architecture simp...... bands realistic. Current 5G investigations show that the advantages of flexible front-ends will be even bigger as technology moves toward software defined radio. \\end{abstract}...

  7. Fiber laser front end for high energy petawatt laser systems

    International Nuclear Information System (INIS)

    Dawson, J W; Messerly, M J; Phan, H; Mitchell, S; Drobshoff, A; Beach, R J; Siders, C; Lucianetti, A; Crane, J K; Barty, C J

    2006-01-01

    We are developing a fiber laser front end suitable for high energy petawatt laser systems on large glass lasers such as NIF. The front end includes generation of the pulses in a fiber mode-locked oscillator, amplification and pulse cleaning, stretching of the pulses to >3ns, dispersion trimming, timing, fiber transport of the pulses to the main laser bay and amplification of the pulses to an injection energy of 150 (micro)J. We will discuss current status of our work including data from packaged components. Design detail such as how the system addresses pulse contrast, dispersion trimming and pulse width adjustment and impact of B-integral on the pulse amplification will be discussed. A schematic of the fiber laser system we are constructing is shown in figure 1 below. A 40MHz packaged mode-locked fiber oscillator produces ∼1nJ pulses which are phase locked to a 10MHz reference clock. These pulses are down selected to 100kHz and then amplified while still compressed. The amplified compressed pulses are sent through a non-linear polarization rotation based pulse cleaner to remove background amplified spontaneous emission (ASE). The pulses are then stretched by a chirped fiber Bragg grating (CFBG) and then sent through a splitter. The splitter splits the signal into two beams. (From this point we follow only one beam as the other follows an identical path.) The pulses are sent through a pulse tweaker that trims dispersion imbalances between the final large optics compressor and the CFBG. The pulse tweaker also permits the dispersion of the system to be adjusted for the purpose of controlling the final pulse width. Fine scale timing between the two beam lines can also be adjusted in the tweaker. A large mode area photonic crystal single polarization fiber is used to transport the pulses from the master oscillator room to the main laser bay. The pulses are then amplified a two stage fiber amplifier to 150mJ. These pulses are then launched into the main amplifier

  8. Fully Integrated Biopotential Acquisition Analog Front-End IC.

    Science.gov (United States)

    Song, Haryong; Park, Yunjong; Kim, Hyungseup; Ko, Hyoungho

    2015-09-30

    A biopotential acquisition analog front-end (AFE) integrated circuit (IC) is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA) to achieve low input referred noise (IRN) and to block unwanted DC potential signals. A DC servo loop (DSL) is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL) is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL) is designed to enhance the input impedance and common mode rejection ratio (CMRR) without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL) at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M) complementary metal oxide semiconductor (CMOS) process. The core chip size of the AFE without input/output (I/O) pads is 10.5 mm². A fourth-order band-pass filter (BPF) with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  9. Fully Integrated Biopotential Acquisition Analog Front-End IC

    Directory of Open Access Journals (Sweden)

    Haryong Song

    2015-09-01

    Full Text Available A biopotential acquisition analog front-end (AFE integrated circuit (IC is presented. The biopotential AFE includes a capacitively coupled chopper instrumentation amplifier (CCIA to achieve low input referred noise (IRN and to block unwanted DC potential signals. A DC servo loop (DSL is designed to minimize the offset voltage in the chopper amplifier and low frequency respiration artifacts. An AC coupled ripple rejection loop (RRL is employed to reduce ripple due to chopper stabilization. A capacitive impedance boosting loop (CIBL is designed to enhance the input impedance and common mode rejection ratio (CMRR without additional power consumption, even under an external electrode mismatch. The AFE IC consists of two-stage CCIA that include three compensation loops (DSL, RRL, and CIBL at each CCIA stage. The biopotential AFE is fabricated using a 0.18 μm one polysilicon and six metal layers (1P6M complementary metal oxide semiconductor (CMOS process. The core chip size of the AFE without input/output (I/O pads is 10.5 mm2. A fourth-order band-pass filter (BPF with a pass-band in the band-width from 1 Hz to 100 Hz was integrated to attenuate unwanted signal and noise. The overall gain and band-width are reconfigurable by using programmable capacitors. The IRN is measured to be 0.94 μVRMS in the pass band. The maximum amplifying gain of the pass-band was measured as 71.9 dB. The CIBL enhances the CMRR from 57.9 dB to 67 dB at 60 Hz under electrode mismatch conditions.

  10. Realization of Miniaturized Multi-/Wideband Microwave Front-Ends

    Science.gov (United States)

    Al Shamaileh, Khair A.

    The ever-growing demand toward designing microwave front-end components with enhanced access to the radio spectrum (e.g., multi-/wideband functionality) and improved physical features (e.g., miniaturized circuitry, ease and cost of fabrication) is becoming more paramount than ever before. This dissertation proposes new design methodologies, simulations, and experimental validations of passive front-ends (i.e., antennas, couplers, dividers) at microwave frequencies. The presented design concepts optimize both electrical and physical characteristics without degrading the intended performance. The developed designs are essential to the upcoming wireless technologies. The first proposed component is a compact ultra-wideband (UWB) Wilkinson power divider (WPD). The design procedure is accomplished by replacing the uniform transmission lines in each arm of the conventional single-frequency divider with impedance-varying profiles governed by a truncated Fourier series. While such non-uniform transmission lines (NTLs) are obtained through the even-mode analysis, three isolation resistors are optimized in the odd-mode circuit to achieve proper isolation and output ports matching over the frequency range of interest. The proposed design methodology is systematic, and results in single-layered and compact structures. For verification purposes, an equal split WPD is designed, simulated, and measured. The obtained results show that the input and output ports matching as well as the isolation between the output ports are below --10 dB; whereas the transmission parameters vary between --3.2 dB and --5 dB across the 3.1--10.6 GHz band. The designed divider is expected to find applications in UWB antenna diversity, multiple-input-multiple-output (MIMO) schemes, and antenna arrays feeding networks. The second proposed component is a wideband multi-way Bagley power divider (BPD). Wideband functionality is achieved by replacing the single-frequency matching uniform microstrip lines in

  11. FELIX: the detector readout upgrade of the ATLAS experiment

    CERN Document Server

    Ryu, Soo; The ATLAS collaboration

    2015-01-01

    After the Phase-I upgrade and onward, the Front-End Link eXchange(FELIX) system will be the interface between the readout system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a gateway to a commodity switched network which will use standard technologies (Ethernet or Infiniband) to communicate with data collecting and processing components. In this talk the system architecture of FELIX will be described and the testing results of the FELIX demonstrator will be presented

  12. Performance of the front-end electronics of the ANTARES neutrino telescope

    Science.gov (United States)

    Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Assis Jesus, A. C.; Astraatmadja, T.; Aubert, J.-J.; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Cârloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th.; Charvis; Chiarusi, T.; Chon Sen, N.; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; de Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J.-P.; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J.-L.; Gay, P.; Giacomelli, G.; Gómez-González, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernández-Rey, J. J.; Herold, B.; Hößl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le van Suu, A.; Lefèvre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch.; Ostasch, R.; Palioselitis, D.; Păvăla, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J.-P.; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Réthoré, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schöck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zúñiga, J.; ANTARES Collaboration

    2010-10-01

    ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube signals, measure their arrival time, amplitude and shape as well as perform monitoring and calibration tasks. The ARS chip processes the analogue signals from the optical modules and converts information into digital data. All the information is transmitted to shore through further multiplexing electronics and an optical link. This paper describes the performance of the ARS chip; results from the functionality and characterization tests in the laboratory are summarized and the long-term performance in the apparatus is illustrated.

  13. The DIRC front-end electronics chain for BaBar

    CERN Document Server

    Bailly, P; Del Buono, L; Genat, J F; Lebbolo, H; Roos, L; Zhang, B; Beigbeder-Beau, C; Bernier, R; Breton, D; Cacéres, T; Chase, Robert L; Ducorps, A; Hrisoho, A; Imbert, P; Sen, S; Tocut, V; Truong, K; Wormser, G; Zomer, F; Bonneaud, G; Dohou, F; Gastaldi, F; Matricon, P; Renard, C; Thiebaux, C; Vasileiadis, G; Verderi, M; Oxoby, G; Vavra, J; Warner, D; Wilson, R J

    1999-01-01

    The detector of Internally Reflected Cherenkov light (DIRC) of the BaBar detector (SLAC Stanford, USA) measures better than 1 ns the arrival time of Cherenkov photoelectrons, detected in a 11 000 phototubes array and their amplitude spectra. It mainly comprises of 64-channel DIRC Front-End Boards (DFB) equipped with eight full-custom Analog chips performing zero-cross discrimination with 2 mV threshold and pulse shaping, four full-custom Digital TDC chips for timing measurements with 500 ps binning and a readout logic selecting hits in the trigger window, and DIRC Crate Controller cards (DCC) serializing the data collected from up to 16 DFBs onto a 1.2 Gb/s optical link. Extensive test of the pre-production chips have been performed as well as system tests.

  14. The front-end data conversion and readout electronics for the CMS ECAL upgrade

    CERN Document Server

    Mazza, Gianni

    2017-01-01

    The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with 13 bit resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

  15. CMS Tracker Readout Prototype Front-End Driver PCI Mezzanine Card (Mk1) (connector side)

    CERN Multimedia

    J.Coughlan

    1998-01-01

    The tracking system of the CMS detector at the LHC employs Front End Driver (FED) cards to digitise, buffer and sparsify analogue data arriving via optical links from on detector pipeline chips. This paper describes a prototype version of the FED based upon the popular commercial PCI bus Mezzanine Card (PMC) form factor. The FED-PMC consists of an 8 channel, 9 bit ADC, card, providing a 1 MByte data buffer and operating at the LHC design frequency of 40 MHz. The core of the card is a re-programmable FPGA which allows the functionality of the card to be conveniently modified. The card is supplied with a comprehensive library of C routines.The PMC form factor allows the card to be plugged onto a wide variety of processor carrier boards and even directly into PCI based PCs. The flexibility of the FPGA based design permits the card to be used in a variety of ADC based applications.

  16. Upgrade Design of TileCal Front-end Readout Electronics and Radiation Hardness Studies

    CERN Document Server

    Anderson, K; The ATLAS collaboration; Drake, G; Eriksson, D; Muschter, S; Oreglia, M; Pilcher, J; Price, L; Tang, F

    2011-01-01

    The ATLAS Tile Calorimeter (TileCal) is essential for measuring the energy and direction of hadrons and taus produced in LHC collisions. The TileCal consists of "tiles" of plastic scintillator dispersed in a fine-grained steel matrix . Optical fibers from the tiles are sent to ~10,000 photomultiplier tubes (PMT) and associated readout electronics. The TileCal front-end analog readout electronics process the signals from ~10,000 PMTs. Signals from each PMT are shaped with a 7-pole passive LC shaper and split it to two channels amplified by a pair of clamping amplifiers with a gain ratio of 32. Incorporated with two 40Msps 12-bit ADCs, the readout electronics provide a combined dynamic range of 17-bits. With this dynamic range, the readout system is capable of measuring the energy deposition in the calorimeter cells from ~220MeV to 1.3TeV with the least signal-to-noise ratio of greater than 20. The digitized data from each PMT are transmitted off-detector optically, where the data are further processed with ded...

  17. Development of pixel front-end electronics using advanced deep submicron CMOS technologies

    International Nuclear Information System (INIS)

    Havranek, Miroslav

    2014-09-01

    The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

  18. Front-End Electronics in calorimetry: from LHC to ILC

    International Nuclear Information System (INIS)

    De La Taille, Ch.

    2009-09-01

    This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

  19. 40 CFR 63.491 - Batch front-end process vents-recordkeeping requirements.

    Science.gov (United States)

    2010-07-01

    ... combustion device to control halogenated batch front-end process vents or halogenated aggregate batch vent... periods of process or control device operation when monitors are not operating. (f) Aggregate batch vent... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents...

  20. Sustainability in the front-end of innovation at design agencies

    NARCIS (Netherlands)

    Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

    2013-01-01

    In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

  1. Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Jagd, A M

    1992-01-01

    Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...

  2. Ultra-wideband wireless receiver front-end for high-speed indoor applications

    Directory of Open Access Journals (Sweden)

    Zhe-Yang Huang

    2014-12-01

    Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

  3. Programmer's guide to FFE: a fast front-end data-acquisition program

    International Nuclear Information System (INIS)

    Million, D.L.

    1983-05-01

    The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

  4. Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

    DEFF Research Database (Denmark)

    Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

    1994-01-01

    In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

  5. Test results of the front-end system for the Silicon Drift Detectors of ALICE

    CERN Document Server

    Mazza, G; Anelli, G; Martínez, M I; Rotondo, F; Tosello, F; Wheadon, R

    2001-01-01

    The front-end system of the Silicon Drift Detectors (SDDs) of the ALICE experiment is made of two ASICs. The first chip performs the preamplification, temporary analogue storage and analogue-to-digital conversion of the detector signals. The second chip is a digital buffer that allows for a significant reduction of the connection from the front-end module to the outside world. In this paper, the results achieved on the first complete prototype of the front-end system for the SDDs of ALICE are presented.

  6. Optical Links for the ATLAS Pixel Detector

    CERN Document Server

    Gregor, Ingrid-Maria

    In der vorliegenden Dissertation wird eine strahlentolerante optische Datenstrecke mit hoher Datenrate für den Einsatz in dem Hochenergiephysikexperiment Atlas am Lhc Beschleuniger entwickelt. Da die Lhc-Experimente extremen Strahlenbelastungen ausgesetzt sind, müssen die Komponenten spezielle Ansprüche hinsichtlich der Strahlentoleranz erfüllen. Die Qualifikation der einzelnen Bauteile wurde im Rahmen dieser Arbeit durchgeführt. Die zu erwartenden Fluenzen im Atlas Inner Detector für Silizium und Gallium Arsenid (GaAs) wurden berechnet. Siliziumbauteile werden einer Fluenz von bis zu 1.1.1015neq /cm2 in 1 MeV äquivalenten Neutronen ausgesetzt sein, wohingegen GaAs Bauteile bis zu 7.8.1015neq /cm2 ausgesetzt sein werden. Die Strahlentoleranz der einzelnen benötigten Komponenten wie z.B. der Laserdioden sowie der jeweiligen Treiberchips wurde untersucht. Sowohl die Photo- als auch die Laserdioden haben sich als strahlentolerant für die Fluenzen an dem vorgesehenen Radius erwiesen. Aus de...

  7. Optimization of DC-DC Converters for Improved Electromagnetic Compatibility With High Energy Physics Front-End Electronics

    CERN Document Server

    Fuentes, C; Michelis, S; Blanchot, G; Allongue, B; Faccio, F; Orlandi, S; Kayal, M; Pontt, J

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  8. A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2013-01-01

    to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

  9. A digital Front-End and Readout MIcrosystem for calorimetry at LHC

    CERN Multimedia

    2002-01-01

    % RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

  10. Front end designs for the 7-GeV advanced photon source

    International Nuclear Information System (INIS)

    Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

    1992-01-01

    The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

  11. Installation and testing of the 112 boards for the front-end electronics.

    CERN Multimedia

    2006-01-01

    Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

  12. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

  13. Desarrollo de un terminal punto de venta (TPV) : Arquitectura front-end con Angular2

    OpenAIRE

    López Jurado, Francisco Carlos

    2017-01-01

    Desarrollo de la arquitectura front-end para un terminal de punto de venta. Diseño y maquetación de las vistas de la aplicación. Implementación de todas las vistas, utilizando una arquitectura de componentes con Angular2. Definición de los endpoints del back-end que debe utilizar la capa front-end. Definición e implementación de los modelos de la capa front-end, que serán recibidos por la capa back-end como wrappers. Implantación de un plan de pruebas para la capa front-end, haciend...

  14. RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — In this proposal, AlphaSense, Inc. (AI) and the Carnegie Mellon University (CMU) detail the development of RF front end based on MEMS components for miniaturized...

  15. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\

  16. A Contingency Approach on the Impact of Front-End Success on Project Portfolio Success

    OpenAIRE

    Kock, Alexander; Heising, Wilderich; Gemünden, Hans Georg

    2016-01-01

    This is the article as published by PMI The pre-project or ideation phase is often disregarded in project portfolio management. Senior managers put more emphasis on later project stages, and researchers predominantly investigate the front end from a single project perspective. This study investigates how and under which circumstances the performance of the front end affects project portfolio success. Using a sample of 175 firms, we confirm a strong positive re...

  17. Front end embedded microprocessors in the JET computer-based control system, past, present and future

    International Nuclear Information System (INIS)

    Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

    1987-01-01

    A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

  18. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    International Nuclear Information System (INIS)

    Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

    2016-01-01

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  19. A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

    2016-07-11

    Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

  20. Measurement of Design Process Front-End – Radical Innovation Approach

    DEFF Research Database (Denmark)

    Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

    2014-01-01

    The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase of the inn...... is flexible and can also be applied extensively to other purposes than manufacturing companies, like service sector, as well....

  1. The next generation FrontEnd Controller for the Phase 1 Upgrade of the CMS Hadron Calorimeters

    OpenAIRE

    Costanza, Francesco

    2016-01-01

    The ngFEC (next generation FrontEnd Controller) is the system responsible for slow and fast control within the Phase 1 Upgrade of the CMS Hadron Calorimeters. It is based on the FC7, a μ TCA compatible Advanced Mezzanine Card developed at CERN and built around the Xilinx Kintex®-7 FPGA. The ngFEC decodes the 40.0788 MHz LHC clock and the synchronization signals received from the backplane and distributes them to the frontend electronics using a GBT link. The latency of the fast control signal...

  2. Evaluation of the Ride-Through Capability of an Active-Front-End Adjustable Speed Drive under Real Grid Conditions

    DEFF Research Database (Denmark)

    Liserre, Marco; Klumpner, Christian; Blaabjerg, Frede

    2004-01-01

    Better quality of the input currents, unity power factor and regenerative capability are not the only benefits of equipping an Adjustable Speed Drive (ASD) with an active front-end-stage. Controlling the power inflow may enable also the reduction of the dc-link energy storage, which will then lead...... to the replacement of the electrolytic capacitors with film capacitors, which have lower energy density meaning that the volume is similar, but will increase the ASD lifetime. In these circumstances, operation under unbalanced and distorted supply voltage as well as high dynamic operation of the ASD makes...

  3. Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

    International Nuclear Information System (INIS)

    Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

  4. Implementasi Analog Front End Pada Sensor Kapasitif Untuk Pengaturan Kelembaban Menggunakan Mikrokontroller STM32

    Directory of Open Access Journals (Sweden)

    Rendy Setiawan

    2017-01-01

    Full Text Available Sensor kapasitif merupakan jenis sensor yang mengubah stimulus fisik menjadi perubahan kapasitansi. Pada sensor kapasitif, adanya stray capacitance atau kapasitansi parasitik pada sensor dapat menyebabkan kesalahan dalam pengukuran. Dalam aplikasi pengaturan kelembaban, dibutuhkan sistem pengukuran kelembaban dengan kesalahan minimum untuk mendapatkan nilai setting point dengan galat minimum. Maka diperlukan implementasi analog front end yang dapat meminimalisir kesalahan akibat stray capacitance pada sensor kapasitif untuk pengukuran kelembaban relatif. Pada sistem pengukuran sensor kapasitif ini, sensor dieksitasi dengan sinyal AC yang dihasilkan oleh generator sinyal pada frekuensi 10 KHz, kemudian diimplementasikan analog front end untuk mengondisikan sinyal dari sensor. Keluaran dari analog front end dikonversi menjadi sinyal DC menggunakan demodulator sinkron dan filter low pass lalu dikonversi menjadi data digital menggunakan ADC di mikrokontroller STM32. Hasil pengukuran yang didapatkan dengan implementasi analog front end kemudian kemudian gunakan untuk mengatur kelembaban pada sebuah plant growth chamber. Berdasarkan hasil dari pengujian, rangkaian analog front end dapat mengompensasi stray capacitance dengan kesalahan pembacaan nilai kapasitansi maksimal sebesar 4.2% pada kondisi stray capacitance sebesar 236,6pF, 174,3pF dan 115,7pF. Implementasi analog front end pada pengaturan kelembaban menghasilkan galat pada setting point maksimal sebesar 8.8% untuk nilai RH 75% dan 33%.

  5. Demonstration of an RF front-end based on GaN HEMT technology

    Science.gov (United States)

    Ture, Erdin; Musser, Markus; Hülsmann, Axel; Quay, Rüdiger; Ambacher, Oliver

    2017-05-01

    The effectiveness of the developed front-end on blocking the communication link of a commercial drone vehicle has been demonstrated in this work. A jamming approach has been taken in a broadband fashion by using GaN HEMT technology. Equipped with a modulated-signal generator, a broadband power amplifier, and an omni-directional antenna, the proposed system is capable of producing jamming signals in a very wide frequency range between 0.1 - 3 GHz. The maximum RF output power of the amplifier module has been software-limited to 27 dBm (500 mW), complying to the legal spectral regulations of the 2.4 GHz ISM band. In order to test the proof of concept, a real-world scenario has been prepared in which a commercially-available quadcopter UAV is flown in a controlled environment while the jammer system has been placed in a distance of about 10 m from the drone. It has been proven that the drone of interest can be neutralized as soon as it falls within the range of coverage (˜3 m) which endorses the promising potential of the broadband jamming approach.

  6. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

  7. A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

    Science.gov (United States)

    Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

    2017-11-01

    A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

  8. Upgrade to the front-end electronics of the BESIII muon identification system

    International Nuclear Information System (INIS)

    Xi Jianbo; Liang Hao; Xiang Shitao

    2014-01-01

    Resistive Plate Chambers (RPCs) built from a new type of Bakelite developed at Institute of High Energy Physics (IHEP), Chinese Academy of Sciences have been used in the BESIII Muon identification system for several years without linseed oil coating, but characteristic aging performances were observed. To adapt to the RPCs in the aging state, the front-end electronics have been upgraded by enhancing the front-end protection, improving the threshold setting circuit, and separating power supplies of the comparator and the field programmable gate array (FPGA). Improvements in system stability, front-end protection and threshold consistency have been achieved. In this paper, the system upgrade and the test results are described in detail. (authors)

  9. Analog front end circuit design of CSNS beam loss monitor system

    International Nuclear Information System (INIS)

    Xiao Shuai; Guo Xian; Tian Jianmin; Zeng Lei; Xu Taoguang; Fu Shinian

    2013-01-01

    The China Spallation Neutron Source (CSNS) beam loss monitor system uses gas ionization chamber to detect beam losses. The output signals from ionization chamber need to be processed in the analog front end circuit, which has been designed and developed independently. The way of transimpedance amplifier was used to achieve current-voltage (I-V) conversion measurement of signal with low repetition rate, low duty cycle and low amplitude. The analog front end circuit also realized rapid response to the larger beam loss in order to protect the safe operation of the accelerator equipment. The testing results show that the analog front end circuit meets the requirements of beam loss monitor system. (authors)

  10. Report on the value engineering workshop on APS beamline front ends

    International Nuclear Information System (INIS)

    Kuzay, T.

    1993-01-01

    A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

  11. The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

    CERN Document Server

    Cadeddu, S; Lai, A

    2004-01-01

    We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

  12. Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

    Energy Technology Data Exchange (ETDEWEB)

    Brett Carlsen; Emily Tavrides; Erich Schneider

    2010-08-01

    Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

  13. Alternative Muon Front-end for the International Design Study (IDS)

    CERN Document Server

    Alekou, A; Martini, M; Prior, G; Rogers, C; Stratakis, D; Yoshikawa, C; Zisman, M

    2010-01-01

    We discuss alternative designs of the muon capture front end of the Neutrino Factory International Design Study (IDS). In the front end, a proton bunch on a target creates secondary pions that drift into a capture channel, decaying into muons. A sequence of RF cavities forms the resulting muon beams into strings of bunches of differing energies, aligns the bunches to (nearly) equal central energies, and initiates ionization cooling. This design is affected by limitations on accelerating gradients within magnetic fields. The effects of gradient limitations are explored, and mitigation strategies are presented

  14. LHCb calorimeter front-end electronics radiation dose and single event effects

    CERN Document Server

    Beigbeder-Beau, C; Charlet, D; Lefrançois, J; Machefert, F P; Tocut, V; Truong, K D

    2002-01-01

    The LHCb calorimeter front-end electronics will be located above the ECAL / HCAL, i.e. in a region which is not protected from radiations. We present here an estimation of the radiation effect for the electronics and the solutions we investigate to reduce it. Two irradiation tests of the calorimeter front-end shaper have been performed, in June 2001 at the Centre de Proton Thérapie (Orsay) and in December 2001 at GANIL (Caen). The results of the tests clearly show the satisfying resistance of the shaper to SEL.

  15. EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

    International Nuclear Information System (INIS)

    Carlson, R.B.

    1992-01-01

    The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

  16. Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

    International Nuclear Information System (INIS)

    Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

    2013-01-01

    New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

  17. Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

    2015-01-01

    A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not ...... together with a positive-sequence current controller for the front-end rectifier. A gain in the feedforward term can be changed to control the negative-sequence current. Simulation results are presented to verify the theory....

  18. The Optical Links of the ATLAS SemiConductor Tracker

    CERN Document Server

    Abdesselam, A; Apsimon, R; Band, C; Barr, C; Batchelor, L; Bates, R; Bell, P; Bernabeu, J; Bizzell, J; Brenner, R; Brodbeck, T; Bruckman De Renstrom, P; Buttar, C; Carter, J; Charlton, D; Cheplakov, A; Chilingarov, A; Chu, M-L; Colijn, A-P; Dawson, I; Demirkõz, B; de Jong, P; Dervan, P; Dolezal, Z; Dowell, J; Escobar, P; Spencer, E; Ekelöf, T J C; Eklund, L; Ferrere, D; Fraser, T; French, M; French, R; Fuster, J; Gallop, B; García, C; Goodrick, M; Greenall, A; Grillo, A; Grosse-Knetter, J; Hartjes, F; Hessey, N; Hill, J C; Homer, J; Hou, L; Hughes, G; Ikegami, Y; Issever, C; Jackson, J; Jones, M; Jones, T J; Jovanovic, P; Koffeman, E; Kodys, P; Kohriki, T; Lee, S-C; Lester, C; Limper, M; Lindsay, S W; Lozano, M; Macwaters, C; Magrath, C; Mahout, G; Mandic, I; Matheson, J; McMahon, T; Mikulec, B; Muijs, A; Morrissey, M; Nichols, A; Nickerson, R; O'Shea, V; Pagenis, S; Parker, M; Pater, J; Perrin, E; Pernegger, H; Peeters, S; Phillips, P; Postranecky, M; Robinson, D; Robson, A; Rudge, A; Sandaker, H; Sedlak, K; Smith, N A; Stapnes, S; Stugu, B; Teng, P K; Terada, S; Tricoli, A; Tyndel, M; Ujiie, N; Ullán, M; Unno, Y; van der Kraaij, E; Van Vulpen, I; Viehhauser, G; Vossebeld, J H; Warren, M; Wastie, R; Weidberg, A; Wells, P; White, D; Wilson, J

    2007-01-01

    Optical links are used for the readout of the 4088 silicon microstrip modules that make up the SemiConductor Tracker of the ATLAS experiment at the CERN Large Hadron Collider (LHC). The optical link requirements are reviewed, with particular emphasis on the very demanding environment at the LHC. The on-detector components have to operate in high radiation levels for 10 years, with no maintenance, and there are very strict requirements on power consumption, material and space. A novel concept for the packaging of the on-detector optoelectronics has been developed to meet these requirements. The system architecture, including its redundancy features, is explained and the critical on-detector components are described. The results of the extensive Quality Assurance performed during all steps of the assembly are discussed. Optical links are used for the readout of the 4088 silicon microstrip modules that make up the SemiConductor Tracker of the ATLAS experiment at the CERN Large Hadron Collider (LHC). The optical ...

  19. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

    DEFF Research Database (Denmark)

    di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere

    2016-01-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point s...

  20. POLARIS: ESA's airborne ice sounding radar front-end design, performance assessment and first results

    DEFF Research Database (Denmark)

    Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens

    2009-01-01

    B noise figure, 160 ns receiver recovery time and -46 dBc 3rd order IMD products. The system comprises also, a digital front-end, a digital signal generator, a microstrip antenna array and a control unit. All the subsystems were integrated, certified and functionally tested, and in May 2008 a successful...

  1. Magnet Misalignment Studies for the Front-end of the Neutrino Factory

    CERN Document Server

    Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

    2013-01-01

    In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

  2. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...... that can be translated into successful projects....

  3. Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

    Science.gov (United States)

    Spignesi, B.

    This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

  4. Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

    CERN Document Server

    Lo Presti, D; Caponetto, L

    2007-01-01

    A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

  5. Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

    2015-09-16

    The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

  6. Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

    Energy Technology Data Exchange (ETDEWEB)

    Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

    2015-09-01

    This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

  7. The ICARUS Front-end Preamplifier Working at Liquid Argon Temperature

    CERN Document Server

    Baibussinov, B; Casagrande, F; Cennini, P; Centro, S; Curioni, A; Meng, G; Picchi, P; Pietropaolo, F; Rubbia, C; Sergiampietri, F; Ventura, S

    2011-01-01

    We describe characteristics and performance of the low-noise front-end preamplifier used in the ICARUS 50-litre liquid Argon Time Projection Chamber installed in the CERN West Area Neutrino Facility during the 1997-98 neutrino runs. The preamplifiers were designed to work immersed in ultra-pure liquid Argon at a temperature of 87K.

  8. Social Networks in the Front End: The Organizational Life of an Idea

    NARCIS (Netherlands)

    R.C. Kijkuit (Bob)

    2007-01-01

    textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study

  9. Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

    Science.gov (United States)

    Prele, D.

    2015-08-01

    As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

  10. Status on the development of front-end and readout electronics for ...

    Indian Academy of Sciences (India)

    Status on the development of front-end and readout electronics for large silicon trackers. J David M Dhellot J-F Genat F Kapusta H Lebbolo T-H Pham F Rossel A Savoy-Navarro E Deumens P Mallisse D Fougeron R Hermel Y Karyotakis S Vilalte. Tracking and Vertexing Volume 69 Issue 6 December 2007 pp 969-975 ...

  11. Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

    DEFF Research Database (Denmark)

    Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

    2009-01-01

    Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

  12. Structure and thermal analysis of the water cooling mask at NSRL front end

    International Nuclear Information System (INIS)

    Zhao Feiyun; Xu Chaoyin; Wang Qiuping; Wang Naxiu

    2003-01-01

    A water cooling mask is an important part of the front end, usually used for absorbing high power density synchrotron radiation to protect the apparatus from being destroyed by heat load. This paper presents the structure of the water cooling mask and the thermal analysis results of the mask block at NSRL using Program ANSYS5.5

  13. Single-Stage Low-Power Quadrature RF Receiver Front-End: The LMV Cell

    DEFF Research Database (Denmark)

    Liscidini, Antonio; Mazzanti, Andrea; Tonietto, Riccardo

    2006-01-01

    This paper presents the first quadrature RF receiver front-end where, in a single stage, low-noise amplifier (LNA), mixer and voltage-controlled oscillator (VCO) share the same bias current. The new structure exploits the intrinsic mixing functionality of a classical LC-tank oscillator providing ...

  14. Active Feedback Technique for RF Channel Selection in Front-End Receivers

    NARCIS (Netherlands)

    Youssef, S.S.T.; van der Zee, Ronan A.R.; Nauta, Bram

    2012-01-01

    Co-existence problems in a mobile terminal environment pose strict requirements on the linearity of a front-end receiver. In this paper, active feedback is explored as a means to relax such requirements by providing channel selectivity as early as possible in the receiver chain. The proposed

  15. Practices of a "green" front end of innovation; A gateway to environmental innovation

    NARCIS (Netherlands)

    Hassi, L.; Wever, R.

    2010-01-01

    Activities in the fuzzy front end of the innovation process (FFE) are the root of success for any company hoping to compete on the basis of innovations. Considering the importance of the FFE, it would seem logical to bring the environmental considerations already to the activities of the early

  16. Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

    DEFF Research Database (Denmark)

    Song, Zhanfeng; Tian, Yanjun; Chen, Wei

    2016-01-01

    This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...

  17. The fuzziness of the fuzzy front end : the influence of non-technical factors

    NARCIS (Netherlands)

    Kiewiet, Derk Jan; van Engelen, Jo; Achterkamp, Marjolein; Chen, J; Xu, QR; Wu, XB

    2007-01-01

    The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to

  18. Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

    DEFF Research Database (Denmark)

    Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

    2013-01-01

    patterns adopted for product development. Currently, there is not a systematic approach that can be followed for the formulation of PSS proposals in the fuzzy front end. Therefore, the aim of this research is to develop a method for defining PSS project proposals based on attributes that should...

  19. InP DHBT MMICs for millimeter-wave front-ends

    DEFF Research Database (Denmark)

    Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

    2009-01-01

    In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

  20. Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

    Science.gov (United States)

    2016-09-01

    PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION by Chew K. Tan... PHOTONIC ARCHITECTURE FOR DIRECTION FINDING OF LPI EMITTERS: FRONT-END ANALOG CIRCUIT DESIGN AND COMPONENT CHARACTERIZATION 5. FUNDING NUMBERS 6. AUTHOR...miniature microwave- photonic phase-sampling DF technique is investigated in this thesis. This front-end design uses a combination of integrated optical

  1. Parameters-adjustable front-end controller in digital nuclear measurement system

    International Nuclear Information System (INIS)

    Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

    2013-01-01

    Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

  2. An inquiry on managers use of decision-making tools in the core front end of the innovation process

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.

    2013-01-01

    This paper focuses on the Core Front End (CFE) activities of the innovation process to say, Opportunity Identification and Opportunity Analysis. In the CFE of innovation, several tools are used to facilitate and optimise decisions. To select them, managers of the product development team have...... to use several premises to decide which tool is more appropriate to which activity. This paper provides an overview of these mechanisms by looking inside five companies from two different countries. Those mechanisms underline the dimensions influencing the decision process before a specific tool...... is chosen and how those tools impact specific performance metrics. From the analyses and hypotheses testing performed, it clearly emerges that there is no link between being aware of basic requirements (inputs/outputs) to appropriately use a certain tool and dimensions such as tools’ effectiveness...

  3. FELIX - the new detector readout system for the ATLAS experiment

    CERN Document Server

    AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Vermeulen, Jos; Wu, Weihao; Zhang, Jinlong

    2016-01-01

    From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability. Different Front-end data types or different data sources can be routed to different network endpoints that handle that data type or source: e.g. event data, configuration, calibration, detector control, monito...

  4. Status of the Warm Front End of PIP-II Injector Test

    Energy Technology Data Exchange (ETDEWEB)

    Shemyakin, Alexander [Fermilab; Alvarez, Matthew [Fermilab; Andrews, Richard [Fermilab; Baffes, Curtis [Fermilab; Carneiro, Jean-Paul [Fermilab; Chen, Alex [Fermilab; Derwent, Paul [Fermilab; Edelen, Jonathan [Fermilab; Frolov, Daniil [Fermilab; Hanna, Bruce [Fermilab; Prost, Lionel [Fermilab; Saewert, Gregory [Fermilab; Saini, Arun [Fermilab; Scarpine, Victor [Fermilab; Sista, V. Lalitha [Fermilab; Steimel, Jim [Fermilab; Sun, Ding [Fermilab; Warner, Arden [Fermilab

    2017-05-01

    The Proton Improvement Plan II (PIP-II) at Fermilab is a program of upgrades to the injection complex. At its core is the design and construction of a CW-compatible, pulsed H⁻ SRF linac. To validate the concept of the front-end of such machine, a test accelerator known as PIP-II Injector Test is under construction. It includes a 10 mA DC, 30 keV H⁻ ion source, a 2 m-long Low Energy Beam Transport (LEBT), a 2.1 MeV CW RFQ, followed by a Medium Energy Beam Transport (MEBT) that feeds the first of 2 cryomodules increasing the beam energy to about 25 MeV, and a High Energy Beam Transport section (HEBT) that takes the beam to a dump. The ion source, LEBT, RFQ, and initial version of the MEBT have been built, installed, and commissioned. This report presents the overall status of the warm front end.

  5. All-Dielectric Photonic-Assisted Radio Front-End Technology

    Science.gov (United States)

    Ayazi, Hossein Ali

    The threats to civil society posed by high-power electromagnetic weapons are viewed as a grim but real possibility in the world after 11 September 2001. These weapons produce a power surge capable of destroying or damaging sensitive circuitry in electronic systems. Unfortunately, the trend towards circuits with smaller sizes and voltages renders modern electronics highly susceptible to such damage. Radiofrequency communication systems are particularly vulnerable, because the antenna provides a direct port of entry for electromagnetic radiation. In this work, we present a novel type of radiofrequency receiver front end featuring a complete absence of electronic circuitry and metal interconnects, the traditional 'soft spots' of a conventional radiofrequency receiver. The device exploits a dielectric resonator antenna to capture and deliver the radiofrequency signal onto a whispering-gallery mode electro-optic field sensor. The dielectric approach has an added benefit in that it reduces the physical size of the front end, an important benefit in mobile applications.

  6. Commissioning of the SNS front-end systems at Berkeley Lab

    International Nuclear Information System (INIS)

    Keller, R.; Ayers, J.J.; Doolittle, L.; Greer, J.B.; Lewis, S.; Lionberger, C.; Monroy, M.; Pruyn, J.; Ratti, A.; Staples, J.W.; Syversrud, D.; Thomae, R.

    2002-01-01

    Construction of a 2.5-MeV linac injector, the Front-End (FE) for the Spallation Neutron Source (SNS) project, was completed in the spring of 2002. Of the major FE subsystems, the rf-driven H- ion source, the electrostatic LEBT, and the first of four RFQ modules had been commissioned by the spring of 2001, and commissioning of the remaining RFQ modules as well as the full system including the elaborate MEBT was carried out in Jan. through May, 2002. The Front End will be shipped to Oak Ridge, starting in June, 2002, and re-commissioned after installation at the SNS site. This paper gives an overview of FE major design features and experimental results obtained during the commissioning process at LBNL

  7. System front-end design for concurrent acquisition of electroencephalograms and EIT data

    Science.gov (United States)

    Guardo, R.; Jehanne-Lacasse, J.; Moumbe, A. P.; Gagnon, H.

    2010-04-01

    There is recently considerable interest in medical imaging to combine recording of bioelectrical signals with imaging procedures. For example, electroencephalograms (EEGs) recorded during functional magnetic resonance imaging are increasingly being used for neurological and behavioural research. Concurrent acquisition of EEGs and electrical impedance tomography (EIT) data have been suggested as a non invasive technique that could help localize the area of the brain responsible for seizures in epileptic patients awaiting resective surgery. Despite reasonably distinct spectra, EEGs and EIT signals are difficult to record simultaneously because of their very different amplitudes. In this paper, we describe the front-end of a 24-channel system designed to acquire both signals from the same set of scalp electrodes using time-division multiplexing. We have developped a 10-layer 20×15 cm printed circuit board of the front-end and are currently performing circuit characterization tests. System performance parameters and in vivo images will be presented at the conference.

  8. An ASIC implementation of digital front-end electronics for a high resolution PET scanner

    International Nuclear Information System (INIS)

    Newport, D.F.; Young, J.W.

    1993-01-01

    AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

  9. Towards a new perspective of managing ideas in front-end innovation as actor networks

    DEFF Research Database (Denmark)

    Vagn, Anna Rose; Clausen, Christian; Gish, Liv

    2013-01-01

    been identified as front-end innovation processes. The front-end innovation is distinguished from linear product development and characterised as more informal, unstructured, and unpredictable. This paper presents the preliminary results of a PhD project concerning idea management in front......For decades the innovation process in R&D organisations has been discussed. Product development processes is well-established in R&D organisations and improvements has been implemented through theories as Lean product development and agile methods. In recent decades, more diffuse processes have......-end innovation of R&D organisations. Through theoretical and empirical investigations of managing activities of idea processes an indicative analysis in the perspective of actor network theory is performed. The analysis show how managers and employees navigate in a complex environment of organisational...

  10. Complementary bipolar application specific analog semicustom array, intended to implement front-end units

    CERN Document Server

    Atkin, E; Kondratenko, S; Maslennikov, V; Meshcheriakov, V; Mishin, Yu; Volkov, Yu

    2002-01-01

    The structure of an analog semicustom array, intended to implement front-end electronics ICs on its basis, is considered. The features of this array are: implementation with an inexpensive bipolar process despite containing an equal number of NPN and PNP structures with well matched characteristics, supply voltages from 1.5 V to 15 V, transistor current gains Bst~100 and unity gain frequencies Ft > 3 GHz at collector currents of (100...300) mu A, high- and low-ohmic resistors, MOS capacitors, minimum two variable plating levels available. Specific circuit diagrams and parameters of the front-end electronics ICs, created on the basis of the considered array, are presented. The results of their tests are given. (4 refs).

  11. A front-end electronics module for the PHENIX pad chamber

    International Nuclear Information System (INIS)

    Smith, M.C.; Bryan, W.L.; Smith, D.

    1999-01-01

    The Pad Chamber (PC) is part of the Tracking System of the PHENIX detector at the RHIC accelerator of Brookhaven National Laboratory. A front-end electronics module (FEM) has been developed for the PHENIX Pad Chamber. The module's control functions are performed by the heap manager unit, an FPGE-based circuit on the FEM. Each FEM processes signals from 2,160 channels of front-end electronics (FEE). Data readout and formatting are performed by an additional FPGA-based circuit of the FEM. Three external systems provide initialization, timing, and data information via serial interfaces. This paper discusses the application of the heap manager, data formatter, and serial interfaces to meet the specific control and data readout needs of the Pad Chamber subsystem. Unit functions, interfaces, timing, data format, and communication rates will be discussed. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling and FPGA/Implementation and programming will be presented

  12. Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

    International Nuclear Information System (INIS)

    Ericson, M.N.; Allen, M.D.; Boissevain, J.

    1997-11-01

    Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

  13. Mitigating RF Front-End Nonlinearity of Sensor Nodes to Enhance Spectrum Sensing

    Directory of Open Access Journals (Sweden)

    Lin Hu

    2016-11-01

    Full Text Available The cognitive radio wireless sensor network (CR-WSN has gained worldwide attention in recent years for its potential applications. Reliable spectrum sensing is the premise for opportunistic access to sensor nodes. However, as a result of the radio frequency (RF front-end nonlinearity of sensor nodes, distortion products can easily degrade the spectrum sensing performance by causing false alarms and degrading the detection probability. Given the limitations of the widely-used adaptive interference cancellation (AIC algorithm, this paper develops several details to avoid these limitations and form a new mitigation architecture to alleviate nonlinear distortions. To demonstrate the efficiency of the proposed algorithm, verification tests for both simulations and actual RF front-end measurements are presented and discussed. The obtained results show that distortions can be suppressed significantly, thus improving the reliability of spectrum sensing. Moreover, compared to AIC, the proposed algorithm clearly shows better performance, especially at the band edges of the interferer signal.

  14. DSP-based Mitigation of RF Front-end Non-linearity in Cognitive Wideband Receivers

    Science.gov (United States)

    Grimm, Michael; Sharma, Rajesh K.; Hein, Matthias A.; Thomä, Reiner S.

    2012-09-01

    Software defined radios are increasingly used in modern communication systems, especially in cognitive radio. Since this technology has been commercially available, more and more practical deployments are emerging and its challenges and realistic limitations are being revealed. One of the main problems is the RF performance of the front-end over a wide bandwidth. This paper presents an analysis and mitigation of RF impairments in wideband front-ends for software defined radios, focussing on non-linear distortions in the receiver. We discuss the effects of non-linear distortions upon spectrum sensing in cognitive radio and analyse the performance of a typical wideband software-defined receiver. Digital signal processing techniques are used to alleviate non-linear distortions in the baseband signal. A feed-forward mitigation algorithm with an adaptive filter is implemented and applied to real measurement data. The results obtained show that distortions can be suppressed significantly and thus increasing the reliability of spectrum sensing.

  15. Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

    Energy Technology Data Exchange (ETDEWEB)

    Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

    2016-07-01

    This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

  16. Production of the front-end boards of the LHCb muon system

    CERN Document Server

    Bonivento, W; Auriemma, G

    2008-01-01

    This note describes the production of the front end boards CARDIAC, for the 1368 MWPC, and CARDIAC-GEM, for the 12 triple-GEM chambers, of the LHCb muon system. The PCB structure and component layout and the production issues, such as component soldering, quality assurance at the company and delivery rates, are described. The performance of these boards will be the subject of a future publication.

  17. Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

    International Nuclear Information System (INIS)

    Nielsen, R.; Kuzay, T.M.

    1992-01-01

    Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al 2 O 3 )- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

  18. Design and characterization of integrated front-end transistors in a micro-strip detector technology

    International Nuclear Information System (INIS)

    Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; U. Pignatel, G.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

    2002-01-01

    We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures

  19. Transmitter Systems and Bidirectional RF Front-End for Millimeter-Wave Communications

    OpenAIRE

    Wu, Po-Yi

    2015-01-01

    In this dissertation, millimeter-wave transmitter systems and a bidirectional transceiver front-end circuit are presented. To reach high data rate for next generation communication systems, complex modulation schemes such as QAM are necessary to take advantage of the signal bandwidth. In a transmitter system, higher-order QAM not only requires the PA to operate in linear region, while the output power and efficiency are maintained, but also requires the calibrations for the modulator to minim...

  20. Automation of front-end loaders : electronic self leveling and payload estimation

    OpenAIRE

    Yung, I

    2017-01-01

    A growing population is driving automatization in agricultural industry to strive for more productive arable land. Being part of this process, this work is aimed to investigate the possibility to implement sensor-based automation in a particular system called Front End Loader, which is a lifting arms that is commonly mounted on the front of a tractor. Two main tasks are considered here, namely Electronic Self Leveling (ESL) and payload estimation. To propose commercially implementable solutio...

  1. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Umit H. Yapanel

    2008-08-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  2. Front-end electronics for accurate energy measurement of double beta decays

    International Nuclear Information System (INIS)

    Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

    2012-01-01

    NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

  3. Reviewed approach to defining the Active Interlock Envelope for Front End ray tracing

    Energy Technology Data Exchange (ETDEWEB)

    Seletskiy, S. [Brookhaven National Lab. (BNL), Upton, NY (United States); Shaftan, T. [Brookhaven National Lab. (BNL), Upton, NY (United States)

    2015-09-24

    To protect the NSLS-II Storage Ring (SR) components from damage from synchrotron radiation produced by insertion devices (IDs) the Active Interlock (AI) keeps electron beam within some safe envelope (a.k.a Active Interlock Envelope or AIE) in the transverse phase space. The beamline Front Ends (FEs) are designed under assumption that above certain beam current (typically 2 mA) the ID synchrotron radiation (IDSR) fan is produced by the interlocked e-beam. These assumptions also define how the ray tracing for FE is done. To simplify the FE ray tracing for typical uncanted ID it was decided to provide the Mechanical Engineering group with a single set of numbers (x,x’,y,y’) for the AIE at the center of the long (or short) ID straight section. Such unified approach to the design of the beamline Front Ends will accelerate the design process and save valuable human resources. In this paper we describe our new approach to defining the AI envelope and provide the resulting numbers required for design of the typical Front End.

  4. Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

    Directory of Open Access Journals (Sweden)

    Yapanel UmitH

    2008-01-01

    Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

  5. 40-80 MHZ MUON front-end for the Neutrino factory design study

    CERN Document Server

    Prior, G; Alexandri, A E

    2011-01-01

    To understand better the neutrino properties, machines able to produce 1021 neutrinos per year have to be built. One of the proposed machines is called the neutrino factory. In this scenario, muons produced by the decay of pions coming from the interaction of a proton beam onto a target are accelerated to energies of several GeV and injected in a storage ring where they will decay in neutrinos. The so-called front-end section of the neutrino factory is conceived to reduce the transverse divergence of the muon beam and to adapt its temporal structure to the acceptance of the downstream accelerator to minimize losses. We present a re-evaluation of the muon front-end scenario which used 40-80 MHz radio-frequency (RF) cavities capturing one sign at a time in a single-bunch to bucket mode. The standard software environment of the International Design Study for the Neutrino Factory (IDS-NF) has been used, for comparison of its performance with the IDS-NF baseline front-end design which operates with higher frequen...

  6. Web-based DAQ systems: connecting the user and electronics front-ends

    International Nuclear Information System (INIS)

    Lenzi, Thomas

    2016-01-01

    Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

  7. Proposal for a readout driver card for the ATLAS Insertable B-Layer

    CERN Document Server

    Falchieri, D; The ATLAS collaboration; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N C; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHC-PHASE1. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The poster presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

  8. ATLAS IBL: Integration of new HW/SW readout features for the additional layer of pixels

    CERN Document Server

    Gabrielli, A; The ATLAS collaboration; Bruschi, M; D’Antone, I; Dopke, J; Falchieri, D; Flick, T; Gross-Kettner, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Christian Schroer, N; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS pixel detector, called Insertable B-Layer (IBL), is under design and it will be installed by LHCPHASE1. New front-end readout ASICs fabrication is ongoing and will replace the previous chips in this layer. The new system features higher readout speed - 160Mbit/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). The paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS DAQ system.

  9. Proposal for a readout driver card for the ATLAS Insertable B-Layer

    CERN Document Server

    Falchieri, D; The ATLAS collaboration; Bruschi, M; D'Antone, I; Dopke, J; Flick, T; Gabrielli, A; Grosse-Knetter, J; Joseph, J; Krieger, N; Kugel, A; Morettini, P; Polini, A; Rizzi, M; Schroer, N; Travaglini, R; Zannoli, S; Zoccoli, A

    2010-01-01

    An additional inner layer for the existing ATLAS Pixel Detector, called Insertable B-Layer (IBL), is under design and it will be installed by Phase 1. New front-end readout ASICs fabrication (FE-I4) will replace the previous chips in this layer. The new system features higher readout speed - 160Mb/s per ASIC - and simplified control. The current data acquisition chains are composed of front-end detectors, readout chips, Back-Of-Crate (BOCs) cards and ReadOut Driver cards (RODs). This paper presents a proposal for the new ROD board, which implements modern FPGAs and high-speed links with the detector and with the ATLAS TDAQ system.

  10. Design and simulation of front end power converter for a microgrid with fuel cells and solar power sources

    Science.gov (United States)

    Jeevargi, Chetankumar; Lodhi, Anuj; Sateeshkumar, Allu; Elangovan, D.; Arunkumar, G.

    2017-11-01

    The need for Renewable Energy Sources (RES) is increasing due to increased demand for the supply of power and it is also environment friendly.In the recent few years, the cost of generation of the power from the RES has been decreased. This paper aims to design the front end power converter which is required for integrating the fuel cells and solar power sources to the micro grid. The simulation of the designed front end converter is carried out in the PSIM 9.1.1 software. The results show that the designed front end power converter is sufficient for integrating the micro grid with fuel cells and solar power sources.

  11. First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

    International Nuclear Information System (INIS)

    Szadkowski, Zbigniew

    2015-01-01

    The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone R V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

  12. Development of front-end readout electronics for multi-channel silicon detector

    International Nuclear Information System (INIS)

    Zhang Fei; Fan Ruirui; Peng Wenxi; Dong Yifan; Gong Ke; Wang Huanyu

    2014-01-01

    A front-end readout circuit used in charge measurement for multi-channel silicon detector and its performance test results are introduced in this paper. A 64-channel charge sensitive ASIC chip (VA140) from IDEAS company is adopted in this method. With its features of low power consumption (< 0.29 mW/ch), low noise (RMSE < O.l fC), large dynamic range (-200 fC∼ +200 fC) and high integration (include 64 channels preamplifier-shaper), it can be used in future particle detecting experiments base on silicon detector. (authors)

  13. Testing of the Front-End Hybrid Circuits for the CMS Tracker Upgrade

    CERN Document Server

    Gadek, Tomasz; Honma, Alan; Kovacs, Mark Istvan; Raymond, David Mark; Rose, Pierre

    2017-01-01

    The upgrade of the CMS tracker for the HL-LHC requires the design of new double-sensor, silicon detector modules, which implement Level 1 trigger functionality in the increased luminosity environment. These new modules will contain two different, high density front-end hybrid circuits, equipped with flip-chip ASICs, auxiliary electronic components and mechanical structures. The hybrids require qualification tests before they are assembled into modules. Test methods are proposed together with the corresponding test hardware and software. They include functional tests and signal injection in a cold environment to find possible failure modes of the hybrids under real operating conditions.

  14. The front end test stand high performance H- ion source at Rutherford Appleton Laboratory.

    Science.gov (United States)

    Faircloth, D C; Lawrie, S; Letchford, A P; Gabor, C; Wise, P; Whitehead, M; Wood, T; Westall, M; Findlay, D; Perkins, M; Savage, P J; Lee, D A; Pozimski, J K

    2010-02-01

    The aim of the front end test stand (FETS) project is to demonstrate that chopped low energy beams of high quality can be produced. FETS consists of a 60 mA Penning Surface Plasma Ion Source, a three solenoid low energy beam transport, a 3 MeV radio frequency quadrupole, a chopper, and a comprehensive suite of diagnostics. This paper details the design and initial performance of the ion source and the laser profile measurement system. Beam current, profile, and emittance measurements are shown for different operating conditions.

  15. A new wire chamber front-end system, based on the ASD-8 B chip

    Energy Technology Data Exchange (ETDEWEB)

    Kruesemann, B.A.M. E-mail: kruesemann@kvi.nl; Bassini, R.; Ellinghaus, F.; Frekers, D.; Hagemann, M.; Hannen, V.M.; Heynitz, H. von; Heyse, J.; Rakers, S.; Sohlbach, H.; Woertche, H.J

    1999-07-11

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  16. The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

    CERN Document Server

    Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

    2007-01-01

    In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

  17. Computer Aided Design of Microwave Front-End Components and Antennas for Ultrawideband Systems

    Science.gov (United States)

    Almalkawi, Mohammad J.

    This dissertation contributes to the development of novel designs, and implementation techniques for microwave front-end components and packaging employing both transmission line theory and classical circuit theory. For compact realization, all the presented components have been implemented using planar microstrip technology. Recently, there has been an increase in the demand for compact microwave front-ends which exhibit advanced functions. Under this trend, the development of multiband front-end components such as antennas with multiple band-notches, dual-band microwave filters, and high-Q reconfigurable filters play a pivotal role for more convenient and compact products. Therefore, the content of this dissertation is composed of three parts. The first part focuses on packaging as an essential process in RF/microwave integration that is used to mitigate unwanted radiations or crosstalk due to the connection traces. In printed circuit board (PCB) interconnects, crosstalk reduction has been achieved by adding a guard trace with/without vias or stitching capacitors that control the coupling between the traces. In this research, a new signal trace configuration to reduce crosstalk without adding additional components or guard traces is introduced. The second part of this dissertation considers the inherent challenges in the design of multiple-band notched ultrawideband antennas that include the integration of multilayer antennas with RF front-ends and the realization of compact size antennas. In this work, a compact UWB antenna with quad band-notched frequency characteristics was designed, fabricated, and tested demonstrating the desired performance. The third part discusses the design of single- and dual-band dual-mode filters exhibiting both symmetric and asymmetric transfer characteristics. In dual-mode filters, the numbers of resonators that determine the order of a filter are reduced by half while maintaining the performance of the actual filter order. Here, in

  18. Managing inter-firm collaboration in the fuzzy front-end

    DEFF Research Database (Denmark)

    Jørgensen, Jacob; Bergenholtz, Carsten; Goduscheit, René Chester

    2011-01-01

    Literature on innovation emphasises the potential for organisations to collaborate and network instead of carrying out innovation individually. Integrating suppliers, customers and other organisations into the innovation process is perceived as a key to success in innovation management (Chesbrough...... organisations in an innovation network are somewhat neglected in the literature. The aim of this paper is hence to address the challenges that an organisation faces when integrating a plurality of suppliers, customers and other organisations into the Fuzzy Front End of the innovation process....

  19. A front-end ASIC for ionising radiation monitoring with femto-amp capabilities

    International Nuclear Information System (INIS)

    Voulgari, E.; Noy, M.; Anghinolfi, F.; Perrin, D.; Krummenacher, F.; Kayal, M.

    2016-01-01

    An ultra-low leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 μm CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) through charge balancing and demonstrates a wide dynamic range of 8.5 decades without range changing. Due to a design aimed at minimising input leakage currents, input currents as low as 01 fA can be measured

  20. BGO front-end electronics and signal processing in the MXGS instrument for the ASIM mission

    DEFF Research Database (Denmark)

    Skogseide, Yngve; Cenkeramaddi, Linga Reddy; Genov, Georgi

    2012-01-01

    for the design and development of the detector layers and readout electronics for the MXGS instrument. The principal objective of the instrument is to detect Terrestrial Gamma ray Flashes (TGFs), which are related to thunderstorm activity. The digital pulse processing scheme used in the MXGS BGO detector gives......This paper presents the Bismuth Germanate Oxide (BGO) front-end electronics design and signal processing in Modular X- and Gamma ray sensor (MXGS) instrument onboard the Atmosphere Space Interaction Monitor (ASIM) mission, funded by the European Space Agency. University of Bergen is responsible...

  1. LHCb: Test Station for the LHCb Muon Front-End Electronic

    CERN Multimedia

    Polycarpo, E

    2005-01-01

    The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

  2. A new wire chamber front-end system, based on the ASD-8 B chip

    CERN Document Server

    Kruesemann, B A M; Ellinghaus, F; Frekers, D; Hagemann, M; Hannen, V M; Heynitz, H V; Heyse, J; Rakers, S; Sohlbach, H; Wörtche, H J

    1999-01-01

    The Focal-Plane Polarimeter (FPP) for the Big-Bite Spectrometer van den Berg (Nucl. Instr. and Meth. B 99 (1995) 637ff) at the KVI requires the read-out of four large-area MWPCs and two VDCs with 3872 wires in total. The EUROSUPERNOVA collaboration (SNOVA) developed a digital 16 channel preamplifier front-end board, housing two amplifier-shaper-discriminatorchips ASD-8 B. The main features of this board are a fast single-wire readout, a high integration density, a low power consumption and compatibility to common instrumentation standards. The board represents the first successfully running application of the ASD-8 for wire chamber readout. (author)

  3. Polyphase Filter Banks for Embedded Sample Rate Changes in Digital Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2011-01-01

    This paper presents efficient processing engines for software-defined radio (SDR) front-ends. These engines, based on a polyphase channelizer, perform arbitrary sample-rate changes, frequency selection, and bandwidth control. This paper presents an M-path polyphase filter bank based on a modified N....... A non-maximally-decimated polyphase filter bank (where the number of data loads is not equal to the number of M subfilters) processes M subfilters in a time period that is less than or greater than the M data loads. A polyphase filter bank with five different resampling modes is used as a case study...

  4. A new design for SLAM front-end based on recursive SOM

    Science.gov (United States)

    Yang, Xuesi; Xia, Shengping

    2015-12-01

    Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

  5. Optimization of the design of DC-DC converters for improving the electromagnetic compatibility with the Front-End electronic for the super Large Hadron Collider Trackers

    CERN Document Server

    Fuentes Rojas, Cristian Alejandro; Blanchot, G

    2011-01-01

    The upgrade of the Large Hadron Collider (LHC) experiments at CERN sets new challenges for the powering of the detectors. One of the powering schemes under study is based on DC-DC buck converters mounted on the front-end modules. The hard environmental conditions impose strict restrictions to the converters in terms of low volume, radiation and magnetic field tolerance. Furthermore, the noise emission of the switching converters must not affect the performance of the powered systems. A study of the sources and paths of noise of a synchronous buck converter has been made for identifying the critical parameters to reduce their emissions. As proof of principle, a converter was designed following the PCB layout considerations proposed and then used for powering a silicon strip module prototype for the ATLAS upgrade, in order to evaluate their compatibility.

  6. Performance of a 128 channel analogue front-end chip for read-out of Si strip detector modules for LHC experiments

    CERN Document Server

    Chesi, Enrico Guido; Cindro, V; Dabrowski, W; Ferrère, D; Kramberger, G; Kaplon, J; Lacasta, C; Lozano-Bahilo, J; Mikuz, M; Morone, C; Roe, S; Szczygiel, R; Tadel, M; Weilhammer, Peter; Zsenei, A

    2000-01-01

    We present a 128-channel analogue front-end chip, SCT128A-HC, for readout of silicon strip detectors employed in the inner tracking detectors of the LHC experiment. The chip is produced in the radiation hard DMILL technology. The architecture of the chip and critical design issues are discussed. The performance of the chip has been evaluated in details in the test bench and is presented in the paper. The chip is used to read out prototype analogue modules compatible in size, functionality and performance with the ATLAS SCT base line modules. Several full size detector modules equipped with SCT128A-HC chips has been built and tested successfully in the lab with beta particles as well as in the test beam. The results concerning the signal-to-noise ratio, noise occupancy, efficiency and spatial resolution are presented. The radiation hardness issues are discussed. (5 refs).

  7. A 3-Channel 14-Bit Optimum SNS Wideband Digital Antenna: Analysis of the Electro-Optic Sampling Front End

    National Research Council Canada - National Science Library

    Foster, Kevin

    1997-01-01

    .... This thesis describes the design, construction, testing and analysis of the optical electronics at the front end of a prototype optimum SNS digital antenna with a desired accuracy of 14 bits and a bandwidth of 2.5 MHz...

  8. System Electronics for the ATLAS Upgraded Strip Detector

    CERN Document Server

    Affolder, T; The ATLAS collaboration; Clark, A; Dabrowskic, W; Dewitt, J; Diez Cornell, S; Dressdant, N; Fadeyev, V; Farthouat, P; Ferrere, D; Greenall, A; Grillo, A; Kaplon, J; Key-Charriere, M; La Marra, D; Lipeles, E; Lynn, D; Newcomer, M; Pereirab, F; Phillips, P; Spencer, E; Swientekc, K; Warren, M; Weidberg, A

    2013-01-01

    The basic concept of the front-end system of the Silicon Strip Detector in the Atlas Detector upgraded for the HL-LHC is being elaborated and proposed. The readout electronics of this new detector is based on front-end chips (ABC130), Hybrid Controller chips (HCC) and End of Stave Controller chips (EOSC). This document defines the basic functionality of the front-end system and of the different ASICs.

  9. BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

    International Nuclear Information System (INIS)

    Baum, G.; Birsa, R.; Bradamante, F.; Bressan, A.; Colavita, A.; Crespo, M.; Costa, S.; Dalla Torre, S.; Fauland, P.; Finger, M.; Fratnik, F.; Giorgi, M.; Gobbo, B.; Grasso, A.; Lamanna, M.; Martin, A.; Menon, G.; Panzieri, D.; Schiavon, P.; Tessarotto, F.; Zanetti, A.M.

    1999-01-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

  10. FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

    International Nuclear Information System (INIS)

    Alexanian, H.; Appelquist, G.; Bailly, P.

    1995-01-01

    We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

  11. Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management.

    Science.gov (United States)

    George, Libin; Gargiulo, Gaetano Dario; Lehmann, Torsten; Hamilton, Tara Julia

    2015-11-19

    Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm²), uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm) 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

  12. CPRF/ZTH front-end torus design and fabrication status

    International Nuclear Information System (INIS)

    Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

    1989-01-01

    Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end torus. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

  13. Concept Design for a 1-Lead Wearable/Implantable ECG Front-End: Power Management

    Directory of Open Access Journals (Sweden)

    Libin George

    2015-11-01

    Full Text Available Power supply quality and stability are critical for wearable and implantable biomedical applications. For this reason we have designed a reconfigurable switched-capacitor DC-DC converter that, aside from having an extremely small footprint (with an active on-chip area of only 0.04 mm2, uses a novel output voltage control method based upon a combination of adaptive gain and discrete frequency scaling control schemes. This novel DC-DC converter achieves a measured output voltage range of 1.0 to 2.2 V with power delivery up to 7.5 mW with 75% efficiency. In this paper, we present the use of this converter as a power supply for a concept design of a wearable (15 mm × 15 mm 1-lead ECG front-end sensor device that simultaneously harvests power and communicates with external receivers when exposed to a suitable RF field. Due to voltage range limitations of the fabrication process of the current prototype chip, we focus our analysis solely on the power supply of the ECG front-end whose design is also detailed in this paper. Measurement results show not just that the power supplied is regulated, clean and does not infringe upon the ECG bandwidth, but that there is negligible difference between signals acquired using standard linear power-supplies and when the power is regulated by our power management chip.

  14. A Comparative Analysis of CMUT Receiving Architectures for the Design Optimization of Integrated Transceiver Front Ends.

    Science.gov (United States)

    Sautto, Marco; Savoia, Alessandro Stuart; Quaglia, Fabio; Caliano, Giosue; Mazzanti, Andrea

    2017-05-01

    A formal comparison between fundamental RX amplifier configurations for capacitive micromachined ultrasonic transducers (CMUTs) is proposed in this paper. The impact on both RX and the pulse-echo frequency response and on the output SNR is thoroughly analyzed and discussed. It is shown that the resistive-feedback amplifier yields a bandpass RX frequency response, while both open-loop voltage and capacitive-feedback amplifiers exhibit a low-pass frequency response. For a given power dissipation, it is formally proved that a capacitive-feedback amplifier provides a remarkable SNR improvement against the commonly adopted resistive feedback stage, achieved at the expense of a reduced pulse-echo center frequency, making its use convenient in low-frequency and midfrequency ultrasound imaging applications. The advantage mostly comes from a much lower noise contributed by the active devices, especially with low- Q , broadband transducers. The results of the analysis are applied to the design of a CMUT front end in BIPOLAR-CMOS-DMOS Silicon-on-Insulator technology operating at 10-MHz center frequency. It comprises a low-power RX amplifier, a high-voltage Transmission/Reception switch, and a 100-V TX driver. Extensive electrical characterization, pulse-echo measurements, and imaging results are shown. Compared with previously reported CMUT front ends, this transceiver demonstrates the highest dynamic range and state-of-the-art noise performance with an RX amplifier power dissipation of 1 mW.

  15. BORA: A front end board, with local intelligence, for the rich detector of the compass collaboration

    International Nuclear Information System (INIS)

    Baum, G.; Birsa, R.; Bradamante, F.

    1999-02-01

    In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analogue voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analogue channel. After the analog values are digitized they are written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analogue channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC. (author)

  16. Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

    Energy Technology Data Exchange (ETDEWEB)

    Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2015-07-01

    The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

  17. Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

    International Nuclear Information System (INIS)

    Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

    2008-01-01

    The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

  18. An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

    Science.gov (United States)

    Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

    2015-10-01

    An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

  19. Front end with offset-free symmetrical current source optimized for time domain impedance spectroscopy.

    Science.gov (United States)

    Pliquett, Uwe; Schönfeldt, Markus; Barthel, Andreas; Frense, Dieter; Nacke, Thomas; Beckmann, Dieter

    2011-07-01

    Fast impedance measurements are often performed in time domain utilizing broad bandwidth excitation signals. Other than in frequency domain measurements harmonic distortion cannot be compensated which requires careful design of the analog front end. In order to minimize the influence of electrode polarization and noise, especially in low-frequency measurements, current injection shows several advantages compared to voltage application. Here, we show an active front end based on a voltage-controlled current source for a wide range of impedances. Using proper feedback, the majority of the parasitic capacitances are compensated. The bandwidth ranges from dc to 20 MHz for impedance magnitude below 5 kΩ. The output is a symmetric signal without dc-offset which is accomplished by combination of a current conveyor and a voltage inverter. An independent feedback loop compensates the offset arising from asymmetries within the circuitry. We focused especially on the stability of the current source for usage with small metal electrodes in aqueous solutions. At the monitor side two identical, high input impedance difference amplifiers convert the net current through the object and the voltage dropping across into a 50 Ω symmetric output. The entire circuitry is optimized for step response making it suitable for fast time domain measurements.

  20. Characterisation of the VMM3 Front-end read-out ASIC

    CERN Document Server

    Bartels, Lara Maria

    2018-01-01

    This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

  1. Numerical study of a magnetically insulated front-end channel for a neutrino factory

    Directory of Open Access Journals (Sweden)

    Diktys Stratakis

    2011-01-01

    Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

  2. Front-End Data Reduction in Computer-Aided Diagnosis of Mammograms: A Pilot Study

    Energy Technology Data Exchange (ETDEWEB)

    Gleason, S.S.; Nishikawa, R.M.; Sari-Sarraf, H.

    1999-02-20

    This paper presents the results of a pilot study whose primary objective was to further substantiate the efficacy of front-end data reduction in computer-aided diagnosis (CAD) of mammograms. This concept is realized by a preprocessing module that can be utilized at the front-end of most mammographic CAD systems. Based on fractal encoding, this module takes a mammo-graphic image as its input and generates, as its output, a collection of subregions called focus-of-attention regions (FARs). These FARs contain all structures in the input image that appear to be different from the normal background tissue. Subsequently, the CAD systems need only to process the presented FARs, rather than the entire input image. This accomplishes two objectives simultaneously: (1) an increase in throughput via a reduction in the input data, and (2) a reduction in false detections by limiting the scope of the detection algorithms to FARs only. The pilot study consisted of using the preprocessing module to analyze 80 mammographic images. The results were an average data reduction of 83% over all 80 images and an average false detection reduction of 86%. Furthermore, out of a total of 507 marked microcalcifications, 467 fell within FW, representing a coverage rate of 92%.

  3. A front-end electronic system for large arrays of bolometers

    Science.gov (United States)

    Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

    2018-02-01

    CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

  4. Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

    KAUST Repository

    Bader, Ahmed

    2016-06-14

    The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

  5. Front-end electronics and readout system for the ILD TPC

    CERN Document Server

    Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

    2015-01-01

    A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

  6. OLS Dialog: An open-source front end to the Ontology Lookup Service

    Directory of Open Access Journals (Sweden)

    Eidhammer Ingvar

    2010-01-01

    Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

  7. CPRF/ZTH front-end torus design and fabrication status

    International Nuclear Information System (INIS)

    Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

    1989-01-01

    Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

  8. A low power dual-band multi-mode RF front-end for GNSS applications

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Hao; Li Zhiqun; Wang Zhigong, E-mail: zhhseu@gmail.com [Institute of RF- and OE- ICs, Southeast University, Nanjing 210096 (China)

    2010-11-15

    A CMOS dual-band multi-mode RF front-end for the global navigation satellite system receivers of all GPS, Bei-Dou, Galileo and Glonass systems is presented. It consists of a reconfigurable low noise amplifier (LNA), a broadband active balun, a high linearity mixer and a bandgap reference (BGR) circuit. The effect of the input parasitic capacitance on the input impedance of the inductively degenerated common source LNA is analyzed in detail. By using two different LC networks at the input port and the switched capacitor at the output port, the LNA can work at two different frequency bands (1.2 GHz and 1.5 GHz) under low power consumption. The active balun uses a hybrid-connection structure to achieve high bandwidth. The mixer uses the multiple gated transistors technique to acquire a high linearity under low power consumption but does not deteriorate other performances. The measurement results of the proposed front-end achieve a noise figure of 2.1/2.0 dB, again of 33.9/33.8 dB and an input 1-dB compression point of 0/1 dBm at 1227.6/1575.42 MHz. The power consumption is about 16 mW under a 1.8 V power supply.

  9. Dedicated front-end and readout electronics developments for real time 3D directional detection of dark matter with MIMAC

    OpenAIRE

    Bourrion, O.; Bosson, G.; Grignon, C.; Richer, J. P.; Guillaudin, O.; Mayet, F.; Billard, J.; Santos, D.

    2011-01-01

    A complete dedicated electronics, from front-end to back-end, was developed to instrument a MIMAC prototype. A front end ASIC able to monitor 64 strips of pixels and to provide their individual "Time Over Threshold" information has been designed. An associated acquisition electronics and a real time track reconstruction software have been developed to monitor a 512 channel prototype. This auto-triggered electronic uses embedded processing to reduce the data transfer to its useful part only, i...

  10. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

    Energy Technology Data Exchange (ETDEWEB)

    Knopf, Jan

    2009-07-08

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  11. Architecture and Implementation of the Front-End Electronics of the Time Projection Chambers in the T2K Experiment

    Science.gov (United States)

    Baron, P.; Besin, D.; Calvet, D.; Coquelet, C.; De La Broise, X.; Delagnes, E.; Druillole, F.; Le Coguie, A.; Monmarthe, E.; Zonca, E.

    2010-04-01

    The tracker of the near detector in the T2K neutrino oscillation experiment comprises three time projection chambers based on micro-pattern gaseous detectors. A new readout system is being developed to amplify, condition and acquire in real time the data produced by the 124.000 detector channels. The cornerstone of the system is a 72-channel application specific integrated circuit which is based on a switched capacitor array. Using analog memories combined with deferred digitization enables reducing the initial burstiness of traffic from 50 Tbps to 400 Gbps in a practical manner and with a very low power budget. Modern field programmable gate arrays coupled to commercial digital memories are the next elements in the chain. Multi-gigabit optical links provide 140 Gbps of aggregate bandwidth to carry data outside of the magnet surrounding the detector to concentrator cards that pack data and provide the interface to commercial PCs via a standard Gigabit Ethernet network. We describe the requirements and constraints for this application and justify our technical choices. We detail the design and the performance of several key elements and show the deployment of the front-end electronics on the first time projection chamber where the final tests before installation on-site are being conducted.

  12. Ammonia-water exchange front end process for ammonia-hydrogen heavy water plants (Preprint No. PD-1)

    International Nuclear Information System (INIS)

    Sadhukhan, H.K.; Varadarajan, T.G.; Nair, N.K.; Das, S.K.; Nath, G.K.

    1989-04-01

    The ammonia-hydrogen exchange process, which utilizes the deutrium exchange between liquid ammonia and gaseous hydrogen is a parasitic process and the heavy water plants (HWP) based on this process has to be linked with the fertilizer plant (FP) for its enormous requirements of hydrogen (synthesis gas, N 2 +3H 2 ). This dependence of HWP on FP gives rise to certain constraints which are listed. These deficiencies of the ammonia-hydrogen process can be overcome to a great extent by delinking the HWP from FP by incorporating NH 3 -H 2 O exchange as the front end step. In addition to the elimination of the above limitations, by employing water as the ultimate feed for the HWP, the plant capacity can be increased substantially and this would go a long way in achieving economies of the large capacity plants. A schematic diagram of this integrated plant is given. Some of the results of developmental efforts and feasibility studies of this NH 3 -H 2 O exchange are briefly reviewed. (author). 4 figs

  13. The front-end electronics for the 1.8-kchannel SiPM tracking plane in the NEW detector

    International Nuclear Information System (INIS)

    Rodríguez, J.; Lorca, D.; Monrabal, F.; Toledo, J.; Esteve, R.

    2015-01-01

    NEW is the first phase of NEXT-100 experiment, an experiment aimed at searching for neutrinoless double-beta decay. NEXT technology combines an excellent energy resolution with tracking capabilities thanks to a combination of optical sensors, PMTs for the energy measurement and SiPMs for topology reconstruction. Those two tools result in one of the highest background rejection potentials in the field. This work describes the tracking plane that will be constructed for the NEW detector which consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards. Then it focuses in the development of the electronics needed to read the 1800 channels with a front-end board that includes per-channel differential transimpedance input amplifier, gated integrator, automatic offset voltage compensation and 12-bit ADC. Finally, a description of how the FPGA buffers data, carries out zero suppression and sends data to the DAQ interface using CERN RD-51 SRS's DTCC link specification complements the description of the electronics of the NEW detector tracking plane

  14. Key differences and similarities in ways of managing and supporting radical pharmaceutical front end innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2015-01-01

    the different nationalities. This presents propositions of important aspects to consider in facilitation of radical FEI in general and in multinational pharmaceutical companies. In addition, proposals are made for a global study of innovation management and FEI support including Chinese and other Asian......The purpose of this paper is to explore how Front End Innovation (FEI) is supported and managed among companies of different nationality within the context of pharmaceutical R&D. The present study is carried out in order to contribute to the development of a clearer understanding of active...... of the Danish and US based pharmaceutical company, H. Lundbeck A/S, and a comparative study including five European and American pharmaceutical companies. The findings from the study reveal a number of similarities and differences in innovation management and FEI support of radical projects and among...

  15. Review of input stages used in front end electronics for particle detectors

    CERN Document Server

    Kaplon, J

    2015-01-01

    In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

  16. CMOS front end analog signal readout chip for Si-strip/PIN detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2001-01-01

    The paper presents the design of an 8-channel front-end chip for Si-strip detectors, ranging in capacitance from 1 to 30 pf. Each channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a track-hold stage. The channel outputs are connected to an analog multiplexer which is controlled by an external clock for serial readout. The peaking time is adjustable over 250ns-2us in four fixed steps by external control. There is provision for changing gain low/high. A derivative of the chip is also developed for dosimeter application that uses small area diodes as detectors. The circuit has a power dissipation of 6 MW per channel and is designed to fabricate in 1.2um CMOS technology. The Opf noise is ∼400e. The design approach is presented and the results of simulation are shown. (author)

  17. LTCC-Based Highly Integrated Millimeter-Wave Receiver Front-End Module

    Science.gov (United States)

    Xia, Lei; Xu, Ruimin; Yan, Bo

    2006-07-01

    This paper presents the design and fabrication of a highly integrated Low Temperature Co-fired Ceramic (LTCC) receiver front-end module. This LTCC module is a dual channel receiver module, works at Ka-band, and fabricated including six Ferro A6M dielectric layers and five metal layers, contains eight embedded resistors and eight MMICs. All MMICs are mounted into pre-making cavities on the top surface of the LTCC substrate. Three slot coupled waveguide-to-microstrip transitions are integrated at LTCC substrate to realize RF and LO signal input. The developed module is highly integrated and reliable, which has a compact size of 58 × 50 × 22 mm3 (including the metal cavity). Each channel of the receiver has the noise figure of less than 9 dB and the gain of more than 24 dB at Ka-band.

  18. Physics at the front-end of a neutrino factory a quantitative appraisal

    CERN Document Server

    Mangano, Michelangelo L.; Anselmino, M.; Ball, R.D.; Boglione, Mariaelena; D'Alesio, U.; Davidson, S.; Lellis, De; Ellis, John R.; Forte, S.; Gambino, P.; Gehrmann, T.; Kataev, A.L.; Kotzinian, A.; Kulagin, Sergey A.; Lehmann-Dronke, B.; Migliozzi, P.; Murgia, F.; Ridolfi, G.

    2004-01-01

    We present a quantitative appraisal of the physics potential for neutrino experiments at the front-end of a muon storage ring. We estimate the forseeable accuracy in the determination of several interesting observables, and explore the consequences of these measurements. We discuss the extraction of individual quark and antiquark densities from polarized and unpolarized deep-inelastic scattering. In particular we study the implications for the undertanding of the nucleon spin structure. We assess the determination of alpha_s from scaling violation of structure functions, and from sum rules, and the determination of sin^2(theta_W) from elastic nu-e and deep-inelastic nu-p scattering. We then consider the production of charmed hadrons, and the measurement of their absolute branching ratios. We study the polarization of Lambda baryons produced in the current and target fragmentation regions. Finally, we discuss the sensitivity to physics beyond the Standard Model.

  19. The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

    DEFF Research Database (Denmark)

    Aagaard, Annabeth

    2012-01-01

    , Steven & Burly, 2003, and Vernorn et al., 2008) and that innovation strategies play a central role in optimization of innovation (Clark & Wheelwright, 1995; Cottam et al., 2001; Morgan & Berthon, 2008). Innovation strategies are suggested in literature (e.g. Page, 1993; Oke, 2002; Adams et al., 2006...... research and FEI to produce more valid candidates and faster for drug development. This paper explores how pharmaceutical front end innovation can be actively supported through the development and implementation of an innovation strategy. The empirical field and applied methodology is an action......-oriented longitudinal case study of a Danish pharmaceutical company. The findings and key learnings from the study are presented as propositions of how innovation strategies can be applied to actively facilitate FEI and with measurable results....

  20. Prototype specification of antenna and radio front-end schemes for PAN devices

    DEFF Research Database (Denmark)

    Wang, Yu; Nguyen, Hung Tuan; johansson, Anders

    2007-01-01

    be implemented in the prototype directly, or used as references in antenna selections for the prototype. Interference mitigation on antenna system level for both HDR and LDR systems is investigated. For the LDR system, interference from the HDR system and UWB systems is identified as most critical. Front......-end filtering with high attenuation on 5.2 GHz is suggested to suppress interference from the HDR system. A low-complexity switching diversity antenna system is designed to mitigate UWB interference. The performance of proposed scheme is evaluated with measured channels. The implementation of the scheme......This document provides antenna system specifications for the MAGNET Beyond prototype. Requirements on selecting antenna elements and diversity antenna systems are presented. A number of antenna elements and diversity systems suitable for MAGNET systems are specified. Presented antennas can...

  1. Front-End-Electronics Communication software for multiple detectors in the ALICE experiment

    CERN Document Server

    Bablok, Sebastian; Hartung, G; Keidel, R; Kofler, C; Krawutschke, T; Lindenstruth, V; Röhrich, D

    2006-01-01

    In the ALICE experiment at CERN, the Detector Control System (DCS) employs several interacting software components to accomplish its task of ensuring the correct operation and monitoring of the experiment. This paper describes the Front-End-Electronics Communication (FeeCommunication) software and its role within the DCS. The FeeCommunication software's central task is passing configuration and monitoring data between the top level DCS process control and the field devices of several detectors within ALICE. The lowest level of the FeeCommunication software runs on the DCS boards, specialized embedded systems which are in direct contact with the field devices and are physically located within the detector. The middle and upper layers run on standard PC hardware located in the counting room or other external locations. This paper focuses on the design and implementation of the FeeCommunication software and the steps that were taken to fulfill the imposed reliability and performance requirements, specifically th...

  2. Detector and Front-end electronics for ALICE and STAR silicon strip layers

    CERN Document Server

    Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

    1998-01-01

    Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

  3. Cognitive radio receiver front-ends RF/analog circuit techniques

    CERN Document Server

    Sadhu, Bodhisatwa

    2014-01-01

    This book focuses on the architecture and circuit design for cognitive radio receiver front-ends.  The authors first provide a holistic explanation of RF circuits for cognitive radio systems. This is followed by an in-depth exploration of existing techniques that can be utilized by circuit designers. Coverage also includes novel circuit techniques and architectures that can be invaluable for designers for cognitive radio systems.   • Discusses in detail the circuit-level challenges that exist for cognitive radio systems; • Provides readers with a holistic understanding of RF circuits for cognitive radio systems; • Enables communications engineers and systems designers to design better cognitive radio architectures and communication protocols.

  4. Impact of political and legislative events on the front end of the fuel cycle

    International Nuclear Information System (INIS)

    Steyn, J.J.

    1987-01-01

    This paper examines recent political and legislative events in the U.S. which could impact the supply of natural uranium, uranium hexafluoride, conversion services, and uranium enrichment services. While the industry has been clouded with continuing uncertainty resulting from the ongoing miners vs. DOE litigation and a number of legislative proposals to embargo the import of uranium, very little attention was being paid to the free trade agreement discussions which were taking place between the U.S. and Canada. However, with a draft agreement now being fact and its ratification a possibility by mid-1988, the front end of the fuel cycle may finally begin to achieve some normalcy within the next year. The impact of these factors on the industry are addressed

  5. A front-end read out chip for the OPERA scintillator tracker

    CERN Document Server

    Lucotte, A; Borer, K; Campagne, J E; Cazes, A; Hess, M; de La Taille, C; Martin-Chassard, G; Raux, L; Repellin, J P

    2004-01-01

    Multi-anode photomultipliers H7546 are used to readout signal from the OPERA Scintillator Tracker (CERN/SPSC 2000-028, SPSC/P318, LNGSP 25/2000; CERN/SPSC 2001-025, SPSC/M668, LNGS-EXP30/2001). A 32- channel front-end Read Out Chip prototype accommodating the H7546 has been designed at LAL. This device features a low-noise, variable gain preamplifier to correct for multi-anode non-uniformity, an auto- trigger capability 100% efficient at a 0.3 photo-electron, and a charge measurement extending over a large dynamic range left bracket 0-100 right bracket photo-electrons. In this article we describe the ASIC architecture that is being implemented for the Target Tracker in OPERA, with a special emphasis put on the designs and the measured performance.

  6. Front end electronics and first results of the ALICE V0 detector

    Energy Technology Data Exchange (ETDEWEB)

    Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

    2011-01-21

    This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

  7. Modeling, simulation, and optimization of a front-end system for acetylene hydrogenation reactors

    Directory of Open Access Journals (Sweden)

    R. Gobbo

    2004-12-01

    Full Text Available The modeling, simulation, and dynamic optimization of an industrial reaction system for acetylene hydrogenation are discussed in the present work. The process consists of three adiabatic fixed-bed reactors, in series, with interstage cooling. These reactors are located after the compression and the caustic scrubbing sections of an ethylene plant, characterizing a front-end system; in contrast to the tail-end system where the reactors are placed after the de-ethanizer unit. The acetylene conversion and selectivity profiles for the reactors are optimized, taking into account catalyst deactivation and process constraints. A dynamic optimal temperature profile that maximizes ethylene production and meets product specifications is obtained by controlling the feed and intercoolers temperatures. An industrial acetylene hydrogenation system is used to provide the necessary data to adjust kinetics and transport parameters and to validate the approach.

  8. Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

    Science.gov (United States)

    Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

    2015-08-01

    This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

  9. Radiation Protection Aspects of the Linac Coherent Light Source Front End Enclosure

    Energy Technology Data Exchange (ETDEWEB)

    Vollaire, J.; Fasso, A.; Liu, J.C.; Mao, X.S.; Prinz, A.; Rokni, S.H.; Leitner, M.Santana; /SLAC

    2010-08-26

    The Front End Enclosure (FEE) of the Linac Coherent Light Source (LCLS) is a shielding housing located between the electron dump area and the first experimental hutch. The upstream part of the FEE hosts the commissioning diagnostics for the FEL beam. In the downstream part of the FEE, two sets of grazing incidence mirror and several collimators are used to direct the beam to one of the experimental stations and reduce the bremsstrahlung background and the hard component of the spontaneous radiation spectrum. This paper addresses the beam loss assumptions and radiation sources entering the FEE used for the design of the FEE shielding using the Monte-Carlo code FLUKA. The beam containment system prevents abnormal levels of radiations inside the FEE and ensures that the beam remains in its intended path is also described.

  10. A low power low noise analog front end for portable healthcare system

    International Nuclear Information System (INIS)

    Wang Yanchao; Ke Keren; Qin Wenhui; Qin Yajie; Yi Ting; Hong Zhiliang

    2015-01-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

  11. PDP-11 front-end for a VAX-11/780

    International Nuclear Information System (INIS)

    Browne, M.J.; Granieri, C.; Sherden, D.J.; Weaver, L.J.

    1980-01-01

    An unpublicized feature of the VAX-11/780 is the provision for attaching a PDP-11 to the VAX UNIBUS Adapter. Doing this can give significantly improved I/O performance for applications which are limited by overhead in the VAX I/O driver rather than by the transfer speed of the UNIBUS itself. Such a system was implemented by using a PDP-11/04 as a front-end to a CAMAC data acquisition system. Both the PDP and the VAX have full access to the UNIBUS. That portion of the PDP address space that does not have UNIBUS memory can be mapped to buffers in the VAX memory; this approach allows the PDP to access VAX memory and to initiate DMA transfers directly to the VAX. The VAX also has full access to the PDP memory; a convenient means for developing and downloading the PDP software is thus provided. 5 figures

  12. Interfirm collaboration in the Fuzzy Front-End of the innovation process

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholtz, Carsten

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... recommendations for the manufacturer to improve the innovation process and enhance the chances of success. However, the waist majority of these projects belong to an intra-organizational paradigm where the manufacturer is considered to be the only part involved in the process, controlling and influencing......, marketing, sales. The focus of this paper is on collaboration where innovation is the main part of the collaborative effort. Innovation refers to the research and development (R&D) activity devoted to increasing scientific or technical knowledge and the application of that knowledge to the creation of new...

  13. A front-end system for industrial type controls at the SSC

    International Nuclear Information System (INIS)

    Haenni, D.R.

    1992-01-01

    The SSC control system is tasked with coordinating the operation of many different accelerator subsystems, a number of which use industrial type process controls. The design of a high-performance control system front end is presented which serves both as a data concentrator and a distributed process controller. In addition it provides strong support for a centralized control system architecture, allows for regional control systems, and simplifies the construction of inter-subsystem controls. An implementation of this design will be discussed which uses STD-Bus for accelerator hardware interfacing, a time domain multiplexing (TDM) communications transport system, and a modified reflective memory interface to the rest of the control system. (author)

  14. Understanding Managers Decision Making Process for Tools Selection in the Core Front End of Innovation

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; McAloone, Tim C.

    2011-01-01

    and optimise the activities. To select these tools, managers of the product development team have to use several premises to decide upon which tool is more appropriate to which activity. This paper proposes an approach to model the decision making process of the managers. The results underline the dimensions......New product development (NPD) describes the process of bringing a new product or service to the market. The Fuzzy Front End (FFE) of Innovation is the term describing the activities happening before the product development phase of NPD. In the FFE of innovation, several tools are used to facilitate...... influencing the decision process before a certain tool is chosen, and how those tools impact the performance of cost, time and efficiency. In order to achieve this, five companies participated for the data collection. Interesting trends and differences emerge from the analysis of the data in hand, and several...

  15. A full custom analog front-end for long-time ECG monitoring.

    Science.gov (United States)

    Wen, Meiying; Cheng, Yayu; Li, Ye

    2013-01-01

    An analog front-end (AFE) used in portable electrocardiogram (ECG) monitoring devices is proposed. This AFE has included all necessary functions for the commercial applications. The core circuit consists of the instrumentation amplifier (IA), a 2(nd) order Butterworth low pass filter, and the second amplifying stage. The driven-right-leg circuit is integrated in the IA to effectively suppress the common mode interference. And the power management circuits provide a stable supply voltage, bias current and reference voltage for the other circuits. To guarantee the validity of the continuous monitoring data, the leadoff monitoring circuit is developed to monitor the connection of the leads. The chip is taped out with SMIC 0.18 µm CMOS process, and the measured results show that the common mode rejection ratio (CMRR) and power supply rejection ratio (PSRR) achieve 75 dB and 90dB respectively, and the equivalent input referred noise is 12 µV.

  16. Fuzzy Decision Support for Tools Selection in the Core Front End Activities of New Product Development

    DEFF Research Database (Denmark)

    Achiche, S.; Appio, F.P.; McAloone, Tim C.

    2013-01-01

    managers, working for five different companies. The automatically constructed FDSMs accurately reproduced the managers’ estimations using the learning data sets and were very robust when validated with hidden data sets. The developed models can be easily used for quick financial assessments of tools...... in CFE activities can vary a lot and hence largely influence their financial performances later on in the NPD process......., an economic evaluation of the cost of tool usage is critical, and there is furthermore a need to characterize them in terms of their influence on the FE. This paper focuses on decision support for managers/ designers in their process of assessing the cost of choosing/using tools in the core front end (CFE...

  17. System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe.

    Science.gov (United States)

    Di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere; Jorgensen, Ivan Harald Holger; Jensen, Jorgen Arendt

    2016-11-01

    In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point spread function is simulated in Field II from 10 to 160 mm using a convex array transducer. A noise analysis is performed, and the minimum signal-to-noise ratio (SNR) requirements are derived for the low-noise amplifiers (LNAs) and A/D converters (ADCs) to fulfill the design specifications of a dynamic range of 60 dB and a penetration depth of 160 mm in the B-mode image. Six front-end implementations are compared using Nyquist-rate and Σ∆ modulator ADCs. The image quality is evaluated as a function of the depth in terms of lateral full-width at half-maximum (FWHM) and -12-dB cystic resolution (CR). The designs that minimally satisfy the specifications are based on an 8-b 30-MSPS Nyquist converter and a single-bit third-order 240-MSPS Σ∆ modulator, with an SNR for the LNA in both cases equal to 64 dB. The mean lateral FWHM and CR are 2.4% and 7.1% lower for the Σ∆ architecture compared with the Nyquist-rate one. However, the results generally show minimal differences between equivalent architectures. Advantages and drawbacks are finally discussed for the two families of converters.

  18. Optimizing read-out of the NECTAr front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

    2012-12-11

    We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

  19. The front-end chip of the SuperB SVT detector

    Science.gov (United States)

    Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.; Ganaway, F.; Cenci, R.; Bombelli, L.; Citterio, M.; Coelli, S.; Fiorini, C.; Liberali, V.; Monti, M.; Nasri, B.; Neri, N.; Palombo, F.; Stabile, A.; Balestri, G.; Batignani, G.; Bernardelli, A.; Bettarini, S.; Bosi, F.; Casarosa, G.; Ceccanti, M.; Forti, F.; Giorgi, M. A.; Lusiani, A.; Mammini, P.; Morsani, F.; Oberhof, B.; Paoloni, E.; Perez, A.; Petragnani, G.; Profeti, A.; Rizzo, G.; Soldani, A.; Walsh, J.; Gaioni, L.; Manazza, A.; Quartieri, E.; Ratti, L.; Zucca, S.; Dalla Betta, G.-F.; Fontana, G.; Pancheri, L.; Povoli, M.; Verzellesi, G.; Bosisio, L.; Lanceri, L.; Rashevskaya, I.; Stella, C.; Vitale, L.

    2013-08-01

    The asymmetric e+e- collider SuperB is designed to deliver a high luminosity, greater than 1036cm-2s-1, with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%.

  20. Scintillation counter and wire chamber front end modules for high energy physics experiments

    International Nuclear Information System (INIS)

    Baldin, Boris; DalMonte, Lou

    2011-01-01

    This document describes two front-end modules developed for the proposed MIPP upgrade (P-960) experiment at Fermilab. The scintillation counter module was developed for the Plastic Ball detector time and charge measurements. The module has eight LEMO 00 input connectors terminated with 50 ohms and accepts negative photomultiplier signals in the range 0.25...1000 pC with the maximum input voltage of 4.0 V. Each input has a passive splitter with integration and differentiation times of ∼20 ns. The integrated portion of the signal is digitized at 26.55 MHz by Analog Devices AD9229 12-bit pipelined 4-channel ADC. The differentiated signal is discriminated for time measurement and sent to one of the four TMC304 inputs. The 4-channel TMC304 chip allows high precision time measurement of rising and falling edges with ∼100 ps resolution and has internal digital pipeline. The ADC data is also pipelined which allows deadtime-less operation with trigger decision times of ∼4 (micro)s. The wire chamber module was developed for MIPP EMCal detector charge measurements. The 32-channel digitizer accepts differential analog signals from four 8-channel integrating wire amplifiers. The connection between wire amplifier and digitizer is provided via 26-wire twist-n-flat cable. The wire amplifier integrates input wire current and has sensitivity of 275 mV/pC and the noise level of ∼0.013 pC. The digitizer uses the same 12-bit AD9229 ADC chip as the scintillator counter module. The wire amplifier has a built-in test pulser with a mask register to provide testing of the individual channels. Both modules are implemented as a 6Ux220 mm VME size board with 48-pin power connector. A custom europack (VME) 21-slot crate is developed for housing these front-end modules.

  1. Dual stage beamforming in the absence of front-end receive focusing

    Science.gov (United States)

    Bera, Deep; Bosch, Johan G.; Verweij, Martin D.; de Jong, Nico; Vos, Hendrik J.

    2017-08-01

    Ultrasound front-end receive designs for miniature, wireless, and/or matrix transducers can be simplified considerably by direct-element summation in receive. In this paper we develop a dual-stage beamforming technique that is able to produce a high-quality image from scanlines that are produced with focused transmit, and simple summation in receive (no delays). We call this non-delayed sequential beamforming (NDSB). In the first stage, low-resolution RF scanlines are formed by simple summation of element signals from a running sub-aperture. In the second stage, delay-and-sum beamforming is performed in which the delays are calculated considering the transmit focal points as virtual sources emitting spherical waves, and the sub-apertures as large unfocused receive elements. The NDSB method is validated with simulations in Field II. For experimental validation, RF channel data were acquired with a commercial research scanner using a 5 MHz linear array, and were subsequently processed offline. For NDSB, good average lateral resolution (0.99 mm) and low grating lobe levels (spread function was on average 20% smaller than that of DRF except for at depths  <30 mm and 10% larger than SASB considering all the depths. NDSB showed only a minor degradation in contrast-to-noise ratio and contrast ratio compared to DRF and SASB when measured on an anechoic cyst embedded in a tissue-mimicking phantom. In conclusion, using simple receive electronics front-end, NDSB can attain an image quality better than DRF and slightly inferior to SASB.

  2. The Virtual Learning Commons: Supporting the Fuzzy Front End of Scientific Research with Emerging Technologies

    Science.gov (United States)

    Pennington, D. D.; Gandara, A.; Gris, I.

    2012-12-01

    The Virtual Learning Commons (VLC), funded by the National Science Foundation Office of Cyberinfrastructure CI-Team Program, is a combination of Semantic Web, mash up, and social networking tools that supports knowledge sharing and innovation across scientific disciplines in research and education communities and networks. The explosion of scientific resources (data, models, algorithms, tools, and cyberinfrastructure) challenges the ability of researchers to be aware of resources that might benefit them. Even when aware, it can be difficult to understand enough about those resources to become potential adopters or re-users. Often scientific data and emerging technologies have little documentation, especially about the context of their use. The VLC tackles this challenge by providing mechanisms for individuals and groups of researchers to organize Web resources into virtual collections, and engage each other around those collections in order to a) learn about potentially relevant resources that are available; b) design research that leverages those resources; and c) develop initial work plans. The VLC aims to support the "fuzzy front end" of innovation, where novel ideas emerge and there is the greatest potential for impact on research design. It is during the fuzzy front end that conceptual collisions across disciplines and exposure to diverse perspectives provide opportunity for creative thinking that can lead to inventive outcomes. The VLC integrates Semantic Web functionality for structuring distributed information, mash up functionality for retrieving and displaying information, and social media for discussing/rating information. We are working to provide three views of information that support researchers in different ways: 1. Innovation Marketplace: supports users as they try to understand what research is being conducted, who is conducting it, where they are located, and who they collaborate with; 2. Conceptual Mapper: supports users as they organize their

  3. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays

    OpenAIRE

    Çiçek, İhsan; Cicek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-01-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMU...

  4. Hardware Architecture of Polyphase Filter Banks Performing Embedded Resampling for Software-Defined Radio Front-Ends

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Le Moullec, Yannick; Koch, Peter

    2012-01-01

    In this paper, we describe resource-efficient hardware architectures for software-defined radio (SDR) front-ends. These architectures are made efficient by using a polyphase channelizer that performs arbitrary sample rate changes, frequency selection, and bandwidth control. We discuss area, time...... for maximally decimated, under-decimated, over-decimated, and combined up- and down-sampled scenarios is used as a case study, and an analysis of area, time, and power for their FPGA architectures is given. For resource-optimized SDR front-ends, RA is superior for reducing operating clock rates and dynamic...

  5. A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Document Server

    Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

  6. LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

    CERN Multimedia

    Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

    2014-01-01

    The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

  7. Utilizing a Novel Approach at the Fuzzy Front-End of New Product Development: A Case Study in a Flexible Fabric Supercapacitor

    Directory of Open Access Journals (Sweden)

    Gwo-Tsuen Jou

    2016-08-01

    Full Text Available The fuzzy front-end plays a most crucial part in new product development (NPD, leading to the success of product development and product launch in the market. This study proposes a novel method, TTRI_MP, by combining Crawford and Di Benedetto’s model and Cooper’s model, to strengthen the management of the fuzzy front-end. The proposed method comprises four stages: market exploration and technology forecasting, idea generation and segmentation, portfolio analysis and technology roadmapping (TRM. In the first stage, SWOT was utilized to identify the key strategic areas, and the technology readiness level (TRL was adopted to position the level of developed technologies. In the second stage, the business concepts were required to go through the viability test and customers, collaborators, competitors and company (4C. In the third stage, the Strategic Position Analysis (SPAN and Financial Analysis (FAN developed by IBM were employed in the portfolio analysis to screen out potential NPD projects. In the last stage, the selected NPD projects were linked with their functions and technologies in the TRM chart. The method was successfully implemented by a research team working on a flexible fabric supercapacitor at the Taiwan Textile Research Institute (TTRI.

  8. Radiation tolerant optical links for the readout of the ATLAS experiment

    CERN Document Server

    Pearce, M

    2000-01-01

    The ATLAS experiment will use radiation tolerant optical links to transfer data to and from sub-detector systems. The link specifications can be broadly divided into two classes, represented by the inner tracking detectors and the electromagnetic calorimeter. A feature common to all the readout links is the use of vertical cavity surface emitting laser diodes coupled to multimode optical fibres. Results from the development for both of these environments are reviewed with particular attention bring paid to irradiation studies. (8 refs).

  9. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  10. A novel pseudo resistor structure for biomedical front-end amplifiers.

    Science.gov (United States)

    Yu-Chieh Huang; Tzu-Sen Yang; Shun-Hsi Hsu; Xin-Zhuang Chen; Jin-Chern Chiou

    2015-08-01

    This study proposes a novel pseudo resistor structure with a tunable DC bias voltage for biomedical front-end amplifiers (FEAs). In the proposed FEA, the high-pass filter composed of differential difference amplifier and a pseudo resistor is implemented. The FEA is manufactured by using a standard TSMC 0.35 μm CMOS process. In this study, three types FEAs included three different pseudo resistor are simulated, fabricated and measured for comparison and electrocorticography (ECoG) measurement, and all the results show the proposed pseudo resistor is superior to other two types in bandwidth. In chip implementation, the lower and upper cutoff frequencies of the high-pass filter with the proposed pseudo resistor are 0.15 Hz and 4.98 KHz, respectively. It also demonstrates lower total harmonic distortion performance of -58 dB at 1 kHz and higher stability with wide supply range (1.8 V and 3.3 V) and control voltage range (0.9 V and 1.65 V) than others. Moreover, the FEA with the proposed pseudo successfully recorded spike-and-wave discharges of ECoG signal in in vivo experiment on rat with pentylenetetrazol-induced seizures.

  11. CMOS Receiver Front-ends for Gigabit Short-Range Optical Communications

    CERN Document Server

    Aznar, Francisco; Calvo Lopez, Belén

    2013-01-01

    This book describes optical receiver solutions integrated in standard CMOS technology, attaining high-speed short-range transmission within cost-effective constraints.  These techniques support short reach applications, such as local area networks, fiber-to-the-home and multimedia systems in cars and homes. The authors show how to implement the optical front-end in the same technology as the subsequent digital circuitry, leading to integration of the entire receiver system in the same chip.  The presentation focuses on CMOS receiver design targeting gigabit transmission along a low-cost, standardized plastic optical fiber up to 50m in length.  This book includes a detailed study of CMOS optical receiver design – from building blocks to the system level. Reviews optical communications, including long-haul transmission systems and emerging applications focused on short-range; Explains necessary fundamentals, such as characteristics of a data signal, system requirements affecting receiver design and key par...

  12. Photodetectors and front-end electronics for the LHCb RICH upgrade

    Science.gov (United States)

    Cassina, L.; LHCb RICH

    2017-12-01

    The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

  13. Replacing PS controls front end minicomputers by VME based 32-bit processors

    International Nuclear Information System (INIS)

    Gagnaire, A.; Metz Noblat, N. de; Serre, Ch.; Sicard, Cl.H.

    1992-01-01

    The PS controls have started the first phase of system rejuvenation, targeted towards the LEP Preinjector Controls. The main impact of this phase is in the architectural change, as both the front-end minicomputers and the CAMAC embedded microprocessors are replaced by microprocessor based VME crates called Device Stub Controllers (DSC). This paper discusses the different steps planned for this first phase, i.e: (1) implementing the basic set of CERN Accelerator common facilities for DSCs (error handling, system surveillance, remote boot and network access); (2) porting the equipment access software layer; (3) applying the Real-time tasks to the LynxOS operating system and I/O architecture, conforming to the real-time constraints for control and acquisition; (4) defining the number and contents of the different DSC needed, according to geographical and cpu-load constraints; (5) providing the general services outside the DSC crates (file servers, data-base services); (6) emulating the current Console programs onto the new workstations. (author)

  14. A multichannel front end ASIC for PMT readout in LHAASO WCDA

    Science.gov (United States)

    Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

    2018-01-01

    Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

  15. Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

    Science.gov (United States)

    Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

    2012-07-01

    There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

  16. Dynamic testing for radiation induced failures in a standard CMOS submicron technology pixel front-end

    International Nuclear Information System (INIS)

    Venuto, D. de; Corsi, F.; Ohletz, M.J.

    1999-01-01

    A testing method for the detection of performance degradation induced by high-dose irradiation in high-energy experiments has been developed. The method used is based on a fault signature generation defined on the basis of the state-space analysis for linear circuits. By sampling the response of the circuit under test (CUT) to a single rectangular pulse, a set of parameters α are evaluated which are functions of the circuit singularities and constitute a signature for the CUT. Amplitude perturbations of these parameters engendered by element drift failure indicate a possible faulty condition. The effects of radiation induced faults in the analogue CMOS front-end of a silicon pixel detector employed in high energy physics experiments has been investigated. The results show that, even for the 800 krad dose, the test devised is able to detect the degradation of the amplifier performances. The results show also that hardened devices do not necessarily produce high circuit immunity to radiation and the proposed test method provides a mean to detect these performance deviations and to monitor them during the operating life of the chip. (A.C.)

  17. Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

    Energy Technology Data Exchange (ETDEWEB)

    Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

    2015-09-21

    In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

  18. Continuous-time digital front-ends for multistandard wireless transmission

    CERN Document Server

    Nuyts, Pieter A J; Dehaene, Wim

    2014-01-01

    This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components.  After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware.  As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling.  The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality.  Next, a high-level theoretical analysis of two different PWM-based architectures – baseband PWM and RF PWM – is made.  On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits.  Important design criteria are identified and diff...

  19. A low power low noise analog front end for portable healthcare system

    Science.gov (United States)

    Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

    2015-10-01

    The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

  20. Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

    CERN Document Server

    Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

    1997-01-01

    We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

  1. A low power, low noise Programmable Analog Front End (PAFE) for biopotential measurements.

    Science.gov (United States)

    Adimulam, Mahesh Kumar; Divya, A; Tejaswi, K; Srinivas, M B

    2017-07-01

    A low power Programmable Analog Front End (PAFE) for biopotential measurements is presented in this paper. The PAFE circuit processes electrocardiogram (ECG), electromyography (EMG) and electroencephalogram (EEG) signals with higher accuracy. It consists mainly of improved transconductance programmable gain instrumentational amplifier (PGIA), programmable high pass filter (PHPF), and second order low pass filter (SLPF). A 15-bit programmable 5-stage successive approximation analog-to-digital converter (SAR-ADC) is implemented for improving the performance, whose power consumption is reduced due to multiple stages and by OTA/Comparator sharing technique between the stages. The power consumption is further reduced by operating the analog portion of PAFE on 0.5V supply voltage and digital portion on 0.3V supply voltage generated internally through a voltage regulator. The proposed low power PAFE has been fabricated in 180nm standard CMOS process. The performance parameters of PAFE in 15-bit mode are found to be, gain of 31-70 dB, input referred noise of 1.15 μVrms, CMRR of 110 dB, PSRR of 104 dB, and signal-to-noise distortion ratio (SNDR) of 83.5dB. The power consumption of the design is 1.1 μW @ 0.5 V supply voltage and it occupies a core silicon area of 1.2 mm 2 .

  2. A low-power high-sensitivity analog front-end for PPG sensor.

    Science.gov (United States)

    Binghui Lin; Atef, Mohamed; Guoxing Wang

    2017-07-01

    This paper presents a low-power analog front-end (AFE) photoplethysmography (PPG) sensor fabricated in 0.35 μm CMOS process. The AFE amplifies the weak photocurrent from the photodiode (PD) and converts it to a strong voltage at the output. In order to decrease the power consumption, the circuits are designed in subthreshold region; so the total biasing current of the AFE is 10 μ A. Since the large input DC photocurrent is a big issue for the PPG sensing circuit, we apply a DC photocurrent rejection technique by adding a DC current-cancellation loop to reject the large DC photocurrent up to 10 μA. In addition, a pseudo resistor is used to reduce the high-pass corner frequency below 0.5 Hz and Gm-C filter is adapted to reject the out-of-band noise higher than 16 Hz. For the whole sensor, the amplifier chain can achieve a total gain of 140 dBμ and an input integrated noise current of 68.87 pA rms up to 16 Hz.

  3. AFTER, the front end ASIC of the T2K Time Projection Chambers

    CERN Document Server

    Baron, P; Calvet, D; de la Broise, X; Delagnes, E; Delbart, A; Druillole, F; Le Coguie, A; Mazzucato, E; Monmarthe, E; Zito, M

    2009-01-01

    The T2K (Tokai-to-Kamioka) experiment is a long baseline neutrino oscillation experiment in Japan. A near detector, located at 280m of the production target, is used to characterize the beam. One of its key elements is a tracker, made of three Time Projection Chambers (TPC) read by Micromegas endplates. A new readout system has been developed to collect, amplify, condition and acquire the data produced by the 124,000 detector channels of these detectors. The front-end element of this system is a a new 72-channel application specific integrated circuit. Each channel includes a low noise charge preamplifier, a pole zero compensation stage, a second order Sallen-Key low pass filter and a 511-cell Switched Capacitor Array. This electronics offers a large flexibility in sampling frequency, shaping time, gain, while taking advantage of the low physics events rate of 0.3 Hz. We detail the design and the performance of this ASIC and report on the deployment of the frond-end electronics on-site.

  4. The PreProcessors for the ATLAS Tile Calorimeter Phase II Upgrade

    CERN Document Server

    AUTHOR|(SzGeCERN)713745; The ATLAS collaboration; Castillo, V.; Cerda, L.; Ferrer, A.; Fiorini, L.; Hernandez, Y.; Higon, E.; Moreno, P.; Solans, C.; Valero, A.; Valls, J.A.

    2016-01-01

    The Large Hadron Collider (LHC) has envisaged a series of upgrades towards a High Luminosity LHC (HL-LHC) delivering five times the LHC nominal instantaneous luminosity. The ATLAS Phase II upgrade will accommodate the detector and data acquisition system for the HL-LHC. In particular, the Tile Hadronic Calorimeter (TileCal) will replace completely front-end and back-end electronics using a new readout architecture. The digitized detector data will be transferred for every beam crossing to the PreProcessors (TilePPr) located in off-detector counting rooms with a total data bandwidth of roughly 80 Tbps. The TilePPr implements increased pipelines memories and must provide pre-processed digital trigger information to Level 0 trigger systems. The TilePPr system represents the link between the front-end electronics and the overall ATLAS data acquisition system. It also implements the interface between the Detector Control System (DCS) and the front-end electronics which is used to control and monitor the high volta...

  5. High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

    Science.gov (United States)

    Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

    2010-01-01

    In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

  6. Interfirm collaboration in the fuzzy front-end of the innovation process - Exploring new forms of collaboration

    DEFF Research Database (Denmark)

    Bergenholtz, Carsten; Jørgensen, Jacob Høj; Goduscheit, Rene Chester

    The objective of this paper is to elaborate on the differentiating characteristics between intra-firm and inter-firm innovation projects in the Fuzzy Front-End (FFE) of the innovation process. Focus is on management methods of the collaboration and the CEO-commitment to the project. The main poin...

  7. Workshop on physics at the first muon collider and front-end of a muon collider: A brief summary

    International Nuclear Information System (INIS)

    Geer, S.

    1998-01-01

    In November 1997 a workshop was held at Fermilab to explore the physics potential of the first muon collider, and the physics potential of the accelerator complex at the 'front-end' of the collider. An extensive physics program emerged from the workshop. This paper attempts to summarize this physics program and identify the main conclusions from the workshop

  8. Influence Of Tools Input/Output Requirements On Managers Core Front End Activities In New Product Development

    DEFF Research Database (Denmark)

    Appio, Francesco P.; Achiche, Sofiane; Minin, Alberto Di

    2011-01-01

    The object of analysis of this explorative research is the Fuzzy Front End of Innovation in Product Development, described by those activities going from the opportunity identification to the concept definition. Business scholars have shown that confusion in terms of goals and different ideas abo...

  9. Play it forward : A Game-based tool for Sustainable Product and Business Model Innovation in the Fuzzy Front End

    NARCIS (Netherlands)

    Dewulf, K.R.

    2010-01-01

    Dealing with sustainability in the fuzzy front end of innovation is complex and often hard. There are a number of tools available to guide designers, engineers and managers in the design process after the specifications of the product or service are already set, but methods supporting goal finding

  10. A front-end wafer-level microsystem packaging technique with micro-cap array

    Science.gov (United States)

    Chiang, Yuh-Min

    2002-09-01

    The back-end packaging process is the remaining challenge for the micromachining industry to commercialize microsystem technology (MST) devices at low cost. This dissertation presents a novel wafer level protection technique as a final step of the front-end fabrication process for MSTs. It facilitates improved manufacturing throughput and automation in package assembly, wafer level testing of devices, and enhanced device performance. The method involves the use of a wafer-sized micro-cap array, which consists of an assortment of small caps micro-molded onto a material with adjustable shapes and sizes to serve as protective structures against the hostile environments during packaging. The micro-cap array is first constructed by a micromachining process with micro-molding technique, then sealed to the device wafer at wafer level. Epoxy-based wafer-level micro cap array has been successfully fabricated and showed good compatibility with conventional back-end packaging processes. An adhesive transfer technique was demonstrated to seal the micro cap array with a MEMS device wafer. No damage or gross leak was observed while wafer dicing or later during a gross leak test. Applications of the micro cap array are demonstrated on MEMS, microactuators fabricated using CRONOS MUMPS process. Depending on the application needs, the micro-molded cap can be designed and modified to facilitate additional component functions, such as optical, electrical, mechanical, and chemical functions, which are not easily achieved in the device by traditional means. Successful fabrication of a micro cap array comprised with microlenses can provide active functions as well as passive protection. An optical tweezer array could be one possibility for applications of a micro cap with microlenses. The micro cap itself could serve as micro well for DNA or bacteria amplification as well.

  11. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-01-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  12. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-12-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  13. Integration of 2D CMUT arrays with front-end electronics for volumetric ultrasound imaging.

    Science.gov (United States)

    Wygant, Ira O; Zhuang, Xuefeng; Yeh, David T; Oralkan, Omer; Sanli Ergun, A; Karaman, Mustafa; Khuri-Yakub, Butrus T

    2008-02-01

    For three-dimensional (3D) ultrasound imaging, connecting elements of a two-dimensional (2D) transducer array to the imaging system's front-end electronics is a challenge because of the large number of array elements and the small element size. To compactly connect the transducer array with electronics, we flip-chip bond a 2D 16 x 16-element capacitive micromachined ultrasonic transducer (CMUT) array to a custom-designed integrated circuit (IC). Through-wafer interconnects are used to connect the CMUT elements on the top side of the array with flip-chip bond pads on the back side. The IC provides a 25-V pulser and a transimpedance preamplifier to each element of the array. For each of three characterized devices, the element yield is excellent (99 to 100% of the elements are functional). Center frequencies range from 2.6 MHz to 5.1 MHz. For pulse echo operation, the average - 6-dB fractional bandwidth is as high as 125%. Transmit pressures normalized to the face of the transducer are as high as 339 kPa and input-referred receiver noise is typically 1.2 to 2.1 mPa/pHz. The flip-chip bonded devices were used to acquire 3D synthetic aperture images of a wire-target phantom. Combining the transducer array and IC, as shown in this paper, allows for better utilization of large arrays, improves receive sensitivity, and may lead to new imaging techniques that depend on transducer arrays that are closely coupled to IC electronics.

  14. The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

    Science.gov (United States)

    Noy, M.; Aglieri Rinella, G.; Ceccucci, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Mazza, G.; Martoiu, S.; Morel, M.; Perktold, L.; Rivetti, A.; Tiuraniemi, S.

    2011-06-01

    The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16 cm active area made of an assembly of 10 readout ASICs bump bonded to a 200 μm thick pixel silicon sensor, comprising 18000 pixels of 300 μm×300 μm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5 Mhit s mm together with an extreme time resolution of 100 ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4 ns, with a planar silicon sensor operating up to 300 V over depletion. Moreover, the radiation level is severe, 2×10 1 MeV n cm per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130 nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

  15. Wireless front-end with power management for an implantable cardiac microstimulator.

    Science.gov (United States)

    Lee, Shuenn-Yuh; Hsieh, Cheng-Han; Yang, Chung-Min

    2012-02-01

    Inductive coupling is presented with the help of a high-efficiency Class-E power amplifier for an implantable cardiac microstimulator. The external coil inductively transmits power and data with a carrier frequency of 256 kHz into the internal coil of electronic devices inside the body. The detected cardiac signal is fed back to the external device with the same pair of coils to save on space in the telemetry device. To maintain the power reliability of the microstimulator for long-term use, two small rechargeable batteries are employed to supply voltage to the internal circuits. The power management unit, which includes radio frequency front-end circuits with battery charging and detection functions, is used for the supply control. For cardiac stimulation, a high-efficiency charge pump is also proposed in the present paper to generate a stimulated voltage of 3.2 V under a 1 V supply voltage. A phase-locked-loop (PLL)-based phase shift keying demodulator is implemented to efficiently extract the data and clock from an inductive AC signal. The circuits, with an area of 0.45 mm², are implemented in a TSMC 0.35 μm 2P4M standard CMOS process. Measurement results reveal that power can be extracted from the inductive coupling and stored in rechargeable batteries, which are controlled by the power management unit, when one of the batteries is drained. Moreover, the data and clock can be precisely recovered from the coil coupling, and a stimulated voltage of 3.2 V can be readily generated by the proposed charge-pump circuits to stimulate cardiac tissues.

  16. Custom single-photon avalanche diode with integrated front-end for parallel photon timing applications

    Science.gov (United States)

    Cammi, C.; Panzeri, F.; Gulinatti, A.; Rech, I.; Ghioni, M.

    2012-03-01

    Emerged as a solid state alternative to photo multiplier tubes (PMTs), single-photon avalanche diodes (SPADs) are nowadays widely used in the field of single-photon timing applications. Custom technology SPADs assure remarkable performance, in particular a 10 counts/s dark count rate (DCR) at low temperature, a high photon detection efficiency (PDE) with a 50% peak at 550 nm and a 30 ps (full width at half maximum, FWHM) temporal resolution, even with large area devices, have been obtained. Over the past few years, the birth of novel techniques of analysis has led to the parallelization of the measurement systems and to a consequent increasing demand for the development of monolithic arrays of detectors. Unfortunately, the implementation of a multidimensional system is a challenging task from the electrical point of view; in particular, the avalanche current pick-up circuit, used to obtain the previously reported performance, has to be modified in order to enable high parallel temporal resolution, while minimizing the electrical crosstalk probability between channels. In the past, the problem has been solved by integrating the front-end electronics next to the photodetector, in order to reduce the parasitic capacitances and consequently the filtering action on the current signal of the SPAD, leading to an improvement of the timing jitter at higher threshold. This solution has been implemented by using standard complementary metal-oxide-semiconductor (CMOS) technologies, which, however, do not allow a complete control on the SPAD structure; for this reason the intrinsic performance of CMOS SPADs, such as DCR, PDE, and afterpulsing probability, are worse than those attainable with custom detectors. In this paper, we propose a pixel architecture, which enables the development of custom SPAD arrays in which every channel maintains the performance of the best single photodetector. The system relies on the integration of the timing signal pick-up circuit next to the

  17. Level-1 Data Driver Card of the ATLAS New Small Wheel Upgrade Compatible with the Phase II 1 MHz Readout

    CERN Document Server

    Gkountoumis, Panagiotis; The ATLAS collaboration

    2016-01-01

    The Level-1 Data Driver Card (L1DDC) will be designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 data along with monitoring data and transmits them to a network interface through a single bidirectional fiber link. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach 1 MHz. This paper describes the overall scheme of the data acquisition process and especially the L1DDC board. Finally, the electronics layout on the chamber is also mentioned

  18. A −3 dBm RF transmitter front-end for 802.11g application

    International Nuclear Information System (INIS)

    Zhao Jinxin; Yan Jun; Shi Yin

    2013-01-01

    A 2.4 GHz, direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals. The front-end output power is −3 dBm while the corresponding EVM is −27 dB which is necessary for the 802.11g standard of EVM at −25 dB. With the adopted gain control strategy the output power changes from −14.3 to −3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process. A power detector indicates the output power and delivers a voltage to the baseband to control the output power. (semiconductor integrated circuits)

  19. Development of a data management front-end for use with a LANDSAT-based information system

    Science.gov (United States)

    Turner, B. J.

    1982-01-01

    The development and implementation of a data management front-end system for use with a LANDSAT based information system that facilitates the processsing of both LANDSAT and ancillary data was examined. The final tasks, reported on here, involved; (1) the implementation of the VICAR image processing software system at Penn State and the development of a user-friendly front-end for this system; (2) the implementation of JPL-developed software based on VICAR, for mosaicking LANDSAT scenes; (3) the creation and storage of a mosiac of 1981 summer LANDSAT data for the entire state of Pennsylvania; (4) demonstrations of the defoliation assessment procedure for Perry and Centre Counties, and presentation of the results at the 1982 National Gypsy Moth Review Meeting, and (5) the training of Pennsylvania Bureau of Forestry personnel in the use of the defoliation analysis system.

  20. One size does not fit all - understanding the front-end and back-ens of business model innovation

    DEFF Research Database (Denmark)

    Günzel, Franziska; Holm, Anna B.

    2013-01-01

    production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance......Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed...... understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...

  1. Coupling Front-End Separations, Ion Mobility Spectrometry, and Mass Spectrometry For Enhanced Multidimensional Biological and Environmental Analyses

    Science.gov (United States)

    Zheng, Xueyun; Wojcik, Roza; Zhang, Xing; Ibrahim, Yehia M.; Burnum-Johnson, Kristin E.; Orton, Daniel J.; Monroe, Matthew E.; Moore, Ronald J.; Smith, Richard D.; Baker, Erin S.

    2017-01-01

    Ion mobility spectrometry (IMS) is a widely used analytical technique for rapid molecular separations in the gas phase. Though IMS alone is useful, its coupling with mass spectrometry (MS) and front-end separations is extremely beneficial for increasing measurement sensitivity, peak capacity of complex mixtures, and the scope of molecular information available from biological and environmental sample analyses. In fact, multiple disease screening and environmental evaluations have illustrated that the IMS-based multidimensional separations extract information that cannot be acquired with each technique individually. This review highlights three-dimensional separations using IMS-MS in conjunction with a range of front-end techniques, such as gas chromatography, supercritical fluid chromatography, liquid chromatography, solid-phase extractions, capillary electrophoresis, field asymmetric ion mobility spectrometry, and microfluidic devices. The origination, current state, various applications, and future capabilities of these multidimensional approaches are described in detail to provide insight into their uses and benefits. PMID:28301728

  2. Coupling Front-End Separations, Ion Mobility Spectrometry, and Mass Spectrometry For Enhanced Multidimensional Biological and Environmental Analyses

    Energy Technology Data Exchange (ETDEWEB)

    Zheng, Xueyun; Wojcik, Roza; Zhang, Xing; Ibrahim, Yehia M.; Burnum-Johnson, Kristin E.; Orton, Daniel J.; Monroe, Matthew E.; Moore, Ronald J.; Smith, Richard D.; Baker, Erin M.

    2017-06-12

    Ion mobility spectrometry (IMS) is a widely used analytical technique for rapid molecular separations in the gas phase. IMS alone is useful, but its coupling with mass spectrometry (MS) and front-end separations has been extremely beneficial for increasing measurement sensitivity, peak capacity of complex mixtures, and the scope of molecular information in biological and environmental sample analyses. Multiple studies in disease screening and environmental evaluations have even shown these IMS-based multidimensional separations extract information not possible with each technique individually. This review highlights 3-dimensional separations using IMS-MS in conjunction with a range of front-end techniques, such as gas chromatography (GC), supercritical fluid chromatography (SFC), liquid chromatography (LC), solid phase extractions (SPE), capillary electrophoresis (CE), field asymmetric ion mobility spectrometry (FAIMS), and microfluidic devices. The origination, current state, various applications, and future capabilities for these multidimensional approaches are described to provide insight into the utility and potential of each technique.

  3. A 7-13 GHz low-noise tuned optical front-end amplifier for heterodyne transmission system application

    DEFF Research Database (Denmark)

    Ebskamp, Frank; Schiellerup, Gert; Høgdal, Morten

    1991-01-01

    The authors present a 7-13 GHz low-noise bandpass tuned optical front-end amplifier, showing 46±1 dBΩ transimpedance, and a noise spectral density of about 12 pA/√Hz. This is the first time such a flat response and such low noise were obtained simultaneously at these frequencies, without any...... further equalization. A new lay-out technique enabled close monitoring of each manufacturing step, and excellent agreement between the measurements and simulations was observed. The front-end was used in an optical 2.5 Gb/s coherent CPFSK continuous phase frequency shift keying system experiment......, resulting in a sensitivity of -41.7 dBm at a bit error rate of 10-9...

  4. Redesign and Reconstruction of the Equipment Protection Systems for the Upgrading Front Ends and Beamlines at BSRF

    International Nuclear Information System (INIS)

    Xiong Shenshou; Tan Yinglei; Wu Xuehui

    2007-01-01

    The BEPC(Beijing Electron-Positron Collider) is upgraded to be BEPCII, a two-ring Electron-Positron collider. Due to the construction of the BEPCII and upgrade of the existing front ends and beamlines, all the existing EPSs(Equipment Protection Systems) have to be redesigned and reconstructed at BSRF. All the redesigned EPSs for the upgrading front ends and beamlines are a PLC- and SCADA-based equipment protection and control and monitoring system. The EPSs are used to protect BEPCII two storage rings vacuum against vacuum failures in a beamline, as well as to protect the front-end and beamline components from being damaged by synchrotron radiation. For the high-power wiggler beam lines, a fast movable mask is used to protect the blade of a fast-closing valve from damage when the fast-closing valve is triggered to close, which does not need to dump the electron beam running in BEPCII outer ring. In addition, all redesigned PLC- based EPSs are used to communicate with the same centralized monitoring computer to monitor a variety of parameters from all PLC- based EPS systems. The monitoring computer runs the SCADA (Supervisory Control And Data Acquisition) software with its own web server. Graphical HMI interfaces are used to display a few overall views of all front-end equipment operation status and the further detailed information for each EPS in a different pop-up window. On the web services, the SCADA-based centralized monitoring system provides a web browse function, etc. The design of the reconstructed systems is described in this paper

  5. Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications

    Directory of Open Access Journals (Sweden)

    Munir M. El-Desouki

    2015-05-01

    Full Text Available The demand for radio frequency (RF transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN.

  6. Toward Realization of 2.4 GHz Balunless Narrowband Receiver Front-End for Short Range Wireless Applications.

    Science.gov (United States)

    El-Desouki, Munir M; Qasim, Syed Manzoor; BenSaleh, Mohammed S; Deen, M Jamal

    2015-05-07

    The demand for radio frequency (RF) transceivers operating at 2.4 GHz band has attracted considerable research interest due to the advancement in short range wireless technologies. The performance of RF transceivers depends heavily on the transmitter and receiver front-ends. The receiver front-end is comprised of a low-noise amplifier (LNA) and a downconversion mixer. There are very few designs that focus on connecting the single-ended output LNA to a double-balanced mixer without the use of on-chip transformer, also known as a balun. The objective of designing such a receiver front-end is to achieve high integration and low power consumption. To meet these requirements, we present the design of fully-integrated 2.4 GHz receiver front-end, consisting of a narrow-band LNA and a double balanced mixer without using a balun. Here, the single-ended RF output signal of the LNA is translated into differential signal using an NMOS-PMOS (n-channel metal-oxide-semiconductor, p-channel metal-oxide-semiconductor) transistor differential pair instead of the conventional NMOS-NMOS transistor configuration, for the RF amplification stage of the double-balanced mixer. The proposed receiver circuit fabricated using TSMC 0.18 µm CMOS technology operates at 2.4 GHz and produces an output signal at 300 MHz. The fabricated receiver achieves a gain of 16.3 dB and consumes only 6.74 mW operating at 1.5 V, while utilizing 2.08 mm2 of chip area. Measurement results demonstrate the effectiveness and suitability of the proposed receiver for short-range wireless applications, such as in wireless sensor network (WSN).

  7. Design, development, and verification of the Planck low frequency instrument 70 GHz front-end and back-end modules

    OpenAIRE

    J. Varis, N..J..H.; Laaninen, M.; Kilpiä, V..H.; Jukkala, P.; Tuovinen, J.; Ovaska, S.; Sjöman, P.; Kangaslahti, P.; Gaier, T.; Hoyland, R.; Meinhold, P.; Mennella, A.; Bersanelli, M.; Butler, R..C.; Cuttaia, F.

    2009-01-01

    70 GHz radiometer front-end and back-end modules for the Low Frequency Instrument of the European Space Agencys Planck Mission were built and tested. The operating principles and the design details of the mechanical structures are described along with the key InP MMIC low noise amplifiers and phase switches of the units. The units were tested in specially designed cryogenic vacuum chambers capable of producing the operating conditions required for Planck radiometers, specifically, a physical ...

  8. Recent advancements of chemical engineering in front end fuel cycle technologies at NFC. Contributed Paper IT-01

    International Nuclear Information System (INIS)

    Saibaba, N.

    2014-01-01

    On front end fuel cycle side, Nuclear Fuel Complex (NFC) has been a pioneer in processing the uranium and zirconium ore concentrates from different sources. The uranium and zirconium ore concentrates are converted into nuclear grade uranium and zirconium di oxide powders through the conventional TBP purification and precipitation route. In case of zirconium powders, they are converted into pure nuclear grade zirconium sponge through chlorination route for the production of zirconium alloys, which are mainly used as reactor core structural material

  9. A fully integrated, low noise and low power BiCMOS front-end readout system for capacitive detectors

    CERN Document Server

    Guo, C C; Deptuch, G; Hu, Y Y

    2001-01-01

    Bipolar transistors are interesting for low noise front-end readout systems when high speed and low power consumption are required. This paper presents a fully integrated, low noise front-end design for the future Large Hadron Collider (LHC) experiments using the radiation hard SOI BiCMOS process. In the present prototype, the input-referred Equivalent Noise Charge (ENC) of 990 electrons (r.m.s.) for 12 pF detector capacitance with a shaping time of 25 ns and power consumption of 1.4 mW/channel has been measured. The gain of this front-end is 90 mV/MIP (Minimum Ionisation Particle: 1 MIP=3.84 fC) with non-linearity of less than 3% and linear input dynamic range is +or-5 MIP. These results are obtained at room temperature and before irradiation. The measurements after irradiations by high intensity pion beam with an integrated flux of 1.0*10/sup 14/ pions/cm/sup 2/ are also presented in this paper. (10 refs).

  10. 60-GHz Band Copper Ball Vertical Interconnection for MMW 3-D System-in-Package Front-End Modules

    Science.gov (United States)

    Yoshida, Satoshi; Tanifuji, Shoichi; Kameda, Suguru; Suematsu, Noriharu; Takagi, Tadashi; Tsubouchi, Kazuo

    In order to realize millimeter-wave (MMW) 3-D system-in-package (SiP) front-end modules, we propose a 60-GHz band copper ball vertical interconnection structure, which interconnects between vertically stacked substrates. The structure enables ICs to be placed between the vertically stacked substrates. Since the diameter of the copper balls must exceed the thickness of the ICs, the distance between the substrates in the modules is larger than that of the flip-chip interconnection widely used in the MMW-band. Therefore, the conventional flip-chip interconnection does not scale for the interconnection between the substrates in MMW 3-D SiP front-end modules. The layout of grounded copper balls and the patterns of inner ground layers in the upper/lower substrates are designed using 3-D electromagnetic field simulation. The designed structure allows less than 1dB transmission loss up to 71.1GHz, compared with a through transmission line. The result is verified with fabrication and measurement and confirms the feasibility of MMW 3-D SiP front-end modules.

  11. Neural recording front-end IC using action potential detection and analog buffer with digital delay for data compression.

    Science.gov (United States)

    Liu, Lei; Yao, Lei; Zou, Xiaodan; Goh, Wang Ling; Je, Minkyu

    2013-01-01

    This paper presents a neural recording analog front-end IC intended for simultaneous neural recording with action potential (AP) detection for data compression in wireless multichannel neural implants. The proposed neural recording front-end IC detects the neural spikes and sends only the preserved AP information for wireless transmission in order to reduce the overall power consumption of the neural implant. The IC consists of a low-noise neural amplifier, an AP detection circuit and an analog buffer with digital delay. The neural amplifier makes use of a current-reuse technique to maximize the transconductance efficiency for attaining a good noise efficiency factor. The AP detection circuit uses an adaptive threshold voltage to generate an enable signal for the subsequent functional blocks. The analog buffer with digital delay is employed using a finite impulse response (FIR) filter which preserves the AP waveform before the enable signal as well as provides low-pass filtering. The neural recording front-end IC has been designed using standard CMOS 0.18-µm technology occupying a core area of 220 µm by 820 µm.

  12. Low Noise and Highly Linear Wideband CMOS RF Front-End for DVB-H Direct-Conversion Receiver

    Science.gov (United States)

    Nam, Ilku; Moon, Hyunwon; Woo, Doo Hyung

    In this paper, a wideband CMOS radio frequency (RF) front-end for digital video broadcasting-handheld (DVB-H) receiver is proposed. The RF front-end circuit is composed of a single-ended resistive feedback low noise amplifier (LNA), a single-to-differential amplifier, an I/Q down-conversion mixer with linearized transconductors employing third order intermodulation distortion cancellation, and a divide-by-two circuit with LO buffers. By employing a third order intermodulation (IMD3) cancellation technique and vertical NPN bipolar junction transistor (BJT) switching pair for an I/Q down-conversion mixer, the proposed RF front-end circuit has high linearity and low low-frequency noise performance. It is fabricated in a 0.18µm deep n-well CMOS technology and draws 12mA from a 1.8V supply voltage. It shows a voltage gain of 31dB, a noise figure (NF) lower than 2.6dB, and an IIP3 of -8dBm from 470MHz to 862MHz.

  13. Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

    Science.gov (United States)

    Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

    2016-08-01

    The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

  14. A High-Frequency Isolation (HFI Charging DC Port Combining a Front-End Three-Level Converter with a Back-End LLC Resonant Converter

    Directory of Open Access Journals (Sweden)

    Guowei Cai

    2017-09-01

    Full Text Available The high-frequency isolation (HFI charging DC port can serve as the interface between unipolar/bipolar DC buses and electric vehicles (EVs through the two-power-stage system structure that combines the front-end three-level converter with the back-end logical link control (LLC resonant converter. The DC output voltage can be maintained within the desired voltage range by the front-end converter. The electrical isolation can be realized by the back-end LLC converter, which has the bus converter function. According to the three-level topology, the low-voltage rating power devices can be adapted for half-voltage stress of the total DC grid, and the PWM phase-shift control can double the equivalent switching frequency to greatly reduce the filter volume. LLC resonant converters have advance characteristics of inverter-side zero-voltage-switching (ZVS and rectifier-side zero-current switching (ZCS. In particular, it can achieve better performance under quasi-resonant frequency mode. Additionally, the magnetizing current can be modified following different DC output voltages, which have the self-adaptation ZVS condition for decreasing the circulating current. Here, the principles of the proposed topology are analyzed in detail, and the design conditions of the three-level output filter and high-frequency isolation transformer are explored. Finally, a 20 kW prototype with the 760 V input and 200–500 V output are designed and tested. The experimental results are demonstrated to verify the validity and performance of this charging DC port system structure.

  15. The design of an optical link for the ATLAS Liquid Argon Calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2012-01-01

    We present the design of an optical link for the ATLAS liquid argon calorimeter upgrade. Challenging requirements are high data bandwidth (over 150 Gb/s raw data rate per board), radiation tolerance, low power consumption, high reliability, and low transmission latency. We discuss the link system design and component developments, especially those for the transmitting side that has to operate in the radiation environment. This presentation also serves as a summary of a few other presentations that detail in a particular function block of this link.

  16. Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschätzung des Untergrundes im Zerfall $B^{0}_{s} \\to J\\Psi \\Phi$

    CERN Document Server

    Knopf, Jan

    2009-01-01

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1,6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Phi_s. It can be measured by using the golden decay m...

  17. Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B0s → J/ψ Φ

    International Nuclear Information System (INIS)

    Knopf, Jan

    2009-01-01

    The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Φ s . It can be measured by using the golden decay mode B 0 s → J/ψ Φ. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

  18. Ganga - an Optimiser and Front-End for Grid Job Submission (Demo)

    CERN Document Server

    Maier, A; Egede, U; Elmsheuser, J; Gaidioz, B; Harrison, K; Hurng-Chun Lee; Liko, D; Mosckicki, J; Muraru, A; Romanovsky, V; Soroko, A; Tan, C L; Koblitz, B

    2007-01-01

    The presentation will introduce the Ganga job-management system (http://cern.ch/ganga), developed as an ATLAS/LHCb common project. The main goal of Ganga is to provide a simple and consistent way of preparing, organising and executing analysis tasks, allowing physicists to concentrate on the algorithmic part without having to worry about technical details. Ganga provides a clean Python API that reduces and simplifies the work involved in preparing an application, organizing the submission, and gathering results. Technical details of submitting a job to the Grid, for example the preparation of a job-description file, are factored out and taken care of transparently by the system. By changing the parameter that identifies the execution backend, a user can trivially switch between running an application on a portable PC, running higherstatistics tests on a local batch system, and analysing all available statistics on the Grid. Although Ganga is being developed for LHCb and ATLAS, it is not limited to use with HE...

  19. QIE10: a new front-end custom integrated circuit for high-rate experiments

    International Nuclear Information System (INIS)

    Baumbaugh, A; Monte, L Dal; Freeman, J; Hare, D; Los, S; Shaw, T; Vidal, R; Whitmore, J; Zimmerman, T; Drake, G; Proudfoot, J; Rojas, H Hernandez; Hughes, E; Mendez, D Mendez; Tully, C

    2014-01-01

    We present results on a new version of the QIE (Charge Integrator and Encoder), a custom Application Specific Integrated Circuit (ASIC) designed at Fermilab. Developed specifically for the measurement of charge from photo-detectors in high-rate environments, this most recent addition to the QIE family features 3 fC sensitivity, 17-bits of dynamic range with logarithmic response, a Time-to-Digital Converter (TDC) with sub-nanosecond resolution, and internal charge injection. The device is capable of dead-timeless operation at 40 MHz, making it ideal for calorimetry at the Large hadron Collider (LHC). We present bench measurements and integration studies that characterize the performance, radiation tolerance measurements, and plans for deployment in the Atlas and CMS detectors as part of the Phase 1 and Phase 2 upgrades

  20. Level-1 Data Driver Card of the ATLAS New Small Wheel upgrade compatible with the Phase II 1 MHz readout scheme

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00549793; The ATLAS collaboration

    2016-01-01

    The Level-1 Data Driver Card (L1DDC) will be designed for the needs of the future upgrades of the innermost stations of the ATLAS end-cap muon spectrometer. The L1DDC is a high speed aggregator board capable of communicating with a large number of front-end electronics. It collects the Level-1 data along with monitoring data and transmits them to a network interface through a single bidirectional fiber link. In addition, the L1DDC board distributes trigger, time and configuration data coming from the network interface to the front-end boards. The L1DDC is fully compatible with the Phase II upgrade where the trigger rate is expected to reach 1 MHz. This paper describes the overall scheme of the data acquisition process and especially the three different L1DDC boards that will be fabricated. Moreover the L1DDC prototype-1 is also described.

  1. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    International Nuclear Information System (INIS)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

    2015-01-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  2. System-level considerations for the front-end readout ASIC in the CBM experiment from the power supply perspective

    Science.gov (United States)

    Kasinski, K.; Koczon, P.; Ayet, S.; Löchner, S.; Schmidt, C. J.

    2017-03-01

    New fixed target experiments using high intensity beams with energy up to 10 AGeV from the SIS100 synchrotron presently being constructed at FAIR/GSI are under preparation. Most of the readout electronics and power supplies are expected to be exposed to a very high flux of nuclear reaction products and have to be radiation tolerant up to 3 MRad (TID) and sustain up to 1014/cm2 of 1 MeV neutron equivalent in their life time. Moreover, the mostly minimum ionising particles under investigation leave very little signal in the sensors. Therefore very low noise level amplitude measurements are required by the front-end electronics for effective tracking. Sensor and interconnecting micro-cable capacitance and series resistance in conjunction with intrinsic noise of the charge sensitive amplifier are dominant noise sources in the system. However, the single-ended architecture of the amplifiers employed for the charge processing channels implies a potential problem with noise contributions from power supply sources. Strict system-level constraints leave very little freedom in selecting a power supply structure optimal with respect to: power efficiency, cooling capabilities and power density on modules, but also noise injection to the front-end via the power supply lines. Design of the power supply and distribution system of the Silicon Tracking System in the CBM experiment together with details on the front-end ASICs (STS -XYTER2) and measurement results of power supply and conditioning electronics (selected DC/DC converter and LDO regulators) are presented.

  3. Quality control considerations for the development of the front end hybrid circuits for the CMS Outer Tracker upgrade

    CERN Document Server

    Gadek, Tomasz; Bonnaud, Julien Yves Robert; De Clercq, Jarne Theo; Honma, Alan; Koliatos, Alexandros; Kovacs, Mark Istvan; Luetic, Jelena

    2017-01-01

    The upgrade of the CMS Outer Tracker for the HL-LHC requires the design of new double-sensor modules. They contain two high-density front end hybrid circuits, equipped with flip-chip ASICs, passives and mechanical structures. First prototype hybrids in a close-to-final form have been ordered from three manufacturers. To qualify these hybrids a test setup was built, which emulates future tracker temperature and humidity conditions, provides temporary interconnection, and implements testing features. The system was automated to minimize the testing time in view of the production phase. Failure modes, deliberately implemented in the produced hybrids, provided feedback on the system’s effectiveness.

  4. Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

    Energy Technology Data Exchange (ETDEWEB)

    Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

    2017-09-01

    This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

  5. Quality control considerations for the development of the front end hybrid circuits for the CMS Outer Tracker upgrade

    CERN Document Server

    Gadek, Tomasz; Bonnaud, Julien Yves Robert; De Clercq, Jarne Theo; Honma, Alan; Koliatos, Alexandros; Kovacs, Mark Istvan; Luetic, Jelena

    2017-01-01

    The upgrade of the CMS Outer Tracker for the HL-LHC requires the design of new double-sensor modules. They contain two high-density front end hybrid circuits, equipped with flip-chip ASICs, passives and mechanical structures. First prototype hybrids in a close-to-final form have been received from three manufacturers. To qualify these hybrids a test setup was built, which emulates future tracker temperature and humidity conditions, provides temporary interconnection, and implements testing features. The system was automated to minimize the testing time in view for the production phase. Failure modes, deliberately implemented in the produced hybrids, provided feedback on the system's effectiveness.

  6. Front-end and back-end electrochemistry of molten salt in accelerator-driven transmutation systems

    International Nuclear Information System (INIS)

    Williamson, M.A.; Venneri, F.

    1995-01-01

    The objective of this work is to develop preparation and clean-up processes for the fuel and carrier salt in the Los Alamos Accelerator-Driven Transmutation Technology molten salt nuclear system. The front-end or fuel preparation process focuses on the removal of fission products, uranium, and zirconium from spent nuclear fuel by utilizing electrochemical methods (i.e., electrowinning). The same method provides the separation of the so-called noble metal fission products at the back-end of the fuel cycle. Both implementations would have important diversion safeguards. The proposed separation processes and a thermodynamic analysis of the electrochemical separation method are presented

  7. Production and performance of LHCb triple-GEM detectors equipped with the dedicated CARDIAC-GEM front-end electronics

    Energy Technology Data Exchange (ETDEWEB)

    Alfonsi, M. [Laboratori Nazionali di Frascati - INFN (Italy)]. E-mail: matteo.alfonsi@lnf.infn.it; Bencivenni, G. [Laboratori Nazionali di Frascati - INFN (Italy); Bonivento, W. [Sezione INFN di Cagliari (Italy); Cardelli, E. [Sezione INFN di Cagliari (Italy); Cardini, A. [Sezione INFN di Cagliari (Italy); De Simone, P. [Laboratori Nazionali di Frascati - INFN (Italy); Domenici, D. [Laboratori Nazionali di Frascati - INFN (Italy); Murtas, F. [Laboratori Nazionali di Frascati - INFN (Italy); Pinci, D. [Sezione INFN di Roma 1 (Italy); Poli Lener, M. [Laboratori Nazionali di Frascati - INFN (Italy); Raspino, D. [Sezione INFN di Cagliari (Italy); Saitta, B. [Sezione INFN di Cagliari (Italy)

    2007-03-01

    The production of the triple-GEM detectors for the innermost region of the first muon station of the LHCb experiment has started in February 2006, and is foreseen to be completed by the end of July. The final design of the detector and the construction procedure and tools, as well as the quality controls are defined. The performances of each detector, composed by two triple-GEM chambers equipped with dedicated CARDIAC-GEM front-end electronics, are studied with a cosmic ray telescope. The cosmic ray telescope has been set up including all the final off-detector components.

  8. Charge-sensitive amplifier front-end with an nJFET and a forward-biased reset diode

    Energy Technology Data Exchange (ETDEWEB)

    Fazzi, A. [Politecnico di Milano (Italy); Jalas, P. [Univ. of Helsinki, Espoo (Finland); Rehak, P. [Brookhaven National Lab., Upton, NY (United States); Holl, P. [Max Planck Inst., Garching (Germany)

    1996-12-01

    A new configuration of a resistorless charge sensitive preamplifier with an nJFET as an input device was tested. The dc level of the input of the amplifier was kept constant by a slightly forward-biased np junction connected between the input of the amplifier and ground. A noise level of 22 root mean square (r.m.s.) electrons is measured at 295 K and 15 r.m.s. electrons at 253 K. The dynamic behavior of the amplifier is investigated with different leakage current conditions. The technological benefits and the suitability of the front-end connection for room temperature detectors, particularly multianode drift chambers, are highlighted.

  9. Design, development, installation and commissioning of water-cooled pre-masks for undulator front-ends of Indus-2

    International Nuclear Information System (INIS)

    Raghuvanshi, V.K.; Prasad, Vijendra; Garg, S.R.; Jain, Vikas

    2015-01-01

    Recently two undulators U1 and U2 are installed in Indus-2 storage ring at RRCAT, Indore. When U1 and U2 are put in operation, a bright synchrotron radiation (SR) is produced which is transmitted through the zero degree port of the dipole vacuum chamber. In addition, a part of SR beam from the bending magnets, at the upstream and downstream of the undulator, is also overlapped with the undulator SR beam and transmitted in to the front-end through the same port. The front-end is a long ultra high vacuum (UHV) assembly consisting of water-cooled pre-mask, water-cooled shutters, UHV valves, diagnostic devices, safety shutter, vacuum pumps etc which acts as an interface between Indus-2 ring and beamline. Water-cooled pre- masks have been designed to cut a part of unwanted SR beam from the bending magnets. The pre-mask is a first active component in the undulator front-end which is also capable of absorbing high thermal load due to mis-steering of the SR beam from the undulator in the worst case scenario. The watercooled pre-mask consists of a copper block which has fixed aperture with slant faces to distribute the heat flux over a large surface area. The cooling channels are made on outer periphery of the block. The copper block is vacuum brazed with two conflat flanges of stainless steel at the two ends. The pre-mask is designed to absorb thermal load of 3 kW of synchrotron beam from undulator U1 and 2 kW of synchrotron beam from undulator U2. The thermal analysis of the pre-masks was carried out with the help of ANSYS® and the design was optimized with different cooling configurations. The main design criteria was to limit the maximum temperature of the mask less than 60 °C. This is to avoid substantial thermal outgassing from the heated portion which may deteriorate the ultra high vacuum. Pre-masks have been successfully tested, installed and commissioned with synchrotron beam in the undulator front-ends and are operating under vacuum of 5x10 -10 mbar. (author)

  10. Silicon photomultipliers: On ground characterizations and modelling for use in front-end electronics aimed to space-borne experiments

    Energy Technology Data Exchange (ETDEWEB)

    Badoni, Davide [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy)]. E-mail: davide.badoni@roma2.infn.it; Altamura, Francesco [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Basili, Alessandro [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Bencardino, Raffaele [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Bidoli, Vittorio [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Casolino, Marco [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); De Carli, Anna [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Froysland, Tom [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Marchetti, Marcello [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Messi, Roberto [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Minori, Mauro [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Picozza, Piergiorgio [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Salina, Gaetano [Phy. Dep. Univ. ' Tor Vergata' , Tor Vergata Sect. INFN (Italy); Galper, Arkady [Moscow Engineering and Physics Institute (Russian Federation); Korotkov, Mikhail [Moscow Engineering and Physics Institute (Russian Federation); Popov, Alexander [Moscow Engineering and Physics Institute (Russian Federation)

    2007-03-01

    Silicon Photomultipliers (Si-PM) consist of an array of semiconductor photodiodes joint on the common substrate and operating in limited geiger mode. A new generation of Si-PM is currently under test in INFN Rome Tor Vergata facilities: they consist of a 5625 element, 3*3mm{sup 2} array with an improved light response. These elements have been characterized. Furthermore, a functional model of the Si-PM has been developed to be used in a VLSI development of front-end electronics.

  11. A high dynamic range programmable CMOS front-end filter with a tuning range from 1850 to 2400 MHz

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais; Lee, Thomas H.; Bruun, Erik

    2005-01-01

    This paper presents a highly programmable front-end filter and amplifier intended to replace SAW filters and low noise amplifiers (LNA) in multi-mode direct conversion radio receivers. The filter has a 42 MHz bandwidth, is tunable from 1850 to 2400 MHz, achieves a 5.8 dB NF, -25 dBm in-band 1-dB ......B input compression point (ICP) and 0 dBm out-of-band ICP while drawing 26 mA from a 2.5 V supply....

  12. ATLAS

    Data.gov (United States)

    Federal Laboratory Consortium — ATLAS is a particle physics experiment at the Large Hadron Collider at CERN, the European Organization for Nuclear Research. Scientists from Brookhaven have played...

  13. A combined analogue+ digital software defined radio receiver front-end for Bluetooth and Hiperlan/2

    NARCIS (Netherlands)

    Arkesteijn, V.J.; Schiphorst, Roelof; Hoeksema, F.W.; Klumperink, Eric A.M.; Nauta, Bram; Slump, Cornelis H.

    2004-01-01

    The number of wireless communication links is witnessing tremendous growth and new standards are being introduced at high pace. However, circuit development is costly and time consuming due to mask costs and design iterations. Moreover, with ever-increasing radio standard complexity, these costs are

  14. Analog front-end electronics for the outer layers of the SuperB SVT: Design and expected performances

    Science.gov (United States)

    Bombelli, Luca; Fiorini, Carlo; Nasri, Bayan; Trigilio, Paolo; Citterio, Mauro; Neri, Nicola

    2013-08-01

    The Silicon Vertex Tracker (SVT) of the new SuperB collider will be composed of 6 different detector layers [1]. The innermost layer (L0) will be composed by striplets or pixels [2]; the other 5 detector layers will be double-sided long-strip detectors. The strip geometries and the foreseen hit-rates will change according to the different layers. As a consequence, different optimization of the analog read-out electronics is needed in order to provide high detection-efficiency and low noise level in the different layers. Two readout ASICs are currently developed, one for layers 0-3, another for layers 4 and 5; they differ mainly in the analog front-end. In this work, we present the design and the expected performances of the analog front-end for layers 4 and 5. For these layers, the strip detectors show a very high stray capacitance and high series resistance. In this condition, the noise optimization is our primary concern. A necessary compromise on the best peaking time to achieve an acceptable noise level together with efficiency and timing accuracy has been found. We will present the design of preamplifier and shaper and the results of simulation of noise performance and efficiency (with the expected background rates). In addition, the design of the time-over-threshold and its use to correct the time-walk of the event trigger is discussed as well as the achievable timing accuracy of the circuit.

  15. Design of a front-end integrated circuit for 3D acoustic imaging using 2D CMUT arrays.

    Science.gov (United States)

    Ciçek, Ihsan; Bozkurt, Ayhan; Karaman, Mustafa

    2005-12-01

    Integration of front-end electronics with 2D capacitive micromachined ultrasonic transducer (CMUT) arrays has been a challenging issue due to the small element size and large channel count. We present design and verification of a front-end drive-readout integrated circuit for 3D ultrasonic imaging using 2D CMUT arrays. The circuit cell dedicated to a single CMUT array element consists of a high-voltage pulser and a low-noise readout amplifier. To analyze the circuit cell together with the CMUT element, we developed an electrical CMUT model with parameters derived through finite element analysis, and performed both the pre- and postlayout verification. An experimental chip consisting of 4 X 4 array of the designed circuit cells, each cell occupying a 200 X 200 microm2 area, was formed for the initial test studies and scheduled for fabrication in 0.8 microm, 50 V CMOS technology. The designed circuit is suitable for integration with CMUT arrays through flip-chip bonding and the CMUT-on-CMOS process.

  16. The SSC field bus: A high-performance control system front end concentrator for 'slow' accelerator controls

    International Nuclear Information System (INIS)

    Haenni, D.R.; Saltmarsh, C.G.; Lue, H.C.; Hunt, S.M.

    1991-01-01

    The SSC control system must support a large number of 'slow' or industrial type control points. A front-end system is described which could serve as both a data concentrator and a distributed process controller for these points. Unlike many distributed control systems, this front end is designed to provide strong support for centralized controls. The live parameter data base in the central system can be updated at a rate which is fast compared to that usually needed for process control loops. Portions of this data base can be optionally replicated in regional computers to provide both local control stations and distributed control loops. In addition to the global and regional levels the system also allows the distribution of loops to the local I/O crate level. A possible implementation of this system is under development which is based on industrial standard STD-Bus for accelerator hardware interfacing, time domain multiplexing (TDM) for communications transport, and a form of reflective memory for the back-end interface to the rest of the control system

  17. A front end ASIC for the readout of the PMT in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

    2010-01-01

    In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

  18. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Fleury, J; Ahmad, S; Callier, S; Taille, C de La; Seguin, N; Thienpont, D; Dulucq, F; Martin, G

    2014-01-01

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  19. Design of low noise front-end ASIC and DAQ system for CdZnTe detector

    International Nuclear Information System (INIS)

    Luo Jie; Deng Zhi; Liu Yinong

    2012-01-01

    A low noise front-end ASIC has been designed for CdZnTe detector. This chip contains 16 channels and each channel consists of a dual-stage charge sensitive preamplifier, 4th order semi-Gaussian shaper, leakage current compensation (LCC) circuit, discriminator and output buffer. This chip has been fabricated in Chartered 0.35 μm CMOS process, the preliminary results show that it works well. The total channel charge gain can be adjusted from 100 mV/fC to 400 mV/fC and the peaking time can be adjusted from 1 μs to 4 μs. The minimum measured ENC at zero input capacitance is 70 e and minimum noise slope is 20 e/pF. The peak detector and derandomizer (PDD) ASIC developed by BNL and an associated USB DAQ board are also introduced in this paper. Two front-end ASICs can be connected to the PDD ASIC on the USB DAQ board and compose a 32 channels DAQ system for CdZnTe detector. (authors)

  20. Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

    Science.gov (United States)

    Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

    2017-12-01

    Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

  1. Safety control system and its interface to EPICS for the off-line front end of the SPES project

    International Nuclear Information System (INIS)

    Vasquez, J.; Andrighetto, A.; Bassato, G.; Costa, L.; Giacchini, M.; Bertocco, M.

    2012-01-01

    The SPES (Selective Production of Exotic Species) project is based on a facility for the production of neutron-rich radioactive ion beams using the isotope separation on-line technique. The SPES off-line front-end apparatus involves a number of subsystems and procedures that are potentially dangerous both for human operators and for the equipment. The high voltage power supply, the ion source complex power supplies, the target chamber handling systems and the laser source are some example of these subsystems. For that reason, a safety control system has been developed. It is based on Schneider Electrics Preventa family safety modules that control the power supply of critical subsystems in combination with safety detectors that monitor critical variables. A Programmable Logic Controller (PLC), model BMXP342020 from the Schneider Electrics Modicon M340 family, is used for monitoring the status of the system as well as controlling the sequence of some operations in automatic way. A touch screen, model XBTGT5330 from the Schneider Electrics Magelis family, is used as Human Machine Interface (HMI) and communicates with the PLC using MODBUS-TCP. Additionally, an interface to the EPICS control network was developed using a home-made MODBUS-TCP EPICS driver in order to integrate it to the control system of the Front End as well as present the status of the system to the users on the main control panel. (authors)

  2. 2.5 Gbit/s Optical Receiver Front-End Circuit with High Sensitivity and Wide Dynamic Range

    Science.gov (United States)

    Zhu, Tiezhu; Mo, Taishan; Ye, Tianchun

    2017-12-01

    An optical receiver front-end circuit is designed for passive optical network and fabricated in a 0.18 um CMOS technology. The whole circuit consists of a transimpedance amplifier (TIA), a single-ended to differential amplifier and an output driver. The TIA employs a cascode stage as the input stage and auxiliary amplifier to reduce the miller effect. Current injecting technique is employed to enlarge the input transistor's transconductance, optimize the noise performance and overcome the lack of voltage headroom. To achieve a wide dynamic range, an automatic gain control circuit with self-adaptive function is proposed. Experiment results show an optical sensitivity of -28 dBm for a bit error rate of 10-10 at 2.5 Gbit/s and a maxim input optical power of 2 dBm using an external photodiode. The chip occupies an area of 1×0.9 mm2 and consumes around 30 mW from single 1.8 V supply. The front-end circuit can be used in various optical receivers.

  3. The CBM Experiment at FAIR-New challenges for Front-End Electronics, Data Acquisition and Trigger Systems

    International Nuclear Information System (INIS)

    Mueller, Walter F J

    2006-01-01

    The 'Compressed Baryonic Matter' (CBM) experiment at the new 'Facility for Antiproton and Ion Research' (FAIR) in Darmstadt is designed to study the properties of highly compressed baryonic matter produced in nucleus-nucleus collisions in the 10 to 45 A GeV energy range. One of the key observables is hidden (J/ψ) and open (D 0 , D ± ) charm production. To achieve an adequate sensitivity extremely high interaction rates of up to 10 7 events/second are required, resulting in major technological challenges for the detectors, front-end electronics and data processing. The front-end electronics will be self-triggered, autonomously detect particle hits, and output hit parameter together with a precise absolute time-stamp. Several layers of feature extraction and event selection will reduce the primary data flow of about 1 TByte/sec to a level of 1 GByte/sec. This new architecture avoids many limitations of conventional DAQ/Trigger systems and is for example essential for open charm detection, which requires the reconstruction of displaced vertices, in a high-rate heavy ion environment

  4. UTD-CRSS Submission for MGB-3 Arabic Dialect Identification: Front-end and Back-end Advancements on Broadcast Speech

    OpenAIRE

    Bulut, Ahmet E.; Zhang, Qian; Zhang, Chunlei; Bahmaninezhad, Fahimeh; Hansen, John H. L.

    2017-01-01

    This study presents systems submitted by the University of Texas at Dallas, Center for Robust Speech Systems (UTD-CRSS) to the MGB-3 Arabic Dialect Identification (ADI) subtask. This task is defined to discriminate between five dialects of Arabic, including Egyptian, Gulf, Levantine, North African, and Modern Standard Arabic. We develop multiple single systems with different front-end representations and back-end classifiers. At the front-end level, feature extraction methods such as Mel-freq...

  5. FELIX: the new detector readout system for the ATLAS experiment

    CERN Document Server

    ATLAS TDAQ Collaboration; The ATLAS collaboration

    2017-01-01

    After the Phase-I upgrade and onward, the Front-End Link eXchange (FELIX) system will be the interface between the data handling system and the detector front-end electronics and trigger electronics at the ATLAS experiment. FELIX will function as a router between custom serial links and a commodity switch network which will use standard technologies to communicate with data collecting and processing components. The FELIX system is being developed by using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card interfacing to GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. Dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software will provide the required functionality. On the network side, the FELIX unit connects to both Ethernet-based network and Infiniband. The system architecture of FE...

  6. FELIX: the new detector readout system for the ATLAS experiment

    CERN Document Server

    ATLAS TDAQ Collaboration; The ATLAS collaboration

    2017-01-01

    Starting during the upcoming major LHC shutdown from 2019-2021, the ATLAS experiment at CERN will move to the the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. The FELIX system is being developed using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card hosting GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. FELIX functions will be implemented with dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software. On the network side, FELIX is able to connect to both Ethernet or Infiniband network a...

  7. FELIX: the new detector readout system for the ATLAS experiment

    CERN Document Server

    Bauer, Kevin Thomas; The ATLAS collaboration

    2018-01-01

    Starting during the upcoming major LHC shutdown from 2019-2021, the ATLAS experiment at CERN will move to the the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. The FELIX system is being developed using commercial-off-the-shelf server PC technology in combination with a FPGA-based PCIe Gen3 I/O card hosting GigaBit Transceiver links and with Timing, Trigger and Control connectivity provided by an FMC-based mezzanine card. FELIX functions will be implemented with dedicated firmware for the Xilinx FPGA (Virtex 7 and Kintex UltraScale) installed on the I/O card alongside an interrupt-driven Linux kernel driver and user-space software. On the network side, FELIX is able to connect to both Ethernet or Infiniband network a...

  8. Measuring Single Event Upsets in the ATLAS Inner Tracker

    CERN Multimedia

    CERN. Geneva

    2015-01-01

    When the HL-LHC starts collecting data, the electronics inside will be subject to massive amounts of radiation. As a result, single event upsets could pose a threat to the ATLAS readout chain. The ABC130, a prototype front-end ASIC for the ATLAS inner tracker, must be tested for its susceptibility to single event upsets.

  9. Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

    Science.gov (United States)

    Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

    2014-02-01

    Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

  10. Current Controller for Multi-level Front-end Converter and Its Digital Implementation Considerations on Three-level Flying Capacitor Topology

    Science.gov (United States)

    Tekwani, P. N.; Shah, M. T.

    2017-10-01

    This paper presents behaviour analysis and digital implementation of current error space phasor based hysteresis controller applied to three-phase three-level flying capacitor converter as front-end topology. The controller is self-adaptive in nature, and takes the converter from three-level to two-level mode of operation and vice versa, following various trajectories of sector change with the change in reference dc-link voltage demanded by the load. It keeps current error space phasor within the prescribed hexagonal boundary. During the contingencies, the proposed controller takes the converter in over modulation mode to meet the load demand, and once the need is satisfied, controller brings back the converter in normal operating range. Simulation results are presented to validate behaviour of controller to meet the said contingencies. Unity power factor is assured by proposed controller with low current harmonic distortion satisfying limits prescribed in IEEE 519-2014. Proposed controller is implemented using TMS320LF2407 16-bit fixed-point digital signal processor. Detailed analysis of numerical format to avoid overflow of sensed variables in processor, and per-unit model implementation in software are discussed and hardware results are presented at various stages of signal conditioning to validate the experimental setup. Control logic for the generation of reference currents is implemented in TMS320LF2407A using assembly language and experimental results are also presented for the same.

  11. Cold front-end electronics and Ethernet-based DAQ systems for large LAr TPC readout

    CERN Document Server

    D.Autiero,; B.Carlus,; Y.Declais,; S.Gardien,; C.Girerd,; J.Marteau; H.Mathez

    2010-01-01

    Large LAr TPCs are among the most powerful detectors to address open problems in particle and astro-particle physics, such as CP violation in leptonic sector, neutrino properties and their astrophysical implications, proton decay search etc. The scale of such detectors implies severe constraints on their readout and DAQ system. We are carrying on a R&D in electronics on a complete readout chain including an ASIC located close to the collecting planes in the argon gas phase and a DAQ system based on smart Ethernet sensors implemented in a µTCA standard. The choice of the latter standard is motivated by the similarity in the constraints with those existing in Network Telecommunication Industry. We also developed a synchronization scheme developed from the IEEE1588 standard integrated by the use of the recovered clock from the Gigabit link

  12. Channel Control ASIC for the CMS hadron calorimeter front end readout module

    CERN Document Server

    Yarema, R J; Boubekeur, A; Elias, J E; Shaw, T

    2002-01-01

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link. (2 refs) .

  13. The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

    International Nuclear Information System (INIS)

    Lafond, E.; Mur, M.; Schanne, S.

    1998-01-01

    The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

  14. Design and construction of the front-end electronics data acquisition for the SLD CRID [Cherenkov Ring Imaging Detector

    International Nuclear Information System (INIS)

    Hoeflich, J.; McShurley, D.; Marshall, D.; Oxoby, G.; Shapiro, S.; Stiles, P.; Spencer, E.

    1990-10-01

    We describe the front-end electronics for the Cherenkov Ring Imaging Detector (CRID) of the SLD at the Stanford Linear Accelerator Center. The design philosophy and implementation are discussed with emphasis on the low-noise hybrid amplifiers, signal processing and data acquisition electronics. The system receives signals from a highly efficient single-photo electron detector. These signals are shaped and amplified before being stored in an analog memory and processed by a digitizing system. The data from several ADCs are multiplexed and transmitted via fiber optics to the SLD FASTBUS system. We highlight the technologies used, as well as the space, power dissipation, and environmental constraints imposed on the system. 16 refs., 10 figs

  15. Explosive bonding and its application in the Advanced Photon Source front-end and beamline components design

    International Nuclear Information System (INIS)

    Shu, D.; Li, Y.; Ryding, D.; Kuzay, T.M.

    1994-01-01

    Explosive bonding is a bonding method in which the controlled energy of a detonating explosive is used to create a metallurgical bonding between two or more similar or dissimilar materials. Since 1991, a number of explosive-bonding joints have been designed for high-thermal-load ultrahigh-vacuum (UHV) compatible components in the Advanced Photon Source. A series of standardized explosive bonded joint units has also been designed and tested, such as: oxygen-free copper (OFHC) to stainless-steel vacuum joints for slits and shutters, GlidCop to stainless-steel vacuum joints for fixed masks, and GlidCop to OFHC thermal and mechanical joints for shutter face-plates, etc. The design and test results for the explosive bonding units to be used in the Advanced Photon Source front ends and beamlines will be discussed in this paper

  16. Considerations on the design of front-end electronics for silicon calorimetry for the SSC [Superconducting Super Collider

    International Nuclear Information System (INIS)

    Wintenberg, A.L.; Bauer, M.L.; Britton, C.L. Jr.; Kennedy, E.J.; Todd, R.A.; Berridge, S.C.; Bugg, W.M.

    1990-01-01

    Some considerations are described for the design of a silicon-based sampling calorimetry detector for the Superconducting Super Collider (SSC). The use of silicon as the detection medium allows fast, accurate, and fine-grained energy measurements -- but for optimal performance, the front-end electronics must be matched to the detector characteristics and have the speed required by the high SSC interaction rates. The relation between the signal-to-noise ratio of the calorimeter electronics and the charge collection time, the preamplifier power dissipation, detector capacitance and leakage, charge gain, and signal shaping and sampling was studied. The electrostatic transformer connection was analyzed and found to be unusable for a tightly arranged calorimeter because of stray capacitance effects. The method of deconvolutional sampling was developed as a means for pileup correction following synchronous sampling and analog storage. 3 refs., 6 figs

  17. The STS-XYTER ASIC. A dedicated front-end chip for the CBM silicon tracking system

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH, Darmstadt (Germany); Kiev Institute for Nuclear Research, Kiev (Ukraine); Krzysztof, Krzysztof; Kleczek, Rafal; Otfinowski, Piotr; Szczygiel, Robert [AGH University of Science and Technology, Cracow (Poland); Kleipa, Volker [GSI Helmholtzzentrum fuer Schwerionenforschung GmbH, Darmstadt (Germany); Collaboration: CBM-Collaboration

    2015-07-01

    The STS-XYTER is a 128-channel charge-sensitive front-end chip, designed specifically for the Silicon Tracking System of the CBM experiment. The chip features a self-triggering architecture, which enables it to measure the signal amplitude and the time of arrival in each input channel autonomously, as soon as the signal in the given channel exceeds a predefined threshold. The design time resolution is about 10 ns, the dynamic range is 15 fC, and the amplitude is digitized with an integrated 5-bit flash ADC. Two shapers with distinct rise times are used to achieve low rate of noise hits in combination with the good time resolution, and low power consumption (6 mW/channel). The characterization of chips samples is ongoing. An overview of the chip architecture as well as the operation principle is given.

  18. WNA's worldwide overview on front-end nuclear fuel cycle growth and health, safety and environmental issues.

    Science.gov (United States)

    Saint-Pierre, Sylvain; Kidd, Steve

    2011-01-01

    This paper presents the WNA's worldwide nuclear industry overview on the anticipated growth of the front-end nuclear fuel cycle from uranium mining to conversion and enrichment, and on the related key health, safety, and environmental (HSE) issues and challenges. It also puts an emphasis on uranium mining in new producing countries with insufficiently developed regulatory regimes that pose greater HSE concerns. It introduces the new WNA policy on uranium mining: Sustaining Global Best Practices in Uranium Mining and Processing-Principles for Managing Radiation, Health and Safety and the Environment, which is an outgrowth of an International Atomic Energy Agency (IAEA) cooperation project that closely involved industry and governmental experts in uranium mining from around the world. Copyright © 2010 Health Physics Society

  19. High-average-power, 50-fs parametric amplifier front-end at 1.55 μm.

    Science.gov (United States)

    Mero, Mark; Noack, Frank; Bach, Florian; Petrov, Valentin; Vrakking, Marc J J

    2015-12-28

    An average-power-scalable, two-stage optical parametric chirped pulse amplifier is presented providing 90-μJ signal pulses at 1.55 μm and 45-μJ idler pulses at 3.1 μm at a repetition rate of 100 kHz. The signal pulses were recompressible to within a few percent of their ~50-fs Fourier limit in anti-reflection coated fused silica at negligible losses. The overall energy conversion efficiency from the 1030-nm pump to the recompressed signal reached 19%, significantly reducing the cost per watt of pump power compared to similar systems. The two-stage source will serve as the front-end of a three-stage system permitting the development of novel experimental strategies towards laser-based imaging of molecular structures and chemical reactivity.

  20. A Nonlinearity Mitigation Method for a Broadband RF Front-End in a Sensor Based on Best Delay Searching.

    Science.gov (United States)

    Zhao, Wen; Ma, Hong; Zhang, Hua; Jin, Jiang; Dai, Gang; Hu, Lin

    2017-09-28

    The cognitive radio wireless sensor network (CR-WSN) is experiencing more and more attention for its capacity to automatically extract broadband instantaneous radio environment information. Obtaining sufficient linearity and spurious-free dynamic range (SFDR) is a significant premise of guaranteeing sensing performance which, however, usually suffers from the nonlinear distortion coming from the broadband radio frequency (RF) front-end in the sensor node. Moreover, unlike other existing methods, the joint effect of non-constant group delay distortion and nonlinear distortion is discussed, and its corresponding solution is provided in this paper. After that, the nonlinearity mitigation architecture based on best delay searching is proposed. Finally, verification experiments, both on simulation signals and signals from real-world measurement, are conducted and discussed. The achieved results demonstrate that with best delay searching, nonlinear distortion can be alleviated significantly and, in this way, spectrum sensing performance is more reliable and accurate.

  1. A Nonlinearity Mitigation Method for a Broadband RF Front-End in a Sensor Based on Best Delay Searching

    Directory of Open Access Journals (Sweden)

    Wen Zhao

    2017-09-01

    Full Text Available The cognitive radio wireless sensor network (CR-WSN is experiencing more and more attention for its capacity to automatically extract broadband instantaneous radio environment information. Obtaining sufficient linearity and spurious-free dynamic range (SFDR is a significant premise of guaranteeing sensing performance which, however, usually suffers from the nonlinear distortion coming from the broadband radio frequency (RF front-end in the sensor node. Moreover, unlike other existing methods, the joint effect of non-constant group delay distortion and nonlinear distortion is discussed, and its corresponding solution is provided in this paper. After that, the nonlinearity mitigation architecture based on best delay searching is proposed. Finally, verification experiments, both on simulation signals and signals from real-world measurement, are conducted and discussed. The achieved results demonstrate that with best delay searching, nonlinear distortion can be alleviated significantly and, in this way, spectrum sensing performance is more reliable and accurate.

  2. A wide dynamic range BF{sub 3} neutron monitor with front-end electronics based on a logarithmic amplifier

    Energy Technology Data Exchange (ETDEWEB)

    Ferrarini, M., E-mail: michele.ferrarini@polimi.i [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Fondazione CNAO, via Caminadella 16, 20123 Milano (Italy); Varoli, V. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Favalli, A. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Vatican City State, Holy See) (Italy); Caresana, M. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Pedersen, B. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Italy)

    2010-02-01

    This paper describes a wide dynamic range neutron monitor based on a BF{sub 3} neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10{sup 6} s{sup -1}. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

  3. The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

    International Nuclear Information System (INIS)

    Balsamo, E; Bergnoli, A; Bertolin, A; Brugnera, R; Carrara, E; Ciesielski, R; Dal Corso, F; Dusini, S; Garfagnini, A; Kose, U; Longhin, A; Medinaceli, E; Stanco, L

    2012-01-01

    The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m 2 , and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

  4. The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

    Science.gov (United States)

    Balsamo, E.; Bergnoli, A.; Bertolin, A.; Brugnera, R.; Carrara, E.; Ciesielski, R.; Dal Corso, F.; Dusini, S.; Garfagnini, A.; Kose, U.; Longhin, A.; Medinaceli, E.; Stanco, L.

    2012-11-01

    The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m2, and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

  5. The front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector

    International Nuclear Information System (INIS)

    Haller, G.M.; Freytag, D.R.; Fox, J.; Olsen, J.; Paffrath, L.; Yim, A.; Honma, A.

    1990-10-01

    The front-end signal processing electronics for the drift-chambers of the Stanford Large Detector (SLD) at the Stanford Linear Collider is described. The system is implemented with printed-circuit boards which are shaped for direct mounting on the detector. Typically, a motherboard comprises 64 channels of transimpedance amplification and analog waveform sampling, A/D conversion, and associated control and readout circuitry. The loaded motherboard thus forms a processor which records low-level wave forms from 64 detector channels and transforms the information into a 64 k-byte serial data stream. In addition, the package performs calibration functions, measures leakage currents on the wires, and generates wire hit patterns for triggering purposes. The construction and operation of the electronic circuits utilizing monolithic, hybridized, and programmable components are discussed

  6. Inter-firm collaboration in the Fuzzy Front-End of the innovation process - Exploring New Forms of Collaboration

    DEFF Research Database (Denmark)

    Jørgensen, Jacob Høj; Goduscheit, René Chester; Bergenholz, Carsten

    2007-01-01

    Innovation and innovation processes has traditionally been considered from the manufacturing companies' perspective. The innovation process is typically divided into a series of succeeding stages where the Fuzzy Front-End is the first stage to encounter. Several research projects have formulated...... recommendations for the manufacturer to improve the innovation process and enhance the chances of success. However, the waist majority of these projects belong to an intra-organizational paradigm where the manufacturer is considered to be the only part involved in the process, controlling and influencing......, marketing, sales. The focus of this paper is on collaboration where innovation is the main part of the collaborative effort. Innovation refers to the research and development (R&D) activity devoted to increasing scientific or technical knowledge and the application of that knowledge to the creation of new...

  7. Controller design and implementation of a three-phase Active Front End using SiC based MOSFETs

    DEFF Research Database (Denmark)

    Haase, Frerk; Kouchaki, Alireza; Nymand, Morten

    2015-01-01

    The design and implementation of a three phase Active Front End for power factor correction purposes using fast switching SiC based MOSFETs is presented. Possible applications are within the drives- and renewable energy sector. The controller is designed and implemented in the synchronous rotating...... factor correction for an active rectifier in comparison to a passive rectifier. The SiC based power switches thereby offer the possibility of using high switching frequencies leading to a reduction in filter size - here a simple L filter. The controller is able to validate the simulation results...... reference frame. Besides the theoretical modelling the controller is optimized through simulations and implemented on a low cost DSP processor using a visual programming language - here MATLAB/SIMULINK - with automatic code generation for embedded targets. The paper illustrates the advantages of power...

  8. A 410 μW, 70 dB SNR high performance analog front-end for portable audio application

    Science.gov (United States)

    Lan, Dai; Wenkai, Liu; Yan, Lu

    2014-10-01

    This paper describes an analog front-end (AFE) intended for portable audio application, which operates at 1 V and consumes only 410 μW. The AFE consists of a 30 dB-gain programmable gain amplifier (PGA) and a 2nd-order 3-bit sigma-delta modulator. The PGA with single input and on-chip common-mode bias voltage shows good noise-reduction performance. The modulator makes use of data weighted averaging to reduce the linearity requirements of the digital-to-analog converter in the feedback loop. The AFE is implemented in the SMIC 0.13 μm 1P8M CMOS process. The measurement results show that in a 1 V power supply, at 200 mVp-p, between 100 Hz and 20 kHz, the maximal signal-to-noise ratio is 70 dB, and the total power is 410 μW.

  9. Performance analysis of a low power low noise tunable band pass filter for multiband RF front end

    Science.gov (United States)

    Manjula, J.; Malarvizhi, S.

    2014-03-01

    This paper presents a low power tunable active inductor and RF band pass filter suitable for multiband RF front end circuits. The active inductor circuit uses the PMOS cascode structure as the negative transconductor of a gyrator to reduce the noise voltage. Also, this structure provides possible negative resistance to reduce the inductor loss with wide inductive bandwidth and high resonance frequency. The RF band pass filter is realized using the proposed active inductor with suitable input and output buffer stages. The tuning of the center frequency for multiband operation is achieved through the controllable current source. The designed active inductor and RF band pass filter are simulated in 180 nm and 45 nm CMOS process using the Synopsys HSPICE simulation tool and their performances are compared. The parameters, such as resonance frequency, tuning capability, noise and power dissipation, are analyzed for these CMOS technologies and discussed. The design of a third order band pass filter using an active inductor is also presented.

  10. Channel Analysis for a 6.4 Gb s-1 DDR5 Data Buffer Receiver Front-End

    Science.gov (United States)

    Lehmann, Stefanie; Gerfers, Friedel

    2017-09-01

    In this contribution, the channel characteristic of the next generation DDR5-SDRAM architecture and possible approaches to overcome channel impairments are analysed. Because modern enterprise server applications and networks demand higher memory bandwidth, throughput and capacity, the DDR5-SDRAM specification is currently under development as a follow-up of DDR4-SDRAM technology. In this specification, the data rate is doubled to DDR5-6400 per IO as compared to the former DDR4-3200 architecture, resulting in a total per DIMM data rate of up to 409.6 Gb s-1. The single-ended multi-point-to-point CPU channel architecture in DDRX technology remains the same for DDR5 systems. At the specified target data rate, insertion loss, reflections, cross-talk as well as power supply noise become more severe and have to be considered. Using the data buffer receiver front-end of a load-reduced memory module, sophisticated equalisation techniques can be applied to ensure target BER at the increased data rate. In this work, the worst case CPU back-plane channel is analysed to derive requirements for receiver-side equalisation from the channel response characteristics. First, channel impairments such as inter-symbol-interference, reflections from the multi-point channel structure, and crosstalk from neighboring lines are analysed in detail. Based on these results, different correction methods for DDR5 data buffer front-ends are discussed. An architecture with 1-tap FFE in combination with a multi-tap DFE is proposed. Simulation of the architecture using a random input data stream is used to reveal the required DFE tap filter depth to effectively eliminate the dominant ISI and reflection based error components.

  11. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  12. Imaging X-ray detector front-end with high dynamic range: IDeF-X HD

    Science.gov (United States)

    Gevin, O.; Lemaire, O.; Lugiez, F.; Michalowska, A.; Baron, P.; Limousin, O.; Delagnes, E.

    2012-12-01

    Presented circuit, IDeF-X HD (Imaging Detector Front-end) is a member of the IDeF-X ASICs family for space applications. It has been optimized for a half millimeter pitch CdTe or CdZnTe pixelated detector arranged in 16×16 array. It is aimed to operate in the hard X-ray range from few keV up to 250 keV or more. The ASIC has been realized in AMS 0.35 μm CMOS process. The IDeF-X HD is a 32 channel analog front-end with self-triggering capability. The architecture of the analog channel includes a chain of charge sensitive amplifier with continuous reset system and non-stationary noise suppressor, adjustable gain stage, pole-zero cancellation stage, adjustable shaping time low pass filter, baseline holder and peak detector with discriminator. The power consumption of the IDeF-X HD is 800 μW per channel. With the in-channel variable gain stage the nominal 250 keV dynamic range of the ASIC can be extended up to 1 MeV anticipating future applications using thick sensors. Measuring the noise performance without a detector at the input with minimized leakage current (programmable) at the input, we achieved ENC of 33 electrons rms at 10.7 μs peak time. Measurements with CdTe detector show good energy resolution FWHM of 1.1 keV at 60 keV and 4.3 keV at 662 keV with detection threshold below 4 keV. In addition, an absolute temperature sensor has been integrated with resolution of 1.5 °C.

  13. A radiation tolerant Data link board for the ATLAS Tile Cal upgrade

    Science.gov (United States)

    Åkerstedt, H.; Bohm, C.; Muschter, S.; Silverstein, S.; Valdes, E.

    2016-01-01

    This paper describes the latest, full-functionality revision of the high-speed data link board developed for the Phase-2 upgrade of ATLAS hadronic Tile Calorimeter. The link board design is highly redundant, with digital functionality implemented in two Xilinx Kintex-7 FPGAs, and two Molex QSFP+ electro-optic modules with uplinks run at 10 Gbps. The FPGAs are remotely configured through two radiation-hard CERN GBTx deserialisers (GBTx), which also provide the LHC-synchronous system clock. The redundant design eliminates virtually all single-point error modes, and a combination of triple-mode redundancy (TMR), internal and external scrubbing will provide adequate protection against radiation-induced errors. The small portion of the FPGA design that cannot be protected by TMR will be the dominant source of radiation-induced errors, even if that area is small.

  14. Functional Super Read Out Driver Demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter

    CERN Document Server

    Carrió, F; The ATLAS collaboration; Ferrer, A; Fiorini, L; González, V; Hernández, Y; Higón, E; Moreno, P; Sanchis, E; Solans, C; Valero, A; Valls, J

    2011-01-01

    This work presents the implementation of a functional super Read Out Driver (sROD) demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) in the LHC experiment. The proposed front-end for the Phase II Upgrade communicates with back-end electronics using a multifiber optical connector with a data rate of 57.6 Gbps using the GBT protocol. This functional sROD demonstrator aims to help in the understanding of the problems that could arise in the upgrade of back-end electronics. The demonstrator is composed of three different boards that have been developed in the framework of ATLAS activities: the Optical Multiplexer Board (OMB), the Read-Out Driver (ROD) and the Optical Link Card (OLC). This functional sROD demonstrator will be used to develop a prototype, in ATCA format, of the new ROD for the Phase II.

  15. Desenvolupament d'un Front End de mesura per a la caracterització in-vitro de múltiples cultius cel·lulars simultanis

    OpenAIRE

    Jaén Cárceles, Marc

    2010-01-01

    L'objectiu d'aquesta tesi de Màster és desenvolupar una etapa frontal (Front End) per a la mesura de la bioimpedància, basat en Espectroscopia d'Impedància Elèctrica. Front End explicat en els capítols 3 i 4, i Impedància Elèctrica en el capítol 2. Amb aquest sistema es permetrà la monitorització i caracterització de múltiples cultius de cèl·lules in vivo i in vitro. El sentit d'aquesta tesi és el disseny i la seva implementació d'una nova versió de Front End, amb elements c...

  16. Decision feedback equalization for radiation hard data link at 5 Gbps

    Science.gov (United States)

    Wallängen, V.; Garcia-Sciveres, M.

    2017-01-01

    The increased particle collision rate following the upgrade of the Large Hadron Collider (LHC) to an increased luminosity requires an increased readout data speed, especially for the ATLAS pixel detector, located closest to the particle interaction point. For this reason, during the Phase-II upgrade of the ATLAS experiment the output data speed of the pixel front-end chips will be increased from 160 Mbps to 5 Gbps. The increased radiation levels will require a radiation hard data transmission link to be designed to carry this data from the pixel front-end to the off-detector system where it will undergo optical conversion. We propose a receiver utilizing the concept of Decision Feedback Equalization (DFE) to be used in this link, where the number of filter taps can be determined from simulations using S-parameter data from measurements of various customized cable prototypes under characterization as candidates to function as transmission medium between the on-chip data driver and the receiver of the link. A dedicated framework has been set up in Matlab to analyze the S-parameter characteristics for the various cable prototypes and investigate the possibilities for signal recovery and maintained signal integrity using DFE, as well as pre-emphasis and different encoding schemes. The simulation results indicate that DFE could be an excellent choice for expanding the system bandwidth to reach required data speeds with minimal signal distortion.

  17. Simulation study of n-XYTER front-end electronics in overflow situations for early prototyping of detectors in the CBM experiment

    Energy Technology Data Exchange (ETDEWEB)

    Balog, Tomas [GSI Darmstadt (Germany); Collaboration: CBM-Collaboration

    2011-07-01

    In high-rate experiments a situation can occur in which the data rate temporarily exceeds the available bandwidth. With self-triggered front end electronics such overload situations would lead, without further measures, to uncontrolled data losses and potentially large number of incomplete events. Mechanisms needed to control data losses and to ensure complete events can be understood using simulations performed by the hardware description language SystemC. Simulations of a simplified n-XYTER based front-end electronics are presented that give first insight in the behaviour of data flow and data losses in the DAQ system of the CBM experiment.

  18. The new version of the LHCb SOL40-SCA core to drive front-end GBT-SCAs for the LHCb upgrade

    CERN Document Server

    Viana Barbosa, Joao Vitor; Gaspar, Clara

    2018-01-01

    The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

  19. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger. The ATLAS Tile Calorimeter on-detector electronics is housed in the drawers at the back of each of the 256 detector wedges. Each drawer services up to 48 photomultiplier tubes. The new readout system is designed to replace the present system as it will reach component lifetime and radiation tolerance limits making it incompatible with continued use into the HL-LHC era. Wi...

  20. Functional Super Read Out Driver Demonstrator for the Phase II Upgrade of the Atlas Tile Calorimeter

    CERN Document Server

    Carrió, F; The ATLAS collaboration; Ferrer, A; González, V; Higón, E; Moreno, P; Sanchis, E; Solans, C; Valero, A; Valls, J

    2011-01-01

    This work presents the implementation of a functional super Read Out Driver (sROD) demonstrator for the Phase II Upgrade of the ATLAS Tile Calorimeter (TileCal) in the LHC experiment. The proposed front-end for the Phase II Upgrade communicates with back-end electronics using a multifiber optical connector with a data rate of 57.6 Gbps using the GBT protocol. This functional sROD demonstrator aims to help in the understanding of the problems that could arise in the upgrade of back-end electronics. The demonstrator is composed of three different boards that have been developed in the framework of ATLAS activities: the Optical Multiplexer Board (OMB), the Read-Out Driver (ROD) and the Optical Link Card (OLC). The first two boards, OMB and ROD, are part of the current back-end system where OMB receives two optical fibers with redundant data from front-end, performs online CRC for data and send to ROD the data from the error-free fiber; and ROD is the main element of the back-end electronics and it is responsible...

  1. ATLAS

    CERN Multimedia

    Akhnazarov, V; Canepa, A; Bremer, J; Burckhart, H; Cattai, A; Voss, R; Hervas, L; Kaplon, J; Nessi, M; Werner, P; Ten kate, H; Tyrvainen, H; Vandelli, W; Krasznahorkay, A; Gray, H; Alvarez gonzalez, B; Eifert, T F; Rolando, G; Oide, H; Barak, L; Glatzer, J; Backhaus, M; Schaefer, D M; Maciejewski, J P; Milic, A; Jin, S; Von torne, E; Limbach, C; Medinnis, M J; Gregor, I; Levonian, S; Schmitt, S; Waananen, A; Monnier, E; Muanza, S G; Pralavorio, P; Talby, M; Tiouchichine, E; Tocut, V M; Rybkin, G; Wang, S; Lacour, D; Laforge, B; Ocariz, J H; Bertoli, W; Malaescu, B; Sbarra, C; Yamamoto, A; Sasaki, O; Koriki, T; Hara, K; Da silva gomes, A; Carvalho maneira, J; Marcalo da palma, A; Chekulaev, S; Tikhomirov, V; Snesarev, A; Buzykaev, A; Maslennikov, A; Peleganchuk, S; Sukharev, A; Kaplan, B E; Swiatlowski, M J; Nef, P D; Schnoor, U; Oakham, G F; Ueno, R; Orr, R S; Abouzeid, O; Haug, S; Peng, H; Kus, V; Vitek, M; Temming, K K; Dang, N P; Meier, K; Schultz-coulon, H; Geisler, M P; Sander, H; Schaefer, U; Ellinghaus, F; Rieke, S; Nussbaumer, A; Liu, Y; Richter, R; Kortner, S; Fernandez-bosman, M; Ullan comes, M; Espinal curull, J; Chiriotti alvarez, S; Caubet serrabou, M; Valladolid gallego, E; Kaci, M; Carrasco vela, N; Lancon, E C; Besson, N E; Gautard, V; Bracinik, J; Bartsch, V C; Potter, C J; Lester, C G; Moeller, V A; Rosten, J; Crooks, D; Mathieson, K; Houston, S C; Wright, M; Jones, T W; Harris, O B; Byatt, T J; Dobson, E; Hodgson, P; Hodgkinson, M C; Dris, M; Karakostas, K; Ntekas, K; Oren, D; Duchovni, E; Etzion, E; Oren, Y; Ferrer, L M; Testa, M; Doria, A; Merola, L; Sekhniaidze, G; Giordano, R; Ricciardi, S; Milazzo, A; Falciano, S; De pedis, D; Dionisi, C; Veneziano, S; Cardarelli, R; Verzegnassi, C; Soualah, R; Ochi, A; Ohshima, T; Kishiki, S; Linde, F L; Vreeswijk, M; Werneke, P; Muijs, A; Vankov, P H; Jansweijer, P P M; Dale, O; Lund, E; Bruckman de renstrom, P; Dabrowski, W; Adamek, J D; Wolters, H; Micu, L; Pantea, D; Tudorache, V; Mjoernmark, J; Klimek, P J; Ferrari, A; Abdinov, O; Akhoundov, A; Hashimov, R; Shelkov, G; Khubua, J; Ladygin, E; Lazarev, A; Glagolev, V; Dedovich, D; Lykasov, G; Zhemchugov, A; Zolnikov, Y; Ryabenko, M; Sivoklokov, S; Vasilyev, I; Shalimov, A; Lobanov, M; Paramoshkina, E; Mosidze, M; Bingul, A; Nodulman, L J; Guarino, V J; Yoshida, R; Drake, G R; Calafiura, P; Haber, C; Quarrie, D R; Alonso, J R; Anderson, C; Evans, H; Lammers, S W; Baubock, M; Anderson, K; Petti, R; Suhr, C A; Linnemann, J T; Richards, R A; Tollefson, K A; Holzbauer, J L; Stoker, D P; Pier, S; Nelson, A J; Isakov, V; Martin, A J; Adelman, J A; Paganini, M; Gutierrez, P; Snow, J M; Pearson, B L; Cleland, W E; Savinov, V; Wong, W; Goodson, J J; Li, H; Lacey, R A; Gordeev, A; Gordon, H; Lanni, F; Nevski, P; Rescia, S; Kierstead, J A; Liu, Z; Yu, W W H; Bensinger, J; Hashemi, K S; Bogavac, D; Cindro, V; Hoeferkamp, M R; Coelli, S; Iodice, M; Piegaia, R N; Alonso, F; Wahlberg, H P; Barberio, E L; Limosani, A; Rodd, N L; Jennens, D T; Hill, E C; Pospisil, S; Smolek, K; Schaile, D A; Rauscher, F G; Adomeit, S; Mattig, P M; Wahlen, H; Volkmer, F; Calvente lopez, S; Sanchis peris, E J; Pallin, D; Podlyski, F; Says, L; Boumediene, D E; Scott, W; Phillips, P W; Greenall, A; Turner, P; Gwilliam, C B; Kluge, T; Wrona, B; Sellers, G J; Millward, G; Adragna, P; Hartin, A; Alpigiani, C; Piccaro, E; Bret cano, M; Hughes jones, R E; Mercer, D; Oh, A; Chavda, V S; Carminati, L; Cavasinni, V; Fedin, O; Patrichev, S; Ryabov, Y; Nesterov, S; Grebenyuk, O; Sasso, J; Mahmood, H; Polsdofer, E; Dai, T; Ferretti, C; Liu, H; Hegazy, K H; Benjamin, D P; Zobernig, G; Ban, J; Brooijmans, G H; Keener, P; Williams, H H; Le geyt, B C; Hines, E J; Fadeyev, V; Schumm, B A; Law, A T; Kuhl, A D; Neubauer, M S; Shang, R; Gagliardi, G; Calabro, D; Conta, C; Zinna, M; Jones, G; Li, J; Stradling, A R; Hadavand, H K; Mcguigan, P; Chiu, P; Baldelomar, E; Stroynowski, R A; Kehoe, R L; De groot, N; Timmermans, C; Lach-heb, F; Addy, T N; Nakano, I; Moreno lopez, D; Grosse-knetter, J; Tyson, B; Rude, G D; Tafirout, R; Benoit, P; Danielsson, H O; Elsing, M; Fassnacht, P; Froidevaux, D; Ganis, G; Gorini, B; Lasseur, C; Lehmann miotto, G; Kollar, D; Aleksa, M; Sfyrla, A; Duehrssen-debling, K; Fressard-batraneanu, S; Van der ster, D C; Bortolin, C; Schumacher, J; Mentink, M; Geich-gimbel, C; Yau wong, K H; Lafaye, R; Crepe-renaudin, S; Albrand, S; Hoffmann, D; Pangaud, P; Meessen, C; Hrivnac, J; Vernay, E; Perus, A; Henrot versille, S L; Le dortz, O; Derue, F; Piccinini, M; Polini, A; Terada, S; Arai, Y; Ikeno, M; Fujii, H; Nagano, K; Ukegawa, F; Aguilar saavedra, J A; Conde muino, P; Castro, N F; Eremin, V; Kopytine, M; Sulin, V; Tsukerman, I; Korol, A; Nemethy, P; Bartoldus, R; Glatte, A; Chelsky, S; Van nieuwkoop, J; Bellerive, A; Sinervo, J K; Battaglia, A; Barbier, G J; Pohl, M; Rosselet, L; Alexandre, G B; Prokoshin, F; Pezoa rivera, R A; Batkova, L; Kladiva, E; Stastny, J; Kubes, T; Vidlakova, Z; Esch, H; Homann, M; Herten, L G; Zimmermann, S U; Pfeifer, B; Stenzel, H; Andrei, G V; Wessels, M; Buescher, V; Kleinknecht, K; Fiedler, F M; Schroeder, C D; Fernandez, E; Mir martinez, L; Vorwerk, V; Bernabeu verdu, J; Salt, J; Civera navarrete, J V; Bernard, R; Berriaud, C P; Chevalier, L P; Hubbard, R; Schune, P; Nikolopoulos, K; Batley, J R; Brochu, F M; Phillips, A W; Teixeira-dias, P J; Rose, M B D; Buttar, C; Buckley, A G; Nurse, E L; Larner, A B; Boddy, C; Henderson, J; Costanzo, D; Tarem, S; Maccarrone, G; Laurelli, P F; Alviggi, M; Chiaramonte, R; Izzo, V; Palumbo, V; Fraternali, M; Crosetti, G; Marchese, F; Yamaguchi, Y; Hessey, N P; Mechnich, J M; Liebig, W; Kastanas, K A; Sjursen, T B; Zalieckas, J; Cameron, D G; Banka, P; Kowalewska, A B; Dwuznik, M; Mindur, B; Boldea, V; Hedberg, V; Smirnova, O; Sellden, B; Allahverdiyev, T; Gornushkin, Y; Koultchitski, I; Tokmenin, V; Chizhov, M; Gongadze, A; Khramov, E; Sadykov, R; Krasnoslobodtsev, I; Smirnova, L; Kramarenko, V; Minaenko, A; Zenin, O; Beddall, A J; Ozcan, E V; Hou, S; Wang, S; Moyse, E; Willocq, S; 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Wickens, F J; Martin, V J; Jackson, J N; Prichard, P; Kretzschmar, J; Martin, A J; Walker, C J; Potter, K M; Kourkoumelis, C; Tzamarias, S; Houiris, A G; Iliadis, D; Fanti, M; Bertolucci, F; Maleev, V; Sultanov, S; Rosenberg, E I; Krumnack, N E; Bieganek, C; Diehl, E B; Mc kee, S P; Eppig, A P; Harper, D R; Liu, C; Schwarz, T A; Mazor, B; Looper, K A; Wiedenmann, W; Huang, P; Stahlman, J M; Battaglia, M; Nielsen, J A; Zhao, T; Khanov, A; Kaushik, V S; Vichou, E; Liss, A M; Gemme, C; Morettini, P; Parodi, F; Passaggio, S; Rossi, L; Kuzhir, P; Ignatenko, A; Ferrari, R; Spairani, M; Pianori, E; Sekula, S J; Firan, A I; Cao, T; Hetherly, J W; Gouighri, M; Vassilakopoulos, V; Long, M C; Shimojima, M; Sawyer, L H; Brummett, R E; Losada, M A; Schorlemmer, A L; Mantoani, M; Bawa, H S; Mornacchi, G; Nicquevert, B; Palestini, S; Stapnes, S; Veness, R; Kotamaki, M J; Sorde, C; Iengo, P; Campana, S; Goossens, L; Zajacova, Z; Pribyl, L; Poveda torres, J; Marzin, A; Conti, G; Carrillo montoya, G D; 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Mcgarvie, S A; Kilvington, G J; D'auria, S; O'shea, V; Mcglone, H M; Fox, H; Henderson, R; Kartvelishvili, V; Davies, B; Sherwood, P; Fraser, J T; Lancaster, M A; Tseng, J C; Hays, C P; Apolle, R; Dixon, S D; Parker, K A; Gazis, E; Papadopoulou, T; Panagiotopoulou, E; Karastathis, N; Hershenhorn, A D; Milov, A; Groth-jensen, J; Bilokon, H; Miscetti, S; Canale, V; Rebuzzi, D M; Capua, M; Bagnaia, P; De salvo, A; Gentile, S; Safai tehrani, F; Solfaroli camillocci, E; Sasao, N; Tsunada, K; Massaro, G; Magrath, C A; Van kesteren, Z; Beker, M G; Van den wollenberg, W; Bugge, L; Buran, T; Read, A L; Gjelsten, B K; Banas, E A; Turnau, J; Derendarz, D K; Kisielewska, D; Chesneanu, D; Rotaru, M; Maurer, J B; Wong, M L; Lund-jensen, B; Asman, B; Jon-and, K B; Silverstein, S B; Johansen, M; Alexandrov, I; Iatsounenko, I; Krumshteyn, Z; Peshekhonov, V; Rybaltchenko, K; Samoylov, V; Cheplakov, A; Kekelidze, G; Lyablin, M; Teterine, V; Bednyakov, V; Kruchonak, U; Shiyakova, M M; Demichev, M; Denisov, S P; Fenyuk, A; Djobava, T; Salukvadze, G; Cetin, S A; Brau, B P; Pais, P R; Proudfoot, J; Van gemmeren, P; Zhang, Q; Beringer, J A; Ely, R; Leggett, C; Pengg, F X; Barnett, M R; Quick, R E; Williams, S; Gardner jr, R W; Huston, J; Brock, R; Wanotayaroj, C; Unel, G N; Taffard, A C; Frate, M; Baker, K O; Tipton, P L; Hutchison, A; Walsh, B J; Norberg, S R; Su, J; Tsybyshev, D; Caballero bejar, J; Ernst, M U; Wellenstein, H; Vudragovic, D; Vidic, I; Gorelov, I V; Toms, K; Alimonti, G; Petrucci, F; Kolanoski, H; Smith, J; Jeng, G; Watson, I J; Guimaraes ferreira, F; Miranda vieira xavier, F; Araujo pereira, R; Poffenberger, P; Sopko, V; Elmsheuser, J; Wittkowski, J; Glitza, K; Gorfine, G W; Ferrer soria, A; Fuster verdu, J A; Sanchis lozano, A; Reinmuth, G; Busato, E; Haywood, S J; Mcmahon, S J; Qian, W; Villani, E G; Laycock, P J; Poll, A J; Rizvi, E S; Foster, J M; Loebinger, F; Forti, A; Plano, W G; Brown, G J A; Kordas, K; Vegni, G; Ohsugi, T; Iwata, Y; Cherkaoui el moursli, R; Sahin, M; Akyazi, E; Carlsen, A; Kanwal, B; Cochran jr, J H; Aronnax, M V; Lockner, M J; Zhou, B; Levin, D S; Weaverdyck, C J; Grom, G F; Rudge, A; Ebenstein, W L; Jia, B; Yamaoka, J; Jared, R C; Wu, S L; Banerjee, S; Lu, Q; Hughes, E W; Alkire, S P; Degenhardt, J D; Lipeles, E D; Spencer, E N; Savine, A; Cheu, E C; Lampl, W; Veatch, J R; Roberts, K; Atkinson, M J; Odino, G A; Polesello, G; Martin, T; White, A P; Stephens, R; Grinbaum sarkisyan, E; Vartapetian, A; Yu, J; Sosebee, M; Thilagar, P A; Spurlock, B; Bonde, R; Filthaut, F; Klok, P; Hoummada, A; Ouchrif, M; Pellegrini, G; Rafi tatjer, J M; Navarro, G A; Blumenschein, U; Weingarten, J C; Mueller, D; Graber, L; Gao, Y; Bode, A; Capeans garrido, M D M; Carli, T; Wells, P; Beltramello, O; Vuillermet, R; Dudarev, A; Salzburger, A; Torchiani, C I; Serfon, C L G; Sloper, J E; Duperrier, G; Lilova, P T; Knecht, M O; Lassnig, M; Anders, G; Deviveiros, P; Young, C; Sforza, F; Shaochen, C; Lu, F; Wermes, N; Wienemann, P; Schwindt, T; Hansen, P H; Hansen, J B; Pingel, A M; Massol, N; Elles, S L; Hallewell, G D; Rozanov, A; Vacavant, L; Fournier, D A; Poggioli, L; Puzo, P M; Tanaka, R; Escalier, M A; Makovec, N; Rezynkina, K; De cecco, S; Cavalleri, P G; Massa, I; Zoccoli, A; Tanaka, S; Odaka, S; Mitsui, S; Tomasio pina, J A; Santos, H F; Satsounkevitch, I; Harkusha, S; Baranov, S; Nechaeva, P; Kayumov, F; Kazanin, V; Asai, M; Mount, R P; Nelson, T K; Smith, D; Kenney, C J; Malone, C M; Kobel, M; Friedrich, F; Grohs, J P; Jais, W J; O'neil, D C; Warburton, A T; Vincter, M; Mccarthy, T G; Groer, L S; Pham, Q T; Taylor, W J; La marra, D; Perrin, E; Wu, X; Bell, W H; Delitzsch, C M; Feng, C; Zhu, C; Tokar, S; Bruncko, D; Kupco, A; Marcisovsky, M; Jakoubek, T; Bruneliere, R; Aktas, A; Narrias villar, D I; Tapprogge, S; Mattmann, J; Kroha, H; Crespo, J; Korolkov, I; Cavallaro, E; Cabrera urban, S; Mitsou, V; Kozanecki, W; Mansoulie, B; Pabot, Y; Etienvre, A; Bauer, F; Chevallier, F; Bouty, A R; Watkins, P; Watson, A; Faulkner, P J W; Curtis, C J; Murillo quijada, J A; Grout, Z J; Chapman, J D; Cowan, G D; George, S; Boisvert, V; Mcmahon, T R; Doyle, A T; Thompson, S A; Britton, D; Smizanska, M; Campanelli, M; Butterworth, J M; Loken, J; Renton, P; Barr, A J; Issever, C; Short, D; Crispin ortuzar, M; Tovey, D R; French, R; Rozen, Y; Alexander, G; Kreisel, A; Conventi, F; Raulo, A; Schioppa, M; Susinno, G; Tassi, E; Giagu, S; Luci, C; Nisati, A; Cobal, M; Ishikawa, A; Jinnouchi, O; Bos, K; Verkerke, W; Vermeulen, J; Van vulpen, I B; Kieft, G; Mora, K D; Olsen, F; Rohne, O M; Pajchel, K; Nilsen, J K; Wosiek, B K; Wozniak, K W; Badescu, E; Jinaru, A; Bohm, C; Johansson, E K; Sjoelin, J B R; Clement, C; Buszello, C P; Huseynova, D; Boyko, I; Popov, B; Poukhov, O; Vinogradov, V; Tsiareshka, P; Skvorodnev, N; Soldatov, A; Chuguev, A; Gushchin, V; Yazici, E; Lutz, M S; Malon, D; Vanyashin, A; Lavrijsen, W; Spieler, H; Biesiada, J L; Bahr, M; Kong, J; Tatarkhanov, M; Ogren, H; Van kooten, R J; Cwetanski, P; Butler, J M; Shank, J T; Chakraborty, D; Ermoline, I; Sinev, N; Whiteson, D O; Corso radu, A; Huang, J; Werth, M P; Kastoryano, M; Meirose da silva costa, B; Namasivayam, H; Hobbs, J D; Schamberger jr, R D; Guo, F; Potekhin, M; Popovic, D; Gorisek, A; Sokhrannyi, G; Hofsajer, I W; Mandelli, L; Ceradini, F; Graziani, E; Giorgi, F; Zur nedden, M E G; Grancagnolo, S; Volpi, M; Nunes hanninger, G; Rados, P K; Milesi, M; Cuthbert, C J; Black, C W; Fink grael, F; Fincke-keeler, M; Keeler, R; Kowalewski, R V; Berghaus, F O; Qi, M; Davidek, T; Tas, P; Jakubek, J; Duckeck, G; Walker, R; Mitterer, C A; Harenberg, T; Sandvoss, S A; Del peso, J; Llorente merino, J; Gonzalez millan, V; Irles quiles, A; Crouau, M; Gris, P L Y; Liauzu, S; Romano saez, S M; Gallop, B J; Jones, T J; Austin, N C; Morris, J; Duerdoth, I; Thompson, R J; Kelly, M P; Leisos, A; Garas, A; Pizio, C; Venda pinto, B A; Kudin, L; Qian, J; Wilson, A W; Mietlicki, D; Long, J D; Sang, Z; Arms, K E; Rahimi, A M; Moss, J J; Oh, S H; Parker, S I; Parsons, J; Cunitz, H; Vanguri, R S; Sadrozinski, H; Lockman, W S; Martinez-mc kinney, G; Goussiou, A; Jones, A; Lie, K; Hasegawa, Y; Olcese, M; Gilewsky, V; Harrison, P F; Janus, M; Spangenberg, M; De, K; Ozturk, N; Pal, A K; Darmora, S; Bullock, D J; Oviawe, O; Derkaoui, J E; Rahal, G; Sircar, A; Frey, A S; Stolte, P; Rosien, N; Zoch, K; Li, L; Schouten, D W; Catinaccio, A; Ciapetti, M; Delruelle, N; Ellis, N; Farthouat, P; Hoecker, A; Klioutchnikova, T; Macina, D; Malyukov, S; Spiwoks, R D; Unal, G P; Vandoni, G; Petersen, B A; Pommes, K; Nairz, A M; Wengler, T; Mladenov, D; Solans sanchez, C A; Lantzsch, K; Schmieden, K; Jakobsen, S; Ritsch, E; Sciuccati, A; Alves dos santos, A M; Ouyang, Q; Zhou, M; Brock, I C; Janssen, J; Katzy, J; Anders, C F; Nilsson, B S; Bazan, A; Di ciaccio, L; Yildizkaya, T; Collot, J; Malek, F; Trocme, B S; Breugnon, P; Godiot, S; Adam bourdarios, C; Coulon, J; Duflot, L; Petroff, P G; Zerwas, D; Lieuvin, M; Calderini, G; Laporte, D; Ocariz, J; Gabrielli, A; Ohska, T K; Kurochkin, Y; Kantserov, V; Vasilyeva, L; Speransky, M; Smirnov, S; Antonov, A; Bulekov, O; Tikhonov, Y; Sargsyan, L; Vardanyan, G; Budick, B; Kocian, M L; Luitz, S; Young, C C; Grenier, P J; Kelsey, M; Black, J E; Kneringer, E; Jussel, P; Horton, A J; Beaudry, J; Chandra, A; Ereditato, A; Topfel, C M; Mathieu, R; Bucci, F; Muenstermann, D; White, R M; He, M; Urban, J; Straka, M; Vrba, V; Schumacher, M; Parzefall, U; Mahboubi, K; Sommer, P O; Koepke, L H; Bethke, S; Moser, H; Wiesmann, M; Walkowiak, W A; Fleck, I J; Martinez-perez, M; Sanchez sanchez, C A; Jorgensen roca, S; Accion garcia, E; Sainz ruiz, C A; Valls ferrer, J A; Amoros vicente, G; Vives torrescasana, R; Ouraou, A; Formica, A; Hassani, S; Watson, M F; Cottin buracchio, G F; Bussey, P J; Saxon, D; Ferrando, J E; Collins-tooth, C L; Hall, D C; Cuhadar donszelmann, T; Dawson, I; Duxfield, R; Argyropoulos, T; Brodet, E; Livneh, R; Shougaev, K; Reinherz, E I; Guttman, N; Beretta, M M; Vilucchi, E; Aloisio, A; Patricelli, S; Caprio, M; Cevenini, F; De vecchi, C; Livan, M; Rimoldi, A; Vercesi, V; Ayad, R; Mastroberardino, A; Ciapetti, G; Luminari, L; Rescigno, M; Santonico, R; Salamon, A; Del papa, C; Kurashige, H; Homma, Y; Tomoto, M; Horii, Y; Sugaya, Y; Hanagaki, K; Bobbink, G; Kluit, P M; Koffeman, E N; Van eijk, B; Lee, H; Eigen, G; Dorholt, O; Strandlie, A; Strzempek, P B; Dita, S; Stoicea, G; Chitan, A; Leven, S S; Moa, T; Brenner, R; Ekelof, T J C; Olshevskiy, A; Roumiantsev, V; Chlachidze, G; Zimine, N; Gusakov, Y; Grigalashvili, N; Mineev, M; Potrap, I; Barashkou, A; Shoukavy, D; Shaykhatdenov, B; Pikelner, A; Gladilin, L; Ammosov, V; Abramov, A; Arik, M; Sahinsoy, M; Uysal, Z; Azizi, K; Hotinli, S C; Zhou, S; Berger, E; Blair, R; Underwood, D G; Einsweiler, K; Garcia-sciveres, M A; Siegrist, J L; Kipnis, I; Dahl, O; Holland, S; Barbaro galtieri, A; Smith, P T; Parua, N; Franklin, M; Mercurio, K M; Tong, B; Pod, E; Cole, S G; Hopkins, W H; Guest, D H; Severini, H; Marsicano, J J; Abbott, B K; Wang, Q; Lissauer, D; Ma, H; Takai, H; Rajagopalan, S; Protopopescu, S D; Snyder, S S; Undrus, A; Popescu, R N; Begel, M A; Blocker, C A; Amelung, C; Mandic, I; Macek, B; Tucker, B H; Citterio, M; Troncon, C; Orestano, D; Taccini, C; Romeo, G L; Dova, M T; Taylor, G N; Gesualdi manhaes, A; Mcpherson, R A; Sobie, R; Taylor, R P; Dolezal, Z; Kodys, P; Slovak, R; Sopko, B; Vacek, V; Sanders, M P; Hertenberger, R; Meineck, C; Becks, K; Kind, P; Sandhoff, M; Cantero garcia, J; De la torre perez, H; Castillo gimenez, V; Ros, E; Hernandez jimenez, Y; Chadelas, R; Santoni, C; Washbrook, A J; O'brien, B J; Wynne, B M; Mehta, A; Vossebeld, J H; Landon, M; Teixeira dias castanheira, M; Cerrito, L; Keates, J R; Fassouliotis, D; Chardalas, M; Manousos, A; Grachev, V; Seliverstov, D; Sedykh, E; Cakir, O; Ciftci, R; Edson, W; Prell, S A; Rosati, M; Stroman, T; Jiang, H; Neal, H A; Li, X; Gan, K K; Smith, D S; Kruse, M C; Ko, B R; Leung fook cheong, A M; Cole, B; Angerami, A R; Greene, Z S; Kroll, J I; Van berg, R P; Forbush, D A; Lubatti, H; Raisher, J; Shupe, M A; Wolin, S; Oshita, H; Gaudio, G; Das, R; Konig, A C; Croft, V A; Harvey, A; Maaroufi, F; Melo, I; Greenwood jr, Z D; Shabalina, E; Mchedlidze, G; Drechsler, E; Rieger, J K; Blackston, M; Colombo, T

    2002-01-01

    % ATLAS \\\\ \\\\ ATLAS is a general-purpose experiment for recording proton-proton collisions at LHC. The ATLAS collaboration consists of 144 participating institutions (June 1998) with more than 1750~physicists and engineers (700 from non-Member States). The detector design has been optimized to cover the largest possible range of LHC physics: searches for Higgs bosons and alternative schemes for the spontaneous symmetry-breaking mechanism; searches for supersymmetric particles, new gauge bosons, leptoquarks, and quark and lepton compositeness indicating extensions to the Standard Model and new physics beyond it; studies of the origin of CP violation via high-precision measurements of CP-violating B-decays; high-precision measurements of the third quark family such as the top-quark mass and decay properties, rare decays of B-hadrons, spectroscopy of rare B-hadrons, and $ B ^0 _{s} $-mixing. \\\\ \\\\The ATLAS dectector, shown in the Figure includes an inner tracking detector inside a 2~T~solenoid providing an axial...

  2. Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

    CERN Document Server

    de La Taille, C

    2008-01-01

    The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

  3. High strength steels, stiffness of vehicle front-end structure, and risk of injury to rear seat occupants.

    Science.gov (United States)

    Sahraei, Elham; Digges, Kennerly; Marzougui, Dhafer; Roddis, Kim

    2014-05-01

    Previous research has shown that rear seat occupant protection has decreased over model years, and front-end stiffness is a possible factor causing this trend. In this research, the effects of a change in stiffness on protection of rear seat occupants in frontal crashes were investigated. The stiffness was adjusted by using higher strength steels (DP and TRIP), or thicker metal sheets. Finite element simulations were performed, using an LS Dyna vehicle model coupled with a MADYMO dummy. Simulation results showed that an increase in stiffness, to the extent it happened in recent model years, can increase the risk of AIS3+ head injuries from 4.8% in the original model (with a stiffness of 1,000 N/mm) to 24.2% in a modified model (with a stiffness of 2,356 N/mm). The simulations also showed an increased risk of chest injury from 9.1% in the original model to 11.8% in the modified model. Distribution of injuries from real world accident data confirms the findings of the simulations. Copyright © 2014 Elsevier Ltd. All rights reserved.

  4. An ultrafast front-end ASIC for APD array detectors in X-ray time-resolved experiments

    Science.gov (United States)

    Zhou, Yang-Fan; Li, Qiu-Ju; Liu, Peng; Fan, Lei; Xu, Wei; Tao, Ye; Li, Zhen-Jie

    2017-06-01

    An ultrafast front-end ASIC chip has been developed for APD array detectors in X-ray time-resolved experiments. The chip has five channels: four complete channels and one test channel with an analog output. Each complete channel consists of a preamplifier, a voltage discriminator and an open-drain output driver. A prototype chip has been designed and fabricated using 0.13 μm CMOS technology with a chip size of 1.3 mm × 1.9 mm. The electrical characterizations of the circuit demonstrate a very good intrinsic time resolution (rms) on the output pulse leading edge, with the test result better than 30 ps for high input signal charges (> 75 fC) and better than 100 ps for low input signal charges (30-75 fC), while keeping a low power consumption of 5 mW per complete channel. Supported by the National Natural Science Foundation of China (11605227), High Energy Photon Source-Test Facility Project, and the State Key Laboratory of Particle Detection and Electronics. This research used resources of the BSRF.

  5. A Study of the Effect of the Front-End Styling of Sport Utility Vehicles on Pedestrian Head Injuries

    Directory of Open Access Journals (Sweden)

    Guanjun Zhang

    2018-01-01

    Full Text Available Background. The number of sport utility vehicles (SUVs on China market is continuously increasing. It is necessary to investigate the relationships between the front-end styling features of SUVs and head injuries at the styling design stage for improving the pedestrian protection performance and product development efficiency. Methods. Styling feature parameters were extracted from the SUV side contour line. And simplified finite element models were established based on the 78 SUV side contour lines. Pedestrian headform impact simulations were performed and validated. The head injury criterion of 15 ms (HIC15 at four wrap-around distances was obtained. A multiple linear regression analysis method was employed to describe the relationships between the styling feature parameters and the HIC15 at each impact point. Results. The relationship between the selected styling features and the HIC15 showed reasonable correlations, and the regression models and the selected independent variables showed statistical significance. Conclusions. The regression equations obtained by multiple linear regression can be used to assess the performance of SUV styling in protecting pedestrians’ heads and provide styling designers with technical guidance regarding their artistic creations.

  6. Analog Circuit Design Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

    CERN Document Server

    Roermund, Arthur; Baschirotto, Andrea

    2012-01-01

    The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design.  Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of Low-Voltage Low-Power Data Converters - Chaired by Prof. Anderea Baschirotto, University of Milan-Bicocca Short Range Wireless Front-Ends - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology Power management and DC-DC - Chaired by Prof. M. Steyaert, Katholieke University Leuven Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

  7. An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

    Science.gov (United States)

    Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

    2017-07-01

    This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

  8. Exploring the mechanisms of vehicle front-end shape on pedestrian head injuries caused by ground impact.

    Science.gov (United States)

    Yin, Sha; Li, Jiani; Xu, Jun

    2017-09-01

    In pedestrian-vehicle accidents, pedestrians typically suffer from secondary impact with the ground after the primary contact with vehicles. However, information about the fundamental mechanism of pedestrian head injury from ground impact remains minimal, thereby hindering further improvement in pedestrian safety. This study addresses this issue by using multi-body modeling and computation to investigate the influence of vehicle front-end shape on pedestrian safety. Accordingly, a simulation matrix is constructed to vary bonnet leading-edge height, bonnet length, bonnet angle, and windshield angle. Subsequently, a set of 315 pedestrian-vehicle crash simulations are conducted using the multi-body simulation software MADYMO. Three vehicle velocities, i.e., 20, 30, and 40km/h, are set as the scenarios. Results show that the top governing factor is bonnet leading-edge height. The posture and head injury at the instant of head ground impact vary dramatically with increasing height because of the significant rise of the body bending point and the movement of the collision point. The bonnet angle is the second dominant factor that affects head-ground injury, followed by bonnet length and windshield angle. The results may elucidate one of the critical barriers to understanding head injury caused by ground impact and provide a solid theoretical guideline for considering pedestrian safety in vehicle design. Copyright © 2017 Elsevier Ltd. All rights reserved.

  9. LHCb: Dynamically Adaptive Header Generator and Front-End Source Emulator for a 100 Gbps FPGA Based DAQ

    CERN Multimedia

    Srikanth, S

    2014-01-01

    The proposed upgrade for the LHCb experiment envisages a system of 500 Data sources each generating data at 100 Gbps, the acquisition and processing of which is a big challenge even for the current state of the art FPGAs. This requires an FPGA DAQ module that not only handles the data generated by the experiment but also is versatile enough to dynamically adapt to potential inadequacies of other components like the network and PCs. Such a module needs to maintain real time operation while at the same time maintaining system stability and overall data integrity. This also creates a need for a Front-end source Emulator capable of generating the various data patterns, that acts as a testbed to validate the functionality and performance of the Header Generator. The rest of the abstract briefly describes these modules and their implementation. The Header Generator is used to packetize the streaming data from the detectors before it is sent to the PCs for further processing. This is achieved by continuously scannin...

  10. Image based overlay measurement improvements of 28nm FD-SOI CMOS front-end critical steps

    Science.gov (United States)

    Dettoni, F.; Shapoval, T.; Bouyssou, R.; Itzkovich, T.; Haupt, R.; Dezauzier, C.

    2017-03-01

    Technology shrinkage leads to tight specifications in advanced semiconductor industries. For several years', metrology for lithography has been a key technology to address this challenge and to improve yield. More specifically overlay metrology is the object of special attention for tool suppliers and semiconductor manufacturers. This work focuses on Image Based Overlay (IBO) metrology for 28 nm FD-SOI CMOS front-end critical steps (gate and contact). With Overlay specifications below 10 nm, accuracy of the measurement is critical. In this study we show specific cases where target designs need to be optimized in order to minimize process effects (CMP, etch, deposition, etc.) that could lead to overlay measurement errors. Another important aspect of the metrology target is that its design must be device-like in order to better control and correct overlay errors leading to yield loss. Methodologies to optimize overlay metrology recipes are also presented. If the process effects cannot be removed entirely by target design optimization, recipe parameters have to be carefully chosen and controlled to minimize the influence of the target imperfection on measured overlay. With target asymmetry being one of the main contributors to those residual overlay measurement errors the Qmerit accuracy flag can be used to quantify the measurement error and recipe parameters can be set accordingly in order to minimize the target asymmetry impact. Reference technique measurements (CD-SEM) were used to check accuracy of the optimized overlay measurements.

  11. A low-phase-noise wide-band CMOS quadrature VCO for multi-standard RF front-ends

    DEFF Research Database (Denmark)

    Fard, Ali; Andreani, Pietro

    2005-01-01

    A low phase noise CMOS LC quadrature VCO (QVCO) with a wide frequency range of 3.6-5.6 GHz, designed in a standard 0.18 μm process for multi-standard front-ends, is presented. A significant advantage of the topology is the larger oscillation amplitude when compared to other conventional QVCO...... structures. The QVCO is compared to a double cross-coupled LC-tank differential oscillator, both in theory and experiments, for evaluation of its phase noise, providing a good insight into its performance. The measured data displays up to 2 dBc/Hz lower phase noise in the 1/f2 region for the QVCO, when...... consuming twice the current of the differential VCO, based on an identical LC-tank. Experimental results on the QVCO show a phase noise level of -127.5 dBc/Hz at 3 MHz offset from a 5.6 GHz carrier while dissipating 8 mA of current, resulting in a figure of merit of 181.3 dBc/Hz....

  12. Explosion bonding of dissimilar materials for fabricating APS front end components: Analysis of metallurgical and mechanical properties and UHV applications

    International Nuclear Information System (INIS)

    Li, Yuheng; Shu, Deming; Kuzay, T.M.

    1994-01-01

    The front end beamline section contains photon shutters and fixed masks. These components are made of OFHC copper and GlidCOP AL-15. Stainless steels (304 or 316) are also used for connecting photon shutters and fixed masks to other components that operate in the ultrahigh vacuum system. All these dissimilar materials need to be joined together. However, bonding these dissimilar materials is very difficult because of their different mechanical and thermal properties and incompatible metallurgical properties. Explosion bonding is a bonding method in which the controlled energy of a detonating explosive is used to create a metallurgical bond between two or more similar or dissimilar materials. No intermediate filler metal, for example, a brazing compound or soldering alloy, is needed to promote bonding, and no external heat need be applied. A study of the metallurgical and mechanical properties and YGV applications of GlidCop AL-15, OFHC copper, and 304 stainless steel explosion-bonded joints has been done. This report contains five parts: an ultrasonic examination of explosion-bonded joints and a standard setup; mechanical-property and thermal-cycle tests of GlidCop AL-15/304 stainless steel explosion-bonded joints; leak tests of a GlidCop AL-15/304 stainless steel explosion-bonded interfaces for UHV application; metallurgical examination of explosion-bonded interfaces and failure analysis, and discussion and conclusion

  13. A GEM-TPC prototype with low-Noise highly integrated front-end electronics for linear collider studies

    CERN Document Server

    Kappler, Steffen; Kaminski, Jochen; Ledermann, Bernhard; Müller, Thomas; Ronan, Michael T; Ropelewski, Leszek; Sauli, Fabio; Settles, Ronald

    2004-01-01

    Connected to the linear collider project, studies on the readout of time projection chambers (TPCs) based on the gas electron multiplier (GEM) are ongoing. Higher granularity and intrinsically suppressed ion feedback are the major advantages of this technology. After a short discussion of these issues, we present the design of a small and very flexible TPC prototype, whose cylindrical drift volume can be equipped with endcaps of different gas detector types. An endcap with multi-GEM readout is currently set up and successfully operated with a low-noise highly integrated front-end electronics. We discuss results of measurements with this system in high intensity particle beams at CERN, where 99.3 plus or minus 0.2% single-pad-row efficiency could be achieved at an effective gain of 2.5 multiplied by 10**3 only, and spatial resolutions down to 63 plus or minus 3 mum could be demonstrated. Finally, these results are extrapolated to the high magnetic field in a linear collider TPC. 5 Refs.

  14. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed on purpose to execute pattern matching with a high degree of parallelism. It finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report on the performance of the intermedia...

  15. The Serial Link Processor for the Fast TracKer (FTK) at ATLAS

    CERN Document Server

    Annovi, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Biesuz, N; Billereau, W; Combe, J M; Citterio, M; Citraro, S; Crescioli, F; Dimas, D; Donati, S; Gentsos, C; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Rossi, E; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A; Vulliez, P

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problem inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. We report also on the performance of a first prototype based on the use of a min@sic AM chip, a small but complete version ...

  16. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Biesuz, Nicolo Vladi; The ATLAS collaboration; Luciano, Pierluigi; Magalotti, Daniel; Rossi, Enrico

    2015-01-01

    The Associative Memory (AM) system of the Fast Tracker (FTK) processor has been designed to perform pattern matching using the hit information of the ATLAS experiment silicon tracker. The AM is the heart of FTK and is mainly based on the use of ASICs (AM chips) designed to execute pattern matching with a high degree of parallelism. The AM system finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside FTK, multiple board and chip designs have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 828 2 Gbit/s serial links for a total in/out bandwidth of 56 Gb/s. This paper reports on the design of the Serial Link Processor consisting of two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. ...

  17. The Serial Link Processor for the Fast TracKer (FTK) processor at ATLAS

    CERN Document Server

    Andreani, A; The ATLAS collaboration; Beccherle, R; Beretta, M; Cipriani, R; Citraro, S; Citterio, M; Colombo, A; Crescioli, F; Dimas, D; Donati, S; Giannetti, P; Kordas, K; Lanza, A; Liberali, V; Luciano, P; Magalotti, D; Neroutsos, P; Nikolaidis, S; Piendibene, M; Sakellariou, A; Shojaii, S; Sotiropoulou, C-L; Stabile, A

    2014-01-01

    The Associative Memory (AM) system of the FTK processor has been designed to perform pattern matching using the hit information of the ATLAS silicon tracker. The AM is the heart of the FTK and it finds track candidates at low resolution that are seeds for a full resolution track fitting. To solve the very challenging data traffic problems inside the FTK, multiple designs and tests have been performed. The currently proposed solution is named the “Serial Link Processor” and is based on an extremely powerful network of 2 Gb/s serial links. This paper reports on the design of the Serial Link Processor consisting of the AM chip, an ASIC designed and optimized to perform pattern matching, and two types of boards, the Local Associative Memory Board (LAMB), a mezzanine where the AM chips are mounted, and the Associative Memory Board (AMB), a 9U VME board which holds and exercises four LAMBs. Special relevance will be given to the AMchip design that includes two custom cells optimized for low consumption. We repo...

  18. AUTOMOTIVE DIESEL MAINTENANCE 1. UNIT XIX, I--ENGINE TUNE-UP--CUMMINS DIESEL ENGINE, II--FRONT END SUSPENSION AND AXLES.

    Science.gov (United States)

    Minnesota State Dept. of Education, St. Paul. Div. of Vocational and Technical Education.

    THIS MODULE OF A 30-MODULE COURSE IS DESIGNED TO DEVELOP AN UNDERSTANDING OF DIESEL ENGINE TUNE-UP PROCEDURES AND THE DESIGN OF FRONT END SUSPENSION AND AXLES USED ON DIESEL ENGINE EQUIPMENT. TOPICS ARE (1) PRE-TUNE-UP CHECKS, (2) TIMING THE ENGINE, (3) INJECTOR PLUNGER AND VALVE ADJUSTMENTS, (4) FUEL PUMP ADJUSTMENTS ON THE ENGINE (PTR AND PTG),…

  19. Effectiveness and cost of car front end design for pedestrian injury prevention and the problem of conflicting requirements : a literature review.

    NARCIS (Netherlands)

    Kampen, L.T.B. van

    1991-01-01

    SWOV carried out a literature review on the subject of car front end design for pedestrian injury prevention. The review is aimed at effectiveness and cost of such a design and at the problem of conflicting requirements. Such requirements are existing safety standards and common design rules on the

  20. A Front-End ASIC with Receive Sub-array Beamforming Integrated with a 32 × 32 PZT Matrix Transducer for 3-D Transesophageal Echocardiography

    NARCIS (Netherlands)

    Chen, C.; Chen, Z.; Bera, Deep; Raghunathan, S.B.; ShabaniMotlagh, M.; Noothout, E.C.; Chang, Z.Y.; Ponte, Jacco; Prins, Christian; Vos, H.J.; Bosch, Johan G.; Verweij, M.D.; de Jong, N.; Pertijs, M.A.P.

    2017-01-01

    This paper presents a power-and area-efficient front-end application-specific integrated circuit (ASIC) that is directly integrated with an array of 32 × 32 piezoelectric transducer elements to enable next-generation miniature ultrasound probes for real-time 3-D transesophageal echocardiography.

  1. A self-interference cancelling front-end for in-band full-duplex wireless and its phase noise performance

    NARCIS (Netherlands)

    van den Broek, Dirk-Jan; Klumperink, Eric A.M.; Nauta, Bram

    2015-01-01

    This paper describes a frequency-agile RF front-end in 65nm CMOS targeting short-range full-duplex wireless communication. Complementing previous work on a self-interference cancelling receiver, this work describes the co-integrated transmitter and reports the phase noise advantages of using

  2. The VFAT3-Comm-Port: a complete communication port for front-end ASICs intended for use within the high luminosity radiation environments of the LHC

    International Nuclear Information System (INIS)

    Dabrowski, M.; Aspell, P.; Bonacini, S.; Ciaglia, D.; Kloukinas, K.; Lentdecker, G. De; Robertis, G. De; Kupiainen, M.; Talvitie, J.; Tuuva, T.; Leroux, P.; Tavernier, F.

    2015-01-01

    This paper presents the VFAT3 Comm-Port (V3CP), which offers a single port for all communication to and from a front-end ASIC within the HL-LHC environment. This includes synchronization to the LHC clock, slow control communication, the execution of fast control commands and the readout of data

  3. A Novel High Bandwidth Current Control Strategy for SiC mosfet Based Active Front-End Rectifiers Under Unbalanced Input Voltage Conditions

    DEFF Research Database (Denmark)

    Maheshwari, Ramkrishan; Trintis, Ionut; Török, Lajos

    2017-01-01

    SiC mosfet based converters are capable of high switching frequency operation. In this paper, the converter is operated with 50-kHz switching frequency for an active front-end rectifier application. Due to high switching frequency, the grid-side filter size is reduced, and the possibility of a high...

  4. Can new passenger cars reduce pedestrian lower extremity injury? A review of geometrical changes of front-end design before and after regulatory efforts.

    Science.gov (United States)

    Nie, Bingbing; Zhou, Qing

    2016-10-02

    Pedestrian lower extremity represents the most frequently injured body region in car-to-pedestrian accidents. The European Directive concerning pedestrian safety was established in 2003 for evaluating pedestrian protection performance of car models. However, design changes have not been quantified since then. The goal of this study was to investigate front-end profiles of representative passenger car models and the potential influence on pedestrian lower extremity injury risk. The front-end styling of sedans and sport utility vehicles (SUV) released from 2008 to 2011 was characterized by the geometrical parameters related to pedestrian safety and compared to representative car models before 2003. The influence of geometrical design change on the resultant risk of injury to pedestrian lower extremity-that is, knee ligament rupture and long bone fracture-was estimated by a previously developed assessment tool assuming identical structural stiffness. Based on response surface generated from simulation results of a human body model (HBM), the tool provided kinematic and kinetic responses of pedestrian lower extremity resulted from a given car's front-end design. Newer passenger cars exhibited a "flatter" front-end design. The median value of the sedan models provided 87.5 mm less bottom depth, and the SUV models exhibited 94.7 mm less bottom depth. In the lateral impact configuration similar to that in the regulatory test methods, these geometrical changes tend to reduce the injury risk of human knee ligament rupture by 36.6 and 39.6% based on computational approximation. The geometrical changes did not significantly influence the long bone fracture risk. The present study reviewed the geometrical changes in car front-ends along with regulatory concerns regarding pedestrian safety. A preliminary quantitative benefit of the lower extremity injury reduction was estimated based on these geometrical features. Further investigation is recommended on the structural changes

  5. Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.

    2010-10-01

    The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

  6. A CMOS power-efficient low-noise current-mode front-end amplifier for neural signal recording.

    Science.gov (United States)

    Wu, Chung-Yu; Chen, Wei-Ming; Kuo, Liang-Ting

    2013-04-01

    In this paper, a new current-mode front-end amplifier (CMFEA) for neural signal recording systems is proposed. In the proposed CMFEA, a current-mode preamplifier with an active feedback loop operated at very low frequency is designed as the first gain stage to bypass any dc offset current generated by the electrode-tissue interface and to achieve a low high-pass cutoff frequency below 0.5 Hz. No reset signal or ultra-large pseudo resistor is required. The current-mode preamplifier has low dc operation current to enhance low-noise performance and decrease power consumption. A programmable current gain stage is adopted to provide adjustable gain for adaptive signal scaling. A following current-mode filter is designed to adjust the low-pass cutoff frequency for different neural signals. The proposed CMFEA is designed and fabricated in 0.18-μm CMOS technology and the area of the core circuit is 0.076 mm(2). The measured high-pass cutoff frequency is as low as 0.3 Hz and the low-pass cutoff frequency is adjustable from 1 kHz to 10 kHz. The measured maximum current gain is 55.9 dB. The measured input-referred current noise density is 153 fA /√Hz , and the power consumption is 13 μW at 1-V power supply. The fabricated CMFEA has been successfully applied to the animal test for recording the seizure ECoG of Long-Evan rats.

  7. New Reference PMHS Tests to Assess Whole-Body Pedestrian Impact Using a Simplified Generic Vehicle Front-End.

    Science.gov (United States)

    Song, Eric; Petit, Philippe; Trosseille, Xavier; Uriot, Jerome; Potier, Pascal; Dubois, Denis; Douard, Richard

    2017-11-01

    This study aims to provide a set of reference post-mortem human subject tests which can be used, with easily reproducible test conditions, for developing and/or validating pedestrian dummies and computational human body models against a road vehicle. An adjustable generic buck was first developed to represent vehicle front-ends. It was composed of four components: two steel cylindrical tubes screwed on rigid supports in V-form represent the bumper and spoiler respectively, a quarter of a steel cylindrical tube represents the bonnet leading edge, and a steel plate represents the bonnet. These components were positioned differently to represent three types of vehicle profile: a sedan, a SUV and a van. Eleven post-mortem human subjects were then impacted laterally in a mid-gait stance by the bucks at 40 km/h: three tests with the sedan, five with the SUV, and three with the van. Kinematics of the subjects were recorded via high speed videos, impact forces between the subjects and the bucks were measured via load cells behind each tube, femur and tibia deformation and fractures were monitored via gauges on these bones. Based on these tests, biofidelity corridors were established in terms of: 1) displacement time history and trajectory of the head, shoulder, T1, T4, T12, sacrum, knee and ankle, 2) impact forces between the subjects and the buck. Injury outcome was established for each PMHS via autopsy. Simplicity of its geometry and use of standard steel tubes and plates for the buck will make it easy to perform future, new post-mortem human subject tests in the same conditions, or to assess dummies or computational human body models using these reference tests.

  8. A Low-Power Current-Reuse Analog Front-End for High-Density Neural Recording Implants.

    Science.gov (United States)

    Rezaei, Masoud; Maghsoudloo, Esmaeel; Bories, Cyril; De Koninck, Yves; Gosselin, Benoit

    2018-04-01

    Studying brain activity in vivo requires collecting bioelectrical signals from several microelectrodes simultaneously in order to capture neuron interactions. In this work, we present a new current-reuse analog front-end (AFE), which is scalable to very large numbers of recording channels, thanks to its small implementation silicon area and its low-power consumption. This current-reuse AFE, which is including a low-noise amplifier (LNA) and a programmable gain amplifier (PGA), employs a new fully differential current-mirror topology using fewer transistors, and improving several design parameters, such as power consumption and noise, over previous current-reuse amplifier circuit implementations. We show that the proposed current-reuse amplifier can provide a theoretical noise efficiency factor (NEF) as low as 1.01, which is the lowest reported theoretical NEF provided by an LNA topology. A foue-channel current-reuse AFE implemented in a CMOS 0.18-μm technology is presented as a proof-of-concept. T-network capacitive circuits are used to decrease the size of input capacitors and to increase the gain accuracy in the AFE. The measured performance of the whole AFE is presented. The total power consumption per channel, including the LNA and the PGA stage, is 9 μW (4.5 μW for LNA and 4.5 μW for PGA), for an input referred noise of 3.2 μV rms , achieving a measured NEF of 1.94. The entire AFE presents three selectable gains of 35.04, 43.1, and 49.5 dB, and occupies a die area of 0.072 mm 2 per channel. The implemented circuit has a measured inter-channel rejection ratio of 54 dB. In vivo recording results obtained with the proposed AFE are reported. It successfully allows collecting low-amplitude extracellular action potential signals from a tungsten wire microelectrode implanted in the hippocampus of a laboratory mouse.

  9. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    International Nuclear Information System (INIS)

    Sorokin, Iurii

    2013-01-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10 14 n eq /cm 2 (n eq -neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the amplitude response on

  10. Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

    Energy Technology Data Exchange (ETDEWEB)

    Sorokin, Iurii

    2013-07-01

    The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

  11. Performance of a radiation hard 128 channel analogue front-end chip for the readout of a silicon-based hybrid photon detector

    CERN Document Server

    Lacasta, C; Dulinski, W; Chesi, Enrico Guido; Joram, C; Kaplon, J; Lozano-Bahilo, J; Séguinot, Jacques; Szczygiel, R; Weilhammer, Peter; Ypsilantis, Thomas

    2003-01-01

    The performance is described of a front-end chip, the SCT128A-LC chip, originally developed for the readout of a silicon based Hybrid Photon Detector (HPD), which is part of an RICH detector to be run in an LHC experimental environment. The relatively low signal charge from single photoelectrons, impinging on the silicon pad sensor, put very stringent requirements on the noise performance of the front-end chip. An absolute noise calibration using X-ray sources and a **2**4**1Am gamma source was performed. It is demonstrated that sufficiently good signal over noise ratio can be obtained to use this chip for the read-out of an HPD in LHC experiments.

  12. Characterization and performance of monolithic detector blocks with a dedicated ASIC front-end readout for PET imaging of the human brain

    International Nuclear Information System (INIS)

    Rato Mendes, Pedro; Sarasola Martin, Iciar; Canadas, Mario; Garcia de Acilu, Paz; Cuypers, Robin; Perez, Jose Manuel; Willmott, Carlos

    2011-01-01

    We are developing a human brain PET scanner prototype compatible with MRI based on monolithic scintillator crystals, APD matrices and a dedicated ASIC front-end readout. In this work we report on the performance of individual detector modules and on the operation of such modules in PET coincidence. Results will be presented on the individual characterization of detector blocks and its ASIC front-end readout, with measured energy resolutions of 13% full-width half-maximum (FWHM) at 511 keV and spatial resolutions of the order of 2 mm FWHM. First results on PET coincidence performance indicate spatial resolutions as good as 2.1 mm FWHM for SSRB/FBP reconstruction of tomographic data obtained using a simple PET demonstrator based on a pair of monolithic detector blocks with ASIC readout.

  13. Development of the front-end board of a Xenon gas Time Projection Chamber at the AXEL neutrinoless double beta decay search experiment

    Science.gov (United States)

    Tanaka, Shunsuke; AXEL Collaboration

    2017-09-01

    AXEL is a project to search for 0νββ using a High pressure Xenon gas TPC. AXEL uses SiPM’s to measure the energies and the tracks of 0νββ events. About 50,000 SiPM’s are required for final 0νββ searching version, so developing Front-End Boards (FEB) are necessary. We develop FEB that has high energy resolution and wide dynamic range.

  14. The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

    Czech Academy of Sciences Publication Activity Database

    Aguilar, J.A.; Bilnik, W.; Borkowski, J.; Mandát, Dušan; Pech, Miroslav; Schovánek, Petr

    2016-01-01

    Roč. 830, Sep (2016), s. 219-232 ISSN 0168-9002 R&D Projects: GA MŠk LM2015046; GA MŠk LE13012; GA MŠk LG14019 Institutional support: RVO:68378271 Keywords : CTA * SiPM * G-APD * preamplifier * front-end * slow-control * compensation Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.362, year: 2016

  15. Measurement of the front-end dead-time of the LHCb muon detector and evaluation of its contribution to the muon detection inefficiency

    CERN Document Server

    INSPIRE-00357120; Archilli, F.; Auriemma, G.; Baldini, W.; Bencivenni, G.; Bizzeti, A.; Bocci, V.; Bondar, N.; Bonivento, W.; Bochin, B.; Bozzi, C.; Brundu, D.; Cadeddu, S.; Campana, P.; Carboni, G.; Cardini, A.; Carletti, M.; Casu, L.; Chubykin, A.; Ciambrone, P.; Dané, E.; De Simone, P.; Falabella, A.; Felici, G.; Fiore, M.; Fontana, M.; Fresch, P.; Furfaro, E.; Graziani, G.; Kashchuk, A.; Kotriakhova, S.; Lai, A.; Lanfranchi, G.; Loi, A.; Maev, O.; Manca, G.; Martellotti, G.; Neustroev, P.; Oldeman, R.G.C.; Palutan, M.; Passaleva, G.; Penso, G.; Pinci, D.; Polycarpo, E.; Saitta, B.; Santacesaria, R.; Santimaria, M.; Santovetti, E.; Saputi, A.; Sarti, A.; Satriano, C.; Satta, A.; Schmidt, B.; Schneider, T.; Sciascia, B.; Sciubba, A.; Siddi, B.G.; Tellarini, G.; Vacca, C.; Vazquez-Gomez, R.; Vecchi, S.; Veltri, M.; Vorobyev, A.

    2016-04-06

    A method is described which allows to deduce the dead-time of the front-end electronics of the LHCb muon detector from a series of measurements performed at different luminosities at a bunch-crossing rate of 20 MHz. The measured values of the dead-time range from 70 ns to 100 ns. These results allow to estimate the performance of the muon detector at the future bunch-crossing rate of 40 MHz and at higher luminosity.

  16. Feeding the nuclear fuel cycle with a long term view; AREVA's front-end business units, uranium mining, UF6 conversion and isotopic enrichment

    International Nuclear Information System (INIS)

    Capus, G.A.P.; Autegert, R.

    2005-01-01

    As a leading provider of technological solutions for nuclear power generation and electricity transmission, the AREVA group has the unique capability of offering a fully integrated fuel supply, when requested by its customers. At the core of the AREVA group, COGEMA Front End Division is an essential part of the overall fuel supply chain. Composed of three Business Units and gathering several subsidiaries and joint 'ventures, this division enjoys several leading positions as shown by its market shares and historical production records. Current Uranium market evolutions put the natural uranium supply under focus. The uranium conversion segment also recently revealed some concerning evolutions. And no doubt, the market pressure will soon be directed also at the enrichment segment. Looking towards the long term, AREVA strongly believes that a nuclear power renewal is needed, especially to help limiting green house effect gas release. Therefore, to address future supplies needed to fuel the existing fleet of nuclear power plants, but also new ones, the AREVA group is planning very significant investments to build new facilities in all the three front-end market segments. As far as uranium mining is concerned, these new mines will be based upon uranium reserves of outstanding quality. As for uranium conversion and enrichment, two large projects will be based on the most advanced technologies. This paper is aimed at recalling COGEMA Front End Division experience, the current status of its plants and operating entities and will provide a detailed overview of its major projects. (authors)

  17. Pixel electronics for the ATLAS experiment

    International Nuclear Information System (INIS)

    Fischer, P.

    2001-01-01

    The ATLAS experiment at LHC will use 3 barrel layers and 2x5 disks of silicon pixel detectors as the innermost elements of the semiconductor tracker. The basic building blocks are pixel modules with an active area of 16.4 mmx60.8 mm which include an n + on n-type silicon sensor and 16 VLSI front-end (FE) chips. Every FE chip contains a low power, high speed charge sensitive preamplifier, a fast discriminator, and a readout system which operates at the 40 MHz rate of LHC. The addresses of hit pixels (as well as a low resolution pulse height information) are stored on the FE chips until arrival of a level 1 trigger signal. Hits are then transferred to a module controller chip (MCC) which collects the data of all 16 FE chips, builds complete events and sends the data through two optical links to the data acquisition system. The MCC receives clock and data through an additional optical link and provides timing and configuration information for the FE chips. Two additional chips are used to amplify and decode the pin diode signal and to drive the VCSEL laser diodes of the optical links

  18. The final design of the ATLAS Trigger/DAQ Readout-Buffer Input (ROBIN) Device

    CERN Document Server

    Kugel, A; Müller, M; Yu, M; Krause, E; Gorini, B; Joos, M; Petersen, J; Stancu, S; Green, B; Misiejuk, A; Kieft, G; Van Wasen, J; 10th Workshop on Electronics for LHC and Future Experiments

    2004-01-01

    The ATLAS readout subsystem (ROS) is the main interface between 1600 detector front-end readout links (ROL) and the high level (HLT) trigger farms. Its core device, the readout-buffer input (ROBIN), accepts event data on 3 readout links (ROLs) with a maximum rate of 100 kHz and a bandwidth of up to 160\\,MB/s per link. Incoming event data is temporarily buffered and delivered via PCI or Gigabit Ethernet on request. Two devices, a XILINX XC2V2000 FPGA and an IBM PowerPC 440, are present, implementing the ROBIN's functionality. Furthermore one 64 MB SDRAM event data buffer is available per ROL. The device supports the ATLAS baseline implementation, which foresees the PCI bus as the main communication path inside the ROS, as well as an optional data path using Gigabit Ethernet to increase scalability when needed. The paper presents the final design of the ATLAS ROBIN. Measurement results, obtained with a prototype device in PCI bus and Gigabit Ethernet setups, show the usability and approve the design choices.

  19. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    The current front-end electronics of the ATLAS Liquid Argon calorimeters need to be upgraded to sustain the higher radiation levels and data rates expected at the upgraded LHC machine (HL-LHC), which will have 5 times more luminosity than the LHC in its ultimate configuration. This upgrade calls for an optical link system of 100 Gbps per front-end board (FEB). A high speed, low power, radiation tolerant serializer is the critical component in this system. In this paper, we present the design and test results of a single channel 16:1 serializer and the design of a double-channel 16:1 serializer. Both designs are based on a commercial 0.25 μm silicon-on-sapphire CMOS technology. The single channel serializer consists of a serializing unit, a PLL clock generator and a line driver implemented in current mode logic (CML). The serializing unit multiplexes 16 bit parallel LVDS data into 1-bit width serial CMOS data. The serializing unit is composed of a cascade of 2:1 multiplexing circuits based on static D-flip-fl...

  20. Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

    CERN Document Server

    Ma, Hong; The ATLAS collaboration

    2014-01-01

    The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics for every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34/cm^2/s. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger chan...