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Sample records for asic wafer test

  1. ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

    International Nuclear Information System (INIS)

    Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

    2002-01-01

    An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

  2. Test vehicles for CMS HGCAL readout ASIC

    CERN Document Server

    Thienpont, Damien

    2017-01-01

    This paper presents first measurement results of two test vehicles ASIC embedding some building blocks for the future CMS High Granularity CALorimeter (HGCAL) read-out ASIC. They were fabricated in CMOS 130 nm, in order to first design the Analog and Mixed-Signal blocks before going to a complete and complex chip. Such a circuit needs to achieve low noise high dynamic range charge measurement and 20 ps resolution timing capability. The results show good analog performance but with higher noise levels compared to simulations. We present the results of the preamplifiers, shapers and ADCs.

  3. Generic testability and test methods guidelines for ASIC devices

    International Nuclear Information System (INIS)

    Puri, K.; Takeda, H.

    1996-04-01

    Many industries are switching from analog equipment to digital equipment. This change has become desirable because digital devices have become cost-effective, easily available, highly reliable, easy to qualify and easy to test and replace when needed. The nuclear power industry is beginning to upgrade some of its instrumentation and control equipment from an analog design to digital design. A digital application specific integrated circuit (ASIC) device can be designed to perform the same functions as performed by analog modules. However, the ASIC must be designed for cost-effective testability and qualification. This report provides generic guidelines for designing cost-effective methods for testing and characterizing ASIC devices to accomplish qualification

  4. Beam test performance of the SKIROC2 ASIC

    CERN Document Server

    Frisson, T; Anduze, M; Augustin, J.E; Bonis, J; Boudry, V; Bourgeois, C; Brient, J.C; Callier, S; Cerutti, M; Chen, S; Cornat, R; Cornebise, P; Cuisy, D; David, J; De la Taille, C; Dulucq, F; Frotin, M; Gastaldi, F; Ghislain, P; Giraud, J; Gonnin, A; Grondin, D; Guliyev, E; Hostachy, J.Y; Jeans, D; Kamiya, Y; Kawagoe, K; Kozakai, C; Lacour, D; Lavergne, L; Lee, S.H; Magniette, F; Ono, H; Poeschl, R; Rouëné, J; Seguin-Moreau, N; Song, H.S; Sudo, Y; Thiebault, A; Tran, H; Ueno, H; Van der Kolk, N; Yoshioka, T

    2015-01-01

    Beam tests of the first layers of CALICE silicon tungsten ECAL technological prototype were performed in April and July 2012 using 1–6 GeV electron beam at DESY. This paper presents an analysis of the SKIROC2 readout ASIC performance under test beam conditions.

  5. An external control unit implemented for stimulator ASIC testing ...

    African Journals Online (AJOL)

    ) for a stimulator ASIC testing purposes. The ECU consists of a graphical user interface (GUI) from the PC, a data transceiver and a power transmitter. The GUI was developed using MATLAB for stimulation data setup. The data transceiver was ...

  6. Phase-II Associative Memory ASIC Specifications

    CERN Document Server

    Stabile, Alberto; Warren, Matthew; Green, Barry; Konstantinidis, Nikolaos; Motuk, Halil Erdem; Frontini, Luca; Liberali, Valentino; Crescioli, Francesco; Fedi, Giacomo; Sotiropoulou, Calliope-louisa; De Canio, Francesco; Traversi, Gianluca; Shojaii, Seyed Ruhollah; Kubota, Takashi; Calderini, Giovanni; Palla, Fabrizio; Checcucci, Bruno; Spiller, Laurence Anthony; Mcnamara, Peter Charles

    2018-01-01

    This documents defines the specifications for the Associative Memory ASIC for Phase-II. The work-flow toward the final ASIC is organized in the following three steps • AM08 prototype: small area MPW prototype to test all the full custom features, the VHDL logic and the I/O. This chip must be fully functional with smaller memory area than the final ASIC; • AM09pre pre-production: full area ASIC to be fabricated with a full-mask set pilot run. Production corner wafers will be created; • AM09 production: full area ASIC with refinements for the mass production. The AM09 will be developed built on the AM08 extending the memory area, therefore the specification of both versions must be compatible.

  7. First irradiation test results of the ALICE SAMPA ASIC

    CERN Document Server

    Mahmood, Sohail Musa; Winje, Fredrik Lindseth; Velure, Arild

    2018-01-01

    With the continuous scaling of the CMOS technology, the CMOS circuits are considered to be more tolerant to Single event Latchup (SEL) effects due to the reduction in the supply voltages. This paper reports the results from SEL testing performed on the first two prototypes for the new readout ASIC (SAMPA). During RUN 3/RUN 4 at the Large Hadron Collider (LHC), the SAMPA chip will be used for the upgrade of read-out front end electronics of the ALICE (A Large Ion Collider Experiment) Time Projection Chamber (TPC) and Muon Chambers (MCH). The first prototype MPW1 and the second prototype V2 of the SAMPA chip were delivered in 2015 and 2016, respectively. The results are summarized from two different proton beam irradiation campaigns, conducted for SAMPA MPW1 and V2 prototypes at The Svedberg Laboratory (TSL) in Uppsala, and the Center of Advanced Radiation Technology (KVI) in Groningen, respectively.

  8. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  9. Test beam analysis of ultra-thin hybrid pixel detector assemblies with Timepix readout ASICs

    CERN Document Server

    Alipour Tehrani, Niloufar; Dannheim, Dominik; Firu, Elena; Kulis, Szymon; Redford, Sophie; Sicking, Eva

    2016-01-01

    The requirements for the vertex detector at the proposed Compact Linear Collider imply a very small material budget: less than 0.2% of a radiation length per detection layer including services and mechanical supports. We present here a study using Timepix readout ASICs hybridised to pixel sensors of 50 − 500 μm thickness, including assemblies with 100 μm thick sensors bonded to thinned 100μm thick ASICs. Sensors from three producers (Advacam, Micron Semiconductor Ltd, Canberra) with different edge termination technologies (active edge, slim edge) were bonded to Timepix ASICs. These devices were characterised with the EUDET telescope at the DESY II test beam using 5.6 GeV electrons. Their performance for the detection and tracking of minimum ionising particles was evaluated in terms of charge sharing, detection efficiency, single-point resolution and energy deposition.

  10. Addressable Inverter Matrix Tests Integrated-Circuit Wafer

    Science.gov (United States)

    Buehler, Martin G.

    1988-01-01

    Addressing elements indirectly through shift register reduces number of test probes. With aid of new technique, complex test structure on silicon wafer tested with relatively small number of test probes. Conserves silicon area by reduction of area devoted to pads. Allows thorough evaluation of test structure characteristics and of manufacturing process parameters. Test structure consists of shift register and matrix of inverter/transmission-gate cells connected to two-by-ten array of probe pads. Entire pattern contained in square area having only 1.6-millimeter sides. Shift register is conventional static CMOS device using inverters and transmission gates in master/slave D flip-flop configuration.

  11. Wafer-level radiometric performance testing of uncooled microbolometer arrays

    Science.gov (United States)

    Dufour, Denis G.; Topart, Patrice; Tremblay, Bruno; Julien, Christian; Martin, Louis; Vachon, Carl

    2014-03-01

    A turn-key semi-automated test system was constructed to perform on-wafer testing of microbolometer arrays. The system allows for testing of several performance characteristics of ROIC-fabricated microbolometer arrays including NETD, SiTF, ROIC functionality, noise and matrix operability, both before and after microbolometer fabrication. The system accepts wafers up to 8 inches in diameter and performs automated wafer die mapping using a microscope camera. Once wafer mapping is completed, a custom-designed quick insertion 8-12 μm AR-coated Germanium viewport is placed and the chamber is pumped down to below 10-5 Torr, allowing for the evaluation of package-level focal plane array (FPA) performance. The probe card is electrically connected to an INO IRXCAM camera core, a versatile system that can be adapted to many types of ROICs using custom-built interface printed circuit boards (PCBs). We currently have the capability for testing 384x288, 35 μm pixel size and 160x120, 52 μm pixel size FPAs. For accurate NETD measurements, the system is designed to provide an F/1 view of two rail-mounted blackbodies seen through the Germanium window by the die under test. A master control computer automates the alignment of the probe card to the dies, the positioning of the blackbodies, FPA image frame acquisition using IRXCAM, as well as data analysis and storage. Radiometric measurement precision has been validated by packaging dies measured by the automated probing system and re-measuring the SiTF and Noise using INO's pre-existing benchtop system.

  12. Test of a 32-channel Prototype ASIC for Photon Counting Application.

    Science.gov (United States)

    Chen, Y; Cui, Y; O'Connor, P; Seo, Y; Camarda, G S; Hossain, A; Roy, U; Yang, G; James, R B

    2015-01-01

    A new low-power application-specific integrated circuit (ASIC) for Cadmium Zinc Telluride (CZT) detectors for single-photon emission computed tomography (SPECT) application is being developed at BNL. As the first step, a 32-channel prototype ASIC was designed and tested recently. Each channel has a preamplifier followed by CR-RC 3 shaping circuits and three independent energy bins with comparators and 16-bit counters. The ASIC was fabricated with TSMC 0.35-μm complementary metal-oxide-semiconductor (CMOS) process and tested in laboratories. The power consumption is around 1 mW/ch with a 2.5-V supply. With a gain of 400 mV/fC and the peaking time of 500 ns, the equivalent noise charge (ENC) of 360 e- has been measured in room temperature while the crosstalk rate is less than 0.3%. The 10-bit DACs for global thresholds have an integral nonlinearity (INL) less than 0.56% and differential nonlinearity (DNL) less than 0.33%. In the presentation, we will report the detailed test results with this ASIC.

  13. Tests of a silicon wafer based neutron collimator

    International Nuclear Information System (INIS)

    Cussen, L.D.; Vale, C.J.; Anderson, I.S.; Hoeghoj, P.

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 μm thick single crystal silicon wafers coated on one surface with 4 μm of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators

  14. Tests of a silicon wafer based neutron collimator

    CERN Document Server

    Cussen, L D; Anderson, I S; Hoeghoj, P

    2001-01-01

    A Soller slit neutron collimator has been prepared by stacking 160 mu m thick single crystal silicon wafers coated on one surface with 4 mu m of gadolinium metal. The collimator has an angular width of 20 min full width at half maximum and an effective length of 2.75 cm. The collimator has beam dimensions of 1 cm wide by 5.3 cm high. Tests at neutron wavelengths 7.5A and 1.8A showed a peak transmission of 88% within 2% of the optimum theoretical possibility. The background suppression in the wings is comparable with that of conventional neutron collimators.

  15. Driver ASIC Environmental Testing and Performance Optimization for SpaceBased Active Mirrors

    Science.gov (United States)

    Mejia Prada, Camilo

    Direct imaging of Earth-like planets requires techniques for light suppression, such as coronagraphs or nulling interferometers, in which deformable mirrors (DM) are a principal component. On ground-based systems, DMs are used to correct for turbulence in the Earth’s atmosphere in addition to static aberrations in the optics. For space-based observations, DMs are used to correct for static and quasi- static aberrations in the optical train. State-of-the-art, high-actuator count deformable mirrors suffer from external heavy and bulky electronics in which electrical connections are made through thousands of wires. We are instead developing Application Specific Integrated Circuits (ASICs) capable of direct integration with the DM in a single small package. This integrated ASIC-DM is ideal for space missions, where it offers significant reduction in mass, power and complexity, and performance compatible with high-contrast observations of exoplanets. We have successfully prototyped and tested a 32x32 format Switch-Mode (SM) ASIC which consumes only 2mW static power (total, not per-actuator). A number of constraints were imposed on key parameters of this ASIC design, including sub-picoamp levels of leakage across turned-off switches and from switch-to-substrate, control resolution of 0.04 mV, satisfactory rise/fall times, and a near-zero on-chip crosstalk over a useful range of operating temperatures. This driver ASIC technology is currently at TRL 4. This Supporting Technology proposal will further develop the ASIC technology to TRL 5 by carrying on environmental tests and further optimizing performance, with the end goal of making ASICs suitable for space-based deployment. The effort will be led by JPL, which has considerable expertise with DMs used in highcontrast imaging systems for exoplanet missions and in adaptive optic systems, and in design of DM driver electronics. Microscale, which developed the prototype of the ASICDM, will continue its development. We

  16. Design Implementation and Testing of a VLSI High Performance ASIC for Extracting the Phase of a Complex Signal

    National Research Council Canada - National Science Library

    Altmeyer, Ronald

    2002-01-01

    This thesis documents the research, circuit design, and simulation testing of a VLSI ASIC which extracts phase angle information from a complex sampled signal using the arctangent relationship: (phi=tan/-1 (Q/1...

  17. Localization and Behaviors in Null Mice Suggest that ASIC1 and ASIC2 Modulate Responses to Aversive Stimuli

    OpenAIRE

    Price, Margaret P.; Gong, Huiyu; Parsons, Meredith G.; Kundert, Jacob R.; Reznikov, Leah R.; Bernardinelli, Luisa; Chaloner, Kathryn; Buchanan, Gordon F.; Wemmie, John A.; Richerson, George B.; Cassell, Martin D.; Welsh, Michael J.

    2013-01-01

    Acid sensing ion channels (ASICs) generate H+-gated Na+ currents that contribute to neuronal function and animal behavior. Like ASIC1, ASIC2 subunits are expressed in the brain and multimerize with ASIC1 to influence acid-evoked currents and facilitate ASIC1 localization to dendritic spines. To better understand how ASIC2 contributes to brain function, we localized the protein and tested the behavioral consequences of ASIC2 gene disruption. For comparison, we also localized ASIC1 and studied ...

  18. Bond strength tests between silicon wafers and duran tubes (fusion bonded fluidic interconnects)

    NARCIS (Netherlands)

    Fazal, I.; Berenschot, Johan W.; de Boer, J.H.; Jansen, Henricus V.; Elwenspoek, Michael Curt

    2005-01-01

    The fusion bond strength of glass tubes with standard silicon wafers is presented. Experiments with plain silicon wafers and those coated with silicon oxide and silicon nitride are presented. Results obtained are discussed in terms of homogeneity and strength of fusion bond. High pressure testing

  19. Pilot tests of a PET detector using the TOF-PET ASIC based on monolithic crystals and SiPMs

    International Nuclear Information System (INIS)

    Aguilar, A.; González-Montoro, A.; González, A.J.; Hernández, L.; Monzó, J.M.; Benlloch, J.M.; Bugalho, R.; Ferramacho, L.

    2016-01-01

    In this work we show pilot tests of PET detector blocks using the TOF-PET ASIC, coupled to SiPM detector arrays and different crystal configurations. We have characterized the main ASIC features running calibration processes to compensate the time dispersion among the different ASIC/SiPM paths as well as for the time walk on the arrival of optical photons. The aim of this work is to use of LYSO monolithic crystals and explore their photon Depth of Interaction (DOI) capabilities, keeping good energy and spatial resolutions. First tests have been carried out with crystal arrays. Here we made it possible to reach a coincidence resolving times (CRT) of 370 ps FWHM, with energy resolutions better than 20% and resolving well 2 mm sized crystal elements. When using monolithic crystals, a single-pixel LYSO reference crystal helped to explore the CRT performance. We studied different strategies to provide the best timestamp determination in the monolithic scintillator. Times around 1 ns FWHM have been achieved in these pilot studies. In terms of spatial and energy resolution, values of about 3 mm and better than 30% were found, respectively. We have also demonstrated the capability of this system (monolithic and ASIC) to return accurate DOI information.

  20. Automatic Testing of the Trigger Data Serializer ASIC for the Upgrade of the ATLAS Muon Spectrometer

    CERN Document Server

    Pinkham, Reid; Schwarz, Thomas

    The Trigger Data Serializer (TDS) is a custom designed Application Specific Integrated Circuit (ASIC) designed at the University of Michigan to be used on the ATLAS New Small Wheel (NSW) detector. The TDS is a central hub of the NSW trigger system. It prepares the trigger data for both pad and strip detectors, performs pad-strip matching, and serializes the matched strip data to other circuits on the rim of the NSW. In total, 6000 TDS chips will be produced. As part of the TDS’ initial production run, a test platform was developed to verify the functionality of each chip before being sent to users. The test platform consisted of multiple FPGA evaluation boards with custom designed mezzanine boards to hold the TDS chip during testing and control software running on a local computer. Of the initial run of 200 chips, 161 chips were tested with the automatic setup of which 158 passed. Detailed description of the TDS and automatic test fixture can be found in this thesis.

  1. Probing and irradiation tests of ALICE pixel chip wafers and sensors

    CERN Document Server

    Cinausero, M; Antinori, F; Chochula, P; Dinapoli, R; Dima, R; Fabris, D; Galet, G; Lunardon, M; Manea, C; Marchini, S; Martini, S; Moretto, S; Pepato, Adriano; Prete, G; Riedler, P; Scarlassara, F; Segato, G F; Soramel, F; Stefanini, G; Turrisi, R; Vannucci, L; Viesti, G

    2004-01-01

    In the framework of the ALICE Silicon Pixel Detector (SPD) project a system dedicated to the tests of the ALICE1LHCb chip wafers has been assembled and is now in use for the selection of pixel chips to be bump-bonded to sensor ladders. In parallel, radiation hardness tests of the SPD silicon sensors have been carried out using the 27 MeV proton beam delivered by the XTU TANDEM accelerator at the SIRAD facility in LNL. In this paper we describe the wafer probing and irradiation set-ups and we report the obtained results. (6 refs).

  2. Reliable four-point flexion test and model for die-to-wafer direct bonding

    Energy Technology Data Exchange (ETDEWEB)

    Tabata, T., E-mail: toshiyuki.tabata@cea.fr; Sanchez, L.; Fournel, F.; Moriceau, H. [Univ. Grenoble Alpes, F-38000 Grenoble, France and CEA, LETI, MINATEC Campus, F-38054 Grenoble (France)

    2015-07-07

    For many years, wafer-to-wafer (W2W) direct bonding has been very developed particularly in terms of bonding energy measurement and bonding mechanism comprehension. Nowadays, die-to-wafer (D2W) direct bonding has gained significant attention, for instance, in photonics and microelectro-mechanics, which supposes controlled and reliable fabrication processes. So, whatever the stuck materials may be, it is not obvious whether bonded D2W structures have the same bonding strength as bonded W2W ones, because of possible edge effects of dies. For that reason, it has been strongly required to develop a bonding energy measurement technique which is suitable for D2W structures. In this paper, both D2W- and W2W-type standard SiO{sub 2}-to-SiO{sub 2} direct bonding samples are fabricated from the same full-wafer bonding. Modifications of the four-point flexion test (4PT) technique and applications for measuring D2W direct bonding energies are reported. Thus, the comparison between the modified 4PT and the double-cantilever beam techniques is drawn, also considering possible impacts of the conditions of measures such as the water stress corrosion at the debonding interface and the friction error at the loading contact points. Finally, reliability of a modified technique and a new model established for measuring D2W direct bonding energies is demonstrated.

  3. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  4. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    Bugnet, H.

    1995-01-01

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  5. Wafer-level micro-optics: trends in manufacturing, testing, packaging, and applications

    Science.gov (United States)

    Voelkel, Reinhard; Gong, Li; Rieck, Juergen; Zheng, Alan

    2012-11-01

    Micro-optics is an indispensable key enabling technology (KET) for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the last decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks (supercomputer, ROADM), bringing high-speed internet to our homes (FTTH). Even our modern smart phones contain a variety of micro-optical elements. For example, LED flashlight shaping elements, the secondary camera, and ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by semiconductor industry. Thousands of components are fabricated in parallel on a wafer. We report on the state of the art in wafer-based manufacturing, testing, packaging and present examples and applications for micro-optical components and systems.

  6. CMOS-MEMS Test-Key for Extracting Wafer-Level Mechanical Properties

    Directory of Open Access Journals (Sweden)

    Pei-Zen Chang

    2012-12-01

    Full Text Available This paper develops the technologies of mechanical characterization of CMOS-MEMS devices, and presents a robust algorithm for extracting mechanical properties, such as Young’s modulus, and mean stress, through the external electrical circuit behavior of the micro test-key. An approximate analytical solution for the pull-in voltage of bridge-type test-key subjected to electrostatic load and initial stress is derived based on Euler’s beam model and the minimum energy method. Then one can use the aforesaid closed form solution of the pull-in voltage to extract the Young’s modulus and mean stress of the test structures. The test cases include the test-key fabricated by a TSMC 0.18 μm standard CMOS process, and the experimental results refer to Osterberg’s work on the pull-in voltage of single crystal silicone microbridges. The extracted material properties calculated by the present algorithm are valid. Besides, this paper also analyzes the robustness of this algorithm regarding the dimension effects of test-keys. This mechanical properties extracting method is expected to be applicable to the wafer-level testing in micro-device manufacture and compatible with the wafer-level testing in IC industry since the test process is non-destructive.

  7. Digital Platform for Wafer-Level MEMS Testing and Characterization Using Electrical Response

    Directory of Open Access Journals (Sweden)

    Nuno Brito

    2016-09-01

    Full Text Available The uniqueness of microelectromechanical system (MEMS devices, with their multiphysics characteristics, presents some limitations to the borrowed test methods from traditional integrated circuits (IC manufacturing. Although some improvements have been performed, this specific area still lags behind when compared to the design and manufacturing competencies developed over the last decades by the IC industry. A complete digital solution for fast testing and characterization of inertial sensors with built-in actuation mechanisms is presented in this paper, with a fast, full-wafer test as a leading ambition. The full electrical approach and flexibility of modern hardware design technologies allow a fast adaptation for other physical domains with minimum effort. The digital system encloses a processor and the tailored signal acquisition, processing, control, and actuation hardware control modules, capable of the structure position and response analysis when subjected to controlled actuation signals in real time. The hardware performance, together with the simplicity of the sequential programming on a processor, results in a flexible and powerful tool to evaluate the newest and fastest control algorithms. The system enables measurement of resonant frequency (Fr, quality factor (Q, and pull-in voltage (Vpi within 1.5 s with repeatability better than 5 ppt (parts per thousand. A full-wafer with 420 devices under test (DUTs has been evaluated detecting the faulty devices and providing important design specification feedback to the designers.

  8. All-in-One Wafer-Level Solution for MMIC Automatic Testing

    Directory of Open Access Journals (Sweden)

    Xu Ding

    2018-04-01

    Full Text Available In this paper, we present an all-in-one wafer-level solution for MMIC (monolithic microwave integrated circuit automatic testing. The OSL (open short load two tier de-embedding, the calibration verification model, the accurate PAE (power added efficiency testing, and the optimized vector cold source NF (noise figure measurement techniques are integrated in this solution to improve the measurement accuracy. A dual-core topology formed by an IPC (industrial personal computer and a VNA (vector network analyzer, and an automatic test software based on a three-level driver architecture, are applied to enhance the test efficiency. The benefit from this solution is that all the data of a MMIC can be achieved in only one contact, which shows state-of-the-art accuracy and efficiency.

  9. Functional Testing and Characterisation of ISFETs on Wafer Level by Means of a Micro-droplet Cell

    Directory of Open Access Journals (Sweden)

    Michael J. Schöning

    2006-04-01

    Full Text Available A wafer-level functionality testing and characterisation system for ISFETs (ion-sensitive field-effect transistor is realised by means of integration of a specifically designedcapillary electrochemical micro-droplet cell into a commercial wafer prober-station. Thedeveloped system allows the identification and selection of “good” ISFETs at the earlieststage and to avoid expensive bonding, encapsulation and packaging processes for non-functioning ISFETs and thus, to decrease costs, which are wasted for bad dies. Thedeveloped system is also feasible for wafer-level characterisation of ISFETs in terms ofsensitivity, hysteresis and response time. Additionally, the system might be also utilised forwafer-level testing of further electrochemical sensors.

  10. SODR Memory Control Buffer Control ASIC

    Science.gov (United States)

    Hodson, Robert F.

    1994-01-01

    The Spacecraft Optical Disk Recorder (SODR) is a state of the art mass storage system for future NASA missions requiring high transmission rates and a large capacity storage system. This report covers the design and development of an SODR memory buffer control applications specific integrated circuit (ASIC). The memory buffer control ASIC has two primary functions: (1) buffering data to prevent loss of data during disk access times, (2) converting data formats from a high performance parallel interface format to a small computer systems interface format. Ten 144 p in, 50 MHz CMOS ASIC's were designed, fabricated and tested to implement the memory buffer control function.

  11. Examination of optimum test conditions for a 3-point bending and cutting test to evaluate sound emission of wafer during deformation

    Directory of Open Access Journals (Sweden)

    Erdem Carsanba

    2018-04-01

    Full Text Available The purpose of this study was to investigate optimum test conditions of acoustical-mechanical measurement of wafer analysed by Acoustic Envelope Detector attached to the Texture Analyser. Force-displacement and acoustic signals were simultaneously recorded applying two different methods (3-point bending and cutting test. In order to study acoustical-mechanical behaviour of wafers, the parameters “maximum sound pressure”, “total count peaks” and “mean sound value” were used and optimal test conditions of microphone position and test speed were examined. With a microphone position of 45° angle and 1 cm distance and at a low test speed of 0.5 mm/s wafers of different quality could be distinguished best. The angle of microphone did not have significant effect on acoustic results and the number of peaks of the force and acoustic signal decreased with increasing distance and test speed.

  12. Estimating Delays In ASIC's

    Science.gov (United States)

    Burke, Gary; Nesheiwat, Jeffrey; Su, Ling

    1994-01-01

    Verification is important aspect of process of designing application-specific integrated circuit (ASIC). Design must not only be functionally accurate, but must also maintain correct timing. IFA, Intelligent Front Annotation program, assists in verifying timing of ASIC early in design process. This program speeds design-and-verification cycle by estimating delays before layouts completed. Written in C language.

  13. ASIC design at Fermilab

    International Nuclear Information System (INIS)

    Yarema, R.

    1991-06-01

    In the past few years, ASIC (Application Specific Integrated Circuit) design has become important at Fermilab. The purpose of this paper is to present an overview of the in-house ASIC design activity which has taken place. This design effort has added much value to the high energy physics program and physics capability at Fermilab. The two approaches to ASIC development being pursued at Fermilab are examined by looking at some of the types of projects where ASICs are being used or contemplated. To help estimate the cost of future designs, a cost comparison is given to show the relative development and production expenses for these two ASIC approaches. 5 refs., 14 figs., 7 tabs

  14. Performance test of SKIROC II ASIC chip for the radiation detection

    Energy Technology Data Exchange (ETDEWEB)

    Jun, W. J.; Namgoong, H.; Kim, B. K.; Song, H. S.; Kim, H. S.; Lee, S. H.; Choi, H. J.; Ghergherehchi, M.; Chai, J. S. [Sungkyunkwan University, Suwon (Korea, Republic of)

    2017-04-15

    There is a PCB board called FEV8 board which can readout analog signal from any energy source, and amplify it for signal processing. For precise detection, the board had been designed to operate in wide range of energy condition, with high-resolutive detection performance. This function has the possibility of the utilization for the radiation detection. The channels of the prototype board must be evaluated to make sure that the board is perfect or not. This research had made an progress for the radiation detection as well as the electronics of the intricate combination of the measurement instrumentations. The number of the noisy channels had been measured for threshold scan, and every channels in the board had been evaluated. By improving the experimental conditions such as test script in Linux system or well designed ground condition of the test bench, much more clean data will be able to be acquisited.

  15. Hsc70 regulates cell surface ASIC2 expression and vascular smooth muscle cell migration.

    Science.gov (United States)

    Grifoni, Samira C; McKey, Susan E; Drummond, Heather A

    2008-05-01

    Recent studies suggest members of the degenerin (DEG)/epithelial Na(+) channel (ENaC)/acid-sensing ion channel (ASIC) protein family play an important role in vascular smooth muscle cell (VSMC) migration. In a previous investigation, we found suppression of a certain DEG/ENaC/ASIC member, ASIC2, increased VSMC chemotactic migration, raising the possibility that ASIC2 may play an inhibitory role. Because ASIC2 protein was retained in the cytoplasm, we reasoned increasing surface expression of ASIC2 might unmask the inhibitory role of ASIC2 in VSMC migration so we could test the hypothesis that ASIC2 inhibits VSMC migration. Therefore, we used the chemical chaperone glycerol to enhance ASIC2 expression. Glycerol 1) increased cytoplasm ASIC2 expression, 2) permitted detection of ASIC2 at the cell surface, and 3) inhibited platelet-derived growth factor (PDGF)-bb mediated VSMC migration. Furthermore, ASIC2 silencing completely abolished the inhibitory effect of glycerol on migration, suggesting upregulation of ASIC2 is responsible for glycerol-induced inhibition of VSMC migration. Because other investigators have shown that glycerol regulates ENaC/ASIC via interactions with a certain heat shock protein, heat shock protein 70 (Hsc70), we wanted to determine the importance of Hsc70 on ASIC2 expression in VSMCs. We found that Hsc70 silencing increases ASIC2 cell surface expression and inhibits VSMC migration, which is abolished by cosilencing ASIC2. These data demonstrate that Hsc70 inhibits ASIC2 expression, and, when the inhibitory effect of Hsc70 is removed, ASIC2 expression increases, resulting in reduced VSMC migration. Because VSMC migration contributes to vasculogenesis and remodeling following vascular injury, our findings raise the possibility that ASIC2-Hsc70 interactions may play a role in these processes.

  16. Testing of a resistive plate chamber using NINO-ASIC based front end electronics

    International Nuclear Information System (INIS)

    Mondal, M.; Saini, J.; Ahammed, Z.; Chattopadhyay, S.; Ganai, R.; Barai, C.

    2017-01-01

    The Resistive Plate Chamber (RPC) has shown promising results while testing with the NINO FEE board. It has shown ∼ 80% efficiency in detecting cosmic muons with a noise rate of ∼ 40 Hz/cm 2 . The low threshold in the NINO board may be a possible reason for high noise rate. We plan to test the RPC for different gas mixtures to achieve an efficiency above 95%. The calibration of the NINO onboard threshold with input pulse amplitude need to be done. The time resolution of RPC is ∼ 2.66 ns at 12 kV for avalanche mode gas mixture. The minimum time resolution of the RPC has to determined by measuring the time spectra over the full plateau region of voltages. The signal charge has to be measured by time over- threshold for slewing correction. As J7 input of the board was not working properly, efficiency and noise rate data for the particular input has not been measured

  17. A distributed current stimulator ASIC for high density neural stimulation.

    Science.gov (United States)

    Jeong Hoan Park; Chaebin Kim; Seung-Hee Ahn; Tae Mok Gwon; Joonsoo Jeong; Sang Beom Jun; Sung June Kim

    2016-08-01

    This paper presents a novel distributed neural stimulator scheme. Instead of a single stimulator ASIC in the package, multiple ASICs are embedded at each electrode site for stimulation with a high density electrode array. This distributed architecture enables the simplification of wiring between electrodes and stimulator ASIC that otherwise could become too complex as the number of electrode increases. The individual ASIC chip is designed to have a shared data bus that independently controls multiple stimulating channels. Therefore, the number of metal lines is determined by the distributed ASICs, not by the channel number. The function of current steering is also implemented within each ASIC in order to increase the effective number of channels via pseudo channel stimulation. Therefore, the chip area can be used more efficiently. The designed chip was fabricated with area of 0.3 mm2 using 0.18 μm BCDMOS process, and the bench-top test was also conducted to validate chip performance.

  18. The challenges encountered in the integration of an early test wafer surface scanning inspection system into a 450mm manufacturing line

    Science.gov (United States)

    Lee, Jeffrey; McGarvey, Steve

    2013-04-01

    The introduction of early test wafer (ETW) 450mm Surface Scanning Inspection Systems (SSIS) into Si manufacturing has brought with it numerous technical, commercial, and logistical challenges on the path to rapid recipe development and subsequent qualification of other 450mm wafer processing equipment. This paper will explore the feasibility of eliminating the Polystyrene Latex Sphere deposition process step and the subsequent creation of SSIS recipes based upon the theoretical optical properties of both the SSIS and the process film stack(s). The process of Polystyrene Latex Sphere deposition for SSIS recipe generation and development is generally accepted on the previous technology nodes for 150/200/300mm wafers. PSL is deposited with a commercially available deposition system onto a non-patterned bare Si or non-patterned filmed Si wafer. After deposition of multiple PSL spots, located in different positions on a wafer, the wafer is inspected on a SSIS and a response curve is generated. The response curve is based on the the light scattering intensity of the NIST certified PSL that was deposited on the wafer. As the initial 450mm Si wafer manufacturing began, there were no inspection systems with sub-90nm sensitivities available for defect and haze level verification. The introduction of a 450mm sub-30nm inspection system into the manufacturing line generated instant challenges. Whereas the 450mm wafers were relatively defect free at 90nm, at 40nm the wafers contained several hundred thousand defects. When PSL was deposited onto wafers with these kinds of defect levels, PSL with signals less than the sub-90nm defects were difficult to extract. As the defectivity level of the wafers from the Si suppliers rapidly improves the challenges of SSIS recipe creation with high defectivity decreases while at the same time the cost of PSL deposition increases. The current cost per wafer is fifteen thousand dollars for a 450mm PSL deposition service. When viewed from the

  19. AVME readout module for multichannel ASIC characterization

    International Nuclear Information System (INIS)

    Borkar, S.P.; Lalwani, S.K.; Ghodgaonkar, M.D.; Kataria, S.K.; Reynaud, Serge; )

    2004-01-01

    Electronics Division, BARC has been working on the development of multi-channel ASIC, called SPAIR (Silicon-strip Pulse Amplifier Integrated Readout). It contains 8 channels of preamplifier, shaper and track-and-hold circuitry. Electronics Division has also actively participated in development of test setup for the front-end ASIC, called PACE, for the preshower detector of the Compact Muon Solenoid (CMS) Experiment at CERN, Geneva. PACE is a 32 channel ASIC for silicon strip detector, containing preamplifier, shaper, calibration circuitry, switched capacitor array, readout amplifier per channel and an analog multiplexer. A VME Readout Module, (VRM) is developed which can be utilized in data acquisition from ASICs like PACE and SPAIR. The VRM can also be used as the Detector Dependent Unit for digitally processing the data received from the front-end electronics on the 16-bit LVDS port. The processed, data can be read by the VME system. Thus the VRM is very useful in building an ASIC characterization system and/or the automated ASIC production testing system. It can be used also to build the applications using such ASICs. To cater to various requirements arising in future, variety of VME modules are to be developed like ADCs, DACs and D 1/0. VME interface remains a common part to all these modules. The different functional blocks of these modules can be designed and fabricated on small piggyback boards (called Test Boards) and mounted on the VRM, which provides the common VME interface. The design details and uses of VRM are presented here. (author)

  20. High Throughput, High Precision Hot Testing Tool for HBLED Wafer Level Testing

    Energy Technology Data Exchange (ETDEWEB)

    Solarz, Richard [KLA-Tencor Corporation, Milpitas, CA (United States); McCord, Mark [KLA-Tencor Corporation, Milpitas, CA (United States)

    2015-12-31

    The Socrates research effort developed an in depth understanding and demonstrated in a prototype tool new precise methods for teh characterization of color characteristics and flux from individual LEDs for the production of uniform quality lighting. This effort was focused on improving the color quality and consistency of solid state lighting and potentially reducing characterization costs for all LED product types. The patented laser hot testing method was demonstrated to be far more accurate than all current state of the art color and flux characterization methods in use by the solid state lighting industry today. A seperately patented LED grouping method (statistical binning) was demonstrated to be a useful approach to improving utilization of entire lots of large color and flux distributions of manufactured LEDs for high quality color solid-state lighting. At the conclusion of the research in late 2015 the solid-state lighting industry was however generally satisfied with its existing production methods for high quality color products for the small segment of customers that demand it, albeit with added costs.

  1. ASIC proteins regulate smooth muscle cell migration.

    Science.gov (United States)

    Grifoni, Samira C; Jernigan, Nikki L; Hamilton, Gina; Drummond, Heather A

    2008-03-01

    The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated that Epithelial Na(+)Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration; however, the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence individual ASIC expression and determine the importance of ASIC proteins in wound healing and chemotaxis (PDGF-bb)-initiated migration. We found ASIC1, ASIC2, and ASIC3, but not ASIC4, expression in A10 cells. ASIC1, ASIC2, and ASIC3 siRNA molecules significantly suppressed expression of their respective proteins compared to non-targeting siRNA (RISC) transfected controls by 63%, 44%, and 55%, respectively. Wound healing was inhibited by 10, 20, and 26% compared to RISC controls following suppression of ASIC1, ASIC2, and ASIC3, respectively. Chemotactic migration was inhibited by 30% and 45%, respectively, following suppression of ASIC1 and ASIC3. ASIC2 suppression produced a small, but significant, increase in chemotactic migration (4%). Our data indicate that ASIC expression is required for normal migration and may suggest a novel role for ASIC proteins in cellular migration.

  2. EQUIPMENT FOR NONDESTRUCTIVE TESTING OF SILICON WAFERS SUBMICRON TOPOLOGY DURING THE FABRICATION OF INTEGRATED CIRCUITS

    Directory of Open Access Journals (Sweden)

    S. A. Chizhik

    2013-01-01

    Full Text Available The advantages of using an atomic force microscopy in manufacturing of submicron integrated circuits are described. The possibilities of characterizing the surface morphology and the etching profile for silicon substrate and bus lines, estimation of the periodicity and size of bus lines, geometrical stability for elementary bus line are shown. Methods of optical and atomic force microcopies are combined in one diagnostic unit. Scanning  probe  microscope  (SPM  200  is  designed  and  produced.  Complex  SPM  200  realizes  nondestructive control of microelectronics elements made on silicon wafers up to 200 mm in diameter and it is introduced by JSC «Integral» for the purpose of operational control, metrology and acceptance of the final product.

  3. Readout ASIC of pair-monitor for international linear collider

    International Nuclear Information System (INIS)

    Sato, Yutaro; Ikeda, Hirokazu; Ito, Kazutoshi; Miyamoto, Akiya; Nagamine, Tadashi; Sasaki, Rei; Takubo, Yosuke; Tauchi, Toshiaki; Yamamoto, Hitoshi

    2010-01-01

    The pair-monitor is a beam profile monitor at the interaction point of the international linear collider. A prototype of the readout ASIC for the pair-monitor has been designed and tested. Since the pair-monitor uses the hit distribution of electrons and positrons generated by the beam-crossing to measure the beam profile, the readout ASIC is designed to count the number of hits. In a prototype ASIC, 36 readout cells were implemented by TSMC 0.25-μm CMOS process. Each readout cell is equipped with an amplifier, comparator, 8-bit counter and 16 count-registers. By the operation test, all the ASIC component were confirmed to work correctly. As the next step, we develop the prototype ASIC with the silicon on insulator technology. It is produced with OKI 0.2-μm FD-SOI CMOS process.

  4. Memory, microprocessor, and ASIC

    CERN Document Server

    Chen, Wai-Kai

    2003-01-01

    System Timing. ROM/PROM/EPROM. SRAM. Embedded Memory. Flash Memories. Dynamic Random Access Memory. Low-Power Memory Circuits. Timing and Signal Integrity Analysis. Microprocessor Design Verification. Microprocessor Layout Method. Architecture. ASIC Design. Logic Synthesis for Field Programmable Gate Array (EPGA) Technology. Testability Concepts and DFT. ATPG and BIST. CAD Tools for BIST/DFT and Delay Faults.

  5. Radiation hardness tests and characterization of the CLARO-CMOS, a low power and fast single-photon counting ASIC in 0.35 micron CMOS technology

    International Nuclear Information System (INIS)

    Fiorini, M.; Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2014-01-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with 5 ns peaking time, a recovery time to baseline smaller than 25 ns, and a power consumption of less than 1 mW per channel. This chip is capable of single-photon counting with multi-anode photomultipliers and finds applications also in the read-out of silicon photomultipliers and microchannel plates. The prototype is realized in AMS 0.35 micron CMOS technology. In the LHCb RICH environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade in Long Shutdown 2 (LS2), the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionizing dose of 400 krad. A systematic evaluation of the radiation effects on the CLARO-CMOS performance is therefore crucial to ensure long term stability of the electronics front-end. The results of multi-step irradiation tests with neutrons and X-rays up to the fluence of 10 14 cm −2 and a dose of 4 Mrad, respectively, are presented, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step. - Highlights: • CLARO chip capable of single-photon counting with 5 ns peaking time. • Chip irradiated up to very high neutron, proton and X-rays fluences, as expected for upgraded LHCb RICH detectors. • No significant performance degradation is observed after irradiation

  6. ASIC1A in neurons is critical for fear-related behaviors.

    Science.gov (United States)

    Taugher, R J; Lu, Y; Fan, R; Ghobbeh, A; Kreple, C J; Faraci, F M; Wemmie, J A

    2017-11-01

    Acid-sensing ion channels (ASICs) have been implicated in fear-, addiction- and depression-related behaviors in mice. While these effects have been attributed to ASIC1A in neurons, it has been reported that ASICs may also function in nonneuronal cells. To determine if ASIC1A in neurons is indeed required, we generated neuron-specific knockout (KO) mice with floxed Asic1a alleles disrupted by Cre recombinase driven by the neuron-specific synapsin I promoter (SynAsic1a KO mice). We confirmed that Cre expression occurred in neurons, but not all neurons, and not in nonneuronal cells including astrocytes. Consequent loss of ASIC1A in some but not all neurons was verified by western blotting, immunohistochemistry and electrophysiology. We found ASIC1A was disrupted in fear circuit neurons, and SynAsic1a KO mice exhibited prominent deficits in multiple fear-related behaviors including Pavlovian fear conditioning to cue and context, predator odor-evoked freezing and freezing responses to carbon dioxide inhalation. In contrast, in the nucleus accumbens ASIC1A expression was relatively normal in SynAsic1a KO mice, and consistent with this observation, cocaine conditioned place preference (CPP) was normal. Interestingly, depression-related behavior in the forced swim test, which has been previously linked to ASIC1A in the amygdala, was also normal. Together, these data suggest neurons are an important site of ASIC1A action in fear-related behaviors, whereas other behaviors likely depend on ASIC1A in other neurons or cell types not targeted in SynAsic1a KO mice. These findings highlight the need for further work to discern the roles of ASICs in specific cell types and brain sites. © 2017 John Wiley & Sons Ltd and International Behavioural and Neural Genetics Society.

  7. CASAGEM: a readout ASIC for micro pattern gas detectors

    International Nuclear Information System (INIS)

    He Li; Deng Zhi; Liu Yinong

    2012-01-01

    A readout ASIC for micro pattern gas detectors has been designed This ASIC integrates 16 channels for anode readout and 1 channel for cathode readout which can make use of the signal of detector's cathode to generate a trigger Every channel can provide amplification and shaping of detector signals. The ASIC can also provide adjustable gain which can be adjusted from 2 mV/fC to 40 mV/fC, and adjustable shaping time which can be adjusted from 20 ns to 80 ns; so this ASIC can be applied to detectors with wide range output signal and different counting rate. The ASIC is fabricated with Chartered 0.35 μm CMOS process More circuit design Details and test results will be presented. (authors)

  8. Simultaneous Disruption of Mouse ASIC1a, ASIC2 and ASIC3 Genes Enhances Cutaneous Mechanosensitivity

    Science.gov (United States)

    Kang, Sinyoung; Jang, Jun Ho; Price, Margaret P.; Gautam, Mamta; Benson, Christopher J.; Gong, Huiyu; Welsh, Michael J.; Brennan, Timothy J.

    2012-01-01

    Three observations have suggested that acid-sensing ion channels (ASICs) might be mammalian cutaneous mechanoreceptors; they are structurally related to Caenorhabditis elegans mechanoreceptors, they are localized in specialized cutaneous mechanosensory structures, and mechanical displacement generates an ASIC-dependent depolarization in some neurons. However, previous studies of mice bearing a single disrupted ASIC gene showed only subtle or no alterations in cutaneous mechanosensitivity. Because functional redundancy of ASIC subunits might explain limited phenotypic alterations, we hypothesized that disrupting multiple ASIC genes would markedly impair cutaneous mechanosensation. We found the opposite. In behavioral studies, mice with simultaneous disruptions of ASIC1a, -2 and -3 genes (triple-knockouts, TKOs) showed increased paw withdrawal frequencies when mechanically stimulated with von Frey filaments. Moreover, in single-fiber nerve recordings of cutaneous afferents, mechanical stimulation generated enhanced activity in A-mechanonociceptors of ASIC TKOs compared to wild-type mice. Responses of all other fiber types did not differ between the two genotypes. These data indicate that ASIC subunits influence cutaneous mechanosensitivity. However, it is unlikely that ASICs directly transduce mechanical stimuli. We speculate that physical and/or functional association of ASICs with other components of the mechanosensory transduction apparatus contributes to normal cutaneous mechanosensation. PMID:22506072

  9. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    Science.gov (United States)

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitude, pH sensitivity, the kinetics of desensitization and recovery from desensitization, and pharmacological modulation) in isolated, labeled mouse muscle afferents from wild-type (C57BL/6J) and specific ASIC−/− mice. We found that ASIC-like currents in wild-type muscle afferents displayed fast desensitization, indicating that they are carried by heteromeric channels. Currents from ASIC1a−/− muscle afferents were less pH-sensitive and displayed faster recovery, currents from ASIC2−/− mice showed diminished potentiation by zinc, and currents from ASIC3−/− mice displayed slower desensitization than those from wild-type mice. Finally, ASIC-like currents were absent from triple-null mice lacking ASIC1a, ASIC2a, and ASIC3. We conclude that ASIC1a, ASIC2a, and ASIC3 heteromers are the principle channels in skeletal muscle afferents. These results will help us understand the role of ASICs in exercise physiology and provide a molecular target for potential drug therapies to treat muscle pain.—Gautam, M., Benson, C. J. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits. PMID:23109675

  10. The expression profile of acid-sensing ion channel (ASIC) subunits ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3 in the esophageal vagal afferent nerve subtypes.

    Science.gov (United States)

    Dusenkova, Svetlana; Ru, Fei; Surdenikova, Lenka; Nassenstein, Christina; Hatok, Jozef; Dusenka, Robert; Banovcin, Peter; Kliment, Jan; Tatar, Milos; Kollarik, Marian

    2014-11-01

    Acid-sensing ion channels (ASICs) have been implicated in esophageal acid sensing and mechanotransduction. However, insufficient knowledge of ASIC subunit expression profile in esophageal afferent nerves hampers the understanding of their role. This knowledge is essential because ASIC subunits form heteromultimeric channels with distinct functional properties. We hypothesized that the esophageal putative nociceptive C-fiber nerves (transient receptor potential vanilloid 1, TRPV1-positive) express multiple ASIC subunits and that the ASIC expression profile differs between the nodose TRPV1-positive subtype developmentally derived from placodes and the jugular TRPV1-positive subtype derived from neural crest. We performed single cell RT-PCR on the vagal afferent neurons retrogradely labeled from the esophagus. In the guinea pig, nearly all (90%-95%) nodose and jugular esophageal TRPV1-positive neurons expressed ASICs, most often in a combination (65-75%). ASIC1, ASIC2, and ASIC3 were expressed in 65-75%, 55-70%, and 70%, respectively, of both nodose and jugular TRPV1-positive neurons. The ASIC1 splice variants ASIC1a and ASIC1b and the ASIC2 splice variant ASIC2b were similarly expressed in both nodose and jugular TRPV1-positive neurons. However, ASIC2a was found exclusively in the nodose neurons. In contrast to guinea pig, ASIC3 was almost absent from the mouse vagal esophageal TRPV1-positive neurons. However, ASIC3 was similarly expressed in the nonnociceptive TRPV1-negative (tension mechanoreceptors) neurons in both species. We conclude that the majority of esophageal vagal nociceptive neurons express multiple ASIC subunits. The placode-derived nodose neurons selectively express ASIC2a, known to substantially reduce acid sensitivity of ASIC heteromultimers. ASIC3 is expressed in the guinea pig but not in the mouse vagal esophageal TRPV1-positive neurons, indicating species differences in ASIC expression. Copyright © 2014 the American Physiological Society.

  11. Acid-sensing ion channels (ASICs) in mouse skeletal muscle afferents are heteromers composed of ASIC1a, ASIC2, and ASIC3 subunits

    OpenAIRE

    Gautam, Mamta; Benson, Christopher J.

    2013-01-01

    Acid-sensing ion channels (ASICs) are expressed in skeletal muscle afferents, in which they sense extracellular acidosis and other metabolites released during ischemia and exercise. ASICs are formed as homotrimers or heterotrimers of several isoforms (ASIC1a, ASIC1b, ASIC2a, ASIC2b, and ASIC3), with each channel displaying distinct properties. To dissect the ASIC composition in muscle afferents, we used whole-cell patch-clamp recordings to study the properties of acid-evoked currents (amplitu...

  12. The 'KATOD-1' strip readout ASIC for cathode strip chamber

    International Nuclear Information System (INIS)

    Golutvin, I.A.; Gorbunov, N.V.; Karzhavin, V.Yu.; Khabarov, V.S.; Movchan, S.A.; Smolin, D.A.; Dvornikov, O.V.; Shumejko, N.M.; Chekhovskij, V.A.

    2001-01-01

    The 'KATOD-1', a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2 : +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology

  13. The "KATOD-1" Strip Readout ASIC for Cathode Strip Chamber

    CERN Document Server

    Golutvin, I A; Karjavin, V Yu; Khabarov, V S; Movchan, S A; Smolin, D A; Dvornikov, O V; Shumeiko, N M; Tchekhovski, V A

    2001-01-01

    The "KATOD-1", a 16-channels readout ASIC, has been designed to perform tests of P3 and P4 full-scale prototypes of the cathode strip chamber for the ME1/1 forward muon station of the Compact Muon Solenoid (CMS) experiment. The ASIC channel consists of two charge-sensitive preamplifiers, a three-stage shaper with tail cancellation, and an output driver. The ASIC is instrumented with control of gain, in the range of (-4.2\\div +5.0) mV/fC, and control of output pulse-shape. The equivalent input noise is equal to 2400 e with the slope of 12 e/pF for detector capacity up to 200 pF. The peaking time is 100 ns for the chamber signal. The ASIC has been produced by a microwave Bi-jFET technology.

  14. Prototype of a transient waveform recording ASIC

    Science.gov (United States)

    Qin, J.; Zhao, L.; Cheng, B.; Chen, H.; Guo, Y.; Liu, S.; An, Q.

    2018-01-01

    The paper presents the design and measurement results of a transient waveform recording ASIC based on the Switched Capacitor Array (SCA) architecture. This 0.18 μm CMOS prototype device contains two channels and each channel employs a SCA of 128 samples deep, a 12-bit Wilkinson ADC and a serial data readout. A series of tests have been conducted and the results indicate that: a full 1 V signal voltage range is available, the input analog bandwidth is approximately 450 MHz and the sampling speed is adjustable from 0.076 to 3.2 Gsps (Gigabit Samples Per Second). For precision waveform timing extraction, careful calibration of timing intervals between samples is conducted to improve the timing resolution of such chips, and the timing precision of this ASIC is proved to be better than 15 ps RMS.

  15. ASIC1 and ASIC3 Play Different Roles in the Development of Hyperalgesia Following Inflammatory Muscle Injury

    OpenAIRE

    Walder, R.Y.; Rasmussen, L.A.; Rainier, J.D.; Light, A.R.; Wemmie, J.A.; Sluka, K.A.

    2009-01-01

    Acid-sensing ion channels (ASICs) respond to acidosis that normally occurs after inflammation. We examined the expression of ASIC1, ASIC2, and ASIC3 mRNAs in lumbar DRG neurons before and 24h after carrageenan-induced muscle inflammation. Muscle inflammation causes bilateral increases of ASIC2 and ASIC3, but not ASIC1 (neither ASIC1a nor ASIC1b) mRNA, suggesting differential regulation of ASIC1 versus ASIC2 and ASIC3 mRNA. Similar mRNA increases were observed following inflammation in knockou...

  16. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    International Nuclear Information System (INIS)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.

    2010-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using μ-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 (micro)m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  17. Monolithic Active Pixel Matrix with Binary Counters (MAMBO) ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Khalid, Farah F.; Deptuch, Grzegorz; Shenai, Alpana; Yarema, Raymond J.; /Fermilab

    2010-11-01

    Monolithic Active Matrix with Binary Counters (MAMBO) is a counting ASIC designed for detecting and measuring low energy X-rays from 6-12 keV. Each pixel contains analogue functionality implemented with a charge preamplifier, CR-RC{sup 2} shaper and a baseline restorer. It also contains a window comparator which can be trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit ripple counter which is reconfigured as a shift register to serially output the data from the entire ASIC. Each pixel can be tested individually. Two diverse approaches have been used to prevent coupling between the detector and electronics in MAMBO III and MAMBO IV. MAMBO III is a 3D ASIC, the bottom ASIC consists of diodes which are connected to the top ASIC using {mu}-bump bonds. The detector is decoupled from the electronics by physically separating them on two tiers and using several metal layers as a shield. MAMBO IV is a monolithic structure which uses a nested well approach to isolate the detector from the electronics. The ASICs are being fabricated using the SOI 0.2 {micro}m OKI process, MAMBO III is 3D bonded at T-Micro and MAMBO IV nested well structure was developed in collaboration between OKI and Fermilab.

  18. Beamsteerable GNSS Radio Occultation ASIC

    Data.gov (United States)

    National Aeronautics and Space Administration — We will develop an integrated RF ASIC to enable high quality radio occultation (RO) weather observations using the Global Navigations System Satellite (GNSS)...

  19. Mongoose ASIC microcontroller programming guide

    Science.gov (United States)

    Smith, Brian S.

    1993-01-01

    The 'Mongoose' ASIC microcontroller is a radiation-hard implementation of the R3000 microprocessor. This document describes the internals of the microcontroller in a level of detail necessary for someone implementing a software design.

  20. VMM - An ASIC for Micropattern Detectors

    Directory of Open Access Journals (Sweden)

    Iakovidis George

    2018-01-01

    Full Text Available The VMM is a custom Application Specific Integrated Circuit (ASIC that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

  1. Latest generation of ASICs for photodetector readout

    International Nuclear Information System (INIS)

    Seguin-Moreau, N.

    2013-01-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips

  2. VMM - An ASIC for Micropattern Detectors

    Science.gov (United States)

    Iakovidis, George

    2018-02-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21×21 mm2. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are described.

  3. Latest generation of ASICs for photodetector readout

    Science.gov (United States)

    Seguin-Moreau, N.

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the "ROC" family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the "ROC" chips.

  4. Latest generation of ASICs for photodetector readout

    Energy Technology Data Exchange (ETDEWEB)

    Seguin-Moreau, N., E-mail: seguin@lal.in2p3.fr [Laboratoire de l’Accélérateur Linéaire, IN2P3-CNRS, Université Paris-Sud, Bâtiment 200, 91898 Orsay Cedex (France)

    2013-08-01

    The OMEGA microelectronics group has designed a new generation of multichannel integrated circuits, the “ROC” family, in AustrianMicroSystem (AMS) SiGe 0.35 μm technology to read out signals from various families of photodetectors. The chip named MAROC (standing for Multi Anode ReadOut Chip) has been designed to read out MultiAnode Photomultipliers (MAPMT), Photomultiplier ARray In SiGe ReadOut Chip (PARISROC) to read out Photomultipliers (PMTs) and SiPM Integrated ReadOut Chip (SPIROC) to readout Silicon PhotoMultiplier (SiPM) detectors and which was the first ASIC to do so. The three of them fulfill the stringent requirements of the future photodetectors, in particular in terms of low noise, radiation hardness, large dynamic range, high density and high speed while keeping low power thanks to the SiGe technology. These multi-channel ASICs are real System on Chip (SoC) as they provide charge, time and photon-counting information which are digitized internally. Their complexity and versatility enable innovative frontier detectors and also cover spin off of these detectors in adjacent fields such as medical or material imaging as well as smart detectors. In this presentation, the three ASIC architectures and test results will be described to give a general panorama of the “ROC” chips.

  5. VMM - An ASIC for micropattern detectors

    CERN Document Server

    AUTHOR|(INSPIRE)INSPIRE-00215906; The ATLAS collaboration; Polychronakos, Venetios; De Geronimo, Gianluigi

    2015-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) that can be used in a variety of charge interpolating tracking detectors. It is designed to be used with the resistive strip micromegas and sTGC detectors in the New Small Wheel upgrade of the ATLAS Muon spectrometer. The ASIC is designed at Brookhaven National Laboratory and fabricated in the 130 nm Global Foundries 8RF-DM process. It is packaged in a Ball Grid Array with outline dimensions of 21 $\\times$ 21 mm$^2$. It integrates 64 channels, each providing charge amplification, discrimination, neighbour logic, amplitude and timing measurements, analog-to-digital conversions, and either direct output for trigger or multiplexed readout. The front-end amplifier can operate with a wide range of input capacitances, has adjustable polarity, gain and peaking time. The VMM1 and VMM2 are the first two versions of the VMM ASIC family fabricated in 2012 and 2014 respectively. The design, tests and qualification of the VMM1, VMM2 and roadmap to VMM3 are...

  6. ASIC PROTEINS REGULATE SMOOTH MUSCLE CELL MIGRATION

    OpenAIRE

    Grifoni, Samira C.; Jernigan, Nikki L.; Hamilton, Gina; Drummond, Heather A.

    2007-01-01

    The purpose of the present study was to investigate Acid Sensing Ion Channel (ASIC) protein expression and importance in cellular migration. We recently demonstrated Epithelial Na+ Channel (ENaC) proteins are required for vascular smooth muscle cell (VSMC) migration, however the role of the closely related ASIC proteins has not been addressed. We used RT-PCR and immunolabeling to determine expression of ASIC1, ASIC2, ASIC3 and ASIC4 in A10 cells. We used small interference RNA to silence indi...

  7. Design and prototyping of a readout aggregation ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Lemke, Frank; Schatral, Sven; Bruening, Ulrich [ZITI, Universitaet Heidelberg (Germany); Som, Indranil; Bhattacharyya, Tarun [Indian Institute of Technology, Kharagpur (India); Collaboration: CBM-Collaboration

    2015-07-01

    In close collaboration between the Indian Institute of Technology Kharagpur (IITKGP) and the Institute for Computer Engineering (ZITI) at the University of Heidelberg a readout aggregation ASIC was designed. This happened in the context of the Compressed Baryonic Matter (CBM) experiment at the Facility for Antiproton and Ion Research (FAIR). The ASIC is designed in 65nm TSMC technology. Its miniASIC tapeout to verify the analog and high-speed components is scheduled to the first quarter of 2015. This mixed-signal ASIC consists of a full-custom 5Gb/s serializer/deserializer, designed by the IITKGP including design elements such as phase-locked loop, bandgap reference, and clock data recovery, and a digital designed network communication and aggregation part designed by the ZITI. In addition, there are test structures and an I2C readout integrated to ease bring up and monitoring. A specialty of this test ASIC is the aggregation of links featuring different data rates, running with bundles of 500 MB/s LVDS. This enables flexible readout setups of mixed detectors respectively readout of various chips. As communication protocol, a unified link protocol is used including control messages, data messages, and synchronization messages on an identical lane. The design has been simulated, verified, and hardware emulated using Spartan 6 FPGAs.

  8. The STAR cluster-finder ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Botlo, M.; LeVine, M.J.; Scheetz, R.A.; Schulz, M.W. [Brookhaven National Lab., Upton, NY (United States); Short, P.; Woods, J. [InnovASIC, Inc., Albuquerque, NM (United States); Crosetto, D. [Rice Univ., Houston, TX (United States). Bonner Nuclear Lab.

    1997-12-01

    STAR is a large TPC-based experiment at RHIC, the relativistic heavy ion collider at Brookhaven National Laboratory. The STAR experiment reads out a TPC and an SVT (silicon vertex tracker), both of which require in-line pedestal subtraction, compression of ADC values from 10-bit to 8-bit, and location of time sequences representing responses to charged-particle tracks. The STAR cluster finder ASIC responds to all of these needs. Pedestal subtraction and compression are performed using lookup tables in attached RAM. The authors describe its design and implementation, as well as testing methodology and results of tests performed on foundry prototypes.

  9. Status Report on the LOC ASIC

    CERN Document Server

    Ye, J

    2008-01-01

    Based on a commercially available 0.25 μm Silicon on Sapphire CMOS technology, we are developing the LOC ASIC for high speed serial data transmission in the front-end electronics systems of the ATLAS upgrade for the SLHC1. Evaluation of this technology for applications in the SLHC, based on a dedicated test chip, has been performed with irradiation tests in gamma (Co-60) and in 230 MeV proton beams. Test results indicate that this may be a candidate technology of ASIC developments for the SLHC. More thorough evaluation tests will be carried out under another R&D program supported through the Advanced Detector Research (ADR) from the Department of Energy. Characterization tests on the first prototype serializer, LOC1, have been carried out in lab. Based on the lessons learned from this chip, we propose a new architecture design of the second prototype, LOC2, aiming for a serial data rate in the range of 5 Gbps. Simulation on key components of LOC2 are being carried out and the results we have so far are p...

  10. The Mixed-Signal ASIC design course at Twente

    NARCIS (Netherlands)

    Stehelin, G.; Tangelder, R.J.W.T.; Gerez, Sabih H.; Kerkhoff, Hans G.; Klumperink, Eric A.M.; Smit, J.; Snijders, H.; Speek, H.; de Vries, H.

    2000-01-01

    In this paper we give a detailed overview of the ASIC design course as it is being given at the Department of Electrical Engineering of the University of Twente. This course covers the complete trajectory from system design via circuit design and actual implementation to testing. Design and testing

  11. ASIC3 channels in multimodal sensory perception.

    Science.gov (United States)

    Li, Wei-Guang; Xu, Tian-Le

    2011-01-19

    Acid-sensing ion channels (ASICs), which are members of the sodium-selective cation channels belonging to the epithelial sodium channel/degenerin (ENaC/DEG) family, act as membrane-bound receptors for extracellular protons as well as nonproton ligands. At least five ASIC subunits have been identified in mammalian neurons, which form both homotrimeric and heterotrimeric channels. The highly proton sensitive ASIC3 channels are predominantly distributed in peripheral sensory neurons, correlating with their roles in multimodal sensory perception, including nociception, mechanosensation, and chemosensation. Different from other ASIC subunit composing ion channels, ASIC3 channels can mediate a sustained window current in response to mild extracellular acidosis (pH 7.3-6.7), which often occurs accompanied by many sensory stimuli. Furthermore, recent evidence indicates that the sustained component of ASIC3 currents can be enhanced by nonproton ligands including the endogenous metabolite agmatine. In this review, we first summarize the growing body of evidence for the involvement of ASIC3 channels in multimodal sensory perception and then discuss the potential mechanisms underlying ASIC3 activation and mediation of sensory perception, with a special emphasis on its role in nociception. We conclude that ASIC3 activation and modulation by diverse sensory stimuli represent a new avenue for understanding the role of ASIC3 channels in sensory perception. Furthermore, the emerging implications of ASIC3 channels in multiple sensory dysfunctions including nociception allow the development of new pharmacotherapy.

  12. Indigenous design and development of digital ASICs

    International Nuclear Information System (INIS)

    Misra, M.K.; Kishore, G.V.; Sridhar, N.; Palanisami, K.; Thirugnana Murthy, D.

    2013-01-01

    FPGAs and CPLDs were extensively used for the design and development of Instrumentation and Control systems including safety systems of Prototype Fast Breeder Reactor (PFBR). The developed I and C systems have been tested extensively for their functionality and also undergone various qualification tests. Some of these I and C systems have also been deployed in Fast Breeder Test Reactor. The performance of these designs is found to be satisfactory. However FPGAs/CPLDs are rapidly evolving and the devices become obsolete in a short span of time (typically about 5 to 8 years), whereas reactor's life time is typically about 40 years. This obsolescence problem can be handled in different ways. This paper discusses design and fabrication of digital ASICs as one of the alternate for handling obsolescence problems. Aim of this development work is to establish complete digital ASIC design, fabrication and testing flow, so that the same can be used in some of the critical/strategic requirements. (author)

  13. Command Interface ASIC - Analog Interface ASIC Chip Set

    Science.gov (United States)

    Ruiz, Baldes; Jaffe, Burton; Burke, Gary; Lung, Gerald; Pixler, Gregory; Plummer, Joe; Katanyoutanant,, Sunant; Whitaker, William

    2003-01-01

    A command interface application-specific integrated circuit (ASIC) and an analog interface ASIC have been developed as a chip set for remote actuation and monitoring of a collection of switches, which can be used to control generic loads, pyrotechnic devices, and valves in a high-radiation environment. The command interface ASIC (CIA) can be used alone or in combination with the analog interface ASIC (AIA). Designed primarily for incorporation into spacecraft control systems, they are also suitable for use in high-radiation terrestrial environments (e.g., in nuclear power plants and facilities that process radioactive materials). The primary role of the CIA within a spacecraft or other power system is to provide a reconfigurable means of regulating the power bus, actuating all valves, firing all pyrotechnic devices, and controlling the switching of power to all switchable loads. The CIA is a mixed-signal (analog and digital) ASIC that includes an embedded microcontroller with supporting fault-tolerant switch control and monitoring circuitry that is capable of connecting to a redundant set of interintegrated circuit (I(sup 2)C) buses. Commands and telemetry requests are communicated to the CIA. Adherence to the I(sup 2)C bus standard helps to reduce development costs by facilitating the use of previously developed, commercially available components. The AIA is a mixed-signal ASIC that includes the analog circuitry needed to connect the CIA to a custom higher powered version of the I(sup 2)C bus. The higher-powered version is designed to enable operation with bus cables longer than those contemplated in the I(sup 2)C standard. If there are multiple higher-power I(sup 2)C-like buses, then there must an AIA between the CIA and each such bus. The AIA includes two identical interface blocks: one for the side-A I(sup 2)C clock and data buses and the other for the side B buses. All the AIAs on each side are powered from a common power converter module (PCM). Sides A and B

  14. Rad-Hard Structured ASIC Body of Knowledge

    Science.gov (United States)

    Heidecker, Jason

    2013-01-01

    Structured Application-Specific Integrated Circuit (ASIC) technology is a platform between traditional ASICs and Field-Programmable Gate Arrays (FPGA). The motivation behind structured ASICs is to combine the low nonrecurring engineering costs (NRE) costs of FPGAs with the high performance of ASICs. This report provides an overview of the structured ASIC platforms that are radiation-hardened and intended for space application

  15. ANUSANSKAR: a 16 channel frontend electronics (FEE) ASIC targeted for silicon pixel array detector based prototype Alice FOCAL

    International Nuclear Information System (INIS)

    Mukhopadhyay, Sourav; Chandratre, V.B.; Sukhwani, Menka; Pithawa, C.K.; Singaraju, Ramnarayan; Muhuri, Sanjib; Nayak, T.; Khan, S.A.; Saini, Jogendra

    2013-01-01

    ANUSANSKAR is a 16 channel pulse processing ASIC with analog multiplexed output designed in 0.7 um standard CMOS technology with each channel consisting of CSA, Semi Gaussian pulse shaper, DC cancellation and pedestal control, track and hold, output buffer blocks. The ASIC's analog multiplexed output can be read serially in daisy-chain topology. Testing, characterization and validation of ANUSANSKAR ASIC as readout for prototype ALICE forward calorimeter (FOCAL) has been carried out in PS beam line at CERN with up to 6 GeV of pion and electron beam. This paper describes the ANUSANSKAR ASIC along with the experimental results. (author)

  16. ASIC design in the KM3NeT detector

    International Nuclear Information System (INIS)

    Gajanana, D; Gromov, V; Timmer, P

    2013-01-01

    In the KM3NeT project [1], Cherenkov light from the muon interactions with transparent matter around the detector, is used to detect neutrinos. Photo multiplier tubes (PMT) used as photon sensor, are housed in a glass sphere (aka Optical Module) to detect single photons from the Cherenkov light. The PMT needs high operational voltage ( ∼ 1.5 kV) and is generated by a Cockroft-Walton (CW) multiplier circuit. The electronics required to control the PMT's and collect the signals is integrated in two ASIC's namely: 1) a front-end mixed signal ASIC (PROMiS) for the readout of the PMT and 2) an analog ASIC (CoCo) to generate pulses for charging the CW circuit and to control the feedback of the CW circuit. In this article, we discuss the two integrated circuits and test results of the complete setup. PROMiS amplifies the input charge, converts it to a pulse width and delivers the information via LVDS signals. These LVDS signals carry accurate information on the Time of arrival ( 2 C bus. This unique combination of the ASIC's results in a very cost and power efficient PMT base design.

  17. ASIC Development for Three-Dimensional Silicon Imaging Array for Cold Neutrons

    International Nuclear Information System (INIS)

    Britton, C.L.; Jagadish, U.; Bryan, W.L.

    2004-01-01

    An Integrated Circuit (IC) readout chip with four channels arranged so as to receive input charge from the corners of the chip was designed for use with 5- to 7-mm pixel detectors. This Application Specific IC (ASIC) can be used for cold neutron imaging, for study of structural order in materials using cold neutron scattering or for particle physics experiments. The ASIC is fabricated in a 0.5-(micro)m n-well AMI process. The design of the ASIC and the test measurements made is reported. Noise measurements are also reported

  18. Characterization of low-mass deformable mirrors and ASIC drivers for high-contrast imaging

    Science.gov (United States)

    Mejia Prada, Camilo; Yao, Li; Wu, Yuqian; Roberts, Lewis C.; Shelton, Chris; Wu, Xingtao

    2017-09-01

    The development of compact, high performance Deformable Mirrors (DMs) is one of the most important technological challenges for high-contrast imaging on space missions. Microscale Inc. has fabricated and characterized piezoelectric stack actuator deformable mirrors (PZT-DMs) and Application-Specific Integrated Circuit (ASIC) drivers for direct integration. The DM-ASIC system is designed to eliminate almost all cables, enabling a very compact optical system with low mass and low power consumption. We report on the optical tests used to evaluate the performance of the DM and ASIC units. We also compare the results to the requirements for space-based high-contrast imaging of exoplanets.

  19. SPIDR, a general-purpose readout system for pixel ASICs

    International Nuclear Information System (INIS)

    Heijden, B. van der; Visser, J.; Beuzekom, M. van; Boterenbrood, H.; Munneke, B.; Schreuder, F.; Kulis, S.

    2017-01-01

    The SPIDR (Speedy PIxel Detector Readout) system is a flexible general-purpose readout platform that can be easily adapted to test and characterize new and existing detector readout ASICs. It is originally designed for the readout of pixel ASICs from the Medipix/Timepix family, but other types of ASICs or front-end circuits can be read out as well. The SPIDR system consists of an FPGA board with memory and various communication interfaces, FPGA firmware, CPU subsystem and an API library on the PC . The FPGA firmware can be adapted to read out other ASICs by re-using IP blocks. The available IP blocks include a UDP packet builder, 1 and 10 Gigabit Ethernet MAC's and a 'soft core' CPU . Currently the firmware is targeted at the Xilinx VC707 development board and at a custom board called Compact-SPIDR . The firmware can easily be ported to other Xilinx 7 series and ultra scale FPGAs. The gap between an ASIC and the data acquisition back-end is bridged by the SPIDR system. Using the high pin count VITA 57 FPGA Mezzanine Card (FMC) connector only a simple chip carrier PCB is required. A 1 and a 10 Gigabit Ethernet interface handle the connection to the back-end. These can be used simultaneously for high-speed data and configuration over separate channels. In addition to the FMC connector, configurable inputs and outputs are available for synchronization with other detectors. A high resolution (≈ 27 ps bin size) Time to Digital converter is provided for time stamping events in the detector. The SPIDR system is frequently used as readout for the Medipix3 and Timepix3 ASICs. Using the 10 Gigabit Ethernet interface it is possible to read out a single chip at full bandwidth or up to 12 chips at a reduced rate. Another recent application is the test-bed for the VeloPix ASIC, which is developed for the Vertex Detector of the LHCb experiment. In this case the SPIDR system processes the 20 Gbps scrambled data stream from the VeloPix and distributes it over four

  20. Modelling deformation and fracture in confectionery wafers

    Energy Technology Data Exchange (ETDEWEB)

    Mohammed, Idris K.; Charalambides, Maria N.; Williams, J. Gordon; Rasburn, John [Mechanical Engineering Department, Imperial College London, South Kensington, London, SW7 2AZ, United Kingdom and Nestec York Ltd., Nestlé Product Technology Centre, Haxby Road, PO Box 204, York YO91 1XY (United Kingdom)

    2015-01-22

    The aim of this research is to model the deformation and fracture behaviour of brittle wafers often used in chocolate confectionary products. Three point bending and compression experiments were performed on beam and circular disc samples respectively to determine the 'apparent' stress-strain curves in bending and compression. The deformation of the wafer for both these testing types was observed in-situ within an SEM. The wafer is modeled analytically and numerically as a composite material with a core which is more porous than the skins. X-ray tomography was used to generate a three dimensional volume of the wafer microstructure which was then meshed and used for quantitative analysis. A linear elastic material model, with a damage function and element deletion, was used and the XMT generated architecture was loaded in compression. The output from the FE simulations correlates closely to the load-deflection deformation observed experimentally.

  1. READ - Remote Analog ASIC Design System

    Directory of Open Access Journals (Sweden)

    Michael E. Auer

    2006-11-01

    Full Text Available The scope of this work is to present a solution to implement a remote electronic laboratory for testing and designing analog ASICs (ispPAC10. The application allows users to create circuit schematics, upload the design to the device and perform measurements. The software used for designing circuits is the PAC-Designer and it runs on a Citrix server. The signals are generated and the responses are acquired by a data acquisition board controlled by LabView. The virtual instruments interact with some ActiveX controls specially designed to look like real oscilloscope and function generator devices and represent the user interface of the lab. These ActiveX give users the control over the LabView VIs and the access to its facilities in order to perform electronic exercises.

  2. A Serializer ASIC for High Speed Data Transmission in Cryogenic and HiRel Environment

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2010-01-01

    A high speed 16:1 serializer ASIC has been developed using a commercial 0.25 μm silicon-on-sapphire CMOS technology. At room temperature the ASIC operates from 4.0 to 5.7 Gbps with power consumption of 463 mW. The total jitter is 62 ps at the bit error rate of 10-12 at 5 Gbps. A 200-MeV proton beam test indicates that the ASIC is suitable for high energy physics applications. A liquid nitrogen temperature test indicates that the ASIC may be used at cryogenic temperature applications. The reliability of the serializer at liquid nitrogen temperature is to be studied. A 6-lane serializer array with 10 Gbps/lane with redundancy capability is under development.

  3. Implementation of the Timepix ASIC in the Scalable Readout System

    Energy Technology Data Exchange (ETDEWEB)

    Lupberger, M., E-mail: lupberger@physik.uni-bonn.de; Desch, K.; Kaminski, J.

    2016-09-11

    We report on the development of electronics hardware, FPGA firmware and software to provide a flexible multi-chip readout of the Timepix ASIC within the framework of the Scalable Readout System (SRS). The system features FPGA-based zero-suppression and the possibility to read out up to 4×8 chips with a single Front End Concentrator (FEC). By operating several FECs in parallel, in principle an arbitrary number of chips can be read out, exploiting the scaling features of SRS. Specifically, we tested the system with a setup consisting of 160 Timepix ASICs, operated as GridPix devices in a large TPC field cage in a 1 T magnetic field at a DESY test beam facility providing an electron beam of up to 6 GeV. We discuss the design choices, the dedicated hardware components, the FPGA firmware as well as the performance of the system in the test beam.

  4. A High-Performance Deformable Mirror with Integrated Driver ASIC for Space Based Active Optics

    Science.gov (United States)

    Shelton, Chris

    Direct imaging of exoplanets is key to fully understanding these systems through spectroscopy and astrometry. The primary impediment to direct imaging of exoplanets is the extremely high brightness ratio between the planet and its parent star. Direct imaging requires a technique for contrast suppression, which include coronagraphs, and nulling interferometers. Deformable mirrors (DMs) are essential to both of these techniques. With space missions in mind, Microscale is developing a novel DM with direct integration of DM and its electronic control functions in a single small envelope. The Application Specific Integrated Circuit (ASIC) is key to the shrinking of the electronic control functions to a size compatible with direct integration with the DM. Through a NASA SBIR project, Microscale, with JPL oversight, has successfully demonstrated a unique deformable mirror (DM) driver ASIC prototype based on an ultra-low power switch architecture. Microscale calls this the Switch-Mode ASIC, or SM-ASIC, and has characterized it for a key set of performance parameters, and has tested its operation with a variety of actuator loads, such as piezo stack and unimorph, and over a wide temperature range. These tests show the SM-ASIC's capability of supporting active optics in correcting aberrations of a telescope in space. Microscale has also developed DMs to go with the SM-ASIC driver. The latest DM version produced uses small piezo stack elements in an 8x8 array, bonded to a novel silicon facesheet structure fabricated monolithically into a polished mirror on one side and mechanical linkage posts that connect to the piezoelectric stack actuators on the other. In this Supporting Technology proposal we propose to further develop the ASIC-DM and have assembled a very capable team to do so. It will be led by JPL, which has considerable expertise with DMs used in Adaptive Optics systems, with high-contrast imaging systems for exoplanet missions, and with designing DM driver

  5. Development of n+-in-p planar pixel quadsensor flip-chipped with FE-I4 readout ASICs

    International Nuclear Information System (INIS)

    Unno, Y.; Hanagaki, K.; Hori, R.; Ikegami, Y.; Nakamura, K.; Takubo, Y.; Kamada, S.; Yamamura, K.; Yamamoto, H.; Takashima, R.; Tojo, J.; Kono, T.; Nagai, R.; Saito, S.; Sugibayashi, K.; Hirose, M.; Jinnouchi, O.; Sato, S.; Sawai, H.; Hara, K.

    2017-01-01

    We have developed flip-chip modules applicable to the pixel detector for the HL-LHC. New radiation-tolerant n + -in-p planar pixel sensors of a size of four FE-I4 application-specific integrated circuits (ASICs) are laid out in a 6-in wafer. Variation in readout connection for the pixels at the boundary of ASICs is implemented in the design of quadsensors. Bump bonding technology is developed for four ASICs onto one quadsensor. Both sensors and ASICs are thinned to 150 μm before bump bonding, and are held flat with vacuum chucks. Using lead-free SnAg solder bumps, we encounter deficiency with large areas of disconnected bumps after thermal stress treatment, including irradiation. Surface oxidation of the solder bumps is identified as a critical source of this deficiency after bump bonding trials, using SnAg bumps with solder flux, indium bumps, and SnAg bumps with a newly-introduced hydrogen-reflow process. With hydrogen-reflow, we establish flux-less bump bonding technology with SnAg bumps, appropriate for mass production of the flip-chip modules with thin sensors and thin ASICs.

  6. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    International Nuclear Information System (INIS)

    Cha, Bo Kyung; Jeon, Seongchae; Seo, Chang-Woo

    2016-01-01

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd_2O_2S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  7. X-ray performance of a wafer-scale CMOS flat panel imager for applications in medical imaging and nondestructive testing

    Energy Technology Data Exchange (ETDEWEB)

    Cha, Bo Kyung, E-mail: goldrain99@kaist.ac.kr [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Jeon, Seongchae [Advanced Medical Device Research Center, Korea Electrotechnology Research Institute, Ansan (Korea, Republic of); Seo, Chang-Woo [Department of Radiological Science, Yonsei University, Gangwon-do 220-710 (Korea, Republic of)

    2016-09-21

    This paper presents a wafer-scale complementary metal-oxide semiconductor (CMOS)-based X-ray flat panel detector for medical imaging and nondestructive testing applications. In this study, our proposed X-ray CMOS flat panel imager has been fabricated by using a 0.35 µm 1-poly/4-metal CMOS process. The pixel size is 100 µm×100 µm and the pixel array format is 1200×1200 pixels, which provide a field-of-view (FOV) of 120mm×120 mm. The 14.3-bit extended counting analog-to digital converter (ADC) with built-in binning mode was used to reduce the area and simultaneously improve the image resolution. The different screens such as thallium-doped CsI (CsI:Tl) and terbium gadolinium oxysulfide (Gd{sub 2}O{sub 2}S:Tb) scintillators were used as conversion materials for X-rays to visible light photons. The X-ray imaging performance such as X-ray sensitivity as a function of X-ray exposure dose, spatial resolution, image lag and X-ray images of various objects were measured under practical medical and industrial application conditions. This paper results demonstrate that our prototype CMOS-based X-ray flat panel imager has the significant potential for medical imaging and non-destructive testing (NDT) applications with high-resolution and high speed rate.

  8. FROST: an ASIC for digital mammography with synchrotron radiation

    International Nuclear Information System (INIS)

    Bergamaschi, A.; Prest, M.; Vallazza, E.; Arfelli, F.; Dreossi, D.; Longo, R.; Olivo, A.; Pani, S.; Castelli, E.

    2003-01-01

    The FRONTier RADiography (FRONTRAD) collaboration is developing a digital system for mammography at the Elettra Synchrotron Light Source in Trieste. The system is based on a silicon microstrip detector array. The ASIC FROST (FRONTRAD Read Out sySTem) was developed as a collaboration between INFN Trieste and Aurelia Microelettronica and is designed to operate in single photon counting mode. FROST provides low-noise and high-gain performances and is able to work at incident photon rates higher than 100 kHz with almost 100% efficiency. The ASIC has been tested and the first images of mammographic test objects will be shown. The acquisition time per breast image should be of about 10 s

  9. Extracellular acidosis activates ASIC-like channels in freshly isolated cerebral artery smooth muscle cells.

    Science.gov (United States)

    Chung, Wen-Shuo; Farley, Jerry M; Swenson, Alyssa; Barnard, John M; Hamilton, Gina; Chiposi, Rumbidzayi; Drummond, Heather A

    2010-05-01

    Recent studies suggest that certain acid-sensing ion channels (ASIC) are expressed in vascular smooth muscle cells (VSMCs) and are required for VSMC functions. However, electrophysiological evidence of ASIC channels in VSMCs is lacking. The purpose of this study was to test the hypothesis that isolated cerebral artery VSMCs express ASIC-like channels. To address this hypothesis, we used RT-PCR, Western blotting, immunolabeling, and conventional whole cell patch-clamp technique. We found extracellular H(+)-induced inward currents in 46% of cells tested (n = 58 of 126 VSMCs, pH 6.5-5.0). The percentage of responsive cells and the current amplitude increased as the external H(+) concentration increased (pH(6.0), n = 28/65 VSMCs responsive, mean current density = 8.1 +/- 1.2 pA/pF). Extracellular acidosis (pH(6.0)) shifted the whole cell reversal potential toward the Nernst potential of Na(+) (n = 6) and substitution of extracellular Na(+) by N-methyl-d-glucamine abolished the inward current (n = 6), indicating that Na(+) is a major charge carrier. The broad-spectrum ASIC blocker amiloride (20 microM) inhibited proton-induced currents to 16.5 +/- 8.7% of control (n = 6, pH(6.0)). Psalmotoxin 1 (PcTx1), an ASIC1a inhibitor and ASIC1b activator, had mixed effects: PcTx1 either 1) abolished H(+)-induced currents (11% of VSMCs, 5/45), 2) enhanced or promoted activation of H(+)-induced currents (76%, 34/45), or 3) failed to promote H(+) activation in nonresponsive VSMCs (13%, 6/45). These findings suggest that freshly dissociated cerebral artery VSMCs express ASIC-like channels, which are predominantly formed by ASIC1b.

  10. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    International Nuclear Information System (INIS)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P.; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J. Michael

    2015-01-01

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers

  11. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels

    Energy Technology Data Exchange (ETDEWEB)

    Jeggle, Pia; Smith, Ewan St. J.; Stewart, Andrew P. [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom); Haerteis, Silke; Korbmacher, Christoph [Institut für Zelluläre und Molekulare Physiologie, Friedrich-Alexander-Universität Erlangen-Nürnberg, Waldstrasse 6, 91054 Erlangen (Germany); Edwardson, J. Michael, E-mail: jme1000@cam.ac.uk [Department of Pharmacology, University of Cambridge, Tennis Court Road, Cambridge CB2 1PD (United Kingdom)

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. - Highlights: • There is evidence for a close association between ASIC and ENaC. • We used AFM to test whether ASIC1a and ENaC subunits form cross-clade ion channels. • Isolated proteins were incubated with subunit-specific antibodies and Fab fragments. • Some proteins were doubly decorated at ∼120° by an antibody and a Fab fragment. • Our results indicate the formation of ASIC1a/ENaC heterotrimers.

  12. ASIC subunit ratio and differential surface trafficking in the brain.

    Science.gov (United States)

    Wu, Junjun; Xu, Yuanyuan; Jiang, Yu-Qing; Xu, Jiangping; Hu, Youjia; Zha, Xiang-ming

    2016-01-08

    Acid-sensing ion channels (ASICs) are key mediators of acidosis-induced responses in neurons. However, little is known about the relative abundance of different ASIC subunits in the brain. Such data are fundamental for interpreting the relative contribution of ASIC1a homomers and 1a/2 heteromers to acid signaling, and essential for designing therapeutic interventions to target these channels. We used a simple biochemical approach and semi-quantitatively determined the molar ratio of ASIC1a and 2 subunits in mouse brain. Further, we investigated differential surface trafficking of ASIC1a, ASIC2a, and ASIC2b. ASIC1a subunits outnumber the sum of ASIC2a and ASIC2b. There is a region-specific variation in ASIC2a and 2b expression, with cerebellum and striatum expressing predominantly 2b and 2a, respectively. Further, we performed surface biotinylation and found that surface ASIC1a and ASIC2a ratio correlates with their total expression. In contrast, ASIC2b exhibits little surface presence in the brain. This result is consistent with increased co-localization of ASIC2b with an ER marker in 3T3 cells. Our data are the first semi-quantitative determination of relative subunit ratio of various ASICs in the brain. The differential surface trafficking of ASICs suggests that the main functional ASICs in the brain are ASIC1a homomers and 1a/2a heteromers. This finding provides important insights into the relative contribution of various ASIC complexes to acid signaling in neurons.

  13. Acid-Sensing Ion Channel 2a (ASIC2a) Promotes Surface Trafficking of ASIC2b via Heteromeric Assembly

    OpenAIRE

    Kweon, Hae-Jin; Kim, Dong-Il; Bae, Yeonju; Park, Jae-Yong; Suh, Byung-Chang

    2016-01-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that play important roles as typical proton sensors during pathophysiological conditions and normal synaptic activities. Among the ASIC subunits, ASIC2a and ASIC2b are alternative splicing products from the same gene, ACCN1. It has been shown that ASIC2 isoforms have differential subcellular distribution: ASIC2a targets the cell surface by itself, while ASIC2b resides in the ER. However, the underlying mechanism for this d...

  14. Heteromeric ASIC channels composed of ASIC2b and ASIC1a display novel channel properties and contribute to acidosis-induced neuronal death

    Science.gov (United States)

    Sherwood, Thomas W.; Lee, Kirsten G.; Gormley, Matthew G.; Askwith, Candice C.

    2011-01-01

    Acid-sensing ion channel (ASIC) subunits associate to form homomeric or heteromeric proton-gated ion channels in neurons throughout the nervous system. The ASIC1a subunit plays an important role in establishing the kinetics of proton-gated currents in the central nervous system and activation of ASIC1a homomeric channels induces neuronal death following local acidosis that accompanies cerebral ischemia. The ASIC2b subunit is expressed in the brain in a pattern that overlaps ASIC1a, yet the contribution of ASIC2b has remained elusive. We find that co-expression of ASIC2b with ASIC1a in Xenopus oocytes results in novel proton-gated currents with properties distinct from ASIC1a homomeric channels. In particular, ASIC2b/1a heteromeric channels are inhibited by the non-selective potassium channel blockers tetraethylammonium (TEA) and barium. In addition, steady-state desensitization is induced at more basic pH values and Big Dynorphin sensitivity is enhanced in these unique heteromeric channels. Cultured hippocampal neurons show proton-gated currents consistent with ASIC2b contribution and these currents are lacking in neurons from mice with an ACCN1 (ASIC2) gene disruption. Finally, we find that these ASIC2b/1a heteromeric channels contribute to acidosis-induced neuronal death. Together, our results show that ASIC2b confers unique properties to heteromeric channels in central neurons. Further, these data indicate that ASIC2, like ASIC1, plays a role in acidosis-induced neuronal death and implicate the ASIC2b/1a subtype as a novel pharmacological target to prevent neuronal injury following stroke. PMID:21715637

  15. High Rate Digital Demodulator ASIC

    Science.gov (United States)

    Ghuman, Parminder; Sheikh, Salman; Koubek, Steve; Hoy, Scott; Gray, Andrew

    1998-01-01

    The architecture of High Rate (600 Mega-bits per second) Digital Demodulator (HRDD) ASIC capable of demodulating BPSK and QPSK modulated data is presented in this paper. The advantages of all-digital processing include increased flexibility and reliability with reduced reproduction costs. Conventional serial digital processing would require high processing rates necessitating a hardware implementation in other than CMOS technology such as Gallium Arsenide (GaAs) which has high cost and power requirements. It is more desirable to use CMOS technology with its lower power requirements and higher gate density. However, digital demodulation of high data rates in CMOS requires parallel algorithms to process the sampled data at a rate lower than the data rate. The parallel processing algorithms described here were developed jointly by NASA's Goddard Space Flight Center (GSFC) and the Jet Propulsion Laboratory (JPL). The resulting all-digital receiver has the capability to demodulate BPSK, QPSK, OQPSK, and DQPSK at data rates in excess of 300 Mega-bits per second (Mbps) per channel. This paper will provide an overview of the parallel architecture and features of the HRDR ASIC. In addition, this paper will provide an over-view of the implementation of the hardware architectures used to create flexibility over conventional high rate analog or hybrid receivers. This flexibility includes a wide range of data rates, modulation schemes, and operating environments. In conclusion it will be shown how this high rate digital demodulator can be used with an off-the-shelf A/D and a flexible analog front end, both of which are numerically computer controlled, to produce a very flexible, low cost high rate digital receiver.

  16. Simulation of the D{sub s} semileptonic decay with the PANDA detector and experimental verification of the Micro-Vertex-Detector pixel readout ASIC with proton test beam

    Energy Technology Data Exchange (ETDEWEB)

    Cao, Lu

    2016-07-14

    The PANDA experiment will study a wide range of physics topics with beams of antiprotons incident on fixed proton or complex nuclear targets. One issue is the D{sub s} semileptonic decay, which is governed by the weak and strong forces. The interaction can be parameterized by a transition form factor. The performance of PANDA to measure the decay form factor of D{sup +}{sub s}→ηe{sup +}ν{sub e} is evaluated via Monte Carlo simulation. This thesis concentrates on describing the software development and the evaluation of the expected precision. A preliminary estimate of the expected count rate is obtained. In this measurement, it is essential to reconstruct the D{sub s} semileptonic decay with high efficiency and purity in order to overcome the many orders of magnitude higher background. The Micro-Vertex-Detector plays an import role in the whole tracking system. The rate capability and tracking performance of the recent ASIC prototype for the readout of the MVD is tested using a beam of high-energy protons.

  17. Local ASIC3 modulates pain and disease progression in a rat model of osteoarthritis

    Directory of Open Access Journals (Sweden)

    Izumi Masashi

    2012-08-01

    Full Text Available Abstract Background Recent data have suggested a relationship between acute arthritic pain and acid sensing ion channel 3 (ASIC3 on primary afferent fibers innervating joints. The purpose of this study was to clarify the role of ASIC3 in a rat model of osteoarthritis (OA which is considered a degenerative rather than an inflammatory disease. Methods We induced OA via intra-articular mono-iodoacetate (MIA injection, and evaluated pain-related behaviors including weight bearing measured with an incapacitance tester and paw withdrawal threshold in a von Frey hair test, histology of affected knee joint, and immunohistochemistry of knee joint afferents. We also assessed the effect of ASIC3 selective peptide blocker (APETx2 on pain behavior, disease progression, and ASIC3 expression in knee joint afferents. Results OA rats showed not only weight-bearing pain but also mechanical hyperalgesia outside the knee joint (secondary hyperalgesia. ASIC3 expression in knee joint afferents was significantly upregulated approximately twofold at Day 14. Continuous intra-articular injections of APETx2 inhibited weight distribution asymmetry and secondary hyperalgesia by attenuating ASIC3 upregulation in knee joint afferents. Histology of ipsilateral knee joint showed APETx2 worked chondroprotectively if administered in the early, but not late phase. Conclusions Local ASIC3 immunoreactive nerve is strongly associated with weight-bearing pain and secondary hyperalgesia in MIA-induced OA model. APETx2 inhibited ASIC3 upregulation in knee joint afferents regardless of the time-point of administration. Furthermore, early administration of APETx2 prevented cartilage damage. APETx2 is a novel, promising drug for OA by relieving pain and inhibiting disease progression.

  18. Multichannel wireless ECoG array ASIC devices.

    Science.gov (United States)

    DeMichele, Glenn A; Cogan, Stuart F; Troyk, Philip R; Chen, Hongnan; Hu, Zhe

    2014-01-01

    Surgical resection of epileptogenic foci is often a beneficial treatment for patients suffering debilitating seizures arising from intractable epilepsy [1], [2], [3]. Electrodes placed subdurally on the surface of the brain in the form of an ECoG array is one of the multiple methods for localizing epileptogenic zones for the purpose of defining the region for surgical resection. Currently, transcutaneous wires from ECoG grids limit the duration of time that implanted grids can be used for diagnosis. A wireless ECoG recording and stimulation system may be a solution to extend the diagnostic period. To avoid the transcutaneous connections, a 64-channel wireless silicon recording/stimulating ASIC was developed as the electronic component of a wireless ECoG array that uses SIROF electrodes on a polyimide substrate[4]. Here we describe two new ASIC devices that have been developed and tested as part of the on-going wireless ECoG system design.

  19. PADI ASIC for straw tube read-out

    Energy Technology Data Exchange (ETDEWEB)

    Pietraszko, Jerzy; Traeger, Michael; Fruehauf, Jochen; Schmidt, Christian [GSI, Darmstadt (Germany); Ciobanu, Mircea [ISS, Bucharest (Romania); Collaboration: CBM-Collaboration

    2016-07-01

    A prototype of the CBM MUCH straw tube detector consisting of six individual straws of 6mm inner diameter and 220 mm length filled with Ar/CO{sub 2} gas mixture has been tested at the COSY accelerator in Juelich. The straw tubes were connected to the FEET-PADI6-HDa PCB equipped with PADI-6 fast amplifier/discriminator ASIC. As a reference counter in this measurement the scCVD diamond detector has been used delivering excellent timing, time resolution below 100 ps (sigma), and very precise position information, below 50 μm. The demonstrated position resolution of about 160 μm of the straw tube read out with PADI-6 ASIC confirms the capability of the PADI chip and puts this development as a very attractive readout option for straw tubes and wire chambers.

  20. NINO ASIC electronics used in MRPC/TOF experiment

    International Nuclear Information System (INIS)

    Sun Yongjie; Li Cheng

    2008-01-01

    In order to meet the excellent properties of MRPC, an front-end amplifier/discriminator chip-NINO ASIC, was developed in ALICE TOF group at CERN. This ASIC was fabricated with the 0.25 μm CMOS technology. It is highly integrated and can deal with 8 channels per chip. It has differential input and is differential signal shaping and throughout transition. The peaking time of the amplifier is less than 1 ns. It has LVDS outputs and the width of the output signal depended on the charge of input. This allows the TOT measurement of HPTDC system. A position sensitive MRPC was tested with beam facility using the front-end electronics based on NINO and good results were obtained. (authors)

  1. Handbook of wafer bonding

    CERN Document Server

    Ramm, Peter; Taklo, Maaike M V

    2011-01-01

    Written by an author and editor team from microsystems companies and industry-near research organizations, this handbook and reference presents dependable, first-hand information on bonding technologies.In the first part, researchers from companies and institutions around the world discuss the most reliable and reproducible technologies for the production of bonded wafers. The second part is devoted to current and emerging applications, including microresonators, biosensors and precise measuring devices.

  2. ASIC design and data communications for the Boston retinal prosthesis.

    Science.gov (United States)

    Shire, Douglas B; Ellersick, William; Kelly, Shawn K; Doyle, Patrick; Priplata, Attila; Drohan, William; Mendoza, Oscar; Gingerich, Marcus; McKee, Bruce; Wyatt, John L; Rizzo, Joseph F

    2012-01-01

    We report on the design and testing of a custom application-specific integrated circuit (ASIC) that has been developed as a key component of the Boston retinal prosthesis. This device has been designed for patients who are blind due to age-related macular degeneration or retinitis pigmentosa. Key safety and communication features of the low-power ASIC are described, as are the highly configurable neural stimulation current waveforms that are delivered to its greater than 256 output electrodes. The ASIC was created using an 0.18 micron Si fabrication process utilizing standard 1.8 volt CMOS transistors as well as 20 volt lightly doped drain FETs. The communication system receives frequency-shift keyed inputs at 6.78 MHz from an implanted secondary coil, and transmits data back to the control unit through a lower-bandwidth channel that employs load-shift keying. The design's safety is ensured by on-board electrode voltage monitoring, stimulus charge limits, error checking of data transmitted to the implant, and comprehensive self-test and performance monitoring features. Each stimulus cycle is initiated by a transmitted word with a full 32-bit error check code. Taken together, these features allow researchers to safely and wirelessly tailor retinal stimulation and vision recovery for each patient.

  3. Si-to-Si wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Reus, Roger De; Lindahl, M.

    1997-01-01

    Anodic bonding of Si to Si four inch wafers using evaporated glass was performed in air at temperatures ranging from 300°C to 450°C. Although annealing of Si/glass structures around 340°C for 15 minutes eliminates stress, the bonded wafer pairs exhibit compressive stress. Pull testing revealed...

  4. Digital Heart-Rate Variability Parameter Monitoring and Assessment ASIC.

    Science.gov (United States)

    Massagram, W; Hafner, N; Mingqi Chen; Macchiarulo, L; Lubecke, V M; Boric-Lubecke, O

    2010-02-01

    This paper describes experimental results for an application-specific integrated circuit (ASIC), designed for digital heart rate variability (HRV) parameter monitoring and assessment. This ASIC chip measures beat-to-beat (RR) intervals and stores HRV parameters into its internal memory in real time. A wide range of short-term and long-term ECG signals obtained from Physionet was used for testing. The system detects R peaks with millisecond accuracy, and stores up to 2 min of continuous RR interval data and up to 4 min of RR interval histogram. The prototype chip was fabricated in a 0.5 ¿m complementary metal-oxide semiconductor technology on a 3×3 mm(2) die area, with a measured dynamic power consumption of 10 ¿W and measured leakage current of 2.62 nA. The HRV monitoring system including this HRV ASIC, an analog-to-digital converter, and a low complexity microcontroller was estimated to consume 32.5 ¿V, which is seven times lower power than a stand-alone microcontroller performing the same functions. Compact size, low cost, and low power consumption make this chip suitable for a miniaturized portable HRV monitoring system.

  5. Charged Particle Tracking with the Timepix ASIC

    CERN Document Server

    Akiba, Kazuyoshi; Collins, P; Crossley, M; Dumps, R; Gersabeck, M; Gligorov, Vladimir V; Llopart, X; Nicol, M; Poikela, T; Cabruja, Enric; Fleta, C; Lozano, M; Pellegrini, G; Bates, R; Eklund, L; Hynds, D; Ferre Llin, L; Maneuski, D; Parkes, C; Plackett, R; Rodrigues, E; Stewart, G; Akiba, K; van Beuzekom, M; Heijne, V; Heijne, E H M; Gordon, H; John, M; Gandelman, M; Esperante, D; Gallas, A; Vazquez Regueiro, P; Bayer, F; Michel, T; Needham, M; Artuso, M; Badman, R; Borgia, A; Garofoli, J; Wang, J; Xing, Z; Buytaert, Jan; Leflat, Alexander

    2012-01-01

    A prototype particle tracking telescope has been constructed using Timepix and Medipix ASIC hybrid pixel assemblies as the six sensing planes. Each telescope plane consisted of one 1.4 cm2 assembly, providing a 256x256 array of 55 micron square pixels. The telescope achieved a pointing resolution of 2.3 micron at the position of the device under test. During a beam test in 2009 the telescope was used to evaluate in detail the performance of two Timepix hybrid pixel assemblies; a standard planar 300 micron thick sensor, and 285 micron thick double sided 3D sensor. This paper describes a detailed charge calibration study of the pixel devices, which allows the true charge to be extracted, and reports on measurements of the charge collection characteristics and Landau distributions. The planar sensor achieved a best resolution of 4.0 micron for angled tracks, and resolutions of between 4.4 and 11 micron for perpendicular tracks, depending on the applied bias voltage. The double sided 3D sensor, which has signific...

  6. The Panda Strip Asic: Pasta

    Science.gov (United States)

    Lai, A.

    2018-01-01

    PASTA is the 64 channel front-end chip, designed in a 110 nm CMOS technology to read out the strip sensors of the Micro Vertex Detector (MVD) of the PANDA experiment. This chip provides high resolution timestamp and deposited charge information by means of the time-over-threshold technique. Its working principle is based on a predecessor, the TOFPET ASIC, that was designed for medical applications. A general restructuring of the architecture was needed, in order to meet the specific requirements imposed by the physics programme of PANDA, especially in terms of radiation tolerance, spatial constraints, and readout in absence of a first level hardware trigger. The first revision of PASTA is currently under evaluation at the Forschungszentrum Jülich, where a data acquisition system dedicated to the MVD prototypes has been developed. This paper describes the main aspect of the chip design, gives an overview of the data acquisition system used for the verification, and shows the first results regarding the performance of PASTA.

  7. Electrical Interconnections Through CMOS Wafers

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel

    2003-01-01

    Chips with integrated vias are currently the ultimate miniaturizing solution for 3D packaging of microsystems. Previously the application of vias has almost exclusively been demonstrated within MEMS technology, and only a few of these via technologies have been CMOS compatible. This thesis...... describes the development of vias through a silicon wafer containing Complementary Metal-Oxide Semiconductor (CMOS) circuitry. Two via technologies have been developed and fabricated in blank silicon wafers; one based on KOH etching of wafer through-holes and one based on DRIE of wafer through......-holes. The most promising of these technologies --- the DRIE based process --- has been implemented in CMOS wafers containing hearing aid amplifiers. The main challenges in the development of a CMOS compatible via process depend on the chosen process for etching of wafer through-holes. In the case of KOH etching...

  8. 2nd generation ASICs for CALICE/EUDET calorimeters

    International Nuclear Information System (INIS)

    Dulucq, F; Fleury, J; La Taille, C de; Martin-Chassard, G; Raux, L; Seguin-Moreau, N

    2009-01-01

    Imaging calorimetry depends heavily on the development of high performance, highly integrated readout ASICs embedded inside the detector which readout the millions of foreseen channels. Suitable ASICs prototypes have been fabricated in 2006-2007 and show good preliminary performance.

  9. A new interface weak-capacitance detection ASIC of capacitive liquid level sensor in the rocket

    Science.gov (United States)

    Yin, Liang; Qin, Yao; Liu, Xiao-Wei

    2017-11-01

    A new capacitive liquid level sensing interface weak-capacitance detection ASIC has been designed. This ASIC realized the detection of the output capacitance of the capacitive liquid level sensor, which converts the output capacitance of the capacitive liquid level sensor to voltage. The chip is fabricated in a standard 0.5μm CMOS process. The test results show that the linearity of capacitance detection of the ASIC is 0.05%, output noise is 3.7aF/Hz (when the capacitance which will be detected is 40 pF), the stability of capacitance detection is 7.4 × 10-5pF (1σ, 1h), the output zero position temperature coefficient is 4.5 uV/∘C. The test results prove that this interface ASIC can meet the requirement of high accuracy capacitance detection. Therefore, this interface ASIC can be applied in capacitive liquid level sensing and capacitive humidity sensing field.

  10. Burst Mode ASIC-Based Modem

    Science.gov (United States)

    1997-01-01

    The NASA Lewis Research Center is sponsoring the Advanced Communication Technology Insertion (ACTION) for Commercial Space Applications program. The goal of the program is to expedite the development of new technology with a clear path towards productization and enhancing the competitiveness of U.S. manufacturers. The industry has made significant investment in developing ASIC-based modem technology for continuous-mode applications and has made investigations into East, reliable acquisition of burst-mode digital communication signals. With rapid advances in analog and digital communications ICs, it is expected that more functions will be integrated onto these parts in the near future. In addition custom ASIC's can also be developed to address the areas not covered by the other IC's. Using the commercial chips and custom ASIC's, lower-cost, compact, reliable, and high-performance modems can be built for demanding satellite communication application. This report outlines a frequency-hop burst modem design based on commercially available chips.

  11. Neuroprotective Effects of Psalmotoxin-1, an Acid-Sensing Ion Channel (ASIC) Inhibitor, in Ischemia Reperfusion in Mouse Eyes.

    Science.gov (United States)

    Dibas, Adnan; Millar, Cameron; Al-Farra, Abraham; Yorio, Thomas

    2018-03-29

    The purpose of the current study is to assess changes in the expression of Acid-Sensing Ion Channel (ASIC)1a and ASIC2 in retinal ganglion cells (RGCs) after retinal ischemia and reperfusion (I/R) injury and to test if inhibition of ASIC1a provides RGC neuroprotection. Transient ischemia was induced in one eye of C57BL/6 mice by raising intraocular pressure to 120 mmHg for 60 min followed by retinal reperfusion by restoring normal pressure. RGC function was measured by Pattern electroretinography (PERG). In addition, retinal ASIC1a and ASIC2 were observed by immunohistochemistry and western blot. Changes in calpain, fodrin, heat shock protein 70 (HSP70), Brn3a, super oxide dismutase-1 (SOD1), catalase, and glutathione perioxidase-4 (GPX4) protein levels were assessed by western blot. RGC numbers were measured by immunohistochemistry on whole retinal flat mounts using anti-RNA binding protein with multiple splicing (RBPMS) antibodies. Intravitreal injection of psalmotoxin-1, a selective ASIC1a blocker, was used to assess the neuroprotective effect of ASIC1a inhibition. Levels of ASIC1a and ASIC2 after I/R increased in RGCs. Upregulation of ASIC1a but not ASIC2 was attenuated by intravitreal injection of psalmotoxin-1. I/R induced activation of calpain and degradation of fodrin, HSP70, and reduction in Brn3a. In contrast, while psalmotoxin-1 attenuated calpain activation and increased Brn3a levels, it failed to block HSP70 degradation. Unlike SOD1 protein which was reduced, catalase protein levels increased after I/R. Psalmotoxin-1, although not affecting SOD1 and GPX4, increased catalase levels significantly. Psalmotoxin-1 also increased RBPMS-labeled RGCs following I/R as judged by immunohistochemistry of retinal flat mounts. Finally, psalmotoxin-1 enhanced the amplitude of PERG following I/R, suggesting partial rescue of RGC function. Psalmotoxin-1 appears to exert a neuroprotective effect under ischemic insults and targeting inhibition of ASICs may represent a

  12. SPACIROC2: a front-end readout ASIC for the JEM-EUSO observatory

    International Nuclear Information System (INIS)

    Ahmad, S; Barrillon, P; Blin-Bondil, S; Dagoret-Campagne, S; Taille, C de La; Dulucq, F; Martin-Chassard, G; Kawasaki, Y; Miyamoto, H; Ikeda, H; Iguchi, T; Kajino, F

    2013-01-01

    The SPACIROC ASIC is designed for the JEM-EUSO observatory onboard of the International Space Station (ISS). The main goal of JEM-EUSO is to observe Extensive Air Shower (EAS) produced in the atmosphere by the passage of the high energetic extraterrestrial particles above a few 10 19 eV. A low-power, rad-hard ASIC is proposed for reading out the 64-channel Multi-Anode Photomultipliers which are going to equip the detection surface of JEM-EUSO. The two main features of this ASIC are the photon counting mode for each input and the charge-to-time (Q-to-T) conversion for the multiplexed channels. In the photon counting mode, the 100% triggering efficiency is achieved for 50 fC input charges. For the Q-to-T converter, the ASIC requires a minimum input of 2 pC. In order to comply with the strict power budget available from the ISS, the ASIC is needed to dissipate less than 1 mW/channel. The design of SPACIROC and the test results are presented in this paper.

  13. A design of a valid signal selecting and position decoding ASIC for PET using silicon photomultipliers

    International Nuclear Information System (INIS)

    Cho, M.; Lim, K.-T.; Kim, J.; Lee, C.; Cho, G.; Kim, H.; Yeom, J.-Y.; Choi, H.

    2017-01-01

    In most cases, a PET system has numerous electrical components and channel circuits and thus it would rather be a bulky product. Also, most existing systems receive analog signals from detectors which make them vulnerable to signal distortions. For these reasons, channel reduction techniques are important. In this work, an ASIC for PET module is being proposed. An ASIC chip for 16 PET detector channels, VSSPDC, has been designed and simulated. The main function of the chip is 16-to-1 channel reduction, i.e., finding the position of only the valid signals, signal timing, and magnitudes in all 16 channels at every recorded event. The ASIC comprises four of 4-channel modules and a 2 nd 4-to-1 router. A single channel module comprises a transimpedance amplifier for the silicon photomultipliers, dual comparators with high and low level references, and a logic circuitry. While the high level reference was used to test the validity of the signal, the low level reference was used for the timing. The 1-channel module of the ASIC produced an energy pulse by time-over-threshold method and it also produced a time pulse with a fixed delayed time. Since the ASIC chip outputs only a few digital pulses and does not require an external clock, it has an advantage over noise properties. The cadence simulation showed the good performance of the chip as designed.

  14. Expert System for ASIC Imaging

    Science.gov (United States)

    Gupta, Shri N.; Arshak, Khalil I.; McDonnell, Pearse; Boyce, Conor; Duggan, Andrew

    1989-07-01

    With the developments in the techniques of artificial intelligence over the last few years, development of advisory, scheduling and similar class of problems has become very convenient using tools such as PROLOG. In this paper an expert system has been described which helps lithographers and process engineers in several ways. The methodology used is to model each work station according to its input, output and control parameters, combine these work stations in a logical sequence based on past experience and work out process schedule for a job. In addition, all the requirements vis-a-vis a particular job parameters are converted into decision rules. One example is the exposure time, develop time for a wafer with different feature sizes would be different. This expert system has been written in Turbo Prolog. By building up a large number of rules, one can tune the program to any facility and use it for as diverse applications as advisory help, trouble shooting etc. Leitner (1) has described an advisory expert system that is being used at National Semiconductor. This system is quite different from the one being reported in the present paper. The approach is quite different for one. There is stress on job flow and process for another.

  15. Proton and non-proton activation of ASIC channels.

    Directory of Open Access Journals (Sweden)

    Ivan Gautschi

    Full Text Available The Acid-Sensing Ion Channels (ASIC exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

  16. Proton and non-proton activation of ASIC channels.

    Science.gov (United States)

    Gautschi, Ivan; van Bemmelen, Miguel Xavier; Schild, Laurent

    2017-01-01

    The Acid-Sensing Ion Channels (ASIC) exhibit a fast desensitizing current when activated by pH values below 7.0. By contrast, non-proton ligands are able to trigger sustained ASIC currents at physiological pHs. To analyze the functional basis of the ASIC desensitizing and sustained currents, we have used ASIC1a and ASIC2a mutants with a cysteine in the pore vestibule for covalent binding of different sulfhydryl reagents. We found that ASIC1a and ASIC2a exhibit two distinct currents, a proton-induced desensitizing current and a sustained current triggered by sulfhydryl reagents. These currents differ in their pH dependency, their sensitivity to the sulfhydryl reagents, their ionic selectivity and their relative magnitude. We propose a model for ASIC1 and ASIC2 activity where the channels can function in two distinct modes, a desensitizing mode and a sustained mode depending on the activating ligands. The pore vestibule of the channel represents a functional site for binding non-proton ligands to activate ASIC1 and ASIC2 at neutral pH and to prevent channel desensitization.

  17. ASIC For Complex Fixed-Point Arithmetic

    Science.gov (United States)

    Petilli, Stephen G.; Grimm, Michael J.; Olson, Erlend M.

    1995-01-01

    Application-specific integrated circuit (ASIC) performs 24-bit, fixed-point arithmetic operations on arrays of complex-valued input data. High-performance, wide-band arithmetic logic unit (ALU) designed for use in computing fast Fourier transforms (FFTs) and for performing ditigal filtering functions. Other applications include general computations involved in analysis of spectra and digital signal processing.

  18. Optical data transmission ASICs for the high-luminosity LHC (HL-LHC) experiments

    International Nuclear Information System (INIS)

    Li, X; Huang, G; Sun, X; Liu, G; Deng, B; Gong, D; Guo, D; Liu, C; Liu, T; Xiang, A C; Ye, J; Zhao, X; Chen, J; You, Y; He, M; Hou, S; Teng, P-K; Jin, G; Liang, H; Liang, F

    2014-01-01

    We present the design and test results of two optical data transmission ASICs for the High-Luminosity LHC (HL-LHC) experiments. These ASICs include a two-channel serializer (LOCs2) and a single-channel Vertical Cavity Surface Emitting Laser (VCSEL) driver (LOCld1V2). Both ASICs are fabricated in a commercial 0.25-μm Silicon-on-Sapphire (SoS) CMOS technology and operate at a data rate up to 8 Gbps per channel. The power consumption of LOCs2 and LOCld1V2 are 1.25 W and 0.27 W at 8-Gbps data rate, respectively. LOCld1V2 has been verified meeting the radiation-tolerance requirements for HL-LHC experiments

  19. Readout ASICs and Electronics for the 144-channel HAPDs for the Aerogel RICH at Belle II

    Science.gov (United States)

    Nishida, S.; Adachi, I.; Ikeda, H.; Hara, K.; Iijima, T.; Iwata, S.; Korpar, S.; Križan, P.; Kuroda, E.; Pestotnik, R.; Seljak, A.; Sumiyoshi, T.; Takagaki, H.

    The particle identification (PID) device in the endcap of the Belle detector will be upgraded to a ring imaging Cherenkov counter (RICH) using aerogel as a radiator at the Belle II experiment. We develop the electronics to read out the 70,000 channels of hit information from the 144-channel hybrid avalanche photodetectors (HAPD), of the aerogel RICH detector. A readout ASIC is developed to digitize the HAPD signals, and was used in a beam test with the prototype detector. The performance and plan of the ASIC is reported in this study. We have also designed the readout electronics for the aerogel RICH, which consist of front-end boards with the ASICs merger boards to collect data from the front-end boards. A front-end board that fits in the actual available space for the aerogel RICH electronics was produced.

  20. Wafer bonding applications and technology

    CERN Document Server

    Gösele, Ulrich

    2004-01-01

    During the past decade direct wafer bonding has developed into a mature materials integration technology. This book presents state-of-the-art reviews of the most important applications of wafer bonding written by experts from industry and academia. The topics include bonding-based fabrication methods of silicon-on-insulator, photonic crystals, VCSELs, SiGe-based FETs, MEMS together with hybrid integration and laser lift-off. The non-specialist will learn about the basics of wafer bonding and its various application areas, while the researcher in the field will find up-to-date information about this fast-moving area, including relevant patent information.

  1. Integrated input protection against discharges for Micro Pattern Gas Detectors readout ASICs

    International Nuclear Information System (INIS)

    Fiutowski, T.; Dąbrowski, W.; Koperny, S.; Wiącek, P.

    2017-01-01

    Immunity against possible random discharges inside active detector volume of MPGDs is one of the key aspects that should be addressed in the design of the front-end electronics. This issue becomes particularly critical for systems with high channel counts and high density readout employing the front-end electronics built as multichannel ASICs implemented in modern CMOS technologies, for which the breakdown voltages are in the range of a few Volts. The paper presents the design of various input protection structures integrated in the ASIC manufactured in a 350 nm CMOS process and test results using an electrical circuit to mimic discharges in the detectors.

  2. Cryogenic and radiation hard ASIC design for large format NIR/SWIR detector

    Science.gov (United States)

    Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

    2014-10-01

    An ASIC is developed to control and data quantization for large format NIR/SWIR detector arrays. Both cryogenic and space radiation environment issue are considered during the design. Therefore it can be integrated in the cryogenic chamber, which reduces significantly the vast amount of long wires going in and out the cryogenic chamber, i.e. benefits EMI and noise concerns, as well as the power consumption of cooling system and interfacing circuits. In this paper, we will describe the development of this prototype ASIC for image sensor driving and signal processing as well as the testing in both room and cryogenic temperature.

  3. Specification of requirements for the implementation of ASICs and FPGA in instrumentation and control systems important to safety in German NPPs

    International Nuclear Information System (INIS)

    Schnurer, G.

    2007-01-01

    This paper gives an overview concerning the design as well as the verification and validation of Application Specific Integrated Circuits (ASICs) and Field Programmable Gate Arrays (FPGA) in German NPPs which are applied to carry out I and C functions. The qualification procedures dealt with restricted on ASICs without any microcontroller core. Dependent on the different safety categories, recommendations concerning the qualification level and procedures are elaborated which have to be achieved for ASICs and FPGA. Important aspects within the framework of the expert judgement for upgrading of safety relevant I and C by ASICs and FPGA are dealt with. These aspects are of general character and are mainly focused on suitability test procedures and robustness requirements of ASICs and FPGA

  4. Laser wafering for silicon solar

    International Nuclear Information System (INIS)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-01-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W p (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs (∼20%), embodied energy, and green-house gas GHG emissions (∼50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 (micro)m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  5. Laser wafering for silicon solar.

    Energy Technology Data Exchange (ETDEWEB)

    Friedmann, Thomas Aquinas; Sweatt, William C.; Jared, Bradley Howell

    2011-03-01

    Current technology cuts solar Si wafers by a wire saw process, resulting in 50% 'kerf' loss when machining silicon from a boule or brick into a wafer. We want to develop a kerf-free laser wafering technology that promises to eliminate such wasteful wire saw processes and achieve up to a ten-fold decrease in the g/W{sub p} (grams/peak watt) polysilicon usage from the starting polysilicon material. Compared to today's technology, this will also reduce costs ({approx}20%), embodied energy, and green-house gas GHG emissions ({approx}50%). We will use short pulse laser illumination sharply focused by a solid immersion lens to produce subsurface damage in silicon such that wafers can be mechanically cleaved from a boule or brick. For this concept to succeed, we will need to develop optics, lasers, cleaving, and high throughput processing technologies capable of producing wafers with thicknesses < 50 {micro}m with high throughput (< 10 sec./wafer). Wafer thickness scaling is the 'Moore's Law' of silicon solar. Our concept will allow solar manufacturers to skip entire generations of scaling and achieve grid parity with commercial electricity rates. Yet, this idea is largely untested and a simple demonstration is needed to provide credibility for a larger scale research and development program. The purpose of this project is to lay the groundwork to demonstrate the feasibility of laser wafering. First, to design and procure on optic train suitable for producing subsurface damage in silicon with the required damage and stress profile to promote lateral cleavage of silicon. Second, to use an existing laser to produce subsurface damage in silicon, and third, to characterize the damage using scanning electron microscopy and confocal Raman spectroscopy mapping.

  6. ARTROC—a readout ASIC for GEM-based full-field XRF imaging system

    Science.gov (United States)

    Fiutowski, T.; Koperny, S.; Łach, B.; Mindur, B.; Świentek, K.; Wiącek, P.; Dąbrowski, W.

    2017-12-01

    In the paper we report on development of an Application Specific Integrated Circuit (ASIC), called ARTROC, being part of a full-field X-ray fluorescence spectroscopy (XRF) imaging system equipped with a standard three stage Gas Electron Multiplier (GEM) detector of 10×10 cm2 area. The ARTROC consists of 64 independent channels, allowing for simultaneous recording of the amplitudes (energy sub-channel) and time stamps (timing sub-channel) of incoming signals. Thanks to the implemented token-based read out of derandomizing buffers, the ASIC also provides data sparsification and full zero suppression. Reconstruction of the hit positions is performed in an external data acquisition system by matching the time stamps of signals recorded in X- and Y-strips. The amplitude information is used for centre of gravity finding in clusters of signals on neighbouring strips belonging to the same detection events. The ASIC could work in one of six gain modes and one of two speed modes. In a slower mode the maximum count rate per channel is 105/s while in a faster mode it is three times higher. The ARTROC comprises also input protection circuits against possible random discharges inside active detector volume, so it can be used without any additional input components. The ASIC has been designed in 350 nm CMOS process. The basic functionality and parameters have been evaluated using the testability functions implemented in the ASIC design. The ASIC has been also tested in a fully equipped GEM detector set-up with X-rays source.

  7. Abnormal Cardiac Autonomic Regulation in Mice Lacking ASIC3

    Directory of Open Access Journals (Sweden)

    Ching-Feng Cheng

    2014-01-01

    Full Text Available Integration of sympathetic and parasympathetic outflow is essential in maintaining normal cardiac autonomic function. Recent studies demonstrate that acid-sensing ion channel 3 (ASIC3 is a sensitive acid sensor for cardiac ischemia and prolonged mild acidification can open ASIC3 and evoke a sustained inward current that fires action potentials in cardiac sensory neurons. However, the physiological role of ASIC3 in cardiac autonomic regulation is not known. In this study, we elucidate the role of ASIC3 in cardiac autonomic function using Asic3−/− mice. Asic3−/− mice showed normal baseline heart rate and lower blood pressure as compared with their wild-type littermates. Heart rate variability analyses revealed imbalanced autonomic regulation, with decreased sympathetic function. Furthermore, Asic3−/− mice demonstrated a blunted response to isoproterenol-induced cardiac tachycardia and prolonged duration to recover to baseline heart rate. Moreover, quantitative RT-PCR analysis of gene expression in sensory ganglia and heart revealed that no gene compensation for muscarinic acetylcholines receptors and beta-adrenalin receptors were found in Asic3−/− mice. In summary, we unraveled an important role of ASIC3 in regulating cardiac autonomic function, whereby loss of ASIC3 alters the normal physiological response to ischemic stimuli, which reveals new implications for therapy in autonomic nervous system-related cardiovascular diseases.

  8. Robust Multivariable Optimization and Performance Simulation for ASIC Design

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application-specific-integrated-circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power, and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem, which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques, which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable, are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way that facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as a framework of software modules, templates, and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation.

  9. The Stimulus test stand

    International Nuclear Information System (INIS)

    Christofek, L.; Rapidis, P.; Reinhard, A.; Fermilab

    2005-01-01

    The Stimulus Test Stand was originally constructed and assembled for testing the SVX2 ASIC readout and then upgraded for SVX3 ASIC prototyping and testing. We have modified this system for SVX4 ASIC [1] prototype testing. We described the individual components below. Additional details for other hardware for SVX4 testing can be found in reference [2]. We provide a description of the Stimulus Test Stand used for prototype testing of the SVX4 chip

  10. The interaction between the first transmembrane domain and the thumb of ASIC1a is critical for its N-glycosylation and trafficking.

    Directory of Open Access Journals (Sweden)

    Lan Jing

    Full Text Available Acid-sensing ion channel-1a (ASIC1a, the primary proton receptor in the brain, contributes to multiple diseases including stroke, epilepsy and multiple sclerosis. Thus, a better understanding of its biogenesis will provide important insights into the regulation of ASIC1a in diseases. Interestingly, ASIC1a contains a large, yet well organized ectodomain, which suggests the hypothesis that correct formation of domain-domain interactions at the extracellular side is a key regulatory step for ASIC1a maturation and trafficking. We tested this hypothesis here by focusing on the interaction between the first transmembrane domain (TM1 and the thumb of ASIC1a, an interaction known to be critical in channel gating. We mutated Tyr71 and Trp287, two key residues involved in the TM1-thumb interaction in mouse ASIC1a, and found that both Y71G and W287G decreased synaptic targeting and surface expression of ASIC1a. These defects were likely due to altered folding; both mutants showed increased resistance to tryptic cleavage, suggesting a change in conformation. Moreover, both mutants lacked the maturation of N-linked glycans through mid to late Golgi. These data suggest that disrupting the interaction between TM1 and thumb alters ASIC1a folding, impedes its glycosylation and reduces its trafficking. Moreover, reducing the culture temperature, an approach commonly used to facilitate protein folding, increased ASIC1a glycosylation, surface expression, current density and slowed the rate of desensitization. These results suggest that correct folding of extracellular ectodomain plays a critical role in ASIC1a biogenesis and function.

  11. Multiproject wafers: not just for million-dollar mask sets

    Science.gov (United States)

    Morse, Richard D.

    2003-06-01

    With the advent of Reticle Enhancement Technologies (RET) such as Optical Proximity Correction (OPC) and Phase Shift Masks (PSM) required to manufacture semiconductors in the sub-wavelength era, the cost of photomask tooling has skyrocketed. On the leading edge of technology, mask set prices often exceed $1 million. This shifts an enormous burden back to designers and Electronic Design Automation (EDA) software vendors to create perfect designs at a time when the number of transistors per chip is measured in the hundreds of millions, and gigachips are on the drawing boards. Moore's Law has driven technology to incredible feats. The prime beneficiaries of the technology - memory and microprocessor (MPU) manufacturers - can continue to fit the model because wafer volumes (and chip prices in the MPU case) render tooling costs relatively insignificant. However, Application-Specific IC (ASIC) manufacturers and most foundry clients average very small wafer per reticle ratios causing a dramatic and potentially insupportable rise in the cost of manufacturing. Multi-Project wafers (MPWs) are a way to share the cost of tooling and silicon by putting more than one chip on each reticle. Lacking any unexpected breakthroughs in simulation, verification, or mask technology to reduce the cost of prototyping, more efficient use of reticle space becomes a viable and increasingly attractive choice. It is worthwhile therefore, to discuss the economics of prototyping in the sub-wavelength era and the increasing advantages of the MPW, shared-silicon approach. However, putting together a collection of different-sized chips during tapeout can be challenging and time consuming. Design compatibility, reticle field optimization, and frame generation have traditionally been the biggest worries but, with the advent of dummy-fill for planarization and RET for resolution, another layer of complexity has been added. MPW automation software is quite advanced today, but the size of the task

  12. AMPLITUDE AND TIME MEASUREMENT ASIC WITH ANALOG DERANDOMIZATION

    International Nuclear Information System (INIS)

    O CONNOR, P.; DE GERONIMO, G.; KANDASAMY, A.

    2002-01-01

    We describe a new ASIC for accurate and efficient processing of high-rate pulse signals from highly segmented detectors. In contrast to conventional approaches, this circuit affords a dramatic reduction in data volume through the use of analog techniques (precision peak detectors and time-to-amplitude converters) together with fast arbitration and sequencing logic to concentrate the data before digitization. In operation the circuit functions like a data-driven analog first-in, first-out (FIFO) memory between the preamplifiers and the ADC. Peak amplitudes of pulses arriving at any one of the 32 inputs are sampled, stored, and queued for readout and digitization through a single output port. Hit timing, pulse risetime, and channel address are also available at the output. Prototype chips have been fabricated in 0.35 micron CMOS and tested. First results indicate proper functionality for pulses down to 30 ns peaking time and input rates up to 1.6 MHz/channel. Amplitude accuracy of the peak detect and hold circuit is 0.3% (absolute). TAC accuracy is within 0.3% of full scale. Power consumption is less than 2 mW/channel. Compared with conventional techniques such as track-and-hold and analog memory, this new ASIC will enable efficient pulse height measurement at 20 to 300 times higher rates

  13. Two Aspects of ASIC Function: Synaptic Plasticity and Neuronal Injury.

    Science.gov (United States)

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-01-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. PMID:25582290

  14. Guided ultrasonic wave beam skew in silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2018-04-01

    In the photovoltaic industry, monocrystalline silicon wafers are employed for solar cells with high conversion efficiency. Micro-cracks induced by the cutting process in the thin wafers can lead to brittle wafer fracture. Guided ultrasonic waves would offer an efficient methodology for the in-process non-destructive testing of wafers to assess micro-crack density. The material anisotropy of the monocrystalline silicon leads to variations of the guided wave characteristics, depending on the propagation direction relative to the crystal orientation. Selective guided ultrasonic wave excitation was achieved using a contact piezoelectric transducer with custom-made wedges for the A0 and S0 Lamb wave modes and a transducer holder to achieve controlled contact pressure and orientation. The out-of-plane component of the guided wave propagation was measured using a non-contact laser interferometer. The phase slowness (velocity) of the two fundamental Lamb wave modes was measured experimentally for varying propagation directions relative to the crystal orientation and found to match theoretical predictions. Significant wave beam skew was observed experimentally, especially for the S0 mode, and investigated from 3D finite element simulations. Good agreement was found with the theoretical predictions based on nominal material properties of the silicon wafer. The important contribution of guided wave beam skewing effects for the non-destructive testing of silicon wafers was demonstrated.

  15. Characterisation of the NA62 GigaTracker end of column readout ASIC

    International Nuclear Information System (INIS)

    Noy, M; Rinella, G Aglieri; Fiorini, M; Jarron, P; Kaplon, J; Kluge, A; Morel, M; Perktold, L; Riedler, P; Martin, E

    2011-01-01

    The architecture and characterisation of the End Of Column demonstrator readout ASIC for the NA62 GigaTracker hybrid pixel detector is presented. This ASIC serves as a proof of principle for a pixel chip with 1800 pixels which must perform time stamping to better than 200 ps (RMS), provide 300 μm pitch position information and operate with a dead-time of 1% or less for 800 MHz-1 GHz beam rate. The demonstrator ASIC comprises a full test column with 45 pixels alongside other test structures. The timewalk correction mechanism employed is measurement of the time-over-threshold, coupled with an off-detector look-up table. The time to digital converter is a delay locked loop with 32 contributing delay cells fed with a 320 MHz to yield a nominal bin size of 97 ps. Recently, P-in-N sensors have been bump-bonded to the ASIC and characterisation of these assemblies has begun.

  16. An Implantable Versatile Electrode-Driving ASIC for Chronic Epidural Stimulation in Rats.

    Science.gov (United States)

    Giagka, Vasiliki; Eder, Clemens; Donaldson, Nick; Demosthenous, Andreas

    2015-06-01

    This paper presents the design and testing of an electrode driving application specific integrated circuit (ASIC) intended for epidural spinal cord electrical stimulation in rats. The ASIC can deliver up to 1 mA fully programmable monophasic or biphasic stimulus current pulses, to 13 electrodes selected in any possible configuration. It also supports interleaved stimulation. Communication is achieved via only 3 wires. The current source and the control of the stimulation timing were kept off-chip to reduce the heat dissipation close to the spinal cord. The ASIC was designed in a 0.18- μm high voltage CMOS process. Its output voltage compliance can be up to 25 V. It features a small core area (ASIC was developed to be suitable for integration on the epidural electrode array, and two different versions were fabricated and electrically tested. Results from both versions were almost indistinguishable. The performance of the system was verified for different loads and stimulation parameters. Its suitability to drive a passive epidural 12-electrode array in saline has also been demonstrated.

  17. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    International Nuclear Information System (INIS)

    Kim, Jung-Taek; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

    2001-01-01

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support

  18. Development of advanced I and C in nuclear power plants: ADIOS and ASICS

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jung-Taek E-mail: jtkim@nanum.kaeri.re.kr; Kwon, Kee-Choon; Hwang, In-Koo; Lee, Dong-Young; Park, Won-Man; Kim, Jung-Soo; Lee, Sang-Jeong

    2001-07-01

    In this paper Automatic Startup Intelligent Control System (ASICS) that automatically controls the PWR plant from cold shutdown to 5% of reactor power and Alarm and Diagnosis-Integrated Operator Support System (ADIOS) that is integrated with alarms, process values, and diagnostic information to an expert system focused on alarm processing are described. Nuclear Power Plant is manually controlled from cold shutdown to 5% according to the general operation procedures for startup operation of nuclear power plant. Alarm information is the primary sources to detect abnormalities in nuclear power plants or other process plants. The conventional hardwired alarm systems, characterized by one sensor-one indicator may lead the control room operators to be confused with avalanching alarms during plant transients. ASICS and ADIOS are designed to reduce the operator burden. The advances in computer software and hardware technology and also in information processing provide a good opportunity to improve the control systems and the annunciator systems of nuclear power plants or other similar process plants. It is very important to test and evaluate the performance and the function of the computer- or software-based systems like ASICS and ADIOS. The performance and the function of ASICS and ADIOS are evaluated with the real-time functional test facility and the results have shown that the developed systems are efficient and useful for operation and operator support.

  19. The Role of Custom Design in ASIC Chips

    National Research Council Canada - National Science Library

    Dally, William

    1998-01-01

    The performance of an ASIC can be greatly improved without increasing design time by judiciously employing a number of custom design techniques, including floorplanning, prerouting critical signals...

  20. Low noise preamplifier ASIC for the PANDA experiment

    International Nuclear Information System (INIS)

    Flemming, H; Wieczorek, P

    2011-01-01

    For the electromagnetic calorimeter of the PANDA detector a preamplifier ASIC named APFEL (ASIC for Panda Front-end ELectronics) has been developed at GSI. It is optimized for the readout of large area avalanche photodiodes (LAAPDs) with a capacitance of 300 pF and an event rate of 350 kHz. The ASIC has two equivalent analog channels each consisting of a charge sensitive amplifier, a shaper stage and differential output drivers. For operating the ASIC in a wide temperature range programmable voltage references are implemented on chip.

  1. Configurable Radiation Hardened High Speed Isolated Interface ASIC, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — NVE Corporation will design and build an innovative, low cost, flexible, configurable, radiation hardened, galvanically isolated, interface ASIC chip set that will...

  2. Wafer-scale micro-optics fabrication

    Science.gov (United States)

    Voelkel, Reinhard

    2012-07-01

    Micro-optics is an indispensable key enabling technology for many products and applications today. Probably the most prestigious examples are the diffractive light shaping elements used in high-end DUV lithography steppers. Highly-efficient refractive and diffractive micro-optical elements are used for precise beam and pupil shaping. Micro-optics had a major impact on the reduction of aberrations and diffraction effects in projection lithography, allowing a resolution enhancement from 250 nm to 45 nm within the past decade. Micro-optics also plays a decisive role in medical devices (endoscopes, ophthalmology), in all laser-based devices and fiber communication networks, bringing high-speed internet to our homes. Even our modern smart phones contain a variety of micro-optical elements. For example, LED flash light shaping elements, the secondary camera, ambient light and proximity sensors. Wherever light is involved, micro-optics offers the chance to further miniaturize a device, to improve its performance, or to reduce manufacturing and packaging costs. Wafer-scale micro-optics fabrication is based on technology established by the semiconductor industry. Thousands of components are fabricated in parallel on a wafer. This review paper recapitulates major steps and inventions in wafer-scale micro-optics technology. The state-of-the-art of fabrication, testing and packaging technology is summarized.

  3. Lamb wave propagation in monocrystalline silicon wafers.

    Science.gov (United States)

    Fromme, Paul; Pizzolato, Marco; Robyr, Jean-Luc; Masserey, Bernard

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness and beam skewing of the two fundamental Lamb wave modes A 0 and S 0 were investigated. Experimental measurements using contact wedge transducer excitation and laser measurement were conducted. Good agreement was found between the theoretically calculated angular dependency of the phase slowness and measurements for different propagation directions relative to the crystal orientation. Significant wave skew and beam widening was observed experimentally due to the anisotropy, especially for the S 0 mode. Explicit finite element simulations were conducted to visualize and quantify the guided wave beam skew. Good agreement was found for the A 0 mode, but a systematic discrepancy was observed for the S 0 mode. These effects need to be considered for the non-destructive testing of wafers using guided waves.

  4. Wafer plane inspection with soft resist thresholding

    Science.gov (United States)

    Hess, Carl; Shi, Rui-fang; Wihl, Mark; Xiong, Yalin; Pang, Song

    2008-10-01

    Wafer Plane Inspection (WPI) is an inspection mode on the KLA-Tencor TeraScaTM platform that uses the high signalto- noise ratio images from the high numerical aperture microscope, and then models the entire lithographic process to enable defect detection on the wafer plane[1]. This technology meets the needs of some advanced mask manufacturers to identify the lithographically-significant defects while ignoring the other non-lithographically-significant defects. WPI accomplishes this goal by performing defect detection based on a modeled image of how the mask features would actually print in the photoresist. There are several advantages to this approach: (1) the high fidelity of the images provide a sensitivity advantage over competing approaches; (2) the ability to perform defect detection on the wafer plane allows one to only see those defects that have a printing impact on the wafer; (3) the use of modeling on the lithographic portion of the flow enables unprecedented flexibility to support arbitrary illumination profiles, process-window inspection in unit time, and combination modes to find both printing and non-printing defects. WPI is proving to be a valuable addition to the KLA-Tencor detection algorithm suite. The modeling portion of WPI uses a single resist threshold as the final step in the processing. This has been shown to be adequate on several advanced customer layers, but is not ideal for all layers. Actual resist chemistry has complicated processes including acid and base-diffusion and quench that are not consistently well-modeled with a single resist threshold. We have considered the use of an advanced resist model for WPI, but rejected it because the burdensome requirements for the calibration of the model were not practical for reticle inspection. This paper describes an alternative approach that allows for a "soft" resist threshold to be applied that provides a more robust solution for the most challenging processes. This approach is just

  5. A multichannel front end ASIC for PMT readout in LHAASO WCDA

    Science.gov (United States)

    Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

    2018-01-01

    Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

  6. A Wireless Capsule Endoscope System With Low-Power Controlling and Processing ASIC.

    Science.gov (United States)

    Xinkai Chen; Xiaoyu Zhang; Linwei Zhang; Xiaowen Li; Nan Qi; Hanjun Jiang; Zhihua Wang

    2009-02-01

    This paper presents the design of a wireless capsule endoscope system. The proposed system is mainly composed of a CMOS image sensor, a RF transceiver and a low-power controlling and processing application specific integrated circuit (ASIC). Several design challenges involving system power reduction, system miniaturization and wireless wake-up method are resolved by employing optimized system architecture, integration of an area and power efficient image compression module, a power management unit (PMU) and a novel wireless wake-up subsystem with zero standby current in the ASIC design. The ASIC has been fabricated in 0.18-mum CMOS technology with a die area of 3.4 mm * 3.3 mm. The digital baseband can work under a power supply down to 0.95 V with a power dissipation of 1.3 mW. The prototype capsule based on the ASIC and a data recorder has been developed. Test result shows that proposed system architecture with local image compression lead to an average of 45% energy reduction for transmitting an image frame.

  7. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    International Nuclear Information System (INIS)

    Erdinger, Florian

    2016-01-01

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  8. Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

    Energy Technology Data Exchange (ETDEWEB)

    Erdinger, Florian

    2016-11-22

    The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

  9. Design of a video capsule endoscopy system with low-power ASIC for monitoring gastrointestinal tract.

    Science.gov (United States)

    Liu, Gang; Yan, Guozheng; Zhu, Bingquan; Lu, Li

    2016-11-01

    In recent years, wireless capsule endoscopy (WCE) has been a state-of-the-art tool to examine disorders of the human gastrointestinal tract painlessly. However, system miniaturization, enhancement of the image-data transfer rate and power consumption reduction for the capsule are still key challenges. In this paper, a video capsule endoscopy system with a low-power controlling and processing application-specific integrated circuit (ASIC) is designed and fabricated. In the design, these challenges are resolved by employing a microimage sensor, a novel radio frequency transmitter with an on-off keying modulation rate of 20 Mbps, and an ASIC structure that includes a clock management module, a power-efficient image compression module and a power management unit. An ASIC-based prototype capsule, which measures Φ11 mm × 25 mm, has been developed here. Test results show that the designed ASIC consumes much less power than most of the other WCE systems and that its total power consumption per frame is the least. The image compression module can realize high near-lossless compression rate (3.69) and high image quality (46.2 dB). The proposed system supports multi-spectral imaging, including white light imaging and autofluorescence imaging, at a maximum frame rate of 24 fps and with a resolution of 400 × 400. Tests and in vivo trials in pigs have proved the feasibility of the entire system, but further improvements in capsule control and compression performance inside the ASIC are needed in the future.

  10. Bondability of processed glass wafers

    NARCIS (Netherlands)

    Pandraud, G.; Gui, C.; Lambeck, Paul; Pigeon, F.; Parriaux, O.; Gorecki, Christophe

    1999-01-01

    The mechanism of direct bonding at room temperature has been attributed to the short range inter-molecular and inter-atomic attraction forces, such as Van der Waals forces. Consequently, the wafer surface smoothness becomes one of the most critical parameters in this process. High surface roughness

  11. ASIC design used in high energy physics experiments

    International Nuclear Information System (INIS)

    Zhang Hongyu; Lin Tao; Wu Ling; Zhao jingwei; Gu Shudi

    1997-01-01

    The author introduces an ASIC (Application Specific Integrated Circuit) design environment based on PC. Some design tools used in such environment are also introduced. A kind of ASIC chip used in high energy physics experiment, weighting mean timer, is being developed now

  12. Introduction to the Highlights of the 26th ASIC Conference.

    Science.gov (United States)

    Nehlig, Astrid

    2017-09-10

    The 26th ASIC Conference that was held in 2016 in Kunming, China has been marking the 50th anniversary of the creation of ASIC. The meeting in China was well attended by over 400 participants from all over the world and allowed fruitful exchanges among participants from all horizons of coffee science.

  13. Acid sensing ion channel (ASIC) inhibitors exhibit anxiolytic-like activity in preclinical pharmacological models.

    Science.gov (United States)

    Dwyer, Jason M; Rizzo, Stacey J Sukoff; Neal, Sarah J; Lin, Qian; Jow, Flora; Arias, Robert L; Rosenzweig-Lipson, Sharon; Dunlop, John; Beyer, Chad E

    2009-03-01

    Acid sensing ion channels (ASICs) are proton-gated ion channels located in the central and peripheral nervous systems. Of particular interest is ASIC1a, which is located in areas associated with fear and anxiety behaviors. Recent reports suggest a role for ASIC1a in preclinical models of fear conditioning and anxiety. The present experiments evaluated various ASIC inhibitors in preclinical models of autonomic and behavioral parameters of anxiety. In addition, neurochemical studies evaluated the effects of an ASIC inhibitor (A-317567) on neurotransmitter levels in the amygdala. In electrophysiological studies using hippocampal primary neuronal cultures, three ASIC inhibitors (PcTX-1, A-317567, and amiloride) produced concentration-dependent inhibition of acid-evoked currents. In the stress-induced hyperthermia model, acute administration of psalmotoxin 1 (PcTX-1; 10-56 ng, i.c.v.), A-317567 (0.1-1.0 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) prevented stress-induced elevations in core body temperature. In the four-plate test, acute treatment with PcTX-1 (10-56 ng, i.c.v.) and A-317567 (0.01-0.1 mg/kg, i.p.), but not amiloride (3-100 mg/kg, i.p.), produced dose-dependent and significant increases in the number of punished crossings relative to vehicle-treated animals. Additionally, PcTX-1 (56-178 ng, i.c.v.), A-317567 (0.1-10 mg/kg, i.p.), and amiloride (10-100 mg/kg, i.p.) lacked significant anxiolytic-like activity in the elevated zero maze. In neurochemical studies, an infusion of A-317567 (100 microM) into the amygdala significantly elevated the extracellular levels of GABA, but not glutamate, in this brain region. These findings demonstrate that ASIC inhibition produces anxiolytic-like effects in some behavioral models and indicate a potential role for GABAergic mechanisms to underlie these anxiolytic-like effects.

  14. Wafer of Intel Pentium 4 Prescott Chips

    CERN Multimedia

    Silicon wafer with hundreds of Penryn cores (microprocessor). There are around four times as many Prescott chips can be made per wafer than with the previous generation of Northwood-core Pentium 4 processors. It is faster and cheaper.

  15. Smart Sensor ASIC for Nuclear Power Monitoring

    International Nuclear Information System (INIS)

    Kerwin, David B.; Merkel, Kenneth G.; Rouxel, Olivier

    2013-06-01

    Mixed-signal integrated circuits are used in a variety of applications where ionizing radiation is present, including satellites, space vehicles, nuclear reactor monitoring, medical imaging, and cancer therapy. While total ionizing radiation is present in each of these environments, the type of radiation (e.g. heavy ions vs. high-energy x-rays) and other environmental factors present unique challenges to the mixed-signal designer. This paper discusses a Smart Sensor radiation hardened, mixed-signal, application specific integrated circuit (ASIC) specifically designed for sensor monitoring in a nuclear reactor environment. Results after exposure to gamma rays, neutrons, and temperatures up to 200 deg. C are reported. (authors)

  16. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  17. VMM3, an ASIC for Micropattern Detectors

    CERN Document Server

    Iakovidis, Georgios; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC). It will be used in the front- end readout electronics of both the Micromegas and sTGC detectors of the New Small Wheel upgrade of the ATLAS experiment at CERN. It is being developed at Brookhaven National Laboratory and fabricated in the 130nm Global Foundries 8RF-DM process (former IBM 8RF- DM). The 64 channels ASIC has highly configurable parameters and is able to handle signals of opposite polarities and a high range of capacitances while being low noise and low on power consumption. The VMM has four independent data output paths. First is the “precision” (10-bit) amplitude and (effective) 20-bit time stamp read out continuously (250 ns dead-time per channel) or at when a trigger occurs. Second, a serial output called Address in Real Time (ART). This is the address of the channel which had a signal above threshold within the bunch crossing clock. Third, the parallel prompt outputs from all 64 channels in a variety of selectable formats...

  18. Temperature Dependent Electrical Properties of PZT Wafer

    Science.gov (United States)

    Basu, T.; Sen, S.; Seal, A.; Sen, A.

    2016-04-01

    The electrical and electromechanical properties of lead zirconate titanate (PZT) wafers were investigated and compared with PZT bulk. PZT wafers were prepared by tape casting technique. The transition temperature of both the PZT forms remained the same. The transition from an asymmetric to a symmetric shape was observed for PZT wafers at higher temperature. The piezoelectric coefficient (d 33) values obtained were 560 pc/N and 234 pc/N, and the electromechanical coupling coefficient (k p) values were 0.68 and 0.49 for bulk and wafer, respectively. The reduction in polarization after fatigue was only ~3% in case of PZT bulk and ~7% for PZT wafer.

  19. Wafer level packaging of MEMS

    International Nuclear Information System (INIS)

    Esashi, Masayoshi

    2008-01-01

    Wafer level packaging plays many important roles for MEMS (micro electro mechanical systems), including cost, yield and reliability. MEMS structures on silicon chips are encapsulated between bonded wafers or by surface micromachining, and electrical interconnections are made from the cavity. Bonding at the interface, such as glass–Si anodic bonding and metal-to-metal bonding, requires electrical interconnection through the lid vias in many cases. On the other hand, lateral electrical interconnections on the surface of the chip are used for bonding with intermediate melting materials, such as low melting point glass and solder. The cavity formed by surface micromachining is made using sacrificial etching, and the openings needed for the sacrificial etching are plugged using deposition sealing methods. Vacuum packaging methods and the structures for electrical feedthrough for the interconnection are discussed in this review. (topical review)

  20. Industrial Silicon Wafer Solar Cells

    OpenAIRE

    Neuhaus, Dirk-Holger; Münzer, Adolf

    2007-01-01

    In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future e...

  1. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    International Nuclear Information System (INIS)

    Hari Prasad, K.; Sukhwani, Menka; Saxena, Pooja; Chandratre, V.B.; Pithawa, C.K.

    2014-01-01

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

  2. ALTIROC0, a 20 pico-second time resolution ASIC for the ATLAS High Granularity Timing Detector (HGTD)

    CERN Document Server

    de la Taille, C.; Conforti, S.; Dinaucourt, P.; Martin-Chassard, G.; Seguin-Moreau, N.; Agapopoulou, C.; Makovec, N.; Serin, L.; Simion, S.

    2018-01-01

    ALTIROC0 is an 8-channel ASIC prototype designed to readout 1x1 or 2x2 mm^2 50 µm thick Low Gain Avalanche Diodes (LGAD) of the ATLAS High Granularity Timing Detector (HGTD). The targeted combined time resolution of the sensor and the readout electronics is 30 ps for one MIP. Each analog channel of the ASIC must exhibit an extremely low jitter to ensure this challenging time resolution, while keeping a low power consumption of 2 mW/channel. A “Time Over Threshold” and a “Constant Fraction Discriminator” architecture are integrated to correct for the time walk. Test bench measurements performed on the ASIC received in April 2017 are presented.

  3. A custom front-end ASIC for the readout and timing of 64 SiPM photosensors

    International Nuclear Information System (INIS)

    Bagliesi, M.G.; Avanzini, C.; Bigongiari, G.; Cecchi, R.; Kim, M.Y.; Maestro, P.; Marrocchesi, P.S.; Morsani, F.

    2011-01-01

    A new class of instruments - based on Silicon PhotoMultiplier (SiPM) photosensors - are currently under development for the next generation of Astroparticle Physics experiments in future space missions. A custom front-end ASIC (Application Specific Integrated Circuit) for the readout of 64 SiPM sensors was specified in collaboration with GM-IDEAS (Norway) that designed and manufactured the ASIC. Our group developed a custom readout board equipped with a 16 bit ADC for the digitization of both pulse height and time information. A time stamp, generated by the ASIC in correspondence of the threshold crossing time, is digitized and recorded for each channel. This allows to define a narrow time window around the physics event that reduces significantly the background due to the SiPM dark count rate. In this paper, we report on the preliminary test results obtained with the readout board prototype.

  4. Study of multi-channel readout ASIC and its discrete module for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Fan Lei; Zhang Shengjun; Li Xian

    2013-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout systems, it is the key part for the whole system. This project designed a multi-channel readout ASIC for general detectors. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured and tested. The discrete modules work well, and the 6-channel chip NPRE 6 is ready for test in some particle detection system. (authors)

  5. A Stimulator ASIC Featuring Versatile Management for Vestibular Prostheses.

    Science.gov (United States)

    Dai Jiang; Demosthenous, Andreas; Perkins, Timothy; Xiao Liu; Donaldson, Nick

    2011-04-01

    This paper presents a multichannel stimulator ASIC for an implantable vestibular prosthesis. The system features versatile stimulation management which allows fine setting of the parameters for biphasic stimulation pulses. To address the problem of charge imbalance due to rounding errors, the digital processor can calculate and provide accurate charge correction. A technique to reduce the data rate to the stimulator is described. The stimulator ASIC was implemented in 0.6-μ m high-voltage CMOS technology occupying an area of 2.27 mm(2). The measured performance of the ASIC has been verified using vestibular electrodes in saline.

  6. Two aspects of ASIC function: Synaptic plasticity and neuronal injury.

    Science.gov (United States)

    Huang, Yan; Jiang, Nan; Li, Jun; Ji, Yong-Hua; Xiong, Zhi-Gang; Zha, Xiang-ming

    2015-07-01

    Extracellular brain pH fluctuates in both physiological and disease conditions. The main postsynaptic proton receptor is the acid-sensing ion channels (ASICs). During the past decade, much progress has been made on protons, ASICs, and neurological disease. This review summarizes the recent progress on synaptic role of protons and our current understanding of how ASICs contribute to various types of neuronal injury in the brain. This article is part of the Special Issue entitled 'Acid-Sensing Ion Channels in the Nervous System'. Copyright © 2015 Elsevier Ltd. All rights reserved.

  7. CODA : Compact front-end analog ASIC for silicon detectors

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

    2004-01-01

    The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

  8. Acid-sensing ion channels (ASICs) in the taste buds of adult zebrafish.

    Science.gov (United States)

    Viña, E; Parisi, V; Cabo, R; Laurà, R; López-Velasco, S; López-Muñiz, A; García-Suárez, O; Germanà, A; Vega, J A

    2013-03-01

    In detecting chemical properties of food, different molecules and ion channels are involved including members of the acid-sensing ion channels (ASICs) family. Consistently ASICs are present in sensory cells of taste buds of mammals. In the present study the presence of ASICs (ASIC1, ASIC2, ASIC3 and ASIC4) was investigated in the taste buds of adult zebrafish (zASICs) using Western blot and immunohistochemistry. zASIC1 and zASIC3 were regularly absent from taste buds, whereas faint zASIC2 and robust zASIC4 immunoreactivities were detected in sensory cells. Moreover, zASIC2 also immunolabelled nerves supplying taste buds. The present results demonstrate for the first time the presence of zASICs in taste buds of teleosts, with different patterns to that occurring in mammals, probably due to the function of taste buds in aquatic environment and feeding. Nevertheless, the role of zASICs in taste remains to be demonstrated. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

  9. Synthesis algorithm of VLSI multipliers for ASIC

    Science.gov (United States)

    Chua, O. H.; Eldin, A. G.

    1993-01-01

    Multipliers are critical sub-blocks in ASIC design, especially for digital signal processing and communications applications. A flexible multiplier synthesis tool is developed which is capable of generating multiplier blocks for word size in the range of 4 to 256 bits. A comparison of existing multiplier algorithms is made in terms of speed, silicon area, and suitability for automated synthesis and verification of its VLSI implementation. The algorithm divides the range of supported word sizes into sub-ranges and provides each sub-range with a specific multiplier architecture for optimal speed and area. The algorithm of the synthesis tool and the multiplier architectures are presented. Circuit implementation and the automated synthesis methodology are discussed.

  10. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Short, K.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Sol-gel bonds have been produced between smooth, clean silicon substrates by spin-coating solutions containing partially hydrolysed silicon alkoxides. The two coated substrates were assembled and the resulting sandwich fired at temperatures ranging from 60 to 600 deg. C. The sol-gel coatings were characterised using attenuated total reflectance Fourier transform infrared spectroscopy, ellipsometry, and atomic force microscopy, while the corresponding bonded specimens were investigated using scanning electron microscopy and cross-sectional transmission electron microscopy. Mechanical properties were characterised using both microindentation and tensile testing. Bonding of silicon wafers has been successfully achieved at temperatures as low as 60 deg. C. At 300 deg. C, the interfacial fracture energy was 1.55 J/m 2 . At 600 deg. C, sol-gel bonding provided superior interfacial fracture energy over classical hydrophilic bonding (3.4 J/m 2 vs. 1.5 J/m 2 ). The increase in the interfacial fracture energy is related to the increase in film density due to the sintering of the sol-gel interface with increasing temperature. The superior interfacial fracture energy obtained by sol-gel bonding at low temperature is due to the formation of an interfacial layer, which chemically bonds the two sol-gel coatings on each wafer. Application of a tensile stress on the resulting bond leads to fracture of the samples at the silicon/sol-gel interface

  11. Design and Characterization of the VMM1 ASIC for Micropattern Gas Detectors

    CERN Document Server

    Metcalfe, J; The ATLAS collaboration; Fried, J; Li, S; Nambiar, N; Polychronakos, V; Vernon, E

    2013-01-01

    We present here the measurements of the first prototype VMM1 ASIC designed at Brookhaven National Laboratory in 130 nm CMOS and fabricated in spring 2012. The 64-channel ASIC features a novel design for use with several types of micropattern gas detectors. The data driven system measures peak amplitude and timing information in tracking mode and first channel hit address in trigger mode. Several programmable gain and integration times allows the flexibility to work with Micromegas, Thin Gap Chambers (TGCs), and Gas Electron Multiplier (GEM) detectors. The IC design architecture and features will be presented along with measurements characterizing the performance of the VMM1 such as noise, linearity of the response, time walk, and calibration range. The concept for use with Micromegas in ATLAS Upgrade will also be covered including characterization under test beam conditions.

  12. Irradiation of the CLARO-CMOS chip, a fast ASIC for single-photon counting

    International Nuclear Information System (INIS)

    Andreotti, M.; Baldini, W.; Calabrese, R.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Fiorini, M.; Giachero, A.; Gotti, C.; Luppi, E.; Maino, M.; Malaguti, R.; Pessina, G.; Tomassetti, L.

    2015-01-01

    The CLARO-CMOS is a prototype ASIC that allows fast photon counting with low power consumption, built in AMS 0.35 μm CMOS technology. It is intended to be used as a front-end readout for the upgraded LHCb RICH detectors. In this environment, assuming 10 years of operation at the nominal luminosity expected after the upgrade, the ASIC must withstand a total fluence of about 6×10 12 1 MeV n eq /cm 2 and a total ionising dose of 400 krad. Long term stability of the electronics front-end is essential and the effects of radiation damage on the CLARO-CMOS performance must be carefully studied. This paper describes results of multi-step irradiation tests with protons up to the dose of ~8 Mrad, including measurement of single event effects during irradiation and chip performance evaluation before and after each irradiation step

  13. A Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC

    Data.gov (United States)

    National Aeronautics and Space Administration — This projects seeks to continue the development of the Radiation Hardened Housekeeping Slave Node (RH-HKSN) ASIC. The effort has taken parallel paths by implementing...

  14. Driver ASICs for Advanced Deformable Mirrors, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — The overall goal of the SBIR program is to develop a new Application Specified Integrated Circuit (ASIC) driver to be used in driver electronics of a deformable...

  15. Extreme Temperature, Rad-Hard Power Management ASIC, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a rad-hard Application Specific Integrated Circuit (ASIC) for spacecraft power management that is functional over a temperature range of...

  16. Wafer scale oblique angle plasma etching

    Science.gov (United States)

    Burckel, David Bruce; Jarecki, Jr., Robert L.; Finnegan, Patrick Sean

    2017-05-23

    Wafer scale oblique angle etching of a semiconductor substrate is performed in a conventional plasma etch chamber by using a fixture that supports a multiple number of separate Faraday cages. Each cage is formed to include an angled grid surface and is positioned such that it will be positioned over a separate one of the die locations on the wafer surface when the fixture is placed over the wafer. The presence of the Faraday cages influences the local electric field surrounding each wafer die, re-shaping the local field to be disposed in alignment with the angled grid surface. The re-shaped plasma causes the reactive ions to follow a linear trajectory through the plasma sheath and angled grid surface, ultimately impinging the wafer surface at an angle. The selected geometry of the Faraday cage angled grid surface thus determines the angle at with the reactive ions will impinge the wafer.

  17. Readout ASIC for ILC-FPCCD vertex detector

    International Nuclear Information System (INIS)

    Takubo, Yosuke; Miyamoto, Akiya; Ikeda, Hirokazu; Yamamoto, Hitoshi; Itagaki, Kennosuke; Nagamine, Tadashi; Sugimoto, Yasuhiro

    2010-01-01

    The concept of FPCCD (Fine Pixel CCD) whose pixel size is 5x5μm 2 has been proposed as vertex detector at ILC. Since FPCCD has 128 x20,000 pixels in one readout channel, its readout poses a considerable challenge. We have developed a prototype of readout ASIC to readout the large number of pixels during the inter-train gap of the ILC beam. In this paper, we report the design and performance of the readout ASIC.

  18. Flight Test Results From the Ultra High Resolution, Electro-Optical Framing Camera Containing a 9216 by 9216 Pixel, Wafer Scale, Focal Plane Array

    National Research Council Canada - National Science Library

    Mathews, Bruce; Zwicker, Theodore

    1999-01-01

    The details of the fabrication and results of laboratory testing of the Ultra High Resolution Framing Camera containing onchip forward image motion compensation were presented to the SPIE at Airborne...

  19. MEMS packaging with etching and thinning of lid wafer to form lids and expose device wafer bond pads

    Science.gov (United States)

    Chanchani, Rajen; Nordquist, Christopher; Olsson, Roy H; Peterson, Tracy C; Shul, Randy J; Ahlers, Catalina; Plut, Thomas A; Patrizi, Gary A

    2013-12-03

    In wafer-level packaging of microelectromechanical (MEMS) devices a lid wafer is bonded to a MEMS wafer in a predermined aligned relationship. Portions of the lid wafer are removed to separate the lid wafer into lid portions that respectively correspond in alignment with MEMS devices on the MEMS wafer, and to expose areas of the MEMS wafer that respectively contain sets of bond pads respectively coupled to the MEMS devices.

  20. High Speed On-Wafer Characterization Laboratory

    Data.gov (United States)

    Federal Laboratory Consortium — At the High Speed On-Wafer Characterization Laboratory, researchers characterize and model devices operating at terahertz (THz) and millimeter-wave frequencies. The...

  1. Penggunaan Limbah Kopi Sebagai Bahan Penyusun Ransum Itik Peking dalam Bentuk Wafer Ransum Komplit

    Directory of Open Access Journals (Sweden)

    Muhammad Daud

    2013-04-01

    Full Text Available Effect of coffee waste as component of compiler ration peking duck in the form of wafer complete ration ABSTRACT. Coffee waste is a by-product of coffee processing that potential to be used as feed stuff for peking duck. The weakness of this coffee waste, among others, is perishable, voluminous (bulky and the availability was fluctuated so the processing technology is needed to make this vegetable waste to be durable, easy to stored and to be given to livestock. To solve this problem vegetable waste could be formed as wafer. This research was conducted to study effectiveness of coffee waste as component of compiler ration peking duck in the form of wafer complete ration This experiment was run in completely randomized design which consist of 4 feed treatment and 3 replications.  Ration used was consisted of  P0 = wafer complete ration 0% coffee waste (control, P1 = wafer complete ration 2,5% coffee waste, P2 = wafer complete ration 5% coffee waste, and P3 = Wafer complete ration 7,5% coffee waste. The Variables observed were: physical characteristic (aroma, color, and wafer density and palatability of wafer complete ration. Data collected was analyzed with ANOVA and Duncan Range Test would be used if the result was significantly different. The result showed that the density of wafer complete ration coffee waste was significantly (P< 0.05 differences between of treatment. Mean density wafer complete ration equal to: P0= 0,52±0,03, P1 =0,67±0,04, P2 =0,72±0,03, and P3 = 0,76±0.05 g/cm3. Wafer complete ration coffee waste palatability was significantly (P< 0.05 differences between of treatment. It is concluded that of wafer complete ration composition 5 and 7,5% coffee waste was significantly wafer palatability and gave a highest wafer density. The ration P0 was the most palatable compare to other treatments for the experimental peking duck.

  2. Friction mechanisms of silicon wafer and silicon wafer coated with diamond-like carbon film and two monolayers

    International Nuclear Information System (INIS)

    Singh, R. Arvind; Yoon, Eui Sung; Han, Hung Gu; Kong, Ho Sung

    2006-01-01

    The friction behaviour of Si-wafer, Diamond-Like Carbon (DLC) and two Self-Assembled Monolayers(SAMs) namely DiMethylDiChlorosilane (DMDC) and DiPhenyl-DiChlorosilane (DPDC) coated on Si-wafer was studied under loading conditions in milli-Newton (mN) range. Experiments were performed using a ball-on-flat type reciprocating micro-tribo tester. Glass balls with various radii 0.25 mm, 0.5 mm and 1 mm were used. The applied normal load was in the range of 1.5 mN to 4.8 mN. Results showed that the friction increased with the applied normal load in the case of all the test materials. It was also observed that friction was affected by the ball size. Friction increased with the increase in the ball size in the case of Si-wafer. The SAMs also showed a similar trend, but had lower values of friction than those of Si-wafer. Interestingly, for DLC it was observed that friction decreased with the increase in the ball size. This distinct difference in the behavior of friction in DLC was attributed to the difference in the operating mechanism. It was observed that Si-wafer and DLC exhibited wear, whereas wear was absent in the SAMs. Observations showed that solid-solid adhesion was dominant in Si-wafer, while plowing in DLC. The wear in these two materials significantly influenced their friction. In the case of SAMs their friction behaviour was largely influenced by the nature of their molecular chains

  3. Design of a Trigger Data Serializer ASIC for the Upgrade of the ATLAS Forward Muon Spectrometer

    Science.gov (United States)

    Wang, Jinhong; Guan, Liang; Chapman, J. W.; Zhou, Bing; Zhu, Junjie

    2017-12-01

    The small-strip Thin Gap Chamber (sTGC) will be used for both triggering and precision tracking purposes in the upgrade of the ATLAS forward muon spectrometer. Both sTGC pad and strip detectors are readout by a Trigger Data Serializer (TDS) ASIC in the trigger path. This ASIC has two operation modes to prepare trigger data from pad and strip detectors respectively. The pad mode (pad-TDS) collects the firing status for up to 104 pads from one detector layer and transmits the data at 4.8 Gbps to the pad trigger extractor every 25 ns. The pad trigger extractor collects pad-TDS data from eight detector layers and defines a region of interest along the path of a muon candidate. In the strip mode (strip-TDS), the deposited charges from up to 128 strips are buffered, time-stamped, and a trigger matching procedure is performed to read out strips underneath the region of interest. The strip-TDS output is also transmitted at 4.8 Gbps to the following FPGA processing circuits. Details about the ASIC design and test results are presented in this paper.

  4. CLARO: an ASIC for high rate single photon counting with multi-anode photomultipliers

    Science.gov (United States)

    Baszczyk, M.; Carniti, P.; Cassina, L.; Cotta Ramusino, A.; Dorosz, P.; Fiorini, M.; Gotti, C.; Kucewicz, W.; Malaguti, R.; Pessina, G.

    2017-08-01

    The CLARO is a radiation-hard 8-channel ASIC designed for single photon counting with multi-anode photomultiplier tubes. Each channel outputs a digital pulse when the input signal from the photomultiplier crosses a configurable threshold. The fast return to baseline, typically within 25 ns, and below 50 ns in all conditions, allows to count up to 107 hits/s on each channel, with a power consumption of about 1 mW per channel. The ASIC presented here is a much improved version of the first 4-channel prototype. The threshold can be precisely set in a wide range, between 30 ke- (5 fC) and 16 Me- (2.6 pC). The noise of the amplifier with a 10 pF input capacitance is 3.5 ke- (0.6 fC) RMS. All settings are stored in a 128-bit configuration and status register, protected against soft errors with triple modular redundancy. The paper describes the design of the ASIC at transistor-level, and demonstrates its performance on the test bench.

  5. A 130 nm ASIC prototype for the NA62 Gigatracker readout

    Energy Technology Data Exchange (ETDEWEB)

    Dellacasa, G., E-mail: gdellaca@to.infn.it [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Garbolino, S. [Universita degli Studi di Torino, Dip. Fisica Sperimentale, via Giuria 1, 10125 Torino (Italy); Marchetto, F. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); Martoiu, S. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy); CERN CH-1211, Geneve 23 (Switzerland); Mazza, G.; Rivetti, A.; Wheadon, R. [I.N.F.N. sez. Torino, via Giuria 1, 10125 Torino (Italy)

    2011-09-11

    One of the most challenging detectors of the NA62 experiment is the silicon tracker, called Gigatracker. It consists of three hybrid silicon pixel stations, each one covering an area of 27 mmx60 mm. While the maximum pixel size is fairly large, 300{mu}mx300{mu}m the system has to sustain a very high particle rate, 1.5 MHz/mm{sup 2}, which corresponds to 800 MHz for each station. To obtain an efficient tracking with such a high rate the required track timing resolution is 150 ps (rms). Therefore the front-end ASIC should provide for each pixel a 200 ps time measurement capability, thus leading to the requirement of time walk compensation and very compact TDCs. Moreover, Single Event Upset protection has to be implemented in order to protect the digital circuitry. An ASIC prototype has been realized in CMOS 130 nm technology, containing three pixel columns. The chip performs the time walk compensation by a Constant Fraction Discriminator circuit, while the time measurement is performed by a Time to Amplitude Converter based TDC, both of them implemented on each pixel cell. The End of Column circuit containing only digital logic is responsible for the data readout from the pixel cell. The whole chip works with a system clock of 160 MHz and the digital logic is SEU protected by the use of Hamming codes. The detailed architecture of the ASIC prototype and test results are presented.

  6. A Muscle Fibre Conduction Velocity Tracking ASIC for Local Fatigue Monitoring.

    Science.gov (United States)

    Koutsos, Ermis; Cretu, Vlad; Georgiou, Pantelis

    2016-12-01

    Electromyography analysis can provide information about a muscle's fatigue state by estimating Muscle Fibre Conduction Velocity (MFCV), a measure of the travelling speed of Motor Unit Action Potentials (MUAPs) in muscle tissue. MFCV better represents the physical manifestations of muscle fatigue, compared to the progressive compression of the myoelectic Power Spectral Density, hence it is more suitable for a muscle fatigue tracking system. This paper presents a novel algorithm for the estimation of MFCV using single threshold bit-stream conversion and a dedicated application-specified integrated circuit (ASIC) for its implementation, suitable for a compact, wearable and easy to use muscle fatigue monitor. The presented ASIC is implemented in a commercially available AMS 0.35 [Formula: see text] CMOS technology and utilizes a bit-stream cross-correlator that estimates the conduction velocity of the myoelectric signal in real time. A test group of 20 subjects was used to evaluate the performance of the developed ASIC, achieving good accuracy with an error of only 3.2% compared to Matlab.

  7. Development of thin film measurement program of wafer for spin etcher

    International Nuclear Information System (INIS)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul; Cho, Jung Keun; Bae, Jung Yong

    2001-01-01

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  8. Development of thin film measurement program of wafer for spin etcher

    Energy Technology Data Exchange (ETDEWEB)

    Seo, Hak Suk; Kim, No Hyu; Kim, Young Chul [Korea University of Technology and Education, Cheonan (Korea, Republic of); Cho, Jung Keun; Bae, Jung Yong [Korea DNS, Cheonan (Korea, Republic of)

    2001-11-15

    This paper proposes a thickness measurement method of silicon-oxide and poly-silicon film deposited on 12 inch silicon wafer for spin etcher. Krypton lamp is used as a light source for generating a wide-band spectrum, which is guided and focused on the wafer surface through a optical fiber cable. Interference signal from the film is detected by optical sensor to determine the thickness of the film using spectrum analysis and several signal processing techniques including curve-fitting and filtering. Test wafers with two kinds of priori-known films, silicon-oxide(100nm) and poly-silicon(300nm), are measured under the condition that the wafer is spinning at 20Hz and DI water flowing on the wafer surface. From experiment results the algorithm presented in the paper is proved to be effective with accuracy of maximum 6.5% error.

  9. A Novel Defect Inspection Method for Semiconductor Wafer Based on Magneto-Optic Imaging

    Science.gov (United States)

    Pan, Z.; Chen, L.; Li, W.; Zhang, G.; Wu, P.

    2013-03-01

    The defects of semiconductor wafer may be generated from the manufacturing processes. A novel defect inspection method of semiconductor wafer is presented in this paper. The method is based on magneto-optic imaging, which involves inducing eddy current into the wafer under test, and detecting the magnetic flux associated with eddy current distribution in the wafer by exploiting the Faraday rotation effect. The magneto-optic image being generated may contain some noises that degrade the overall image quality, therefore, in this paper, in order to remove the unwanted noise present in the magneto-optic image, the image enhancement approach using multi-scale wavelet is presented, and the image segmentation approach based on the integration of watershed algorithm and clustering strategy is given. The experimental results show that many types of defects in wafer such as hole and scratch etc. can be detected by the method proposed in this paper.

  10. Trace analysis for 300 MM wafers and processes with TXRF

    International Nuclear Information System (INIS)

    Nutsch, A.; Erdmann, V.; Zielonka, G.; Pfitzner, L.; Ryssel, H.

    2000-01-01

    Efficient fabrication of semiconductor devices is combined with an increasing size of silicon wafers. The contamination level of processes, media, and equipment has to decrease continuously. A new test laboratory for 300 mm was installed in view of the above mentioned aspects. Aside of numerous processing tools this platform consist electrical test methods, particle detection, vapor phase decomposition (VPD) preparation, and TXRF. The equipment is installed in a cleanroom. It is common to perform process or equipment control, development, evaluation and qualification with monitor wafers. The evaluation and the qualification of 300 mm equipment require direct TXRF on 300 mm wafers. A new TXRF setup was installed due to the wafer size of 300 mm. The 300 mm TXRF is equipped with tungsten and molybdenum anode. This combination allows a sensitive detection of elements with fluorescence energy below 10 keV for tungsten excitation. The molybdenum excitation enables the detection of a wide variety of elements. The detection sensitivity for the tungsten anode excited samples is ten times higher than for molybdenum anode measured samples. The system is calibrated with 1 ng Ni. This calibration shows a stability within 5 % when monitored to control system stability. Decreasing the amount of Ni linear results in a linear decrease of the measured Ni signal. This result is verified for a range of elements by multielement samples. New designs demand new processes and materials, e.g. ferroelectric layers and copper. The trace analysis of many of these materials is supported by the higher excitation energy of the molybdenum anode. Reclaim and recycling of 300 mm wafers demand for an accurate contamination control of the processes to avoid cross contamination. Polishing or etching result in modified surfaces. TXRF as a non-destructive test method allows the simultaneously detection of a variety of elements on differing surfaces in view of contamination control and process

  11. ASIC-like, proton-activated currents in rat hippocampal neurons.

    Science.gov (United States)

    Baron, Anne; Waldmann, Rainer; Lazdunski, Michel

    2002-03-01

    The expression of mRNA for acid sensing ion channels (ASIC) subunits ASIC1a, ASIC2a and ASIC2b has been reported in hippocampal neurons, but the presence of functional hippocampal ASIC channels was never assessed. We report here the first characterization of ASIC-like currents in rat hippocampal neurons in primary culture. An extracellular pH drop induces a transient Na(+) current followed by a sustained non-selective cation current. This current is highly sensitive to pH with an activation threshold around pH 6.9 and a pH(0.5) of 6.2. About half of the total peak current is inhibited by the spider toxin PcTX1, which is specific for homomeric ASIC1a channels. The remaining PcTX1-resistant ASIC-like current is increased by 300 microM Zn(2+) and, whereas not fully activated at pH 5, it shows a pH(0.5) of 6.0 between pH 7.4 and 5. We have previously shown that Zn(2+) is a co-activator of ASIC2a-containing channels. Thus, the hippocampal transient ASIC-like current appears to be generated by a mixture of homomeric ASIC1a channels and ASIC2a-containing channels, probably heteromeric ASIC1a+2a channels. The sustained non-selective current suggests the involvement of ASIC2b-containing heteromeric channels. Activation of the hippocampal ASIC-like current by a pH drop to 6.9 or 6.6 induces a transient depolarization which itself triggers an initial action potential (AP) followed by a sustained depolarization and trains of APs. Zn(2+) increases the acid sensitivity of ASIC channels, and consequently neuronal excitability. It is probably an important co-activator of ASIC channels in the central nervous system.

  12. Single event upset test structures for digital CMOS application specific integrated circuits

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Braatz, J.C.; Dao, T.A.

    1993-01-01

    An approach has been developed for the design and utilization of SEU test structures for digital CMOS ASICs. This approach minimizes the number of test structures required by categorizing ASIC library cells according to their SEU response and designing a structure to characterize each response for each category. Critical SEU response parameters extracted from these structures are used to evaluate the SEU hardness of ASIC libraries and predict the hardness of ASIC chips

  13. Methane production using resin-wafer electrodeionization

    Science.gov (United States)

    Snyder, Seth W; Lin, YuPo; Urgun-Demirtas, Meltem

    2014-03-25

    The present invention provides an efficient method for creating natural gas including the anaerobic digestion of biomass to form biogas, and the electrodeionization of biogas to form natural gas and carbon dioxide using a resin-wafer deionization (RW-EDI) system. The method may be further modified to include a wastewater treatment system and can include a chemical conditioning/dewatering system after the anaerobic digestion system. The RW-EDI system, which includes a cathode and an anode, can either comprise at least one pair of wafers, each a basic and acidic wafer, or at least one wafer comprising of a basic portion and an acidic portion. A final embodiment of the RW-EDI system can include only one basic wafer for creating natural gas.

  14. AIDA: A 16-channel amplifier ASIC to read out the advanced implantation detector array for experiments in nuclear decay spectroscopy

    Energy Technology Data Exchange (ETDEWEB)

    Braga, D. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom); Coleman-Smith, P. J. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Davinson, T. [Dept. of Physics and Astronomy, Univ. of Edinburgh, Edinburgh EH9 3JZ (United Kingdom); Lazarus, I. H. [STFC Daresbury Laboratory, Warrington WA4 4AD (United Kingdom); Page, R. D. [Dept. of Physics, Univ. of Liverpool, Oliver Lodge Laboratory, Liverpool L69 7ZE (United Kingdom); Thomas, S. [STFC Rutherford Appleton Laboratory, Didcot, OX11 0QX (United Kingdom)

    2011-07-01

    We have designed a read-out ASIC for nuclear decay spectroscopy as part of the AIDA project - the Advanced Implantation Detector Array. AIDA will be installed in experiments at the Facility for Antiproton and Ion Research in GSI, Darmstadt. The AIDA ASIC will measure the signals when unstable nuclei are implanted into the detector, followed by the much smaller signals when the nuclei subsequently decay. Implant energies can be as high as 20 GeV; decay products need to be measured down to 25 keV within just a few microseconds of the initial implants. The ASIC uses two amplifiers per detector channel, one covering the 20 GeV dynamic range, the other selectable over a 20 MeV or 1 GeV range. The amplifiers are linked together by bypass transistors which are normally switched off. The arrival of a large signal causes saturation of the low-energy amplifier and a fluctuation of the input voltage, which activates the link to the high-energy amplifier. The bypass transistors switch on and the input charge is integrated by the high-energy amplifier. The signal is shaped and stored by a peak-hold, then read out on a multiplexed output. Control logic resets the amplifiers and bypass circuit, allowing the low-energy amplifier to measure the subsequent decay signal. We present simulations and test results, demonstrating the AIDA ASIC operation over a wide range of input signals. (authors)

  15. JOINT RIGIDITY ASSESSMENT WITH PIEZOELECTRIC WAFERS AND ACOUSTIC WAVES

    International Nuclear Information System (INIS)

    Montoya, Angela C.; Maji, Arup K.

    2010-01-01

    There has been an interest in the development of rapid deployment satellites. In a modular satellite design, different panels of specific functions can be pre-manufactured. The satellite can then be assembled and tested just prior to deployment. Traditional vibration testing is time-consuming and expensive. An alternative test method to evaluate the connection between two plates will be proposed. The method investigated and described employs piezoelectric wafers to induce and sense lamb waves in two aluminum plates, which were joined by steel brackets to form an 'L-Style' joint. Lamb wave behavior and piezoelectric material properties will be discussed; the experimental setup and results will be presented. A set of 4 piezoelectric ceramic wafers were used alternately as source and sensor. The energy transmitted was shown to correlate with a mechanical assessment of the joint, demonstrating that this method of testing is a feasible and reliable way to inspect the rigidity of joints.

  16. ASIC-enabled High Resolution Optical Time Domain Reflectometer

    Science.gov (United States)

    Skendzic, Sandra

    Fiber optics has become the preferred technology in communication systems because of what it has to offer: high data transmission rates, immunity to electromagnetic interference, and lightweight, flexible cables. An optical time domain reflectometer (OTDR) provides a convenient method of locating and diagnosing faults (e.g. break in a fiber) along a fiber that can obstruct crucial optical pathways. Both the ability to resolve the precise location of the fault and distinguish between two discrete, closely spaced faults are figures of merit. This thesis presents an implementation of a high resolution OTDR through the use of a compact and programmable ASIC (application specific integrated circuit). The integration of many essential OTDR functions on a single chip is advantageous over existing commercial instruments because it enables small, lightweight packaging, and offers low power and cost efficiency. Furthermore, its compactness presents the option of placing multiple ASICs in parallel, which can conceivably ease the characterization of densely populated fiber optic networks. The OTDR ASIC consists of a tunable clock, pattern generator, precise timer, electrical receiver, and signal sampling circuit. During OTDR operation, the chip generates narrow electrical pulse, which can then be converted to optical format when coupled with an external laser diode driver. The ASIC also works with an external photodetector to measure the timing and amplitude of optical reflections in a fiber. It has a 1 cm sampling resolution, which allows for a 2 cm spatial resolution. While this OTDR ASIC has been previously demonstrated for multimode fiber fault diagnostics, this thesis focuses on extending its functionality to single mode fiber. To validate this novel approach to OTDR, this thesis is divided into five chapters: (1) introduction, (2) implementation, (3), performance of ASIC-based OTDR, (4) exploration in optical pre-amplification with a semiconductor optical amplifier, and

  17. A Radiation Hardened by Design CMOS ASIC for Thermopile Readouts

    Science.gov (United States)

    Quilligan, G.; Aslam, S.; DuMonthier, J.

    2012-01-01

    A radiation hardened by design (RHBD) mixed-signal application specific integrated circuit (ASIC) has been designed for a thermopile readout for operation in the harsh Jovian orbital environment. The multi-channel digitizer (MCD) ASIC includes 18 low noise amplifier channels which have tunable gain/filtering coefficients, a 16-bit sigma-delta analog-digital converter (SDADC) and an on-chip controller. The 18 channels, SDADC and controller were designed to operate with immunity to single event latchup (SEL) and to at least 10 Mrad total ionizing dose (TID). The ASIC also contains a radiation tolerant 16-bit 20 MHz Nyquist ADC for general purpose instrumentation digitizer needs. The ASIC is currently undergoing fabrication in a commercial 180 nm CMOS process. Although this ASIC was designed specifically for the harsh radiation environment of the NASA led JEO mission it is suitable for integration into instrumentation payloads 011 the ESA JUICE mission where the radiation hardness requirements are slightly less stringent.

  18. DST9-1, an ASIC for receiving and delivery of time signals

    International Nuclear Information System (INIS)

    Cuzon, J.C.

    1999-01-01

    In order to evaluate the 1.2 μ BiCMOS technology of AMS foundry the electronics department developed a full custom ASIC for time signal receiving and shaping according to our fast TDC pre-diffused ASIC. (author)

  19. A Low Power Application-Specific Integrated Circuit (ASIC) Implementation of Wavelet Transform/Inverse Transform

    National Research Council Canada - National Science Library

    Harvala, Daniel

    2001-01-01

    .... The ASIC is based on an existing four-chip FPGA implementation. Implementing the design using a dedicated ASIC enhances the speed, decreases chip count to a single die, and uses significantly less power compared to the FPGA implementation...

  20. Development of Charge Sensitive Preamplifier and Readout Integrate Circuit Board for High Resolution Detector using ASIC Process

    Energy Technology Data Exchange (ETDEWEB)

    Jeon, J. Y.; Kim, J. H.; Park, J. M.; Yang, J. Y.; Kim, K. Y.; Kim, Y. S. [RadTek Co., Daejeon (Korea, Republic of)

    2010-06-15

    - Design of discrete type charge sensitive amplifier for high resolution semi-conductor sensor - Design and develop the test board for the performance of charge sensitive amplifier with sensor - Performance of electrical test for the sensor and charge sensitive amplifier - Development of prototype 8 x 8 array type detector module - Noise equivalent charge test for the charge sensitive amplifier - Design and development of Micro SMD discrete type amplifier applying ASIC procedure - Development of Hybrid type charge sensitive amplifier including shape

  1. Acid-sensing ion channel (ASIC) 1a/2a heteromers have a flexible 2:1/1:2 stoichiometry.

    Science.gov (United States)

    Bartoi, Tudor; Augustinowski, Katrin; Polleichtner, Georg; Gründer, Stefan; Ulbrich, Maximilian H

    2014-06-03

    Acid-sensing ion channels (ASICs) are widely expressed proton-gated Na(+) channels playing a role in tissue acidosis and pain. A trimeric composition of ASICs has been suggested by crystallization. Upon coexpression of ASIC1a and ASIC2a in Xenopus oocytes, we observed the formation of heteromers and their coexistence with homomers by electrophysiology, but could not determine whether heteromeric complexes have a fixed subunit stoichiometry or whether certain stoichiometries are preferred over others. We therefore imaged ASICs labeled with green and red fluorescent proteins on a single-molecule level, counted bleaching steps from GFP and colocalized them with red tandem tetrameric mCherry for many individual complexes. Combinatorial analysis suggests a model of random mixing of ASIC1a and ASIC2a subunits to yield both 2:1 and 1:2 ASIC1a:ASIC2a heteromers together with ASIC1a and ASIC2a homomers.

  2. Advanced type 1 diabetes is associated with ASIC alterations in mouse lower thoracic dorsal root ganglia neurons.

    Science.gov (United States)

    Radu, Beatrice Mihaela; Dumitrescu, Diana Ionela; Marin, Adela; Banciu, Daniel Dumitru; Iancu, Adina Daniela; Selescu, Tudor; Radu, Mihai

    2014-01-01

    Acid-sensing ion channels (ASICs) from dorsal root ganglia (DRG) neurons are proton sensors during ischemia and inflammation. Little is known about their role in type 1 diabetes (T1D). Our study was focused on ASICs alterations determined by advanced T1D status. Primary neuronal cultures were obtained from lower (T9-T12) thoracic DRG neurons from Balb/c and TCR-HA(+/-)/Ins-HA(+/-) diabetic male mice (16 weeks of age). Patch-clamp recordings indicate a change in the number of small DRG neurons presenting different ASIC-type currents. Multiple molecular sites of ASICs are distinctly affected in T1D, probably due to particular steric constraints for glycans accessibility to the active site: (i) ASIC1 current inactivates faster, while ASIC2 is slower; (ii) PcTx1 partly reverts diabetes effects against ASIC1- and ASIC2-inactivations; (iii) APETx2 maintains unaltered potency against ASIC3 current amplitude, but slows ASIC3 inactivation. Immunofluorescence indicates opposite regulation of different ASIC transcripts while qRT-PCR shows that ASIC mRNA ranking (ASIC2 > ASIC1 > ASIC3) remains unaltered. In conclusion, our study has identified biochemical and biophysical ASIC changes in lower thoracic DRG neurons due to advanced T1D. As hypoalgesia is present in advanced T1D, ASICs alterations might be the cause or the consequence of diabetic insensate neuropathy.

  3. Distinct ASIC currents are expressed in rat putative nociceptors and are modulated by nerve injury.

    Science.gov (United States)

    Poirot, Olivier; Berta, Temugin; Decosterd, Isabelle; Kellenberger, Stephan

    2006-10-01

    The H(+)-gated acid-sensing ion channels (ASICs) are expressed in dorsal root ganglion (DRG) neurones. Studies with ASIC knockout mice indicated either a pro-nociceptive or a modulatory role of ASICs in pain sensation. We have investigated in freshly isolated rat DRG neurones whether neurones with different ASIC current properties exist, which may explain distinct cellular roles, and we have investigated ASIC regulation in an experimental model of neuropathic pain. Small-diameter DRG neurones expressed three different ASIC current types which were all preferentially expressed in putative nociceptors. Type 1 currents were mediated by ASIC1a homomultimers and characterized by steep pH dependence of current activation in the pH range 6.8-6.0. Type 3 currents were activated in a similar pH range as type 1, while type 2 currents were activated at pH ASIC current density. Nerve injury induced differential regulation of ASIC subunit expression and selective changes in ASIC function in DRG neurones, suggesting a complex reorganization of ASICs during the development of neuropathic pain. In summary, we describe a basis for distinct cellular functions of different ASIC types in small-diameter DRG neurones.

  4. A 32-channels, 025 mu m CMOS ASIC for the readout of the Silicon Drift Detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anelli, G; Anghinolfi, F; Martínez, M I; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the Silicon Drift Detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same chip 32 transimpedance amplifiers, a 32*256 cells analogue memory and 16 successive approximation 10 bit A /D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way; when an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial. 0.25 mu m CMOS technology. It has been extensively tested both on a bench and connected with the detector in several beam tests. In this paper both design issues and test results are presented. The commercial technology used for the design has been yield radiation tolerant with special layout techniques. Total dose irradiation tests are also presented. (13 refs).

  5. A 32-channel, 025 mum CMOS ASIC for the readout of the silicon drift detectors of the ALICE experiment

    CERN Document Server

    Mazza, G; Anghinolfi, F; Martínez, M I; Rivetti, A; Rotondo, F

    2004-01-01

    In this paper we present a 32 channel ASIC prototype for the readout of the silicon drift detectors (SDDs) of the ALICE experiment. The ASIC integrates on the same substrate 32 transimpedance amplifiers, a 32 x 256 cell analogue memory and 16 successive approximation 10 bit A/D converters. The circuit amplifies and samples at 40 MS/s the input signal in a continuous way. When an external trigger signal validates the acquisition, the sampling is stopped and the data are digitized at lower speed (0.5 MS/s). The chip has been designed and fabricated in a commercial 0.25 mum CMOS technology. It has been extensively tested both on a bench and connected with a detector in several beam tests. In this paper both design issues and test results are presented. The radiation tolerance of the design has been increased by special layout techniques. Total dose irradiation tests are also presented.

  6. Industrial Silicon Wafer Solar Cells

    Directory of Open Access Journals (Sweden)

    Dirk-Holger Neuhaus

    2007-01-01

    Full Text Available In 2006, around 86% of all wafer-based silicon solar cells were produced using screen printing to form the silver front and aluminium rear contacts and chemical vapour deposition to grow silicon nitride as the antireflection coating onto the front surface. This paper reviews this dominant solar cell technology looking into state-of-the-art equipment and corresponding processes for each process step. The main efficiency losses of this type of solar cell are analyzed to demonstrate the future efficiency potential of this technology. In research and development, more various advanced solar cell concepts have demonstrated higher efficiencies. The question which arises is “why are new solar cell concepts not transferred into industrial production more frequently?”. We look into the requirements a new solar cell technology has to fulfill to have an advantage over the current approach. Finally, we give an overview of high-efficiency concepts which have already been transferred into industrial production.

  7. Single wafer rapid thermal multiprocessing

    International Nuclear Information System (INIS)

    Saraswat, K.C.; Moslehi, M.M.; Grossman, D.D.; Wood, S.; Wright, P.; Booth, L.

    1989-01-01

    Future success in microelectronics will demand rapid innovation, rapid product introduction and ability to react to a change in technological and business climate quickly. These technological advances in integrated electronics will require development of flexible manufacturing technology for VLSI systems. However, the current approach of establishing factories for mass manufacturing of chips at a cost of more than 200 million dollars is detrimental to flexible manufacturing. The authors propose concepts of a micro factory which may be characterized by more economical small scale production, higher flexibility to accommodate many products on several processes, and faster turnaround and learning. In-situ multiprocessing equipment where several process steps can be done in sequence may be a key ingredient in this approach. For this environment to be flexible, the equipment must have ability to change processing environment, requiring extensive in-situ measurements and real time control. This paper describes the development of a novel single wafer rapid thermal multiprocessing (RTM) reactor for next generation flexible VLSI manufacturing. This reactor will combine lamp heating, remote microwave plasma and photo processing in a single cold-wall chamber, with applications for multilayer in-situ growth and deposition of dielectrics, semiconductors and metals

  8. TRP and ASIC channels mediate the antinociceptive effect of citronellyl acetate.

    Science.gov (United States)

    Rios, Emiliano Ricardo Vasconcelos; Rocha, Nayrton Flávio Moura; Carvalho, Alyne Mara Rodrigues; Vasconcelos, Leonardo Freire; Dias, Marília Leite; de Sousa, Damião Pergentino; de Sousa, Francisca Cléa Florenço; Fonteles, Marta Maria de França

    2013-05-25

    Citronellyl acetate (CAT), a monoterpene product of the secondary metabolism of plants, has been shown in the literature to possess several different biological activities. However, no antinociceptive abilities have yet been discussed. Here, we used acute pain animal models to describe the antinociceptive action of CAT. The acetic acid-induced writhing test and the paw-licking test, in which paw licking was induced by glutamate and formalin, were performed to evaluate the antinociceptive action of CAT and to determine the involvement of PKC, PKA, TRPV1, TRPA1, TRPM8 and ASIC in its antinociceptive mechanism. To do so, we induced paw-linking using agonists. CAT was administered intragastrically (25, 50, 75, 100 and 200 mg/kg), and the two higher doses caused antinociceptive effects in the acetic acid model; the highest dose reduced pain for 4h after it was administered (200 mg/kg). In the formalin test, two doses of CAT promoted antinociception in both the early and later phases of the test. The glutamate test showed that its receptors are involved in the antinociceptive mechanism of CAT. Pretreatment with CAT did not alter locomotor activity or motor coordination. In an investigation into the participation of TRP channels and ASICs in CAT's antinociceptive mechanism, we used capsaicin (2.2 μg/paw), cinnamaldehyde (10 mmol/paw), menthol (1.2 mmol/paw) and acidified saline (2% acetic acid, pH 1.98). The results showed that TRPV1, TRPM8 and ASIC, but not TRPA1, are involved in the antinociceptive mechanism. Finally, the involvement of PKC and PKA was also studied, and we showed that both play a role in the antinociceptive mechanism of CAT. The results of this work contribute information regarding the antinociceptive properties of CAT on acute pain and show that, at least in part, TRPV1, TRPM8, ASIC, glutamate receptors, PKC and PKA participate in CAT's antinociceptive mechanism. Copyright © 2013 Elsevier Ireland Ltd. All rights reserved.

  9. Wafer Cakes of Improved Amino Acid Structure

    Directory of Open Access Journals (Sweden)

    Roksolana Boidunyk

    2017-11-01

    Full Text Available The article presents the results of the study of the amino acid composition of newly developed wafer cakes with adipose fillings combined with natural additives. The appropriateness of the using non-traditional raw materials (powder of willow herb, poppy oilcake, carob, as well as skimmed milk powder in order to increase the biological value of wafer cakes and improve their amino acid composition is proven.

  10. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  11. Lamb wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Fromme, P.; Pizzolato, M.; Robyr, J-L; Masserey, B.

    2018-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. Guided ultrasonic waves offer the potential to efficiently detect micro-cracks in the thin wafers. Previous studies of ultrasonic wave propagation in silicon focused on effects of material anisotropy on bulk ultrasonic waves, but the dependence of the wave propagation characteristics on the material anisotropy is not well understood for Lamb waves. The phase slowness a...

  12. Acid-sensing ion channel (ASIC) 4 predominantly localizes to an early endosome-related organelle upon heterologous expression.

    Science.gov (United States)

    Schwartz, Verena; Friedrich, Katharina; Polleichtner, Georg; Gründer, Stefan

    2015-12-15

    Acid-sensing ion channels (ASICs) are voltage-independent proton-gated amiloride sensitive sodium channels, belonging to the DEG/ENaC gene family. Six different ASICs have been identified (ASIC1a, ASIC1b, ASIC2a, ASIC2b, ASIC3, ASIC4) that are activated by a drop in extracellular pH, either as homo- or heteromers. An exception is ASIC4, which is not activated by protons as a homomer and which does not contribute to functional heteromeric ASICs. Insensitivity of ASIC4 to protons and its comparatively low sequence identity to other ASICs (45%) raises the question whether ASIC4 may have different functions than other ASICs. In this study, we therefore investigated the subcellular localization of ASIC4 in heterologous cell lines, which revealed a surprising accumulation of the channel in early endosome-related vacuoles. Moreover, we identified an unique amino-terminal motif as important for forward-trafficking from the ER/Golgi to the early endosome-related compartment. Collectively, our results show that heterologously expressed ASIC4 predominantly resides in an intracellular endosomal compartment.

  13. On the design and implementation of a wafer yield editor

    NARCIS (Netherlands)

    Pineda de Gyvez, J.; Jess, J.A.G.

    1989-01-01

    An interactive environment is presented for the analysis of yield information required on modern integrated circuit manufacturing lines. The system estimates wafer yields and wafer-yield variations, quantifies regional yield variations within wafers, identifies clusters in wafers and/or in lots, and

  14. A 64ch readout module for PPD/MPPC/SiPM using EASIROC ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Nakamura, Isamu, E-mail: isamu.nakamura@kek.jp [KEK, 1-1 Oho Tsukuba 305-0801 (Japan); Ishijima, N.; Hanagaki, K. [Osaka University, 1-1 Machikaneyama, Toyonaka, Osaka 560-0043 (Japan); Yoshimura, K. [Okayama University, 1-1 Tsushimanaka, Kita-ku, Okayama 700-8530 (Japan); Nakai, Y. [Kyushu University, 6-10-1 Hakozaki, Higashi-ku, Fukuoka 812-8581 (Japan); Ueno, K. [KEK, 1-1 Oho Tsukuba 305-0801 (Japan)

    2015-07-01

    A readout module for PPD/MPPC/GAPD/SiPM is developed using EASIROC ASIC. The module can handle 64 PPDs and has on-board bias power supply, ADC for energy measurement, 1 ns TDC on FPGA as well as 64ch Logic output for external trigger. Controls and data transfer are through SiTCP technology implemented in FPGA. The module has NIM format for convenience, but can be operated without crate with 5 V AC/DC converter. Basic performance of production module was tested and the results are presented in the poster.

  15. Modeling the wafer temperature profile in a multiwafer LPCVD furnace

    Energy Technology Data Exchange (ETDEWEB)

    Badgwell, T.A. [Rice Univ., Houston, TX (United States). Dept. of Chemical Engineering; Trachtenberg, I.; Edgar, T.F. [Univ. of Texas, Austin, TX (United States). Dept. of Chemical Engineering

    1994-01-01

    A mathematical model has been developed to predict wafer temperatures within a hot-wall multiwafer low pressure chemical vapor deposition (LPCVD) reactor. The model predicts both axial (wafer-to-wafer) and radial (across-wafer) temperature profiles. Model predictions compare favorably with in situ wafer temperature measurements described in an earlier paper. Measured axial and radial temperature nonuniformities are explained in terms of radiative heat-transfer effects. A simulation study demonstrates how changes in the outer tube temperature profile and reactor geometry affect wafer temperatures. Reactor design changes which could improve the wafer temperature profile are discussed.

  16. Evidence for the involvement of ASIC3 in sensory mechanotransduction in proprioceptors

    Science.gov (United States)

    Lin, Shing-Hong; Cheng, Yuan-Ren; Banks, Robert W.; Min, Ming-Yuan; Bewick, Guy S.; Chen, Chih-Cheng

    2016-01-01

    Acid-sensing ion channel 3 (ASIC3) is involved in acid nociception, but its possible role in neurosensory mechanotransduction is disputed. We report here the generation of Asic3-knockout/eGFPf-knockin mice and subsequent characterization of heterogeneous expression of ASIC3 in the dorsal root ganglion (DRG). ASIC3 is expressed in parvalbumin (Pv+) proprioceptor axons innervating muscle spindles. We further generate a floxed allele of Asic3 (Asic3f/f) and probe the role of ASIC3 in mechanotransduction in neurite-bearing Pv+ DRG neurons through localized elastic matrix movements and electrophysiology. Targeted knockout of Asic3 disrupts spindle afferent sensitivity to dynamic stimuli and impairs mechanotransduction in Pv+ DRG neurons because of substrate deformation-induced neurite stretching, but not to direct neurite indentation. In behavioural tasks, global knockout (Asic3−/−) and Pv-Cre::Asic3f/f mice produce similar deficits in grid and balance beam walking tasks. We conclude that, at least in mouse, ASIC3 is a molecular determinant contributing to dynamic mechanosensitivity in proprioceptors. PMID:27161260

  17. ASIC2 Subunits Target Acid-Sensing Ion Channels to the Synapse via an Association with PSD-95

    OpenAIRE

    Zha, Xiang-ming; Costa, Vivian; Harding, Anne Marie S.; Reznikov, Leah; Benson, Christopher J.; Welsh, Michael J.

    2009-01-01

    Acid-sensing ion channel-1a (ASIC1a) mediates H+-gated current to influence normal brain physiology and impact several models of disease. Although ASIC2 subunits are widely expressed in brain and modulate ASIC1a current, their function remains poorly understood. We identified ASIC2a in dendrites, dendritic spines, and brain synaptosomes. This localization largely relied on ASIC2a binding to PSD-95 and matched that of ASIC1a, which does not co-immunoprecipitate with PSD-95. We found that ASIC2...

  18. A Batteryless Sensor ASIC for Implantable Bio-Impedance Applications.

    Science.gov (United States)

    Rodriguez, Saul; Ollmar, Stig; Waqar, Muhammad; Rusu, Ana

    2016-06-01

    The measurement of the biological tissue's electrical impedance is an active research field that has attracted a lot of attention during the last decades. Bio-impedances are closely related to a large variety of physiological conditions; therefore, they are useful for diagnosis and monitoring in many medical applications. Measuring living tissues, however, is a challenging task that poses countless technical and practical problems, in particular if the tissues need to be measured under the skin. This paper presents a bio-impedance sensor ASIC targeting a battery-free, miniature size, implantable device, which performs accurate 4-point complex impedance extraction in the frequency range from 2 kHz to 2 MHz. The ASIC is fabricated in 150 nm CMOS, has a size of 1.22 mm × 1.22 mm and consumes 165 μA from a 1.8 V power supply. The ASIC is embedded in a prototype which communicates with, and is powered by an external reader device through inductive coupling. The prototype is validated by measuring the impedances of different combinations of discrete components, measuring the electrochemical impedance of physiological solution, and performing ex vivo measurements on animal organs. The proposed ASIC is able to extract complex impedances with around 1 Ω resolution; therefore enabling accurate wireless tissue measurements.

  19. Delay 25 an ASIC for timing adjustment in LHC

    NARCIS (Netherlands)

    Furtado, H.; Schrader, J.H.R.; Marchioro, A.; Moreira, P.

    A five channel programmable delay line ASIC was designed featuring 4 channels that allow to phase delay periodic or non-periodic digital signals and a master channel that can be used to phase delay a clock signal. The master channel serves as a calibration reference guaranteeing independence from

  20. Three-dimensional stacked structured ASIC devices and methods of fabrication thereof

    Science.gov (United States)

    Shinde, Subhash L.; Teifel, John; Flores, Richard S.; Jarecki Jr., Robert L.; Bauer, Todd

    2015-11-19

    A 3D stacked sASIC is provided that includes a plurality of 2D reconfigurable structured structured ASIC (sASIC) levels interconnected through hard-wired arrays of 3D vias. The 2D sASIC levels may contain logic, memory, analog functions, and device input/output pad circuitry. During fabrication, these 2D sASIC levels are stacked on top of each other and fused together with 3D metal vias. Such 3D vias may be fabricated as through-silicon vias (TSVs). They may connect to the back-side of the 2D sASIC level, or they may be connected to top metal pads on the front-side of the 2D sASIC level.

  1. Contacting graphene in a 200 mm wafer silicon technology environment

    Science.gov (United States)

    Lisker, Marco; Lukosius, Mindaugas; Kitzmann, Julia; Fraschke, Mirko; Wolansky, Dirk; Schulze, Sebastian; Lupina, Grzegorz; Mai, Andreas

    2018-06-01

    Two different approaches for contacting graphene in a 200 mm wafer silicon technology environment were tested. The key is the opportunity to create a thin SiN passivation layer on top of the graphene protecting it from the damage by plasma processes. The first approach uses pure Ni contacts with a thickness of 200 nm. For the second attempt, Ni is used as the contact metal which substitutes the Ti compared to a standard contact hole filling process. Accordingly, the contact hole filling of this "stacked via" approach is Ni/TiN/W. We demonstrate that the second "stacked Via" is beneficial and shows contact resistances of a wafer scale process with values below 200 Ohm μm.

  2. Fabrication of High Aspect Ratio Through-Wafer Vias in CMOS Wafers for 3-D Packaging Applications

    DEFF Research Database (Denmark)

    Rasmussen, Frank Engel; Frech, J.; Heschel, M.

    2003-01-01

    A process for fabrication of through-wafer vias in CMOS wafers is presented. The process presented offers simple and well controlled fabrication of through-wafer vias using DRIE formation of wafer through-holes, low temperature deposition of through-hole insulation, doubled sided sputtering of Cr...

  3. CBC3: a CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    CERN Document Server

    Prydderch, Mark Lyndon; Bell, Stephen Jean-marc; Key-Charriere, M; Jones, Lawrence; Auzinger, Georg; Borg, Johan; Hall, Geoffrey; Pesaresi, Mark Franco; Raymond, David Mark; Uchida, Kirika; Goldstein, Joel; Seif El Nasr, Sarah

    2018-01-01

    The CBC3 is the latest version of the CMS Binary Chip ASIC for readout of the outer radial region of the upgraded CMS Tracker at HL-LHC. This 254-channel, 130nm CMOS ASIC is designed to be bump-bonded to a substrate to which sensors will be wire-bonded. It will instrument double-layer 2S-modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips. On-chip logic identifies first level trigger primitives from high transverse-momentum tracks by selecting correlated hits in the two sensors. Delivered in late 2016, the CBC3 has been under test for several months, including X-ray irradiations and SEU testing. Results and performance are reported.

  4. Porous solid ion exchange wafer for immobilizing biomolecules

    Science.gov (United States)

    Arora, Michelle B.; Hestekin, Jamie A.; Lin, YuPo J.; St. Martin, Edward J.; Snyder, Seth W.

    2007-12-11

    A porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer. Also disclosed is a porous solid ion exchange wafer having a combination of a biomolecule capture-resin and an ion-exchange resin forming a charged capture resin within said wafer containing a biomolecule with a tag. A separate bioreactor is also disclosed incorporating the wafer described above.

  5. FF-EMU: a radiation tolerant ASIC for the distribution of timing, trigger and control signals in the CMS End-Cap Muon detector

    International Nuclear Information System (INIS)

    Campagnari, C; Costantino, N; Magazzù, G; Tongiani, Claudio

    2012-01-01

    A radiation tolerant integrated circuit for the distribution of clock, trigger and control signals in the Front-End electronics of the CMS End-Cap Muon detector has been developed in the IBM CMOS 130nm technology. The circuit houses transmitter and receiver interfaces to serial links implementing the FF-LYNX protocol that allows the integrated transmission of triggers and data frames with different latency constraints. Encoder and decoder modules associate signal transitions to FF-LYNX frames. The system and the ASIC architecture and behavior and the results of test and characterization of the ASIC prototypes will be presented.

  6. Altered myogenic vasoconstriction and regulation of whole kidney blood flow in the ASIC2 knockout mouse.

    Science.gov (United States)

    Gannon, Kimberly P; McKey, Susan E; Stec, David E; Drummond, Heather A

    2015-02-15

    Previous studies from our laboratory have suggested that degenerin proteins contribute to myogenic constriction, a mechanism of blood flow regulation and protection against pressure-dependent organ injury, in renal vessels. The goal of the present study was to determine the importance of one family member, acid-sensing ion channel 2 (ASIC2), in myogenic constriction of renal interlobar arteries, myogenic regulation of whole kidney blood flow, renal injury, and blood pressure using ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice. Myogenic constriction in renal interlobar arteries was impaired in ASIC2(+/-) and ASIC2(-/-) mice, whereas constriction to KCl/phenylephrine was unchanged. Correction of whole kidney renal vascular resistance (RVR) during the first 5 s after a 10- to 20-mmHg step increase in perfusion pressure, a timeframe associated with myogenic-mediated correction of RVR, was slowed (4.2 ± 0.9, 0.3 ± 0.7, and 2.4 ± 0.3 resistance units/s in ASIC2(+/+), ASIC2(+/-), and ASIC2(-/-) mice). Although modest reductions in function were observed in ASIC2(-/-) mice, greater reductions were observed in ASIC2(+/-) mice, which may be explained by protein-protein interactions of ASIC2 with other degenerins. Isolated glomeruli from ASIC2(+/-) and ASIC2(-/-) mice had modest alterations in the expression of inflammation and injury markers (transforming growth factor-β, mouse anti-target of antiproliferative antibody-1, and nephrin), whereas ASIC2(+/-) mice had an increase in the remodeling marker collagen type III. Consistent with a more severe loss of function, mean arterial pressure was increased in ASIC2(+/-) mice (131 ± 3 mmHg) but not in ASIC2(-/-) mice (122 ± 3 vs. 117 ± 2 mmHg in ASIC2(+/+) mice). These results suggest that ASIC2 contributes to transduction of the renal myogenic response and are consistent with the protective role of myogenic constriction against renal injury and hypertension. Copyright © 2015 the American Physiological Society.

  7. Glioblastoma cancer stem cell lines express functional acid sensing ion channels ASIC1a and ASIC3

    DEFF Research Database (Denmark)

    Tian, Yuemin; Bresenitz, Pia; Reska, Anna

    2017-01-01

    Acidic microenvironment is commonly observed in tumour tissues, including glioblastoma (GBM), the most aggressive and lethal brain tumour in adults. Acid sensing ion channels (ASICs) are neuronal voltage-insensitive sodium channels, which are sensors of extracellular protons. Here we studied...

  8. X-ray analytics for 450-mm wafer; Roentgenanalytik fuer 450-mm-Wafer

    Energy Technology Data Exchange (ETDEWEB)

    Anon.

    2014-09-15

    The introduction of the 450-mm technology in the wafer fabrication and the further reduction of critical dimensions requires improved X-ray analysis methods. Therefor the PTB has concipated a metrology chamber for the characterization of 450-mm wafers, the crucial element of which is a multi-axis patent-pending manipulator.

  9. Characterization of the CBC2 readout ASIC for the CMS strip-tracker high-luminosity upgrade

    International Nuclear Information System (INIS)

    Braga, D; Hall, G; Pesaresi, M; Raymond, M; Jones, L; Murray, P; Prydderch, M

    2014-01-01

    The CMS Binary Chip 2 (CBC2) is a full-scale prototype ASIC developed for the front-end readout of the high-luminosity upgrade of the CMS silicon strip tracker. The 254-channel, 130 nm CMOS ASIC is designed for the binary readout of double-layer modules, and features cluster-width discrimination and coincidence logic for detecting high-P T track candidates. The chip was delivered in January 2013 and has since been bump-bonded to a dual-chip hybrid and extensively tested. The CBC2 is fully functional and working to specification: we present the result of electrical characterization of the chip, including gain, noise, threshold scan and power consumption, together with the performance of the stub finding logic. Finally we will outline the plan for future developments towards the production version

  10. The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

    International Nuclear Information System (INIS)

    Lafond, E.; Mur, M.; Schanne, S.

    1998-01-01

    The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

  11. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    Energy Technology Data Exchange (ETDEWEB)

    Nishino, H., E-mail: nishino@post.kek.j [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A. [Institute for Cosmic Ray Research, University of Tokyo, Chiba 277-8582 (Japan); Ishikawa, K.; Minegishi, A. [Iwatsu Test Instruments Corporation, Tokyo 168-8511 (Japan); Arai, Y. [The Institute of Particle and Nuclear Studies, KEK, Ibaraki 305-0801 (Japan)

    2009-11-11

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mVapprox3V; 0.2approx2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

  12. Performance of the First Version of VMM Front-End ASIC with Resistive Micromegas Detectors

    CERN Document Server

    The ATLAS collaboration

    2014-01-01

    This note describes the performance of the first version of a front end ASIC, VMM1, being developed for the Micromegas and sTGC detectors of the ATLAS New Small Wheel (NSW) upgrade. The VMM1 ASIC was designed by the micro-electronics group of the Instrumentation Division of Brookhaven National Laboratory. It contains 64-channels of linear, low noise amplifiers with adaptive feedback, charge amplitude peak detectors with time stamp. It can accept inputs of both polarities, features selectable gain and shaping time and has a built-in calibration system. It is designed to operate with micro-pattern gas detectors providing both trigger and tracking information. The VMM1 was tested during August 2012 test beam campaign at SPS/H6 beam line at CERN using micromegas detectors of the Muon ATLAS MicroMega Activity R&D program. We present here the VMM1 configuration, the software that was developed to achieve its operation, as well as the calibration procedure. Furthermore, we present the analysis performed with the...

  13. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    International Nuclear Information System (INIS)

    Nishino, H.; Awai, K.; Hayato, Y.; Nakayama, S.; Okumura, K.; Shiozawa, M.; Takeda, A.; Ishikawa, K.; Minegishi, A.; Arai, Y.

    2009-01-01

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders of magnitude dynamic range (0.3mV∼3V; 0.2∼2500pC), 1% charge linearity, 0.2 pC charge resolution, and 0.1 ns timing resolution. Test results on ambient temperature dependence, channel isolation, and rate dependence also meet specifications.

  14. Involvement of Opioid System, TRPM8, and ASIC Receptors in Antinociceptive Effect of Arrabidaea brachypoda (DC Bureau

    Directory of Open Access Journals (Sweden)

    Vinícius Peixoto Rodrigues

    2017-11-01

    Full Text Available Arrabidaea brachypoda (DC Bureau is a medicinal plant found in Brazil. Known as “cipó-una”, it is popularly used as a natural therapeutic agent against pain and inflammation. This study evaluated the chemical composition and antinociceptive activity of the dichloromethane fraction from the roots of A. brachypoda (DEAB and its mechanism of action. The chemical composition was characterized by high-performance liquid chromatography, and this fraction is composed only of dimeric flavonoids. The antinociceptive effect was evaluated in formalin and hot plate tests after oral administration (10–100 mg/kg in male Swiss mice. We also investigated the involvement of TRPV1 (transient receptor potential vanilloid 1, TRPA1 (transient receptor potential ankyrin 1, TRPM8 (transient receptor potential melastatin 8, and ASIC (acid-sensing ion channel, as well as the opioidergic, glutamatergic, and supraspinal pathways. Moreover, the nociceptive response was reduced (30 mg/kg in the early and late phase of the formalin test. DEAB activity appears to involve the opioid system, TRPM8, and ASIC receptors, clearly showing that the DEAB alleviates acute pain in mice and suggesting the involvement of the TRPM8 and ASIC receptors and the opioid system in acute pain relief.

  15. Involvement of Opioid System, TRPM8, and ASIC Receptors in Antinociceptive Effect of Arrabidaea brachypoda (DC) Bureau.

    Science.gov (United States)

    Rodrigues, Vinícius Peixoto; Rocha, Cláudia Quintino da; Périco, Larissa Lucena; Santos, Raquel de Cássia Dos; Ohara, Rie; Nishijima, Catarine Massucato; Ferreira Queiroz, Emerson; Wolfender, Jean-Luc; Rocha, Lúcia Regina Machado da; Santos, Adair Roberto Soares; Vilegas, Wagner; Hiruma-Lima, Clélia Akiko

    2017-11-02

    Arrabidaea brachypoda (DC) Bureau is a medicinal plant found in Brazil. Known as "cipó-una", it is popularly used as a natural therapeutic agent against pain and inflammation. This study evaluated the chemical composition and antinociceptive activity of the dichloromethane fraction from the roots of A. brachypoda (DEAB) and its mechanism of action. The chemical composition was characterized by high-performance liquid chromatography, and this fraction is composed only of dimeric flavonoids. The antinociceptive effect was evaluated in formalin and hot plate tests after oral administration (10-100 mg/kg) in male Swiss mice. We also investigated the involvement of TRPV1 (transient receptor potential vanilloid 1), TRPA1 (transient receptor potential ankyrin 1), TRPM8 (transient receptor potential melastatin 8), and ASIC (acid-sensing ion channel), as well as the opioidergic, glutamatergic, and supraspinal pathways. Moreover, the nociceptive response was reduced (30 mg/kg) in the early and late phase of the formalin test. DEAB activity appears to involve the opioid system, TRPM8, and ASIC receptors, clearly showing that the DEAB alleviates acute pain in mice and suggesting the involvement of the TRPM8 and ASIC receptors and the opioid system in acute pain relief.

  16. Wafer level 3-D ICs process technology

    CERN Document Server

    Tan, Chuan Seng; Reif, L Rafael

    2009-01-01

    This book focuses on foundry-based process technology that enables the fabrication of 3-D ICs. The core of the book discusses the technology platform for pre-packaging wafer lever 3-D ICs. However, this book does not include a detailed discussion of 3-D ICs design and 3-D packaging. This is an edited book based on chapters contributed by various experts in the field of wafer-level 3-D ICs process technology. They are from academia, research labs and industry.

  17. Making Porous Luminescent Regions In Silicon Wafers

    Science.gov (United States)

    Fathauer, Robert W.; Jones, Eric W.

    1994-01-01

    Regions damaged by ion implantation stain-etched. Porous regions within single-crystal silicon wafers fabricated by straightforward stain-etching process. Regions exhibit visible photoluminescence at room temperature and might constitute basis of novel class of optoelectronic devices. Stain-etching process has advantages over recently investigated anodic-etching process. Process works on both n-doped and p-doped silicon wafers. Related development reported in article, "Porous Si(x)Ge(1-x) Layers Within Single Crystals of Si," (NPO-18836).

  18. Microemulsion-Based Mucoadhesive Buccal Wafers: Wafer Formation, In Vitro Release, and Ex Vivo Evaluation.

    Science.gov (United States)

    Pham, Minh Nguyet; Van Vo, Toi; Tran, Van-Thanh; Tran, Phuong Ha-Lien; Tran, Thao Truong-Dinh

    2017-10-01

    Microemulsion has the potentials to enhance dissolution as well as facilitate absorption and permeation of poorly water-soluble drugs through biological membranes. However, its application to govern a controlled release buccal delivery for local treatment has not been discovered. The aim of this study is to develop microemulsion-based mucoadhesive wafers for buccal delivery based on an incorporation of the microemulsion with mucoadhesive agents and mannitol. Ratio of oil to surfactant to water in the microemulsion significantly impacted quality of the wafers. Furthermore, the combination of carbopol and mannitol played a key role in forming the desired buccal wafers. The addition of an extra 50% of water to the formulation was suitable for wafer formation by freeze-drying, which affected the appearance and distribution of carbopol in the wafers. The amount of carbopol was critical for the enhancement of mucoadhesive properties and the sustained drug release patterns. Release study presented a significant improvement of the drug release profile following sustained release for 6 h. Ex vivo mucoadhesive studies provided decisive evidence to the increased retention time of wafers along with the increased carbopol content. The success of this study indicates an encouraging strategy to formulate a controlled drug delivery system by incorporating microemulsions into mucoadhesive wafers.

  19. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Science.gov (United States)

    Lim, Stephen CB; Paech, Michael J; Sunderland, Bruce; Liu, Yandi

    2013-01-01

    Background The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. PMID:23596347

  20. A wafer mapping technique for residual stress in surface micromachined films

    International Nuclear Information System (INIS)

    Schiavone, G; Murray, J; Smith, S; Walton, A J; Desmulliez, M P Y; Mount, A R

    2016-01-01

    The design of MEMS devices employing movable structures is crucially dependant on the mechanical behaviour of the deposited materials. It is therefore important to be able to fully characterize the micromachined films and predict with confidence the mechanical properties of patterned structures. This paper presents a characterization technique that enables the residual stress in MEMS films to be mapped at the wafer level by using microstructures released by surface micromachining. These dedicated MEMS test structures and the associated measurement techniques are used to extract localized information on the strain and Young’s modulus of the film under investigation. The residual stress is then determined by numerically coupling this data with a finite element analysis of the structure. This paper illustrates the measurement routine and demonstrates it with a case study using electrochemically deposited alloys of nickel and iron, particularly prone to develop high levels of residual stress. The results show that the technique enables wafer mapping of film non-uniformities and identifies wafer-to-wafer differences. A comparison between the results obtained from the mapping technique and conventional wafer bow measurements highlights the benefits of using a procedure tailored to films that are non-uniform, patterned and surface-micromachined, as opposed to simple standard stress extraction methods. The presented technique reveals detailed information that is generally unexplored when using conventional stress extraction methods such as wafer bow measurements. (paper)

  1. A high performance multi-channel preamplifier ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1991-11-01

    A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref.

  2. ASIC and HMC designs for portable nuclear instruments

    International Nuclear Information System (INIS)

    Chandratre, V.B.

    2005-01-01

    This paper describes the seed activity done so far for realizing the goal of compact portable nuclear instruments and related instrumentation that can be designed, developed and manufactured without external constraints. This important activity requires critical components to be made in the country by tapping and gearing the established industrial units for this activity. A good deal of ground work has been carried out over a period of time in setting up IC design facility and CAD-FAB interface. There has been a close interaction with the production and semiconductor facilities to design and develop ASIC, hybrids, display devices, detectors/sensors etc. Efforts are also undertaken to develop the critical technologies that are required to fulfill the requirement. A status report on various technologies, ASIC, hybrids and their application development done in the face of out-standing challenges is being presented here. (author)

  3. Development of the ASICs for the NA62 pixel Gigatracker

    CERN Document Server

    Jarron, P

    2008-01-01

    We present the ASIC development for the readout electronics of the Gigatracker pixel detector of NA62. Specifications of this detector are challenging in terms of timing precision with a hit time stamp accuracy of 100 ps and a peak hit rate of 50 Mhits/cm2/s. A timing precision and hit rate are more than one order of magnitude faster than pixel LHC readout ASIC. The research for pixel cell design and the readout architectures are following two approaches, which are presented and discussed in this paper. Presently demonstrator prototypes are under development and SPICE simulation results of the frontend, the readout strategy and and the pixelcolumn are also presented and discussed.

  4. A high performance multi-channel preamplifier ASIC

    International Nuclear Information System (INIS)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1992-01-01

    This paper reports on a new preamplifier ASIC that has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Collliding Detector Facility. Design of the semicustom IC was completed using a Tektronix QuickChip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems

  5. A high performance multi-channel preamplifier ASIC

    International Nuclear Information System (INIS)

    Yarema, R.J.; Zimmerman, T.; Williams, W.; Binkley, M.; Huffman, T.; Wagner, R.

    1991-11-01

    A new preamplifier ASIC has been designed and built to improve performance of the VTPC (Vertex Time Projection Chamber) at Fermilab's Colliding Detector Facility. Design of the semicustom IC was completed using a Tektronix Quick-Chip 2S bipolar linear array. The ASIC has 6 channels on a chip and provides lower noise, higher gain, lower power, and lower mass packaging than the device which it replaces. Actual performance of the preamplifier was found to match very closely the simulated performance. To reduce the mass of the complete circuit board, bare IC dice were mounted directly on a G-10 substrate using COB (chip on board) techniques. The preamplifier and packaging should be applicable to numerous other systems. 1 ref

  6. High throughput batch wafer handler for 100 to 200 mm wafers

    International Nuclear Information System (INIS)

    Rathmell, R.D.; Raatz, J.E.; Becker, B.L.; Kitchen, R.L.; Luck, T.R.; Decker, J.H.

    1989-01-01

    A new batch processing end station for ion implantation has been developed for wafers of 100 to 200 mm diameter. It usilizes a spinning disk with clampless wafer support. All wafer transport is done with backside handling and is carried out in vacuum. This end station incorporates a new dose control scheme which is able to monitor the incident particle current independently of the charge state of the ions. This technique prevents errors which may be caused by charge exchange between the beam and residual gas. The design and features of this system will be reviewed and the performance to date will be presented. (orig.)

  7. An SEU analysis approach for error propagation in digital VLSI CMOS ASICs

    International Nuclear Information System (INIS)

    Baze, M.P.; Bartholet, W.G.; Dao, T.A.; Buchner, S.

    1995-01-01

    A critical issue in the development of ASIC designs is the ability to achieve first pass fabrication success. Unsuccessful fabrication runs have serious impact on ASIC costs and schedules. The ability to predict an ASICs radiation response prior to fabrication is therefore a key issue when designing ASICs for military and aerospace systems. This paper describes an analysis approach for calculating static bit error propagation in synchronous VLSI CMOS circuits developed as an aid for predicting the SEU response of ASIC's. The technique is intended for eventual application as an ASIC development simulation tool which can be used by circuit design engineers for performance evaluation during the pre-fabrication design process in much the same way that logic and timing simulators are used

  8. Multiplexed detection of cardiac biomarkers in serum with nanowire arrays using readout ASIC.

    Science.gov (United States)

    Zhang, Guo-Jun; Chai, Kevin Tshun Chuan; Luo, Henry Zhan Hong; Huang, Joon Min; Tay, Ignatius Guang Kai; Lim, Andy Eu-Jin; Je, Minkyu

    2012-05-15

    Early detection of cardiac biomarkers for diagnosis of heart attack is the key to saving lives. Conventional method of detection like the enzyme-linked immunosorbent assay (ELISA) is time consuming and low in sensitivity. Here, we present a label-free detection system consisting of an array of silicon nanowire sensors and an interface readout application specific integrated circuit (ASIC). This system provides a rapid solution that is highly sensitive and is able to perform direct simultaneous-multiplexed detection of cardiac biomarkers in serum. Nanowire sensor arrays were demonstrated to have the required selectivity and sensitivity to perform multiplexed detection of 100 fg/ml troponin T, creatine kinase MM, and creatine kinase MB in serum. A good correlation between measurements from a probe station and the readout ASIC was obtained. Our detection system is expected to address the existing limitations in cardiac health management that are currently imposed by the conventional testing platform, and opens up possibilities in the development of a miniaturized device for point-of-care diagnostic applications. Copyright © 2012 Elsevier B.V. All rights reserved.

  9. A low-power high dynamic range front-end ASIC for imaging calorimeters

    CERN Document Server

    Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

    2002-01-01

    High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

  10. Four-channel readout ASIC for silicon pad detectors

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Zamiatin, N.I.

    2000-01-01

    A custom front-end readout ASIC has been designed for silicon calorimeters supposed to be used in high-energy physics experiments. The ASIC was produced using BJT-JFET technology. It contains four channels of a fast low-noise charge-sensitive preamplifier (CSP) with inverting outputs summed by a linear adder (LA) followed by an RC-CR shaping amplifier (SA) with 30 ns peaking time. Availability of separate outputs of the CSPs and the LA makes it possible to join any number of silicon detector layers to obtain the longitudinal and transversal resolution required using only this ASIC in any silicon calorimeter minitower configuration. Noise performance is ENC=1800e - +18e - /pF at 30 ns peaking time for detector capacitance up to C d =400 pF. Rise time is 8 ns at input capacitance C d =100 pF. Power dissipation is less than 50 mW/ chip at voltage supply 5 V

  11. VeloPix ASIC for the LHCb VELO Upgrade

    CERN Multimedia

    Cid Vidal, Xabier

    2015-01-01

    The LHCb Vertex Detector (VELO) will be upgraded in 2018 along with the other subsystems of LHCb in order to enable full detector readout at 40 MHz. LHCb will run without a hardware trigger and all data will be fed directly to the software triggering algorithms in the CPU farm. The upgraded VELO is a lightweight silicon hybrid pixel detector with 55 um square pixels, operating in vacuum in close proximity to the LHC beams. The readout will be provided by a dedicated front end ASIC, dubbed VeloPix, matched to the LHCb luminosity requirements. VeloPix is a binary pixel chip with a matrix of 256 x 256 pixels, covering an area of 2 cm^2. It is designed in a 130 nm CMOS technology, and is closely related to the Timepix3, from the Medipix family of ASICs. The principal challenge that the chip has to meet is a hit rate of up to 900 Mhits/s/ASIC, resulting in a data rate of more than 16 Gbit/s. Combining pixels into groups of 2x4 super-pixels enables the use of shared logic and a reduction of bandwidth due to combine...

  12. Development and evaluation of an ultra-fast ASIC for future PET scanners using TOF-capable MPPC array detectors

    International Nuclear Information System (INIS)

    Ambe, T.; Ikeda, H.; Kataoka, J.; Matsuda, H.; Kato, T.

    2015-01-01

    We developed a front-end ASIC for future PET scanners with Time-Of-Flight (TOF) capability to be coupled with 4×4 Multi-Pixel Photon Counter (MPPC) arrays. The ASIC is designed based on the open-IP project proposed by JAXA and realized in TSMC 0.35 μm CMOS technology. The circuit comprises 16-channel, low impedance current conveyors for effectively acquiring fast MPPC signals. For precise measurement of the coincidence timing of 511-keV gamma rays, the leading-edge method was used to discriminate the signals. We first tested the time response of the ASIC by illuminating each channel of a MPPC array device 3×3 mm 2 in size with a Pico-second Light Pulsar with a light emission peak of 655 nm and pulse duration of 54 ps (FWHM). We obtained 105 ps (FWHM) on average for each channel in time jitter measurements. Moreover, we compensated for the time lag of each channel with inner delay circuits and succeeded in suppressing about a 700-ps lag to only 15 ps. This paper reports TOF measurements using back-to-back 511-keV signals, and suggests that the ASIC can be a promising device for future TOF-PET scanners based on the MPPC array. - Highlights: • We developed a newly designed large-area monolithic MPPC array. • We obtained fine gain uniformity, and good energy and time resolutions when coupled to the LYSO scintillator. • We fabricated gamma-ray camera consisting of the MPPC array and the submillimeter pixelized LYSO and GGAG scintillators. • In the flood images, each crystal of scintillator matrices was clearly resolved. • Good energy resolutions for 662 keV gamma-rays for each LYSO and GGAG scintillator matrices were obtained

  13. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    International Nuclear Information System (INIS)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

    2015-01-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  14. A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

    Energy Technology Data Exchange (ETDEWEB)

    Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

    2015-07-01

    This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

  15. ASIC channel inhibition enhances excitotoxic neuronal death in an in vitro model of spinal cord injury.

    Science.gov (United States)

    Mazzone, Graciela L; Veeraraghavan, Priyadharishini; Gonzalez-Inchauspe, Carlota; Nistri, Andrea; Uchitel, Osvaldo D

    2017-02-20

    In the spinal cord high extracellular glutamate evokes excitotoxic damage with neuronal loss and severe locomotor impairment. During the cell dysfunction process, extracellular pH becomes acid and may activate acid-sensing ion channels (ASICs) which could be important contributors to neurodegenerative pathologies. Our previous studies have shown that transient application of the glutamate analog kainate (KA) evokes delayed excitotoxic death of spinal neurons, while white matter is mainly spared. The present goal was to enquire if ASIC channels modulated KA damage in relation to locomotor network function and cell death. Mouse spinal cord slices were treated with KA (0.01 or 0.1mM) for 1h, and then washed out for 24h prior to analysis. RT-PCR results showed that KA (at 0.01mM concentration that is near-threshold for damage) increased mRNA expression of ASIC1a, ASIC1b, ASIC2 and ASIC3, an effect reversed by the ASIC inhibitor 4',6-diamidino-2-phenylindole (DAPI). A KA neurotoxic dose (0.1mM) reduced ASIC1a and ASIC2 expression. Cell viability assays demonstrated KA-induced large damage in spinal slices from mice with ASIC1a gene ablation. Likewise, immunohistochemistry indicated significant neuronal loss when KA was followed by the ASIC inhibitors DAPI or amiloride. Electrophysiological recording from ventral roots of isolated spinal cords showed that alternating oscillatory cycles were slowed down by 0.01mMKA, and intensely inhibited by subsequently applied DAPI or amiloride. Our data suggest that early rise in ASIC expression and function counteracted deleterious effects on spinal networks by raising the excitotoxicity threshold, a result with potential implications for improving neuroprotection. Copyright © 2016 IBRO. Published by Elsevier Ltd. All rights reserved.

  16. ASIC3 Channels Integrate Agmatine and Multiple Inflammatory Signals through the Nonproton Ligand Sensing Domain

    Directory of Open Access Journals (Sweden)

    Cao Hui

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channels (ASICs have long been known to sense extracellular protons and contribute to sensory perception. Peripheral ASIC3 channels represent natural sensors of acidic and inflammatory pain. We recently reported the use of a synthetic compound, 2-guanidine-4-methylquinazoline (GMQ, to identify a novel nonproton sensing domain in the ASIC3 channel, and proposed that, based on its structural similarity with GMQ, the arginine metabolite agmatine (AGM may be an endogenous nonproton ligand for ASIC3 channels. Results Here, we present further evidence for the physiological correlation between AGM and ASIC3. Among arginine metabolites, only AGM and its analog arcaine (ARC activated ASIC3 channels at neutral pH in a sustained manner similar to GMQ. In addition to the homomeric ASIC3 channels, AGM also activated heteromeric ASIC3 plus ASIC1b channels, extending its potential physiological relevance. Importantly, the process of activation by AGM was highly sensitive to mild acidosis, hyperosmolarity, arachidonic acid (AA, lactic acid and reduced extracellular Ca2+. AGM-induced ASIC3 channel activation was not through the chelation of extracellular Ca2+ as occurs with increased lactate, but rather through a direct interaction with the newly identified nonproton ligand sensing domain. Finally, AGM cooperated with the multiple inflammatory signals to cause pain-related behaviors in an ASIC3-dependent manner. Conclusions Nonproton ligand sensing domain might represent a novel mechanism for activation or sensitization of ASIC3 channels underlying inflammatory pain-sensing under in vivo conditions.

  17. Controllable laser thermal cleavage of sapphire wafers

    Science.gov (United States)

    Xu, Jiayu; Hu, Hong; Zhuang, Changhui; Ma, Guodong; Han, Junlong; Lei, Yulin

    2018-03-01

    Laser processing of substrates for light-emitting diodes (LEDs) offers advantages over other processing techniques and is therefore an active research area in both industrial and academic sectors. The processing of sapphire wafers is problematic because sapphire is a hard and brittle material. Semiconductor laser scribing processing suffers certain disadvantages that have yet to be overcome, thereby necessitating further investigation. In this work, a platform for controllable laser thermal cleavage was constructed. A sapphire LED wafer was modeled using the finite element method to simulate the thermal and stress distributions under different conditions. A guide groove cut by laser ablation before the cleavage process was observed to guide the crack extension and avoid deviation. The surface and cross section of sapphire wafers processed using controllable laser thermal cleavage were characterized by scanning electron microscopy and optical microscopy, and their morphology was compared to that of wafers processed using stealth dicing. The differences in luminous efficiency between substrates prepared using these two processing methods are explained.

  18. Optimal Wafer Cutting in Shuttle Layout Problems

    DEFF Research Database (Denmark)

    Nisted, Lasse; Pisinger, David; Altman, Avri

    2011-01-01

    . The shuttle layout problem is frequently solved in two phases: first, a floorplan of the shuttle is generated. Then, a cutting plan is found which minimizes the overall number of wafers needed to satisfy the demand of each die type. Since some die types require special production technologies, only compatible...

  19. Silicon waveguides produced by wafer bonding

    DEFF Research Database (Denmark)

    Poulsen, Mette; Jensen, Flemming; Bunk, Oliver

    2005-01-01

    X-ray waveguides are successfully produced employing standard silicon technology of UV photolithography and wafer bonding. Contrary to theoretical expectations for similar systems even 100 mu m broad guides of less than 80 nm height do not collapse and can be used as one dimensional waveguides...

  20. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang

    2014-05-20

    This paper reports a low-cost silicon wafer dicing technique using a commercial craft cutter. The 4-inch silicon wafers were scribed using a crafter cutter with a mounted diamond blade. The pre-programmed automated process can reach a minimum die feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared with other wafer dicing methods, our proposed dicing technique is extremely low cost (lower than $1,000), and suitable for silicon wafer dicing in microelectromechanical or microfluidic fields, which usually have a relatively large die dimension. The proposed dicing technique is also usable for dicing multiple project wafers, a process where dies of different dimensions are diced on the same wafer.

  1. Acid-sensing ion channel 2 (asic 2) and trkb interrelationships within the intervertebral disc.

    Science.gov (United States)

    Cuesta, Antonio; Viña, Eliseo; Cabo, Roberto; Vázquez, Gorka; Cobo, Ramón; García-Suárez, Olivia; García-Cosamalón, José; Vega, José A

    2015-01-01

    The cells of the intervertebral disc (IVD) have an unusual acidic and hyperosmotic microenvironment. They express acid-sensing ion channels (ASICs), gated by extracellular protons and mechanical forces, as well as neurotrophins and their signalling receptors. In the nervous tissues some neurotrophins regulate the expression of ASICs. The expression of ASIC2 and TrkB in human normal and degenerated IVD was assessed using quantitative-PCR, Western blot, and immunohistochemistry. Moreover, we investigated immunohistochemically the expression of ASIC2 in the IVD of TrkB-deficient mice. ASIC2 and TrkB mRNAs were found in normal human IVD and both increased significantly in degenerated IVD. ASIC2 and TrkB proteins were also found co-localized in a variable percentage of cells, being significantly higher in degenerated IVD than in controls. The murine IVD displayed ASIC2 immunoreactivity which was absent in the IVD of TrkB-deficient mice. Present results demonstrate the occurrence of ASIC2 and TrkB in the human IVD, and the increased expression of both in pathological IVD suggest their involvement in IVD degeneration. These data also suggest that TrkB-ligands might be involved in the regulation of ASIC2 expression, and therefore in mechanisms by which the IVD cells accommodate to low pH and hypertonicity.

  2. Identification of a novel protein complex containing ASIC1a and GABAA receptors and their interregulation.

    Directory of Open Access Journals (Sweden)

    Dongbo Zhao

    Full Text Available Acid-sensing ion channels (ASICs belong to the family of the epithelial sodium channel/degenerin (ENaC/DEG and are activated by extracellular protons. They are widely distributed within both the central and peripheral nervous systems. ASICs were modified by the activation of γ-aminobutyric acid receptors (GABAA, a ligand-gated chloride channels, in hippocampal neurons. In contrast, the activity of GABAA receptors were also modulated by extracellular pH. However so far, the mechanisms underlying this intermodulation remain obscure. We hypothesized that these two receptors-GABAA receptors and ASICs channels might form a novel protein complex and functionally interact with each other. In the study reported here, we found that ASICs were modified by the activation of GABAA receptors either in HEK293 cells following transient co-transfection of GABAA and ASIC1a or in primary cultured dorsal root ganglia (DRG neurons. Conversely, activation of ASIC1a also modifies the GABAA receptor-channel kinetics. Immunoassays showed that both GABAA and ASIC1a proteins were co-immunoprecipitated mutually either in HEK293 cells co-transfected with GABAA and ASIC1a or in primary cultured DRG neurons. Our results indicate that putative GABAA and ASIC1a channels functionally interact with each other, possibly via an inter-molecular association by forming a novel protein complex.

  3. A high speed serializer ASIC for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2014-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  4. Update on the high speed serializer ASIC development for ATLAS Liquid Argon calorimeter upgrade

    CERN Document Server

    Liu, T; The ATLAS collaboration

    2011-01-01

    We have been developing a serializer application-specific integrated circuit (ASIC) based on a commercial 0.25-μm silicon-on-sapphire (SOS) CMOS technology for the ATLAS liquid argon calorimeter front-end electronics upgrade. The first prototype, a 5 Gbps 16:1 serializer has been designed, fabricated, and tested in lab environment and in a 200 MeV proton beam. The test results indicate that the first prototype meets the design goals. The second prototype, a double-lane, 8 Gbps per lane serializer is under development. The post-layout simulation indicates that 8 Gbps is achievable. In this paper we present the design and the test results of the first prototype and the design and status of the second prototype.

  5. Wafer plane inspection for advanced reticle defects

    Science.gov (United States)

    Nagpal, Rajesh; Ghadiali, Firoz; Kim, Jun; Huang, Tracy; Pang, Song

    2008-05-01

    Readiness of new mask defect inspection technology is one of the key enablers for insertion & transition of the next generation technology from development into production. High volume production in mask shops and wafer fabs demands a reticle inspection system with superior sensitivity complemented by a low false defect rate to ensure fast turnaround of reticle repair and defect disposition (W. Chou et al 2007). Wafer Plane Inspection (WPI) is a novel approach to mask defect inspection, complementing the high resolution inspection capabilities of the TeraScanHR defect inspection system. WPI is accomplished by using the high resolution mask images to construct a physical mask model (D. Pettibone et al 1999). This mask model is then used to create the mask image in the wafer aerial plane. A threshold model is applied to enhance the inspectability of printing defects. WPI can eliminate the mask restrictions imposed on OPC solutions by inspection tool limitations in the past. Historically, minimum image restrictions were required to avoid nuisance inspection stops and/or subsequent loss of sensitivity to defects. WPI has the potential to eliminate these limitations by moving the mask defect inspections to the wafer plane. This paper outlines Wafer Plane Inspection technology, and explores the application of this technology to advanced reticle inspection. A total of twelve representative critical layers were inspected using WPI die-to-die mode. The results from scanning these advanced reticles have shown that applying WPI with a pixel size of 90nm (WPI P90) captures all the defects of interest (DOI) with low false defect detection rates. In validating CD predictions, the delta CDs from WPI are compared against Aerial Imaging Measurement System (AIMS), where a good correlation is established between WPI and AIMSTM.

  6. Noncontact sheet resistance measurement technique for wafer inspection

    Science.gov (United States)

    Kempa, Krzysztof; Rommel, J. Martin; Litovsky, Roman; Becla, Peter; Lojek, Bohumil; Bryson, Frank; Blake, Julian

    1995-12-01

    A new technique, MICROTHERM, has been developed for noncontact sheet resistance measurements of semiconductor wafers. It is based on the application of microwave energy to the wafer, and simultaneous detection of the infrared radiation resulting from ohmic heating. The pattern of the emitted radiation corresponds to the sheet resistance distribution across the wafer. This method is nondestructive, noncontact, and allows for measurements of very small areas (several square microns) of the wafer.

  7. Modeling of direct wafer bonding: Effect of wafer bow and etch patterns

    Science.gov (United States)

    Turner, K. T.; Spearing, S. M.

    2002-12-01

    Direct wafer bonding is an important technology for the manufacture of silicon-on-insulator substrates and microelectromechanical systems. As devices become more complex and require the bonding of multiple patterned wafers, there is a need to understand the mechanics of the bonding process. A general bonding criterion based on the competition between the strain energy accumulated in the wafers and the surface energy that is dissipated as the bond front advances is developed. The bonding criterion is used to examine the case of bonding bowed wafers. An analytical expression for the strain energy accumulation rate, which is the quantity that controls bonding, and the final curvature of a bonded stack is developed. It is demonstrated that the thickness of the wafers plays a large role and bonding success is independent of wafer diameter. The analytical results are verified through a finite element model and a general method for implementing the bonding criterion numerically is presented. The bonding criterion developed permits the effect of etched features to be assessed. Shallow etched patterns are shown to make bonding more difficult, while it is demonstrated that deep etched features can facilitate bonding. Model results and their process design implications are discussed in detail.

  8. Water saving in IC wafer washing process; IC wafer senjo deno sessui taisaku

    Energy Technology Data Exchange (ETDEWEB)

    Harada, H. [Mitsubishi Corp., Tokyo (Japan); Araki, M.; Nakazawa, T.

    1997-11-30

    This paper reports features of a wafer washing technology, a new IC wafer washing process, its pure water saving effect, and a `QC washing` which has pure water saving effect in the wafer washing. Wafer washing processes generally include the SC1 process (using ammonia + hydrogen peroxide aqueous solution) purposed for removing contamination due to ultrafine particles, the SC2 process (using hydrochloric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to heavy metals, the piranha washing process (using hot sulfuric acid + hydrogen peroxide aqueous solution) purposed for removing contamination due to organic matters, and the DHF (using dilute hydrofluoric acid) purposed for removing natural oxide films. Natural oxide films are now remained as surface protection films, by which surface contamination has been reduced remarkably. A high-temperature washing chemical circulating and filtering technology developed in Japan has brought about a reform in wafer washing processes having been used previously. Spin washing is used as a water saving measure, in which washing chemicals or pure water are sprayed onto one each of wafers which is spin-rotated, allowing washing and rinsing to be made with small amount of washing chemicals and pure water. The QC washing is a method to replace tank interior with pure was as quick as possible in order to increase the rinsing effect. 7 refs., 5 figs.

  9. [Effect of Scalp-acupuncture Stimulation on Neurological Function and Expression of ASIC 1 a and ASIC 2 b of Hippocampal CA 1 Region in Cerebral Ischemia Rats].

    Science.gov (United States)

    Tian, Liang; Wang, Jin-Hai; Zhao, Min; Bao, Ying-Cun; Shang, Jun-Fang; Yan, Qi; Zhang, Zhen-Chang; Du, Xiao-Zheng; Jiang, Hua; Sun, Run-Jie; Yuan, Bo; Zhang, Xing-Hua; Zhang, Ting-Zhuo; Li, Xing-Lan

    2016-10-25

    To observe the influence of scalp-acupuncture on the expression of acid-sensing ion channels (ASICs) 1 a and 2 b of hippocampal CA 1 region in cerebral ischemia (CI) rats, so as to investigate its mechanism underlying improvement of ischemic stroke. Thirty-two male SD rats were randomly allocated to normal control, model, scalp-acupuncture and Amiloride group ( n =8 in each group). The model of focal CI was established by middle cerebral artery occlusion (MCAO). Scalp acupuncture stimulation was applied to bilateral Dingnieqianxiexian (MS 6) and Dingniehouxiexian (MS 7), once daily for 7 days. Rats of the Amiloride group were fed with Amiloride solution, twice a day for 7 days, and those of the normal control and model groups were grabbled and fixed in the same way with the acupuncture and Amiloride groups. The neurological deficit score was given according to Longa's method. The expression of hippocampal ASIC 1 a and ASIC 2 b was detected by immunohistochemistry, and the Ca 2+ concentration in the hippocampal tissue assayed using flowing cytometry. After the intervention, the neurological deficit score of both the scalp-acupuncture and Amiloride groups were significantly decreased in comparison with pre-treatment ( P ASIC 1 a and ASIC 2 b in the hippocampal CA 1 region and hip-pocampal Ca 2+ concentration were significantly up-regulated in the model group compared with the normal control group ( P ASIC 1 a and ASIC 2 b expression and Ca 2+ concentration ( P >0.05). Scalp-acupuncture stimulation can improve neurological function in CI rats, which may be related to its effects in suppressing the increased expression of hippocampal ASIC 1 a and ASIC 2 b proteins and in reducing calcium overload in hip-pocampal neurocytes.

  10. Comparative study on the predictability of statistical models (RSM and ANN) on the behavior of optimized buccoadhesive wafers containing Loratadine and their in vivo assessment.

    Science.gov (United States)

    Chakraborty, Prithviraj; Parcha, Versha; Chakraborty, Debarupa D; Ghosh, Amitava

    2016-01-01

    Buccoadhesive wafer dosage form containing Loratadine is formulated utilizing Formulation by Design (FbD) approach incorporating sodium alginate and lactose monohydrate as independent variable employing solvent casting method. The wafers were statistically optimized using Response Surface Methodology (RSM) and Artificial Neural Network algorithm (ANN) for predicting physicochemical and physico-mechanical properties of the wafers as responses. Morphologically wafers were tested using SEM. Quick disintegration of the samples was examined employing Optical Contact Angle (OCA). The comparison of the predictability of RSM and ANN showed a high prognostic capacity of RSM model over ANN model in forecasting mechanical and physicochemical properties of the wafers. The in vivo assessment of the optimized buccoadhesive wafer exhibits marked increase in bioavailability justifying the administration of Loratadine through buccal route, bypassing hepatic first pass metabolism.

  11. The role of periodontal ASIC3 in orofacial pain induced by experimental tooth movement in rats.

    Science.gov (United States)

    Gao, Meiya; Long, Hu; Ma, Wenqiang; Liao, Lina; Yang, Xin; Zhou, Yang; Shan, Di; Huang, Renhuan; Jian, Fan; Wang, Yan; Lai, Wenli

    2016-12-01

    This study aimed to clarify the roles of Acid-sensing ion channel 3 (ASIC3) in orofacial pain following experimental tooth movement. Sixty male Sprague-Dawley rats were divided into the experimental group (40g, n = 30) and the sham group (0g, n = 30). Closed coil springs were ligated between maxillary incisor and molars to achieve experimental tooth movement. Rat grimace scale (RGS) scores were assessed at 0, 1, 3, 5, 7, and 14 days after the placement of the springs. ASIC3 immunostaining was performed and the expression levels of ASIC3 were measured through integrated optical density/area in Image-Pro Plus 6.0. Moreover, 18 rats were divided into APETx2 group (n = 6), amiloride group (n = 6), and vehicle group (n = 6), and RGS scores were obtained compared among them to verify the roles of ASIC3 in orofacial pain following tooth movement. ASIC3 expression levels became significantly higher in the experimental group than in sham group on 1, 3, and 5 days and became similar on 7 and 14 days. Pain levels (RGS scores) increased in both groups and were significantly higher in the experimental group on 1, 3, 5, and 7 days and were similar on 14 days. Periodontal ASIC3 expression levels were correlated with orofacial pain levels following experimental tooth movement. Periodontal administrations of ASIC3 antagonists (APETx2 and amiloride) could alleviate pain. This study needs to be better evidenced by RNA interference of ASIC3 in periodontal tissues in rats following experimental tooth movement. Moreover, we hope further studies would concentrate on the pain perception of ASIC3 knockout (ASIC3 -/- ) mice. Our results suggest that periodontal ASIC3 plays an important role in orofacial pain induced by experimental tooth movement. © The Author 2015. Published by Oxford University Press on behalf of the European Orthodontic Society. All rights reserved. For permissions, please email: journals.permissions@oup.com.

  12. Size of silicon strip sensor from 6 inch wafer (right) compared to that from a 4 inch wafer (left).

    CERN Multimedia

    Honma, Alan

    1999-01-01

    Silicon strip sensors made from 6 inch wafers will allow for much larger surface area coverage at a reduced cost per unit surface area. A prototype sensor of size 8cm x 11cm made by Hamamatsu from a 6 inch wafer is shown next to a traditional 6cm x 6cm sensor from a 4 inch wafer.

  13. In vitro and in vivo evaluation of a sublingual fentanyl wafer formulation

    Directory of Open Access Journals (Sweden)

    Lim SCB

    2013-04-01

    Full Text Available Stephen CB Lim,1,3 Michael J Paech,2 Bruce Sunderland,3 Yandi Liu3 1Pharmacy Department, Armadale Health Service, Armadale, 2School of Medicine and Pharmacology, University of Western Australia, and Department of Anaesthesia and Pain Medicine, King Edward Memorial Hospital for Women, Subiaco, 3School of Pharmacy, Curtin Health Innovation Research Institute, Curtin University, Perth, WA, Australia Background: The objective of this study was to prepare a novel fentanyl wafer formulation by a freeze-drying method, and to evaluate its in vitro and in vivo release characteristics, including its bioavailability via the sublingual route. Methods: The wafer formulation was prepared by freeze-drying an aqueous dispersion of fentanyl containing sodium carboxymethylcellulose and amylogum as matrix formers. Uniformity of weight, friability, and dissolution testing of the fentanyl wafer was achieved using standard methods, and the residual moisture content was measured. The fentanyl wafer was also examined using scanning electron microscopy and x-ray diffraction. The absolute bioavailability of the fentanyl wafer was evaluated in 11 opioid-naïve adult female patients using a randomized crossover design. Results: In vitro release showed that almost 90% of the fentanyl dissolved in one minute. In vivo, the first detectable plasma fentanyl concentration was observed after 3.5 minutes and the peak plasma concentration between 61.5 and 67 minutes. The median absolute bioavailability was 53.0%. Conclusion: These results indicate that this wafer has potential as an alternative sublingual fentanyl formulation. Keywords: absolute bioavailability, fentanyl wafer, in vitro dissolution, in vivo study, pharmacokinetics, sublingual

  14. Mechanics of wafer bonding: Effect of clamping

    Science.gov (United States)

    Turner, K. T.; Thouless, M. D.; Spearing, S. M.

    2004-01-01

    A mechanics-based model is developed to examine the effects of clamping during wafer bonding processes. The model provides closed-form expressions that relate the initial geometry and elastic properties of the wafers to the final shape of the bonded pair and the strain energy release rate at the interface for two different clamping configurations. The results demonstrate that the curvature of bonded pairs may be controlled through the use of specific clamping arrangements during the bonding process. Furthermore, it is demonstrated that the strain energy release rate depends on the clamping configuration and that using applied loads usually leads to an undesirable increase in the strain energy release rate. The results are discussed in detail and implications for process development and bonding tool design are highlighted.

  15. Optical cavity furnace for semiconductor wafer processing

    Science.gov (United States)

    Sopori, Bhushan L.

    2014-08-05

    An optical cavity furnace 10 having multiple optical energy sources 12 associated with an optical cavity 18 of the furnace. The multiple optical energy sources 12 may be lamps or other devices suitable for producing an appropriate level of optical energy. The optical cavity furnace 10 may also include one or more reflectors 14 and one or more walls 16 associated with the optical energy sources 12 such that the reflectors 14 and walls 16 define the optical cavity 18. The walls 16 may have any desired configuration or shape to enhance operation of the furnace as an optical cavity 18. The optical energy sources 12 may be positioned at any location with respect to the reflectors 14 and walls defining the optical cavity. The optical cavity furnace 10 may further include a semiconductor wafer transport system 22 for transporting one or more semiconductor wafers 20 through the optical cavity.

  16. Wafer integrated micro-scale concentrating photovoltaics

    Science.gov (United States)

    Gu, Tian; Li, Duanhui; Li, Lan; Jared, Bradley; Keeler, Gordon; Miller, Bill; Sweatt, William; Paap, Scott; Saavedra, Michael; Das, Ujjwal; Hegedus, Steve; Tauke-Pedretti, Anna; Hu, Juejun

    2017-09-01

    Recent development of a novel micro-scale PV/CPV technology is presented. The Wafer Integrated Micro-scale PV approach (WPV) seamlessly integrates multijunction micro-cells with a multi-functional silicon platform that provides optical micro-concentration, hybrid photovoltaic, and mechanical micro-assembly. The wafer-embedded micro-concentrating elements is shown to considerably improve the concentration-acceptance-angle product, potentially leading to dramatically reduced module materials and fabrication costs, sufficient angular tolerance for low-cost trackers, and an ultra-compact optical architecture, which makes the WPV module compatible with commercial flat panel infrastructures. The PV/CPV hybrid architecture further allows the collection of both direct and diffuse sunlight, thus extending the geographic and market domains for cost-effective PV system deployment. The WPV approach can potentially benefits from both the high performance of multijunction cells and the low cost of flat plate Si PV systems.

  17. Carbon dioxide capture using resin-wafer electrodeionization

    Science.gov (United States)

    Lin, YuPo J.; Snyder, Seth W.; Trachtenberg, Michael S.; Cowan, Robert M.; Datta, Saurav

    2015-09-08

    The present invention provides a resin-wafer electrodeionization (RW-EDI) apparatus including cathode and anode electrodes separated by a plurality of porous solid ion exchange resin wafers, which when in use are filled with an aqueous fluid. The apparatus includes one or more wafers comprising a basic ion exchange medium, and preferably includes one or more wafers comprising an acidic ion exchange medium. The wafers are separated from one another by ion exchange membranes. The fluid within the acidic and/or basic ion exchange wafers preferably includes, or is in contact with, a carbonic anhydrase (CA) enzyme to facilitate conversion of bicarbonate ion to carbon dioxide within the acidic medium. A pH suitable for exchange of CO.sub.2 is electrochemically maintained within the basic and acidic ion exchange wafers by applying an electric potential across the cathode and anode.

  18. Science and technology of plasma activated direct wafer bonding

    Science.gov (United States)

    Roberds, Brian Edward

    This dissertation studied the kinetics of silicon direct wafer bonding with emphasis on low temperature bonding mechanisms. The project goals were to understand the topological requirements for initial bonding, develop a tensile test to measure the bond strength as a function of time and temperature and, using the kinetic information obtained, develop lower temperature methods of bonding. A reproducible surface metrology metric for bonding was best described by power spectral density derived from atomic force microscopy measurements. From the tensile strength kinetics study it was found that low annealing temperatures could be used to obtain strong bonds, but at the expense of longer annealing times. Three models were developed to describe the kinetics. A diffusion controlled model and a reaction rate controlled model were developed for the higher temperature regimes (T > 600sp°C), and an electric field assisted oxidation model was proposed for the low temperature range. An in situ oxygen plasma treatment was used to further enhance the field-controlled mechanism which resulted in dramatic increases in the low temperature bonding kinetics. Multiple internal transmission Fourier transform infrared spectroscopy (MIT-FTIR) was used to monitor species evolution at the bonded interface and a capacitance-voltage (CV) study was undertaken to investigate charge distribution and surface states resulting from plasma activation. A short, less than a minute, plasma exposure prior to contacting the wafers was found to obtain very strong bonds for hydrophobic silicon wafers at very low temperatures (100sp°C). This novel bonding method may enable new technologies involving heterogeneous material systems or bonding partially fabricated devices to become realities.

  19. ASIC-dependent LTP at multiple glutamatergic synapses in amygdala network is required for fear memory.

    Science.gov (United States)

    Chiang, Po-Han; Chien, Ta-Chun; Chen, Chih-Cheng; Yanagawa, Yuchio; Lien, Cheng-Chang

    2015-05-19

    Genetic variants in the human ortholog of acid-sensing ion channel-1a subunit (ASIC1a) gene are associated with panic disorder and amygdala dysfunction. Both fear learning and activity-induced long-term potentiation (LTP) of cortico-basolateral amygdala (BLA) synapses are impaired in ASIC1a-null mice, suggesting a critical role of ASICs in fear memory formation. In this study, we found that ASICs were differentially expressed within the amygdala neuronal population, and the extent of LTP at various glutamatergic synapses correlated with the level of ASIC expression in postsynaptic neurons. Importantly, selective deletion of ASIC1a in GABAergic cells, including amygdala output neurons, eliminated LTP in these cells and reduced fear learning to the same extent as that found when ASIC1a was selectively abolished in BLA glutamatergic neurons. Thus, fear learning requires ASIC-dependent LTP at multiple amygdala synapses, including both cortico-BLA input synapses and intra-amygdala synapses on output neurons.

  20. Nanometer CMOS ICs from basics to ASICs

    CERN Document Server

    J M Veendrick, Harry

    2017-01-01

    This textbook provides a comprehensive, fully-updated introduction to the essentials of nanometer CMOS integrated circuits. It includes aspects of scaling to even beyond 12nm CMOS technologies and designs. It clearly describes the fundamental CMOS operating principles and presents substantial insight into the various aspects of design implementation and application. Coverage includes all associated disciplines of nanometer CMOS ICs, including physics, lithography, technology, design, memories, VLSI, power consumption, variability, reliability and signal integrity, testing, yield, failure analysis, packaging, scaling trends and road blocks. The text is based upon in-house Philips, NXP Semiconductors, Applied Materials, ASML, IMEC, ST-Ericsson, TSMC, etc., courseware, which, to date, has been completed by more than 4500 engineers working in a large variety of related disciplines: architecture, design, test, fabrication process, packaging, failure analysis and software.

  1. Wafer-shape metrics based foundry lithography

    Science.gov (United States)

    Kim, Sungtae; Liang, Frida; Mileham, Jeffrey; Tsai, Damon; Bouche, Eric; Lee, Sean; Huang, Albert; Hua, C. F.; Wei, Ming Sheng

    2017-03-01

    As device shrink, there are many difficulties with process integration and device yield. Lithography process control is expected to be a major challenge due to tighter overlay and focus control requirement. The understanding and control of stresses accumulated during device fabrication has becoming more critical at advanced technology nodes. Within-wafer stress variations cause local wafer distortions which in turn present challenges for managing overlay and depth of focus during lithography. A novel technique for measuring distortion is Coherent Gradient Sensing (CGS) interferometry, which is capable of generating a high-density distortion data set of the full wafer within a time frame suitable for a high volume manufacturing (HVM) environment. In this paper, we describe the adoption of CGS (Coherent Gradient Sensing) interferometry into high volume foundry manufacturing to overcome these challenges. Leveraging this high density 3D metrology, we characterized its In-plane distortion as well as its topography capabilities applied to the full flow of an advanced foundry manufacturing. Case studies are presented that summarize the use of CGS data to reveal correlations between in-plane distortion and overlay variation as well as between topography and device yield.

  2. Design for ASIC reliability for low-temperature applications

    Science.gov (United States)

    Chen, Yuan; Mojaradi, Mohammad; Westergard, Lynett; Billman, Curtis; Cozy, Scott; Burke, Gary; Kolawa, Elizabeth

    2005-01-01

    In this paper, we present a methodology to design for reliability for low temperature applications without requiring process improvement. The developed hot carrier aging lifetime projection model takes into account both the transistor substrate current profile and temperature profile to determine the minimum transistor size needed in order to meet reliability requirements. The methodology is applicable for automotive, military, and space applications, where there can be varying temperature ranges. A case study utilizing this methodology is given to design for reliability into a custom application-specific integrated circuit (ASIC) for a Mars exploration mission.

  3. Coarse Grain Reconfigurable ASIC through Multiplexer Based Switches

    Science.gov (United States)

    2015-09-15

    chip area (0.5 mm2), and from simulation their power consumption is negligible (0.002% from simulation, too small to measure in physical system...performing implementation that is also flexible. REFERENCES [1] I. Kuon and J. Rose, “ Measuring the gap between FPGAs and ASICs,” IEEE Trans...A 3GPP- LTE Example," Solid-State Circuits, IEEE Journal of , vol.47, no.3, pp.757,768, March 2012. [5] Agarwal, A.; Hassanieh, H.; Abari, O

  4. PICK1 regulates the trafficking of ASIC1a and acidotoxicity in a BAR domain lipid binding-dependent manner

    Directory of Open Access Journals (Sweden)

    Jin Wenying

    2010-12-01

    Full Text Available Abstract Background Acid-sensing ion channel 1a (ASIC1a is the major ASIC subunit determining acid-activated currents in brain neurons. Recent studies show that ASIC1a play critical roles in acid-induced cell toxicity. While these studies raise the importance of ASIC1a in diseases, mechanisms for ASIC1a trafficking are not well understood. Interestingly, ASIC1a interacts with PICK1 (protein interacting with C-kinase 1, an intracellular protein that regulates trafficking of several membrane proteins. However, whether PICK1 regulates ASIC1a surface expression remains unknown. Results Here, we show that PICK1 overexpression increases ASIC1a surface level. A BAR domain mutant of PICK1, which impairs its lipid binding capability, blocks this increase. Lipid binding of PICK1 is also required for PICK1-induced clustering of ASIC1a. Consistent with the effect on ASIC1a surface levels, PICK1 increases ASIC1a-mediated acidotoxicity and this effect requires both the PDZ and BAR domains of PICK1. Conclusions Taken together, our results indicate that PICK1 regulates trafficking and function of ASIC1a in a lipid binding-dependent manner.

  5. The Human Acid-Sensing Ion Channel ASIC1a: Evidence for a Homotetrameric Assembly State at the Cell Surface.

    Directory of Open Access Journals (Sweden)

    Miguel Xavier van Bemmelen

    Full Text Available The chicken acid-sensing ion channel ASIC1 has been crystallized as a homotrimer. We address here the oligomeric state of the functional ASIC1 in situ at the cell surface. The oligomeric states of functional ASIC1a and mutants with additional cysteines introduced in the extracellular pore vestibule were resolved on SDS-PAGE. The functional ASIC1 complexes were stabilized at the cell surface of Xenopus laevis oocytes or CHO cells either using the sulfhydryl crosslinker BMOE, or sodium tetrathionate (NaTT. Under these different crosslinking conditions ASIC1a migrates as four distinct oligomeric states that correspond by mass to multiples of a single ASIC1a subunit. The relative importance of each of the four ASIC1a oligomers was critically dependent on the availability of cysteines in the transmembrane domain for crosslinking, consistent with the presence of ASIC1a homo-oligomers. The expression of ASIC1a monomers, trimeric or tetrameric concatemeric cDNA constructs resulted in functional channels. The resulting ASIC1a complexes are resolved as a predominant tetramer over the other oligomeric forms, after stabilization with BMOE or NaTT and SDS-PAGE/western blot analysis. Our data identify a major ASIC1a homotetramer at the surface membrane of the cell expressing functional ASIC1a channel.

  6. Multichannel readout ASIC design flow for high energy physics and cosmic rays experiments

    International Nuclear Information System (INIS)

    Voronin, A; Malankin, E

    2016-01-01

    In the large-scale high energy physics and astrophysics experiments multi-channel readout application specific integrated circuits (ASICs) are widely used. The ASICs for such experiments are complicated systems, which usually include both analog and digital building blocks. The complexity and large number of channels in such ASICs require the proper methodological approach to their design. The paper represents the mixed-signal design flow of the ASICs for high energy physics and cosmic rays experiments. This flow was successfully embedded to the development of the read-out ASIC prototype for the muon chambers of the CBM experiment. The approach was approved in UMC CMOS MMRF 180 nm process. The design flow enable to analyse the mixed-signal system operation on the different levels: functional, behavioural, schematic and post layout including parasitic elements. The proposed design flow allows reducing the simulation period and eliminating the functionality mismatches on the very early stage of the design. (paper)

  7. Very Low-Power Consumption Analog Pulse Processing ASIC for Semiconductor Radiation Detectors

    International Nuclear Information System (INIS)

    Wessendorf, K.O.; Lund, J.C.; Brunett, B.A.; Laguna, G.R.; Clements, J.W.

    1999-01-01

    We describe a very-low power consumption circuit for processing the pulses from a semiconductor radiation detector. The circuit was designed for use with a cadmium zinc telluride (CZT) detector for unattended monitoring of stored nuclear materials. The device is intended to be battery powered and operate at low duty-cycles over a long period of time. This system will provide adequate performance for medium resolution gamma-ray pulse-height spectroscopy applications. The circuit incorporates the functions of a charge sensitive preamplifier, shaping amplifier, and peak sample and hold circuit. An application specific integrated circuit (ASIC) version of the design has been designed, built and tested. With the exception of the input field effect transistor (FET), the circuit is constructed using bipolar components. In this paper the design philosophy and measured performance characteristics of the circuit are described

  8. The TDCPix ASIC: Tracking for the NA62 GigaTracker

    CERN Document Server

    Noy, Matthew; Bonacini, Sandro; Kaplon, Jan; Kluge, Alexander; Morel, Michel; Perktold, Lukas; Poltorak, Karolina

    2014-01-01

    The TDCPix is a hybrid pixel detector readout ASIC designed for the NA62 GigaTracker detec- tor. The asynchronously operating pixel array consists of 1800 pixels, each 300x300 m m 2 . The requirements are a single-hit timing resolution better than 200 ps RMS and a read-out efficiency of 99% or better in the presence of a beam rate between 800 MHz and 1 GHz . The discrimina- tor time walk effect is compensated by time-over-threshold discriminators connected to an array of 360 dual TDC channels. The TDCpix processes up to 210 Mhits = s and provides the hit data without the need of a trigger in a continuous data stream via four 3.2 Gb = s serialisers. Under test since January 2014, the TDCPix chip is fully functional and shows excellent performance.

  9. Palladium-based on-wafer electroluminescence studies of GaN-based LED structures

    Energy Technology Data Exchange (ETDEWEB)

    Salcianu, C.O.; Thrush, E.J.; Humphreys, C.J. [Department of Materials Science and Metallurgy, University of Cambridge, Pembroke Street, Cambridge CB2 3QZ (United Kingdom); Plumb, R.G. [Centre for Photonic Systems, Department of Engineering, University of Cambridge, Cambridge CB3 0FD (United Kingdom); Boyd, A.R.; Rockenfeller, O.; Schmitz, D.; Heuken, M. [AIXTRON AG, Kackertstr. 15-17, 52072 Aachen (Germany)

    2008-07-01

    Electroluminescence (EL) testing of Light Emitting Diode (LED) structures is usually done at the chip level. Assessing the optical and electrical properties of LED structures at the wafer scale prior to their processing would improve the cost effectiveness of producing LED-lamps. A non-destructive method for studying the luminescence properties of the structure at the wafer-scale is photoluminescence (PL). However, the relationship between the on-wafer PL data and the final device EL can be less than straightforward (Y. H Aliyu et al., Meas. Sci. Technol. 8, 437 (1997)) as the two techniques employ different carrier injection mechanisms. This paper provides an overview of some different techniques in which palladium is used as a contact in order to obtain on-wafer electroluminescence information which could be used to screen wafers prior to processing into final devices. Quick mapping of the electrical and optical characteristics was performed using either palladium needle electrodes directly, or using the latter in conjunction with evaporated palladium contacts to inject both electrons and holes into the active region via the p-type capping layer of the structure. For comparison, indium was also used to make contact to the n-layer so that electrons could be directly injected into that layer. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  10. 120 mm Single-crystalline perovskite and wafers: towards viable applications

    Institute of Scientific and Technical Information of China (English)

    Yucheng Liu; Bo Wang; Qingbo Wei; Fengwei Xiao; Haibo Fan; Hao Deng; Liangping Deng; Shengzhong (Frank) Liu; Xiaodong Ren; Jing Zhang; Zhou Yang; Dong Yang; Fengyang Yu; Jiankun Sun; Changming Zhao; Zhun Yao

    2017-01-01

    As the large single-crystalline silicon wafers have revolutionized many industries including electronics and solar cells,it is envisioned that the availability of large single-crystalline perovskite crystals and wafers will revolutionize its broad applications in photovoltaics,optoelectronics,lasers,photodetectors,light emitting diodes (LEDs),etc.Here we report a method to grow large single-crystalline perovskites including single-halide crystals:CH3NH3PbX3 (X=Ⅰ,Br,Cl),and dual-halide ones:CH3NH3Pb(ClxBr1-x)3 and CH3NH3Pb(BrxI1-x)3,with the largest crystal being 120 mm in length.Meanwhile,we have advanced a process to slice the large perovskite crystals into thin wafers.It is found that the wafers exhibit remarkable features:(1) its trap-state density is a million times smaller than that in the microcrystalline perovskite thin films (MPTF);(2) its carrier mobility is 410 times higher than its most popular organic counterpart P3HT;(3) its optical absorption is expanded to as high as 910 nm comparing to 797 nm for the MPTF;(4) while MPTF decomposes at 150 ℃,the wafer is stable at high temperature up to 270 ℃;(5) when exposed to high humidity (75% RH),MPTF decomposes in 5 h while the wafer shows no change for overnight;(6) its photocurrent response is 250 times higher than its MPTF counterpart.A few electronic devices have been fabricated using the crystalline wafers.Among them,the Hall test gives low carrier concentration with high mobility.The trap-state density is measured much lower than common semiconductors.Moreover,the large SC-wafer is found particularly useful for mass production of integrated circuits.By adjusting the halide composition,both the optical absorption and the light emission can be fine-tuned across the entire visible spectrum from 400 nm to 800 nm.It is envisioned that a range of visible lasers and LEDs may be developed using the dual-halide perovskites.With fewer trap states,high mobility,broader absorption,and humidity resistance,it is

  11. Methods for characterization of wafer-level encapsulation applied on silicon to LTCC anodic bonding

    International Nuclear Information System (INIS)

    Khan, M F; Ghavanini, F A; Enoksson, P; Haasl, S; Löfgren, L; Persson, K; Rusu, C; Schjølberg-Henriksen, K

    2010-01-01

    This paper presents initial results on generic characterization methods for wafer-level encapsulation. The methods, developed specifically to evaluate anodic bonding of low-temperature cofired ceramics (LTCC) to Si, are generally applicable to wafer-level encapsulation. Different microelectromechanical system (MEMS) structures positioned over the whole wafer provide local information about the bond quality. The structures include (i) resonating cantilevers as pressure sensors for bond hermeticity, (ii) resonating bridges as stress sensors for measuring the stress induced by the bonding and (iii) frames/mesas for pull tests. These MEMS structures have been designed, fabricated and characterized indicating that local information can easily be obtained. Buried electrodes to enable localized bonding have been implemented and their effectiveness is indicated from first results of the novel Si to LTCC anodic bonding.

  12. Cost-Efficient Wafer-Level Capping for MEMS and Imaging Sensors by Adhesive Wafer Bonding

    Directory of Open Access Journals (Sweden)

    Simon J. Bleiker

    2016-10-01

    Full Text Available Device encapsulation and packaging often constitutes a substantial part of the fabrication cost of micro electro-mechanical systems (MEMS transducers and imaging sensor devices. In this paper, we propose a simple and cost-effective wafer-level capping method that utilizes a limited number of highly standardized process steps as well as low-cost materials. The proposed capping process is based on low-temperature adhesive wafer bonding, which ensures full complementary metal-oxide-semiconductor (CMOS compatibility. All necessary fabrication steps for the wafer bonding, such as cavity formation and deposition of the adhesive, are performed on the capping substrate. The polymer adhesive is deposited by spray-coating on the capping wafer containing the cavities. Thus, no lithographic patterning of the polymer adhesive is needed, and material waste is minimized. Furthermore, this process does not require any additional fabrication steps on the device wafer, which lowers the process complexity and fabrication costs. We demonstrate the proposed capping method by packaging two different MEMS devices. The two MEMS devices include a vibration sensor and an acceleration switch, which employ two different electrical interconnection schemes. The experimental results show wafer-level capping with excellent bond quality due to the re-flow behavior of the polymer adhesive. No impediment to the functionality of the MEMS devices was observed, which indicates that the encapsulation does not introduce significant tensile nor compressive stresses. Thus, we present a highly versatile, robust, and cost-efficient capping method for components such as MEMS and imaging sensors.

  13. First thin AC-coupled silicon strip sensors on 8-inch wafers

    Energy Technology Data Exchange (ETDEWEB)

    Bergauer, T., E-mail: thomas.bergauer@oeaw.ac.at [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Dragicevic, M.; König, A. [Institute of High Energy Physics of the Austrian Academy of Sciences, Nikolsdorfer Gasse 18, 1050 Wien (Vienna) (Austria); Hacker, J.; Bartl, U. [Infineon Technologies Austria AG, Siemensstrasse 2, 9500 Villach (Austria)

    2016-09-11

    The Institute of High Energy Physics (HEPHY) in Vienna and the semiconductor manufacturer Infineon Technologies Austria AG developed a production process for planar AC-coupled silicon strip sensors manufactured on 200 μm thick 8-inch p-type wafers. In late 2015, the first wafers were delivered featuring the world's largest AC-coupled silicon strip sensors. Detailed electrical measurements were carried out at HEPHY, where single strip and global parameters were measured. Mechanical studies were conducted and the long-term behavior was investigated using a climate chamber. Furthermore, the electrical properties of various test structures were investigated to validate the quality of the manufacturing process.

  14. A CMOS ASIC Design for SiPM Arrays.

    Science.gov (United States)

    Dey, Samrat; Banks, Lushon; Chen, Shaw-Pin; Xu, Wenbin; Lewellen, Thomas K; Miyaoka, Robert S; Rudell, Jacques C

    2011-12-01

    Our lab has previously reported on novel board-level readout electronics for an 8×8 silicon photomultiplier (SiPM) array featuring row/column summation technique to reduce the hardware requirements for signal processing. We are taking the next step by implementing a monolithic CMOS chip which is based on the row-column architecture. In addition, this paper explores the option of using diagonal summation as well as calibration to compensate for temperature and process variations. Further description of a timing pickoff signal which aligns all of the positioning (spatial channels) pulses in the array is described. The ASIC design is targeted to be scalable with the detector size and flexible to accommodate detectors from different vendors. This paper focuses on circuit implementation issues associated with the design of the ASIC to interface our Phase II MiCES FPGA board with a SiPM array. Moreover, a discussion is provided for strategies to eventually integrate all the analog and mixed-signal electronics with the SiPM, on either a single-silicon substrate or multi-chip module (MCM).

  15. Exploring Many-Core Design Templates for FPGAs and ASICs

    Directory of Open Access Journals (Sweden)

    Ilia Lebedev

    2012-01-01

    Full Text Available We present a highly productive approach to hardware design based on a many-core microarchitectural template used to implement compute-bound applications expressed in a high-level data-parallel language such as OpenCL. The template is customized on a per-application basis via a range of high-level parameters such as the interconnect topology or processing element architecture. The key benefits of this approach are that it (i allows programmers to express parallelism through an API defined in a high-level programming language, (ii supports coarse-grained multithreading and fine-grained threading while permitting bit-level resource control, and (iii reduces the effort required to repurpose the system for different algorithms or different applications. We compare template-driven design to both full-custom and programmable approaches by studying implementations of a compute-bound data-parallel Bayesian graph inference algorithm across several candidate platforms. Specifically, we examine a range of template-based implementations on both FPGA and ASIC platforms and compare each against full custom designs. Throughout this study, we use a general-purpose graphics processing unit (GPGPU implementation as a performance and area baseline. We show that our approach, similar in productivity to programmable approaches such as GPGPU applications, yields implementations with performance approaching that of full-custom designs on both FPGA and ASIC platforms.

  16. Highly Integrated MEMS-ASIC Sensing System for Intracorporeal Physiological Condition Monitoring.

    Science.gov (United States)

    Xue, Ning; Wang, Chao; Liu, Cunxiu; Sun, Jianhai

    2018-01-02

    In this paper, a highly monolithic-integrated multi-modality sensor is proposed for intracorporeal monitoring. The single-chip sensor consists of a solid-state based temperature sensor, a capacitive based pressure sensor, and an electrochemical oxygen sensor with their respective interface application-specific integrated circuits (ASICs). The solid-state-based temperature sensor and the interface ASICs were first designed and fabricated based on a 0.18-μm 1.8-V CMOS (complementary metal-oxide-semiconductor) process. The oxygen sensor and pressure sensor were fabricated by the standard CMOS process and subsequent CMOS-compatible MEMS (micro-electromechanical systems) post-processing. The multi-sensor single chip was completely sealed by the nafion, parylene, and PDMS (polydimethylsiloxane) layers for biocompatibility study. The size of the compact sensor chip is only 3.65 mm × 1.65 mm × 0.72 mm. The functionality, stability, and sensitivity of the multi-functional sensor was tested ex vivo. Cytotoxicity assessment was performed to verify that the bio-compatibility of the device is conforming to the ISO 10993-5:2009 standards. The measured sensitivities of the sensors for the temperature, pressure, and oxygen concentration are 10.2 mV/°C, 5.58 mV/kPa, and 20 mV·L/mg, respectively. The measurement results show that the proposed multi-sensor single chip is suitable to sense the temperature, pressure, and oxygen concentration of human tissues for intracorporeal physiological condition monitoring.

  17. NECTAr0, a new high speed digitizer ASIC for the Cherenkov telescope array

    International Nuclear Information System (INIS)

    Delagnes, E.; Glicenstein, J.F.; Guilloux, F.; Bolmont, J.; Corona, P.; Naumann, C.L.; Nayman, P.; Tavemet, J.P.; Toussenel, F.; Vincent, P.; Dzahini, D.; Rarbi, F.; Feinstein, F.; Vorobiov, S.; Gascon, D.; Sanuy, A.

    2011-01-01

    H.E.S.S. and MAGIC experiments have demonstrated the high level of maturity of Imaging Atmospheric Cherenkov Telescopes (IACTs) dedicated to very-high-energy gamma ray astronomy domain. The astro-particle physics community is preparing the next generation of instruments, with sensitivity improved by an order of magnitude in the 10 GeV to 100 TeV range. To reach this goal, the Cherenkov Telescope Array (CTA) will consist in an array of 50-100 dishes of various sizes and various spacing, each equipped with a camera, made of few thousands fast photo-detectors and its associated front-end electronics. The total number of electronics channels will be larger than 100,000 to be compared to the total of 6,000 channels of the 5-telescopes H.E.S.S.-I H.E.S.S.-II array. To decrease the overall CTA cost, a consequent effort should be done to lower the cost of the electronics while keeping performance at least as good as the one demonstrated on the current experiments and simplifying its maintenance. This will be allowed by mass production, use of standardized modules and integration of front-end functions in ASICs. The 3-year NECTAr program started in 2009 addresses these two topics. Its final aim is to develop and test a demonstrator module of a generic CTA camera. The paper is mainly focused on one of the main components of this module, the NECTAr ASIC which samples the photo-detector signal in a circular analog memory at several GSPS and digitizes it over 12 bits after having received an external trigger. (authors)

  18. Accurate characterization of wafer bond toughness with the double cantilever specimen

    Science.gov (United States)

    Turner, Kevin T.; Spearing, S. Mark

    2008-01-01

    The displacement loaded double cantilever test, also referred to as the "Maszara test" and the "crack opening method" by the wafer bonding community, is a common technique used to evaluate the interface toughness or surface energy of direct wafer bonds. While the specimen is widely used, there has been a persistent question as to the accuracy of the method since the actual specimen geometry differs from the ideal beam geometry assumed in the expression used for data reduction. The effect of conducting the test on whole wafer pairs, in which the arms of cantilevers are wide plates rather than slender beams, is examined in this work using finite element analysis. A model is developed to predict the equilibrium shape of the crack front and to develop a corrected expression for calculating interface toughness from crack length measurements obtained in tests conducted on whole wafer pairs. The finite element model, which is validated through comparison to experiments, demonstrates that using the traditional beam theory-based expressions for data reduction can lead to errors of up to 25%.

  19. A facility for plastic deformation of germanium single-crystal wafers

    DEFF Research Database (Denmark)

    Lebech, B.; Theodor, K.; Breiting, B.

    1998-01-01

    . All movements and temperature changes are done by a robot via a PLC-control system. Two nine-crystal focusing monochromators (54 x 116 and 70 x 116 mm(2)) made from 100 wafers with average mosaicity similar to 13' have been constructed. Summaries of the test results are presented. (C) 1998 Elsevier...

  20. Characterization of silicon-on-insulator wafers

    Science.gov (United States)

    Park, Ki Hoon

    The silicon-on-insulator (SOI) is attracting more interest as it is being used for an advanced complementary-metal-oxide-semiconductor (CMOS) and a base substrate for novel devices to overcome present obstacles in bulk Si scaling. Furthermore, SOI fabrication technology has improved greatly in recent years and industries produce high quality wafers with high yield. This dissertation investigated SOI material properties with simple, yet accurate methods. The electrical properties of as-grown wafers such as electron and hole mobilities, buried oxide (BOX) charges, interface trap densities, and carrier lifetimes were mainly studied. For this, various electrical measurement techniques were utilized such as pseudo-metal-oxide-semiconductor field-effect-transistor (PseudoMOSFET) static current-voltage (I-V) and transient drain current (I-t), Hall effect, and MOS capacitance-voltage/capacitance-time (C-V/C-t). The electrical characterization, however, mainly depends on the pseudo-MOSFET method, which takes advantage of the intrinsic SOI structure. From the static current-voltage and pulsed measurement, carrier mobilities, lifetimes and interface trap densities were extracted. During the course of this study, a pseudo-MOSFET drain current hysteresis regarding different gate voltage sweeping directions was discovered and the cause was revealed through systematic experiments and simulations. In addition to characterization of normal SOI, strain relaxation of strained silicon-on-insulator (sSOI) was also measured. As sSOI takes advantage of wafer bonding in its fabrication process, the tenacity of bonding between the sSOI and the BOX layer was investigated by means of thermal treatment and high dose energetic gamma-ray irradiation. It was found that the strain did not relax with processes more severe than standard CMOS processes, such as anneals at temperature as high as 1350 degree Celsius.

  1. Wafer-Scale Integration of Systolic Arrays,

    Science.gov (United States)

    1985-10-01

    hus wtha rbaiith hig robabili, e aubrbe orutysta mostck b(e)adstotoefwsi the cenofther cnnel thati are connted to (g.The kery ato the alevel of t...problems considered heretofore in this paper also have an interpretation in a purely graph theoretic model. Suppose we are given a two-dimensional...graphs," Magyar 7Td. Akad. Math . Kut. Int. Kozl, Vol. 5, 1960, pp. 17-61. [6] D. Fussell and P. Varman, "Fault-tolerant wafer-scale architectures for

  2. Wafer-scale pixelated detector system

    Science.gov (United States)

    Fahim, Farah; Deptuch, Grzegorz; Zimmerman, Tom

    2017-10-17

    A large area, gapless, detection system comprises at least one sensor; an interposer operably connected to the at least one sensor; and at least one application specific integrated circuit operably connected to the sensor via the interposer wherein the detection system provides high dynamic range while maintaining small pixel area and low power dissipation. Thereby the invention provides methods and systems for a wafer-scale gapless and seamless detector systems with small pixels, which have both high dynamic range and low power dissipation.

  3. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    International Nuclear Information System (INIS)

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Buchholz, P; Wiese, A; Ziolkowskic, M

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad with 24 GeV/c protons. The observed modest degradation is acceptable and the single event upset rate is negligible.

  4. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    CERN Document Server

    Gan, K K; Kagan, H P; Kass, R D; Moore, J R; Smith, D S; Wiese, A; Ziolkowskic, M; 10.1088/1748-0221/5/12/C12006

    2010-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for the VCSEL and a receiver/decoder to decode the signal received at the PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder can properly decode the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ~ 5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value. The ASICs were irradiated to a dose of 46 Mrad ...

  5. Wafer-Level Membrane-Transfer Process for Fabricating MEMS

    Science.gov (United States)

    Yang, Eui-Hyeok; Wiberg, Dean

    2003-01-01

    A process for transferring an entire wafer-level micromachined silicon structure for mating with and bonding to another such structure has been devised. This process is intended especially for use in wafer-level integration of microelectromechanical systems (MEMS) that have been fabricated on dissimilar substrates. Unlike in some older membrane-transfer processes, there is no use of wax or epoxy during transfer. In this process, the substrate of a wafer-level structure to be transferred serves as a carrier, and is etched away once the transfer has been completed. Another important feature of this process is that two electrodes constitutes an electrostatic actuator array. An SOI wafer and a silicon wafer (see Figure 1) are used as the carrier and electrode wafers, respectively. After oxidation, both wafers are patterned and etched to define a corrugation profile and electrode array, respectively. The polysilicon layer is deposited on the SOI wafer. The carrier wafer is bonded to the electrode wafer by using evaporated indium bumps. The piston pressure of 4 kPa is applied at 156 C in a vacuum chamber to provide hermetic sealing. The substrate of the SOI wafer is etched in a 25 weight percent TMAH bath at 80 C. The exposed buried oxide is then removed by using 49 percent HF droplets after an oxygen plasma ashing. The SOI top silicon layer is etched away by using an SF6 plasma to define the corrugation profile, followed by the HF droplet etching of the remaining oxide. The SF6 plasma with a shadow mask selectively etches the polysilicon membrane, if the transferred membrane structure needs to be patterned. Electrostatic actuators with various electrode gaps have been fabricated by this transfer technique. The gap between the transferred membrane and electrode substrate is very uniform ( 0.1 m across a wafer diameter of 100 mm, provided by optimizing the bonding control). Figure 2 depicts the finished product.

  6. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'Brien, Deirdre

    2012-02-01

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  7. Candida parapsilosis meningitis associated with Gliadel (BCNU) wafer implants.

    LENUS (Irish Health Repository)

    O'brien, Deirdre

    2010-12-15

    A 58-year old male presented with meningitis associated with subgaleal and subdural collections 6 weeks following a temporal craniotomy for resection of recurrent glioblastoma multiforme and Gliadel wafer implantation. Candida parapsilosis was cultured from cerebrospinal fluid (CSF) and Gliadel wafers removed during surgical debridement. He was successfully treated with liposomal amphotericin B. To our knowledge, this is the first reported case of Candida parapsilosis meningitis secondary to Gliadel wafer placement.

  8. High frequency guided wave propagation in monocrystalline silicon wafers

    OpenAIRE

    Pizzolato, M.; Masserey, B.; Robyr, J. L.; Fromme, P.

    2017-01-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full...

  9. Subtype-specific Modulation of Acid-sensing Ion Channel (ASIC) Function by 2-Guanidine-4-methylquinazoline*

    Science.gov (United States)

    Alijevic, Omar; Kellenberger, Stephan

    2012-01-01

    Acid-sensing ion channels (ASICs) are neuronal Na+-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mm, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH. PMID:22948146

  10. Subtype-specific modulation of acid-sensing ion channel (ASIC) function by 2-guanidine-4-methylquinazoline.

    Science.gov (United States)

    Alijevic, Omar; Kellenberger, Stephan

    2012-10-19

    Acid-sensing ion channels (ASICs) are neuronal Na(+)-selective channels that are transiently activated by extracellular acidification. ASICs are involved in fear and anxiety, learning, neurodegeneration after ischemic stroke, and pain sensation. The small molecule 2-guanidine-4-methylquinazoline (GMQ) was recently shown to open ASIC3 at physiological pH. We have investigated the mechanisms underlying this effect and the possibility that GMQ may alter the function of other ASICs besides ASIC3. GMQ shifts the pH dependence of activation to more acidic pH in ASIC1a and ASIC1b, whereas in ASIC3 this shift goes in the opposite direction and is accompanied by a decrease in its steepness. GMQ also induces an acidic shift of the pH dependence of inactivation of ASIC1a, -1b, -2a, and -3. As a consequence, the activation and inactivation curves of ASIC3 but not other ASICs overlap in the presence of GMQ at pH 7.4, thereby creating a window current. At concentrations >1 mM, GMQ decreases maximal peak currents by reducing the unitary current amplitude. Mutation of residue Glu-79 in the palm domain of ASIC3, previously shown to be critical for channel opening by GMQ, disrupted the GMQ effects on inactivation but not activation. This suggests that this residue is involved in the consequences of GMQ binding rather than in the binding interaction itself. This study describes the mechanisms underlying the effects of a novel class of ligands that modulate the function of all ASICs as well as activate ASIC3 at physiological pH.

  11. Aerial image measurement technique for automated reticle defect disposition (ARDD) in wafer fabs

    Science.gov (United States)

    Zibold, Axel M.; Schmid, Rainer M.; Stegemann, B.; Scheruebl, Thomas; Harnisch, Wolfgang; Kobiyama, Yuji

    2004-08-01

    The Aerial Image Measurement System (AIMS)* for 193 nm lithography emulation has been brought into operation successfully worldwide. A second generation system comprising 193 nm AIMS capability, mini-environment and SMIF, the AIMS fab 193 plus is currently introduced into the market. By adjustment of numerical aperture (NA), illumination type and partial illumination coherence to match the conditions in 193 nm steppers or scanners, it can emulate the exposure tool for any type of reticles like binary, OPC and PSM down to the 65 nm node. The system allows a rapid prediction of wafer printability of defects or defect repairs, and critical features, like dense patterns or contacts on the masks without the need to perform expensive image qualification consisting of test wafer exposures followed by SEM measurements. Therefore, AIMS is a mask quality verification standard for high-end photo masks and established in mask shops worldwide. The progress on the AIMS technology described in this paper will highlight that besides mask shops there will be a very beneficial use of the AIMS in the wafer fab and we propose an Automated Reticle Defect Disposition (ARDD) process. With smaller nodes, where design rules are 65 nm or less, it is expected that smaller defects on reticles will occur in increasing numbers in the wafer fab. These smaller mask defects will matter more and more and become a serious yield limiting factor. With increasing mask prices and increasing number of defects and severability on reticles it will become cost beneficial to perform defect disposition on the reticles in wafer production. Currently ongoing studies demonstrate AIMS benefits for wafer fab applications. An outlook will be given for extension of 193 nm aerial imaging down to the 45 nm node based on emulation of immersion scanners.

  12. Study of preamplifier, shaper and peak detector in readout ASIC for particle detector

    International Nuclear Information System (INIS)

    Wang Ke; Zhang Shengjun; Fan Lei; Li Xian

    2014-01-01

    Recently, kinds of particle detectors have used Application Specific Integrated Circuits (ASIC) in their electronics readout system and ASICs have been designed in China now. This project designed a multi-channel readout ASIC for general detector. The chip has Preamplifier, Shaper and Peak Detector embedded for easy readout. For each channel, signal which is preprocessed by a low-noise preamplifier is sent to the shaper to form a quasi-Gaussian pulse and keep its peak for readout. This chip and modules of individual Preamplifier, Shaper and Peak Detector have been manufactured, results will be reported in time. (authors)

  13. The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

    International Nuclear Information System (INIS)

    Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

    2002-01-01

    The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

  14. Development and characterisation of a front-end ASIC for macro array of photo-detectors of large dimensions

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.

    2010-10-01

    The coverage of large areas of photo-detection is a crucial element of experiments studying high energy atmospheric cosmic showers and neutrinos from different sources. The objective of this project is to realize big detectors using thousands of photomultipliers (PMT). The project proposes to segment the large surface of photo-detection into macro pixels consisting of an array of 16 PMT of 12 inches (2*2 m 2 ), connected to an autonomous front-end electronics which works in without-trigger data acquisition mode placed near the array. This is possible thanks to the microelectronics progress that allows to integrate the readout and the signal processing, of all the multipliers, in the same circuit (ASIC) named PARISROC (Photomultiplier Array Integrated ins SiGe Read Out Chip). The ASIC must only send out the digital data by network to the surface central data storage. The PARISROC chip made in AM's Silicon Germanium (SiGe) 0.35 μm technology, integrates 16 independent channels for each PMT of the array, providing charge and time measurements. The first prototype of PARISROC chip has a total surface of 19 mm 2 . The ASIC measurements have led to the realization of a second prototype. Important measurements were performed in terms of noise, dynamic range, readout frequency (from 10 MHz to 40 MHz), time measurements (TDC improvements) and charge measurements (Slow shaper improvements). This new prototype of PARISROC-2 has been tested and the characterisation has shown a good overall behavior and the verification of the improvements. (author)

  15. Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

    CERN Document Server

    Gkountoumis, Panagiotis; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the front-end readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10/100/1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micromegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies wi...

  16. Prototype board development for the validation of the VMM ASICs for the New Small Wheel ATLAS upgrade project

    CERN Document Server

    Gkountoumis, Panagiotis; The ATLAS collaboration

    2018-01-01

    The VMM is a custom Application Specific Integrated Circuit (ASIC) which was designed to be used in the frontend readout electronics of both micromegas (MM) and small Thin Gap Chambers (sTGC) detectors of the New Small Wheel (NSW) Phase-I upgrade project of the ATLAS experiment. A new version of the VMM was recently fabricated and for that reason various prototype boards, the micromegas Front-End (MMFE1) and the General Purpose VMM (GPVMM), have been fabricated and extensively tested in order to validate the functionality of the ASIC. These boards use commercial Field Programmable Gate Arrays (FPGAs) for direct communication with computers which is achieved through 10=100=1000 Mbps Ethernet and UDP/IP protocols. The low noise performance of these boards gave the opportunity to be used in various test beams with micormegas detectors for validating the VMM and for performance studies of the sTGC detectors. A detailed description of the boards along with the results of the test beam and the detector studies will...

  17. Macro Pixel ASIC (MPA): The readout ASIC for the pixel-strip (PS) module of the CMS outer tracker at HL-LHC

    CERN Document Server

    Ceresa, Davide; Kloukinas, Konstantinos; Jan Kaplon; Bialas, Wojciech; Re, Valerio; Traversi, Gianluca; Gaioni, Luigi; Ratti, Lodovico

    2014-01-01

    The CMS tracker at HL-LHC is required to provide prompt information on particles with high transverse momentum to the central Level\\,1 trigger. For this purpose, the innermost part of the outer tracker is based on a combination of a pixelated sensor with a short strip sensor, the so-called Pixel-Strip module (PS). The readout of these sensors is carried out by distinct ASICs, the Strip Sensor ASIC (SSA), for the strip layer, and the Macro Pixel ASIC (MPA) for the pixel layer. The processing of the data directly on the front-end module represents a design challenge due to the large data volume (30720\\,pixels and 1920\\,strips per module) and the limited power budget. This is the reason why several studies have been carried out to find the best compromise between ASICs performance and power consumption. This paper describes the current status of the MPA ASIC development where the logic for generating prompt information on particles with high transverse momentum is implemented. An overview of the readout method i...

  18. Wafer edge overlay control solution for N7 and beyond

    Science.gov (United States)

    van Haren, Richard; Calado, Victor; van Dijk, Leon; Hermans, Jan; Kumar, Kaushik; Yamashita, Fumiko

    2018-03-01

    Historically, the on-product overlay performance close to the wafer edge is lagging with respect to the inner part of the wafer. The reason for this is that wafer processing is less controlled close to the wafer edge as opposed to the rest of the wafer. It is generally accepted that Chemical Vapor Deposition (CVD) of stressed layers that cause wafer warp, wafer table contamination, Chemical Mechanical Polishing (CMP), and Reactive Ion Etch (RIE) may deteriorate the overlay performance and/or registration close to the wafer edge. For the N7 technology node and beyond, it is anticipated that the tight on-product overlay specification is required across the full wafer which includes the edge region. In this work, we highlight one contributor that may negatively impact the on-product overlay performance, namely the etch step. The focus will be mainly on the wafer edge region but the remaining part of the wafer is considered as well. Three use-cases are examined: multiple Litho-Etch steps (LEn), contact hole layer etch, and the copper dual damascene etch. We characterize the etch contribution by considering the overlay measurement after resist development inspect (ADI) and after etch inspect (AEI). We show that the Yieldstar diffraction based overlay (μDBO) measurements can be utilized to characterize the etch contribution to the overlay budget. The effects of target asymmetry as well as overlay shifts are considered and compared with SEM measurements. Based on the results above, we propose a control solution aiming to reduce or even eliminate the delta between ADI and AEI. By doing so, target/mark to device offsets due to etch might be avoided.

  19. Acid-sensing ion channel (ASIC) structure and function: Insights from spider, snake and sea anemone venoms.

    Science.gov (United States)

    Cristofori-Armstrong, Ben; Rash, Lachlan D

    2017-12-01

    Acid-sensing ion channels (ASICs) are proton-activated cation channels that are expressed in a variety of neuronal and non-neuronal tissues. As proton-gated channels, they have been implicated in many pathophysiological conditions where pH is perturbed. Venom derived compounds represent the most potent and selective modulators of ASICs described to date, and thus have been invaluable as pharmacological tools to study ASIC structure, function, and biological roles. There are now ten ASIC modulators described from animal venoms, with those from snakes and spiders favouring ASIC1, while the sea anemones preferentially target ASIC3. Some modulators, such as the prototypical ASIC1 modulator PcTx1 have been studied in great detail, while some of the newer members of the club remain largely unstudied. Here we review the current state of knowledge on venom derived ASIC modulators, with a particular focus on their molecular interaction with ASICs, what they have taught us about channel structure, and what they might still reveal about ASIC function and pathophysiological roles. This article is part of the Special Issue entitled 'Venom-derived Peptides as Pharmacological Tools.' Copyright © 2017 Elsevier Ltd. All rights reserved.

  20. An ASIC implementation of digital front-end electronics for a high resolution PET scanner

    International Nuclear Information System (INIS)

    Newport, D.F.; Young, J.W.

    1993-01-01

    AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

  1. Low power frontend ASIC (Anusuchak) for dosimeter using Si-PIN detector

    International Nuclear Information System (INIS)

    Darad, A.; Chandratre, V.B.

    2010-01-01

    A low power ASIC (Anusuchak) for silicon PIN detector signal processing channel designed for pocket dosimeter in 0.35 μm CMOS process. The ASIC contains two channels one for Beta particle and other for Gamma ray. The channel is a CSA integrated with a shaper, gain stage and comparator with total power consumption of 4.6 mW. The ASIC has gain of 12 mV/fC and can be raised to 29 mV/fC without degrading the noise, power or linearity specification of the channel. The channel has a peaking time of 1.2 μs with baseline recovery within 5.3 μs and noise figure of 420 e- at 0 pF. The noise slope is 17 e-/pF. The ASIC is designed for single supply of 3.3 V for which battery is available. (author)

  2. Wide Temperature Rad-Hard ASIC for Process Control of a Fuel Cell System, Phase II

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group developed a top-level design of a rad-hard application-specific integrated circuit (ASIC) for spacecraft power management that is functional over a...

  3. Direct Electroplating on Highly Doped Patterned Silicon Wafers

    NARCIS (Netherlands)

    Vargas Llona, Laura Dolores; Jansen, Henricus V.; Elwenspoek, Michael Curt

    Nickel thin films have been electrodeposited directly on highly doped silicon wafers after removal of the native oxide layer. These substrates conduct sufficiently well to allow deposition using a periferical electrical contact on the wafer. Films 2 μm thick were deposited using a nickel sulfamate

  4. Low-cost silicon wafer dicing using a craft cutter

    KAUST Repository

    Fan, Yiqiang; Carreno, Armando Arpys Arevalo; Li, Huawei; Foulds, Ian G.

    2014-01-01

    feature of 3 mm by 3 mm. We performed this scribing process on the top polished surface of a silicon wafer; we also created a scribing method for the back-unpolished surface in order to protect the structures on the wafer during scribing. Compared

  5. E-beam direct write versus reticle/stepper technology for ASICS in small volume production

    International Nuclear Information System (INIS)

    Wheeler, M.J.

    1987-01-01

    The pros and cons of using e-beam direct writing or reticles plus optical/UV steppers in fast prototyping and the small volume production of ASICs are discussed. The main conclusion is that fast prototyping is best achieved by e-beam direct write whereas small volume production of ASICs is best done via reticles and optical/UV stepping provided that the reticles are made in-house rather than by commercial maskhouses

  6. Semiconductor industry wafer fab exhaust management

    CERN Document Server

    Sherer, Michael J

    2005-01-01

    Given the myriad exhaust compounds and the corresponding problems that they can pose in an exhaust management system, the proper choice of such systems is a complex task. Presenting the fundamentals, technical details, and general solutions to real-world problems, Semiconductor Industry: Wafer Fab Exhaust Management offers practical guidance on selecting an appropriate system for a given application. Using examples that provide a clear understanding of the concepts discussed, Sherer covers facility layout, support facilities operations, and semiconductor process equipment, followed by exhaust types and challenges. He reviews exhaust point-of-use devices and exhaust line requirements needed between process equipment and the centralized exhaust system. The book includes information on wet scrubbers for a centralized acid exhaust system and a centralized ammonia exhaust system and on centralized equipment to control volatile organic compounds. It concludes with a chapter devoted to emergency releases and a separ...

  7. Voltage-assisted polymer wafer bonding

    International Nuclear Information System (INIS)

    Varsanik, J S; Bernstein, J J

    2012-01-01

    Polymer wafer bonding is a widely used process for fabrication of microfluidic devices. However, best practices for polymer bonds do not achieve sufficient bond strength for many applications. By applying a voltage to a polymer bond in a process called voltage-assisted bonding, bond strength is shown to improve dramatically for two polymers (Cytop™ and poly(methyl methacrylate)). Several experiments were performed to provide a starting point for further exploration of this technique. An optimal voltage range is experimentally observed with a reduction in bonding strength at higher voltages. Additionally, voltage-assisted bonding is shown to reduce void diameter due to bond defects. An electrostatic force model is proposed to explain the improved bond characteristics. This process can be used to improve bond strength for most polymers. (paper)

  8. Chemical polishing of epitoxial silicon wafer

    International Nuclear Information System (INIS)

    Osada, Shohei

    1978-01-01

    SSD telescopes are used for the determination of the kind and energy of charged particles produced by nuclear reactions, and are the equipments combining ΔE counters and E counters. The ΔE counter is a thin SSD which is required to be thin and homogeneous enough to get the high resolution of measurement. The SSDs for ΔE counters have so far been obtained by polishing silicon plates mechanically and chemically or by applying electrolytic polishing method on epitaxial silicon wafers, but it was very hard to obtain them. The creative etching equipment and technique developed this time make it possible to obtain thin SSDs for ΔE counters. The outline of the etching equipment and its technique are described in the report. The etching technique applied for the silicon films for ΔE counters with thickness of about 10 μm was able to be experimentally established in this study. (Kobatake, H.)

  9. Thermoelectric properties of boron and boron phosphide CVD wafers

    Energy Technology Data Exchange (ETDEWEB)

    Kumashiro, Y.; Yokoyama, T.; Sato, A.; Ando, Y. [Yokohama National Univ. (Japan)

    1997-10-01

    Electrical and thermal conductivities and thermoelectric power of p-type boron and n-type boron phosphide wafers with amorphous and polycrystalline structures were measured up to high temperatures. The electrical conductivity of amorphous boron wafers is compatible to that of polycrystals at high temperatures and obeys Mott`s T{sup -{1/4}} rule. The thermoelectric power of polycrystalline boron decreases with increasing temperature, while that of amorphous boron is almost constant in a wide temperature range. The weak temperature dependence of the thermal conductivity of BP polycrystalline wafers reflects phonon scattering by grain boundaries. Thermal conductivity of an amorphous boron wafer is almost constant in a wide temperature range, showing a characteristic of a glass. The figure of merit of polycrystalline BP wafers is 10{sup -7}/K at high temperatures while that of amorphous boron is 10{sup -5}/K.

  10. Reticle variation influence on manufacturing line and wafer device performance

    Science.gov (United States)

    Nistler, John L.; Spurlock, Kyle

    1994-01-01

    Cost effective manufacturing of devices at 0.5, 0.35 and 0.25μm geometries will be highly dependent on a companys' ability to obtain an economic return on investment. The high capital investment in equipment and facilities, not to mention the related chemical and wafer costs, for producing 200mm silicon wafers requires aspects of wafer processing to be tightly controlled. Reduction in errors and enhanced yield management requires early correction or avoidance of reticle problems. It is becoming increasingly important to recognize and track all pertinent factors impacting both the technical and financial viability of a wafer manufacturing fabrication area. Reticle related effects on wafer manufacturing can be costly and affect the total quality perceived by the device customer.

  11. Fluorine-enhanced low-temperature wafer bonding of native-oxide covered Si wafers

    Science.gov (United States)

    Tong, Q.-Y.; Gan, Q.; Fountain, G.; Enquist, P.; Scholz, R.; Gösele, U.

    2004-10-01

    The bonding energy of bonded native-oxide-covered silicon wafers treated in the HNO3/H2O/HF or the HNO3/HF solution prior to room-temperature contact is significantly higher than bonded standard RCA1 cleaned wafer pairs after low-temperature annealing. The bonding energy reaches over 2000mJ/m2 after annealing at 100 °C. The very slight etching and fluorine in the chemically grown oxide are believed to be the main contributors to the enhanced bonding energy. Transmission-electron-microscopic images have shown that the chemically formed native oxide at bonding interface is embedded with many flake-like cavities. The cavities can absorb the by-products of the interfacial reactions that result in covalent bond formation at low temperatures allowing the strong bond to be retained.

  12. Graphitized silicon carbide microbeams: wafer-level, self-aligned graphene on silicon wafers

    International Nuclear Information System (INIS)

    Cunning, Benjamin V; Ahmed, Mohsin; Mishra, Neeraj; Kermany, Atieh Ranjbar; Iacopi, Francesca; Wood, Barry

    2014-01-01

    Currently proven methods that are used to obtain devices with high-quality graphene on silicon wafers involve the transfer of graphene flakes from a growth substrate, resulting in fundamental limitations for large-scale device fabrication. Moreover, the complex three-dimensional structures of interest for microelectromechanical and nanoelectromechanical systems are hardly compatible with such transfer processes. Here, we introduce a methodology for obtaining thousands of microbeams, made of graphitized silicon carbide on silicon, through a site-selective and wafer-scale approach. A Ni-Cu alloy catalyst mediates a self-aligned graphitization on prepatterned SiC microstructures at a temperature that is compatible with silicon technologies. The graphene nanocoating leads to a dramatically enhanced electrical conductivity, which elevates this approach to an ideal method for the replacement of conductive metal films in silicon carbide-based MEMS and NEMS devices. (paper)

  13. ASIC1a Deficient Mice Show Unaltered Neurodegeneration in the Subacute MPTP Model of Parkinson Disease.

    Directory of Open Access Journals (Sweden)

    Daniel Komnig

    Full Text Available Inflammation contributes to the death of dopaminergic neurons in Parkinson disease and can be accompanied by acidification of extracellular pH, which may activate acid-sensing ion channels (ASIC. Accordingly, amiloride, a non-selective inhibitor of ASIC, was protective in an acute 1-methyl-4-phenyl-1,2,3,6-tetrahydropyridine (MPTP mouse model of Parkinson disease. To complement these findings we determined MPTP toxicity in mice deficient for ASIC1a, the most common ASIC isoform in neurons. MPTP was applied i.p. in doses of 30 mg per kg on five consecutive days. We determined the number of dopaminergic neurons in the substantia nigra, assayed by stereological counting 14 days after the last MPTP injection, the number of Nissl positive neurons in the substantia nigra, and the concentration of catecholamines in the striatum. There was no difference between ASIC1a-deficient mice and wildtype controls. We are therefore not able to confirm that ASIC1a are involved in MPTP toxicity. The difference might relate to the subacute MPTP model we used, which more closely resembles the pathogenesis of Parkinson disease, or to further targets of amiloride.

  14. Radiation-hard ASICs for optical data transmission in the first phase of the LHC upgrade

    International Nuclear Information System (INIS)

    Gan, K.K.; Buchholz, P.; Kagan, H.P.; Kass, R.D.; Moore, J.R.; Smith, D.S.; Wiese, A.; Ziolkowskic, M.

    2011-01-01

    We have designed two ASICs for possible applications in the optical links of a new layer of the pixel detector to be install inside the ATLAS Pixel detector for the first phase of the LHC luminosity upgrade. The ASICs include a high-speed driver for a VCSEL and a receiver/decoder to decode the signal received at a PIN diode to extract the data and clock. Both ASICs contain 4 channels for operation with a VCSEL or PIN array. The ASICs were designed using a 130 nm CMOS process to enhance the radiation-hardness. We have characterized the fabricated ASICs and the performance of the ASICs is satisfactory. The receiver/decoder properly decodes the bi-phase marked input stream with low PIN current and the driver can operate a VCSEL up to ∼5 Gb/s. The added functionalities are also successful, including redundancy to bypass a broken VCSEL or PIN channel, individual control of VCSEL current, and power-on reset circuit to set all VCSEL currents to a nominal value.

  15. A comparative study of the time performance between NINO and FlexToT ASICs

    International Nuclear Information System (INIS)

    Sarasola, I.; Rato, P.; Marín, J.; Nemallapudi, M.V.; Gundacker, S.; Auffray, E.; Sánchez, D.; Gascón, D.

    2017-01-01

    Universitat de Barcelona (UB) and CIEMAT have designed the FlexToT ASIC for the front-end readout of SiPM-based scintillator detectors. This ASIC is aimed at time of flight (ToF) positron emission tomography (PET) applications. In this work we have evaluated the time performance of the FlexToT v2 ASIC compared to the NINO ASIC, a fast ASIC developped at CERN. NINO electronics give 64 ps sigma for single-photon time resolution (SPTR) and 93 ps FWHM for coincidence time resolution (CTR) with 2 × 2 × 5 mm 3 LSO:Ce,Ca crystals and S13360-3050CS SiPMs. Using the same SiPMs and crystals, the FlexToT v2 ASIC yields 91 ps sigma for SPTR and 123 ps FWHM for CTR. Despite worse time performace than NINO, FlexToT v2 features lower power consumption (11 vs. 27 mW/ch) and linear ToT energy measurement.

  16. ASIC3, an acid-sensing ion channel, is expressed in metaboreceptive sensory neurons

    Directory of Open Access Journals (Sweden)

    Fierro Leonardo

    2005-11-01

    Full Text Available Abstract Background ASIC3, the most sensitive of the acid-sensing ion channels, depolarizes certain rat sensory neurons when lactic acid appears in the extracellular medium. Two functions have been proposed for it: 1 ASIC3 might trigger ischemic pain in heart and muscle; 2 it might contribute to some forms of touch mechanosensation. Here, we used immunocytochemistry, retrograde labelling, and electrophysiology to ask whether the distribution of ASIC3 in rat sensory neurons is consistent with either of these hypotheses. Results Less than half (40% of dorsal root ganglion sensory neurons react with anti-ASIC3, and the population is heterogeneous. They vary widely in cell diameter and express different growth factor receptors: 68% express TrkA, the receptor for nerve growth factor, and 25% express TrkC, the NT3 growth factor receptor. Consistent with a role in muscle nociception, small ( Conclusion Our data indicates that: 1 ASIC3 is expressed in a restricted population of nociceptors and probably in some non-nociceptors; 2 co-expression of ASIC3 and CGRP, and the absence of P2X3, are distinguishing properties of a class of sensory neurons, some of which innervate blood vessels. We suggest that these latter afferents may be muscle metaboreceptors, neurons that sense the metabolic state of muscle and can trigger pain when there is insufficient oxygen.

  17. Camera-Based Lock-in and Heterodyne Carrierographic Photoluminescence Imaging of Crystalline Silicon Wafers

    Science.gov (United States)

    Sun, Q. M.; Melnikov, A.; Mandelis, A.

    2015-06-01

    Carrierographic (spectrally gated photoluminescence) imaging of a crystalline silicon wafer using an InGaAs camera and two spread super-bandgap illumination laser beams is introduced in both low-frequency lock-in and high-frequency heterodyne modes. Lock-in carrierographic images of the wafer up to 400 Hz modulation frequency are presented. To overcome the frame rate and exposure time limitations of the camera, a heterodyne method is employed for high-frequency carrierographic imaging which results in high-resolution near-subsurface information. The feasibility of the method is guaranteed by the typical superlinearity behavior of photoluminescence, which allows one to construct a slow enough beat frequency component from nonlinear mixing of two high frequencies. Intensity-scan measurements were carried out with a conventional single-element InGaAs detector photocarrier radiometry system, and the nonlinearity exponent of the wafer was found to be around 1.7. Heterodyne images of the wafer up to 4 kHz have been obtained and qualitatively analyzed. With the help of the complementary lock-in and heterodyne modes, camera-based carrierographic imaging in a wide frequency range has been realized for fundamental research and industrial applications toward in-line nondestructive testing of semiconductor materials and devices.

  18. Ultimate intra-wafer critical dimension uniformity control by using lithography and etch tool corrections

    Science.gov (United States)

    Kubis, Michael; Wise, Rich; Reijnen, Liesbeth; Viatkina, Katja; Jaenen, Patrick; Luca, Melisa; Mernier, Guillaume; Chahine, Charlotte; Hellin, David; Kam, Benjamin; Sobieski, Daniel; Vertommen, Johan; Mulkens, Jan; Dusa, Mircea; Dixit, Girish; Shamma, Nader; Leray, Philippe

    2016-03-01

    With shrinking design rules, the overall patterning requirements are getting aggressively tighter. For the 7-nm node and below, allowable CD uniformity variations are entering the Angstrom region (ref [1]). Optimizing inter- and intra-field CD uniformity of the final pattern requires a holistic tuning of all process steps. In previous work, CD control with either litho cluster or etch tool corrections has been discussed. Today, we present a holistic CD control approach, combining the correction capability of the etch tool with the correction capability of the exposure tool. The study is done on 10-nm logic node wafers, processed with a test vehicle stack patterning sequence. We include wafer-to-wafer and lot-to-lot variation and apply optical scatterometry to characterize the fingerprints. Making use of all available correction capabilities (lithography and etch), we investigated single application of exposure tool corrections and of etch tool corrections as well as combinations of both to reach the lowest CD uniformity. Results of the final pattern uniformity based on single and combined corrections are shown. We conclude on the application of this holistic lithography and etch optimization to 7nm High-Volume manufacturing, paving the way to ultimate within-wafer CD uniformity control.

  19. Influence of Wafer Edge Geometry on Removal Rate Profile in Chemical Mechanical Polishing: Wafer Edge Roll-Off and Notch

    Science.gov (United States)

    Fukuda, Akira; Fukuda, Tetsuo; Fukunaga, Akira; Tsujimura, Manabu

    2012-05-01

    In the chemical mechanical polishing (CMP) process, uniform polishing up to near the wafer edge is essential to reduce edge exclusion and improve yield. In this study, we examine the influences of inherent wafer edge geometries, i.e., wafer edge roll-off and notch, on the CMP removal rate profile. We clarify the areas in which the removal rate profile is affected by the wafer edge roll-off and the notch, as well as the intensity of their effects on the removal rate profile. In addition, we propose the use of a small notch to reduce the influence of the wafer notch and present the results of an examination by finite element method (FEM) analysis.

  20. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    Energy Technology Data Exchange (ETDEWEB)

    Thil, Ch., E-mail: christophe.thil@ziti.uni-heidelberg.d [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Baron, A.Q.R. [RIKEN SPring-8 Center, 1-1-1 Kouto, Sayo-cho, Sayo-gun, Hyogo 679-5148 (Japan); Fajardo, P. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France); Fischer, P. [Heidelberg University, Institute of Computer Engineering, B6, 26, 68161 Mannheim (Germany); Graafsma, H. [DESY, Notkestrasse 85, 22607 Hamburg (Germany); Rueffer, R. [ESRF, Polygone Scientifique Louis Neel, 6, rue Jules Horowitz, 38000 Grenoble (France)

    2011-02-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm{sup 2} active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280{mu}mx280{mu}m size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  1. Pixel readout ASIC for an APD based 2D X-ray hybrid pixel detector with sub-nanosecond resolution

    International Nuclear Information System (INIS)

    Thil, Ch.; Baron, A.Q.R.; Fajardo, P.; Fischer, P.; Graafsma, H.; Rueffer, R.

    2011-01-01

    The fast response and the short recovery time of avalanche photodiodes (APDs) in linear mode make those devices ideal for direct X-ray detection in applications requiring high time resolution or counting rate. In order to provide position sensitivity, the XNAP project aims at creating a hybrid pixel detector with nanosecond time resolution based on a monolithic APD sensor array with 32 x32 pixels covering about 1 cm 2 active area. The readout is implemented in a pixelated front-end ASIC suited for the readout of such arrays, matched to pixels of 280μmx280μm size. Every single channel features a fast transimpedance amplifier, a discriminator with locally adjustable threshold and two counters with high dynamic range and counting speed able to accumulate X-ray hits with no readout dead time. Additionally, the detector can be operated in list mode by time-stamping every single event with sub-nanosecond resolution. In a first phase of the project, a 4x4 pixel test module is built to validate the conceptual design of the detector. The XNAP project is briefly presented and the performance of the readout ASIC is discussed.

  2. Integration of SPICE with TEK LV500 ASIC Design Verification System

    Directory of Open Access Journals (Sweden)

    A. Srivastava

    1996-01-01

    Full Text Available The present work involves integration of the simulation stage of design of a VLSI circuit and its testing stage. The SPICE simulator, TEK LV500 ASIC Design Verification System, and TekWaves, a test program generator for LV500, were integrated. A software interface in ‘C’ language in UNIX ‘solaris 1.x’ environment has been developed between SPICE and the testing tools (TekWAVES and LV500. The function of the software interface developed is multifold. It takes input from either SPICE2G.6 or SPICE 3e.1. The output generated by the interface software can be given as an input to either TekWAVES or LV500. A graphical user interface has also been developed with OPENWlNDOWS using Xview tool kit on SUN workstation. As an example, a two phase clock generator circuit has been considered and usefulness of the software demonstrated. The interface software could be easily linked with VLSI design such as MAGIC layout editor.

  3. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    International Nuclear Information System (INIS)

    Zeng, Huiming; Wei, Tingcun; Wang, Jia

    2017-01-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e − +16.3e − /pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  4. Linearity enhancement design of a 16-channel low-noise front-end readout ASIC for CdZnTe detectors

    Energy Technology Data Exchange (ETDEWEB)

    Zeng, Huiming; Wei, Tingcun, E-mail: weitc@nwpu.edu.cn; Wang, Jia

    2017-03-01

    A 16-channel front-end readout application-specific integrated circuit (ASIC) with linearity enhancement design for cadmium zinc telluride (CdZnTe) detectors is presented in this paper. The resistors in the slow shaper are realized using a high-Z circuit to obtain constant resistance value instead of using only a metal–oxide–semiconductor (MOS) transistor, thus the shaping time of the slow shaper can be kept constant for different amounts of input energies. As a result, the linearity of conversion gain is improved significantly. The ASIC was designed and fabricated in a 0.35 µm CMOS process with a die size of 2.60 mm×3.53 mm. The tested results show that a typical channel provides an equivalent noise charge (ENC) of 109.7e{sup −}+16.3e{sup −}/pF with a power consumption of 4 mW and achieves a conversion gain of 87 mV/fC with a nonlinearity of <0.4%. The linearity of conversion gain is improved by at least 86.6% as compared with the traditional approaches using the same front-end readout architecture and manufacture process. Moreover, the inconsistency among channels is <0.3%. An energy resolution of 2.975 keV (FWHM) for gamma rays of 59.5 keV was measured by connecting the ASIC to a 5 mm×5 mm ×2 mm CdZnTe detector at room temperature. The front-end readout ASIC presented in this paper achieves an outstanding linearity performance without compromising the noise, power consumption, and chip size performances.

  5. A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

    International Nuclear Information System (INIS)

    Guo, Di; Liu, Chonghan; Chen, Jinghong; Chramowicz, John; Gong, Datao; He, Huiqin; Hou, Suen; Liu, Tiankuan; Prosser, Alan; Teng, Ping-Kun; Xiang, Annie C.; Xiao, Le; Ye, Jingbo

    2016-01-01

    This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

  6. A 4×8-Gbps VCSEL array driver ASIC and integration with a custom array transmitter module for the LHC front-end transmission

    Energy Technology Data Exchange (ETDEWEB)

    Guo, Di [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); State Key Laboratory of Particle Detection and Electronics, University of Science and Technology of China, Hefei Anhui 230026 (China); Liu, Chonghan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Chen, Jinghong [Department of Electrical and Computer Engineering, University of Houston, Houston, TX 77004 (United States); Chramowicz, John [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Gong, Datao [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); He, Huiqin [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Shenzhen Polytechnic, Shenzhen 518055 (China); Hou, Suen [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Liu, Tiankuan [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Prosser, Alan [Real-Time Systems Engineering Department, Fermi National Laboratory, Batavia, IL 60510 (United States); Teng, Ping-Kun [Institute of Physics, Academia Sinica, Nangang 11529, Taipei, Taiwan (China); Xiang, Annie C. [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Xiao, Le [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States); Department of Physics, Central China Normal University, Wuhan, Hubei 430079 (China); Ye, Jingbo [Department of Physics, Southern Methodist University, Dallas, TX 75275 (United States)

    2016-09-21

    This paper describes the design, fabrication and experiment results of a 4×8-Gbps Vertical-Cavity Surface-Emitting Laser (VCSEL) array driver ASIC with the adjustable active-shunt peaking technique and the novel balanced output structure under the Silicon-on-Sapphire (SOS) process, and a custom array optical transmitter module, featuring a compact size of 10 mm×15 mm×5.3 mm. Both the array driver ASIC and the module have been fully tested after integration as a complete parallel transmitter. Optical eye diagram of each channel passes the eye mask at 8 Gbps/ch with adjacent channel working simultaneously with a power consumption of 150 mW/ch. The optical transmission of Bit-Error Rate (BER) less than 10E-12 is achieved at an aggregated data rate of 4×8-Gbps. - Highlights: • An anode-driven VCSEL Array driver ASIC with the configurable active-shunt peaking technique in pre-driving stages. • A novel full-differential balanced output structure is used to minimize the noise and crosstalk from the power. • A custom array optical transmitter module with custom low-cost reliable alignment method.

  7. Effect of a temperature increase in the non-noxious range on proton-evoked ASIC and TRPV1 activity.

    Science.gov (United States)

    Blanchard, Maxime G; Kellenberger, Stephan

    2011-01-01

    Acid-sensing ion channels (ASICs) are neuronal H(+)-gated cation channels, and the transient receptor potential vanilloid 1 channel (TRPV1) is a multimodal cation channel activated by low pH, noxious heat, capsaicin, and voltage. ASICs and TRPV1 are present in sensory neurons. It has been shown that raising the temperature increases TRPV1 and decreases ASIC H(+)-gated current amplitudes. To understand the underlying mechanisms, we have analyzed ASIC and TRPV1 function in a recombinant expression system and in dorsal root ganglion (DRG) neurons at room and physiological temperature. We show that temperature in the range studied does not affect the pH dependence of ASIC and TRPV1 activation. A temperature increase induces, however, a small alkaline shift of the pH dependence of steady-state inactivation of ASIC1a, ASIC1b, and ASIC2a. The decrease in ASIC peak current amplitudes at higher temperatures is likely in part due to the observed accelerated open channel inactivation kinetics and for some ASIC types to the changed pH dependence of steady-state inactivation. The increase in H(+)-activated TRPV1 current at the higher temperature is at least in part due to a hyperpolarizing shift in its voltage dependence. The contribution of TRPV1 relative to ASICs to H(+)-gated currents in DRG neurons increases with higher temperature and acidity. Still, ASICs remain the principal pH sensors of DRG neurons at 35°C in the pH range ≥6.

  8. Dislocation behavior of surface-oxygen-concentration controlled Si wafers

    International Nuclear Information System (INIS)

    Asazu, Hirotada; Takeuchi, Shotaro; Sannai, Hiroya; Sudo, Haruo; Araki, Koji; Nakamura, Yoshiaki; Izunome, Koji; Sakai, Akira

    2014-01-01

    We have investigated dislocation behavior in the surface area of surface-oxygen-concentration controlled Si wafers treated by a high temperature rapid thermal oxidation (HT-RTO). The HT-RTO process allows us to precisely control the interstitial oxygen concentration ([O i ]) in the surface area of the Si wafers. Sizes of rosette patterns, generated by nano-indentation and subsequent thermal annealing at 900 °C for 1 h, were measured for the Si wafers with various [O i ]. It was found that the rosette size decreases in proportion to the − 0.25 power of [O i ] in the surface area of the Si wafers, which were higher than [O i ] of 1 × 10 17 atoms/cm 3 . On the other hand, [O i ] of lower than 1 × 10 17 atoms/cm 3 did not affect the rosette size very much. These experimental results demonstrate the ability of the HT-RTO process to suppress the dislocation movements in the surface area of the Si wafer. - Highlights: • Surface-oxygen-concentration controlled Si wafers have been made. • The oxygen concentration was controlled by high temperature rapid thermal oxidation. • Dislocation behavior in the surface area of the Si wafers has been investigated. • Rosette size decreased with increasing of interstitial oxygen atoms. • The interstitial oxygen atoms have a pinning effect of dislocations at the surface

  9. Wafer-level vacuum/hermetic packaging technologies for MEMS

    Science.gov (United States)

    Lee, Sang-Hyun; Mitchell, Jay; Welch, Warren; Lee, Sangwoo; Najafi, Khalil

    2010-02-01

    An overview of wafer-level packaging technologies developed at the University of Michigan is presented. Two sets of packaging technologies are discussed: (i) a low temperature wafer-level packaging processes for vacuum/hermeticity sealing, and (ii) an environmentally resistant packaging (ERP) technology for thermal and mechanical control as well as vacuum packaging. The low temperature wafer-level encapsulation processes are implemented using solder bond rings which are first patterned on a cap wafer and then mated with a device wafer in order to encircle and encapsulate the device at temperatures ranging from 200 to 390 °C. Vacuum levels below 10 mTorr were achieved with yields in an optimized process of better than 90%. Pressures were monitored for more than 4 years yielding important information on reliability and process control. The ERP adopts an environment isolation platform in the packaging substrate. The isolation platform is designed to provide low power oven-control, vibration isolation and shock protection. It involves batch flip-chip assembly of a MEMS device onto the isolation platform wafer. The MEMS device and isolation structure are encapsulated at the wafer-level by another substrate with vertical feedthroughs for vacuum/hermetic sealing and electrical signal connections. This technology was developed for high performance gyroscopes, but can be applied to any type of MEMS device.

  10. Multifunctional medicated lyophilised wafer dressing for effective chronic wound healing.

    Science.gov (United States)

    Pawar, Harshavardhan V; Boateng, Joshua S; Ayensu, Isaac; Tetteh, John

    2014-06-01

    Wafers combining weight ratios of Polyox with carrageenan (75/25) or sodium alginate (50/50) containing streptomycin and diclofenac were prepared to improve chronic wound healing. Gels were freeze-dried using a lyophilisation cycle incorporating an annealing step. Wafers were characterised for morphology, mechanical and in vitro functional (swelling, adhesion, drug release in the presence of simulated wound fluid) characteristics. Both blank (BLK) and drug-loaded (DL) wafers were soft, flexible, elegant in appearance and non-brittle in nature. Annealing helped to improve porous nature of wafers but was affected by the addition of drugs. Mechanical characterisation demonstrated that the wafers were strong enough to withstand normal stresses but also flexible to prevent damage to newly formed skin tissue. Differences in swelling, adhesion and drug release characteristics could be attributed to differences in pore size and sodium sulphate formed because of the salt forms of the two drugs. BLK wafers showed relatively higher swelling and adhesion than DL wafers with the latter showing controlled release of streptomycin and diclofenac. The optimised dressing has the potential to reduce bacterial infection and can also help to reduce swelling and pain associated with injury due to the anti-inflammatory action of diclofenac and help to achieve more rapid wound healing. © 2014 Wiley Periodicals, Inc. and the American Pharmacists Association.

  11. Wafer-Level Vacuum Packaging of Smart Sensors

    Directory of Open Access Journals (Sweden)

    Allan Hilton

    2016-10-01

    Full Text Available The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  12. Wafer-Level Vacuum Packaging of Smart Sensors.

    Science.gov (United States)

    Hilton, Allan; Temple, Dorota S

    2016-10-31

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors-"low cost" for ubiquitous presence, and "smart" for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging technology of smart sensors. We describe the processes needed to create the wafer-scale vacuum microchambers, focusing on approaches that involve metal seals and that are compatible with the thermal budget of complementary metal-oxide semiconductor (CMOS) integrated circuits. We review choices of seal materials and structures that are available to a device designer, and present techniques used for the fabrication of metal seals on device and window wafers. We also analyze the deposition and activation of thin film getters needed to maintain vacuum in the ultra-small chambers, and the wafer-to-wafer bonding processes that form the hermetic seal. We discuss inherent trade-offs and challenges of each seal material set and the corresponding bonding processes. Finally, we identify areas for further research that could help broaden implementations of the wafer-level vacuum packaging technology.

  13. Synthesis, structure-activity relationship, and pharmacological profile of analogs of the ASIC-3 inhibitor A-317567.

    Science.gov (United States)

    Kuduk, Scott D; Di Marco, Christina N; Bodmer-Narkevitch, Vera; Cook, Sean P; Cato, Matthew J; Jovanovska, Aneta; Urban, Mark O; Leitl, Michael; Sain, Nova; Liang, Annie; Spencer, Robert H; Kane, Stefanie A; Hartman, George D; Bilodeau, Mark T

    2010-01-20

    The synthesis, structure-activity relationship (SAR), and pharmacological evaluation of analogs of the acid-sensing ion channel (ASIC) inhibitor A-317567 are reported. It was found that the compound with an acetylenic linkage was the most potent ASIC-3 channel blocker. This compound reversed mechanical hypersensitivity in the rat iodoacetate model of osteoarthritis pain, although sedation was noted. Sedation was also observed in ASIC-3 knockout mice, questioning whether sedation and antinociception are mediated via a non-ASIC-3 specific mechanism.

  14. ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion

    OpenAIRE

    Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

    2016-01-01

    Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without alte...

  15. Characterisation of the VMM3 Front-end read-out ASIC

    CERN Document Server

    Bartels, Lara Maria

    2018-01-01

    This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

  16. Development of X-ray CCD camera system with high readout rate using ASIC

    International Nuclear Information System (INIS)

    Nakajima, Hiroshi; Matsuura, Daisuke; Anabuki, Naohisa; Miyata, Emi; Tsunemi, Hiroshi; Doty, John P.; Ikeda, Hirokazu; Katayama, Haruyoshi

    2009-01-01

    We report on the development of an X-ray charge-coupled device (CCD) camera system with high readout rate using application-specific integrated circuit (ASIC) and Camera Link standard. The distinctive ΔΣ type analog-to-digital converter is introduced into the chip to achieve effective noise shaping and to obtain a high resolution with relatively simple circuits. The unit test proved moderately low equivalent input noise of 70μV with a high readout pixel rate of 625 kHz, while the entire chip consumes only 100 mW. The Camera Link standard was applied for the connectivity between the camera system and frame grabbers. In the initial test of the whole system, we adopted a P-channel CCD with a thick depletion layer developed for X-ray CCD camera onboard the next Japanese X-ray astronomical satellite. The characteristic X-rays from 109 Cd were successfully read out resulting in the energy resolution of 379(±7)eV (FWHM) at 22.1 keV, that is, ΔE/E=1.7% with a readout rate of 44 kHz.

  17. The uses of Man-Made diamond in wafering applications

    Science.gov (United States)

    Fallon, D. B.

    1982-01-01

    The continuing, rapid growth of the semiconductor industry requires the involvement of several specialized industries in the development of special products geared toward the unique requirements of this new industry. A specialized manufactured diamond to meet various material removal needs was discussed. The area of silicon wafer slicing has presented yet anothr challenge and it is met most effectively. The history, operation, and performance of Man-Made diamond and particularly as applied to silicon wafer slicing is discussed. Product development is underway to come up with a diamond specifically for sawing silicon wafers on an electroplated blade.

  18. Multi-channel Waveform Sampling ASIC for radiation detection and measurement

    International Nuclear Information System (INIS)

    Shimazoe, K.; Takahashi, H.; Yeom, J.Y.; Furumiya, T.; Ohi, J.

    2013-01-01

    We have designed and fabricated a 16-channel Waveform Sampling ASIC for radiation detection and measurement. Waveform sampling is very important for the pulse shape analysis and discrimination, which is often used in radiation detection to discriminate different radiations such as alpha, beta and gamma rays. One channel of the fabricated ASIC consists of a charge-sensitive preamplifier, a VGA (Variable Gain Amplifier), an ADC (Analog to Digital Converter) and digital circuits. The preamplifier converts the current signal to the voltage signal, and the VGA amplifies the signal to appropriate level for the ADC. The ADC was designed to digitize the waveform with a frequency of 100 MHz and a resolution of 6bits. Digital circuits consist of a free-running ADC and a multiplexer which were designed to convert a digitized 100 MHz/6bit signal to a 200 MHz/3bit one, which is effective for the reduction of the number and for the achievement of the high integration in one chip. This chip was designed and fabricated with 0.35 μm CMOS technology by ROHM and the size of the ASIC is 4.9 mm by 4.9 mm. The design concept and some experimental results are shown in this paper. -- Highlights: ► Waveform sampling (WS) ASIC is newly developed for pulse shape discrimination. ► WS ASIC can be used for radiation measurement and discrimination. ► WS ASIC is fabricated by submicron CMOS technology for 5 mm × 5 mm area. ► WS ASIC achieves high integration and can be used in very limited space

  19. ASIC Readout Circuit Architecture for Large Geiger Photodiode Arrays

    Science.gov (United States)

    Vasile, Stefan; Lipson, Jerold

    2012-01-01

    The objective of this work was to develop a new class of readout integrated circuit (ROIC) arrays to be operated with Geiger avalanche photodiode (GPD) arrays, by integrating multiple functions at the pixel level (smart-pixel or active pixel technology) in 250-nm CMOS (complementary metal oxide semiconductor) processes. In order to pack a maximum of functions within a minimum pixel size, the ROIC array is a full, custom application-specific integrated circuit (ASIC) design using a mixed-signal CMOS process with compact primitive layout cells. The ROIC array was processed to allow assembly in bump-bonding technology with photon-counting infrared detector arrays into 3-D imaging cameras (LADAR). The ROIC architecture was designed to work with either common- anode Si GPD arrays or common-cathode InGaAs GPD arrays. The current ROIC pixel design is hardwired prior to processing one of the two GPD array configurations, and it has the provision to allow soft reconfiguration to either array (to be implemented into the next ROIC array generation). The ROIC pixel architecture implements the Geiger avalanche quenching, bias, reset, and time to digital conversion (TDC) functions in full-digital design, and uses time domain over-sampling (vernier) to allow high temporal resolution at low clock rates, increased data yield, and improved utilization of the laser beam.

  20. VeloPix ASIC development for LHCb VELO upgrade

    CERN Document Server

    van Beuzekom, M; Campbell, M; Collins, P; Gromov, V; Kluit, R; Llopart, X; Poikela, T; Wyllie, K; Zivkovic, V

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and fl exibility in accessing the physics channels of interest in the future, in particular the identi fi cation of fl avour tagged events with displaced vertices. The data acquisition and front end electronics systems require signi fi cant modi fi cation to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-thresho...

  1. VeloPix ASIC development for LHCb VELO upgrade

    International Nuclear Information System (INIS)

    Beuzekom, M. van; Buytaert, J.; Campbell, M.; Collins, P.; Gromov, V.; Kluit, R.; Llopart, X.; Poikela, T.; Wyllie, K.; Zivkovic, V.

    2013-01-01

    The upgrade of the LHCb experiment, planned for 2018, will transform the readout of the entire experiment to a triggerless system operating at 40 MHz. All data reduction algorithms will be run in a high level software farm, and will have access to event information from all subdetectors. This approach will give great power and flexibility in accessing the physics channels of interest in the future, in particular the identification of flavour tagged events with displaced vertices. The data acquisition and front end electronics systems require significant modification to cope with the enormous throughput of data. For the silicon vertex locator (VELO) a dedicated development is underway for a new ASIC, VeloPix, which will be a derivative of the Timepix/Medipix family of chips. The chip will be radiation hard and be able to cope with pixel hit rates of above 500 MHz, highly non-uniformly distributed over the 2 cm 2 chip area. The chip will incorporate local intelligence in the pixels for time-over-threshold measurements, time-stamping and sparse readout. It must in addition be low power, radiation hard, and immune to single event upsets. In order to cope with the datarates and use the pixel area most effectively, an on-chip data compression scheme will integrated. This paper will describe the requirements of the LHCb VELO upgrade, and give an overview of the digital architecture being developed specifically for the readout chip

  2. FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

    Energy Technology Data Exchange (ETDEWEB)

    DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

    2007-10-27

    We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

  3. Studies and development of a readout ASIC for pixelated CdTe detectors for space applications

    International Nuclear Information System (INIS)

    Michalowska, A.

    2013-01-01

    designed two ASICs. The first one, Caterpylar, is a test-chip, which enables the characterization of differently dimensioned CSA circuits to choose the most suitable one for the final application. It is optimized for readout of the target CdTe detector with 300 μm pixel pitch and the corresponding input parameters. With this circuit I have also analyzed possible filtering methods, in particular the semi-Gaussian shaping and the Multi-Correlated Double Sampling (MCDS). Their comparison is preceded by the theoretical analysis of these shapers. The second ASIC D 2 R 1 is a complete readout circuit, containing 256 channels to readout CdTe detector with the same number of pixels, arranged in 16 *16 array. Each channel fits into a layout area of 300 μm - 300 μm. It is based on the MCDS processing with self-triggering capabilities. The mean electronic noise measured over all channels is 29 electrons rms when characterized without the detector. The corresponding power consumption is 315 μW/channel. With these results the future measurements with the detector give prospects for reaching an FWHM spectral resolution in the order of 600 eV at 60 keV. (author) [fr

  4. Sol-gel bonding of silicon wafers

    International Nuclear Information System (INIS)

    Barbe, C.J.; Cassidy, D.J.; Triani, G.; Latella, B.A.; Mitchell, D.R.G.; Finnie, K.S.; Bartlett, J.R.; Woolfrey, J.L.; Collins, G.A.

    2005-01-01

    Low temperature bonding of silicon wafers was achieved using sol-gel technology. The initial sol-gel chemistry of the coating solution was found to influence the mechanical properties of the resulting bonds. More precisely, the influence of parameters such as the alkoxide concentration, water-to-alkoxide molar ratio, pH, and solution aging on the final bond morphologies and interfacial fracture energy was studied. The thickness and density of the sol-gel coating were characterised using ellipsometry. The corresponding bonded specimens were investigated using attenuated total reflectance Fourier transformed infrared spectroscopy to monitor their chemical composition, infrared imaging to control bond integrity, and cross-sectional transmission electron microscopy to study their microstructure. Their interfacial fracture energy was measured using microindentation. An optimum water-to-alkoxide molar ratio of 10 and hydrolysis water at pH = 2 were found. Such conditions led to relatively dense films (> 90%), resulting in bonds with a fracture energy of 3.5 J/m 2 , significantly higher than those obtained using classical hydrophilic bonding (typically 1.5-2.5 J/m 2 ). Ageing of the coating solution was found to decrease the bond strength

  5. Optoelectronic interconnects for 3D wafer stacks

    Science.gov (United States)

    Ludwig, David; Carson, John C.; Lome, Louis S.

    1996-01-01

    Wafer and chip stacking are envisioned as means of providing increased processing power within the small confines of a three-dimensional structure. Optoelectronic devices can play an important role in these dense 3-D processing electronic packages in two ways. In pure electronic processing, optoelectronics can provide a method for increasing the number of input/output communication channels within the layers of the 3-D chip stack. Non-free space communication links allow the density of highly parallel input/output ports to increase dramatically over typical edge bus connections. In hybrid processors, where electronics and optics play a role in defining the computational algorithm, free space communication links are typically utilized for, among other reasons, the increased network link complexity which can be achieved. Free space optical interconnections provide bandwidths and interconnection complexity unobtainable in pure electrical interconnections. Stacked 3-D architectures can provide the electronics real estate and structure to deal with the increased bandwidth and global information provided by free space optical communications. This paper will provide definitions and examples of 3-D stacked architectures in optoelectronics processors. The benefits and issues of these technologies will be discussed.

  6. development and evaluation of lyophilized thiolated-chitosan wafers

    African Journals Online (AJOL)

    User

    THIOLATED-CHITOSAN WAFERS FOR BUCCAL DELIVERY. OF PROTEIN ... of the thiolated polymer incorporating per polymer weight, 10 % each of glycerol as plasticizer, D-mannitol as ..... delivery systems: in vitro stability, in vivo fate, and ...

  7. Cohesive zone model for direct silicon wafer bonding

    Science.gov (United States)

    Kubair, D. V.; Spearing, S. M.

    2007-05-01

    Direct silicon wafer bonding and decohesion are simulated using a spectral scheme in conjunction with a rate-dependent cohesive model. The cohesive model is derived assuming the presence of a thin continuum liquid layer at the interface. Cohesive tractions due to the presence of a liquid meniscus always tend to reduce the separation distance between the wafers, thereby opposing debonding, while assisting the bonding process. In the absence of the rate-dependence effects the energy needed to bond a pair of wafers is equal to that needed to separate them. When rate-dependence is considered in the cohesive law, the experimentally observed asymmetry in the energetics can be explained. The derived cohesive model has the potential to form a bridge between experiments and a multiscale-modelling approach to understand the mechanics of wafer bonding.

  8. Design and screening of ASIC inhibitors based on aromatic diamidines for combating neurological disorders.

    Science.gov (United States)

    Chen, Xuanmao; Orser, Beverley A; MacDonald, John F

    2010-12-01

    Acid sensing ion channels (ASICs) are implicated in various brain functions including learning and memory and are involved in a number of neurological disorders such as pain, ischemic stroke, depression, and multiple sclerosis. We have recently defined ASICs as one of receptor targets of aromatic diamidines in neurons. Aromatic diamidines are DNA-binding agents and have long been used in the treatment of leishmaniasis, trypanosomiasis, pneumocystis pneumonia and babesiosis. Moreover, some aromatic diamidines are used as skin-care and baby products and others have potential to suppress tumor growth or to combat malaria. A large number of aromatic diamidines or analogs have been synthesized. Many efforts are being made to optimize the therapeutic spectrum of aromatic diamidines, i.e. to reduce toxicity, increase oral bioavailability and enhance their penetration of the blood-brain barrier. Aromatic diamidines therefore provide a shortcut of screening for selective ASIC inhibitors with therapeutic potential. Intriguingly nafamostat, a protease inhibitor for treating acute pancreatitis, also inhibits ASIC activities. Aromatic diamidines and nafamostat have many similarities although they belong to distinct classes of medicinal agents for curing different diseases. Here we delineate background, clinical application and drug development of aromatic diamidines that could facilitate the screening for selective ASIC inhibitors for research purposes. Further studies may lead to a drug with therapeutic value and extend the therapeutic scope of aromatic diamidines to combat neurological diseases. Copyright © 2010 Elsevier B.V. All rights reserved.

  9. Automated reticle inspection data analysis for wafer fabs

    Science.gov (United States)

    Summers, Derek; Chen, Gong; Reese, Bryan; Hutchinson, Trent; Liesching, Marcus; Ying, Hai; Dover, Russell

    2009-04-01

    To minimize potential wafer yield loss due to mask defects, most wafer fabs implement some form of reticle inspection system to monitor photomask quality in high-volume wafer manufacturing environments. Traditionally, experienced operators review reticle defects found by an inspection tool and then manually classify each defect as 'pass, warn, or fail' based on its size and location. However, in the event reticle defects are suspected of causing repeating wafer defects on a completed wafer, potential defects on all associated reticles must be manually searched on a layer-by-layer basis in an effort to identify the reticle responsible for the wafer yield loss. This 'problem reticle' search process is a very tedious and time-consuming task and may cause extended manufacturing line-down situations. Often times, Process Engineers and other team members need to manually investigate several reticle inspection reports to determine if yield loss can be tied to a specific layer. Because of the very nature of this detailed work, calculation errors may occur resulting in an incorrect root cause analysis effort. These delays waste valuable resources that could be spent working on other more productive activities. This paper examines an automated software solution for converting KLA-Tencor reticle inspection defect maps into a format compatible with KLA-Tencor's Klarity Defect(R) data analysis database. The objective is to use the graphical charting capabilities of Klarity Defect to reveal a clearer understanding of defect trends for individual reticle layers or entire mask sets. Automated analysis features include reticle defect count trend analysis and potentially stacking reticle defect maps for signature analysis against wafer inspection defect data. Other possible benefits include optimizing reticle inspection sample plans in an effort to support "lean manufacturing" initiatives for wafer fabs.

  10. Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

    Science.gov (United States)

    Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

    2016-01-01

    The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

  11. A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

    CERN Document Server

    Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

    2010-01-01

    High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

  12. ASIC for time-of-flight measurements with picosecond timing resolution

    Energy Technology Data Exchange (ETDEWEB)

    Stankova, Vera; Shen, Wei; Harion, Tobias [Kirchhoff-Institute for Physics, Heidelberg Univ. (Germany)

    2015-07-01

    The Positron Emission Tomography (PET) images are especially affected by a high level of noise. This noise affects the potential to detect and discriminate the tumor in relation to the background. Including Time-of-Flight information, with picosecond time resolution, within the conventional PET scanners will improve the signal-to-noise ratio (SNR) and in sequence the quality of the medical images. A mix-mode ASIC (STIC3) has been developed for high precision timing measurements with Silicon Photomultipliers (SiPM). The STiC3 is 64-channel chip, with fully differential analog front-end for crosstalk and electronic noise immunity. It integrates Time to Digital Converters (TDC) with time binning of 50.2 ps for time and energy measurements. Measurements of the of the analog front-end show a time jitter less than 20 ps and jitter of the TDC together with the digital part is around 37 ps. Further the timing of a channel has been tested by injecting a pulse into two channels and measuring the time difference of the recorded timestamps. A Coincidence Time Resolution (CTR) of 215 ps FWHM has been obtained with 3.1 x 3.1 x 15 mm{sup 2} LYSO:Ce scintillator crystals and Hamamatsu SiPM matric (S12643-050CN(x)). Characterization measurements with the chip and its performances are presented.

  13. Latest results of SEE measurements obtained by the STRURED demonstrator ASIC

    Energy Technology Data Exchange (ETDEWEB)

    Candelori, A. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); De Robertis, G. [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Gabrielli, A. [Physics Department, University of Bologna, Viale Berti Pichat 6/2, c.a.p. 40127, Bologna (Italy); Mattiazzo, S.; Pantano, D. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy); Ranieri, A., E-mail: antonio.ranieri@ba.infn.i [INFN Section of Bari, Via Orabona 4, c.a.p. 70126, Bari (Italy); Tessaro, M. [INFN, Section of Padova, Via Marzolo 8, c.a.p. 35131, Padova (Italy)

    2011-01-21

    With the perspective to develop a radiation-tolerant circuit for High Energy Physics (HEP) applications, a test digital ASIC VLSI chip, called STRURED, has been designed and fabricated using a standard-cell library of commercial 130 nm CMOS technology by implementing three different radiation-tolerant architectures (Hamming, Triple Modular Redundancy and Triple Time Redundancy) in order to correct circuit malfunctions induced by the occurrence of Soft Errors (SEs). SEs are one of the main reasons of failures affecting electronic digital circuits operating in harsh radiation environments, such as in experiments performed at HEP colliders or in apparatus to be operated in space. In this paper we present and discuss the latest results of SE cross-section measurements performed using the STRURED digital device, exposed to high energy heavy ions at the SIRAD irradiation facility of the INFN National Laboratories of Legnaro (Padova, Italy). In particular the different behaviors of the input part and the core of the three radiation-tolerant architectures are analyzed in detail.

  14. Test and verification of a reactor protection system application-specific integrated circuit

    International Nuclear Information System (INIS)

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

    1997-01-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

  15. ASIC1a regulates insular long-term depression and is required for the extinction of conditioned taste aversion.

    Science.gov (United States)

    Li, Wei-Guang; Liu, Ming-Gang; Deng, Shining; Liu, Yan-Mei; Shang, Lin; Ding, Jing; Hsu, Tsan-Ting; Jiang, Qin; Li, Ying; Li, Fei; Zhu, Michael Xi; Xu, Tian-Le

    2016-12-07

    Acid-sensing ion channel 1a (ASIC1a) has been shown to play important roles in synaptic plasticity, learning and memory. Here we identify a crucial role for ASIC1a in long-term depression (LTD) at mouse insular synapses. Genetic ablation and pharmacological inhibition of ASIC1a reduced the induction probability of LTD without affecting that of long-term potentiation in the insular cortex. The disruption of ASIC1a also attenuated the extinction of established taste aversion memory without altering the initial associative taste learning or its long-term retention. Extinction of taste aversive memory led to the reduced insular synaptic efficacy, which precluded further LTD induction. The impaired LTD and extinction learning in ASIC1a null mice were restored by virus-mediated expression of wild-type ASIC1a, but not its ion-impermeable mutant, in the insular cortices. Our data demonstrate the involvement of an ASIC1a-mediated insular synaptic depression mechanism in extinction learning, which raises the possibility of targeting ASIC1a to manage adaptive behaviours.

  16. Full Wafer Redistribution and Wafer Embedding as Key Technologies for a Multi-Scale Neuromorphic Hardware Cluster

    OpenAIRE

    Zoschke, Kai; Güttler, Maurice; Böttcher, Lars; Grübl, Andreas; Husmann, Dan; Schemmel, Johannes; Meier, Karlheinz; Ehrmann, Oswin

    2018-01-01

    Together with the Kirchhoff-Institute for Physics(KIP) the Fraunhofer IZM has developed a full wafer redistribution and embedding technology as base for a large-scale neuromorphic hardware system. The paper will give an overview of the neuromorphic computing platform at the KIP and the associated hardware requirements which drove the described technological developments. In the first phase of the project standard redistribution technologies from wafer level packaging were adapted to enable a ...

  17. The CaloRIC ASIC: Signal Processing for High Granularity Calorimeter

    International Nuclear Information System (INIS)

    Royer, L; Manen, S; Soumpholphakdy, X; Bonnard, J; Gay, P

    2013-01-01

    A readout ASIC called CaloRIC, has been developed to fulfil the signal processing requirements for the Silicon-Tungsten (Si-W) electromagnetic calorimeter of the International Linear Collider (ILC). This ASIC performs the complete processing of the signal delivered by the Si-PIN diode of the detector: charge sensitive amplification, shaping, analog memorization and digitization. Measurements show a global integral non-linearity better than 0.2% for low energy particles, and limited to 2% for high energy particles. The measured Equivalent Noise Charge (ENC) is evaluated at 0.6 fC, which corresponds to 1/6 times the signal released by a Minimum Ionizing Particle (MIP). With the timing sequence of the ILC, the power consumption of the complete channel is evaluated at 43 μW using a power pulsing. A new ASIC (CaloRIC 4 ch) with four improved readout channels has been designed and is ready for manufacturing.

  18. A Low-Power ASIC Signal Processor for a Vestibular Prosthesis.

    Science.gov (United States)

    Töreyin, Hakan; Bhatti, Pamela T

    2016-06-01

    A low-power ASIC signal processor for a vestibular prosthesis (VP) is reported. Fabricated with TI 0.35 μm CMOS technology and designed to interface with implanted inertial sensors, the digitally assisted analog signal processor operates extensively in the CMOS subthreshold region. During its operation the ASIC encodes head motion signals captured by the inertial sensors as electrical pulses ultimately targeted for in-vivo stimulation of vestibular nerve fibers. To achieve this, the ASIC implements a coordinate system transformation to correct for misalignment between natural sensors and implanted inertial sensors. It also mimics the frequency response characteristics and frequency encoding mappings of angular and linear head motions observed at the peripheral sense organs, semicircular canals and otolith. Overall the design occupies an area of 6.22 mm (2) and consumes 1.24 mW when supplied with ± 1.6 V.

  19. A 64-channel readout ASIC for nanowire biosensor array with electrical calibration scheme.

    Science.gov (United States)

    Chai, Kevin T C; Choe, Kunil; Bernal, Olivier D; Gopalakrishnan, Pradeep K; Zhang, Guo-Jun; Kang, Tae Goo; Je, Minkyu

    2010-01-01

    A 1.8-mW, 18.5-mm(2) 64-channel current readout ASIC was implemented in 0.18-µm CMOS together with a new calibration scheme for silicon nanowire biosensor arrays. The ASIC consists of 64 channels of dedicated readout and conditioning circuits which incorporate correlated double sampling scheme to reduce the effect of 1/f noise and offset from the analog front-end. The ASIC provides a 10-bit digital output with a sampling rate of 300 S/s whilst achieving a minimum resolution of 7 pA(rms). A new electrical calibration method was introduced to mitigate the issue of large variations in the nano-scale sensor device parameters and optimize the sensor sensitivity. The experimental results show that the proposed calibration technique improved the sensitivity by 2 to 10 times and reduced the variation between dataset by 9 times.

  20. Femtosecond Resolution Timing in Multi-GS/s Waveform Digitizing ASICs

    Science.gov (United States)

    Orel, Peter; Varner, Gary S.

    2017-07-01

    A waveform digitizer with high-resolution timing provides with the possibility of a novel approach to vertex detectors for high-luminosity particle colliders. Present efforts are centered on the development of an application specific integrated circuit (ASIC) intended to measure signal arrival times with timing resolution in the range of 100 fs or less. The design of such an ASIC requires very good understanding of the effects that impact the timing resolution. This paper presents the simulation results that clearly identify and quantify the sources of error and the underlying coupling mechanisms. In addition, a synthetic waveform generator, developed solely for this purpose, is presented and validated through the measurement results. Crucial knowledge, insights, and confidence have been gained for the development of the ASIC or any other fast, wideband RF systems that aim to achieve such performance.

  1. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  2. Asic3(-/- female mice with hearing deficit affects social development of pups.

    Directory of Open Access Journals (Sweden)

    Wei-Li Wu

    Full Text Available BACKGROUND: Infant crying is an important cue for mothers to respond adequately. Inappropriate response to infant crying can hinder social development in infants. In rodents, the pup-mother interaction largely depends on pup's calls. Mouse pups emit high frequency to ultrasonic vocalization (2-90 kHz to communicate with their dam for maternal care. However, little is known about how the maternal response to infant crying or pup calls affects social development over the long term. METHODOLOGY/PRINCIPAL FINDINGS: Here we used mice lacking acid-sensing ion channel 3 (Asic3(-/- to create a hearing deficit to probe the effect of caregiver hearing on maternal care and adolescent social development. Female Asic3(-/- mice showed elevated hearing thresholds for low to ultrasonic frequency (4-32 kHz on auditory brain stem response, which thus hindered their response to their pups' wriggling calls and ultrasonic vocalization, as well as their retrieval of pups. In adolescence, pups reared by Asic3(-/- mice showed a social deficit in juvenile social behaviors as compared with those reared by wild-type or heterozygous dams. The social-deficit phenotype in juvenile mice reared by Asic3(-/- mice was associated with the reduced serotonin transmission of the brain. However, Asic3(-/- pups cross-fostered to wild-type dams showed rescued social deficit. CONCLUSIONS/SIGNIFICANCE: Inadequate response to pups' calls as a result of ASIC3-dependent hearing loss confers maternal deficits in caregivers and social development deficits in their young.

  3. Atomic force microscopy imaging reveals the formation of ASIC/ENaC cross-clade ion channels.

    Science.gov (United States)

    Jeggle, Pia; Smith, Ewan St J; Stewart, Andrew P; Haerteis, Silke; Korbmacher, Christoph; Edwardson, J Michael

    2015-08-14

    ASIC and ENaC are co-expressed in various cell types, and there is evidence for a close association between them. Here, we used atomic force microscopy (AFM) to determine whether ASIC1a and ENaC subunits are able to form cross-clade hybrid ion channels. ASIC1a and ENaC could be co-isolated from detergent extracts of tsA 201 cells co-expressing the two subunits. Isolated proteins were incubated with antibodies against ENaC and Fab fragments against ASIC1a. AFM imaging revealed proteins that were decorated by both an antibody and a Fab fragment with an angle of ∼120° between them, indicating the formation of ASIC1a/ENaC heterotrimers. Copyright © 2015 Elsevier Inc. All rights reserved.

  4. A low noise ASIC for two dimensional neutron gas detector with performance of high spatial resolution (Contract research)

    International Nuclear Information System (INIS)

    Yamagishi, Hideshi; Toh, Kentaro; Nakamura, Tatsuya; Sakasai, Kaoru; Soyama, Kazuhiko

    2012-02-01

    An ASD-ASIC (Amplifier-Shaper-Discriminator ASIC) with fast response and low noise performances has been designed for two-dimensional position sensitive neutron gas detectors (InSPaD). The InSPaD is a 2D neutron detector system with 3 He gas and provides a high spatial resolution by making distinction between proton and triton particles generated in the gas chamber. The new ASD-ASIC is required to have very low noise, a wide dynamic range, good output linearity and high counting rate. The new ASD-ASIC has been designed by using CMOS and consisted of 64-channel ASDs, a 16-channel multiplexer with LVTTL drivers and sum amplifier system for summing all analog signals. The performances were evaluated by the Spice simulation. It was confirmed that the new ASD-ASIC had very low noise performance, wide dynamic range and fast signal processing functions. (author)

  5. Development of a multi-channel front-end electronics module based on ASIC for silicon strip array detectors

    International Nuclear Information System (INIS)

    Zhao Xingwen; Yan Duo; Su Hong; Qian Yi; Kong Jie; Zhang Xueheng; Li Zhankui; Li Haixia

    2014-01-01

    The silicon strip array detector is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou (HIRFL-CSR). Using the ASICs, the front-end electronics module has been developed for the silicon strip array detectors and can implement measurement of energy of 96 channels. The performance of the front-end electronics module has been tested. The energy linearity of the front-end electronics module is better than 0.3% for the dynamic range of 0.1∼0.7 V. The energy resolution is better than 0.45%. The maximum channel crosstalk is better than 10%. The channel consistency is better than 1.3%. After continuously working for 24 h at room temperature, the maximum drift of the zero-peak is 1.48 mV. (authors)

  6. CBC2: A CMS microstrip readout ASIC with logic for track-trigger modules at HL-LHC

    Energy Technology Data Exchange (ETDEWEB)

    Hall, G., E-mail: g.hall@imperial.ac.uk [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Pesaresi, M.; Raymond, M. [Blackett Laboratory, Imperial College, London SW7 2AZ (United Kingdom); Braga, D.; Jones, L.; Murray, P.; Prydderch, M. [Rutherford Appleton Laboratory, Chilton, Didcot, Oxon OX11 OQX (United Kingdom); Abbaneo, D.; Blanchot, G.; Honma, A.; Kovacs, M.; Vasey, F. [CERN, CH-1211, Geneva (Switzerland)

    2014-11-21

    The CBC2 is the latest version of the CMS Binary Chip ASIC for readout of the upgraded CMS Tracker at the High Luminosity LHC. It is designed in 130 nm CMOS with 254 input channels and will be bump-bonded to a substrate to which sensors will be wire-bonded. The CBC2 is designed to instrument double layer modules, consisting of two overlaid silicon microstrip sensors with aligned microstrips, in the outer tracker. It incorporates logic to identify L1 trigger primitives in the form of “stubs”: high transverse-momentum track candidates which are identified within the low momentum background by selecting correlated hits between two closely separated microstrip sensors. The first prototype modules have been assembled. The performance of the chip in recent laboratory tests is briefly reported and the status of module construction described.

  7. A 128-channel event driven readout ASIC for the R3B tracker

    International Nuclear Information System (INIS)

    Jones, L.; Bell, S.; Morrissey, Q.; Prydderch, M.; Church, I.; Lazarus, I.; Kogimtzis, M.; Pucknell, V.; Labiche, M.; Thornhill, J.; Borri, M.

    2016-01-01

    R 3 B is a detector with high efficiency, acceptance, and resolution for kinematically complete measurements of reactions with high-energy radioactive beams. Detectors track and identify radioactive beams into and out of a reaction target. Three layers of double-sided stereoscopic silicon strips form the tracker detector which must provide precise tracking and vertex determination and in addition include energy and multiplicity measurements. The R 3 B ASIC has been manufactured and is intended for processing and digitising signals generated by ionising particles passing through the tracker. The ASIC processes signals and provides spatial, energy and time measurements

  8. A Low-Power Correlator ASIC for Arrays with Many Antennas

    Science.gov (United States)

    D'Addario, Larry R.; Wang, Douglas

    2016-01-01

    We report the design of a new application-specific integrated circuit (ASIC) for use in radio telescope correlators. It supports the construction of correlators for an arbitrarily large number of signals. The ASIC uses an intrinsically low-power architecture along with design techniques and a process that together result in unprecedentedly low power consumption. The design is flexible in that it can support telescopes with almost any number of antennas N. It is intended for use in an "FX" correlator, where a uniform filter bank breaks each signal into separate frequency channels prior to correlation.

  9. Performance study of SKIROC2/A ASIC for ILD Si-W ECAL

    Science.gov (United States)

    Suehara, T.; Sekiya, I.; Callier, S.; Balagura, V.; Boudry, V.; Brient, J.-C.; de la Taille, C.; Kawagoe, K.; Irles, A.; Magniette, F.; Nanni, J.; Pöschl, R.; Yoshioka, T.

    2018-03-01

    The ILD Si-W ECAL is a sampling calorimeter with tungsten absorber and highly segmented silicon layers for the International Large Detector (ILD), one of the two detector concepts for the International Linear Collider. SKIROC2 is an ASIC for the ILD Si-W ECAL. To investigate the issues found in prototype detectors, we prepared dedicated ASIC evaluation boards with either BGA sockets or directly soldered SKIROC2. We report a performance study with the evaluation boards, including signal-to-noise ratio and TDC performance with comparing SKIROC2 and an updated version, SKIROC2A.

  10. Design and characterization of the readout ASIC for the BESIII CGEM detector

    CERN Document Server

    Cossio, Fabio; Bugalho, Ricardo; Chai, Junying; Cheng, Weishuai; Da Rocha Rolo, Manuel Dionisio; Di Francesco, Agostino; Greco, Michela; Leng, Chongyang; Li, Huaishen; Maggiora, Marco; Marcello, Simonetta; Mignone, Marco; Rivetti, Angelo; Varela, Joao; Wheadon, Richard

    2018-01-01

    TIGER (Turin Integrated Gem Electronics for Readout) is a mixed-mode ASIC for the readout of signals from CGEM (Cylindrical Gas Electron Multiplier) detector in the upgraded inner tracker of the BESIII experiment, carried out at BEPCII in Beijing. The ASIC includes 64 channels, each of which features a dual-branch architecture optimized for timing and energy measurement. The input signal time-of-arrival and charge measurement is provided by low-power TDCs, based on analogue interpolation techniques, and Wilkinson ADCs, with a fully-digital output. The silicon results of TIGER first prototype are presented showing its full functionality.

  11. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

    International Nuclear Information System (INIS)

    Perktold, L; Christiansen, J

    2014-01-01

    The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

  12. Cryogenic and radiation-hard asic for interfacing large format NIR/SWIR detector arrays

    Science.gov (United States)

    Gao, Peng; Dupont, Benoit; Dierickx, Bart; Müller, Eric; Verbruggen, Geert; Gielis, Stijn; Valvekens, Ramses

    2017-11-01

    For scientific and earth observation space missions, weight and power consumption is usually a critical factor. In order to obtain better vehicle integration, efficiency and controllability for large format NIR/SWIR detector arrays, a prototype ASIC is designed. It performs multiple detector array interfacing, power regulation and data acquisition operations inside the cryogenic chambers. Both operation commands and imaging data are communicated via the SpaceWire interface which will significantly reduce the number of wire goes in and out the cryogenic chamber. This "ASIC" prototype is realized in 0.18um CMOS technology and is designed for radiation hardness.

  13. Channel control ASIC for the CMS hadron calorimeter front end readout module

    International Nuclear Information System (INIS)

    Ray Yarema et al.

    2002-01-01

    The Channel Control ASIC (CCA) is used along with a custom Charge Integrator and Encoder (QIE) ASIC to digitize signals from the hybrid photo diodes (HPDs) and photomultiplier tubes (PMTs) in the CMS hadron calorimeter. The CCA sits between the QIE and the data acquisition system. All digital signals to and from the QIE pass through the CCA chip. One CCA chip interfaces with two QIE channels. The CCA provides individually delayed clocks to each of the QIE chips in addition to various control signals. The QIE sends digitized PMT or HPD signals and time slice information to the CCA, which sends the data to the data acquisition system through an optical link

  14. The TDCpix readout ASIC: A 75 ps resolution timing front-end for the NA62 Gigatracker hybrid pixel detector

    Energy Technology Data Exchange (ETDEWEB)

    Kluge, A., E-mail: alexander.kluge@cern.ch; Aglieri Rinella, G.; Bonacini, S.; Jarron, P.; Kaplon, J.; Morel, M.; Noy, M.; Perktold, L.; Poltorak, K.

    2013-12-21

    The TDCpix is a novel pixel readout ASIC for the NA62 Gigatracker detector. NA62 is a new experiment being installed at the CERN Super Proton Synchrotron. Its Gigatracker detector shall provide on-beam tracking and time stamping of individual particles with a time resolution of 150 ps rms. It will consist of three tracking stations, each with one hybrid pixel sensor. The peak flow of particles crossing the detector modules reaches 1.27 MHz/mm{sup 2} for a total rate of about 0.75 GHz. Ten TDCpix chips will be bump-bonded to every silicon pixel sensor. Each chip shall perform time stamping of 100 M particle hits per second with a detection efficiency above 99% and a timing accuracy better than 200 ps rms for an overall three-station-setup time resolution of better than 150 ps. The TDCpix chip has been designed in a 130 nm CMOS technology. It will feature 45×40 square pixels of 300×300μm{sup 2} and a complex End of Column peripheral region including an array of TDCs based on DLLs, four high speed serializers, a low-jitter PLL, readout and control circuits. This contribution will describe the complete design of the final TDCpix ASIC. It will discuss design choices, the challenges faced and some of the lessons learned. Furthermore, experimental results from the testing of circuit prototypes will be presented. These demonstrate the achievement of key performance figures such as a time resolution of the processing chain of 75 ps rms with a laser sent to the center of the pixel and the capability of time stamping charged particles with an overall resolution below 200 ps rms. -- Highlights: • Feasibility demonstration of a silicon pixel detector with sub-ns time tagging capability. • Demonstrator detector assembly with a time resolution of 75 ps RMS with laser charge injection; 170 ps RMS with particle beam. • Design of trigger-less TDCpix ASIC with 1800 pixels, 720 TDC channels and 4 3.2 Gbit/s serializers.

  15. Preparation and characterisation of immobilised humic acid on silicon wafer

    International Nuclear Information System (INIS)

    Szabo, Gy.; Guczi, J.; Telegdi, J.; Pashalidis, I.; Szymczak, W.; Buckau, G.

    2005-01-01

    Full text of publication follows: The chemistry of the interactions of radionuclides with humic acid needs to be understood in details so that humate-mediated migration of radionuclides through the environment can be predicted. To achieve such a data in microscopic scale, several detective techniques, such as atomic force microscopy (AFM), chemical force microscopy (CFM), nuclear microprobe analysis (NMA) and X-ray photoelectron spectroscopy (XPS) can be used to measure intermolecular forces and to visualize the surface morphology. The main aim of this work was to provide humic material with specific properties in order to study with different spectroscopic techniques, the complexation behaviour of surface bound humic acid in microscopic scale. Namely, humic acid has been immobilised on silicon wafers in order to mimic surface bound humic substances in natural aquatic systems. In this communication, we present a simple protocol to immobilize humic acid on silicon wafer surface. A tri-functional silane reagent 3-amino-propyl-tri-methoxy-silane (APTES) was used to modify the surface of silicon wafers and appeared to be able to strongly attached soluble humic acid through their carboxylic groups to solid support. Characterisation of the surfaces, after any preparation steps, was done by ATR-FTIR, AFM and TOF-SIMS. These methods have proved that the humic acid forms a relatively homogeneous layer on the wafers. Immobilisation of humic acid on silicon wafer was further proved by binding isotherm of Am/Nd. (authors)

  16. Increasing reticle inspection efficiency and reducing wafer print-checks using automated defect classification and simulation

    Science.gov (United States)

    Ryu, Sung Jae; Lim, Sung Taek; Vacca, Anthony; Fiekowsky, Peter; Fiekowsky, Dan

    2013-09-01

    IC fabs inspect critical masks on a regular basis to ensure high wafer yields. These requalification inspections are costly for many reasons including the capital equipment, system maintenance, and labor costs. In addition, masks typically remain in the "requal" phase for extended, non-productive periods of time. The overall "requal" cycle time in which reticles remain non-productive is challenging to control. Shipping schedules can slip when wafer lots are put on hold until the master critical layer reticle is returned to production. Unfortunately, substituting backup critical layer reticles can significantly reduce an otherwise tightly controlled process window adversely affecting wafer yields. One major requal cycle time component is the disposition process of mask inspections containing hundreds of defects. Not only is precious non-productive time extended by reviewing hundreds of potentially yield-limiting detections, each additional classification increases the risk of manual review techniques accidentally passing real yield limiting defects. Even assuming all defects of interest are flagged by operators, how can any person's judgment be confident regarding lithographic impact of such defects? The time reticles spend away from scanners combined with potential yield loss due to lithographic uncertainty presents significant cycle time loss and increased production costs. Fortunately, a software program has been developed which automates defect classification with simulated printability measurement greatly reducing requal cycle time and improving overall disposition accuracy. This product, called ADAS (Auto Defect Analysis System), has been tested in both engineering and high-volume production environments with very successful results. In this paper, data is presented supporting significant reduction for costly wafer print checks, improved inspection area productivity, and minimized risk of misclassified yield limiting defects.

  17. Photolithography diagnostic expert systems: a systematic approach to problem solving in a wafer fabrication facility

    Science.gov (United States)

    Weatherwax Scott, Caroline; Tsareff, Christopher R.

    1990-06-01

    One of the main goals of process engineering in the semiconductor industry is to improve wafer fabrication productivity and throughput. Engineers must work continuously toward this goal in addition to performing sustaining and development tasks. To accomplish these objectives, managers must make efficient use of engineering resources. One of the tools being used to improve efficiency is the diagnostic expert system. Expert systems are knowledge based computer programs designed to lead the user through the analysis and solution of a problem. Several photolithography diagnostic expert systems have been implemented at the Hughes Technology Center to provide a systematic approach to process problem solving. This systematic approach was achieved by documenting cause and effect analyses for a wide variety of processing problems. This knowledge was organized in the form of IF-THEN rules, a common structure for knowledge representation in expert system technology. These rules form the knowledge base of the expert system which is stored in the computer. The systems also include the problem solving methodology used by the expert when addressing a problem in his area of expertise. Operators now use the expert systems to solve many process problems without engineering assistance. The systems also facilitate the collection of appropriate data to assist engineering in solving unanticipated problems. Currently, several expert systems have been implemented to cover all aspects of the photolithography process. The systems, which have been in use for over a year, include wafer surface preparation (HMDS), photoresist coat and softbake, align and expose on a wafer stepper, and develop inspection. These systems are part of a plan to implement an expert system diagnostic environment throughout the wafer fabrication facility. In this paper, the systems' construction is described, including knowledge acquisition, rule construction, knowledge refinement, testing, and evaluation. The roles

  18. SENSROC4: An Multichannel Low-Noise Front-End Readout ASIC Dedicated to CZT Detectors for PET Imaging

    International Nuclear Information System (INIS)

    Gao, W.; Liu, H.; Gao, D.; Gan, B.; Wei, T.; Hu, Y.

    2013-06-01

    In this paper, we present the design of a novel low-noise front-end readout application-specific integrated circuit (ASIC) for our small animal PET systems which objective is to achieve the following performances, the spatial resolution of 1 mm 3 , the detection efficiency of 15 % and the time resolution of 1 ns. A cascade amplifier based on the PMOS input transistor is selected to realize the charge-sensitive amplifier (CSA) for the sake of good noise performances. The output of the CSA is split into two branches. One is connected to a slow shaper for energy measurements. The other is connected to a fast shaper for time acquisition. A novel monostable circuit is designed to adjust the time delay of the trigger signals so that the peak value of the shaped voltages can be sampled and stored. Based on the above techniques, an eight-channel front-end readout prototype chip is designed and implemented in 0.35 μm CMOS process. The die size is 2.286 mm x 2.282 mm. The input range of the ASIC is from 2000 e- to 180000 e-, reflecting to the energy of the gamma ray from 11.2 keV to 1 MeV. The gain of the readout channel is 65 V/pC. The best test result of ENC is 86.5 e- at zero farad plus 9.3 e- per pico-farad. The nonlinearity is less than 3 %. The crosstalk is less than 2 %. The power dissipation is about 9 mW/channel (authors)

  19. ASIC or PIC? Implantable stimulators based on semi-custom CMOS technology or low-power microcontroller architecture.

    Science.gov (United States)

    Salmons, S; Gunning, G T; Taylor, I; Grainger, S R; Hitchings, D J; Blackhurst, J; Jarvis, J C

    2001-01-01

    To gain a better understanding of the effects of chronic stimulation on mammalian muscles we needed to generate patterns of greater variety and complexity than simple constant-frequency or burst patterns. We describe here two approaches to the design of implantable neuromuscular stimulators that can satisfy these requirements. Devices of both types were developed and used in long-term experiments. The first device was based on a semi-custom Application Specific Integrated Circuit (ASIC). This approach has the advantage that the circuit can be completely tested at every stage of development and production, assuring a high degree of reliability. It has the drawback of inflexibility: the patterns are produced by state machines implemented in silicon, so each new set of patterns requires a fresh production run, which is costly and time-consuming. The second device was based on a commercial microcontroller (Microchip PIC16C84). The functionality of this type of circuit is specified in software rather than in silicon hardware, allowing a single device to be programmed for different functions. With the use of features designed to improve fault-tolerance we found this approach to be as reliable as that based on ASICs. The encapsulated devices can easily be accommodated subcutaneously on the flank of a rabbit and a recent version is small enough to implant into the peritoneal cavity of rats. The current devices are programmed with a predetermined set of 12 patterns before assembly; the desired pattern is selected after implantation with an electronic flash gun. The operating current drain is less than 40 microA.

  20. Characterizing SOI Wafers By Use Of AOTF-PHI

    Science.gov (United States)

    Cheng, Li-Jen; Li, Guann-Pyng; Zang, Deyu

    1995-01-01

    Developmental nondestructive method of characterizing layers of silicon-on-insulator (SOI) wafer involves combination of polarimetric hyperspectral imaging by use of acousto-optical tunable filters (AOTF-PHI) and computational resources for extracting pertinent data on SOI wafers from polarimetric hyperspectral images. Offers high spectral resolution and both ease and rapidity of optical-wavelength tuning. Further efforts to implement all of processing of polarimetric spectral image data in special-purpose hardware for sake of procesing speed. Enables characterization of SOI wafers in real time for online monitoring and adjustment of production. Also accelerates application of AOTF-PHI to other applications in which need for high-resolution spectral imaging, both with and without polarimetry.

  1. Nonlinear resonance ultrasonic vibrations in Czochralski-silicon wafers

    Science.gov (United States)

    Ostapenko, S.; Tarasov, I.

    2000-04-01

    A resonance effect of generation of subharmonic acoustic vibrations is observed in as-grown, oxidized, and epitaxial silicon wafers. Ultrasonic vibrations were generated into a standard 200 mm Czochralski-silicon (Cz-Si) wafer using a circular ultrasound transducer with major frequency of the radial vibrations at about 26 kHz. By tuning frequency (f) of the transducer within a resonance curve, we observed a generation of intense f/2 subharmonic acoustic mode assigned as a "whistle." The whistle mode has a threshold amplitude behavior and narrow frequency band. The whistle is attributed to a nonlinear acoustic vibration of a silicon plate. It is demonstrated that characteristics of the whistle mode are sensitive to internal stress and can be used for quality control and in-line diagnostics of oxidized and epitaxial Cz-Si wafers.

  2. Wafer-scale fabrication of polymer distributed feedback lasers

    DEFF Research Database (Denmark)

    Christiansen, Mads Brøkner; Schøler, Mikkel; Balslev, Søren

    2006-01-01

    The authors demonstrate wafer-scale, parallel process fabrication of distributed feedback (DFB) polymer dye lasers by two different nanoimprint techniques: By thermal nanoimprint lithography (TNIL) in polymethyl methacrylate and by combined nanoimprint and photolithography (CNP) in SU-8. In both...... techniques, a thin film of polymer, doped with rhodamine-6G laser dye, is spin coated onto a Borofloat glass buffer substrate and shaped into a planar waveguide slab with first order DFB surface corrugations forming the laser resonator. When optically pumped at 532 nm, lasing is obtained in the wavelength...... range between 576 and 607 nm, determined by the grating period. The results, where 13 laser devices are defined across a 10 cm diameter wafer substrate, demonstrate the feasibility of NIL and CNP for parallel wafer-scale fabrication of advanced nanostructured active optical polymer components...

  3. Uniformity across 200 mm silicon wafers printed by nanoimprint lithography

    International Nuclear Information System (INIS)

    Gourgon, C; Perret, C; Tallal, J; Lazzarino, F; Landis, S; Joubert, O; Pelzer, R

    2005-01-01

    Uniformity of the printing process is one of the key parameters of nanoimprint lithography. This technique has to be extended to large size wafers to be useful for several industrial applications, and the uniformity of micro and nanostructures has to be guaranteed on large surfaces. This paper presents results of printing on 200 mm diameter wafers. The residual thickness uniformity after printing is demonstrated at the wafer scale in large patterns (100 μm), in smaller lines of 250 nm and in sub-100 nm features. We show that a mould deformation occurs during the printing process, and that this deformation is needed to guarantee printing uniformity. However, the mould deformation is also responsible for the potential degradation of the patterns

  4. Combined, but not individual, blockade of ASIC3, P2X, and EP4 receptors attenuates the exercise pressor reflex in rats with freely perfused hindlimb muscles.

    Science.gov (United States)

    Stone, Audrey J; Copp, Steven W; Kim, Joyce S; Kaufman, Marc P

    2015-12-01

    In healthy humans, tests of the hypothesis that lactic acid, PGE2, or ATP plays a role in evoking the exercise pressor reflex proved controversial. The findings in humans resembled ours in decerebrate rats that individual blockade of the receptors to lactic acid, PGE2, and ATP had only small effects on the exercise pressor reflex provided that the muscles were freely perfused. This similarity between humans and rats prompted us to test the hypothesis that in rats with freely perfused muscles combined receptor blockade is required to attenuate the exercise pressor reflex. We first compared the reflex before and after injecting either PPADS (10 mg/kg), a P2X receptor antagonist, APETx2 (100 μg/kg), an activating acid-sensing ion channel 3 (ASIC) channel antagonist, or L161982 (2 μg/kg), an EP4 receptor antagonist, into the arterial supply of the hindlimb of decerebrated rats. We then examined the effects of combined blockade of P2X receptors, ASIC3 channels, and EP4 receptors on the exercise pressor reflex using the same doses, intra-arterial route, and time course of antagonist injections as those used for individual blockade. We found that neither PPADS (n = 5), APETx2 (n = 6), nor L161982 (n = 6) attenuated the reflex. In contrast, combined blockade of these receptors (n = 7) attenuated the peak (↓27%, P reflex. Combined blockade injected intravenously had no effect on the reflex. We conclude that combined blockade of P2X receptors, ASIC3 channels, and EP4 receptors on the endings of thin fiber muscle afferents is required to attenuate the exercise pressor reflex in rats with freely perfused hindlimbs. Copyright © 2015 the American Physiological Society.

  5. FRONT-END ASIC FOR HIGH RESOLUTION X-RAY SPECTROMETERS

    International Nuclear Information System (INIS)

    DE GERONIMO, G.; CHEN, W.; FRIED, J.; LI, Z.; PINELLI, D.A.; REHAK, P.; VERNON, E.; GASKIN, J.A.; RAMSEY, B.D.; ANELLI, G.

    2007-01-01

    We present an application specific integrated circuit (ASIC) for high-resolution x-ray spectrometers. The ASIC is designed to read out signals from a pixelated silicon drift detector (SDD). Each hexagonal pixel has an area of 15 mmz and an anode capacitance of less than 100 fF. There is no integrated Field Effect transistor (FET) in the pixel, rather, the readout is done by wirebonding the anodes to the inputs of the ASIC. The ASIC provides 14 channels of low-noise charge amplification, high-order shaping with baseline stabilization, and peak detection with analog memory. The readout is sparse and based on low voltage differential signaling. An interposer provides all the interconnections required to bias and operate the system. The channel dissipates 1.6 mW. The complete 14-pixel unit covers an area of 210 mm 2 , dissipates 12 mW cm -2 , and can be tiled to cover an arbitrarily large detection area. We measured a preliminary resolution of 172 eV at -35 C on the 6 keV peak of a 55 Fe source

  6. Asic developments for radiation imaging applications: The medipix and timepix family

    Science.gov (United States)

    Ballabriga, Rafael; Campbell, Michael; Llopart, Xavier

    2018-01-01

    Hybrid pixel detectors were developed to meet the requirements for tracking in the inner layers at the LHC experiments. With low input capacitance per channel (10-100 fF) it is relatively straightforward to design pulse processing readout electronics with input referred noise of ∼ 100 e-rms and pulse shaping times consistent with tagging of events to a single LHC bunch crossing providing clean 'images' of the ionising tracks generated. In the Medipix Collaborations the same concept has been adapted to provide practically noise hit free imaging in a wide range of applications. This paper reports on the development of three generations of readout ASICs. Two distinctive streams of development can be identified: the Medipix ASICs which integrate data from multiple hits on a pixel and provide the images in the form of frames and the Timepix ASICs who aim to send as much information about individual interactions as possible off-chip for further processing. One outstanding circumstance in the use of these devices has been their numerous successful applications, thanks to a large and active community of developers and users. That process has even permitted new developments for detectors for High Energy Physics. This paper reviews the ASICs themselves and details some of the many applications.

  7. A wireless capsule system with ASIC for monitoring the physiological signals of the human gastrointestinal tract.

    Science.gov (United States)

    Xu, Fei; Yan, Guozheng; Zhao, Kai; Lu, Li; Gao, Jinyang; Liu, Gang

    2014-12-01

    This paper presents the design of a wireless capsule system for monitoring the physiological signals of the human gastrointestinal (GI) tract. The primary components of the system include a wireless capsule, a portable data recorder, and a workstation. Temperature, pH, and pressure sensors; an RF transceiver; a controlling and processing application specific integrated circuit (ASIC); and batteries were applied in a wireless capsule. Decreasing capsule size, improving sensor precision, and reducing power needs were the primary challenges; these were resolved by employing micro sensors, optimized architecture, and an ASIC design that include power management, clock management, a programmable gain amplifier (PGA), an A/D converter (ADC), and a serial peripheral interface (SPI) communication unit. The ASIC has been fabricated in 0.18- μm CMOS technology with a die area of 5.0 mm × 5.0 mm. The wireless capsule integrating the ASIC controller measures Φ 11 mm × 26 mm. A data recorder and a workstation were developed, and 20 cases of human experiments were conducted in hospitals. Preprocessing in the workstation can significantly improve the quality of the data, and 76 original features were determined by mathematical statistics. Based on the 13 optimal features achieved in the evaluation of the features, the clustering algorithm can identify the patients who lack GI motility with a recognition rate reaching 83.3%.

  8. A DES ASIC Suitable for Network Encryption at 10 Gbps and Beyond

    International Nuclear Information System (INIS)

    Gass, Karl; Pierson, Lyndon G.; Robertson, Perry J.; Wilcox, D. Craig; Witzke, Edward L.

    1999-01-01

    The Sandia National Laboratories (SNL) Data Encryption Standard (DES) Application Specific Integrated Circuit (ASIC) is the fastest known implementation of the DES algorithm as defined in the Federal Information Processing Standards (FIPS) Publication 46-2. DES is used for protecting data by cryptographic means. The SNL DES ASIC, over 10 times faster than other currently available DES chips, is a high-speed, filly pipelined implementation offering encryption, decryption, unique key input, or algorithm bypassing on each clock cycle. Operating beyond 105 MHz on 64 bit words, this device is capable of data throughputs greater than 6.7 Billion bits per second (tester limited). Simulations predict proper operation up to 9.28 Billion bits per second. In low frequency, low data rate applications, the ASIC consumes less that one milliwatt of power. The device has features for passing control signals synchronized to throughput data. Three SNL DES ASICS may be easily cascaded to provide the much greater security of triple-key, triple-DES

  9. A 2.5 gb/s GaAs ATM Mux Demux ASIC

    DEFF Research Database (Denmark)

    Madsen, Jens Kargaard; Lassen, Peter Stuhr

    1995-01-01

    This paper describes the design and implementation of a high speed GaAs ATM Mux Demur ASIC (AMDA) which is the key element in a high speed ATM Add-Drop unit. This unit is used in a new distributed ATM multiplexing-demultiplexing architecture for broadband switching systems. The Add-Drop unit...

  10. Development of front-end ASIC for radiation detection and measurement

    International Nuclear Information System (INIS)

    Shimazoe, K.

    2014-01-01

    For realizing the multichannel spectroscopy of gamma rays, the technology of integrated circuits is necessary. Multi-channel gamma ray spectroscopy is very important for many applications including the medical imaging and the environmental monitoring. The current progress in the development of application specific integrated circuit (ASIC) for multi-channel radiation detection is introduced and reviewed. (author)

  11. Front-End ASICs for 3-D Ultrasound : From Beamforming to Digitization

    NARCIS (Netherlands)

    Chen, C.

    2018-01-01

    This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as

  12. An Energy-Efficient ASIC for Wireless Body Sensor Networks in Medical Applications.

    Science.gov (United States)

    Xiaoyu Zhang; Hanjun Jiang; Lingwei Zhang; Chun Zhang; Zhihua Wang; Xinkai Chen

    2010-02-01

    An energy-efficient application-specific integrated circuit (ASIC) featured with a work-on-demand protocol is designed for wireless body sensor networks (WBSNs) in medical applications. Dedicated for ultra-low-power wireless sensor nodes, the ASIC consists of a low-power microcontroller unit (MCU), a power-management unit (PMU), reconfigurable sensor interfaces, communication ports controlling a wireless transceiver, and an integrated passive radio-frequency (RF) receiver with energy harvesting ability. The MCU, together with the PMU, provides quite flexible communication and power-control modes for energy-efficient operations. The always-on passive RF receiver with an RF energy harvesting block offers the sensor nodes the capability of work-on-demand with zero standby power. Fabricated in standard 0.18-¿m complementary metal-oxide semiconductor technology, the ASIC occupies a die area of 2 mm × 2.5 mm. A wireless body sensor network sensor-node prototype using this ASIC only consumes < 10-nA current under the passive standby mode, and < 10 ¿A under the active standby mode, when supplied by a 3-V battery.

  13. Development of a 32-channel ASIC for an X-ray APD detector onboard the ISS

    Science.gov (United States)

    Arimoto, Makoto; Harita, Shohei; Sugita, Satoshi; Yatsu, Yoichi; Kawai, Nobuyuki; Ikeda, Hirokazu; Tomida, Hiroshi; Isobe, Naoki; Ueno, Shiro; Mihara, Tatehiro; Serino, Motoko; Kohmura, Takayoshi; Sakamoto, Takanori; Yoshida, Atsumasa; Tsunemi, Hiroshi; Hatori, Satoshi; Kume, Kyo; Hasegawa, Takashi

    2018-02-01

    We report on the design and performance of a mixed-signal application specific integrated circuit (ASIC) dedicated to avalanche photodiodes (APDs) in order to detect hard X-ray emissions in a wide energy band onboard the International Space Station. To realize wide-band detection from 20 keV to 1 MeV, we use Ce:GAGG scintillators, each coupled to an APD, with low-noise front-end electronics capable of achieving a minimum energy detection threshold of 20 keV. The developed ASIC has the ability to read out 32-channel APD signals using 0.35 μm CMOS technology, and an analog amplifier at the input stage is designed to suppress the capacitive noise primarily arising from the large detector capacitance of the APDs. The ASIC achieves a performance of 2099 e- + 1.5 e-/pF at root mean square (RMS) with a wide 300 fC dynamic range. Coupling a reverse-type APD with a Ce:GAGG scintillator, we obtain an energy resolution of 6.7% (FWHM) at 662 keV and a minimum detectable energy of 20 keV at room temperature (20 °C). Furthermore, we examine the radiation tolerance for space applications by using a 90 MeV proton beam, confirming that the ASIC is free of single-event effects and can operate properly without serious degradation in analog and digital processing.

  14. The GBT-SCA, a radiation tolerant ASIC for detector control applications in SLHC experiments

    CERN Document Server

    Gabrielli, A; Kloukinas, K; Marchioro, A; Moreira, P; Ranieri, A; De Robertis, D

    2009-01-01

    This work describes the architecture of the GigaBit Transceiver – Slow Control Adapter (GBT–SCA) ASIC suitable for the control and monitoring applications of the embedded front-end electronics in the future SLHC experiments. The GBT–SCA is part the GBT chipset currently under development for the SLHC detector upgrades. It is designed for radiation tolerance and it will be fabricated in a commercial 130 nm CMOS technology. The paper discusses the GBT-SCA architecture, the data transfer protocol, the ASIC interfaces, and its integration with the GBT optical link. The GBT–SCA is one the components of the GBT system chipset. It is proposed for the future SLHC experiments and is designed to be configurable matching different front-end system requirements. The GBT-SCA is intended for the slow control and monitoring of the embedded front end electronics and implements a point-to-multi point connection between one GBT optical link ASIC and several front end ASICs. The GBT-SCA connects to a dedicated electrica...

  15. Development of a two-dimensional ASIC for hard X-ray spectroscopy and imaging with a CdTe pixel detector

    International Nuclear Information System (INIS)

    Hiruta, Tatsuro; Tamura, K.; Ikeda, H.; Nakazawa, K.; Takasima, T.; Takahashi, T.

    2006-01-01

    We are developing a two-dimensional analog ASIC for the readout of pixel sensors based on silicon (Si) or cadmium telluride (CdTe) for spectroscopic imaging observations in the X-ray and gamma-ray regions. The aim for the ASIC is to obtain a low-noise performance better than 100 electrons (rms) with self-triggering capabilities. As the first step of prototyping, we have fabricated several ASICs. We obtained an energy resolution of 5.4 keV (FWHM) for 81 keV gamma-rays from 133 Ba with a one-dimensional ASIC connected to a CdTe diode and also verified a readout architecture via a two-dimensional ASIC with 144 pixel channels. Based on the results obtained and experience gained through prototype ASICs, we are developing a 4096-channel two-dimensional analog ASIC

  16. A Prototype PZT Matrix Transducer With Low-Power Integrated Receive ASIC for 3-D Transesophageal Echocardiography.

    Science.gov (United States)

    Chen, Chao; Raghunathan, Shreyas B; Yu, Zili; Shabanimotlagh, Maysam; Chen, Zhao; Chang, Zu-yao; Blaak, Sandra; Prins, Christian; Ponte, Jacco; Noothout, Emile; Vos, Hendrik J; Bosch, Johan G; Verweij, Martin D; de Jong, Nico; Pertijs, Michiel A P

    2016-01-01

    This paper presents the design, fabrication, and experimental evaluation of a prototype lead zirconium titanate (PZT) matrix transducer with an integrated receive ASIC, as a proof of concept for a miniature three-dimensional (3-D) transesophageal echocardiography (TEE) probe. It consists of an array of 9 ×12 piezoelectric elements mounted on the ASIC via an integration scheme that involves direct electrical connections between a bond-pad array on the ASIC and the transducer elements. The ASIC addresses the critical challenge of reducing cable count, and includes front-end amplifiers with adjustable gains and micro-beamformer circuits that locally process and combine echo signals received by the elements of each 3 ×3 subarray. Thus, an order-of-magnitude reduction in the number of receive channels is achieved. Dedicated circuit techniques are employed to meet the strict space and power constraints of TEE probes. The ASIC has been fabricated in a standard 0.18-μm CMOS process and consumes only 0.44 mW/channel. The prototype has been acoustically characterized in a water tank. The ASIC allows the array to be presteered across ±37° while achieving an overall dynamic range of 77 dB. Both the measured characteristics of the individual transducer elements and the performance of the ASIC are in good agreement with expectations, demonstrating the effectiveness of the proposed techniques.

  17. 450mm wafer patterning with jet and flash imprint lithography

    Science.gov (United States)

    Thompson, Ecron; Hellebrekers, Paul; Hofemann, Paul; LaBrake, Dwayne L.; Resnick, Douglas J.; Sreenivasan, S. V.

    2013-09-01

    The next step in the evolution of wafer size is 450mm. Any transition in sizing is an enormous task that must account for fabrication space, environmental health and safety concerns, wafer standards, metrology capability, individual process module development and device integration. For 450mm, an aggressive goal of 2018 has been set, with pilot line operation as early as 2016. To address these goals, consortiums have been formed to establish the infrastructure necessary to the transition, with a focus on the development of both process and metrology tools. Central to any process module development, which includes deposition, etch and chemical mechanical polishing is the lithography tool. In order to address the need for early learning and advance process module development, Molecular Imprints Inc. has provided the industry with the first advanced lithography platform, the Imprio® 450, capable of patterning a full 450mm wafer. The Imprio 450 was accepted by Intel at the end of 2012 and is now being used to support the 450mm wafer process development demands as part of a multi-year wafer services contract to facilitate the semiconductor industry's transition to lower cost 450mm wafer production. The Imprio 450 uses a Jet and Flash Imprint Lithography (J-FILTM) process that employs drop dispensing of UV curable resists to assist high resolution patterning for subsequent dry etch pattern transfer. The technology is actively being used to develop solutions for markets including NAND Flash memory, patterned media for hard disk drives and displays. This paper reviews the recent performance of the J-FIL technology (including overlay, throughput and defectivity), mask development improvements provided by Dai Nippon Printing, and the application of the technology to a 450mm lithography platform.

  18. Wafer scale integration of catalyst dots into nonplanar microsystems

    DEFF Research Database (Denmark)

    Gjerde, Kjetil; Kjelstrup-Hansen, Jakob; Gammelgaard, Lauge

    2007-01-01

    In order to successfully integrate bottom-up fabricated nanostructures such as carbon nanotubes or silicon, germanium, or III-V nanowires into microelectromechanical systems on a wafer scale, reliable ways of integrating catalyst dots are needed. Here, four methods for integrating sub-100-nm...... diameter nickel catalyst dots on a wafer scale are presented and compared. Three of the methods are based on a p-Si layer utilized as an in situ mask, an encapsulating layer, and a sacrificial window mask, respectively. All methods enable precise positioning of nickel catalyst dots at the end...

  19. Computational Modeling in Plasma Processing for 300 mm Wafers

    Science.gov (United States)

    Meyyappan, Meyya; Arnold, James O. (Technical Monitor)

    1997-01-01

    Migration toward 300 mm wafer size has been initiated recently due to process economics and to meet future demands for integrated circuits. A major issue facing the semiconductor community at this juncture is development of suitable processing equipment, for example, plasma processing reactors that can accomodate 300 mm wafers. In this Invited Talk, scaling of reactors will be discussed with the aid of computational fluid dynamics results. We have undertaken reactor simulations using CFD with reactor geometry, pressure, and precursor flow rates as parameters in a systematic investigation. These simulations provide guidelines for scaling up in reactor design.

  20. Physical mechanisms of Cu-Cu wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.

    2014-01-01

    Modern manufacturing processes of complex integrated semiconductor devices are based on wafer-level manufacturing of components which are subsequently interconnected. When compared with classical monolithic bi-dimensional integrated circuits (2D ICs), the new approach of three-dimensional integrated circuits (3D ICs) exhibits significant benefits in terms of signal propagation delay and power consumption due to the reduced metal interconnection length and allows high integration levels with reduced form factor. Metal thermo-compression bonding is a process suitable for 3D interconnects applications at wafer level, which facilitates the electrical and mechanical connection of two wafers even processed in different technologies, such as complementary metal oxide semiconductor (CMOS) and microelectromechanical systems (MEMS). Due to its high electrical conductivity, copper is a very attractive material for electrical interconnects. For Cu-Cu wafer bonding the process requires typically bonding for around 1 h at 400°C and high contact pressure applied during bonding. Temperature reduction below such values is required in order to solve issues regarding (i) throughput in the wafer bonder, (ii) wafer-to-wafer misalignment after bonding and (iii) to minimise thermo-mechanical stresses or device degradation. The aim of this work was to study the physical mechanisms of Cu-Cu bonding and based on this study to further optimise the bonding process for low temperatures. The critical sample parameters (roughness, oxide, crystallinity) were identified using selected analytical techniques and correlated with the characteristics of the bonded Cu-Cu interfaces. Based on the results of this study the impact of several materials and process specifications on the bonding result were theoretically defined and experimentally proven. These fundamental findings subsequently facilitated low temperature (LT) metal thermo-compression Cu-Cu wafer bonding and even room temperature direct

  1. Wafer-Level Vacuum Packaging of Smart Sensors

    OpenAIRE

    Hilton, Allan; Temple, Dorota S.

    2016-01-01

    The reach and impact of the Internet of Things will depend on the availability of low-cost, smart sensors—“low cost” for ubiquitous presence, and “smart” for connectivity and autonomy. By using wafer-level processes not only for the smart sensor fabrication and integration, but also for packaging, we can further greatly reduce the cost of sensor components and systems as well as further decrease their size and weight. This paper reviews the state-of-the-art in the wafer-level vacuum packaging...

  2. Role of TRPV1 and ASIC3 channels in experimental occlusal interference-induced hyperalgesia in rat masseter muscle.

    Science.gov (United States)

    Xu, X X; Cao, Y; Ding, T T; Fu, K Y; Li, Y; Xie, Q F

    2016-04-01

    Masticatory muscle pain may occur following immediate occlusal alteration by dental treatment. The underlying mechanisms are poorly understood. Transient receptor potential vanilloid-1 (TRPV1) and acid-sensing ion channel-3 (ASIC3) mediate muscle hyperalgesia under various pathologic conditions. We have developed a rat model of experimental occlusal interference (EOI) that consistently induces mechanical hyperalgesia in jaw muscles. Whether TRPV1 and ASIC3 mediate this EOI-induced hyperalgesia is unknown. Rat model of EOI-induced masseter hyperalgesia was established. Real-time polymerase chain reaction, Western blot and retrograde labelling combined with immunofluorescence were performed to evaluate the modulation of TRPV1 and ASIC3 expression in trigeminal ganglia (TGs) and masseter afferents of rats after EOI. The effects of intramuscular administration of TRPV1 and ASIC3 antagonists on the EOI-induced hyperalgesia in masseter muscle were examined. After EOI, gene expressions and protein levels of TRPV1 and ASIC3 in bilateral TGs were up-regulated. The percentage of ASIC3- (but not TRPV1-) positive neurons in masseter afferents increased after EOI. More small-sized and small to medium-sized masseter afferents expressed TRPV1 and ASIC3 separately following EOI. These changes peaked at day 7 and then returned to original status within 10 days after EOI. Intramuscular administration of the TRPV1 antagonist AMG-9810 partially reversed this mechanical hyperalgesia in masseter muscle. No improvement was exhibited after administration of the ASIC3 antagonist APETx2. Co-injection of AMG-9810 and APETx2 enhanced the effect of AMG-9810 administration alone. Peripheral TRPV1 and ASIC3 contribute to the development of the EOI-induced mechanical hyperalgesia in masseter muscle. © 2015 European Pain Federation - EFIC®

  3. Modulation of ASIC channels in rat cerebellar purkinje neurons by ischaemia-related signals

    Science.gov (United States)

    Allen, Nicola J; Attwell, David

    2002-01-01

    Acid-sensing ion channels (ASICs), activated by a decrease of extracellular pH, are found in neurons throughout the nervous system. They have an amino acid sequence similar to that of ion channels activated by membrane stretch, and have been implicated in touch sensation. Here we characterize the pH-dependent activation of ASICs in cerebellar Purkinje cells and investigate how they are modulated by factors released in ischaemia. Lowering the external pH from 7.4 activated an inward current at −66 mV, carried largely by Na+ ions, which was half-maximal for a step to pH 6.4 and was blocked by amiloride and gadolinium. The H+-gated current desensitized within a few seconds, but approximately 30% of cells showed a sustained inward current (11% of the peak current) in response to the maintained presence of pH 6 solution. The peak H+-evoked current was potentiated by membrane stretch (which occurs in ischaemia when [K+]o rises) and by arachidonic acid (which is released when [Ca2+]i rises in ischaemia). Arachidonic acid increased to 77% the fraction of cells showing a sustained current evoked by acid pH. The ASIC currents were also potentiated by lactate (which is released when metabolism becomes anaerobic in ischaemia) and by FMRFamide (which may mimic the action of related mammalian RFamide transmitters). These data reinforce suggestions of a mechanosensory aspect to ASIC channel function, and show that the activation of ASICs reflects the integration of multiple signals which are present during ischaemia. PMID:12205186

  4. Development and validation of a 64 channel front end ASIC for 3D directional detection for MIMAC

    International Nuclear Information System (INIS)

    Richer, J P; Bourrion, O; Bosson, G; Guillaudin, O; Mayet, F; Santos, D

    2011-01-01

    A front end ASIC has been designed to equip the μTPC prototype developed for the MIMAC project, which requires 3D reconstruction of low energy particle tracks in order to perform directional detection of galactic Dark Matter. Each ASIC is able to monitor 64 strips of pixels and provides the 'Time Over Threshold' information for each of those. These 64 digital informations, sampled at a rate of 50 MHz, can be transferred at 400 MHz by eight LVDS serial links. Eight ASIC were validated on a 2 × 256 strips of pixels prototype.

  5. Low-power digital ASIC for on-chip spectral analysis of low-frequency physiological signals

    International Nuclear Information System (INIS)

    Nie Zedong; Zhang Fengjuan; Li Jie; Wang Lei

    2012-01-01

    A digital ASIC chip customized for battery-operated body sensing devices is presented. The ASIC incorporates a novel hybrid-architecture fast Fourier transform (FFT) unit that is capable of scalable spectral analysis, a licensed ARM7TDMI IP hardcore and several peripheral IP blocks. Extensive experimental results suggest that the complete chip works as intended. The power consumption of the FFT unit is 0.69 mW at 1 MHz with 1.8 V power supply. The low-power and programmable features of the ASIC make it suitable for ‘on-the-fly’ low-frequency physiological signal processing. (semiconductor integrated circuits)

  6. Participation of peripheral TRPV1, TRPV4, TRPA1 and ASIC in a magnesium sulfate-induced local pain model in rat.

    Science.gov (United States)

    Srebro, Dragana; Vučković, Sonja; Prostran, Milica

    2016-12-17

    We previously showed that magnesium sulfate (MS) has systemic antinociceptive and local peripheral pronociceptive effects. The role of transient receptor potential (TRP) channels and acid-sensing ion channels (ASICs) in the mechanism of action of MS has not been investigated in detail. The aim of this study was to explore the participation of TRP channels in the pronociceptive action of MS in rats after its intraplantar injection. The paw withdrawal threshold (PWT) to mechanical stimuli was measured by the electronic von Frey test. Drugs that were tested were either co-administered with an isotonic pH-unadjusted or pH-adjusted solution of MS intraplantarily, or to the contralateral paw to exclude systemic effects. We found that the subcutaneous administration of both pH-adjusted (7.4) and pH-unadjusted (about 6.0) isotonic (6.2% w/v in water) solutions of MS induce the pain at the injection site. The pH-unadjusted MS solution-induced mechanical hyperalgesia decreased in a dose-dependent manner as a consequence of co-injection of capsazepine, a selective TRPV1 antagonist (20, 100 and 500pmol/paw), RN-1734, a selective TRPV4 antagonist (1.55, 3.1 and 6.2μmol/paw), HC-030031, a selective TRPA1 antagonist (5.6, 28.1 and 140nmol/paw), and amiloride hydrochloride, a non-selective ASIC inhibitor (0.83, 2.5 and 7.55μmol/paw). In pH-adjusted MS-induced hyperalgesia, the highest doses of TRPV1, TRPV4 and TRPA1 antagonists displayed effects that were, respectively, either similar, less pronounced or delayed in comparison to the effect induced by administration of the pH-unadjusted MS solution; the ASIC antagonist did not have any effect. These results suggest that the MS-induced local peripheral mechanical hyperalgesia is mediated via modulation of the activity of peripheral TRPV1, TRPV4, TRPA1 and ASICs. Specific local inhibition of TRP channels represents a novel approach to treating local injection-related pain. Copyright © 2016 IBRO. Published by Elsevier Ltd. All

  7. Low-temperature Au/a-Si wafer bonding

    International Nuclear Information System (INIS)

    Jing, Errong; Xiong, Bin; Wang, Yuelin

    2011-01-01

    The Si/SiO 2 /Ti/Au–Au/Ti/a-Si/SiO 2 /Si bonding structure, which can also be used for the bonding of non-silicon material, was investigated for the first time in this paper. The bond quality test showed that the bond yield, bond repeatability and average shear strength are higher for this bonding structure. The interfacial microstructure analysis indicated that the Au-induced crystallization of the amorphous silicon process leads to big Si grains extending across the bond interface and Au filling the other regions of the bond interface, which result into a strong and void-free bond interface. In addition, the Au-induced crystallization reaction leads to a change in the IR images of the bond interface. Therefore, the IR microscope can be used to evaluate and compare the different bond strengths qualitatively. Furthermore, in order to verify the superiority of the bonding structure, the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si (i.e. no Ti/Au layer on the a-Si surface) and Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structures (i.e. Au thermocompression bonding) were also investigated. For the Si/SiO 2 /Ti/Au–a-Si/SiO 2 /Si bonding structure, the poor bond quality is due to the native oxide layer on the a-Si surface, and for the Si/SiO 2 /Ti/Au–Au/Ti/SiO 2 /Si bonding structure, the poor bond quality is caused by the wafer surface roughness which prevents intimate contact and limits the interdiffusion at the bond interface.

  8. Scatterometry on pelliclized masks: an option for wafer fabs

    Science.gov (United States)

    Gallagher, Emily; Benson, Craig; Higuchi, Masaru; Okumoto, Yasuhiro; Kwon, Michael; Yedur, Sanjay; Li, Shifang; Lee, Sangbong; Tabet, Milad

    2007-03-01

    Optical scatterometry-based metrology is now widely used in wafer fabs for lithography, etch, and CMP applications. This acceptance of a new metrology method occurred despite the abundance of wellestablished CD-SEM and AFM methods. It was driven by the desire to make measurements faster and with a lower cost of ownership. Over the last year, scatterometry has also been introduced in advanced mask shops for mask measurements. Binary and phase shift masks have been successfully measured at all desired points during photomask production before the pellicle is mounted. There is a significant benefit to measuring masks with the pellicle in place. From the wafer fab's perspective, through-pellicle metrology would verify mask effects on the same features that are characterized on wafer. On-site mask verification would enable quality control and trouble-shooting without returning the mask to a mask house. Another potential application is monitoring changes to mask films once the mask has been delivered to the fab (haze, oxide growth, etc.). Similar opportunities apply to the mask metrologist receiving line returns from a wafer fab. The ability to make line-return measurements without risking defect introduction is clearly attractive. This paper will evaluate the feasibility of collecting scatterometry data on pelliclized masks. We explore the effects of several different pellicle types on scatterometry measurements made with broadband light in the range of 320-780 nm. The complexity introduced by the pellicles' optical behavior will be studied.

  9. Fusion bonding of Si wafers investigated by x ray diffraction

    DEFF Research Database (Denmark)

    Weichel, Steen; Grey, Francois; Rasmussen, Kurt

    2000-01-01

    The interface structure of bonded Si(001) wafers with twist angle 6.5 degrees is studied as a function of annealing temperature. An ordered structure is observed in x-ray diffraction by monitoring a satellite reflection due to the periodic modulation near the interface, which results from...

  10. Prediction of thermo-mechanical reliability of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; van Driel, W.D.; Hoofman, R.J.O.M.; Ernst, L.J.

    2004-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  11. Prediction of thermo-mechanical integrity of wafer backend processes

    NARCIS (Netherlands)

    Gonda, V.; Toonder, den J.M.J.; Beijer, J.G.J.; Zhang, G.Q.; Hoofman, R.J.O.M.; Ernst, L.J.; Ernst, L.J.

    2003-01-01

    More than 65% of IC failures are related to thermal and mechanical problems. For wafer backend processes, thermo-mechanical failure is one of the major bottlenecks. The ongoing technological trends like miniaturization, introduction of new materials, and function/product integration will increase

  12. Sacrificial wafer bonding for planarization after very deep etching

    NARCIS (Netherlands)

    Spiering, V.L.; Spiering, Vincent L.; Berenschot, Johan W.; Elwenspoek, Michael Curt; Fluitman, J.H.J.

    A new technique is presented that provides planarization after a very deep etching step in silicon. This offers the possibility for as well resist spinning and layer patterning as realization of bridges or cantilevers across deep holes or grooves. The sacrificial wafer bonding technique contains a

  13. High frequency guided wave propagation in monocrystalline silicon wafers

    Science.gov (United States)

    Pizzolato, Marco; Masserey, Bernard; Robyr, Jean-Luc; Fromme, Paul

    2017-04-01

    Monocrystalline silicon wafers are widely used in the photovoltaic industry for solar panels with high conversion efficiency. The cutting process can introduce micro-cracks in the thin wafers and lead to varying thickness. High frequency guided ultrasonic waves are considered for the structural monitoring of the wafers. The anisotropy of the monocrystalline silicon leads to variations of the wave characteristics, depending on the propagation direction relative to the crystal orientation. Full three-dimensional Finite Element simulations of the guided wave propagation were conducted to visualize and quantify these effects for a line source. The phase velocity (slowness) and skew angle of the two fundamental Lamb wave modes (first anti-symmetric mode A0 and first symmetric mode S0) for varying propagation directions relative to the crystal orientation were measured experimentally. Selective mode excitation was achieved using a contact piezoelectric transducer with a custom-made wedge and holder to achieve a controlled contact pressure. The out-of-plane component of the guided wave propagation was measured using a noncontact laser interferometer. Good agreement was found with the simulation results and theoretical predictions based on nominal material properties of the silicon wafer.

  14. Surface etching technologies for monocrystalline silicon wafer solar cells

    Science.gov (United States)

    Tang, Muzhi

    With more than 200 GW of accumulated installations in 2015, photovoltaics (PV) has become an important green energy harvesting method. The PV market is dominated by solar cells made from crystalline silicon wafers. The engineering of the wafer surfaces is critical to the solar cell cost reduction and performance enhancement. Therefore, this thesis focuses on the development of surface etching technologies for monocrystalline silicon wafer solar cells. It aims to develop a more efficient alkaline texturing method and more effective surface cleaning processes. Firstly, a rapid, isopropanol alcohol free texturing method is successfully demonstrated to shorten the process time and reduce the consumption of chemicals. This method utilizes the special chemical properties of triethylamine, which can form Si-N bonds with wafer surface atoms. Secondly, a room-temperature anisotropic emitter etch-back process is developed to improve the n+ emitter passivation. Using this method, 19.0% efficient screen-printed aluminium back surface field solar cells are developed that show an efficiency gain of 0.15% (absolute) compared with conventionally made solar cells. Finally, state-of-the-art silicon surface passivation results are achieved using hydrogen plasma etching as a dry alternative to the classical hydrofluoric acid wet-chemical process. The effective native oxide removal and the hydrogenation of the silicon surface are shown to be the reasons for the excellent level of surface passivation achieved with this novel method.

  15. Investigation of Surface Pre-Treatment Methods for Wafer-Level Cu-Cu Thermo-Compression Bonding

    Directory of Open Access Journals (Sweden)

    Koki Tanaka

    2016-12-01

    Full Text Available To increase the yield of the wafer-level Cu-Cu thermo-compression bonding method, certain surface pre-treatment methods for Cu are studied which can be exposed to the atmosphere before bonding. To inhibit re-oxidation under atmospheric conditions, the reduced pure Cu surface is treated by H2/Ar plasma, NH3 plasma and thiol solution, respectively, and is covered by Cu hydride, Cu nitride and a self-assembled monolayer (SAM accordingly. A pair of the treated wafers is then bonded by the thermo-compression bonding method, and evaluated by the tensile test. Results show that the bond strengths of the wafers treated by NH3 plasma and SAM are not sufficient due to the remaining surface protection layers such as Cu nitride and SAMs resulting from the pre-treatment. In contrast, the H2/Ar plasma–treated wafer showed the same strength as the one with formic acid vapor treatment, even when exposed to the atmosphere for 30 min. In the thermal desorption spectroscopy (TDS measurement of the H2/Ar plasma–treated Cu sample, the total number of the detected H2 was 3.1 times more than the citric acid–treated one. Results of the TDS measurement indicate that the modified Cu surface is terminated by chemisorbed hydrogen atoms, which leads to high bonding strength.

  16. Fabrication of Through via Holes in Ultra-Thin Fused Silica Wafers for Microwave and Millimeter-Wave Applications

    Directory of Open Access Journals (Sweden)

    Xiao Li

    2018-03-01

    Full Text Available Through via holes in fused silica are a key infrastructure element of microwave and millimeter-wave circuits and 3D integration. In this work, etching through via holes in ultra-thin fused silica wafers using deep reactive-ion etching (DRIE and laser ablation was developed and analyzed. The experimental setup and process parameters for both methods are presented and compared. For DRIE, three types of mask materials including KMPR 1035 (Nippon Kayaku, Tokyo, Japan photoresist, amorphous silicon and chromium—with their corresponding optimized processing recipes—were tested, aiming at etching through a 100 μm fused silica wafer. From the experiments, we concluded that using chromium as the masking material is the best choice when using DRIE. However, we found that the laser ablation method with a laser pulse fluence of 2.89 J/cm2 and a pulse overlap of 91% has advantages over DRIE. The laser ablation method has a simpler process complexity, while offering a fair etching result. In particular, the sidewall profile angle is measured to be 75° to the bottom surface of the wafer, which is ideal for the subsequent metallization process. As a demonstration, a two-inch wafer with 624 via holes was processed using both technologies, and the laser ablation method showed better efficiency compared to DRIE.

  17. ChromAIX2: A large area, high count-rate energy-resolving photon counting ASIC for a Spectral CT Prototype

    Science.gov (United States)

    Steadman, Roger; Herrmann, Christoph; Livne, Amir

    2017-08-01

    Spectral CT based on energy-resolving photon counting detectors is expected to deliver additional diagnostic value at a lower dose than current state-of-the-art CT [1]. The capability of simultaneously providing a number of spectrally distinct measurements not only allows distinguishing between photo-electric and Compton interactions but also discriminating contrast agents that exhibit a K-edge discontinuity in the absorption spectrum, referred to as K-edge Imaging [2]. Such detectors are based on direct converting sensors (e.g. CdTe or CdZnTe) and high-rate photon counting electronics. To support the development of Spectral CT and show the feasibility of obtaining rates exceeding 10 Mcps/pixel (Poissonian observed count-rate), the ChromAIX ASIC has been previously reported showing 13.5 Mcps/pixel (150 Mcps/mm2 incident) [3]. The ChromAIX has been improved to offer the possibility of a large area coverage detector, and increased overall performance. The new ASIC is called ChromAIX2, and delivers count-rates exceeding 15 Mcps/pixel with an rms-noise performance of approximately 260 e-. It has an isotropic pixel pitch of 500 μm in an array of 22×32 pixels and is tile-able on three of its sides. The pixel topology consists of a two stage amplifier (CSA and Shaper) and a number of test features allowing to thoroughly characterize the ASIC without a sensor. A total of 5 independent thresholds are also available within each pixel, allowing to acquire 5 spectrally distinct measurements simultaneously. The ASIC also incorporates a baseline restorer to eliminate excess currents induced by the sensor (e.g. dark current and low frequency drifts) which would otherwise cause an energy estimation error. In this paper we report on the inherent electrical performance of the ChromAXI2 as well as measurements obtained with CZT (CdZnTe)/CdTe sensors and X-rays and radioactive sources.

  18. ASIC and ENaC type sodium channels: conformational states and the structures of the ion selectivity filters.

    Science.gov (United States)

    Hanukoglu, Israel

    2017-02-01

    The acid-sensing ion channels (ASICs) and epithelial sodium channels (ENaC) are members of a superfamily of channels that play critical roles in mechanosensation, chemosensation, nociception, and regulation of blood volume and pressure. These channels look and function like a tripartite funnel that directs the flow of Na + ions into the cytoplasm via the channel pore in the membrane. The subunits that form these channels share a common structure with two transmembrane segments (TM1 and TM2) and a large extracellular part. In most vertebrates, there are five paralogous genes that code for ASICs (ASIC1-ASIC5), and four for ENaC subunits alpha, beta, gamma, and delta (α, β, γ, and δ). While ASICs can form functional channels as a homo- or heterotrimer, ENaC functions as an obligate heterotrimer composed of α-β-γ or β-γ-δ subunits. The structure of ASIC has been determined in several conformations, including desensitized and open states. This review presents a comparison of the structures of these states using easy-to-understand molecular models of the full complex, the central tunnel that includes an outer vestibule, the channel pore, and ion selectivity filter. The differences in the secondary, tertiary, and quaternary structures of the states are summarized to pinpoint the conformational changes responsible for channel opening. Results of site-directed mutagenesis studies of ENaC subunits are examined in light of ASIC1 models. Based on these comparisons, a molecular model for the selectivity filter of ENaC is built by in silico mutagenesis of an ASIC1 structure. These models suggest that Na + ions pass through the filter in a hydrated state. © 2016 Federation of European Biochemical Societies.

  19. Resveratrol attenuates bone cancer pain through regulating the expression levels of ASIC3 and activating cell autophagy.

    Science.gov (United States)

    Zhu, Haili; Ding, Jieqiong; Wu, Ji; Liu, Tingting; Liang, Jing; Tang, Qiong; Jiao, Ming

    2017-11-01

    Bone cancer pain (BCP) is one of the most common pains in patients with malignant cancers. The mechanism underlying BCP is largely unknown. Our previous studies and the increasing evidence both have shown that acid-sensing ion channels 3 (ASIC3) is an important protein in the pathological pain state in some pain models. We hypothesized that the expression change of ASIC3 might be one of the factors related to BCP. In this study, we established the BCP model through intrathecally injecting rat mammary gland carcinoma cells (MRMT-1) into the left tibia of Sprague-Dawley female rats, and found that the BCP rats showed bone destruction, increased mechanical pain sensitivities and up-regulated ASIC3 protein expression levels in L4-L6 dorsal root ganglion. Then, resveratrol, which was intraperitoneally injected into the BCP rats on post-operative Day 21, dose-dependently increased the paw withdrawal threshold of BCP rats, reversed the pain behavior, and had an antinociceptive effect on BCP rats. In ASIC3-transfected SH-SY5Y cells, the ASIC3 protein expression levels were regulated by resveratrol in a dose- and time-dependent manner. Meanwhile, resveratrol also had an antinociceptive effect in ASIC3-mediated pain rat model. Furthermore, resveratrol also enhanced the phosphorylation of AMPK, SIRT1, and LC3-II levels in ASIC3-transfected SH-SY5Y cells, indicating that resveratrol could activate the AMPK-SIRT1-autophagy signal pathway in ASIC3-transfected SH-SY5Y cells. In BCP rats, SIRT1 and LC3-II were also down-regulated. These findings provide new evidence for the use of resveratrol as a therapeutic treatment during BCP states. © The Author 2017. Published by Oxford University Press on behalf of the Institute of Biochemistry and Cell Biology, Shanghai Institutes for Biological Sciences, Chinese Academy of Sciences. All rights reserved. For permissions, please e-mail: journals.permissions@oup.com.

  20. Differential regulation of proton-sensitive ion channels by phospholipids: a comparative study between ASICs and TRPV1.

    Directory of Open Access Journals (Sweden)

    Hae-Jin Kweon

    Full Text Available Protons are released in pain-generating pathological conditions such as inflammation, ischemic stroke, infection, and cancer. During normal synaptic activities, protons are thought to play a role in neurotransmission processes. Acid-sensing ion channels (ASICs are typical proton sensors in the central nervous system (CNS and the peripheral nervous system (PNS. In addition to ASICs, capsaicin- and heat-activated transient receptor potential vanilloid 1 (TRPV1 channels can also mediate proton-mediated pain signaling. In spite of their importance in perception of pH fluctuations, the regulatory mechanisms of these proton-sensitive ion channels still need to be further investigated. Here, we compared regulation of ASICs and TRPV1 by membrane phosphoinositides, which are general cofactors of many receptors and ion channels. We observed that ASICs do not require membrane phosphatidylinositol 4-phosphate (PI(4P or phosphatidylinositol 4,5-bisphosphate (PI(4,5P2 for their function. However, TRPV1 currents were inhibited by simultaneous breakdown of PI(4P and PI(4,5P2. By using a novel chimeric protein, CF-PTEN, that can specifically dephosphorylate at the D3 position of phosphatidylinositol 3,4,5-trisphosphate (PI(3,4,5P3, we also observed that neither ASICs nor TRPV1 activities were altered by depletion of PI(3,4,5P3 in intact cells. Finally, we compared the effects of arachidonic acid (AA on two proton-sensitive ion channels. We observed that AA potentiates the currents of both ASICs and TRPV1, but that they have different recovery aspects. In conclusion, ASICs and TRPV1 have different sensitivities toward membrane phospholipids, such as PI(4P, PI(4,5P2, and AA, although they have common roles as proton sensors. Further investigation about the complementary roles and respective contributions of ASICs and TRPV1 in proton-mediated signaling is necessary.

  1. Chemical strategies for modifications of the solar cell process, from wafering to emitter diffusion; Chemische Ansaetze zur Neuordnung des Solarzellenprozesses ausgehend vom Wafering bis hin zur Emitterdiffusion

    Energy Technology Data Exchange (ETDEWEB)

    Mayer, Kuno

    2009-11-06

    The paper describes the classic standard industrial solar cell based on monocrystalline silicon and describes new methods of fabrication. The first is an alternative wafering concept using laser microjet cutting instead of multiwire cutting. This method originally uses pure, deionized water; it was modified so that the liquid jet will not only be a liquid light conductor but also a transport medium for etching fluids supporting thermal abrasion of silicon by the laser jet. Two etching fluids were tested experimentally; it was found that water-free fluids based on perfluorinated solvents with very slight additions of gaseous chlorine are superior to all other options. In the second section, the wet chemical process steps between wafering and emitter diffusion (i.e. the first high-temperature step) was to be modified. Alternatives to 2-propanol were to be found in the experimental part. Purification after texturing was to be rationalized in order to reduce the process cost, either by using less chemical substances or by achieving shorter process times. 1-pentanol and p-toluolsulfonic acid were identified as two potential alternatives to 2-propanol as texture additives. Finally, it could be shown that wire-cut substrates processed with the new texturing agents have higher mechanical stabilities than substrates used with the classic texturing agent 2-propanol. [German] Im ersten Kapitel wird die klassische Standard-Industrie-Solarzelle auf der Basis monokristallinen Siliziums vorgestellt. Der bisherige Herstellungsprozess der Standard-Industrie-Solarzelle, der in wesentlichen Teilen darauf abzielt, diese Verluste zu minimieren, dient als Referenz fuer die Entwicklung neuer Fertigungsverfahren, wie sie in dieser Arbeit vorgestellt werden. Den ersten thematischen Schwerpunkt bildet die Entwicklung eines alternativen Wafering-Konzeptes zum Multi-Drahtsaegen. Die Basis des neuen, hier vorgestellten Wafering-Prozesses bildet das Laser-Micro-Jet-Verfahren. Dieses System

  2. Evaluation of the viscoelastic behaviour and glass/mould interface friction coefficient in the wafer based precision glass moulding

    DEFF Research Database (Denmark)

    Sarhadi, Ali; Hattel, Jesper Henri; Hansen, Hans Nørgaard

    2014-01-01

    -placements, internal diameter and thickness of the rings are measured during the tests. Viscoelastic andstructural relaxation behaviour of the glass are implemented into the ABAQUS FEM software through aFORTRAN material subroutine (UMAT) and the FE model is validated with a sandwich seal test. Then, byFE simulation...... of the ring compression test and comparison of the experimental creep with the simulatedone in an iterative procedure, viscoelastic parameters of the glass material are characterized. Finally,interfacial glass/mould friction coefficients at different temperatures are determined through FEM basedfriction...... curves combined with experimental data points. The obtained viscoelastic parameters and inter-facial friction coefficients can later be employed for prediction of the final shape/size as well as the stressdistribution in the glass wafer during a real wafer based precision glass moulding process. © 2014...

  3. Fabrication of Ge-on-insulator wafers by Smart-CutTM with thermal management for undamaged donor Ge wafers

    Science.gov (United States)

    Kim, Munho; Cho, Sang June; Jayeshbhai Dave, Yash; Mi, Hongyi; Mikael, Solomon; Seo, Jung-Hun; Yoon, Jung U.; Ma, Zhenqiang

    2018-01-01

    Newly engineered substrates consisting of semiconductor-on-insulator are gaining much attention as starting materials for the subsequent transfer of semiconductor nanomembranes via selective etching of the insulating layer. Germanium-on-insulator (GeOI) substrates are critically important because of the versatile applications of Ge nanomembranes (Ge NMs) toward electronic and optoelectronic devices. Among various fabrication techniques, the Smart-CutTM technique is more attractive than other methods because a high temperature annealing process can be avoided. Another advantage of Smart-CutTM is the reusability of the donor Ge wafer. However, it is very difficult to realize an undamaged Ge wafer because there exists a large mismatch in the coefficient of thermal expansion among the layers. Although an undamaged donor Ge wafer is a prerequisite for its reuse, research related to this issue has not yet been reported. Here we report the fabrication of 4-inch GeOI substrates using the direct wafer bonding and Smart-CutTM process with a low thermal budget. In addition, a thermo-mechanical simulation of GeOI was performed by COMSOL to analyze induced thermal stress in each layer of GeOI. Crack-free donor Ge wafers were obtained by annealing at 250 °C for 10 h. Raman spectroscopy and x-ray diffraction (XRD) indicated similarly favorable crystalline quality of the Ge layer in GeOI compared to that of bulk Ge. In addition, Ge p-n diodes using transferred Ge NM indicate a clear rectifying behavior with an on and off current ratio of 500 at ±1 V. This demonstration offers great promise for high performance transferrable Ge NM-based device applications.

  4. Blind channel estimation for MLSE receiver in high speed optical communications: theory and ASIC implementation.

    Science.gov (United States)

    Gorshtein, Albert; Levy, Omri; Katz, Gilad; Sadot, Dan

    2013-09-23

    Blind channel estimation is critical for digital signal processing (DSP) compensation of optical fiber communications links. The overall channel consists of deterministic distortions such as chromatic dispersion, as well as random and time varying distortions including polarization mode dispersion and timing jitter. It is critical to obtain robust acquisition and tracking methods for estimating these distortions effects, which, in turn, can be compensated by means of DSP such as Maximum Likelihood Sequence Estimation (MLSE). Here, a novel blind estimation algorithm is developed, accompanied by inclusive mathematical modeling, and followed by extensive set of real time experiments that verify quantitatively its performance and convergence. The developed blind channel estimation is used as the basis of an MLSE receiver. The entire scheme is fully implemented in a 65 nm CMOS Application Specific Integrated Circuit (ASIC). Experimental measurements and results are presented, including Bit Error Rate (BER) measurements, which demonstrate the successful data recovery by the MLSE ASIC under various channel conditions and distances.

  5. An ASIC memory buffer controller for a high speed disk system

    Science.gov (United States)

    Hodson, Robert F.; Campbell, Steve

    1993-01-01

    The need for large capacity, high speed mass memory storage devices has become increasingly evident at NASA during the past decade. High performance mass storage systems are crucial to present and future NASA systems. Spaceborne data storage system requirements have grown in response to the increasing amounts of data generated and processed by orbiting scientific experiments. Predictions indicate increases in the volume of data by orders of magnitude during the next decade. Current predictions are for storage capacities on the order of terabits (Tb), with data rates exceeding one gigabit per second (Gbps). As part of the design effort for a state of the art mass storage system, NASA Langley has designed a 144 CMOS ASIC to support high speed data transfers. This paper discusses the system architecture, ASIC design and some of the lessons learned in the development process.

  6. Measurements of low noise 64 channel counting ASIC for Si and CdTe strip detectors

    International Nuclear Information System (INIS)

    Kachel, M; Grybos, P; Szczygiel, R; Takeyoshi, T

    2011-01-01

    We present the design and performance of a 64-channel ASIC called SXDR64. The circuit is intended to work with DC coupled CdTe detectors as well as with standard AC coupled Si detectors. A single channel of the ASIC consists of a charge sensitive amplifier with a pole-zero cancellation circuit, a 4 th order programmable shaper, a base-line restorer and two independent discriminators with 20-bit counters equipped with RAM. The circuit is able to operate correctly with both polarities of the input signal and the detectors leakage current in a few nA range, with the average rate of input pulses up to 1 Mcps.

  7. ENC Measurement for ASIC Preamp Board as a Detector Module for PET System

    Directory of Open Access Journals (Sweden)

    N. Nagara

    2016-08-01

    Full Text Available We developed a gamma ray detector with an LuAG:Pr scintillator and an avalanche photodiode as a detector for a positron emission tomography (PET system. Studies have been performed on the influences of gamma irradiation on application-specific integrated circuit (ASIC preamp boards used as a detector module. As a device used in nuclear environments for substantial durations, the ASIC has to have a lifetime long enough to ensure that there will be a negligible failure rate during this period. These front-end systems must meet the requirements for standard positron emission tomography (PET systems. Therefore, an equivalent noise charge (ENC experiment is needed to measure the front-end system's characteristics. This study showed that minimum ENC conditions can be achieved if a shorter shaping time could be applied.

  8. Curvature evolution of 200 mm diameter GaN-on-insulator wafer fabricated through metalorganic chemical vapor deposition and bonding

    Science.gov (United States)

    Zhang, Li; Lee, Kwang Hong; Kadir, Abdul; Wang, Yue; Lee, Kenneth E.; Tan, Chuan Seng; Chua, Soo Jin; Fitzgerald, Eugene A.

    2018-05-01

    Crack-free 200 mm diameter N-polar GaN-on-insulator (GaN-OI) wafers are demonstrated by the transfer of metalorganic chemical vapor deposition (MOCVD)-grown Ga-polar GaN layers from Si(111) wafers onto SiO2/Si(100) wafers. The wafer curvature of the GaN-OI wafers after the removal of the original Si(111) substrate is correlated with the wafer curvature of the starting GaN-on-Si wafers and the voids on the GaN-on-Si surface that evolve into cracks on the GaN-OI wafers. In crack-free GaN-OI wafers, the wafer curvature during the removal of the AlN nucleation layer, AlGaN strain-compensation buffer layers and GaN layers is correlated with the residual stress distribution within individual layers in the GaN-OI wafer.

  9. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    International Nuclear Information System (INIS)

    Conforti Di Lorenzo, S.; Campagne, J.E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; La Taille, C. de; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-01-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 10 6 ) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  10. PARISROC, an autonomous front-end ASIC for triggerless acquisition in next generation neutrino experiments

    Science.gov (United States)

    Conforti Di Lorenzo, S.; Campagne, J. E.; Drouet, S.; Dulucq, F.; El Berni, M.; Genolini, B.; de La Taille, C.; Martin-Chassard, G.; Seguin Moreau, N.; Wanlin, E.; Xiangbo, Y.

    2012-12-01

    PARISROC (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is a complete readout chip in AustriaMicroSystems (AMS) SiGe 0.35 μm technology designed to read array of 16 Photomultipliers (PMTs). The ASIC is realized in the context of the PMm2 (square meter PhotoMultiplier) project that has proposed a new system of “smart photo-detectors” composed by sensor and read-out electronics dedicated to next generation neutrino experiments. The future water Cherenkov detectors will take place in megaton size water tanks then with a large surface of photo-detection. We propose to segment the large surface in arrays with a single front-end electronics and only the useful data send in surface to be stocked and analyzed. This paper describes the second version of the ASIC and illustrates the chip principle of operation and the main characteristics thank to a series of measurements. It is a 16-channel ASIC with channels that work independently, in triggerless mode and all managed by a common digital part. Then main innovation is that all the channels are handled independently by the digital part so that only channels that have triggered are digitized. Then the data are transferred to the internal memory and sent out in a data driven way. The ASIC allows charge and time measurement. We measured a charge measurement range starting from 160 fC (1 photoelectron-p.e., at PMT gain of 106) to 100 pC (around 600 p.e.) at 1% of linearity; time tagging at 1 ns thanks to a 24-bit counter at 10 MHz and a Time to Digital Converter (TDC) on a 100 ns ramp.

  11. Timing and control requirements for a 32-channel AMU-ADC ASIC for the PHENIX detector

    International Nuclear Information System (INIS)

    Emery, M.S.; Ericson, M.N.; Britton, C.L. Jr.

    1998-01-01

    A custom CMOS Application Specific Integrated Circuit (ASIC) has been developed consisting of an analog memory unit (AMU) has been developed consisting of an analog memory unit (AMU) and analog to digital converter (ADC), both of which have been designed for applications in the PHENIX experiment. This IC consists of 32 pipes of analog memory with 64 cells per pipe. Each pipe also has its own ADC channel. Timing and control signal requirements for optimum performance are discussed in this paper

  12. Wafer-level packaging with compression-controlled seal ring bonding

    Science.gov (United States)

    Farino, Anthony J

    2013-11-05

    A device may be provided in a sealed package by aligning a seal ring provided on a first surface of a first semiconductor wafer in opposing relationship with a seal ring that is provided on a second surface of a second semiconductor wafer and surrounds a portion of the second wafer that contains the device. Forcible movement of the first and second wafer surfaces toward one another compresses the first and second seal rings against one another. A physical barrier against the movement, other than the first and second seal rings, is provided between the first and second wafer surfaces.

  13. Monolithic Active Pixel Matrix with Binary Counters ASIC with nested wells

    International Nuclear Information System (INIS)

    Fahim, F; Deptuch, G; Holm, S; Shenai, A; Lipton, R

    2013-01-01

    Monolithic Active Matrix with Binary Counters (MAMBO) V ASIC has been designed for detecting and measuring low energy X-rays. A nested well structure with a buried n-well (BNW) and a deeper buried p-well (BPW) is used to electrically isolate the detector from the electronics. BNW acts as an AC ground to electrical signals and behaves as a shield. BPW allows for a homogenous electric field in the entire detector volume. The ASIC consists of a matrix of 50 × 52 pixels, each of 105x105μm 2 . Each pixel contains analog functionality accomplished by a charge preamplifier, CR-RC 2 shaper and a baseline restorer. It also contains a window comparator with Upper and Lower thresholds which can be individually trimmed by 4 bit DACs to remove systematic offsets. The hits are registered by a 12 bit counter which is reconfigured as a shift register to serially output the data from the entire ASIC.

  14. A generic miniature multi-feature programmable wireless powering headstage ASIC for implantable biomedical systems.

    Science.gov (United States)

    Kubendran, Rajkumar; Krishnan, Harish; Manola, Bhupendra; John, Simon W M; Chappell, William J; Irazoqui, Pedro P

    2011-01-01

    Wireless powering holds immense promise to enable a variety of implantable biomedical measurement systems with different power supply and current budget requirements. Effective power management demands more functionality in the headstage design like power level detection for range estimation and power save modes for sleep-wake operation. This paper proposes a single chip ASIC solution that addresses these problems by incorporating digitally programmable features and thus has the potential to enable wireless powering for many implantable systems. The ASIC includes an RF rectifier which has a peak efficiency of 17.9% at 900 MHz and 11.0% at 2.4 GHz, a robust 1 V bandgap reference and LDO voltage regulator whose output can be programmed in the range of 1 V-1.5 V, and can drive upto 4 mA of load current. The input RF power level detector has a threshold of 1.6 V and the power management block can be programmed to give a 6%, 12.5% or 25% duty cycle power line to the transmitter resulting in upto 60% reduction in average power. The ASIC was fabricated using the TSMC 65 nm process, occupies 1mm(2) die area and the headstage consumes ~300 μA at 1.2V regulated supply.

  15. Chemical synthesis, 3D structure, and ASIC binding site of the toxin mambalgin-2.

    Science.gov (United States)

    Schroeder, Christina I; Rash, Lachlan D; Vila-Farrés, Xavier; Rosengren, K Johan; Mobli, Mehdi; King, Glenn F; Alewood, Paul F; Craik, David J; Durek, Thomas

    2014-01-20

    Mambalgins are a novel class of snake venom components that exert potent analgesic effects mediated through the inhibition of acid-sensing ion channels (ASICs). The 57-residue polypeptide mambalgin-2 (Ma-2) was synthesized by using a combination of solid-phase peptide synthesis and native chemical ligation. The structure of the synthetic toxin, determined using homonuclear NMR, revealed an unusual three-finger toxin fold reminiscent of functionally unrelated snake toxins. Electrophysiological analysis of Ma-2 on wild-type and mutant ASIC1a receptors allowed us to identify α-helix 5, which borders on the functionally critical acidic pocket of the channel, as a major part of the Ma-2 binding site. This region is also crucial for the interaction of ASIC1a with the spider toxin PcTx1, thus suggesting that the binding sites for these toxins substantially overlap. This work lays the foundation for structure-activity relationship (SAR) studies and further development of this promising analgesic peptide. Copyright © 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.

  16. α-Dendrotoxin inhibits the ASIC current in dorsal root ganglion neurons from rat.

    Science.gov (United States)

    Báez, Adriana; Salceda, Emilio; Fló, Martín; Graña, Martín; Fernández, Cecilia; Vega, Rosario; Soto, Enrique

    2015-10-08

    Dendrotoxins are a group of peptide toxins purified from the venom of several mamba snakes. α-Dendrotoxin (α-DTx, from the Eastern green mamba Dendroaspis angusticeps) is a well-known blocker of voltage-gated K(+) channels and specifically of K(v)1.1, K(v)1.2 and K(v)1.6. In this work we show that α-DTx inhibited the ASIC currents in DRG neurons (IC50=0.8 μM) when continuously perfused during 25 s (including a 5 s pulse to pH 6.1), but not when co-applied with the pH drop. Additionally, we show that α-DTx abolished a transient component of the outward current that, in some experiments, appeared immediately after the end of the acid pulse. Our data indicate that α-DTx inhibits ASICs in the high nM range while some Kv are inhibited in the low nM range. The α-DTx selectivity and its potential interaction with ASICs should be taken in consideration when DTx is used in the high nM range. Copyright © 2015 Elsevier Ireland Ltd. All rights reserved.

  17. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Science.gov (United States)

    Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

    2016-07-01

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

  18. Active counter electrode in a-SiC electrochemical metallization memory

    Science.gov (United States)

    Morgan, K. A.; Fan, J.; Huang, R.; Zhong, L.; Gowers, R.; Ou, J. Y.; Jiang, L.; De Groot, C. H.

    2017-08-01

    Cu/amorphous-SiC (a-SiC) electrochemical metallization memory cells have been fabricated with two different counter electrode (CE) materials, W and Au, in order to investigate the role of CEs in a non-oxide semiconductor switching matrix. In a positive bipolar regime with Cu filaments forming and rupturing, the CE influences the OFF state resistance and minimum current compliance. Nevertheless, a similarity in SET kinetics is seen for both CEs, which differs from previously published SiO2 memories, confirming that CE effects are dependent on the switching layer material or type. Both a-SiC memories are able to switch in the negative bipolar regime, indicating Au and W filaments. This confirms that CEs can play an active role in a non-oxide semiconducting switching matrix, such as a-SiC. By comparing both Au and W CEs, this work shows that W is superior in terms of a higher R OFF/R ON ratio, along with the ability to switch at lower current compliances making it a favourable material for future low energy applications. With its CMOS compatibility, a-SiC/W is an excellent choice for future resistive memory applications.

  19. A new front-end ASIC for GEM detectors with time and charge measurement capabilities

    Energy Technology Data Exchange (ETDEWEB)

    Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

    2016-07-11

    A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

  20. Denuded zone in Czochralski silicon wafer with high carbon content

    International Nuclear Information System (INIS)

    Chen Jiahe; Yang Deren; Ma Xiangyang; Que Duanlin

    2006-01-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 deg. C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 deg. C. Also, the DZs above 15 μm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits

  1. Denuded zone in Czochralski silicon wafer with high carbon content

    Science.gov (United States)

    Chen, Jiahe; Yang, Deren; Ma, Xiangyang; Que, Duanlin

    2006-12-01

    The thermal stability of the denuded zone (DZ) created by high-low-high-temperature annealing in high carbon content (H[C]) and low carbon content (L[C]) Czochralski silicon (Cz-Si) has been investigated in a subsequent ramping and isothermal 1050 °C annealing. The tiny oxygen precipitates which might occur in the DZ were checked. It was found in the L[C] Cz-Si that the DZ shrank and the density of bulk micro-defects (BMDs) reduced with the increase of time spent at 1050 °C. Also, the DZs above 15 µm of thickness present in the H[C] Cz-Si wafers continuously and the density and total volume of BMDs first decreased then increased and finally decreased again during the treatments. Moreover, tiny oxygen precipitates were hardly generated inside the DZs, indicating that H[C] Cz-Si wafers could support the fabrication of integrated circuits.

  2. Peptide and protein loading into porous silicon wafers

    Energy Technology Data Exchange (ETDEWEB)

    Prestidge, C.A.; Barnes, T.J.; Mierczynska-Vasilev, A.; Kempson, I.; Peddie, F. [Ian Wark Research Institute, University of South Australia, Mawson Lakes (Australia); Barnett, C. [Medica Ltd, Malvern, Worcestershire, UK WR14 3SZ (United Kingdom)

    2008-02-15

    The influence of peptide/protein size and hydrophobicity on the physical and chemical aspects of loading within porous silicon (pSi) wafer samples has been determined using Atomic Force Microscopy (AFM) and Time-of-Flight Secondary Ion Mass Spectroscopy (ToF-SIMS). Both Gramicidin A (a small hydrophobic peptide) and Papain (a larger hydrophilic protein) were observed (ToF-SIMS) to penetrate across the entire pSi layer, even at low loading levels. AFM surface imaging of pSi wafers during peptide/protein loading showed that surface roughness increased with Papain loading, but decreased with Gramicidin A loading. For Papain, the loading methodology was also found to influence loading efficiency. These differences indicate more pronounced surface adsorption of Papain. (copyright 2008 WILEY-VCH Verlag GmbH and Co. KGaA, Weinheim) (orig.)

  3. Silicon-to-silicon wafer bonding using evaporated glass

    DEFF Research Database (Denmark)

    Weichel, Steen; Reus, Roger De; Lindahl, M.

    1998-01-01

    Anodic bending of silicon to silicon 4-in. wafers using an electron-beam evaporated glass (Schott 8329) was performed successfully in air at temperatures ranging from 200 degrees C to 450 degrees C. The composition of the deposited glass is enriched in sodium as compared to the target material....... The roughness of the as-deposited films was below 5 nm and was found to be unchanged by annealing at 500 degrees C for 1 h in air. No change in the macroscopic edge profiles of the glass film was found as a function of annealing; however, small extrusions appear when annealing above 450 degrees C. Annealing...... of silicon/glass structures in air around 340 degrees C for 15 min leads to stress-free structures. Bonded wafer pairs, however, show no reduction in stress and always exhibit compressive stress. The bond yield is larger than 95% for bonding temperatures around 350 degrees C and is above 80% for bonding...

  4. Coaxial twin-shaft magnetic fluid seals applied in vacuum wafer-handling robot

    Science.gov (United States)

    Cong, Ming; Wen, Haiying; Du, Yu; Dai, Penglei

    2012-07-01

    Compared with traditional mechanical seals, magnetic fluid seals have unique characters of high airtightness, minimal friction torque requirements, pollution-free and long life-span, widely used in vacuum robots. With the rapid development of Integrate Circuit (IC), there is a stringent requirement for sealing wafer-handling robots when working in a vacuum environment. The parameters of magnetic fluid seals structure is very important in the vacuum robot design. This paper gives a magnetic fluid seal device for the robot. Firstly, the seal differential pressure formulas of magnetic fluid seal are deduced according to the theory of ferrohydrodynamics, which indicate that the magnetic field gradient in the sealing gap determines the seal capacity of magnetic fluid seal. Secondly, the magnetic analysis model of twin-shaft magnetic fluid seals structure is established. By analyzing the magnetic field distribution of dual magnetic fluid seal, the optimal value ranges of important parameters, including parameters of the permanent magnetic ring, the magnetic pole tooth, the outer shaft, the outer shaft sleeve and the axial relative position of two permanent magnetic rings, which affect the seal differential pressure, are obtained. A wafer-handling robot equipped with coaxial twin-shaft magnetic fluid rotary seals and bellows seal is devised and an optimized twin-shaft magnetic fluid seals experimental platform is built. Test result shows that when the speed of the two rotational shafts ranges from 0-500 r/min, the maximum burst pressure is about 0.24 MPa. Magnetic fluid rotary seals can provide satisfactory performance in the application of wafer-handling robot. The proposed coaxial twin-shaft magnetic fluid rotary seal provides the instruction to design high-speed vacuum robot.

  5. Simplified nonplanar wafer bonding for heterogeneous device integration

    Science.gov (United States)

    Geske, Jon; Bowers, John E.; Riley, Anton

    2004-07-01

    We demonstrate a simplified nonplanar wafer bonding technique for heterogeneous device integration. The improved technique can be used to laterally integrate dissimilar semiconductor device structures on a lattice-mismatched substrate. Using the technique, two different InP-based vertical-cavity surface-emitting laser active regions have been integrated onto GaAs without compromising the quality of the photoluminescence. Experimental and numerical simulation results are presented.

  6. Cost of Czochralski wafers as a function of diameter

    Science.gov (United States)

    Leipold, M. H.; Radics, C.; Kachare, A.

    1980-02-01

    The impact of diameter in the range of 10 to 15 cm on the cost of wafers sliced from Czochralski ingots was analyzed. Increasing silicon waste and decreasing ingot cost with increasing ingot size were estimated along with projected costs. Results indicate a small but continuous decrease in sheet cost with increasing ingot size in this size range. Sheet costs including silicon are projected to be $50 to $60/sq m (1980 $) depending upon technique used.

  7. Development of Formulations for a-SiC and Manganese CMP and Post-CMP Cleaning of Cobalt

    Science.gov (United States)

    Lagudu, Uma Rames Krishna

    . Furthermore, addition of a low concentration of 250 ppm Brij-35 to this slurry suppressed the RRs of silicon dioxide to zero, while retaining the RRs of a-SiC at ˜2700 nm/h , a combination of RRs that is appropriate for hard mask polishing. The second part of this thesis focuses on the polishing of manganese which was proposed as a "self-forming" barrier material to prevent copper diffusion in advanced generation (22 nm and smaller) Si devices. A major challenge associated with such a self-forming Mn barrier for Cu interconnects in sub-22nm devices is galvanic corrosion that can occur at the Cu-Mn interface during chemical mechanical planarization. In the present work, it was shown that an aqueous solution of sucrose, BTA and potassium periodate reduces the corrosion potential gap between Cu and Mn to ˜ 0.01 V at pH 10 while also lowering the galvanic currents significantly and hence can be an excellent candidate for a polishing slurry. We discuss the role of these reagents and the inhibiting film that can be formed at the interface of the bimetallic system in this solution. Preliminary polishing results for Cu and Mn using a silica-based slurry formulated with this solution are also presented. The third part involves the development of compositions for Post CMP cleaning of cobalt barriers in advanced generation (22 nm and smaller). The thickness of the cobalt films was found to impact the corrosion behavior of the films. Thinner films of cobalt were found be more prone to galvanic corrosion in the presence of copper. The corrosion currents were low for both Cu and Co in all the solutions tested but the galvanic currents varied significantly. It was found that while BTA was not able to suppress the galvanic corrosion between Cu and Co (2000 A) at pH 8, either 60 mM of 3 Amino 1,2,4 triazole or 30 mM of 3 Amino 5 methyl thio 1,2,4 triazole were able to suppress the galvanic corrosion between Cu and Co (2000 A) to < 0.3 micro amperes per square cm at pH 8. These compositions

  8. Radiation Hardened Structured ASIC Platform for Rapid Chip Development for Very High Speed System on a Chip (SoC) and Complex Digital Logic Systems, Phase I

    Data.gov (United States)

    National Aeronautics and Space Administration — Radiation Hardened Application Specific Integrated Circuits (ASICs) provide for the highest performance, lowest power and size for Space Missions. In order to...

  9. Physical mechanisms of copper-copper wafer bonding

    International Nuclear Information System (INIS)

    Rebhan, B.; Hingerl, K.

    2015-01-01

    The study of the physical mechanisms driving Cu-Cu wafer bonding allowed for reducing the bonding temperatures below 200 °C. Metal thermo-compression Cu-Cu wafer bonding results obtained at such low temperatures are very encouraging and suggest that the process is possible even at room temperature if some boundary conditions are fulfilled. Sputtered (PVD) and electroplated Cu thin layers were investigated, and the analysis of both metallization techniques demonstrated the importance of decreasing Cu surface roughness. For an equal surface roughness, the bonding temperature of PVD Cu wafers could be even further reduced due to the favorable microstructure. Their smaller grain size enhances the length of the grain boundaries (observed on the surface prior bonding), acting as efficient mass transfer channels across the interface, and hence the grains are able to grow over the initial bonding interface. Due to the higher concentration of random high-angle grain boundaries, this effect is intensified. The model presented is explaining the microstructural changes based on atomic migration, taking into account that the reduction of the grain boundary area is the major driving force to reduce the Gibbs free energy, and predicts the subsequent microstructure evolution (grain growth) during thermal annealing

  10. Mechanical Properties of Photovoltaic Silicon in Relation to Wafer Breakage

    Science.gov (United States)

    Kulshreshtha, Prashant Kumar

    This thesis focuses on the fundamental understanding of stress-modified crack-propagation in photovoltaic (PV) silicon in relation to the critical issue of PV silicon "wafer breakage". The interactions between a propagating crack and impurities/defects/residual stresses have been evaluated for consequential fracture path in a thin PV Si wafer. To investigate the mechanism of brittle fracture in silicon, the phase transformations induced by elastic energy released at a propagating crack-tip have been evaluated by locally stressing the diamond cubic Si lattice using a rigid Berkovich nanoindenter tip (radius ≈50 nm). Unique pressure induced phase transformations and hardness variations have been then related to the distribution of precipitates (O, Cu, Fe etc.), and the local stresses in the wafer. This research demonstrates for the first time the "ductile-like fracture" in almost circular crack path that significantly deviates from its energetically favorable crystallographic [110](111) system. These large diameter (≈ 200 mm) Si wafers were sliced to less than 180 microm thickness from a Czochralski (CZ) ingot that was grown at faster than normal growth rates. The vacancy (vSi) driven precipitation of oxygen at enhanced thermal gradients in the wafer core develops large localized stresses (upto 100 MPa) which we evaluated using Raman spectral analysis. Additional micro-FTIR mapping and microscopic etch pit measurements in the wafer core have related the observed crack path deviations to the presence of concentric ring-like distributions of oxygen precipitates (OPs). To replicate these "real-world" breakage scenarios and provide better insight on crack-propagation, several new and innovative tools/devices/methods have been developed in this study. An accurate quantitative profiling of local stress, phase changes and load-carrying ability of Si lattice has been performed in the vicinity of the controlled micro-cracks created using micro-indentations to represent

  11. Wiping frictional properties of electrospun hydrophobic/hydrophilic polyurethane nanofiber-webs on soda-lime glass and silicon-wafer.

    Science.gov (United States)

    Watanabe, Kei; Wei, Kai; Nakashima, Ryu; Kim, Ick Soo; Enomoto, Yuji

    2013-04-01

    In the present work, we conducted the frictional tests of hydrophobic and hydrophilic polyurethane (PUo and PUi) nanofiber webs against engineering materials; soda-lime glass and silicon wafer. PUi/glass combination, with highest hydrophilicity, showed the highest friction coefficient which decrease with the increase of the applied load. Furthermore, the effects of fluorine coating are also investigated. The friction coefficient of fluorine coated hydrophobic PU nanofiber (PUof) shows great decrease against the silicon wafer. Finally, wiping ability and friction property are investigated when the substrate surface is contaminated. Nano-particle dusts are effectively collected into the pores by wiping with PUo and PUi nanofiber webs both on glass and silicon wafer. The friction coefficient gradually increased with the increase of the applied load.

  12. Magnetron target designs to improve wafer edge trench filling in ionized metal physical vapor deposition

    International Nuclear Information System (INIS)

    Lu Junqing; Yoon, Jae-Hong; Shin, Keesam; Park, Bong-Gyu; Yang Lin

    2006-01-01

    Severe asymmetry of the metal deposits on the trench sidewalls occurs near the wafer edge during low pressure ionized metal physical vapor deposition of Cu seed layer for microprocessor interconnects. To investigate this process and mitigate the asymmetry, an analytical view factor model based on the analogy between metal sputtering and diffuse thermal radiation was constructed. The model was validated based on the agreement between the model predictions and the reported experimental values for the asymmetric metal deposition at trench sidewalls near the wafer edge for a 200 mm wafer. This model could predict the thickness of the metal deposits across the wafer, the symmetry of the deposits on the trench sidewalls at any wafer location, and the angular distributions of the metal fluxes arriving at any wafer location. The model predictions for the 300 mm wafer indicate that as the target-to-wafer distance is shortened, the deposit thickness increases and the asymmetry decreases, however the overall uniformity decreases. Up to reasonable limits, increasing the target size and the sputtering intensity for the outer target portion significantly improves the uniformity across the wafer and the symmetry on the trench sidewalls near the wafer edge

  13. Impact of SiO2 on Al–Al thermocompression wafer bonding

    International Nuclear Information System (INIS)

    Malik, Nishant; Finstad, Terje G; Schjølberg-Henriksen, Kari; Poppe, Erik U; Taklo, Maaike M V

    2015-01-01

    Al–Al thermocompression bonding suitable for wafer level sealing of MEMS devices has been investigated. This paper presents a comparison of thermocompression bonding of Al films deposited on Si with and without a thermal oxide (SiO 2 film). Laminates of diameter 150 mm containing device sealing frames of width 200 µm were realized. The wafers were bonded by applying a bond force of 36 or 60 kN at bonding temperatures ranging from 300–550 °C for bonding times of 15, 30 or 60 min. The effects of these process variations on the quality of the bonded laminates have been studied. The bond quality was estimated by measurements of dicing yield, tensile strength, amount of cohesive fracture in Si and interfacial characterization. The mean bond strength of the tested structures ranged from 18–61 MPa. The laminates with an SiO 2 film had higher dicing yield and bond strength than the laminates without SiO 2 for a 400 °C bonding temperature. The bond strength increased with increasing bonding temperature and bond force. The laminates bonded for 30 and 60 min at 400 °C and 60 kN had similar bond strength and amount of cohesive fracture in the bulk silicon, while the laminates bonded for 15 min had significantly lower bond strength and amount of cohesive fracture in the bulk silicon. (paper)

  14. A study of UO2 wafer fuel for very high-power research reactors

    International Nuclear Information System (INIS)

    Hsieh, T.C.; Jankus, V.Z.; Rest, J.; Billone, M.C.

    1983-01-01

    The Reduced Enrichment Research and Test Reactor Program is aimed at reducing fuel enrichment to 2 caramel fuel is one of the most promising new types of reduced-enrichment fuel for use in research reactors with very high power density. Parametric studies have been carried out to determine the maximum specific power attainable without significant fission-gas release for UO 2 wafers ranging from 0.75 to 1.50 mm in thickness. The results indicate that (1) all the fuel designs considered in this study are predicted not to fail under full power operation up to a burnup, of 1.9x10 21 fis/cm 3 ; (2) for all fuel designs, failure is predicted at approximately the same fuel centerline temperature for a given burnup; (3) the thinner the wafer, the wider the margin for fuel specific power between normal operation and increased-power operation leading to fuel failure; (4) increasing the coolant pressure in the reactor core could improve fuel performance by maintaining the fuel at a higher power level without failure for a given burnup; and (5) for a given power level, fuel failure will occur earlier at a higher cladding surface temperature and/or under power-cycling conditions. (author)

  15. Petiroc and Citiroc: front-end ASICs for SiPM read-out and ToF applications

    International Nuclear Information System (INIS)

    Fleury, J; Ahmad, S; Callier, S; Taille, C de La; Seguin, N; Thienpont, D; Dulucq, F; Martin, G

    2014-01-01

    Petiroc and Citiroc are the two latest ASIC from Weeroc dedicated to SiPM read-out. Petiroc is a 16-channel front-end ASIC designed to readout silicon photomultipliers (SiPMs) for particle time-of-flight measurement applications. It combines a very fast and low-jitter trigger with an accurate charge measurement. Citiroc is a 32-channel front-end ASIC designed to readout silicon photo-multipliers (SiPM). It allows triggering down to 1/3 pe and provides the charge measurement with a good noise rejection. Moreover, Citiroc outputs the 32-channel triggers with a high accuracy (100 ps). Each channel of both ASICs combines a trigger path with an accurate charge measurement path. An adjustment of the SiPM high voltage is possible using a channel-by-channel input DAC. That allows a fine SiPM gain and dark noise adjustment at the system level to correct for the non-uniformity of SiPMs. Timing measurement down to 16 ps RMS jitter for Petiroc and 100 ps RMS for Citiroc is possible along with 1% linearity energy measurement up to 2500 pe. The power consumption is around 3.5 mW/channel for Petiroc and 3 mW/channel for Citiroc, excluding ASICs outing buffer

  16. Characterisation of a human acid-sensing ion channel (hASIC1a) endogenously expressed in HEK293 cells.

    Science.gov (United States)

    Gunthorpe, M J; Smith, G D; Davis, J B; Randall, A D

    2001-08-01

    Acid-sensing ion channels (ASICs) are a new and expanding family of proton-gated cation (Na+/Ca2+) channels that are widely expressed in sensory neurons and the central nervous system. Their distribution suggests that they may play a critical role in the sensation of the pain that accompanies tissue acidosis and may also be important in detecting the subtle pH variations that occur during neuronal signalling. Here, using whole-cell patch-clamp electrophysiology and reverse transcriptase-polymerase chain reaction (RT-PCR), we show that HEK293 cells, a commonly used cell line for the expression and characterisation of many ion channels, functionally express an endogenous proton-gated conductance attributable to the activity of human ASIC1a. These data therefore represent the first functional characterisation of hASIC1 and have many important implications for the use of HEK293 cells as a host cell system for the study of ASICs, vanilloid receptor-1 and any other proton-gated channel. With this latter point in mind we have devised a simple desensitisation strategy to selectively remove the contribution of hASIC1a from proton-gated currents recorded from HEK293 cells expressing vanilloid receptor-1.

  17. Sputtered Encapsulation as Wafer Level Packaging for Isolatable MEMS Devices: A Technique Demonstrated on a Capacitive Accelerometer

    Directory of Open Access Journals (Sweden)

    Azrul Azlan Hamzah

    2008-11-01

    Full Text Available This paper discusses sputtered silicon encapsulation as a wafer level packaging approach for isolatable MEMS devices. Devices such as accelerometers, RF switches, inductors, and filters that do not require interaction with the surroundings to function, could thus be fully encapsulated at the wafer level after fabrication. A MEMSTech 50g capacitive accelerometer was used to demonstrate a sputtered encapsulation technique. Encapsulation with a very uniform surface profile was achieved using spin-on glass (SOG as a sacrificial layer, SU-8 as base layer, RF sputtered silicon as main structural layer, eutectic gold-silicon as seal layer, and liquid crystal polymer (LCP as outer encapsulant layer. SEM inspection and capacitance test indicated that the movable elements were released after encapsulation. Nanoindentation test confirmed that the encapsulated device is sufficiently robust to withstand a transfer molding process. Thus, an encapsulation technique that is robust, CMOS compatible, and economical has been successfully developed for packaging isolatable MEMS devices at the wafer level.

  18. Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

    Science.gov (United States)

    Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

    2008-10-01

    This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

  19. Architecture of a general purpose embedded Slow-Control Adapter ASIC for future high-energy physics experiments

    International Nuclear Information System (INIS)

    Gabrielli, Alessandro; Loddo, Flavio; Ranieri, Antonio; De Robertis, Giuseppe

    2008-01-01

    This work is aimed at defining the architecture of a new digital ASIC, namely Slow-Control Adapter (SCA), which will be designed in a commercial 130-nm CMOS technology. This chip will be embedded within a high-speed data acquisition optical link (GBT) to control and monitor the front-end electronics in future high-energy physics experiments. The GBT link provides a transparent transport layer between the SCA and control electronics in the counting room. The proposed SCA supports a variety of common bus protocols to interface with end-user general-purpose electronics. Between the GBT and the SCA a standard 100 Mb/s IEEE-802.3 compatible protocol will be implemented. This standard protocol allows off-line tests of the prototypes using commercial components that support the same standard. The project is justified because embedded applications in modern large HEP experiments require particular care to assure the lowest possible power consumption, still offering the highest reliability demanded by very large particle detectors.

  20. Experimental characterization of the 192 channel Clear-PEM frontend ASIC coupled to a multi-pixel APD readout of LYSO:Ce crystals

    International Nuclear Information System (INIS)

    Albuquerque, Edgar; Bexiga, Vasco; Bugalho, Ricardo; Carrico, Bruno; Ferreira, Claudia S.; Ferreira, Miguel; Godinho, Joaquim; Goncalves, Fernando; Leong, Carlos; Lousa, Pedro; Machado, Pedro; Moura, Rui; Neves, Pedro; Ortigao, Catarina; Piedade, Fernando; Pinheiro, Joao F.; Rego, Joel; Rivetti, Angelo; Rodrigues, Pedro; Silva, Jose C.

    2009-01-01

    In the framework of the Clear-PEM project for the construction of a high-resolution scanner for breast cancer imaging, a very compact and dense frontend electronics system has been developed for readout of multi-pixel S8550 Hamamatsu APDs. The frontend electronics are instrumented with a mixed-signal Application-Specific Integrated Circuit (ASIC), which incorporates 192 low-noise charge pre-amplifiers, shapers, analog memory cells and digital control blocks. Pulses are continuously stored in memory cells at clock frequency. Channels above a common threshold voltage are readout for digitization by off-chip free-sampling ADCs. The ASIC has a size of 7.3x9.8mm 2 and was implemented in a AMS 0.35μm CMOS technology. In this paper the experimental characterization of the Clear-PEM frontend ASIC, reading out multi-pixel APDs coupled to LYSO:Ce crystal matrices, is presented. The chips were mounted on a custom test board connected to six APD arrays and to the data acquisition system. Six 32-pixel LYSO:Ce crystal matrices coupled on both sides to APD arrays were readout by two test boards. All 384 channels were operational. The chip power consumption is 660 mW (3.4 mW per channel). A very stable behavior of the chip was observed, with an estimated ENC of 1200-1300e - at APD gain 100. The inter-channel noise dispersion and mean baseline variation is less than 8% and 0.5%, respectively. The spread in the gain between different channels is found to be 1.5%. Energy resolution of 16.5% at 511 keV and 12.8% at 662 keV has been measured. Timing measurements between the two APDs that readout the same crystal is extracted and compared with detailed Monte Carlo simulations. At 511 keV the measured single photon time RMS resolution is 1.30 ns, in very good agreement with the expected value of 1.34 ns.

  1. Wafer-level manufacturing technology of glass microlenses

    Science.gov (United States)

    Gossner, U.; Hoeftmann, T.; Wieland, R.; Hansch, W.

    2014-08-01

    In high-tech products, there is an increasing demand to integrate glass lenses into complex micro systems. Especially in the lighting industry LEDs and laser diodes used for automotive applications require encapsulated micro lenses. To enable low-cost production, manufacturing of micro lenses on wafer level base using a replication technology is a key technology. This requires accurate forming of thousands of lenses with a diameter of 1-2 mm on a 200 mm wafer compliant with mass production. The article will discuss the technical aspects of a lens manufacturing replication process and the challenges, which need to be solved: choice of an appropriate master for replication, thermally robust interlayer coating, choice of replica glass, bonding and separation procedure. A promising approach for the master substrate material is based on a lens structured high-quality glass wafer with high melting point covered by a coating layer of amorphous silicon or germanium. This layer serves as an interlayer for the glass bonding process. Low pressure chemical vapor deposition and plasma enhanced chemical vapor deposition processes allow a deposition of layer coatings with different hydrogen and doping content influencing their chemical and physical behavior. A time reduced molding process using a float glass enables the formation of high quality lenses while preserving the recyclability of the mother substrate. The challenge is the separation of the replica from the master mold. An overview of chemical methods based on optimized etching of coating layer through small channels will be given and the impact of glass etching on surface roughness is discussed.

  2. Study of Si wafer surfaces irradiated by gas cluster ion beams

    International Nuclear Information System (INIS)

    Isogai, H.; Toyoda, E.; Senda, T.; Izunome, K.; Kashima, K.; Toyoda, N.; Yamada, I.

    2007-01-01

    The surface structures of Si (1 0 0) wafers subjected to gas cluster ion beam (GCIB) irradiation have been analyzed by cross-sectional transmission electron microscopy (XTEM) and atomic force microscopy (AFM). GCIB irradiation is a promising technique for both precise surface etching and planarization of Si wafers. However, it is very important to understand the crystalline structure of Si wafers after GCIB irradiation. An Ar-GCIB used for the physically sputtering of Si atoms and a SF 6 -GCIB used for the chemical etching of the Si surface are also analyzed. The GCIB irradiation increases the surface roughness of the wafers, and amorphous Si layers are formed on the wafer surface. However, when the Si wafers are annealed in hydrogen at a high temperature after the GCIB irradiation, the surface roughness decreases to the same level as that before the irradiation. Moreover, the amorphous Si layers disappear completely

  3. Underling modification in ion beam induced Si wafers

    International Nuclear Information System (INIS)

    Hazra, S.; Chini, T.K.; Sanyal, M.K.; Grenzer, J.; Pietsch, U.

    2005-01-01

    Subsurface (amorphous-crystalline interface) structure of keV ion beam modified Si(001) wafers was studied for the first time using non-destructive technique and compared with that of the top one. Ion-beam modifications of the Si samples were done using state-of-art high-current ion implanter facility at Saha Institute of Nuclear Physics by changing energy, dose and angle of incidence of the Ar + ion beam. To bring out the underlying modification depth-resolved x-ray grazing incidence diffraction has been carried out using synchrotron radiation facility, while the structure of the top surface was studied through atomic force microscopy

  4. Automotive SOI-BCD Technology Using Bonded Wafers

    International Nuclear Information System (INIS)

    Himi, H.; Fujino, S.

    2008-01-01

    The SOI-BCD device is excelling in high temperature operation and noise immunity because the integrated elements can be electrically separated by dielectric isolation. We have promptly paid attention to this feature and have concentrated to develop SOI-BCD devices seeking to match the automotive requirement. In this paper, the feature technologies specialized for automotive SOI-BCD devices, such as buried N + layer for impurity gettering and noise shielding, LDMOS with improved ESD robustness, crystal defect-less process, and wafer direct bonding through the amorphous layer for intelligent power IC are introduced.

  5. A 58 nW ECG ASIC With Motion-Tolerant Heartbeat Timing Extraction for Wearable Cardiovascular Monitoring.

    Science.gov (United States)

    Da He, David; Sodini, Charles G

    2015-06-01

    An ASIC for wearable cardiovascular monitoring is implemented using a topology that takes advantage of the electrocardiogram's (ECG) waveform to replace the traditional ECG instrumentation amplifier, ADC, and signal processor with a single chip solution. The ASIC can extract heartbeat timings in the presence of baseline drift, muscle artifact, and signal clipping. The circuit can operate with ECGs ranging from the chest location to remote locations where the ECG magnitude is as low as 30 μV. Besides heartbeat detection, a midpoint estimation method can accurately extract the ECG R-wave timing, enabling the calculations of heart rate variability. With 58 nW of power consumption at 0.8 V supply voltage and 0.76 mm (2) of active die area in standard 0.18 μm CMOS technology, the ECG ASIC is sufficiently low power and compact to be suitable for long term and wearable cardiovascular monitoring applications under stringent battery and size constraints.

  6. A 9-Channel, 100 ps LSB Time-to-Digital Converter for the NA62 Gigatracker Readout ASIC (TDCpix)

    International Nuclear Information System (INIS)

    Perktold, L; Rinella, G Aglieri; Noy, M; Kluge, A; Kloukinas, K; Kaplon, J; Jarron, P; Morel, M; Fiorini, M; Martin, E

    2012-01-01

    The TDCpix ASIC is the readout chip for the Gigatracker station of the NA62 experiment. Each station of the Gigatracker needs to provide time stamping of individual particles to 200 ps-rms or better. Bump-bonded to the pixel sensor the ASIC serves an array of 40 columns x 40 pixels. The high precision time measurement of the discriminated hit signals is accomplished with a set of 40 TDCs sitting in the End-Of-Column region of the ASIC. Each TDC provides 9 channels per column. For the time-to-digital converter (TDC) a delay-locked-loop (DLL) approach is employed to achieve a constant time binning of 100 ps. Simulation results show that an average rms time resolution of 33 ps with a power consumption of the TDC better than 33 mW per column is achieved. This contribution will present the design, simulation results and implementation challenges of the TDC.

  7. Improved On-Chip Measurement of Delay in an FPGA or ASIC

    Science.gov (United States)

    Chen, Yuan; Burke, Gary; Sheldon, Douglas

    2007-01-01

    An improved design has been devised for on-chip-circuitry for measuring the delay through a chain of combinational logic elements in a field-programmable gate array (FPGA) or application-specific integrated circuit (ASIC). In the improved design, the delay chain does not include input and output buffers and is not configured as an oscillator. Instead, the delay chain is made part of the signal chain of an on-chip pulse generator. The duration of the pulse is measured on-chip and taken to equal the delay.

  8. A front-end ASIC for ionising radiation monitoring with femto-amp capabilities

    International Nuclear Information System (INIS)

    Voulgari, E.; Noy, M.; Anghinolfi, F.; Perrin, D.; Krummenacher, F.; Kayal, M.

    2016-01-01

    An ultra-low leakage current Application Specific Integrated Circuit (ASIC) called Utopia (Ultralow Picoammeter) has been designed and fabricated in AMS 0.35 μm CMOS, in order to be used as the front-end for ionising radiation monitoring at CERN. It is based on the topology of a Current to Frequency Converter (CFC) through charge balancing and demonstrates a wide dynamic range of 8.5 decades without range changing. Due to a design aimed at minimising input leakage currents, input currents as low as 01 fA can be measured

  9. Transmitting Performance Evaluation of ASICs for CMUT-Based Portable Ultrasound Scanners

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Diederichsen, Søren Elmin; Jørgensen, Ivan Harald Holger

    2017-01-01

    Portable ultrasound scanners (PUS) have, in recent years, raised a lot of attention, as they can potentially overcome some of the limitations of static scanners. However, PUS have a lot of design limitations including size and power consumption. These restrictions can compromise the image quality...... of the scanner. In order to overcome these restrictions, application specific integrated circuits (ASICs) are needed to implement the electronics. In this work, a comparative study of the transmitting performance of a capacitive micromachined ultrasonic transducer (CMUT) driven by a commercial generic ultrasound...

  10. The development of two ASIC's for a fast silicon strip detector readout system

    International Nuclear Information System (INIS)

    Christain, D.; Haldeman, M.; Yarema, R.; Zimmerman, T.; Newcomer, F.M.; VanBerg, R.

    1989-01-01

    A high speed, low noise readout system for silicon strip detectors is being developed for Fermilab E771, which will begin taking data in 1989. E771 is a fixed target experiment designed to study the production of B hadrons by an 800 GeV/c proton beam. The experimental apparatus consists of an open geometry magnetic spectrometer featuring good muon and electron identification and a 16000 channel silicon microstrip vertex detector. This paper reviews the design and prototyping of two application specific integrated circuits (ASIC's) an amplifier and a discriminator, which are being produced for the silicon strip detector readout system

  11. Development and validation of a general-purpose ASIC chip for the control of switched reluctance machines

    International Nuclear Information System (INIS)

    Chen Haijin; Lu Shengli; Shi Longxing

    2009-01-01

    A general-purpose application specific integrated circuit (ASIC) chip for the control of switched reluctance machines (SRMs) was designed and validated to fill the gap between the microcontroller capability and the controller requirements of high performance switched reluctance drive (SRD) systems. It can be used for the control of SRM running either in low speed or in high-speed, i.e., either in chopped current control (CCC) mode or in angular position control (APC) mode. Main functions of the chip include filtering and cycle calculation of rotor angular position signals, commutation logic according to rotor cycle and turn-on/turn-off angles (θ on /θ off ), controllable pulse width modulation (PWM) waveforms generation, chopping control with adjustable delay time, and commutation control with adjustable delay time. All the control parameters of the chip are set online by the microcontroller through a serial peripheral interface (SPI). The chip has been designed with the standard cell based design methodology, and implemented in the central semiconductor manufacturing corporation (CSMC) 0.5 μm complementary metal-oxide-semiconductor (CMOS) process technology. After a successful automatic test equipment (ATE) test using the Nextest's Maverick test system, the chip was further validated through an experimental three-phase 6/2-pole SRD system. Both the ATE test and experimental validation results show that the chip can meet the control requirements of high performance SRD systems, and simplify the controller construction. For a resolution of 0.36 deg. (electrical degree), the chip's maximum processable frequency of the rotor angular position signals is 10 kHz, which is 300,000 rev/min when a three-phase 6/2-pole SRM is concerned

  12. High-density expression of Ca2+-permeable ASIC1a channels in NG2 glia of rat hippocampus.

    Directory of Open Access Journals (Sweden)

    Yen-Chu Lin

    Full Text Available NG2 cells, a fourth type of glial cell in the mammalian CNS, undergo reactive changes in response to a wide variety of brain insults. Recent studies have demonstrated that neuronally expressed acid-sensing ion channels (ASICs are implicated in various neurological disorders including brain ischemia and seizures. Acidosis is a common feature of acute neurological conditions. It is postulated that a drop in pH may be the link between the pathological process and activation of NG2 cells. Such postulate immediately prompts the following questions: Do NG2 cells express ASICs? If so, what are their functional properties and subunit composition? Here, using a combination of electrophysiology, Ca2+ imaging and immunocytochemistry, we present evidence to demonstrate that NG2 cells of the rat hippocampus express high density of Ca2+-permeable ASIC1a channels compared with several types of hippocampal neurons. First, nucleated patch recordings from NG2 cells revealed high density of proton-activated currents. The magnitude of proton-activated current was pH dependent, with a pH for half-maximal activation of 6.3. Second, the current-voltage relationship showed a reversal close to the equilibrium potential for Na+. Third, psalmotoxin 1, a blocker specific for the ASIC1a channel, largely inhibited proton-activated currents. Fourth, Ca2+ imaging showed that activation of proton-activated channels led to an increase of [Ca2+]i. Finally, immunocytochemistry showed co-localization of ASIC1a and NG2 proteins in the hippocampus. Thus the acid chemosensor, the ASIC1a channel, may serve for inducing membrane depolarization and Ca2+ influx, thereby playing a crucial role in the NG2 cell response to injury following ischemia.

  13. Determination of wafer center position during the transfer process by using the beam-breaking method

    International Nuclear Information System (INIS)

    Chen, Yi-Cheng; Wang, Zhi-Gen; Huang, Bo-Kai

    2014-01-01

    A wafer on a robot blade may slip due to inertia sliding during the acceleration or deceleration process. This study presents the implementation and experimental verification of a novel real-time wafer positioning system to be used during the transfer process. A system-integration computer program involving a human–machine interface (HMI) was also developed, exhibiting the following functions: (a) moving direction judgment; (b) notch-passing judgment; (c) indicating the sensor by which the notch passes; and (d) computing the wafer center in real time. The position of the wafer center is calculated based on the time-sequence of the beam-breaking signals from two optical sensors, and the geometric relations among the sensing points of the robot blade and wafer. When using eight-inch wafers, the experimental results indicated the capabilities of the proposed positioning system under various conditions, including distinct parameters regarding the moving direction, wafer displacement and notch-passing sensors. The accuracy and precision (repeatability) of the measurement in various conditions were calculated and discussed. Furthermore, the experimental results demonstrate that, after combining the novel wafer positioning system and HMI program, the proposed method can be used to compute the position of the wafer center in real time in various conditions. (paper)

  14. Off-line wafer level reliability control: unique measurement method to monitor the lifetime indicator of gate oxide validated within bipolar/CMOS/DMOS technology

    Science.gov (United States)

    Gagnard, Xavier; Bonnaud, Olivier

    2000-08-01

    We have recently published a paper on a new rapid method for the determination of the lifetime of the gate oxide involved in a Bipolar/CMOS/DMOS technology (BCD). Because this previous method was based on a current measurement with gate voltage as a parameter needing several stress voltages, it was applied only by lot sampling. Thus, we tried to find an indicator in order to monitor the gate oxide lifetime during the wafer level parametric test and involving only one measurement of the device on each wafer test cell. Using the Weibull law and Crook model, combined with our recent model, we have developed a new test method needing only one electrical measurement of MOS capacitor to monitor the quality of the gate oxide. Based also on a current measurement, the parameter is the lifetime indicator of the gate oxide. From the analysis of several wafers, we gave evidence of the possibility to detect a low performance wafer, which corresponds to the infantile failure on the Weibull plot. In order to insert this new method in the BCD parametric program, a parametric flowchart was established. This type of measurement is an important challenges, because the actual measurements, breakdown charge, Qbd, and breakdown electric field, Ebd, at parametric level and Ebd and interface states density, Dit during the process cannot guarantee the gate oxide lifetime all along fabrication process. This indicator measurement is the only one, which predicts the lifetime decrease.

  15. Control of cavitation using dissolved carbon dioxide for damage-free megasonic cleaning of wafers

    Science.gov (United States)

    Kumari, Sangita

    This dissertation describes the finding that dissolved carbon dioxide is a potent inhibitor of sonoluminescence and describes the implications of the finding in the development of improved megasonic cleaning formulations. Megasonic cleaning, or the removal of contaminants particles from wafer surfaces using sound-irradiated cleaning fluids, has been traditionally used in the semiconductor industry for cleaning of wafers. A critical challenge in the field is to achieve removal of small particles (22 nm to 200 nm) without causing damage to fine wafer features. The work described here addresses this challenge by identifying sonoluminescence and solution pH as two key factors affecting damage and cleaning efficiency, respectively and establishing novel means to control them using CO2(aq) release compounds in the presence of acids and bases. Sonoluminescence (SL) behavior of the major dissolved gases such as Ar, Air, N2, O2 and CO2 was determined using a newly designed Cavitation Threshold Cell (CT Cell). SL, which is the phenomenon of release of light in sound-irradiated liquids, is a sensitive indicator of cavitation, primarily transient cavitation. It was found that all the tested dissolved gases such as Ar, Air, N2 and O2, generated SL signal efficiently. However, dissolved CO2 was found to be completely incapable of generating SL signal. Based on this interesting result, gradual suppression of SL signal was demonstrated using CO2(aq). It was further demonstrated that CO2(aq) is not only incapable but is also a potent inhibitor of SL. The inhibitory role of CO2(aq) was established using a novel method of controlled in-situ release of CO 2 from NH4HCO3. ~130 ppm CO2(aq) was shown to be necessary and sufficient for complete suppression of SL generation in air saturated DI water. The method however required acidification of solution for significant release of CO2, making it unsuitable for the design of cleaning solutions at high pH. Analysis of the underlying ionic

  16. Tracker Readout ASIC for Proton Computed Tomography Data Acquisition.

    Science.gov (United States)

    Johnson, Robert P; Dewitt, Joel; Holcomb, Cole; Macafee, Scott; Sadrozinski, Hartmut F-W; Steinberg, David

    2013-10-01

    A unique CMOS chip has been designed to serve as the front-end of the tracking detector data acquisition system of a pre-clinical prototype scanner for proton computed tomography (pCT). The scanner is to be capable of measuring one to two million proton tracks per second, so the chip must be able to digitize the data and send it out rapidly while keeping the front-end amplifiers active at all times. One chip handles 64 consecutive channels, including logic for control, calibration, triggering, buffering, and zero suppression. It outputs a formatted cluster list for each trigger, and a set of field programmable gate arrays merges those lists from many chips to build the events to be sent to the data acquisition computer. The chip design has been fabricated, and subsequent tests have demonstrated that it meets all of its performance requirements, including excellent low-noise performance.

  17. Hydrogen Incorporation during Aluminium Anodisation on Silicon Wafer Surfaces

    International Nuclear Information System (INIS)

    Lu, Pei Hsuan Doris; Strutzberg, Hartmuth; Wenham, Stuart; Lennon, Alison

    2014-01-01

    Hydrogen can act to reduce recombination at silicon surfaces for solar cell devices and consequently the ability of dielectric layers to provide a source of hydrogen for this purpose is of interest. However, due to the ubiquitous nature of hydrogen and its mobility, direct measurements of hydrogen incorporation in dielectric layers are challenging. In this paper, we report the use of secondary ion mass spectrometry measurements to show that deuterium from an electrolyte can be incorporated in an anodic aluminium oxide (AAO) layer and be introduced into an underlying amorphous silicon layer during anodisation of aluminium on silicon wafers. After annealing at 400 °C, the concentration of deuterium in the AAO was reduced by a factor of two, as the deuterium was re-distributed to the interface between the amorphous silicon and AAO and to the amorphous silicon. The assumption that hydrogen, from an aqueous electrolyte, could be similarly incorporated in AAO, is supported by the observation that the hydrogen content in the underlying amorphous silicon was increased by a factor of ∼ 3 after anodisation. Evidence for hydrogen being introduced into crystalline silicon after aluminium anodisation was provided by electrochemical capacitance voltage measurements indicating boron electrical deactivation in the underlying crystalline silicon. If introduced hydrogen can electrically deactivate dopant atoms at the surface, then it is reasonable to assume that it could also deactivate recombination-active states at the crystalline silicon interface therefore enabling higher minority carrier lifetimes in the silicon wafer

  18. Residual stress in silicon wafer using IR polariscope

    Science.gov (United States)

    Lu, Zhijia; Wang, Pin; Asundi, Anand

    2008-09-01

    The infrared phase shift polariscope (IR-PSP) is a full-field optical technique for stress analysis in Silicon wafers. Phase shift polariscope is preferred to a conventional polariscope, as it can provide quantitative information of the normal stress difference and the shear stress in the specimen. The method is based on the principles of photoelasticity, in which stresses induces temporary birefringence in materials which can be quantitatively analyzed using a phase shift polariscope. Compared to other stress analysis techniques such as x-ray diffraction or laser scanning, infrared photoelastic stress analysis provides full-field information with high resolution and in near real time. As the semiconductor fabrication is advancing, larger wafers, thinner films and more compact packages are being manufactured. This results in a growing demand of process control. Residual stress exist in silicon during semiconductor fabrication and these stresses may make cell processing difficult or even cause the failure of the silicon. Reducing these stresses would improve manufacturability and reliability. Therefore stress analysis is essential to trace the root cause of the stresses. The polariscope images are processed using MATLAB and four-step phase shifting method to provide quantitative as well as qualitative information regarding the residual stress of the sample. The system is calibrated using four-point bend specimen and then the residual stress distribution in a MEMS sample is shown.

  19. Improving scanner wafer alignment performance by target optimization

    Science.gov (United States)

    Leray, Philippe; Jehoul, Christiane; Socha, Robert; Menchtchikov, Boris; Raghunathan, Sudhar; Kent, Eric; Schoonewelle, Hielke; Tinnemans, Patrick; Tuffy, Paul; Belen, Jun; Wise, Rich

    2016-03-01

    In the process nodes of 10nm and below, the patterning complexity along with the processing and materials required has resulted in a need to optimize alignment targets in order to achieve the required precision, accuracy and throughput performance. Recent industry publications on the metrology target optimization process have shown a move from the expensive and time consuming empirical methodologies, towards a faster computational approach. ASML's Design for Control (D4C) application, which is currently used to optimize YieldStar diffraction based overlay (DBO) metrology targets, has been extended to support the optimization of scanner wafer alignment targets. This allows the necessary process information and design methodology, used for DBO target designs, to be leveraged for the optimization of alignment targets. In this paper, we show how we applied this computational approach to wafer alignment target design. We verify the correlation between predictions and measurements for the key alignment performance metrics and finally show the potential alignment and overlay performance improvements that an optimized alignment target could achieve.

  20. Conformational dynamics and role of the acidic pocket in ASIC pH-dependent gating.

    Science.gov (United States)

    Vullo, Sabrina; Bonifacio, Gaetano; Roy, Sophie; Johner, Niklaus; Bernèche, Simon; Kellenberger, Stephan

    2017-04-04

    Acid-sensing ion channels (ASICs) are proton-activated Na + channels expressed in the nervous system, where they are involved in learning, fear behaviors, neurodegeneration, and pain sensation. In this work, we study the role in pH sensing of two regions of the ectodomain enriched in acidic residues: the acidic pocket, which faces the outside of the protein and is the binding site of several animal toxins, and the palm, a central channel domain. Using voltage clamp fluorometry, we find that the acidic pocket undergoes conformational changes during both activation and desensitization. Concurrently, we find that, although proton sensing in the acidic pocket is not required for channel function, it does contribute to both activation and desensitization. Furthermore, protonation-mimicking mutations of acidic residues in the palm induce a dramatic acceleration of desensitization followed by the appearance of a sustained current. In summary, this work describes the roles of potential pH sensors in two extracellular domains, and it proposes a model of acidification-induced conformational changes occurring in the acidic pocket of ASIC1a.