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Sample records for applying fpga partial

  1. Partial reconfiguration of concurrent logic controllers implemented in FPGA devices

    Science.gov (United States)

    Wiśniewski, Remigiusz; Grobelna, Iwona; Stefanowicz, Łukasz

    2016-12-01

    Reconfigurable systems are recently used in many domains. Although the concept of multi-context logic controllers is relatively new, it may be noticed that the subject is receiving a lot of attention, especially in the industry. The work constitutes a stepping stone in design of reconfigurable logic controllers implemented in an FPGA device. An approach of designing of logic controllers oriented for further partial reconfiguration is proposed. A case study of a milling machine is used for an illustration.

  2. Applied partial differential equations

    CERN Document Server

    Logan, J David

    2004-01-01

    This primer on elementary partial differential equations presents the standard material usually covered in a one-semester, undergraduate course on boundary value problems and PDEs. What makes this book unique is that it is a brief treatment, yet it covers all the major ideas: the wave equation, the diffusion equation, the Laplace equation, and the advection equation on bounded and unbounded domains. Methods include eigenfunction expansions, integral transforms, and characteristics. Mathematical ideas are motivated from physical problems, and the exposition is presented in a concise style accessible to science and engineering students; emphasis is on motivation, concepts, methods, and interpretation, rather than formal theory. This second edition contains new and additional exercises, and it includes a new chapter on the applications of PDEs to biology: age structured models, pattern formation; epidemic wave fronts, and advection-diffusion processes. The student who reads through this book and solves many of t...

  3. Applied partial differential equations

    CERN Document Server

    Logan, J David

    2015-01-01

    This text presents the standard material usually covered in a one-semester, undergraduate course on boundary value problems and PDEs.  Emphasis is placed on motivation, concepts, methods, and interpretation, rather than on formal theory. The concise treatment of the subject is maintained in this third edition covering all the major ideas: the wave equation, the diffusion equation, the Laplace equation, and the advection equation on bounded and unbounded domains. Methods include eigenfunction expansions, integral transforms, and characteristics. In this third edition, text remains intimately tied to applications in heat transfer, wave motion, biological systems, and a variety other topics in pure and applied science. The text offers flexibility to instructors who, for example, may wish to insert topics from biology or numerical methods at any time in the course. The exposition is presented in a friendly, easy-to-read, style, with mathematical ideas motivated from physical problems. Many exercises and worked e...

  4. Power consumption reduction in a SDR based wireless communication system using partial reconfigurable FPGA

    Directory of Open Access Journals (Sweden)

    Neenu Joseph

    2012-04-01

    Full Text Available The increase in the consumer demand and the exponential growth for wireless systems, which enables consumer to communicate in any place by means of information, has in turn led to the emergence of many portable wireless communication products. The present research works primarily targets to integrate as much as signal processing applications in a single portable device. Since integration through software applications compromises system speed, integration through hardware will be the better compliment. Software Defined Radio (SDR Technology yields to achieve this small form factor system while keeping power consumption under the limit. SDR enables soft changeable system functionality, such as receiver demodulation technique .In this implementation two type modulation techniques are used, ASK and FSK. The flexibility of changing the receiver functionality in run time is usually attained by FPGA. However, using a complete FPGA for reconfiguration of a particular functionality is not an efficient method in terms of power consumption and switching time. We proposed a SDR architecture using a recent advancement in FPGAs, called Partial Reconfiguration (PR. PR helps to change certain portion of FPGA, while the rest keeps functioning. It also reduces the total hardware usage and hence the power. The different demodulation technique and other signal processing application from an external memory unit can be loaded into FPGA PR modules while the other parts of FPGA doing a constant data processing.

  5. A Controller for Dynamic Partial Reconfiguration in FPGA-Based Real-Time Systems

    DEFF Research Database (Denmark)

    Pezzarossa, Luca; Schoeberl, Martin; Sparsø, Jens

    2017-01-01

    In real-time systems, the use of hardware accelerators can lead to a worst-case execution-time speed-up, to a simplification of its analysis, and to a reduction of its pessimism. When using FPGA technology, dynamic partial reconfiguration (DPR) can be used to minimize the area, by only loading...... those accelerators that are needed at any given point in time. The DPR controllers provided by the FPGA vendors satisfy a wide range of requirements and rely on software to manage the reconfiguration. This approach may lead to slow reconfiguration and unpredictable timing. This paper presents an open....... The paper also presents a software tool for bitstream conversion, compression, and for reconfiguration time analysis. The DPR controller is evaluated in terms of hardware cost, operating frequency, speed, and bitstream compression ratio vs. reconfiguration time trade-off. A simple application example...

  6. Using Partial Reconfiguration and Message Passing to Enable FPGA-Based Generic Computing Platforms

    Directory of Open Access Journals (Sweden)

    Manuel Saldaña

    2012-01-01

    Full Text Available Partial reconfiguration (PR is an FPGA feature that allows the modification of certain parts of an FPGA while the rest of the system continues to operate without disruption. This distinctive characteristic of FPGAs has many potential benefits but also challenges. The lack of good CAD tools and the deep hardware knowledge requirement result in a hard-to-use feature. In this paper, the new partition-based Xilinx PR flow is used to incorporate PR within our MPI-based message-passing framework to allow hardware designers to create template bitstreams, which are predesigned, prerouted, generic bitstreams that can be reused for multiple applications. As an example of the generality of this approach, four different applications that use the same template bitstream are run consecutively, with a PR operation performed at the beginning of each application to instantiate the desired application engine. We demonstrate a simplified, reusable, high-level, and portable PR interface for X86-FPGA hybrid machines. PR issues such as local resets of reconfigurable modules and context saving and restoring are addressed in this paper followed by some examples and preliminary PR overhead measurements.

  7. Self-Partial and Dynamic Reconfiguration Implementation for AES using FPGA

    Directory of Open Access Journals (Sweden)

    Zine El Abidine Alaoui Ismaili

    2009-08-01

    Full Text Available This paper addresses efficient hardware/software implementation approaches for the AES (Advanced Encryption Standard algorithm and describes the design and performance testing algorithm for embedded system. Also, with the spread of reconfigurable hardware such as FPGAs (Field Programmable Gate Array embedded cryptographic hardware became cost-effective. Nevertheless, it is worthy to note that nowadays, even hardwired cryptographic algorithms are not so safe. From another side, the self-reconfiguring platform is reported that enables an FPGA to dynamically reconfigure itself under the control of an embedded microprocessor. Hardware acceleration significantly increases the performance of embedded systems built on programmable logic. Allowing a FPGA-based MicroBlaze processor to self-select the coprocessors uses can help reduce area requirements and increase a system's versatility. The architecture proposed in this paper is an optimal hardware implementation algorithm and takes dynamic partially reconfigurable of FPGA. This implementation is good solution to preserve confidentiality and accessibility to the information in the numeric communication.

  8. Dynamic partial reconfiguration implementation of the SVM/KNN multi-classifier on FPGA for bioinformatics application.

    Science.gov (United States)

    Hussain, Hanaa M; Benkrid, Khaled; Seker, Huseyin

    2015-01-01

    Bioinformatics data tend to be highly dimensional in nature thus impose significant computational demands. To resolve limitations of conventional computing methods, several alternative high performance computing solutions have been proposed by scientists such as Graphical Processing Units (GPUs) and Field Programmable Gate Arrays (FPGAs). The latter have shown to be efficient and high in performance. In recent years, FPGAs have been benefiting from dynamic partial reconfiguration (DPR) feature for adding flexibility to alter specific regions within the chip. This work proposes combing the use of FPGAs and DPR to build a dynamic multi-classifier architecture that can be used in processing bioinformatics data. In bioinformatics, applying different classification algorithms to the same dataset is desirable in order to obtain comparable, more reliable and consensus decision, but it can consume long time when performed on conventional PC. The DPR implementation of two common classifiers, namely support vector machines (SVMs) and K-nearest neighbor (KNN) are combined together to form a multi-classifier FPGA architecture which can utilize specific region of the FPGA to work as either SVM or KNN classifier. This multi-classifier DPR implementation achieved at least ~8x reduction in reconfiguration time over the single non-DPR classifier implementation, and occupied less space and hardware resources than having both classifiers. The proposed architecture can be extended to work as an ensemble classifier.

  9. Bio-Inspired Controller on an FPGA Applied to Closed-Loop Diaphragmatic Stimulation.

    Science.gov (United States)

    Zbrzeski, Adeline; Bornat, Yannick; Hillen, Brian; Siu, Ricardo; Abbas, James; Jung, Ranu; Renaud, Sylvie

    2016-01-01

    Cervical spinal cord injury can disrupt connections between the brain respiratory network and the respiratory muscles which can lead to partial or complete loss of ventilatory control and require ventilatory assistance. Unlike current open-loop technology, a closed-loop diaphragmatic pacing system could overcome the drawbacks of manual titration as well as respond to changing ventilation requirements. We present an original bio-inspired assistive technology for real-time ventilation assistance, implemented in a digital configurable Field Programmable Gate Array (FPGA). The bio-inspired controller, which is a spiking neural network (SNN) inspired by the medullary respiratory network, is as robust as a classic controller while having a flexible, low-power and low-cost hardware design. The system was simulated in MATLAB with FPGA-specific constraints and tested with a computational model of rat breathing; the model reproduced experimentally collected respiratory data in eupneic animals. The open-loop version of the bio-inspired controller was implemented on the FPGA. Electrical test bench characterizations confirmed the system functionality. Open and closed-loop paradigm simulations were simulated to test the FPGA system real-time behavior using the rat computational model. The closed-loop system monitors breathing and changes in respiratory demands to drive diaphragmatic stimulation. The simulated results inform future acute animal experiments and constitute the first step toward the development of a neuromorphic, adaptive, compact, low-power, implantable device. The bio-inspired hardware design optimizes the FPGA resource and time costs while harnessing the computational power of spike-based neuromorphic hardware. Its real-time feature makes it suitable for in vivo applications.

  10. FPGA Implementation of Real-Time Compressive Sensing with Partial Fourier Dictionary

    Directory of Open Access Journals (Sweden)

    Yinghui Quan

    2016-01-01

    Full Text Available This paper presents a novel real-time compressive sensing (CS reconstruction which employs high density field-programmable gate array (FPGA for hardware acceleration. Traditionally, CS can be implemented using a high-level computer language in a personal computer (PC or multicore platforms, such as graphics processing units (GPUs and Digital Signal Processors (DSPs. However, reconstruction algorithms are computing demanding and software implementation of these algorithms is extremely slow and power consuming. In this paper, the orthogonal matching pursuit (OMP algorithm is refined to solve the sparse decomposition optimization for partial Fourier dictionary, which is always adopted in radar imaging and detection application. OMP reconstruction can be divided into two main stages: optimization which finds the closely correlated vectors and least square problem. For large scale dictionary, the implementation of correlation is time consuming since it often requires a large number of matrix multiplications. Also solving the least square problem always needs a scalable matrix decomposition operation. To solve these problems efficiently, the correlation optimization is implemented by fast Fourier transform (FFT and the large scale least square problem is implemented by Conjugate Gradient (CG technique, respectively. The proposed method is verified by FPGA (Xilinx Virtex-7 XC7VX690T realization, revealing its effectiveness in real-time applications.

  11. Design for Review - Applying Lessons Learned to Improve the FPGA Review Process

    Science.gov (United States)

    Figueiredo, Marco A.; Li, Kenneth E.

    2014-01-01

    Flight Field Programmable Gate Array (FPGA) designs are required to be independently reviewed. This paper provides recommendations to Flight FPGA designers to properly prepare their designs for review in order to facilitate the review process, and reduce the impact of the review time in the overall project schedule.

  12. Readback and partial reconfiguration of Virtex-Ⅱ FPGA%Virtex-Ⅱ系列FPGA的回读与部分重配置

    Institute of Scientific and Technical Information of China (English)

    周秀娟; 叶荣润

    2012-01-01

    In this paper, the system functions of an experimental prototype for Virtex-II FPGA based on SRAM are introduced. Readback and partial reconfiguration of XA2V3000 FPGA are performed. The timing sequence on JTAG interfaces is presented as well. Finally, an analysis of experimental results is made. The results indicate that the function of reading back configuration data from FPGA can detect single-event upsets (SEU), while partial reconfiguration can reduce cumulative effects caused by FPGA upsets and repair the system.%介绍了基于SRAM的Virtex-Ⅱ系列FPGA试验样板的系统功能,实现了对XQ2V3000 FPGA的回读与部分重配置,并给出了JTAG接口下的时序,最后分析了试验的结果.结果表明,FPGA回读可以有效地检测FPGA是否发生了单粒子翻转,而部分重配置可以有效地降低FPGA发生翻转的累积效应,并修复系统功能.

  13. Verification of FPGA-Signal using the test board which is applied to Safety-related controller

    Energy Technology Data Exchange (ETDEWEB)

    Chung, Youn-Hu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [SOOSAN ENS, Seoul (Korea, Republic of)

    2016-10-15

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. Saftety-related PLC must meet the international standard specifications. With this reason, we use V and V according to an international standard in order to secure high reliability and safety. By using this, we are supposed to proceed to a variety of verification courses for extra reliability and safety analysis. In order to have efficient verification of test results, we propose the test using the newly changed BGA socket which can resolve the problems of the conventional socket on this paper. The Verification of processes is divided into verification of Hardware and firmware. That processes are carried out in the unit testing and integration testing. The proposed test method is simple, the effect of cost reductions by batch process. In addition, it is advantageous to measure the signal from the Hi-speed-IC due to its short length of the pins and it was plated with the copper around it. Further, it also to prevent abrasion on the IC ball because it has no direct contact with the PCB. Therefore, it can be actually applied is to the BGA package test and we can easily verify logic as well as easily checking the operation of the designed data.

  14. FPGA design

    CERN Document Server

    Simpson, Philip

    2010-01-01

    This book describes best practices for successful FPGA design. It is the result of the author's meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book's content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design t

  15. Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

    Directory of Open Access Journals (Sweden)

    Kearney David

    2007-01-01

    Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

  16. Using Simulated Partial Dynamic Run-Time Reconfiguration to Share Embedded FPGA Compute and Power Resources across a Swarm of Unpiloted Airborne Vehicles

    Directory of Open Access Journals (Sweden)

    David Kearney

    2007-02-01

    Full Text Available We show how the limited electrical power and FPGA compute resources available in a swarm of small UAVs can be shared by moving FPGA tasks from one UAV to another. A software and hardware infrastructure that supports the mobility of embedded FPGA applications on a single FPGA chip and across a group of networked FPGA chips is an integral part of the work described here. It is shown how to allocate a single FPGA's resources at run time and to share a single device through the use of application checkpointing, a memory controller, and an on-chip run-time reconfigurable network. A prototype distributed operating system is described for managing mobile applications across the swarm based on the contents of a fuzzy rule base. It can move applications between UAVs in order to equalize power use or to enable the continuous replenishment of fully fueled planes into the swarm.

  17. Verification of BGA type FPGA logic applied to a control equipment with Safety Class using the special socket

    Energy Technology Data Exchange (ETDEWEB)

    Chung, YounHu; Yoo, Kwanwoo; Lee, Myeongkyun; Yun, Donghwa [PONUTech Co., Seoul (Korea, Republic of)

    2015-10-15

    This article aims to provide the verification method for BGA-type FPGA of Programmable Logic Controller (PLC) developed as Safety Class. The logic of FPGA in the control device with Safety Class is the circuit to control overall logic of PLC. This device converts to the different module from the input signals for both digital and analogue of the equipment in the field and outputs their data. In addition, it should perform the logical controls such as backplane communication control and data communication. We suggest acquiring method of the data signal with efficient logic using the socket in this article. Proposed test socket is made by simpler process than former one, and the process is done in batches by which cost can be reduces, and the test socket can be quickly produced in response to any request. Also, it is possible to reduce the wear by reducing the contact force of the ball phenomenon. The structure on the basis of silicon can be reduced the modification, and it has excellent linearity. At the logic verification, the operation that state data block is designed in the FPGA could be easily confirmed by using a socket.

  18. Degration of Partially Stabilized Zirconia Ceramics under an Applied Stress

    Institute of Scientific and Technical Information of China (English)

    2003-01-01

    Partially stabilized zirconia ceramics were sintered using fine powder of ZrO2-3mol%Y2O3 prepared by the chemical co-precipitation method.The tetragonal-to-monoclinic phase transformation in ZrO2 ceramics during the aging in boiling water and the effect of an applied stress of 100MPa were mainly investigated.The degradation of ZrO2 ceramics is considered to be caused by the reaction between Y2O3 and H2O,which leads to a decreasing in the stability of tetragonal phase of ZrO2.It is found that the tensile stress improves the driving force of the phase transformation and accelerates the degradation while the compressive stress has no obvious effect on the degradation.

  19. Plane waves and spherical means applied to partial differential equations

    CERN Document Server

    John, Fritz

    2004-01-01

    Elementary and self-contained, this heterogeneous collection of results on partial differential equations employs certain elementary identities for plane and spherical integrals of an arbitrary function, showing how a variety of results on fairly general differential equations follow from those identities. The first chapter deals with the decomposition of arbitrary functions into functions of the type of plane waves. Succeeding chapters introduce the first application of the Radon transformation and examine the solution of the initial value problem for homogeneous hyperbolic equations with con

  20. Partial least square regression applied to the QTLMAS 2010 dataset

    NARCIS (Netherlands)

    Coster, A.; Calus, M.P.L.

    2010-01-01

    Detection of genomic regions affecting traits is a goal in many genetic studies. Studies applying distinct methods for detection of these regions, called quantitative trait loci (QTL), have been described, ranging from single marker regression [1] to methods that enable to fit several markers simult

  1. Pipelined Viterbi Decoder Using FPGA

    Directory of Open Access Journals (Sweden)

    Nayel Al-Zubi

    2013-02-01

    Full Text Available Convolutional encoding is used in almost all digital communication systems to get better gain in BER (Bit Error Rate, and all applications needs high throughput rate. The Viterbi algorithm is the solution in decoding process. The nonlinear and feedback nature of the Viterbi decoder makes its high speed implementation harder. One of promising approaches to get high throughput in the Viterbi decoder is to introduce a pipelining. This work applies a carry-save technique, which gets the advantage that the critical path in the ACS feedback becomes in one direction and get rid of carry ripple in the “Add” part of ACS unit. In this simulation and implementation show how this technique will improve the throughput of the Viterbi decoder. The design complexities for the bit-pipelined architecture are evaluated and demonstrated using Verilog HDL simulation. And a general algorithm in software that simulates a Viterbi Decoder was developed. Our research is concerned with implementation of the Viterbi Decoders for Field Programmable Gate Arrays (FPGA. Generally FPGA's are slower than custom integrated circuits but can be configured in the lab in few hours as compared to fabrication which takes few months. The design implemented using Verilog HDL and synthesized for Xilinx FPGA's.

  2. FPGA based Smart Wireless MIMO Control System

    Science.gov (United States)

    Usman Ali, Syed M.; Hussain, Sajid; Akber Siddiqui, Ali; Arshad, Jawad Ali; Darakhshan, Anjum

    2013-12-01

    In our present work, we have successfully designed, and developed an FPGA based smart wireless MIMO (Multiple Input & Multiple Output) system capable of controlling multiple industrial process parameters such as temperature, pressure, stress and vibration etc. To achieve this task we have used Xilin x Spartan 3E FPGA (Field Programmable Gate Array) instead of conventional microcontrollers. By employing FPGA kit to PC via RF transceivers which has a working range of about 100 meters. The developed smart system is capable of performing the control task assigned to it successfully. We have also provided a provision to our proposed system that can be accessed for monitoring and control through the web and GSM as well. Our proposed system can be equally applied to all the hazardous and rugged industrial environments where a conventional system cannot work effectively.

  3. Graph theory for FPGA minimum configurations

    Institute of Scientific and Technical Information of China (English)

    Ruan Aiwu; Li Wenchang; Xiang Chuanyin; Song Jiangmin; Kang Shi; Liao Yongbo

    2011-01-01

    A traditional bottom-up modeling method for minimum configuration numbers is adopted for the study of FPGA minimum configurations.This method is limited ifa large number of LUTs and multiplexers are presented.Since graph theory has been extensively applied to circuit analysis and test,this paper focuses on the modeling FPGA configurations.In our study,an internal logic block and interconnections of an FPGA are considered as a vertex and an edge connecting two vertices in the graph,respectively.A top-down modeling method is proposed in the paper to achieve minimum configuration numbers for CLB and IOB.Based on the proposed modeling approach and exhaustive analysis,the minimum configuration numbers for CLB and IOB are five and three,respectively.

  4. Prototyping Advanced Control Systems on FPGA

    Directory of Open Access Journals (Sweden)

    Simard Stéphane

    2009-01-01

    Full Text Available In advanced digital control and mechatronics, FPGA-based systems on a chip (SoCs promise to supplant older technologies, such as microcontrollers and DSPs. However, the tackling of FPGA technology by control specialists is complicated by the need for skilled hardware/software partitioning and design in order to match the performance requirements of more and more complex algorithms while minimizing cost. Currently, without adequate software support to provide a straightforward design flow, the amount of time and efforts required is prohibitive. In this paper, we discuss our choice, adaptation, and use of a rapid prototyping platform and design flow suitable for the design of on-chip motion controllers and other SoCs with a need for analog interfacing. The platform consists of a customized FPGA design for the Amirix AP1000 PCI FPGA board coupled with a multichannel analog I/O daughter card. The design flow uses Xilinx System Generator in Matlab/Simulink for system design and test, and Xilinx Platform Studio for SoC integration. This approach has been applied to the analysis, design, and hardware implementation of a vector controller for 3-phase AC induction motors. It also has contributed to the development of CMC's MEMS prototyping platform, now used by several Canadian laboratories.

  5. FPGA programming using FX3

    CERN Document Server

    Calleja, Stefano

    2014-01-01

    An FPGA is required to be programmed via USB3 cable. Connectivity to the host PC is achieved by using an FX3 chip. By changing the firmware of the FX3, one can alter the function of the FX3. To program the FPGA via USB3, the FX3 must act as a connector from the host to the FPGA. This type of connection is known as an FPGA link. This method of connection is required to avoid programming the FPGA and FX3 dedicated memories and thus not having to use different programming methods and cables to program the board. It is considered that the FX3 is suitable to be used as an FPGA link since its previous version, the FX2, was also used as an FPGA link in a similar project. Firmware was downloaded on the FX3 using libusb and fx3load files from a Linux terminal. Some testing firmware was verified to perform as intended. However, the connection firmware intended to make the FPGA link truly functional has not been successful so far. Yet, through the FX3 documentation, it can be noted that an FPGA link is possible. UrJTAG ...

  6. FPGA Vision Data Architecture

    Science.gov (United States)

    Morfopoulos, Arin C.; Pham, Thang D.

    2013-01-01

    JPL has produced a series of FPGA (field programmable gate array) vision algorithms that were written with custom interfaces to get data in and out of each vision module. Each module has unique requirements on the data interface, and further vision modules are continually being developed, each with their own custom interfaces. Each memory module had also been designed for direct access to memory or to another memory module.

  7. From OO to FPGA :

    Energy Technology Data Exchange (ETDEWEB)

    Kou, Stephen; Palsberg, Jens; Brooks, Jeffrey

    2012-09-01

    Consumer electronics today such as cell phones often have one or more low-power FPGAs to assist with energy-intensive operations in order to reduce overall energy consumption and increase battery life. However, current techniques for programming FPGAs require people to be specially trained to do so. Ideally, software engineers can more readily take advantage of the benefits FPGAs offer by being able to program them using their existing skills, a common one being object-oriented programming. However, traditional techniques for compiling object-oriented languages are at odds with todays FPGA tools, which support neither pointers nor complex data structures. Open until now is the problem of compiling an object-oriented language to an FPGA in a way that harnesses this potential for huge energy savings. In this paper, we present a new compilation technique that feeds into an existing FPGA tool chain and produces FPGAs with up to almost an order of magnitude in energy savings compared to a low-power microprocessor while still retaining comparable performance and area usage.

  8. OPTIMAL CONTROL THEORY APPLIED TO SYSTEMS DESCRIBED BY PARTIAL DIFFERENTIAL EQUATIONS. VOL. 1 OF FINAL REPORT.

    Science.gov (United States)

    control theory to systems described by partial differential equations. The intent is not to advance the theory of partial differential equations per se. Thus all considerations will be restricted to the more familiar equations of the type which often occur in mathematical physics. Specifically, the distributed parameter systems under consideration are represented by a set of field

  9. Preconditioners based on windowed Fourier frames applied to elliptic partial differential equations

    NARCIS (Netherlands)

    Bhowmik, S.K.; Stolk, C.C.

    2011-01-01

    We investigate the application of windowed Fourier frames to the numerical solution of partial differential equations, focussing on elliptic equations. The action of a partial differential operator (PDO) on a windowed plane wave is close to a multiplication, where the multiplication factor is given

  10. FPGA Implementation of Wave Pipelining CORDIC Algorithms

    Institute of Scientific and Technical Information of China (English)

    CUI Wei

    2008-01-01

    The implementation of the coordinate rotational digital computer (CORDIC) algorithm with wave pipelining technique on field programmable gate array (FPGA) is described. All data in FPGA-based wave pipelining pass through a number of logic gates, in the same way that all data pass through the same number of registers in a conventional pipeline. Moreover, all paths are routed using identical routing resources. The manual placement, timing driven routing and timing analyzing techniques are applied to optimize the layout for achieving good path balance. Experimental results show that a 256-LUT logic depth circuit mapped on XC4VLX15-12 runs as high as 330MHz, which is a little lower than the speed of 336MHz based on the conventional 16-stage pipelining in the same chip. The latency of the wave pipelining circuit is 30.3ns, which is 36.4% shorter than the latency of 16-stage conventional pipelining circuit.

  11. A Hyperbolic Tangent Adaptive PID + LQR Control Applied to a Step-Down Converter Using Poles Placement Design Implemented in FPGA

    Directory of Open Access Journals (Sweden)

    Marcelo Dias Pedroso

    2013-01-01

    Full Text Available This work presents an adaptive control that integrates two linear control strategies applied to a step-down converter: Proportional Integral Derivative (PID and Linear Quadratic Regulator (LQR controls. Considering the converter open loop transfer function and using the poles placement technique, the designs of the two controllers are set so that the operating point of the closed loop system presents the same natural frequency. With poles placement design, the overshoot problems of the LQR controller are avoided. To achieve the best performance of each controller, a hyperbolic tangent weight function is applied. The limits of the hyperbolic tangent function are defined based on the system error range. Simulation results using the Altera DSP Builder software in a MATLAB/SIMULINK environment of the proposed control schemes are presented.

  12. Radiation Tolerant, FPGA-Based SmallSat Computer System

    Science.gov (United States)

    LaMeres, Brock J.; Crum, Gary A.; Martinez, Andres; Petro, Andrew

    2015-01-01

    The Radiation Tolerant, FPGA-based SmallSat Computer System (RadSat) computing platform exploits a commercial off-the-shelf (COTS) Field Programmable Gate Array (FPGA) with real-time partial reconfiguration to provide increased performance, power efficiency and radiation tolerance at a fraction of the cost of existing radiation hardened computing solutions. This technology is ideal for small spacecraft that require state-of-the-art on-board processing in harsh radiation environments but where using radiation hardened processors is cost prohibitive.

  13. SEU mitigation strategies for SRAM-based FPGA

    Science.gov (United States)

    Luo, Pei; Zhang, Jian

    2011-08-01

    The type of Field Programmable Gate Arrays (FPGAs) technology and device family used in a design is a key factor for system reliability. Though antifuse-based FPGAs are widely used in aerospace because of their high reliability, current antifuse-based FPGA devices are expensive and leave no room for mistakes or changes since they are not reprogrammable. The substitute for antifuse-based FPGAs are needed in aerospace design, they should be both reprogrammable and highly reliable to Single Event Upset effects (SEUs). SRAM-based FPGAs are widely and systematically used in complex embedding digital systems both in a single chip industry and commercial applications. They are reprogrammable and high in density because of the smaller SRAM cells and logic structures. But the SRAM-based FPGAs are especially sensitive to cosmic radiation because the configuration information is stored in SRAM memory. The ideal FPGA for aerospace use should be high-density SRAM-based which is also insensitive to cosmic radiation induced SEUs. Therefore, in order to enable the use of SRAM-based FPGAs in safety critical applications, new techniques and strategies are essential to mitigate the SEU errors in such devices. In order to improve the reliability of SRAM-based FPGAs which are very sensitive to SEU errors, techniques such as reconfiguration and Triple Module Redundancy (TMR) are widely used in the aerospace electronic systems to mitigate the SEU and Single Event Functional Interrupt (SEFI) errors. Compared to reconfiguration and triplication, scrubbing and partial reconfiguration will utilize fewer or even no internal resources of FPGA. What's more, the detection and repair process can detect and correct SEU errors in configuration memories of the FPGA without affecting or interrupting the proper working of the system while reconfiguration would terminate the operation of the FPGA. This paper presents a payload system realized on Xilinx Virtex-4 FPGA which mitigates SEU effects in the

  14. Acoustic emission partial discharge detection technique applied to fault diagnosis: Case studies of generator transformers

    Directory of Open Access Journals (Sweden)

    Shanker Tangella Bhavani

    2016-01-01

    Full Text Available In power transformers, locating the partial discharge (PD source is as important as identifying it. Acoustic Emission (AE sensing offers a good solution for both PD detection and PD source location identification. In this paper the principle of the AE technique, along with in-situ findings of the online acoustic emission signals captured from partial discharges on a number of Generator Transformers (GT, is discussed. Of the two cases discussed, the first deals with Acoustic Emission Partial Discharge (AEPD tests on two identical transformers, and the second deals with the AEPD measurement of a transformer carried out on different occasions (years. These transformers are from a hydropower station and a thermal power station in India. Tests conducted in identical transformers give the provision for comparing AE signal amplitudes from the two transformers. These case studies also help in comprehending the efficacy of integrating Dissolved Gas is (DGA data with AEPD test results in detecting and locating the PD source.

  15. A direct algebraic method applied to obtain complex solutions of some nonlinear partial differential equations

    Energy Technology Data Exchange (ETDEWEB)

    Zhang Huiqun [College of Mathematical Science, Qingdao University, Qingdao, Shandong 266071 (China)], E-mail: hellozhq@yahoo.com.cn

    2009-02-15

    By using some exact solutions of an auxiliary ordinary differential equation, a direct algebraic method is described to construct the exact complex solutions for nonlinear partial differential equations. The method is implemented for the NLS equation, a new Hamiltonian amplitude equation, the coupled Schrodinger-KdV equations and the Hirota-Maccari equations. New exact complex solutions are obtained.

  16. Flexible experimental FPGA based platform

    DEFF Research Database (Denmark)

    Andersen, Karsten Holm; Nymand, Morten

    2016-01-01

    This paper presents an experimental flexible Field Programmable Gate Array (FPGA) based platform for testing and verifying digital controlled dc-dc converters. The platform supports different types of control strategies, dc-dc converter topologies and switching frequencies. The controller platform...... interface supporting configuration and reading of setup parameters, controller status and the acquisition memory in a simple way. The FPGA based platform, provides an easy way within education or research to use different digital control strategies and different converter topologies controlled by an FPGA...

  17. FPGA realization of multi-scroll chaotic oscillators

    Science.gov (United States)

    Tlelo-Cuautle, E.; Rangel-Magdaleno, J. J.; Pano-Azucena, A. D.; Obeso-Rodelo, P. J.; Nunez-Perez, J. C.

    2015-10-01

    Chaotic oscillators have been realized using field-programmable gate arrays (FPGAs) showing good results. However, only 2-scrolls have been observed experimentally, and all reported works use commercially-available software tools for FPGA synthesis. In this manner, as a first contribution we show the FPGA realization of two multi-scroll chaotic oscillators that are characterized by their maximum Lyapunov exponent (MLE) for generating from 2- to 6-scrolls. The first multi-scroll chaotic oscillator is based on saturated function series and the second on Chua's circuit. As a second contribution, we show their hardware realization by applying two numerical methods: Forward Euler (FE) and Runge Kutta (RK). The advantage of realizing those multi-scroll chaotic oscillators is that one can avoid the use of multiplier entities, thus optimizing FPGA resources and increasing the processing speed, as we show by realizing single constant multiplication (SCM) blocks. The experiments are verified by performing co-simulation for an FPGA Spartan 3 of Xilinx. Finally, experimental results are shown for different values of MLE (already optimized) for both multi-scroll chaotic oscillators, and the FPGA used resources are listed for generating 6-scrolls when applying FE and RK.

  18. Exploration of Heterogeneous FPGA Architectures

    Directory of Open Access Journals (Sweden)

    Umer Farooq

    2011-01-01

    mesh and tree-based architectures are evaluated for three sets of benchmark circuits. Experimental results show that a more flexible floor-planning in mesh-based FPGA gives better results as compared to the column-based floor-planning. Also it is shown that compared to different floor-plannings of mesh-based FPGA, tree-based architecture gives better area, performance, and power results.

  19. FPGA Boot Loader and Scrubber

    Science.gov (United States)

    Wade, Randall S.; Jones, Bailey

    2009-01-01

    A computer program loads configuration code into a Xilinx field-programmable gate array (FPGA), reads back and verifies that code, reloads the code if an error is detected, and monitors the performance of the FPGA for errors in the presence of radiation. The program consists mainly of a set of VHDL files (wherein "VHDL" signifies "VHSIC Hardware Description Language" and "VHSIC" signifies "very-high-speed integrated circuit").

  20. Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

    Directory of Open Access Journals (Sweden)

    Feng Wang

    2015-01-01

    Full Text Available Network-on-Chip (NoC is one of critical communication architectures for future many-core systems. As technology is continually scaling down, on-chip network meets the increasing leakage power crisis. As a leakage power mitigation technique, power-gating can be utilized in on-chip network to solve the crisis. However, the network performance is severely affected by the disconnection in the conventional power-gated NoC. In this paper, we propose a novel partial power-gating approach to improve the performance in the power-gated NoC. The approach mainly involves a direction-slicing scheme, an improved routing algorithm, and a deadlock recovery mechanism. In the synthetic traffic simulation, the proposed design shows favorable power-efficiency at low-load range and achieves better performance than the conventional power-gated one. For the application trace simulation, the design in the mesh/torus network consumes 15.2%/18.9% more power on average, whereas it can averagely obtain 45.0%/28.7% performance improvement compared with the conventional power-gated design. On balance, the proposed design with partial power-gating has a better tradeoff between performance and power-efficiency.

  1. A novel pipeline based FPGA implementation of a genetic algorithm

    Science.gov (United States)

    Thirer, Nonel

    2014-05-01

    To solve problems when an analytical solution is not available, more and more bio-inspired computation techniques have been applied in the last years. Thus, an efficient algorithm is the Genetic Algorithm (GA), which imitates the biological evolution process, finding the solution by the mechanism of "natural selection", where the strong has higher chances to survive. A genetic algorithm is an iterative procedure which operates on a population of individuals called "chromosomes" or "possible solutions" (usually represented by a binary code). GA performs several processes with the population individuals to produce a new population, like in the biological evolution. To provide a high speed solution, pipelined based FPGA hardware implementations are used, with a nstages pipeline for a n-phases genetic algorithm. The FPGA pipeline implementations are constraints by the different execution time of each stage and by the FPGA chip resources. To minimize these difficulties, we propose a bio-inspired technique to modify the crossover step by using non identical twins. Thus two of the chosen chromosomes (parents) will build up two new chromosomes (children) not only one as in classical GA. We analyze the contribution of this method to reduce the execution time in the asynchronous and synchronous pipelines and also the possibility to a cheaper FPGA implementation, by using smaller populations. The full hardware architecture for a FPGA implementation to our target ALTERA development card is presented and analyzed.

  2. Impression Procedures for Metal Frame Removable Partial Dentures as Applied by General Dental Practitioners.

    Science.gov (United States)

    Fokkinga, Wietske A; van Uchelen, Judith; Witter, Dick J; Mulder, Jan; Creugers, Nico H J

    2016-01-01

    This pilot study analyzed impression procedures for conventional metal frame removable partial dentures (RPDs). Heads of RPD departments of three dental laboratories were asked to record features of all incoming impressions for RPDs during a 2-month period. Records included: (1) impression procedure, tray type (stock/custom), impression material (elastomer/alginate), use of border-molding material (yes/no); and (2) RPD type requested (distal-extension/tooth-bounded/combination). Of the 132 total RPD impressions, 111 (84%) involved custom trays, of which 73 (55%) were combined with an elastomer. Impression border-molding material was used in 4% of the cases. Associations between impression procedure and RPD type or dentists' year/university of graduation were not found.

  3. Study of cross-shaped ultrasonic array sensor applied to partial discharge location in transformer oil.

    Science.gov (United States)

    Li, Jisheng; Xin, Xiaohu; Luo, Yongfen; Ji, Haiying; Li, Yanming; Deng, Junbo

    2013-11-01

    A conformal combined sensor is designed and it is used in Partial Discharge (PD) location experiments in transformer oil. The sensor includes a cross-shaped ultrasonic phased array of 13 elements and an ultra-high-frequency (UHF) electromagnetic rectangle array of 2 × 2 elements. Virtual expansion with high order cumulants, the ultrasonic array can achieve the effect of array with 61 elements. This greatly improves the aperture and direction sharpness of original array and reduces the cost of follow-up hardware. With the cross-shaped ultrasonic array, the results of PD location experiments are precise and the maximum error of the direction of arrival (DOA) is less than 5°.

  4. Comparison and Partial Ordering of Music by Applying a Generic Semantic Index

    Directory of Open Access Journals (Sweden)

    Frank Seifert

    2006-04-01

    Full Text Available Instances of simple data types like strings or numbers can easily be compared and arranged on the basis of a lexical or numerical ordering system. Generic operations are available for the test of equality, greater-than- or less-than-relations can be generated and sometimes even similarity can be assessed. But how to handle multimedia data types such as music? Can we compare music at all? Despite many achievements in music information retrieval and besides low-level evaluation of spectral features we are not able to compare music in their entirety. Therefore we propose a semantic indexing method for musical documents that is based on a generic music description form and which delivers the foundation for comparison and partial ordering music.

  5. FPGA-Based Implementation of Lithuanian Isolated Word Recognition Algorithm

    Directory of Open Access Journals (Sweden)

    Tomyslav Sledevič

    2013-05-01

    Full Text Available The paper describes the FPGA-based implementation of Lithuanian isolated word recognition algorithm. FPGA is selected for parallel process implementation using VHDL to ensure fast signal processing at low rate clock signal. Cepstrum analysis was applied to features extraction in voice. The dynamic time warping algorithm was used to compare the vectors of cepstrum coefficients. A library of 100 words features was created and stored in the internal FPGA BRAM memory. Experimental testing with speaker dependent records demonstrated the recognition rate of 94%. The recognition rate of 58% was achieved for speaker-independent records. Calculation of cepstrum coefficients lasted for 8.52 ms at 50 MHz clock, while 100 DTWs took 66.56 ms at 25 MHz clock.Article in Lithuanian

  6. Power Efficient Gurumukhi Unicode Reader Design and Implementation on FPGA

    DEFF Research Database (Denmark)

    Kaur, Amanpreet; Pandey, Bishwajeet; Hussain, Dil Muhammed Akbar

    2017-01-01

    and is implemented on Virtex-6 FPGA on Xilinx software. This GUR design is tested at an different frequencies by applying frequency scaling techniques .The reader is also observed on two different IO Standards i.e. on SSTL (Stub-Series Terminated Logic) and LVDCI (Low Voltage Digitally Controlled Impedance) logic...

  7. CAN and FPGA communication engineering implementation of a CAN bus based measurement system on an FPGA development kit

    CERN Document Server

    Zhu, Yu

    2010-01-01

    Hauptbeschreibung The Controller Area Network (CAN), invented by Bosch in 1983, is a serial field bus protocol which was originally used in road vehicles and now is widely applied in other industrial fields. Since its birth automotive electronic engineers have been use Microcontrollers (MCU) to control the CAN bus. Today, as the Field-programmable Gate Array (FPGA) has become very advance, this book introduces a new method which uses an FPGA and a MCU jointly instead of a single MCU is to design a CAN bus measurement system. Furthermore the designed system should be able to work at the fastest

  8. An FPGA-Based People Detection System

    Directory of Open Access Journals (Sweden)

    James J. Clark

    2005-05-01

    Full Text Available This paper presents an FPGA-based system for detecting people from video. The system is designed to use JPEG-compressed frames from a network camera. Unlike previous approaches that use techniques such as background subtraction and motion detection, we use a machine-learning-based approach to train an accurate detector. We address the hardware design challenges involved in implementing such a detector, along with JPEG decompression, on an FPGA. We also present an algorithm that efficiently combines JPEG decompression with the detection process. This algorithm carries out the inverse DCT step of JPEG decompression only partially. Therefore, it is computationally more efficient and simpler to implement, and it takes up less space on the chip than the full inverse DCT algorithm. The system is demonstrated on an automated video surveillance application and the performance of both hardware and software implementations is analyzed. The results show that the system can detect people accurately at a rate of about 2.5 frames per second on a Virtex-II 2V1000 using a MicroBlaze processor running at 75 MHz, communicating with dedicated hardware over FSL links.

  9. Digital Waveform Generator Basedon FPGA

    Directory of Open Access Journals (Sweden)

    Shoucheng Ding

    2012-07-01

    Full Text Available Field Programmable Gate Array (FPGA of the Cyclone II series was as the core processor of frequency meter and the Quartus II was as the development plat form. This article had designed the fully digital signal generator. It use dall-digital frequency synthesizer technology and FPGA programming implemented the three waveforms: sin wave and square wave and triangle wave. The frequency was adjustable through10- bit phase accumulator and the analog multiplier achieved amplitude modulation. Using 51soft nuclear FPGA wrote a C program and realized the in put control word. The 4 × 4 matrix keyboard inputted frequency or amplitude value and the LCD1602displayedthem. The test results show that the system has high precision, distortion and low.

  10. FPGA based pulsed NQR spectrometer

    Science.gov (United States)

    Hemnani, Preeti; Rajarajan, A. K.; Joshi, Gopal; Motiwala, Paresh D.; Ravindranath, S. V. G.

    2014-04-01

    An NQR spectrometer for the frequency range of 1 MHz to 5 MHZ has been designed constructed and tested using an FPGA module. Consisting of four modules viz. Transmitter, Probe, Receiver and computer controlled (FPGA & Software) module containing frequency synthesizer, pulse programmer, mixer, detection and display, the instrument is capable of exciting nuclei with a power of 200W and can detect signal of a few microvolts in strength. 14N signal from NaNO2 has been observed with the expected signal strength.

  11. Scope of partial least-squares regression applied to the enantiomeric composition determination of ketoprofen from strongly overlapped chromatographic profiles.

    Science.gov (United States)

    Padró, Juan M; Osorio-Grisales, Jaiver; Arancibia, Juan A; Olivieri, Alejandro C; Castells, Cecilia B

    2015-07-01

    Valuable quantitative information could be obtained from strongly overlapped chromatographic profiles of two enantiomers by using proper chemometric methods. Complete separation profiles where the peaks are fully resolved are difficult to achieve in chiral separation methods, and this becomes a particularly severe problem in case that the analyst needs to measure the chiral purity, i.e., when one of the enantiomers is present in the sample in very low concentrations. In this report, we explore the scope of a multivariate chemometric technique based on unfolded partial least-squares regression, as a mathematical tool to solve this quite frequent difficulty. This technique was applied to obtain quantitative results from partially overlapped chromatographic profiles of R- and S-ketoprofen, with different values of enantioresolution factors (from 0.81 down to less than 0.2 resolution units), and also at several different S:R enantiomeric ratios. Enantiomeric purity below 1% was determined with excellent precision even from almost completely overlapped signals. All these assays were tested on the most demanding condition, i.e., when the minor peak elutes immediately after the main peak. The results were validated using univariate calibration of completely resolved profiles and the method applied to the determination of enantiomeric purity of commercial pharmaceuticals.

  12. Development of an FPGA-Based Motion Control IC for Caving Machine

    Directory of Open Access Journals (Sweden)

    Chiu-Keng Lai

    2014-03-01

    Full Text Available Since the Field Programmable Gate Arrays (FPGAs with high density are available nowadays, systems with complex functions can thus be realized by FPGA in a single chip while they are traditionally implemented by several individual chips. In this research, the control of stepping motor drives as well as motion controller is integrated and implemented on Altera Cyclone III FPGA; the resulting system is evaluated by applying it to a 3-axis caving machine which is driven by stepping motors. Finally, the experimental results of current regulation and motion control integrated in FPGA IC are shown to prove the validness.

  13. Implementation of large kernel 2-D convolution in limited FPGA resource

    Science.gov (United States)

    Zhong, Sheng; Li, Yang; Yan, Luxin; Zhang, Tianxu; Cao, Zhiguo

    2007-12-01

    2-D Convolution is a simple mathematical operation which is fundamental to many common image processing operators. Using FPGA to implement the convolver can greatly reduce the DSP's heavy burden in signal processing. But with the limit resource the FPGA can implement a convolver with small 2-D kernel. In this paper, An FIFO type line delayer is presented to serve as the data buffer for convolution to reduce the data fetching operation. A finite state machine is applied to control the reuse of multipliers and adders arrays. With these two techniques, a resource limited FPGA can be used to implement a larger kernel convolver which is commonly used in image process systems.

  14. Intelligent FPGA Data Acquisition Framework

    Science.gov (United States)

    Bai, Yunpeng; Gaisbauer, Dominic; Huber, Stefan; Konorov, Igor; Levit, Dmytro; Steffen, Dominik; Paul, Stephan

    2017-06-01

    In this paper, we present the field programmable gate arrays (FPGA)-based framework intelligent FPGA data acquisition (IFDAQ), which is used for the development of DAQ systems for detectors in high-energy physics. The framework supports Xilinx FPGA and provides a collection of IP cores written in very high speed integrated circuit hardware description language, which use the common interconnect interface. The IP core library offers functionality required for the development of the full DAQ chain. The library consists of Serializer/Deserializer (SERDES)-based time-to-digital conversion channels, an interface to a multichannel 80-MS/s 10-b analog-digital conversion, data transmission, and synchronization protocol between FPGAs, event builder, and slow control. The functionality is distributed among FPGA modules built in the AMC form factor: front end and data concentrator. This modular design also helps to scale and adapt the DAQ system to the needs of the particular experiment. The first application of the IFDAQ framework is the upgrade of the read-out electronics for the drift chambers and the electromagnetic calorimeters (ECALs) of the COMPASS experiment at CERN. The framework will be presented and discussed in the context of this paper.

  15. CHECHIA cavity driving with FPGA controller

    Energy Technology Data Exchange (ETDEWEB)

    Czarski, T.; Koprek, W.; Pozniak, K.T.; Romaniuk, R.S. [Technical Univ. Warsaw (Poland). ELHEP Laboratory, ISE; Simrock, S. [Deutsches Elektronen-Synchrotron (DESY), Hamburg (Germany). TESLA

    2005-07-01

    The initial control of the superconductive cavity has recently been performed by applying the FPGA (Field Programmable Gate Array) technology system in DESY Hamburg. This first experiment turned attention to the general recognition of the cavity features and projected control methods. The electrical model of the cavity is taken as a consideration origin. The calibration of the signal channel is considered as a key preparation for an efficient cavity driving. The cavity parameters identification is confirmed as a proper approach for the required performance: driving on resonance during filling and field stabilization during flattop time with reasonable power consumption. The feed-forward and feedback modes were applied successfully for the CHECHIA cavity driving. Representative results of experiments are presented for different levels of the cavity field gradient. (orig.)

  16. Applied partial differential equations

    CERN Document Server

    DuChateau, Paul

    2012-01-01

    Book focuses mainly on boundary-value and initial-boundary-value problems on spatially bounded and on unbounded domains; integral transforms; uniqueness and continuous dependence on data, first-order equations, and more. Numerous exercises included.

  17. Single event effects actel AX FPGA

    CERN Document Server

    Machefert, F P

    2002-01-01

    ACTEL and NASA performed irradiation tests at Brookhaven National Laboratory on the AX1000 component of the new ACTEL FPGA family "Axcelerator". The characteristics of these FPGAs are attractive and make them good candidates for the Front-End of the LHCb Calorimeters. The results of the measurements done at BNL are used to determine the resistance of the AX in the environment of the Calorimeter electronics. If mitigation techniques are used (triple voting or horizontal and vertical parity), no major worry is expected in spite of the safety factors applied in the evaluation. In this case and at maximum, a few bit errors could be observed per year on the full Calorimeter system.

  18. Modeling of the Partial Discharge Process in a Liquid Dielectric: Effect of Applied Voltage, Gap Distance, and Electrode Type

    Directory of Open Access Journals (Sweden)

    Tao Yuan

    2013-02-01

    Full Text Available The partial discharge (PD process in liquid dielectrics is influenced by several factors. Although the PD current contains the information representing the discharge process during the PD event, it is difficult to determine the detailed dynamics of what is happening in the bulk of the liquid. In this paper, a microscopic model describing the dynamics of the charge carriers is implemented. The model consists of drift-diffusion equations of electrons, positive and negative ions coupled with Poisson’s equation. The stochastic feature of PD events is included in the equation. First the model is validated through comparison between the calculated PD current and experimental data. Then experiments are conducted to study the effects of the amplitude of the applied voltage, gap distance and electrode type on the PD process. The PD currents under each condition are recorded. Simulations based on the model have been conducted to analyze the dynamics of the PD events under each condition, and thus explain the mechanism of how these factors influence the PD events. The space charge generated in the PD process is revealed as the main reason affecting the microscopic process of the PD events.

  19. Sistema basado en FPGA para la evaluación de redes neuronales orientadas al reconocimiento de imágenes

    Directory of Open Access Journals (Sweden)

    José David Alvarado

    2013-05-01

    Full Text Available This paper presents the use of Field Programmable Gate Arrays (FPGA to evaluate an Artificial Neural Network (ANN system, and also to apply image pattern recognition to alphabetic characters in contexts where different neural network models are utilized. This is performed in order to evaluate the performance of the neural networks implemented in the FPGA and also to analyze the Spartan-3 FPGA XCS200 performance. This study has four phases: neural network model selection; development of a training platform using Labview RNA; design, implementation and verification of RNA models; and parameter setup to evaluate RNA Spartan-3 FPGA XCS200 performance.

  20. DP-FPGA: An FPGA Architecture Optimized for Datapaths

    Directory of Open Access Journals (Sweden)

    Don Cherepacha

    1996-01-01

    Full Text Available This paper presents a new Field-Programmable Gate Array (FPGA architecture which reduces the density gap between FPGAs and Mask-Programmed Gate Arrays (MPGAs for datapath oriented circuits. This is primarily achieved by operating on data as a number of identically programmed four-bit slices. The interconnection network incorporates distinct sets of resources for routing control and data signals. These features reduce circuit area by sharing programming bits among four-bit slices, reducing the total number of storage cells required.

  1. Towards a FPGA-controlled deep phase modulation interferometer

    CERN Document Server

    Terán, M; Gesa, L l; Mateos, I; Gibert, F; Karnesis, N; Ramos-Castro, J; Schwarze, T S; Gerberding, O; Heinzel, G; Guzmán, F; Nofrarias, M

    2014-01-01

    Deep phase modulation interferometry was proposed as a method to enhance homodyne interferometers to work over many fringes. In this scheme, a sinusoidal phase modulation is applied in one arm while the demodulation takes place as a post-processing step. In this contribution we report on the development to implement this scheme in a fiber coupled interferometer controlled by means of a FPGA, which includes a LEON3 soft-core processor. The latter acts as a CPU and executes a custom made application to communicate with a host PC. In contrast to usual FPGA-based designs, this implementation allows a real-time fine tuning of the parameters involved in the setup, from the control to the post-processing parameters.

  2. HIGH SPEED POINT ARITHMETIC ARCHITECTURE FOR ECC ON FPGA

    Directory of Open Access Journals (Sweden)

    Rahila Bilal,

    2010-09-01

    Full Text Available Elliptic curve cryptography plays a crucial role in networking and communication security. ECC have evolved in the recent past as an important alternative to established systems like RSA. This paper describes the implementation of an elliptic curve coprocessor based on the FPGA , which can provide a significant speedup for these cryptosystems. The FPGA configuration file is synthesized from VHDL code applying different hardware synthesis products. The implementation of ECC lies in three levels: scalar multiplication, point addition/doubling and finite field modular arithmetic. In this paper, we present a novel fast architecture for the point addition/doubling level in the projective coordinate. The proposed Architecture is based on Binary Field. The Design performs multiplication using Polynomial Basis. Analysis shows that, with reasonable hardware overhead, our architecture can achieve a high speedup for the point addition operation and point Doubling operation.Furthermore, the architecture is parameterized for different data widths to evaluate the optimal resource utilization.

  3. Cryptographic Applications using FPGA Technology

    Directory of Open Access Journals (Sweden)

    Alexandru Coman

    2011-03-01

    Full Text Available Cryptographic systems have become a part of our daily life through the need of security of many common activities such as communication, payments, data transfers etc. The best support in design and implementation of cryptographic applications is offered by embedded systems such as ASICs and FPGAs. In the past few years, the increase in performance of FPGAs has made them key components in implementing cryptographic systems. One of the most important parts of the cryptographic systems is the random number generator used. Combinations of PRNG and TRNG are commonly used. A good and efficient TRNG implementation is very important and can be achieved through FPGA technology.

  4. FPGA Authentication Methods.

    Energy Technology Data Exchange (ETDEWEB)

    Brotz, Jay Kristoffer [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Hymel, Ross W [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Punnoose, Ratish J. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Mannos, Tom [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Grant, Neil [Atomic Weapons Establishment (AWE), Berkshire (United Kingdom); Evans, Neil [Atomic Weapons Establishment (AWE), Berkshire (United Kingdom)

    2017-05-01

    One of the greatest challenges facing designers of equipment to be used in a nuclear arms control treaty is how to convince the other party in the treaty to trust its results and functionality. Whether the host provides equipment meant to prove treaty obligations and the inspector needs to gain that trust (commonly referred to as authentication), or the inspector provides this equipment and the host needs to gain this trust (commonly considered to be included in certification), one party generally has higher confidence in the equipment at the start of a treaty regime and the other party needs to gain that confidence prior to use. While we focus on authentication in this document—that is, the inspector gaining confidence in host-provided equipment—our conclusions will likely apply to host certification of inspector-provided equipment.

  5. Autonomous Lawnmower using FPGA implementation.

    Science.gov (United States)

    Ahmad, Nabihah; Lokman, Nabill bin; Helmy Abd Wahab, Mohd

    2016-11-01

    Nowadays, there are various types of robot have been invented for multiple purposes. The robots have the special characteristic that surpass the human ability and could operate in extreme environment which human cannot endure. In this paper, an autonomous robot is built to imitate the characteristic of a human cutting grass. A Field Programmable Gate Array (FPGA) is used to control the movements where all data and information would be processed. Very High Speed Integrated Circuit (VHSIC) Hardware Description Language (VHDL) is used to describe the hardware using Quartus II software. This robot has the ability of avoiding obstacle using ultrasonic sensor. This robot used two DC motors for its movement. It could include moving forward, backward, and turning left and right. The movement or the path of the automatic lawn mower is based on a path planning technique. Four Global Positioning System (GPS) plot are set to create a boundary. This to ensure that the lawn mower operates within the area given by user. Every action of the lawn mower is controlled by the FPGA DE' Board Cyclone II with the help of the sensor. Furthermore, Sketch Up software was used to design the structure of the lawn mower. The autonomous lawn mower was able to operate efficiently and smoothly return to coordinated paths after passing the obstacle. It uses 25% of total pins available on the board and 31% of total Digital Signal Processing (DSP) blocks.

  6. STRS Compliant FPGA Waveform Development

    Science.gov (United States)

    Nappier, Jennifer; Downey, Joseph

    2008-01-01

    The Space Telecommunications Radio System (STRS) Architecture Standard describes a standard for NASA space software defined radios (SDRs). It provides a common framework that can be used to develop and operate a space SDR in a reconfigurable and reprogrammable manner. One goal of the STRS Architecture is to promote waveform reuse among multiple software defined radios. Many space domain waveforms are designed to run in the special signal processing (SSP) hardware. However, the STRS Architecture is currently incomplete in defining a standard for designing waveforms in the SSP hardware. Therefore, the STRS Architecture needs to be extended to encompass waveform development in the SSP hardware. A transmit waveform for space applications was developed to determine ways to extend the STRS Architecture to a field programmable gate array (FPGA). These extensions include a standard hardware abstraction layer for FPGAs and a standard interface between waveform functions running inside a FPGA. Current standards were researched and new standard interfaces were proposed. The implementation of the proposed standard interfaces on a laboratory breadboard SDR will be presented.

  7. FPGA design and implementation of Gaussian filter

    Science.gov (United States)

    Yang, Zhihui; Zhou, Gang

    2015-12-01

    In this paper , we choose four different variances of 1,3,6 and 12 to conduct FPGA design with three kinds of Gaussian filtering algorithm ,they are implementing Gaussian filter with a Gaussian filter template, Gaussian filter approximation with mean filtering and Gaussian filter approximation with IIR filtering. By waveform simulation and synthesis, we get the processing results on the experimental image and the consumption of FPGA resources of the three methods. We set the result of Gaussian filter used in matlab as standard to get the result error. By comparing the FPGA resources and the error of FPGA implementation methods, we get the best FPGA design to achieve a Gaussian filter. Conclusions can be drawn based on the results we have already got. When the variance is small, the FPGA resources is enough for the algorithm to implement Gaussian filter with a Gaussian filter template which is the best choice. But when the variance is so large that there is no more FPGA resources, we can chose the mean to approximate Gaussian filter with IIR filtering.

  8. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    Institute of Scientific and Technical Information of China (English)

    Zhao Yan; Gao Jiantou; Wang Jian; Li Ming; Liu Guizhai; Zhang Feng; Guo Xufeng; Zhao Kai; Stanley L.Chen; Yu Fang; Liu Zhongli; Wu Lihua; Han Xiaowei; Li Yan; Zhang Qianli; Chen Liang; Zhang Guoquan; Li Jianzhong; Yang Bo

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based fieldprogrammable gate array (FPGA) VS1000,which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute.Corresponding with the characteristics of the FPGA,each IOB includes a local routing pool and two IO cells composed of a signal path circuit,configurable input/output buffers and an ESD protection network.A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes.Programmable IO buffers can be used at TTL/CMOS standard levels.The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic.Radiation-hardened designs,including A-type and H-type body-tied transistors and special D-type registers,improve the anti-radiation performance.The ESD protection network,which provides a high-impulse discharge path on a pad,prevents the breakdown of the core logic caused by the immense current.These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs.The functionality and performance of the IOB array is proved after a functional test.The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si),a dose survivability rate of 1.5 × 1011 rad(Si)/s,and a neutron fluence immunity of 1 × 1014 n/cm2.

  9. An IO block array in a radiation-hardened SOI SRAM-based FPGA

    Science.gov (United States)

    Yan, Zhao; Lihua, Wu; Xiaowei, Han; Yan, Li; Qianli, Zhang; Liang, Chen; Guoquan, Zhang; Jianzhong, Li; Bo, Yang; Jiantou, Gao; Jian, Wang; Ming, Li; Guizhai, Liu; Feng, Zhang; Xufeng, Guo; Kai, Zhao; Chen, Stanley L.; Fang, Yu; Zhongli, Liu

    2012-01-01

    We present an input/output block (IOB) array used in the radiation-hardened SRAM-based field-programmable gate array (FPGA) VS1000, which is designed and fabricated with a 0.5 μm partially depleted silicon-on-insulator (SOI) logic process at the CETC 58th Institute. Corresponding with the characteristics of the FPGA, each IOB includes a local routing pool and two IO cells composed of a signal path circuit, configurable input/output buffers and an ESD protection network. A boundary-scan path circuit can be used between the programmable buffers and the input/output circuit or as a transparent circuit when the IOB is applied in different modes. Programmable IO buffers can be used at TTL/CMOS standard levels. The local routing pool enhances the flexibility and routability of the connection between the IOB array and the core logic. Radiation-hardened designs, including A-type and H-type body-tied transistors and special D-type registers, improve the anti-radiation performance. The ESD protection network, which provides a high-impulse discharge path on a pad, prevents the breakdown of the core logic caused by the immense current. These design strategies facilitate the design of FPGAs with different capacities or architectures to form a series of FPGAs. The functionality and performance of the IOB array is proved after a functional test. The radiation test indicates that the proposed VS1000 chip with an IOB array has a total dose tolerance of 100 krad(Si), a dose survivability rate of 1.5 × 1011 rad(Si)/s, and a neutron fluence immunity of 1 × 1014 n/cm2.

  10. FPGA implementation of image enhancement techniques

    Science.gov (United States)

    Kumar, Karan; Jain, Aditya; Srivastava, Atul Kumar

    2009-06-01

    The objective of this paper is designing, modeling, simulation and synthesis of four Image Enhancement techniques on FPGA. Image Enhancement Algorithms can be classified as point processing Techniques, in which operation is done on pixel level and Spatial Filtering Technique, in which operation is performed within neighborhood of a pixel. Algorithms of all the techniques are studied and hardware circuits are realized for them. Then hardware logic is modeled in Matlab Simulink using Xilinx System Generator Block set and synthesized onto Virtex4 xc4vsx35-10ff668 FPGA chip. Using hardware co-simulation feature of FPGA kit, the algorithms developed are validated.

  11. Improved adsorption-desorption extraction applied to the partial characterization of the antilisterial bacteriocin produced by Carnobacterium maltaromaticum C2

    OpenAIRE

    Tulini,F. L; E.C.P De Martinis

    2010-01-01

    Bacteriocins are ribosomally produced peptides useful for food biopreservation. An improved adsorption-desorption process is proposed for the partial purification of the bacteriocin produced by the fish isolate Carnobacterium maltaromaticum C2. Analyzis of extract by SDS-PAGE indicated this method may offer an alternative to improve the yield of purification of bacteriocins.

  12. Improved adsorption-desorption extraction applied to the partial characterization of the antilisterial bacteriocin produced by Carnobacterium maltaromaticum C2.

    Science.gov (United States)

    Tulini, F L; De Martinis, E C P

    2010-04-01

    Bacteriocins are ribosomally produced peptides useful for food biopreservation. An improved adsorption-desorption process is proposed for the partial purification of the bacteriocin produced by the fish isolate Carnobacterium maltaromaticum C2. Analyzis of extract by SDS-PAGE indicated this method may offer an alternative to improve the yield of purification of bacteriocins.

  13. Improved adsorption-desorption extraction applied to the partial characterization of the antilisterial bacteriocin produced by Carnobacterium maltaromaticum C2

    Directory of Open Access Journals (Sweden)

    F. L Tulini

    2010-06-01

    Full Text Available Bacteriocins are ribosomally produced peptides useful for food biopreservation. An improved adsorption-desorption process is proposed for the partial purification of the bacteriocin produced by the fish isolate Carnobacterium maltaromaticum C2. Analyzis of extract by SDS-PAGE indicated this method may offer an alternative to improve the yield of purification of bacteriocins.

  14. Optimization of FPGA-based Moore FSM

    Science.gov (United States)

    Barkalov, Aleksander; Titarenko, Larysa; Chmielewski, Sławomir

    2014-10-01

    A metod is proposed for hardware reduction in FPGA-based Moore FSM. It is based on using two sources of codes. It reduces the number of LUTs in the FSM circuit. The results of investigations are shown.

  15. FPGA control utility in JAVA

    Science.gov (United States)

    Drabik, Paweł; Pozniak, Krzysztof T.

    2008-01-01

    Processing of large amount of data for high energy physics experiments is modeled here in a form of a multichannel, distributed measurement system based on photonic and electrical modules. A method to control such a system is presented in this paper. This method is based on a new method of address space management called the Component Internal Interface (CII). An updatable and configurable environment provided by FPGA fulfills technological and functional demands imposed on complex measurement systems of the considered kind. A purpose, design process and realization of the object oriented software application, written in the high level code described. A few examples of usage of the suggested application is presented. The application is intended for usage in HEP experiments and FLASH, XFEL lasers.

  16. Development, verification and validation of an FPGA-based core heat removal protection system for a PWR

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Yichun, E-mail: ycwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China); Shui, Xuanxuan, E-mail: 807001564@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Cai, Yuanfeng, E-mail: 1056303902@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Zhou, Junyi, E-mail: 1032133755@qq.com [College of Energy, Xiamen University, Xiamen 361102 (China); Wu, Zhiqiang, E-mail: npic_wu@126.com [State Key Laboratory of Reactor System Design Technology, Nuclear Power Institute of China, Chengdu 610041 (China); Zheng, Jianxiang, E-mail: zwu@xmu.edu.cn [College of Energy, Xiamen University, Xiamen 361102 (China)

    2016-05-15

    Highlights: • An example on life cycle development process and V&V on FPGA-based I&C is presented. • Software standards and guidelines are used in FPGA-based NPP I&C system logic V&V. • Diversified FPGA design and verification languages and tools are utilized. • An NPP operation principle simulator is used to simulate operation scenarios. - Abstract: To reach high confidence and ensure reliability of nuclear FPGA-based safety system, life cycle processes of discipline specification and implementation of design as well as regulations verification and validation (V&V) are needed. A specific example on how to conduct life cycle development process and V&V on FPGA-based core heat removal (CHR) protection system for CPR1000 pressure water reactor (PWR) is presented in this paper. Using the existing standards and guidelines for life cycle development and V&V, a simplified FPGA-based CHR protection system for PWR has been designed, implemented, verified and validated. Diversified verification and simulation languages and tools are used by the independent design team and the V&V team. In the system acceptance testing V&V phase, a CPR1000 NPP operation principle simulator (OPS) model is utilized to simulate normal and abnormal operation scenarios, and provide input data to the under-test FPGA-based CHR protection system and a verified C code CHR function module. The evaluation results are applied to validate the under-test FPGA-based CHR protection system. The OPS model operation outputs also provide reasonable references for the tests. Using an OPS model in the system acceptance testing V&V is cost-effective and high-efficient. A dedicated OPS, as a commercial-off-the-shelf (COTS) item, would contribute as an important tool in the V&V process of NPP I&C systems, including FPGA-based and microprocessor-based systems.

  17. An FPGA-Based Electronic Cochlea

    OpenAIRE

    M. P. Leong; Jin, Craig T.; Leong, Philip H. W.

    2003-01-01

    A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coeffi...

  18. Protection and Control with FPGA technology

    Energy Technology Data Exchange (ETDEWEB)

    Sohn, K. Y.; Yi, W. J. [Korea Reliability Technology and System, Daejeon (Korea, Republic of); Koo, I. S. [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2012-03-15

    To cope with the experiences such as unsatisfied response time of control and protection system, components obsolescence of those systems, and outstanding coercion of system modernization, nuclear society is striving to resolve this issue fundamentally. The reports and standards issued from IAEA and other standard organization like IBC is interested in the FPGA technology, which is fairly mature technology in other fields of industry. Intuitively it is replacing the high level of micro-processor type equipped with various software and hardware, which causes to accelerate the aging and obsolescence, and demands for system modernization in I and C system in Nuclear Power Plant. Thus utility has to spend much time and effort to upgrade I and C system throughout a decease. This paper summarizes the need of FPGA technology in Nuclear Power Plant, describing the characteristics of FPGA, test methodology and design requirements. Also the specific design and implementation experiences brought up in the course of FPGA-based controller, which has been conducted in KoRTS. The certification and verification and validation process to ensure the integrity of FPGA-based controller will be addressed. After that, Diverse Protection System (DPS) for YGN Unit 3 and 4 that is implemented via VHDL through SDLC is loaded on FPGA-based controller for run-time experimentations such as functionality, performance, integrity and reliability. Some of the test data is addressed in this paper.

  19. Greening the NetFPGA Reference Router

    Directory of Open Access Journals (Sweden)

    Feng Guo

    2016-06-01

    Full Text Available Energy efficiency is an important criterion in the design of next generation networks for both economic and environmental concerns. This paper presents an energy-efficient router that is able to dynamically adapt its routing capability in response to real-time traffic load, achieving energy proportional routing. The NetFPGA reference router, which operates at one of two frequencies (125 MHz or 62.5 MHz, requires a board reset to switch frequencies. We have modified the reference router to allow dynamic switching among five operating frequencies. Experiments with real traces indicate that, compared to the reference router, a 10% power reduction can be achieved through dynamic frequency scaling. When the router is further modified to support green traffic engineering and Ethernet port shut-down, power consumption can be reduced by 46% while maintaining the required quality of service. This allows the router to meet the instantaneous performance requirements while minimizing power dissipation. Similar results can be expected when these general power-saving principles are applied in future commercial routers.

  20. Real-time implementation of camera positioning algorithm based on FPGA & SOPC

    Science.gov (United States)

    Yang, Mingcao; Qiu, Yuehong

    2014-09-01

    In recent years, with the development of positioning algorithm and FPGA, to achieve the camera positioning based on real-time implementation, rapidity, accuracy of FPGA has become a possibility by way of in-depth study of embedded hardware and dual camera positioning system, this thesis set up an infrared optical positioning system based on FPGA and SOPC system, which enables real-time positioning to mark points in space. Thesis completion include: (1) uses a CMOS sensor to extract the pixel of three objects with total feet, implemented through FPGA hardware driver, visible-light LED, used here as the target point of the instrument. (2) prior to extraction of the feature point coordinates, the image needs to be filtered to avoid affecting the physical properties of the system to bring the platform, where the median filtering. (3) Coordinate signs point to FPGA hardware circuit extraction, a new iterative threshold selection method for segmentation of images. Binary image is then segmented image tags, which calculates the coordinates of the feature points of the needle through the center of gravity method. (4) direct linear transformation (DLT) and extreme constraints method is applied to three-dimensional reconstruction of the plane array CMOS system space coordinates. using SOPC system on a chip here, taking advantage of dual-core computing systems, which let match and coordinate operations separately, thus increase processing speed.

  1. [The net analyte preprocessing combined with radial basis partial least squares regression applied in noninvasive measurement of blood glucose].

    Science.gov (United States)

    Li, Qing-Bo; Huang, Zheng-Wei

    2014-02-01

    In order to improve the prediction accuracy of quantitative analysis model in the near-infrared spectroscopy of blood glucose, this paper, by combining net analyte preprocessing (NAP) algorithm and radial basis functions partial least squares (RBFPLS) regression, builds a nonlinear model building method which is suitable for glucose measurement of human, named as NAP-RBFPLS. First, NAP is used to pre-process the near-infrared spectroscopy of blood glucose, in order to effectively extract the information which only relates to glucose signal from the original near-infrared spectra, so that it could effectively weaken the occasional correlation problems of the glucose changes and the interference factors which are caused by the absorption of water, albumin, hemoglobin, fat and other components of the blood in human body, the change of temperature of human body, the drift of measuring instruments, the changes of measuring environment, and the changes of measuring conditions; and then a nonlinear quantitative analysis model is built with the near-infrared spectroscopy data after NAP, in order to solve the nonlinear relationship between glucose concentrations and near-infrared spectroscopy which is caused by body strong scattering. In this paper, the new method is compared with other three quantitative analysis models building on partial least squares (PLS), net analyte preprocessing partial least squares (NAP-PLS) and RBFPLS respectively. At last, the experimental results show that the nonlinear calibration model, developed by combining NAP algorithm and RBFPLS regression, which was put forward in this paper, greatly improves the prediction accuracy of prediction sets, and what has been proved in this paper is that the nonlinear model building method will produce practical applications for the research of non-invasive detection techniques on human glucose concentrations.

  2. Statechart-based design controllers for FPGA partial reconfiguration

    Science.gov (United States)

    Łabiak, Grzegorz; Wegrzyn, Marek; Rosado Muñoz, Alfredo

    2015-09-01

    Statechart diagram and UML technique can be a vital part of early conceptual modeling. At the present time there is no much support in hardware design methodologies for reconfiguration features of reprogrammable devices. Authors try to bridge the gap between imprecise UML model and formal HDL description. The key concept in author's proposal is to describe the behavior of the digital controller by statechart diagrams and to map some parts of the behavior into reprogrammable logic by means of group of states which forms sequential automaton. The whole process is illustrated by the example with experimental results.

  3. Compact FPGA-based beamformer using oversampled 1-bit A/D converters

    DEFF Research Database (Denmark)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-01-01

    reconstruction is done using finite impulse response (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50......% of the available logic resources in a commercially available midrange FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz....

  4. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    Science.gov (United States)

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

  5. Diversity for security: case assessment for FPGA-based safety-critical systems

    Directory of Open Access Journals (Sweden)

    Kharchenko Vyacheslav

    2016-01-01

    Full Text Available Industrial safety critical instrumentation and control systems (I&Cs are facing more with information (in general and cyber, in particular security threats and attacks. The application of programmable logic, first of all, field programmable gate arrays (FPGA in critical systems causes specific safety deficits. Security assessment techniques for such systems are based on heuristic knowledges and the expert judgment. Main challenge is how to take into account features of FPGA technology for safety critical I&Cs including systems in which are applied diversity approach to minimize risks of common cause failure. Such systems are called multi-version (MV systems. The goal of the paper is in description of the technique and tool for case-based security assessment of MV FPGA-based I&Cs.

  6. Partial Reconfiguration on FPGAs Architectures, Tools and Applications

    CERN Document Server

    Koch, Dirk

    2013-01-01

    This is the first book to focus on designing run-time reconfigurable systems on FPGAs, in order to gain resource and power efficiency, as well as to improve speed.  Case studies in partial reconfiguration guide readers through the FPGA jungle, straight toward a working system.  The discussion of partial reconfiguration is comprehensive and practical, with models introduced together with methods to implement efficiently the corresponding systems.  Coverage includes concepts for partial module integration and corresponding communication architectures, floorplanning of the on-FPGA resources, physical implementation aspects starting from constraining primitive placement and routing all the way down to the bitstream required to configure the FPGA, and verification of reconfigurable systems.   Provides comprehensive overview of state-of-the-art partial run-time reconfiguration techniques, including architectures, methods, and tools; Focuses on real applications that will benefit from partial reconfiguration; �...

  7. An efficient HW and SW design of H.264 video compression, storage and playback on FPGA devices for handheld thermal imaging systems

    Science.gov (United States)

    Gunay, Omer; Ozsarac, Ismail; Kamisli, Fatih

    2017-05-01

    Video recording is an essential property of new generation military imaging systems. Playback of the stored video on the same device is also desirable as it provides several operational benefits to end users. Two very important constraints for many military imaging systems, especially for hand-held devices and thermal weapon sights, are power consumption and size. To meet these constraints, it is essential to perform most of the processing applied to the video signal, such as preprocessing, compression, storing, decoding, playback and other system functions on a single programmable chip, such as FPGA, DSP, GPU or ASIC. In this work, H.264/AVC (Advanced Video Coding) compatible video compression, storage, decoding and playback blocks are efficiently designed and implemented on FPGA platforms using FPGA fabric and Altera NIOS II soft processor. Many subblocks that are used in video encoding are also used during video decoding in order to save FPGA resources and power. Computationally complex blocks are designed using FPGA fabric, while blocks such as SD card write/read, H.264 syntax decoding and CAVLC decoding are done using NIOS processor to benefit from software flexibility. In addition, to keep power consumption low, the system was designed to require limited external memory access. The design was tested using 640x480 25 fps thermal camera on CYCLONE V FPGA, which is the ALTERA's lowest power FPGA family, and consumes lower than 40% of CYCLONE V 5CEFA7 FPGA resources on average.

  8. fpga controller design and simulation of a portable dough mixing

    African Journals Online (AJOL)

    In this paper, the design and simulation of a Dough Mixer Controller (DMC) with Proportional ... Keywords: FPGA, VHDL, PID controller, Pulse Width Modulation, Full H-Bridge DC motor driver. 1. ...... parative Analysis among DSP and FPGA-.

  9. Synthetic Aperture Radar Data Processing on an FPGA Multi-Core System

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Kusk, Anders; Dall, Jørgen

    2013-01-01

    on an FPGA. The fabric consisting of 64 processor cores and 2D mesh interconnect utilizes 60% of the hardware resources of a Xilinx Virtex-7 device with 550 thousand logic cells and consumes about 10 watt. We apply software pipelining to hide memory latency and reduce the hardware footprint by 14%. We show...

  10. Applying partial correlation method to analyzing the correlation between ionospheric NmF2 and height of isobaric level in the lower atmosphere

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    On the basis of a multiple linear regression model performed for ionospheric NmF2, partial correlation method is first applied to investigating the relation between NmF2 and h (the height of isobaric level) in the lower atmosphere over Wuhan, China during 1957―2004. The results show that partial correlation method can eliminate the influences of solar and geomagnetic activities as well as the seasonal variation factors and reveal the true correlation between NmF2 and h in the lower atmosphere. A weak positive correlation between NmF2 and h is found in the middle stratosphere. In addition, by comparing the partial correlation coefficients between NmF2 and its influence factors, we find that NmF2 is mainly affected by solar activity and the seasonal variation factors, and weakly affected by geomagnetic activity, but hardly affected by h in the lower atmosphere. The study suggests that partial correlation method is a helpful tool for investigating the correlation between ionospheric parameter and its influence factors.

  11. Traffic Light Controller Using Fpga

    Directory of Open Access Journals (Sweden)

    D.Bhavana

    2015-04-01

    Full Text Available The traffic light sequence works on the specific switching of Red, Green and Yellow lights in a particular way with stipulated time form. The normal function of traffic lights requires sophisticated control and coordination to ensure that traffic moves as smoothly and safely as possible and that pedestrians are protected when they cross the roads [1] .This Traffic Light sequence is generated using a specific switching mechanism which will help to control a traffic light system on a road in a specified sequence. This paper focuses on the fact that the traffic lights can be varied in the day and night mode depending on the intensity of the traffic. It plays a vital role in supervising and running the metropolitan traffic and evade the possibilities of any unfortunate mishaps happening in and around the cities. It is a sequential machine to be scrutinized as per the requirements and programmed through a multistep development process. The methods that are used in this project are proposing the circuit, write a code, simulate, synthesis and implement on the hardware [8] . In this project, XILINX Software was chosen to devise a schematic using schematic edit, write a code using Verilog HDL (Hardware Description Language text editor and implements the circuit on Programmable Logic Device [PLD].The system has been successfully tested and implemented in hardware using Nexys 2 Digilent FPGA.

  12. Applied reaction dynamics: Efficient synthesis gas production via single collision partial oxidation of methane to CO on Rh(111)

    Science.gov (United States)

    Gibson, K. D.; Viste, M.; Sibener, S. J.

    2006-10-01

    Supersonic molecular beams have been used to determine the yield of CO from the partial oxidation of CH4 on a Rh(111) catalytic substrate, CH4+(1/2)O2→CO +2H2, as a function of beam kinetic energy. These experiments were done under ultrahigh vacuum conditions with concurrent molecular beams of O2 and CH4, ensuring that there was only a single collision for the CH4 to react with the surface. The fraction of CH4 converted is strongly dependent on the normal component of the incident beam's translational energy, and approaches unity for energies greater than ˜1.3eV. Comparison with a simplified model of the methane-Rh(111) reactive potential gives insight into the barrier for methane dissociation. These results demonstrate the efficient conversion of methane to synthesis gas, CO +2H2, are of interest in hydrogen generation, and have the optimal stoichiometry for subsequent utilization in synthetic fuel production (Fischer-Tropsch or methanol synthesis). Moreover, under the reaction conditions explored, no CO2 was detected, i.e., the reaction proceeded with the production of very little, if any, unwanted greenhouse gas by-products. These findings demonstrate the efficacy of overcoming the limitations of purely thermal reaction mechanisms by coupling nonthermal mechanistic steps, leading to efficient C-H bond activation with subsequent thermal heterogeneous reactions.

  13. An FPGA-Based Multiple-Axis Velocity Controller and Stepping Motors Drives Design

    Directory of Open Access Journals (Sweden)

    Lai Chiu-Keng

    2016-01-01

    Full Text Available A Field Programmable Gate Array based system is a great hardware platform to support the implementation of hardware controllers such as PID controller and fuzzy controller. It is also programmed as hardware accelerator to speed up the mathematic calculation and greatly enhance the performance as applied to motor drive and motion control. Furthermore, the open structure of FPGA-based system is suitable for those designs with the ability of parallel processing or soft code processor embedded. In this paper, we apply the FPGA to a multi-axis velocity controller design. The developed system integrated three functions inside the FPGA chip, which are respectively the stepping motor drive, the multi-axis motion controller and the motion planning. Furthermore, an embedded controller with a soft code processor compatible to 8051 micro-control unit (MCU is built to handle the data transfer between the FPGA board and host PC. The MCU is also used to initialize the motion control and run the interpolator. The designed system is practically applied to a XYZ motion platform which is driven by stepping motors to verify its performance.

  14. OpenCL-Based FPGA Accelerator for 3D FDTD with Periodic and Absorbing Boundary Conditions

    Directory of Open Access Journals (Sweden)

    Hasitha Muthumala Waidyasooriya

    2017-01-01

    Full Text Available Finite difference time domain (FDTD method is a very poplar way of numerically solving partial differential equations. FDTD has a low operational intensity so that the performances in CPUs and GPUs are often restricted by the memory bandwidth. Recently, deeply pipelined FPGA accelerators have shown a lot of success by exploiting streaming data flows in FDTD computation. In spite of this success, many FPGA accelerators are not suitable for real-world applications that contain complex boundary conditions. Boundary conditions break the regularity of the data flow, so that the performances are significantly reduced. This paper proposes an FPGA accelerator that computes commonly used absorbing and periodic boundary conditions in many 3D FDTD applications. Accelerator is designed using a “C-like” programming language called OpenCL (open computing language. As a result, the proposed accelerator can be customized easily by changing the software code. According to the experimental results, we achieved over 3.3 times and 1.5 times higher processing speed compared to the CPUs and GPUs, respectively. Moreover, the proposed accelerator is more than 14 times faster compared to the recently proposed FPGA accelerators that are capable of handling complex boundary conditions.

  15. FPGA-based data processing module design of on-board radiometric calibration in visible/near infrared bands

    Science.gov (United States)

    Zhou, Guoqing; Li, Chenyang; Yue, Tao; Liu, Na; Jiang, Linjun; Sun, Yue; Li, Mingyan

    2015-12-01

    FPGA technology has long been applied to on-board radiometric calibration data processing however the integration of FPGA program is not good enough. For example, some sensors compressed remote sensing images and transferred to ground station to calculate the calibration coefficients. It will affect the timeliness of on-board radiometric calibration. This paper designs an integrated flow chart of on-board radiometric calibration. Building FPGA-based radiometric calibration data processing modules uses system generator. Thesis focuses on analyzing the calculation accuracy of FPGA-based two-point method and verifies the feasibility of this method. Calibration data was acquired by hardware platform which was built using integrating sphere, CMOS camera (canon 60d), ASD spectrometers and light filter (center wavelength: 690nm, bandwidth: 45nm). The platform can simulate single-band on-board radiometric calibration data acquisition in visible/near infrared band. Making an experiment of calibration coefficients calculation uses obtained data and FPGA modules. Experimental results show that: the camera linearity is above 99% meeting the experimental requirement. Compares with MATLAB the calculation accuracy of two-point method by FPGA are as follows: the error of gain value is 0.0053%; the error of offset value is 0.00038719%. Those results meet experimental accuracy requirement.

  16. FPGA technology in instrumentation and related tools

    CERN Document Server

    Serrano, J

    2005-01-01

    Field Programmable Gate Arrays (FPGA) have become an alternative to traditional Digital Signal Processors (DSP) in many applications. In some cases, where high throughput is the main concern, an FPGA-based system may in fact be the only solution to fulfill the requirements. In the area of particle accelerators, FPGAs are used in many contexts, ranging from digital feedback loops for power converters and RF cavities to Digital Signal Processing for beam instrumentation. These designs harness the vast amount of logic resources inside FPGA chips to deliver unprecedented performance through parallelism and pipelining. After an introduction to the internal architecture of FPGAs and the design process, including advanced issues such as floor planning, we look at two important techniques to implement arithmetic in FPGAs: Distributed Arithmetic (DA) and the Coordinate Rotation DIgital Computer (CORDIC) algorithm. The goal is not to exhaust the list of Digital Signal Processing techniques for FPGAs, but rather to illu...

  17. Optoelectronic date acquisition system based on FPGA

    Science.gov (United States)

    Li, Xin; Liu, Chunyang; Song, De; Tong, Zhiguo; Liu, Xiangqing

    2015-11-01

    An optoelectronic date acquisition system is designed based on FPGA. FPGA chip that is EP1C3T144C8 of Cyclone devices from Altera corporation is used as the centre of logic control, XTP2046 chip is used as A/D converter, host computer that communicates with the date acquisition system through RS-232 serial communication interface are used as display device and photo resistance is used as photo sensor. We use Verilog HDL to write logic control code about FPGA. It is proved that timing sequence is correct through the simulation of ModelSim. Test results indicate that this system meets the design requirement, has fast response and stable operation by actual hardware circuit test.

  18. ADC and TDC implemented using FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Hansen, Sten; Shi, Zonghan; /Fermilab

    2007-11-01

    Several tests of FPGA devices programmed as analog waveform digitizers are discussed. The ADC uses the ramping-comparing scheme. A multi-channel ADC can be implemented with only a few resistors and capacitors as external components. A periodic logic levels are shaped by passive RC network to generate exponential ramps. The FPGA differential input buffers are used as comparators to compare the ramps with the input signals. The times at which these ramps cross the input signals are digitized by time-to-digital-converters (TDCs) implemented within the FPGA. The TDC portion of the logic alone has potentially a broad range of HEP/nuclear science applications. A 96-channel TDC card using FPGAs as TDCs being designed for the Fermilab MIPP electronics upgrade project is discussed. A deserializer circuit based on multisampling circuit used in the TDC, the 'Digital Phase Follower' (DPF) is also documented.

  19. Association between Multidrug-Resistant Tuberculosis and Risk Factors in China: Applying Partial Least Squares Path Modeling.

    Directory of Open Access Journals (Sweden)

    Yun-Xia Liu

    Full Text Available Multidrug-resistant tuberculosis (MDR-TB resulting from various factors has raised serious public health concerns worldwide. Identifying the ecological risk factors associated with MDR-TB is critical to its prevention and control. This study aimed to explore the association between the development of MDR-TB and the risk factors at the group-level (ecological risk factors in China.Data on MDR-TB in 120 counties were obtained from the National Tuberculosis Information Management System, and data on risk-factor variables were extracted from the Health Statistical Yearbook, provincial databases, and the meteorological bureau of each province (municipality. Partial Least Square Path Modeling was used to detect the associations.The median proportion of MDR-TB in new TB cases was 3.96% (range, 0-39.39%. Six latent factors were extracted from the ecological risk factors, which explained 27.60% of the total variance overall in the prevalence of MDR-TB. Based on the results of PLS-PM, TB prevention, health resources, health services, TB treatment, TB detection, geography and climate factors were all associated with the risk of MDR-TB, but socioeconomic factors were not significant.The development of MDR-TB was influenced by TB prevention, health resources, health services, TB treatment, TB detection, geography and climate factors. Such information may help us to establish appropriate public health intervention strategies to prevent and control MDR-TB and yield benefits to the entire public health system in China.

  20. FPGA Implementation of the stepwise shutdown system

    Energy Technology Data Exchange (ETDEWEB)

    Lotjonen, L.

    2012-07-01

    This report elaborates the design process of applications for field-programmable gate array (FPGA) devices. Brief introductions to EPGA technology and the design process are first given and then the design phases are walked through with the aid of a case study. FPGA is a programmable logic device that is programmed by the customer rather than the manufacturer. They are also usually re-programmable which enables updating their programming and otherwise modifying the design. There are also one-time programmable FPGAs that can be used when security issues require it. FPGA is said to be 'hardware designed like software', which means that the design process resembles software development but the end-product is considered a hardware application because the execution of the functions is entirely different from a microprocessor. This duality can give both the flexibility of software and the reliability of hardware. The FPGA design and verification and validation (V and V) methods for NPP safety systems have not yet matured because the technology is rather new in the field. Software development methods and stanfards can be used to some extent but the hardware aspects bring new challenges that cannot be tacled using purely software methods. International efforts are being made to development formal and consistent design and V and V methodology regulations for FPGA devices. A preventive safety function called Stepwise Shutdown System (SWS) was implemented on an Actel M1 IGLOO field-programmable gate array (FPGA) device. SWS is used to drive a process into a normal state if the process measurements deviate from the desired operating values. This can happen in case of process disturbances. The SWS implementation processfrom the reguirements to the functional device is elaborated. The design is tested via simulation and hardware testing. The case study is to be further expanded as a part of a master's thesis. (orig.)

  1. Development of a multitechnology FPGA: a reconfigurable architecture for photonic information processing

    Science.gov (United States)

    Mal, Prosenjit; Toshniwal, Kavita; Hawk, Chris; Bhadri, Prashant R.; Beyette, Fred R., Jr.

    2004-06-01

    Over the years, Field Programmable Gate Arrays (FPGAs) have made a profound impact on the electronics industry with rapidly improving semiconductor-manufacturing technology ranging from sub-micron to deep sub-micron processes and equally innovative CAD tools. Though FPGA has revolutionized programmable/reconfigurable digital logic technology, one limitation of current FPGA"s is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications (ex. analog devices, MEMS devices and microwave components). Over recent years, the growing trend has been towards the incorporation of non-traditional device technologies into traditional CMOS VLSI systems. The integration of these technologies requires a new kind of FPGA that can merge conventional FPGA technology with photonic and other multi-technology devices. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional electronic into photonic and multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems. This new technology will create a tremendous opportunity for applying the conventional programmable/reconfigurable hardware concepts in other disciplines like photonic information processing. To substantiate this novel architectural concept, we have fabricated proof-of-the-concept CMOS VLSI Multi-technology FPGA (MT-FPGA) chips that include both digital field programmable logic blocks and threshold programmable photoreceivers which are suitable for sensing optical signals. Results from these chips strongly support the feasibility of this new optoelectronic device concept.

  2. Design and implementation of a programming circuit in radiation-hardened FPGA

    Institute of Scientific and Technical Information of China (English)

    Wu Lihua; Han Xiaowei; Zhao Yan; Liu Zhongli; Yu Fang; Stanley L. Chen

    2011-01-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip.This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back.The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain.It not only saves area but also provides more flexible configuration operations.By configuring the proposed partial configuration control register,our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented.The hierarchical simulation scheme,optimization of the critical path and the elaborate layout plan make this circuit work well.Also,the radiation hardened by design programming point is introduced.This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process.The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back.Moreover,the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si),dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  3. Design and implementation of a programming circuit in radiation-hardened FPGA

    Science.gov (United States)

    Lihua, Wu; Xiaowei, Han; Yan, Zhao; Zhongli, Liu; Fang, Yu; Chen, Stanley L.

    2011-08-01

    We present a novel programming circuit used in our radiation-hardened field programmable gate array (FPGA) chip. This circuit provides the ability to write user-defined configuration data into an FPGA and then read it back. The proposed circuit adopts the direct-access programming point scheme instead of the typical long token shift register chain. It not only saves area but also provides more flexible configuration operations. By configuring the proposed partial configuration control register, our smallest configuration section can be conveniently configured as a single data and a flexible partial configuration can be easily implemented. The hierarchical simulation scheme, optimization of the critical path and the elaborate layout plan make this circuit work well. Also, the radiation hardened by design programming point is introduced. This circuit has been implemented in a static random access memory (SRAM)-based FPGA fabricated by a 0.5 μm partial-depletion silicon-on-insulator CMOS process. The function test results of the fabricated chip indicate that this programming circuit successfully realizes the desired functions in the configuration and read-back. Moreover, the radiation test results indicate that the programming circuit has total dose tolerance of 1 × 105 rad(Si), dose rate survivability of 1.5 × 1011 rad(Si)/s and neutron fluence immunity of 1 × 1014 n/cm2.

  4. Burst-Mode Asynchronous Controllers on FPGA

    Directory of Open Access Journals (Sweden)

    Duarte L. Oliveira

    2008-01-01

    Full Text Available FPGAs have been mainly used to design synchronous circuits. Asynchronous design on FPGAs is difficult because the resulting circuit may suffer from hazard problems. We propose a method that implements a popular class of asynchronous circuits, known as burst mode, on FPGAs based on look-up table architectures. We present two conditions that, if satisfied, guarantee essential hazard-free implementation on any LUT-based FPGA. By doing that, besides all the intrinsic advantages of asynchronous over synchronous circuits, they also take advantage of the shorter design time and lower cost associated with FPGA designs.

  5. FPGA Based Acceleration of Decimal Operations

    DEFF Research Database (Denmark)

    Nannarelli, Alberto

    2011-01-01

    Field Programmable Gate-Arrays (FPGAs) can efficiently implement application specific processors in nonconventional number systems, such as the decimal (Binary- Coded Decimal, or BCD) number system required for accounting accuracy in financial applications. The main purpose of this work is to show...... that applications requiring several decimal (BCD) operations can be accelerated by a processor implemented on a FPGA board connected to the computer by a standard bus. For the case of a telephone billing application, we demonstrate that even a basic implementation of the decimal processor on the FPGA, without...

  6. Synchro Controller of Radar on FPGA

    Institute of Scientific and Technical Information of China (English)

    JiangTie-zhen; ShiZhen-hua; WuShi-cai

    2003-01-01

    This paper mainly represents the realization of synchro controller based on the programmable logic devices FPGA by request of HF ground wave radar synchro controller under the instance of making the best of the virtues of FPGA.This design introduces the data communication between PC and synchro controller by I2C Bus, which can carry the synchronous signals' parameters to RAM of synchro controller,then according to the theory that the result of comparing counter value with signals' parameters is the needed wave,we produce all waves HF ground wave radar needs, moreover all waves are produced timesharing in order to save resources.

  7. Synchro Controller of Radar on FPGA

    Institute of Scientific and Technical Information of China (English)

    Jiang Tie-zhen; Shi Zhen-huat; Wu Shi-cai

    2003-01-01

    This paper mainly represents the realization of synchro controller based on the programmable logic devices FPGA by request of HF ground wave radar synchro controller under the instance of making the best of the virtues of FPGA.This design introduces the data communication between PC and synchro controller by I2C Bus, which can carry the syn-chronous signals' parameters to RAM of synchro controller,then according to the theory that the result of comparing counter value with signals' parameters is the needed wave,we produce all waves HF ground wave radar needs, moreover all waves are produced time-sharing in order to save re-sources.

  8. FPGA controlled artificial vascular system

    Directory of Open Access Journals (Sweden)

    Laqua D.

    2015-09-01

    Full Text Available Monitoring the oxygen saturation of an unborn child is an invasive procedure, so far. Transabdominal fetal pulse oximetry is a promising method under research, used to estimate the oxygen saturation of a fetus noninvasively. Due to the nature of the method, the fetal information needs to be extracted from a mixed signal. To properly evaluate signal processing algorithms, a phantom modeling fetal and maternal blood circuits and tissue layers is necessary. This paper presents an improved hardware concept for an artificial vascular system, utilizing an FPGA based CompactRIO System from National Instruments. The experimental model to simulate the maternal and fetal blood pressure curve consists of two identical hydraulic circuits. Each of these circuits consists of a pre-pressure system and an artificial vascular system. Pulse curves are generated by proportional valves, separating these two systems. The dilation of the fetal and maternal artificial vessels in tissue substitutes is measured by transmissive and reflective photoplethysmography. The measurement results from the pressure sensors and the transmissive optical sensors are visualized to show the functionality of the pulse generating systems. The trigger frequency for the maternal valve was set to 1 per second, the fetal valve was actuated at 0.7 per second for validation. The reflective curve, capturing pulsations of the fetal and maternal circuit, was obtained with a high power LED (905 nm as light source. The results show that the system generates pulse curves, similar to its physiological equivalent. Further, the acquired reflective optical signal is modulated by the alternating diameter of the tubes of both circuits, allowing for tests of signal processing algorithms.

  9. OrFPGA: An Empirical Performance Tuning Tool for FPGA Designs Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In this Phase II STTR project, RNET and its subcontractors are proposing to fully develop an empirical performance optimization tool called OrFPGA that efficiently...

  10. Comparison of partial least squares and lasso regression techniques as applied to laser-induced breakdown spectroscopy of geological samples

    Energy Technology Data Exchange (ETDEWEB)

    Dyar, M.D., E-mail: mdyar@mtholyoke.edu [Dept. of Astronomy, Mount Holyoke College, 50 College St., South Hadley, MA 01075 (United States); Carmosino, M.L.; Breves, E.A.; Ozanne, M.V. [Dept. of Astronomy, Mount Holyoke College, 50 College St., South Hadley, MA 01075 (United States); Clegg, S.M.; Wiens, R.C. [Los Alamos National Laboratory, P.O. Box 1663, MS J565, Los Alamos, NM 87545 (United States)

    2012-04-15

    A remote laser-induced breakdown spectrometer (LIBS) designed to simulate the ChemCam instrument on the Mars Science Laboratory Rover Curiosity was used to probe 100 geologic samples at a 9-m standoff distance. ChemCam consists of an integrated remote LIBS instrument that will probe samples up to 7 m from the mast of the rover and a remote micro-imager (RMI) that will record context images. The elemental compositions of 100 igneous and highly-metamorphosed rocks are determined with LIBS using three variations of multivariate analysis, with a goal of improving the analytical accuracy. Two forms of partial least squares (PLS) regression are employed with finely-tuned parameters: PLS-1 regresses a single response variable (elemental concentration) against the observation variables (spectra, or intensity at each of 6144 spectrometer channels), while PLS-2 simultaneously regresses multiple response variables (concentrations of the ten major elements in rocks) against the observation predictor variables, taking advantage of natural correlations between elements. Those results are contrasted with those from the multivariate regression technique of the least absolute shrinkage and selection operator (lasso), which is a penalized shrunken regression method that selects the specific channels for each element that explain the most variance in the concentration of that element. To make this comparison, we use results of cross-validation and of held-out testing, and employ unscaled and uncentered spectral intensity data because all of the input variables are already in the same units. Results demonstrate that the lasso, PLS-1, and PLS-2 all yield comparable results in terms of accuracy for this dataset. However, the interpretability of these methods differs greatly in terms of fundamental understanding of LIBS emissions. PLS techniques generate principal components, linear combinations of intensities at any number of spectrometer channels, which explain as much variance in the

  11. Comparison of partial least squares and lasso regression techniques as applied to laser-induced breakdown spectroscopy of geological samples

    Science.gov (United States)

    Dyar, M. D.; Carmosino, M. L.; Breves, E. A.; Ozanne, M. V.; Clegg, S. M.; Wiens, R. C.

    2012-04-01

    A remote laser-induced breakdown spectrometer (LIBS) designed to simulate the ChemCam instrument on the Mars Science Laboratory Rover Curiosity was used to probe 100 geologic samples at a 9-m standoff distance. ChemCam consists of an integrated remote LIBS instrument that will probe samples up to 7 m from the mast of the rover and a remote micro-imager (RMI) that will record context images. The elemental compositions of 100 igneous and highly-metamorphosed rocks are determined with LIBS using three variations of multivariate analysis, with a goal of improving the analytical accuracy. Two forms of partial least squares (PLS) regression are employed with finely-tuned parameters: PLS-1 regresses a single response variable (elemental concentration) against the observation variables (spectra, or intensity at each of 6144 spectrometer channels), while PLS-2 simultaneously regresses multiple response variables (concentrations of the ten major elements in rocks) against the observation predictor variables, taking advantage of natural correlations between elements. Those results are contrasted with those from the multivariate regression technique of the least absolute shrinkage and selection operator (lasso), which is a penalized shrunken regression method that selects the specific channels for each element that explain the most variance in the concentration of that element. To make this comparison, we use results of cross-validation and of held-out testing, and employ unscaled and uncentered spectral intensity data because all of the input variables are already in the same units. Results demonstrate that the lasso, PLS-1, and PLS-2 all yield comparable results in terms of accuracy for this dataset. However, the interpretability of these methods differs greatly in terms of fundamental understanding of LIBS emissions. PLS techniques generate principal components, linear combinations of intensities at any number of spectrometer channels, which explain as much variance in the

  12. ModelSim/Simulink Cosimulation and FPGA Realization of a Multiaxis Motion Controller

    Directory of Open Access Journals (Sweden)

    Ying-Shieh Kung

    2015-01-01

    Full Text Available This paper is to implement a multiaxis servo controller and a motion trajectory planning within one chip. At first, SoPC (system on a programmable chip technology which is composed of an Altera FPGA (field programmable gate arrays chip and an embedded soft-core Nios II processor is taken as the development of a multiaxis motion control IC. The multiaxis motion control IC has two modules. The first module is Nios II processor which realizes the motion trajectory planning by software. It includes the step, circular, window, star, and helical motion trajectory. The second module presents a function of the multiaxis position/speed/current controller IP (intellectual property by hardware. And VHDL (VHSIC Hardware Description Language is applied to describe the multiaxis servo controller behavior. Before the FPGA realization, a cosimulation work by ModelSim/Simulink is applied to test the VHDL code. Then, this IP combined by Nios II processor will be downloaded to FPGA. Therefore, a fully digital multiaxis motion controller can be realized by a single FPGA chip. Finally, to verify the effectiveness and correctness of the proposed multiaxis motion control IP, a three-axis motion platform (XYZ table is constructed and some experimental results are presented.

  13. FPGA Realization of Memory 10 Viterbi Decoder

    DEFF Research Database (Denmark)

    Paaske, Erik; Bach, Thomas Bo; Andersen, Jakob Dahl

    1997-01-01

    sequence mode when feedback from the Reed-Solomon decoder is available. The Viterbi decoder is realized using two Altera FLEX 10K50 FPGA's. The overall operating speed is 30 kbit/s, and since up to three iterations are performed for each frame and only one decoder is used, the operating speed...

  14. FPGA Sequencer for Radar Altimeter Applications

    Science.gov (United States)

    Berkun, Andrew C.; Pollard, Brian D.; Chen, Curtis W.

    2011-01-01

    A sequencer for a radar altimeter provides accurate attitude information for a reliable soft landing of the Mars Science Laboratory (MSL). This is a field-programmable- gate-array (FPGA)-only implementation. A table loaded externally into the FPGA controls timing, processing, and decision structures. Radar is memory-less and does not use previous acquisitions to assist in the current acquisition. All cycles complete in exactly 50 milliseconds, regardless of range or whether a target was found. A RAM (random access memory) within the FPGA holds instructions for up to 15 sets. For each set, timing is run, echoes are processed, and a comparison is made. If a target is seen, more detailed processing is run on that set. If no target is seen, the next set is tried. When all sets have been run, the FPGA terminates and waits for the next 50-millisecond event. This setup simplifies testing and improves reliability. A single vertex chip does the work of an entire assembly. Output products require minor processing to become range and velocity. This technology is the heart of the Terminal Descent Sensor, which is an integral part of the Entry Decent and Landing system for MSL. In addition, it is a strong candidate for manned landings on Mars or the Moon.

  15. FPGA adders: performance evaluation and optimal design

    OpenAIRE

    Xing, S.; Yu, WWH

    1998-01-01

    Delay models and cost analyses developed for ASIC technology are not useful in designing and implementing FPGA devices. The authors discuss costs and operational delays of fixed-point adders on Xilinx 4000 series devices and propose timing models and optimization schemes for carry-skip and carry-select adders.

  16. TOT Measurement Implemented in FPGA TDC

    CERN Document Server

    Fan, Huanhuan; Liu, Shubin; An, Qi

    2015-01-01

    Time measurement plays a crucial rule for the purpose of particle identification in high energy physical experiments. With the upgrading of physical goal and the developing of electronics, modern time measurement system meets the requirement of excellent resolution specification as well as high integrity. Due to Field Programmable Gate Array (FPGA), FPGA time-to-digital converter (TDC) becomes one of mature and prominent time measurement methods in recent years. For correcting time-walk effect caused by leading timing, time-over-threshold (TOT) measurement should be added in the FPGA TDC. TOT can be obtained by measuring the interval time of signal leading and trailing edge. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels can be used at the same time, one for leading, the other for trailing. However, this method will increase the amount of used FPGA resource and reduce the TDC's integrity unavoidably...

  17. Testing Microshutter Arrays Using Commercial FPGA Hardware

    Science.gov (United States)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  18. DYNAMIC LABELING BASED FPGA DELAY OPTIMIZATION ALGORITHM

    Institute of Scientific and Technical Information of China (English)

    吕宗伟; 林争辉; 张镭

    2001-01-01

    DAG-MAP is an FPGA technology mapping algorithm for delay optimization and the labeling phase is the algorithm's kernel. This paper studied the labeling phase and presented an improved labeling method. It is shown through the experimental results on MCNC benchmarks that the improved method is more effective than the original method while the computation time is almost the same.

  19. Design Approach for Fault Tolerance in FPGA Architecture

    Directory of Open Access Journals (Sweden)

    Ms. Shweta S. Meshram

    2011-03-01

    Full Text Available Failures of nano-metric technologies owing to defects and shrinking process tolerances give rise tosignificant challenges for IC testing. In recent years the application space of reconfigurable devices hasgrown to include many platforms with a strong need for fault tolerance. While these systems frequentlycontain hardware redundancy to allow for continued operation in the presence of operational faults, theneed to recover faulty hardware and return it to full functionality quickly and efficiently is great. Inaddition to providing functional density, FPGAs provide a level of fault tolerance generally not found inmask-programmable devices by including the capability to reconfigure around operational faults in thefield. Reliability and process variability are serious issues for FPGAs in the future. With advancement inprocess technology, the feature size is decreasing which leads to higher defect densities, moresophisticated techniques at increased costs are required to avoid defects. If nano-technology fabricationare applied the yield may go down to zero as avoiding defect during fabrication will not be a feasibleoption Hence, feature architecture have to be defect tolerant. In regular structure like FPGA, redundancyis commonly used for fault tolerance. In this work we present a solution in which configuration bit-streamof FPGA is modified by a hardware controller that is present on the chip itself. The technique usesredundant device for replacing faulty device and increases the yield.

  20. An FPGA-based open platform for ultrasound biomicroscopy.

    Science.gov (United States)

    Qiu, Weibao; Yu, Yanyan; Tsang, Fu; Sun, Lei

    2012-07-01

    Ultrasound biomicroscopy (UBM) has been extensively applied to preclinical studies in small animal models. Individual animal study is unique and requires different utilization of the UBM system to accommodate different transducer characteristics, data acquisition strategies, signal processing, and image reconstruction methods. There is a demand for a flexible and open UBM platform to allow users to customize the system for various studies and have full access to experimental data. This paper presents the development of an open UBM platform (center frequency 20 to 80 MHz) for various preclinical studies. The platform design was based on a field-programmable gate array (FPGA) embedded in a printed circuit board to achieve B-mode imaging and directional pulsed-wave Doppler. Instead of hardware circuitry, most functions of the platform, such as filtering, envelope detection, and scan conversion, were achieved by FPGA programs; thus, the system architecture could be easily modified for specific applications. In addition, a novel digital quadrature demodulation algorithm was implemented for fast and accurate Doppler profiling. Finally, test results showed that the platform could offer a minimum detectable signal of 25 μV, allowing a 51 dB dynamic range at 47 dB gain, and real-time imaging at more than 500 frames/s. Phantom and in vivo imaging experiments were conducted and the results demonstrated good system performance.

  1. Optimization on fixed low latency implementation of GBT protocol in FPGA

    CERN Document Server

    Chen, Kai; Wu, Weihao; Xu, Hao; Yao, Lin

    2016-01-01

    For accelerator physics experiment, the Front-End (FE) electronics components are subjected to a radiation background. GigaBit Transceiver (GBT) architecture is a protocol developed by CERN, to provide high-speed (4.8 Gbps) radiation hard optical link for data transmission. To use GBT protocol on the FE detector, GBTX ASIC is designed. For the back-end side, GBT-FPGA is a project launched by CERN, to provide the implementation of GBT protocol in different types of Field Programmable Gate Arrays (FPGA). For ATLAS experiment, GBT protocol is used by FE electronics of several sub-detectors. Back-End exchanges data and commands like TTC information with FE. The low-latency requirement is important especially for the trigger data path. In this paper, we report several changes to the GBT-FPGA IP core. Some optimizations are applied to achieve a lower latency. The adding of multiplexer let GBT mode can be switched between forward error correction mode and wide mode, without FPGA reprogramming. The clock distribution...

  2. A Test Methodology for Determining Space-Readiness of Xilinx SRAM-Based FPGA Designs

    Energy Technology Data Exchange (ETDEWEB)

    Quinn, Heather M [Los Alamos National Laboratory; Graham, Paul S [Los Alamos National Laboratory; Morgan, Keith S [Los Alamos National Laboratory; Caffrey, Michael P [Los Alamos National Laboratory

    2008-01-01

    Using reconfigurable, static random-access memory (SRAM) based field-programmable gate arrays (FPGAs) for space-based computation has been an exciting area of research for the past decade. Since both the circuit and the circuit's state is stored in radiation-tolerant memory, both could be alterd by the harsh space radiation environment. Both the circuit and the circuit's state can be prote cted by triple-moduler redundancy (TMR), but applying TMR to FPGA user designs is often an error-prone process. Faulty application of TMR could cause the FPGA user circuit to output incorrect data. This paper will describe a three-tiered methodology for testing FPGA user designs for space-readiness. We will describe the standard approach to testing FPGA user designs using a particle accelerator, as well as two methods using fault injection and a modeling tool. While accelerator testing is the current 'gold standard' for pre-launch testing, we believe the use of fault injection and modeling tools allows for easy, cheap and uniform access for discovering errors early in the design process.

  3. A Correctness Verification Technique for Commercial FPGA Synthesis Tools

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of); Choi, Jong Gyun; Kim, Jang Yeol; Lee, Jang Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2014-10-15

    Once the FPGA (Filed-Programmable Gate Array) designers designs Verilog programs, the commercial synthesis tools automatically translate the Verilog programs into EDIF programs so that the designers can have largely focused on HDL designs for correctness of functionality. Nuclear regulation authorities, however, require more considerate demonstration of the correctness and safety of mechanical synthesis processes of FPGA synthesis tools, even if the FPGA industry have acknowledged them empirically as correct and safe processes and tools. In order to assure of the safety, the industry standards for the safety of electronic/electrical devices, such as IEC 61508 and IEC 60880, recommend using the formal verification technique. There are several formal verification tools (i.e., 'FormalPro' 'Conformal' 'Formality' and so on) to verify the correctness of translation from Verilog into EDIF programs, but it is too expensive to use and hard to apply them to the works of 3rd-party developers. This paper proposes a formal verification technique which can contribute to the correctness demonstration in part. It formally checks the behavioral equivalence between Verilog and subsequently synthesized Net list with the VIS verification system. A Net list is an intermediate output of FPGA synthesis process, and EDIF is used as a standard format of Net lists. If the formal verification succeeds, then we can assure that the synthesis process from Verilog into Net list worked correctly at least for the Verilog used. In order to support the formal verification, we developed the mechanical translator 'EDIFtoBLIFMV,' which translates EDIF into BLIF-MV as an input front-end of VIS system, while preserving their behavior equivalence.. We performed the case study with an example of a preliminary version of RPS in a Korean nuclear power plant in order to provide the efficiency of the proposed formal verification technique and implemented translator. It

  4. Experimental 3D Asynchronous Field Programmable Gate Array (FPGA)

    Science.gov (United States)

    2015-03-01

    EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) CORNELL UNIVERSITY MARCH 2015 FINAL TECHNICAL REPORT APPROVED FOR PUBLIC...From - To) OCT 2011 – OCT 2014 4. TITLE AND SUBTITLE EXPERIMENTAL 3D ASYNCHRONOUS FIELD PROGRAMMABLE GATE ARRAY ( FPGA ) 5a. CONTRACT NUMBER...in collaboration with Albany’s College of Nanoscale Science and Engineering. 15. SUBJECT TERMS 3D Technology, vertical interconnects, AFPGA, FPGA

  5. RSA Power Analysis Obfuscation: A Dynamic FPGA Architecture

    Science.gov (United States)

    2012-03-01

    research provides a VHDL coded dynamic architecture for synthesization on a Xilinx Virtex-5 FPGA. This architecture provides two-way communication...Component Under Test (CUT) is the dynamic RSA implementation. This dynamic hardware is synthesized from VHDL onto a Xilinx Virtex-5 FPGA. The built in...The hardware platform used for this research is a the Xil- inx Virtex-5 FX FPGA. VHDL code is synthesized using the Xilinx design suite and downloaded

  6. Research and development of infrared object detection system based on FPGA

    Science.gov (United States)

    Zhao, Jianhui; He, Jianwei; Wang, Pengpeng; Li, Fan

    2009-07-01

    Infrared object detection is an important technique of digital image processing. It is widely used in automatic navigation, intelligent video surveillance systems, traffic detection, medical image processing etc. Infrared object detection system requires large storage and high speed processing technology. The current development trend is the system which can be achieved by hardware in real-time with fewer operations and higher performance. As a main large-scale programmable specific integrated circuit, field programmable gate array (FPGA) can meet all the requirements of high speed image processing, with the characteristics of simple algorithm realization, easy programming, good portability and inheritability. So it could get better result by using FPGA to infrared object detection system. According to the requirements, the infrared object detection system is designed on FPGA. By analyzing some of the main algorithms of object detection, two new object detection algorithms called integral compare algorithm (ICA) and gradual approach centroid algorithm (GACA) are presented. The system design applying FPGA in hardware can implement high speed processing technology, which brings the advantage of both performance and flexibility. ICA is a new type of denoising algorithm with advantage of lower computation complexity and less execution time. What is more important is that this algorithm can be implemented in FPGA expediently. Base on image preprocessing of ICA, GACA brings high positioning precision with advantage of insensitivity to the initial value and fewer times of convergence iteration. The experiments indicate that the infrared object detection system can implement high speed infrared object detecting in real-time, with high antijamming ability and high precision. The progress of Verilog-HDL and its architecture are introduced in this paper. Considering the engineering application, this paper gives the particular design idea and the flow of this method

  7. Continuous Attributes Discretization Algorithm based on FPGA

    Directory of Open Access Journals (Sweden)

    Guoqiang Sun

    2013-07-01

    Full Text Available The paper addresses the problem of Discretization of continuous attributes in rough set. Discretization of continuous attributes is an important part of rough set theory because most of data that we usually gain are continuous data. In order to improve processing speed of discretization, we propose a FPGA-based discretization algorithm of continuous attributes making use of the speed advantage of FPGA. Combined attributes dependency degree of rough ret, the discretization system was divided into eight modules according to block design. This method can save much time of pretreatment in rough set and improve operation efficiency. Extensive experiments on a certain fighter fault diagnosis validate the effectiveness of the algorithm.  

  8. 3D FFTs on a Single FPGA.

    Science.gov (United States)

    Humphries, Benjamin; Zhang, Hansen; Sheng, Jiayi; Landaverde, Raphael; Herbordt, Martin C

    2014-05-01

    The 3D FFT is critical in many physical simulations and image processing applications. On FPGAs, however, the 3D FFT was thought to be inefficient relative to other methods such as convolution-based implementations of multi-grid. We find the opposite: a simple design, operating at a conservative frequency, takes 4μs for 16(3), 21μs for 32(3), and 215μs for 64(3) single precision data points. The first two of these compare favorably with the 25μs and 29μs obtained running on a current Nvidia GPU. Some broader significance is that this is a critical piece in implementing a large scale FPGA-based MD engine: even a single FPGA is capable of keeping the FFT off of the critical path for a large fraction of possible MD simulations.

  9. An FPGA helix tracking algorithm for PANDA

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Galuska, Martin; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liang, Yutie; Liu, Ming; Spruck, Bjoern [Justus Liebig University Giessen (Germany); Spataro, Stefano [University of Torino (Italy)

    2010-07-01

    An online track finder for the PANDA experiment at the future FAIR facility was developed and tested. The central Panda tracking detectors for charged particles will consist of a silicon based micro vertex detector (MVD, 5-7 hits/track) and possibly of a straw tube tracker (STT, 15 double layers of straws). Due to the solenoidal magnetic field, tracks of charged particles can be parametrized by a helix (if neglecting energy loss). The algorithm works in several steps. Perpendicular to the beam direction the projection of the tracks is equivalent to a circle. Thus, first a conformal transformation will be used to convert the circles to straight lines. Second, a Hough transform is used to find the straight lines by a peak finding algorithm. Along the beam direction, a different Hough transformation is used. As the algorithm was developed for an FPGA, it uses lookup tables. Possible FPGA implementation is discussed.

  10. Guide to FPGA Implementation of Arithmetic Functions

    CERN Document Server

    Deschamps, Jean-Pierre; Cantó, Enrique

    2012-01-01

    This book is designed both for FPGA users interested in developing new, specific components - generally for reducing execution times –and IP core designers interested in extending their catalog of specific components.  The main focus is circuit synthesis and the discussion shows, for example, how a given algorithm executing some complex function can be translated to a synthesizable circuit description, as well as which are the best choices the designer can make to reduce the circuit cost, latency, or power consumption.  This is not a book on algorithms.  It is a book that shows how to translate efficiently an algorithm to a circuit, using techniques such as parallelism, pipeline, loop unrolling, and others.  Numerous examples of FPGA implementation are described throughout this book and the circuits are modeled in VHDL. Complete and synthesizable source files are available for download.

  11. An FPGA-based Torus Communication Network

    CERN Document Server

    Pivanti, Marcello; Simma, Hubert

    2010-01-01

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results.

  12. An FPGA-Based Electronic Cochlea

    Directory of Open Access Journals (Sweden)

    M. P. Leong

    2003-06-01

    Full Text Available A module generator which can produce an FPGA-based implementation of an electronic cochlea filter with arbitrary precision is presented. Although hardware implementations of electronic cochlea models have traditionally used analog VLSI as the implementation medium due to their small area, high speed, and low power consumption, FPGA-based implementations offer shorter design times, improved dynamic range, higher accuracy, and a simpler computer interface. The tool presented takes filter coefficients as input and produces a synthesizable VHDL description of an application-optimized design as output. Furthermore, the tool can use simulation test vectors in order to determine the appropriate scaling of the fixed point precision parameters for each filter. The resulting model can be used as an accelerator for research in audition or as the front-end for embedded auditory signal processing systems. The application of this module generator to a real-time cochleagram display is also presented.

  13. An FPGA-based torus communication network

    Energy Technology Data Exchange (ETDEWEB)

    Pivanti, Marcello; Schifano, Sebastiano Fabio [INFN, Ferrara (Italy); Ferrara Univ. (Italy); Simma, Hubert [DESY, Zeuthen (Germany). John von Neumann-Institut fuer Computing NIC

    2011-02-15

    We describe the design and FPGA implementation of a 3D torus network (TNW) to provide nearest-neighbor communications between commodity multi-core processors. The aim of this project is to build up tightly interconnected and scalable parallel systems for scientific computing. The design includes the VHDL code to implement on latest FPGA devices a network processor, which can be accessed by the CPU through a PCIe interface and which controls the external PHYs of the physical links. Moreover, a Linux driver and a library implementing custom communication APIs are provided. The TNW has been successfully integrated in two recent parallel machine projects, QPACE and AuroraScience. We describe some details of the porting of the TNW for the AuroraScience system and report performance results. (orig.)

  14. Embedded FPGA platform for fast steering mirror and optical inertial reference unit applications

    Science.gov (United States)

    Wasson, Steven; Morgan, Felix; Eckelkamp-Baker, Dan

    2011-05-01

    Applied Technology Associates (ATA) is developing a field-programmable gate array (FPGA) based processing platform to transition our state-of-the-art fast-steering mirrors (FSM's) and optical inertial reference units (OIRU's) from the laboratory environment to field operation. This platform offers an abundance of reconfigurable high-speed digital input/output (I/O) and parallel hardware-based processing resources in a compact size, weight, and power (SWaP) form factor with a path to a radiation-hardened version. The FPGA's high-speed I/O can be used to acquire sensor data and drive actuators with minimal latency while the FPGA's processing resources can efficiently realize signal processing and control algorithms with deterministic timing. These features allow high sampling rates between 20 KHz - 30 KHz. This will result in higher open-loop bandwidths in our FSM's and OIRU's. This will subsequently result in improved disturbance rejection in our FSM's and improved base motion jitter rejection in our OIRU's. This paper briefly presents the embedded system requirements of ATA's FSM's and OIRU's and the FPGA-based computational architecture derived to meet these requirements. It then describes the FPGA cores and embedded software that have been developed to efficiently realize interfacing, signal processing, and data collection tasks. Special attention is given to ATA's high-performance floating-point co-processor and innovative design approach that translates signal processing and control algorithms developed in MATLAB®/Simulink® into their equivalent implementation on the co-processor.

  15. A FPGA Implementation of JPEG Baseline Encoder for Wearable Devices.

    Science.gov (United States)

    Li, Yuecheng; Jia, Wenyan; Luan, Bo; Mao, Zhi-Hong; Zhang, Hong; Sun, Mingui

    2015-04-01

    In this paper, an efficient field-programmable gate array (FPGA) implementation of the JPEG baseline image compression encoder is presented for wearable devices in health and wellness applications. In order to gain flexibility in developing FPGA-specific software and balance between real-time performance and resources utilization, A High Level Synthesis (HLS) tool is utilized in our system design. An optimized dataflow configuration with a padding scheme simplifies the timing control for data transfer. Our experiments with a system-on-chip multi-sensor system have verified our FPGA implementation with respect to real-time performance, computational efficiency, and FPGA resource utilization.

  16. FPGA Flash Memory High Speed Data Acquisition

    Science.gov (United States)

    Gonzalez, April

    2013-01-01

    The purpose of this research is to design and implement a VHDL ONFI Controller module for a Modular Instrumentation System. The goal of the Modular Instrumentation System will be to have a low power device that will store data and send the data at a low speed to a processor. The benefit of such a system will give an advantage over other purchased binary IP due to the capability of allowing NASA to re-use and modify the memory controller module. To accomplish the performance criteria of a low power system, an in house auxiliary board (Flash/ADC board), FPGA development kit, debug board, and modular instrumentation board will be jointly used for the data acquisition. The Flash/ADC board contains four, 1 MSPS, input channel signals and an Open NAND Flash memory module with an analog to digital converter. The ADC, data bits, and control line signals from the board are sent to an Microsemi/Actel FPGA development kit for VHDL programming of the flash memory WRITE, READ, READ STATUS, ERASE, and RESET operation waveforms using Libero software. The debug board will be used for verification of the analog input signal and be able to communicate via serial interface with the module instrumentation. The scope of the new controller module was to find and develop an ONFI controller with the debug board layout designed and completed for manufacture. Successful flash memory operation waveform test routines were completed, simulated, and tested to work on the FPGA board. Through connection of the Flash/ADC board with the FPGA, it was found that the device specifications were not being meet with Vdd reaching half of its voltage. Further testing showed that it was the manufactured Flash/ADC board that contained a misalignment with the ONFI memory module traces. The errors proved to be too great to fix in the time limit set for the project.

  17. An FPGA-based reconfigurable DDC algorithm

    Science.gov (United States)

    Juszczyk, B.; Kasprowicz, G.

    2016-09-01

    This paper describes implementation of reconfigurable digital down converter in an FPGA structure. System is designed to work with quadrature signals. One of the main criteria of the project was to provied wide range of reconfiguration in order to fulfill various application rage. Potential applications include: software defined radio receiver, passive noise radars and measurement data compression. This document contains general system overview, short description of hardware used in the project and gateware implementation.

  18. TOT measurement implemented in FPGA TDC

    Science.gov (United States)

    Fan, Huan-Huan; Cao, Ping; Liu, Shu-Bin; An, Qi

    2015-11-01

    Time measurement plays a crucial role for the purpose of particle identification in high energy physics experiments. With increasingly demanding physics goals and the development of electronics, modern time measurement systems need to meet the requirement of excellent resolution specification as well as high integrity. Based on Field Programmable Gate Arrays (FPGAs), FPGA time-to-digital converters (TDCs) have become one of the most mature and prominent time measurement methods in recent years. For correcting the time-walk effect caused by leading timing, a time-over-threshold (TOT) measurement should be added to the FPGA TDC. TOT can be obtained by measuring the interval between the signal leading and trailing edges. Unfortunately, a traditional TDC can recognize only one kind of signal edge, the leading or the trailing. Generally, to measure the interval, two TDC channels need to be used at the same time, one for leading, the other for trailing. However, this method unavoidably increases the amount of FPGA resources used and reduces the TDC's integrity. This paper presents one method of TOT measurement implemented in a Xilinx Virtex-5 FPGA. In this method, TOT measurement can be achieved using only one TDC input channel. The consumed resources and time resolution can both be guaranteed. Testing shows that this TDC can achieve resolution better than 15ps for leading edge measurement and 37 ps for TOT measurement. Furthermore, the TDC measurement dead time is about two clock cycles, which makes it good for applications with higher physics event rates. Supported by National Natural Science Foundation of China (11079003, 10979003)

  19. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  20. AREA OPTIMIZED FPGA IMPLEMENTATION OF ADAPTIVE BEAMFORMER

    Directory of Open Access Journals (Sweden)

    Harpreet Kaur

    2012-06-01

    Full Text Available Quadratic Rotation decomposition (QRD based recursive least squares (RLS algorithm can be used in variety of communication applications and its low complexity implementation can be of interest. In this paper we have presented an application of QRD based RLS algorithm using Coordinate Rotation by Digital Computer (CORDIC operator for implementing an adaptive beamformer. FPGA resource estimates along with actual implementation results have been presented and are being compared with its existing implementation.

  1. Implementation of Huffman Decoder on Fpga

    OpenAIRE

    Safia Amir Dahri; Dr Abdul Fattah Chandio

    2016-01-01

    Lossless data compression algorithm is most widely used algorithm in data transmission, reception and storage systems in order to increase data rate, speed and save lots of space on storage devices. Now-a-days, different algorithms are implemented in hardware to achieve benefits of hardware realizations. Hardware implementation of algorithms, digital signal processing algorithms and filter realization is done on programmable devices i.e. FPGA. In lossless data compression algorith...

  2. Active Cancellation of Acoustical Resonances with an FPGA FIR Filter

    CERN Document Server

    Ryou, Albert

    2016-01-01

    We present a novel approach to enhancing the bandwidth of a feedback-controlled mechanical system by digitally canceling acoustical resonances (poles) and anti-resonances (zeros) in the open-loop response via an FPGA FIR filter. By performing a real-time convolution of the feedback error signal with an inverse filter, we can suppress arbitrarily many poles and zeros below 100 kHz, each with a linewidth down to 10 Hz. We demonstrate the efficacy of this technique by canceling the ten largest mechanical resonances and anti-resonances of a high-finesse optical resonator, thereby enhancing the unity gain frequency by more than an order of magnitude. This approach is applicable to a broad array of stabilization problems including optical resonators, external cavity diode lasers, and scanning tunneling microscopes, and points the way to applying modern optimal control techniques to intricate linear acoustical systems.es to intricate linear acoustical systems.

  3. Active cancellation of acoustical resonances with an FPGA FIR filter

    Science.gov (United States)

    Ryou, Albert; Simon, Jonathan

    2017-01-01

    We present a novel approach to enhancing the bandwidth of a feedback-controlled mechanical system by digitally canceling acoustical resonances (poles) and anti-resonances (zeros) in the open-loop response via an FPGA FIR filter. By performing a real-time convolution of the feedback error signal with an inverse filter, we can suppress arbitrarily many poles and zeros below 100 kHz, each with a linewidth down to 10 Hz. We demonstrate the efficacy of this technique by canceling the ten largest mechanical resonances and anti-resonances of a high-finesse optical resonator, thereby enhancing the unity gain frequency by more than an order of magnitude. This approach is applicable to a broad array of stabilization problems including optical resonators, external cavity diode lasers, and scanning tunneling microscopes and points the way to applying modern optimal control techniques to intricate linear acoustical systems.

  4. Active cancellation of acoustical resonances with an FPGA FIR filter.

    Science.gov (United States)

    Ryou, Albert; Simon, Jonathan

    2017-01-01

    We present a novel approach to enhancing the bandwidth of a feedback-controlled mechanical system by digitally canceling acoustical resonances (poles) and anti-resonances (zeros) in the open-loop response via an FPGA FIR filter. By performing a real-time convolution of the feedback error signal with an inverse filter, we can suppress arbitrarily many poles and zeros below 100 kHz, each with a linewidth down to 10 Hz. We demonstrate the efficacy of this technique by canceling the ten largest mechanical resonances and anti-resonances of a high-finesse optical resonator, thereby enhancing the unity gain frequency by more than an order of magnitude. This approach is applicable to a broad array of stabilization problems including optical resonators, external cavity diode lasers, and scanning tunneling microscopes and points the way to applying modern optimal control techniques to intricate linear acoustical systems.

  5. Cycle accurate and cycle reproducible memory for an FPGA based hardware accelerator

    Science.gov (United States)

    Asaad, Sameh W.; Kapur, Mohit

    2016-03-15

    A method, system and computer program product are disclosed for using a Field Programmable Gate Array (FPGA) to simulate operations of a device under test (DUT). The DUT includes a device memory having a number of input ports, and the FPGA is associated with a target memory having a second number of input ports, the second number being less than the first number. In one embodiment, a given set of inputs is applied to the device memory at a frequency Fd and in a defined cycle of time, and the given set of inputs is applied to the target memory at a frequency Ft. Ft is greater than Fd and cycle accuracy is maintained between the device memory and the target memory. In an embodiment, a cycle accurate model of the DUT memory is created by separating the DUT memory interface protocol from the target memory storage array.

  6. FPGA Implementation of Heart Rate Monitoring System.

    Science.gov (United States)

    Panigrahy, D; Rakshit, M; Sahu, P K

    2016-03-01

    This paper describes a field programmable gate array (FPGA) implementation of a system that calculates the heart rate from Electrocardiogram (ECG) signal. After heart rate calculation, tachycardia, bradycardia or normal heart rate can easily be detected. ECG is a diagnosis tool routinely used to access the electrical activities and muscular function of the heart. Heart rate is calculated by detecting the R peaks from the ECG signal. To provide a portable and the continuous heart rate monitoring system for patients using ECG, needs a dedicated hardware. FPGA provides easy testability, allows faster implementation and verification option for implementing a new design. We have proposed a five-stage based methodology by using basic VHDL blocks like addition, multiplication and data conversion (real to the fixed point and vice-versa). Our proposed heart rate calculation (R-peak detection) method has been validated, using 48 first channel ECG records of the MIT-BIH arrhythmia database. It shows an accuracy of 99.84%, the sensitivity of 99.94% and the positive predictive value of 99.89%. Our proposed method outperforms other well-known methods in case of pathological ECG signals and successfully implemented in FPGA.

  7. FPGA Trigger System to Run Klystrons

    Energy Technology Data Exchange (ETDEWEB)

    Gray, Darius; /Texas A-M /SLAC

    2010-08-25

    The Klystron Department is in need of a new trigger system to update the laboratory capabilities. The objective of the research is to develop the trigger system using Field Programmable Gate Array (FPGA) technology with a user interface that will allow one to communicate with the FPGA via a Universal Serial Bus (USB). This trigger system will be used for the testing of klystrons. The key materials used consists of the Xilinx Integrated Software Environment (ISE) Foundation, a Programmable Read Only Memory (Prom) XCF04S, a Xilinx Spartan 3E 35S500E FPGA, Xilinx Platform Cable USB II, a Printed Circuit Board (PCB), a 100 MHz oscillator, and an oscilloscope. Key considerations include eight triggers, two of which have variable phase shifting capabilities. Once the project was completed the output signals were able to be manipulated via a Graphical User Interface by varying the delay and width of the signal. This was as planned; however, the ability to vary the phase was not completed. Future work could consist of being able to vary the phase. This project will give the operators in the Klystron Department more flexibility to run various tests.

  8. FPGA remote update for nuclear environments

    Energy Technology Data Exchange (ETDEWEB)

    Fernandes, Ana; Pereira, Rita C.; Sousa, Jorge; Carvalho, Paulo F.; Correia, Miguel; Rodrigues, Antonio P.; Carvalho, Bernardo B.; Goncalves, Bruno [Instituto de Plasmasbe Fusao Nuclear, Instituto Superior Tecnico, Universidade de Lisboa, 1049-001 Lisboa, (Portugal); Correia, Carlos M.B.A. [Centro de Instrumentacao, Dept. de Fisica, Universidade de Coimbra, 3004-516 Coimbra, (Portugal)

    2015-07-01

    The Instituto de Plasmas e Fusao Nuclear (IPFN) has developed dedicated re-configurable modules based on field programmable gate array (FPGA) devices for several nuclear fusion machines worldwide. Moreover, new Advanced Telecommunication Computing Architecture (ATCA) based modules developed by IPFN are already included in the ITER catalogue. One of the requirements for re-configurable modules operating in future nuclear environments including ITER is the remote update capability. Accordingly, this work presents an alternative method for FPGA remote programing to be implemented in new ATCA based re-configurable modules. FPGAs are volatile devices and their programming code is usually stored in dedicated flash memories for properly configuration during module power-on. The presented method is capable to store new FPGA codes in Serial Peripheral Interface (SPI) flash memories using the PCIexpress (PCIe) network established on the ATCA back-plane, linking data acquisition endpoints and the data switch blades. The method is based on the Xilinx Quick Boot application note, adapted to PCIe protocol and ATCA based modules. (authors)

  9. Implementing a Digital Phasemeter in an FPGA

    Science.gov (United States)

    Rao, Shanti R.

    2008-01-01

    Firmware for implementing a digital phasemeter within a field-programmable gate array (FPGA) has been devised. In the original application of this firmware, the phase that one seeks to measure is the difference between the phases of two nominally-equal-frequency heterodyne signals generated by two interferometers. In that application, zero-crossing detectors convert the heterodyne signals to trains of rectangular pulses, the two pulse trains are fed to a fringe counter (the major part of the phasemeter) controlled by a clock signal having a frequency greater than the heterodyne frequency, and the fringe counter computes a time-averaged estimate of the difference between the phases of the two pulse trains. The firmware also does the following: Causes the FPGA to compute the frequencies of the input signals; Causes the FPGA to implement an Ethernet (or equivalent) transmitter for readout of phase and frequency values; and Provides data for use in diagnosis of communication failures. The readout rate can be set, by programming, to a value between 250 Hz and 1 kHz. Network addresses can be programmed by the user.

  10. Implementation of Huffman Decoder on Fpga

    Directory of Open Access Journals (Sweden)

    Safia Amir Dahri

    2016-01-01

    Full Text Available Lossless data compression algorithm is most widely used algorithm in data transmission, reception and storage systems in order to increase data rate, speed and save lots of space on storage devices. Now-a-days, different algorithms are implemented in hardware to achieve benefits of hardware realizations. Hardware implementation of algorithms, digital signal processing algorithms and filter realization is done on programmable devices i.e. FPGA. In lossless data compression algorithms, Huffman algorithm is most widely used because of its variable length coding features and many other benefits. Huffman algorithms are used in many applications in software form, e.g. Zip and Unzip, communication, etc. In this paper, Huffman algorithm is implemented on Xilinx Spartan 3E board. This FPGA is programmed by Xilinx tool, Xilinx ISE 8.2i. The program is written in VHDL and text data is decoded by a Huffman algorithm on Hardware board which was previously encoded by Huffman algorithm. In order to visualize the output clearly in waveforms, the same code is simulated on ModelSim v6.4. Huffman decoder is also implemented in the MATLAB for verification of operation. The FPGA is a configurable device which is more efficient in all aspects. Text application, image processing, video streaming and in many other applications Huffman algorithms are implemented.

  11. FPGA-based phase control of acousto-optic modulator Fourier synthesis system through gradient descent phase-locking algorithm.

    Science.gov (United States)

    Underwood, Kenneth J; Jones, Andrew M; Gopinath, Juliet T

    2015-06-20

    We present a new application of the stochastic parallel gradient descent (SPGD) algorithm to fast active phase control in a Fourier synthesis system. Pulses (4.9 ns) with an 80 MHz repetition rate are generated by feedback from a single phase-sensitive metric. Phase control is applied via fast current modulation of a tapered amplifier using an SPGD algorithm realized on a field-programmable gate array (FPGA). The waveforms are maintained by constant active feedback from the FPGA. We also discuss the extension of this technique to many more semiconductor laser emitters in a diode laser array.

  12. FPGA-based fast pipeline-parameterized-sorter implementation for first level trigger systems in HEP experiments

    CERN Document Server

    Pozniak, Krzysztof T

    2004-01-01

    The paper describes a behavioral model of fast, pipeline sorter dedicated to electronic triggering applications in the experiments of high energy physics (HEP). The sorter was implemented in FPGA for the RPC Muon Detector of CMS experiment (LHC accelerator, CERN) and for Backing Calorimeter (BAC) in ZEUS experiment (HERA accelerator, DESY) . A general principle of the applied sorting algorithm was presented. The implementation results were debated in detail for chosen FPGA chips by ALTERA and XILINX manufactures. The realization costs have been calculated as function of system parameters.

  13. Throughput Analysis for a High-Performance FPGA-Accelerated Real-Time Search Application

    Directory of Open Access Journals (Sweden)

    Wim Vanderbauwhede

    2012-01-01

    Full Text Available We propose an FPGA design for the relevancy computation part of a high-throughput real-time search application. The application matches terms in a stream of documents against a static profile, held in off-chip memory. We present a mathematical analysis of the throughput of the application and apply it to the problem of scaling the Bloom filter used to discard nonmatches.

  14. FPGA implementation of high-frequency multiple PWM for variable voltage variable frequency controller

    Energy Technology Data Exchange (ETDEWEB)

    Boumaaraf, Abdelâali, E-mail: aboumaaraf@yahoo.fr [Université Abbès Laghrour, Laboratoire des capteurs, Instrumentations et procédés (LCIP), Khenchela (Algeria); University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Mohamadi, Tayeb [University of Farhat Abbas Setif1, Sétif, 19000 (Algeria); Gourmat, Laïd [Université Abbès Laghrour, Khenchela, 40000 (Algeria)

    2016-07-25

    In this paper, we present the FPGA implementation of the multiple pulse width modulation (MPWM) signal generation with repetition of data segments, applied to the variable frequency variable voltage systems and specially at to the photovoltaic water pumping system, in order to generate a signal command very easily between 10 Hz to 60 Hz with a small frequency and reduce the cost of the control system.

  15. Design of FPGA-based radiation tolerant quench detectors for LHC

    Science.gov (United States)

    Steckert, J.; Skoczen, A.

    2017-04-01

    The Large Hadron Collider (LHC) comprises many superconducting circuits. Most elements of these circuits require active protection. The functionality of the quench detectors was initially implemented as microcontroller based equipment. After the initial stage of the LHC operation with beams the introduction of a new type of quench detector began. This article presents briefly the main ideas and architectures applied to the design and the validation of FPGA-based quench detectors.

  16. Design of Ultrasonic Phased Array Transmission System Based on FPGA%基于 FPGA 的超声相控阵发射系统设计

    Institute of Scientific and Technical Information of China (English)

    崔娟; 王红亮; 何常德; 薛晨阳

    2015-01-01

    In order to enhance the ultrasonic signal phased array transmission of underwater ultrasonic imaging system,the ul-trasonic phased array transmission system based on FPGA was designed.The transmission principle of phased focus was analyzed, and the eight channel ultrasonic phased array transmission system was achieved by using FPGA with rich I/ O pins and internal log-ic resources.Then the signal conditioning circuit for excitation signal D/ A conversion and amplification were designed to motivate the piezoelectric transducer effectively.The actual test results show that the system realizes ultrasonic signal phased array focus transmission,and the phase delay precision is 2. 5 ns.The system is with high integration and stable transmission,and it can be ap-plied to the underwater ultrasonic imaging implementation.%为了实现水下超声成像系统中超声信号的相控阵发射,提出并设计了一种基于 FPGA 的超声相控阵发射系统。分析了相控聚焦的发射原理,利用 FPGA 丰富的 I/ O 引脚和内部逻辑资源实现了八通道超声相控阵激励信号的发射,并设计了信号调理电路对激励信号进行 D/ A 转换及放大,以有效驱动压电换能器。通过实验测试表明,该系统可以实现超声信号的相控聚焦发射,相控延时精度达到2.5 ns,发射信号稳定,系统集成度高,可以应用于水下超声成像的实现。

  17. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accele...

  18. FPGA based Control of a Production Cell System

    NARCIS (Netherlands)

    Groothuis, Marcel A.; Zuijlen, van Jasper J.P.; Broenink, Jan F.

    2008-01-01

    Most motion control systems for mechatronic systems are implemented on digital computers. In this paper we present an FPGA based solution implemented on a low cost Xilinx Spartan III FPGA. A Production Cell setup with multiple parallel operating units is chosen as a test case. The embedded control s

  19. Automatic generation of application specific FPGA multicore accelerators

    DEFF Research Database (Denmark)

    Hindborg, Andreas Erik; Schleuniger, Pascal; Jensen, Nicklas Bo

    2014-01-01

    High performance computing systems make increasing use of hardware accelerators to improve performance and power properties. For large high-performance FPGAs to be successfully integrated in such computing systems, methods to raise the abstraction level of FPGA programming are required...... to identify optimal performance energy trade-offs points for a multicore based FPGA accelerator....

  20. A Hardware Framework for on-Chip FPGA Acceleration

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Cardarilli, Gian Carlo; Nannarelli, Alberto

    2016-01-01

    In this work, we present a new framework to dynamically load hardware accelerators on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA...

  1. Application of Remote FPGA Dynamic Reconfiguration System in LED Lighting

    Institute of Scientific and Technical Information of China (English)

    LI Wei; WANG Wei; NIU Ping-juan; ZHANG li-ping

    2009-01-01

    The dynamic reconfiguration technique based on field-programmable gate array (FPGA) can improve the resource utilization.Discussed are the dynamic reconfiguration principles and methods.Proposed is a remote dynamic reconfiguration scheme using Xilinx Virtex-II FPGA and SMCS Ethernet Physical layer transceiver(PHY).The hardware of the system is designed with Xilinx Virtex-II XC2V30P FPGA that embedds MicroBlaze and MAC IP core,and its network communication software based on transmission control protocol/Internet protocol (TCP/IP) protocol is programmed by loading LwlP to MicroBlaze. The experimental results indicate that the remote FPGA dynamic reconfiguration system(RFDRS) can switch freely in the eight lighting modes of light emitting diodes (LED),and that,using dynamic reconfiguration technology,FPGA resource utilization can be reduced remarkably,which is advantageous in the system upgrade and software update.

  2. A generic FPGA-based detector readout and real-time image processing board

    CERN Document Server

    Sarpotdar, Mayuresh; Safonova, Margarita; Murthy, Jayant

    2016-01-01

    For space-based astronomical observations, it is important to have a mechanism to capture the digital output from the standard detector for further on-board analysis and storage. We have developed a generic (application- wise) field-programmable gate array (FPGA) board to interface with an image sensor, a method to generate the clocks required to read the image data from the sensor, and a real-time image processor system (on-chip) which can be used for various image processing tasks. The FPGA board is applied as the image processor board in the Lunar Ultraviolet Cosmic Imager (LUCI) and a star sensor (StarSense) (instruments developed by our group). In this paper, we discuss the various design considerations for this board and its applications in the future balloon and possible space flights.

  3. A Real-Time de novo DNA Sequencing Assembly Platform Based on an FPGA Implementation.

    Science.gov (United States)

    Hu, Yuanqi; Georgiou, Pantelis

    2016-01-01

    This paper presents an FPGA based DNA comparison platform which can be run concurrently with the sensing phase of DNA sequencing and shortens the overall time needed for de novo DNA assembly. A hybrid overlap searching algorithm is applied which is scalable and can deal with incremental detection of new bases. To handle the incomplete data set which gradually increases during sequencing time, all-against-all comparisons are broken down into successive window-against-window comparison phases and executed using a novel dynamic suffix comparison algorithm combined with a partitioned dynamic programming method. The complete system has been designed to facilitate parallel processing in hardware, which allows real-time comparison and full scalability as well as a decrease in the number of computations required. A base pair comparison rate of 51.2 G/s is achieved when implemented on an FPGA with successful DNA comparison when using data sets from real genomes.

  4. Optimal Design of FPGA Switch Matrix with Ion Mobility Based Nonvolatile ReRAM

    Directory of Open Access Journals (Sweden)

    Peng Hai-yun

    2015-01-01

    Full Text Available There are high demands for research of new device with greater accessing speed and stability to replace the current SRAM storage cell. The resistive random access memory (ReRAM is a metal oxide which is based on nonvolatile memory device possessing the characteristics of high read/write speed, high storage density, low power, low cost, very small cell, being nonvolatile, and unlimited writing endurance. The device has extreme short erasing time and the stored charge cannot be destroyed after power-off. Therefore, the ReRAM device is a significant storage device for many applications in the next generation. In this paper, we first explored the mechanism of the ReRAM device based on ion mobility model and then applied this device to optimize the design of FPGA switching matrix. The results show that it is beneficial to enhance the FPGA performance to replace traditional SRAM cells with ReRAM cells for the switching matrix.

  5. Advanced image processing package for FPGA-based re-programmable miniature electronics

    Science.gov (United States)

    Ovod, Vladimir I.; Baxter, Christopher R.; Massie, Mark A.; McCarley, Paul L.

    2005-05-01

    Nova Sensors produces miniature electronics for a variety of real-time digital video camera systems, including foveal sensors based on Nova's Variable Acuity Superpixel Imager (VASITM) technology. An advanced image-processing package has been designed at Nova Sensors to re-configure the FPGA-based co-processor board for numerous applications including motion detection, optical, background velocimetry and target tracking. Currently, the processing package consists of 14 processing operations that cover a broad range of point- and area-applied algorithms. Flexible FPGA designs of these operations and re-programmability of the processing board allows for easy updates of the VASITM sensors, and for low-cost customization of VASITM sensors taking into account specific customer requirements. This paper describes the image processing algorithms implemented and verified in Xilinx FPGAs and provides the major technical performances with figures illustrating practical applications of the processing package.

  6. ROI-based Compression on Radiological Image by Urdhva-Tiryagbhyam and DWT Over FPGA

    Directory of Open Access Journals (Sweden)

    Suma

    2017-02-01

    Full Text Available The area of radiological image compression has not yet met its potential solution. After reviewing the existing mechanism of compression, it was found that majority of the existing techniques suffers from significant pitfalls e.g. more usage of transformation schemes, more resource utilization, delay, less focus on FPGA performance enhancement, extremely less emphasis on Vedic-multipliers. Hence, this paper presents an analytical modelling of ROI (Region of Interest-based radiological image compression that applies Vedic Multiplier Urdhva-Tiryagbhyam to enhance the performance of coding using Discrete Wavelet Transform (DWT. The study outcome was implemented in Matlab and multiple test bed of FPGA devices (Virtex 4 FX100 -12 FF1152 and Spartan 3 XC400-5TQ144 and assessed using both visual and numerical outcomes to find that proposed system excel better performance in comparison to recently existing techniques.

  7. Design of miniature hybrid target recognition system with combination of FPGA+DSP

    Science.gov (United States)

    Luo, Shishang; Li, Xiujian; Jia, Hui; Hu, Wenhua; Nie, Yongming; Chang, Shengli

    2010-10-01

    With advantages of flexibility, high bandwidth, high spatial resolution and high-speed parallel operation, the opto-electronic hybrid target recognition system can be applied in many civil and military areas, such as video surveillance, intelligent navigation and robot vision. A miniature opto-electronic hybrid target recognition system based on FPGA+DSP is designed, which only employs single Fourier lens and with a focal length. With the precise timing control of the FPGA and images pretreatment of the DSP, the system performs both Fourier transform and inverse Fourier transform with all optical process, which can improve recognition speed and reduce the system volume remarkably. We analyzed the system performance, and a method to achieve scale invariant pattern recognition was proposed on the basis of lots of experiments.

  8. Hazard Analysis of Software Requirements Specification for Process Module of FPGA-based Controllers in NPP

    Energy Technology Data Exchange (ETDEWEB)

    Jung; Sejin; Kim, Eui-Sub; Yoo, Junbeom [Konkuk University, Seoul (Korea, Republic of); Keum, Jong Yong; Lee, Jang-Soo [Korea Atomic Energy Research Institute, Daejeon (Korea, Republic of)

    2016-10-15

    Software in PLC, FPGA which are used to develop I and C system also should be analyzed to hazards and risks before used. NUREG/CR-6430 proposes the method for performing software hazard analysis. It suggests analysis technique for software affected hazards and it reveals that software hazard analysis should be performed with the aspects of software life cycle such as requirements analysis, design, detailed design, implements. It also provides the guide phrases for applying software hazard analysis. HAZOP (Hazard and operability analysis) is one of the analysis technique which is introduced in NUREG/CR-6430 and it is useful technique to use guide phrases. HAZOP is sometimes used to analyze the safety of software. Analysis method of NUREG/CR-6430 had been used in Korea nuclear power plant software for PLC development. Appropriate guide phrases and analysis process are selected to apply efficiently and NUREG/CR-6430 provides applicable methods for software hazard analysis is identified in these researches. We perform software hazard analysis of FPGA software requirements specification with two approaches which are NUREG/CR-6430 and HAZOP with using general GW. We also perform the comparative analysis with them. NUREG/CR-6430 approach has several pros and cons comparing with the HAZOP with general guide words and approach. It is enough applicable to analyze the software requirements specification of FPGA.

  9. STRS SpaceWire FPGA Module

    Science.gov (United States)

    Lux, James P.; Taylor, Gregory H.; Lang, Minh; Stern, Ryan A.

    2011-01-01

    An FPGA module leverages the previous work from Goddard Space Flight Center (GSFC) relating to NASA s Space Telecommunications Radio System (STRS) project. The STRS SpaceWire FPGA Module is written in the Verilog Register Transfer Level (RTL) language, and it encapsulates an unmodified GSFC core (which is written in VHDL). The module has the necessary inputs/outputs (I/Os) and parameters to integrate seamlessly with the SPARC I/O FPGA Interface module (also developed for the STRS operating environment, OE). Software running on the SPARC processor can access the configuration and status registers within the SpaceWire module. This allows software to control and monitor the SpaceWire functions, but it is also used to give software direct access to what is transmitted and received through the link. SpaceWire data characters can be sent/received through the software interface, as well as through the dedicated interface on the GSFC core. Similarly, SpaceWire time codes can be sent/received through the software interface or through a dedicated interface on the core. This innovation is designed for plug-and-play integration in the STRS OE. The SpaceWire module simplifies the interfaces to the GSFC core, and synchronizes all I/O to a single clock. An interrupt output (with optional masking) identifies time-sensitive events within the module. Test modes were added to allow internal loopback of the SpaceWire link and internal loopback of the client-side data interface.

  10. A digital pulsar backend based on FPGA

    Science.gov (United States)

    Luo, Jin-Tao; Chen, Lan; Han, Jin-Lin; Esamdin, Ali; Wu, Ya-Jun; Li, Zhi-Xuan; Hao, Long-Fei; Zhang, Xiu-Zhong

    2017-01-01

    A digital pulsar backend based on a Field Programmable Gate Array (FPGA) is developed. It is designed for incoherent de-dispersion of pulsar observations and has a maximum bandwidth of 512 MHz. The channel bandwidth is fixed to 1 MHz, and the highest time resolution is 10 {{μ }} s. Testing observations were carried out using the Urumqi 25-m telescope administered by Xinjiang Astronomical Observatory and the Kunming 40-m telescope administered by Yunnan Observatories, targeting PSR J0332+5434 in the L band and PSR J0437–4715 in the S band, respectively. The successful observation of PSR J0437–4715 demonstrates its ability to observe millisecond pulsars.

  11. FPGA-based prototype storage system with phase change memory

    Science.gov (United States)

    Li, Gezi; Chen, Xiaogang; Chen, Bomy; Li, Shunfen; Zhou, Mi; Han, Wenbing; Song, Zhitang

    2016-10-01

    With the ever-increasing amount of data being stored via social media, mobile telephony base stations, and network devices etc. the database systems face severe bandwidth bottlenecks when moving vast amounts of data from storage to the processing nodes. At the same time, Storage Class Memory (SCM) technologies such as Phase Change Memory (PCM) with unique features like fast read access, high density, non-volatility, byte-addressability, positive response to increasing temperature, superior scalability, and zero standby leakage have changed the landscape of modern computing and storage systems. In such a scenario, we present a storage system called FLEET which can off-load partial or whole SQL queries to the storage engine from CPU. FLEET uses an FPGA rather than conventional CPUs to implement the off-load engine due to its highly parallel nature. We have implemented an initial prototype of FLEET with PCM-based storage. The results demonstrate that significant performance and CPU utilization gains can be achieved by pushing selected query processing components inside in PCM-based storage.

  12. Control de acceso usando FPGA y RFID

    Directory of Open Access Journals (Sweden)

    Dora Luz Almanza Ojeda

    2012-10-01

    Full Text Available Este trabajo presenta el diseño e implementación de un sistema de control de acceso mediante Identificación por Radiofrecuencia (RFID, Radio Frequency Identification controlado por una Matriz de compuertas programables (FPGA, Field Programmable Gate Array. El sistema está constituido por un par de dispositivos de adquisición de radiofrecuencia, una FPGA, un juego de etiquetas y tarjetas pasivas de identificación. Mediante una interfaz gráfica de usuario es posible controlar todo movimiento dentro de una zona determinada, desde los accesos hasta la disponibilidad de equipo; utilizando los dispositivos de adquisición de radiofrecuencia se puede acceder a la información de los usuarios autorizados, así como al control del equipo. Con este sistema es posible monitorear, administrar y reportar todo acceso de personal, movimiento de equipo o plagio de manera eficiente y evitando un gran número de errores humanos.  

  13. Small Microprocessor for ASIC or FPGA Implementation

    Science.gov (United States)

    Kleyner, Igor; Katz, Richard; Blair-Smith, Hugh

    2011-01-01

    A small microprocessor, suitable for use in applications in which high reliability is required, was designed to be implemented in either an application-specific integrated circuit (ASIC) or a field-programmable gate array (FPGA). The design is based on commercial microprocessor architecture, making it possible to use available software development tools and thereby to implement the microprocessor at relatively low cost. The design features enhancements, including trapping during execution of illegal instructions. The internal structure of the design yields relatively high performance, with a significant decrease, relative to other microprocessors that perform the same functions, in the number of microcycles needed to execute macroinstructions. The problem meant to be solved in designing this microprocessor was to provide a modest level of computational capability in a general-purpose processor while adding as little as possible to the power demand, size, and weight of a system into which the microprocessor would be incorporated. As designed, this microprocessor consumes very little power and occupies only a small portion of a typical modern ASIC or FPGA. The microprocessor operates at a rate of about 4 million instructions per second with clock frequency of 20 MHz.

  14. Automated Metabolic P System Placement in FPGA

    Directory of Open Access Journals (Sweden)

    Kulakovskis Darius

    2016-07-01

    Full Text Available An original Very High Speed Integrated Circuit Hardware Description Language (VHDL code generation tool that can be used to automate Metabolic P (MP system implementation in hardware such as Field Programmable Gate Arrays (FPGA is described. Unlike P systems, MP systems use a single membrane in their computations. Nevertheless, there are many biological processes that have been successfully modeled by MP systems in software. This is the first attempt to analyze MP system hardware implementations. Two different MP systems are investigated with the purpose of verifying the developed software: the model of glucose–insulin interactions in the Intravenous Glucose Tolerance Test (IVGTT, and the Non-Photochemical Quenching process. The implemented systems’ calculation accuracy and hardware resource usage are examined. It is found that code generation tool works adequately; however, a final decision has to be done by the developer because sometimes several implementation architecture alternatives have to be considered. As an archetypical example serves the IVGTT MP systems’ 21–23 bits FPGA implementation manifesting this in the Digital Signal Processor (DSP, slice, and 4-input LUT usage.

  15. FPGA-Based Embedded Motion Estimation Sensor

    Directory of Open Access Journals (Sweden)

    Zhaoyi Wei

    2008-01-01

    Full Text Available Accurate real-time motion estimation is very critical to many computer vision tasks. However, because of its computational power and processing speed requirements, it is rarely used for real-time applications, especially for micro unmanned vehicles. In our previous work, a FPGA system was built to process optical flow vectors of 64 frames of 640×480 image per second. Compared to software-based algorithms, this system achieved much higher frame rate but marginal accuracy. In this paper, a more accurate optical flow algorithm is proposed. Temporal smoothing is incorporated in the hardware structure which significantly improves the algorithm accuracy. To accommodate temporal smoothing, the hardware structure is composed of two parts: the derivative (DER module produces intermediate results and the optical flow computation (OFC module calculates the final optical flow vectors. Software running on a built-in processor on the FPGA chip is used in the design to direct the data flow and manage hardware components. This new design has been implemented on a compact, low power, high performance hardware platform for micro UV applications. It is able to process 15 frames of 640×480 image per second and with much improved accuracy. Higher frame rate can be achieved with further optimization and additional memory space.

  16. FPGA Fuzzy Controller Design for Magnetic Ball Levitation

    Directory of Open Access Journals (Sweden)

    Basil Hamed

    2012-09-01

    Full Text Available this paper presents a fuzzy controller design for nonlinear system using FPGA. A magnetic levitation system is considered as a case study and the fuzzy controller is designed to keep a magnetic object suspended in the air counteracting the weight of the object. Fuzzy controller will be implemented using FPGA chip. The design will use a high-level programming language HDL for implementing the fuzzy logic controller using the Xfuzzy tools to implement the fuzzy logic controller into HDL code. This paper, advocates a novel approach to implement the fuzzy logic controller for magnetic ball levitation system by using FPGA.

  17. FPGA Implementation of ADPLL with Ripple Reduction Techniques

    Directory of Open Access Journals (Sweden)

    Manoj kumar

    2012-05-01

    Full Text Available In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

  18. FPGA Implementation of ADPLL with Ripple Reduction Techniques

    Directory of Open Access Journals (Sweden)

    Manoj Kumar

    2012-04-01

    Full Text Available In this paper FPGA implementation of ADPLL using Verilog is presented. ADPLL with ripple reduction techniques is also simulated and implemented on FPGA. For simulation ISE Xilinx 10.1 CAD is used.Vertex5 FPGA (Field Programmable Gate Array is used for implementation. ADPLL performance improvement, while using ripple reduction techniques is also discussed. The ADPLL is designed at the central frequency of 100 kHz. The frequency range of ADPLL is 0 kHz to 199 kHz. But when it is implemented with ripple reduction techniques, the frequency range observed is from 11 kHz to 216 kHz.

  19. FPGA-based voltage and current dual drive system for high frame rate electrical impedance tomography.

    Science.gov (United States)

    Khan, Shadab; Manwaring, Preston; Borsic, Andrea; Halter, Ryan

    2015-04-01

    Electrical impedance tomography (EIT) is used to image the electrical property distribution of a tissue under test. An EIT system comprises complex hardware and software modules, which are typically designed for a specific application. Upgrading these modules is a time-consuming process, and requires rigorous testing to ensure proper functioning of new modules with the existing ones. To this end, we developed a modular and reconfigurable data acquisition (DAQ) system using National Instruments' (NI) hardware and software modules, which offer inherent compatibility over generations of hardware and software revisions. The system can be configured to use up to 32-channels. This EIT system can be used to interchangeably apply current or voltage signal, and measure the tissue response in a semi-parallel fashion. A novel signal averaging algorithm, and 512-point fast Fourier transform (FFT) computation block was implemented on the FPGA. FFT output bins were classified as signal or noise. Signal bins constitute a tissue's response to a pure or mixed tone signal. Signal bins' data can be used for traditional applications, as well as synchronous frequency-difference imaging. Noise bins were used to compute noise power on the FPGA. Noise power represents a metric of signal quality, and can be used to ensure proper tissue-electrode contact. Allocation of these computationally expensive tasks to the FPGA reduced the required bandwidth between PC, and the FPGA for high frame rate EIT. In 16-channel configuration, with a signal-averaging factor of 8, the DAQ frame rate at 100 kHz exceeded 110 frames s (-1), and signal-to-noise ratio exceeded 90 dB across the spectrum. Reciprocity error was found to be for frequencies up to 1 MHz. Static imaging experiments were performed on a high-conductivity inclusion placed in a saline filled tank; the inclusion was clearly localized in the reconstructions obtained for both absolute current and voltage mode data.

  20. A Translator Verification Technique for FPGA Software Development in Nuclear Power Plants

    Energy Technology Data Exchange (ETDEWEB)

    Kim, Jae Yeob; Kim, Eui Sub; Yoo, Jun Beom [Konkuk University, Seoul (Korea, Republic of)

    2014-10-15

    Although the FPGAs give a high performance than PLC (Programmable Logic Controller), the platform change from PLC to FPGA impose all PLC software engineers give up their experience, knowledge and practices accumulated over decades, and start a new FPGA-based hardware development from scratch. We have researched to fine the solution to this problem reducing the risk and preserving the experience and knowledge. One solution is to use the FBDtoVerilog translator, which translates the FBD programs into behavior-preserving Verilog programs. In general, the PLCs are usually designed with an FBD, while the FPGAs are described with a HDL (Hardware Description Language) such as Verilog or VHDL. Once PLC designer designed the FBD programs, the FBDtoVerilog translates the FBD into Verilog, mechanically. The designers, therefore, need not consider the rest of FPGA development process (e.g., Synthesis and Place and Routing) and can preserve the accumulated experience and knowledge. Even if we assure that the translation from FBD to Verilog is correct, it must be verified rigorously and thoroughly since it is used in nuclear power plants, which is one of the most safety critical systems. While the designer develops the FPGA software with the FBD program translated by the translator, there are other translation tools such as synthesis tool and place and routing tool. This paper also focuses to verify them rigorously and thoroughly. There are several verification techniques for correctness of translator, but they are hard to apply because of the outrageous cost and performance time. Instead, this paper tries to use an indirect verification technique for demonstrating the correctness of translator using the co-simulation technique. We intend to prove only against specific inputs which are under development for a target I and C system, not against all possible input cases.

  1. Architecture for Fault- tolerance of FPGA in Aerospace%FPGA的空间容错技术研究

    Institute of Scientific and Technical Information of China (English)

    裴志强; 周刚

    2011-01-01

    基于SRAM的FPGA对于空间粒子辐射非常敏感,很容易产生软故障,所以对基于FPGA的电子系统采取容错措施以防止此类故障的出现非常重要.通过对敏感电路使用三模冗余(TMR)方法并利用FPGA的动态可重构特性,可以有效的增强FPGA的抗单粒子性能,解决FPGA对因空间粒子辐射而形成的软故障.%FPGA based on SRAM is sensitive for space particle, then soft fault occurs easyly. So it is important to take some tolerance action on the fault for the electronic system based on FPGA. By using the Triple Modular Redundancy method and apply the dynamic reconfigurable feature of FPGA, SEU performance of FPGA can be enhanced, hence soft fault brought by space particle radiation is solved.

  2. Applying a Genetic Algorithm to Reconfigurable Hardware

    Science.gov (United States)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  3. Architecture Analysis of an FPGA-Based Hopfield Neural Network

    Directory of Open Access Journals (Sweden)

    Miguel Angelo de Abreu de Sousa

    2014-01-01

    Full Text Available Interconnections between electronic circuits and neural computation have been a strongly researched topic in the machine learning field in order to approach several practical requirements, including decreasing training and operation times in high performance applications and reducing cost, size, and energy consumption for autonomous or embedded developments. Field programmable gate array (FPGA hardware shows some inherent features typically associated with neural networks, such as, parallel processing, modular executions, and dynamic adaptation, and works on different types of FPGA-based neural networks were presented in recent years. This paper aims to address different aspects of architectural characteristics analysis on a Hopfield Neural Network implemented in FPGA, such as maximum operating frequency and chip-area occupancy according to the network capacity. Also, the FPGA implementation methodology, which does not employ multipliers in the architecture developed for the Hopfield neural model, is presented, in detail.

  4. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  5. Rad-Hard and ULP FPGA with "Full" Functionality Project

    Data.gov (United States)

    National Aeronautics and Space Administration — RNET has demonstrated the feasibility of developing an innovative radiation hardened (RH) and ultra low power (ULP) field programmable gate array (FPGA), called the...

  6. A software radio platform based on ARM and FPGA

    Directory of Open Access Journals (Sweden)

    Yang Xin.

    2016-01-01

    Full Text Available The rapid rise in computational performance offered by computer systems has greatly increased the number of practical software radio applications. A scheme presented in this paper is a software radio platform based on ARM and FPGA. FPGA works as the coprocessor together with the ARM, which serves as the core processor. ARM is used for digital signal processing and real-time data transmission, and FPGA is used for synchronous timing control and serial-parallel conversion. A SPI driver for real-time data transmission between ARM and FPGA under ARM-Linux system is provided. By adopting modular design, the software radio platform is capable of implementing wireless communication functions and satisfies the requirements of real-time signal processing platform for high security and broad applicability.

  7. A design of FPGA based intelligent data handling interfacing card.

    Directory of Open Access Journals (Sweden)

    Anandaraj D

    2015-05-01

    Full Text Available With the increasing demand in the custom built logic for avionics systems, FPGA is used in this proposed interfacing card design. This FPGA based intelligent data handling card (IDHC for the IVHM system, will interface the data from aircraft subsystems to the aircraft digital data bus. This IDHC interfacing card is based on the Virtex-5 FPGA (Field Programmable Gate Array, which provides flexibility by re-programming, so that it can be configured to the required functionality. Fault detection can be done within the FPGA and only the anomalies passed to the computer, so that the bus bandwidth can be utilized effectively and also excessive wiring can be eliminated, that would have been required for multiple individual systems. The work concentrates on designing the schematic using OrCAD.

  8. Study and Implementation of MUX Based FPGA in QCA Technology

    Directory of Open Access Journals (Sweden)

    E.N.Ganesh

    2011-06-01

    Full Text Available This paper presents a simple Multiplexer based Field programmable gate arrays with interconnectsbased on quantum cellular automata technology. Quantum cellular automata (QCA technology is apromising nanotechnology of the future. QCA based 4:1 Multiplexer are designed and constructed as amodule in a FPGA. Multiplexer based designs are used to implement complex Boolean functions andeach module can act as a logic element or simple Multiplexer. We have studied here, NOR based logic toimplement Sum function of an adder in a QCA FPGA. Finally we have designed and simulated the MUXbased logic elements to construct QCA FPGA. This study can be useful for building complexConfigurable logic blocks to design a complete FPGA.

  9. Technologies for faults diagnosis of FPGA logic blocks

    Directory of Open Access Journals (Sweden)

    C. U. Ngene

    2012-08-01

    Full Text Available The critical issues of testing field programmable gate arrays (FPGA with a view to diagnosing faults are an important step that ensures the reliability of FPGA designs. Correct diagnosis of faulty logic blocks of FPGAs guarantees restoration of functionality through replacement of faulty block with replacement units. This process can be done autonomously or without the intervention of an engineer depending on application area. This paper considers two methods for analysing test results of FPGA logic blocks with the purpose of localising and distinguishing faults. The algebraic logic and vector-logical methods are proposed for diagnosing faulty logic blocks in FPGA fabric. It is found that the algebraic logic method is more useful for processing of sparse faults tables when the number of coordinates with 1s values with respect to zero values ​​is not more than 20%, whereas the vector-logical method facilitates the analysis of faults table with predominance of 1s values.

  10. Application-specific mesh-based heterogeneous FPGA architectures

    CERN Document Server

    Parvez, Husain

    2011-01-01

    This volume presents a new exploration environment for mesh-based, heterogeneous FPGA architectures. Readers will find a description of state-of-the-art techniques for reducing area requirements, which both increase performance and enable power reduction.

  11. Final Report- "An Algorithmic and Software Framework for Applied Partial Differential Equations (APDEC): A DOE SciDAC Integrated Software Infrastructure Center (ISIC)

    Energy Technology Data Exchange (ETDEWEB)

    Elbridge Gerry Puckett

    2008-05-13

    All of the work conducted under the auspices of DE-FC02-01ER25473 was characterized by exceptionally close collaboration with researchers at the Lawrence Berkeley National Laboratory (LBNL). This included having one of my graduate students - Sarah Williams - spend the summer working with Dr. Ann Almgren a staff scientist in the Center for Computational Sciences and Engineering (CCSE) which is a part of the National Energy Research Supercomputer Center (NERSC) at LBNL. As a result of this visit Sarah decided to work on a problem suggested by Dr. John Bell the head of CCSE for her PhD thesis, which she finished in June 2007. Writing a PhD thesis while working at one of the University of California (UC) managed DOE laboratories is a long established tradition at the University of California and I have always encouraged my students to consider doing this. For example, in 2000 one of my graduate students - Matthew Williams - finished his PhD thesis while working with Dr. Douglas Kothe at the Los Alamos National Laboratory (LANL). Matt is now a staff scientist in the Diagnostic Applications Group in the Applied Physics Division at LANL. Another one of my graduate students - Christopher Algieri - who was partially supported with funds from DE-FC02-01ER25473 wrote am MS Thesis that analyzed and extended work published by Dr. Phil Colella and his colleagues in 1998. Dr. Colella is the head of the Applied Numerical Algorithms Group (ANAG) in the National Energy Research Supercomputer Center at LBNL and is the lead PI for the APDEC ISIC which was comprised of several National Laboratory research groups and at least five University PI's at five different universities. Chris Algieri is now employed as a staff member in Dr. Bill Collins' research group at LBNL developing computational models for climate change research. Bill Collins was recently hired at LBNL to start and be the Head of the Climate Science Department in the Earth Sciences Division at LBNL. Prior to

  12. FPGA for Power Control of MSL Avionics

    Science.gov (United States)

    Wang, Duo; Burke, Gary R.

    2011-01-01

    A PLGT FPGA (Field Programmable Gate Array) is included in the LCC (Load Control Card), GID (Guidance Interface & Drivers), TMC (Telemetry Multiplexer Card), and PFC (Pyro Firing Card) boards of the Mars Science Laboratory (MSL) spacecraft. (PLGT stands for PFC, LCC, GID, and TMC.) It provides the interface between the backside bus and the power drivers on these boards. The LCC drives power switches to switch power loads, and also relays. The GID drives the thrusters and latch valves, as well as having the star-tracker and Sun-sensor interface. The PFC drives pyros, and the TMC receives digital and analog telemetry. The FPGA is implemented both in Xilinx (Spartan 3- 400) and in Actel (RTSX72SU, ASX72S). The Xilinx Spartan 3 part is used for the breadboard, the Actel ASX part is used for the EM (Engineer Module), and the pin-compatible, radiation-hardened RTSX part is used for final EM and flight. The MSL spacecraft uses a FC (Flight Computer) to control power loads, relays, thrusters, latch valves, Sun-sensor, and star-tracker, and to read telemetry such as temperature. Commands are sent over a 1553 bus to the MREU (Multi-Mission System Architecture Platform Remote Engineering Unit). The MREU resends over a remote serial command bus c-bus to the LCC, GID TMC, and PFC. The MREU also sends out telemetry addresses via a remote serial telemetry address bus to the LCC, GID, TMC, and PFC, and the status is returned over the remote serial telemetry data bus.

  13. A Portable Laser Photoacoustic Methane Sensor Based on FPGA

    Science.gov (United States)

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-01-01

    A portable laser photoacoustic sensor for methane (CH4) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated. PMID:27657079

  14. A Portable Laser Photoacoustic Methane Sensor Based on FPGA.

    Science.gov (United States)

    Wang, Jianwei; Wang, Huili; Liu, Xianyong

    2016-09-21

    A portable laser photoacoustic sensor for methane (CH₄) detection based on a field-programmable gate array (FPGA) is reported. A tunable distributed feedback (DFB) diode laser in the 1654 nm wavelength range is used as an excitation source. The photoacoustic signal processing was implemented by a FPGA device. A small resonant photoacoustic cell is designed. The minimum detection limit (1σ) of 10 ppm for methane is demonstrated.

  15. FPGA Architecture for Multi-Style Asynchronous Logic

    CERN Document Server

    Huot, N; Fesquet, L; Renaudin, M

    2011-01-01

    This paper presents a novel FPGA architecture for implementing various styles of asynchronous logic. The main objective is to break the dependency between the FPGA architecture dedicated to asynchronous logic and the logic style. The innovative aspects of the architecture are described. Moreover the structure is well suited to be rebuilt and adapted to fit with further asynchronous logic evolutions thanks to the architecture genericity. A full-adder was implemented in different styles of logic to show the architecture flexibility.

  16. Electronic-generated holograms by FPGA and monochromatic LCD

    Science.gov (United States)

    Castillo-Atoche, A.; Pérez-Cortés, M.; López, M. A.; Ortiz-Gutiérrez, M.

    2006-02-01

    The majority of holograms are made using interference of light and computer-generated holograms. In this work we propose a technique in real time to generate digital holograms with a VLSI digital component, being specific FPGA and a liquid crystal device. The digital design with FPGA presents great advantage for its parallel procesing that carry out by its flexible structure, high integration and velocity. The design was verified using the platform MathLab/Simulink and Xilinx System Generator.

  17. A Reconfigurable FPGA System for Parallel Independent Component Analysis

    Directory of Open Access Journals (Sweden)

    Du Hongtao

    2006-01-01

    Full Text Available A run-time reconfigurable field programmable gate array (FPGA system is presented for the implementation of the parallel independent component analysis (ICA algorithm. In this work, we investigate design challenges caused by the capacity constraints of single FPGA. Using the reconfigurability of FPGA, we show how to manipulate the FPGA-based system and execute processes for the parallel ICA (pICA algorithm. During the implementation procedure, pICA is first partitioned into three temporally independent function blocks, each of which is synthesized by using several ICA-related reconfigurable components (RCs that are developed for reuse and retargeting purposes. All blocks are then integrated into a design and development environment for performing tasks such as FPGA optimization, placement, and routing. With partitioning and reconfiguration, the proposed reconfigurable FPGA system overcomes the capacity constraints for the pICA implementation on embedded systems. We demonstrate the effectiveness of this implementation on real images with large throughput for dimensionality reduction in hyperspectral image (HSI analysis.

  18. A distributed Canny edge detector: algorithm and FPGA implementation.

    Science.gov (United States)

    Xu, Qian; Varadarajan, Srenivas; Chakrabarti, Chaitali; Karam, Lina J

    2014-07-01

    The Canny edge detector is one of the most widely used edge detection algorithms due to its superior performance. Unfortunately, not only is it computationally more intensive as compared with other edge detection algorithms, but it also has a higher latency because it is based on frame-level statistics. In this paper, we propose a mechanism to implement the Canny algorithm at the block level without any loss in edge detection performance compared with the original frame-level Canny algorithm. Directly applying the original Canny algorithm at the block-level leads to excessive edges in smooth regions and to loss of significant edges in high-detailed regions since the original Canny computes the high and low thresholds based on the frame-level statistics. To solve this problem, we present a distributed Canny edge detection algorithm that adaptively computes the edge detection thresholds based on the block type and the local distribution of the gradients in the image block. In addition, the new algorithm uses a nonuniform gradient magnitude histogram to compute block-based hysteresis thresholds. The resulting block-based algorithm has a significantly reduced latency and can be easily integrated with other block-based image codecs. It is capable of supporting fast edge detection of images and videos with high resolutions, including full-HD since the latency is now a function of the block size instead of the frame size. In addition, quantitative conformance evaluations and subjective tests show that the edge detection performance of the proposed algorithm is better than the original frame-based algorithm, especially when noise is present in the images. Finally, this algorithm is implemented using a 32 computing engine architecture and is synthesized on the Xilinx Virtex-5 FPGA. The synthesized architecture takes only 0.721 ms (including the SRAM READ/WRITE time and the computation time) to detect edges of 512 × 512 images in the USC SIPI database when clocked at 100

  19. Design of FPGA-based Digital PID Controller Using Xilinx SysGen® For Regulating Blood Glucose Level of Type-I Diabetic Patients

    Directory of Open Access Journals (Sweden)

    Arezou Geramipour

    2013-04-01

    Full Text Available This paper emphasizes on a method for designing digital PID controller based on Field Programmable Gate Array (FPGA device for regulating blood glucose level of type-I diabetic patients. The controller is tuned using Bergman Minimal model as a diabetic patient model in MATLAB and Simulink environment. The PID parameters are tuned using a genetic algorithm (GA. Because the speed of control systems has influence on their performance and stability, Field Programmable Gate Array (FPGA device is considered. A Simulink to FPGA flow is applied to the structure of PID controller with Xilinx blocks in Simulink. The results of blood glucose of two diabetic patient models using different quantization in bits are simulated. The results show that unsuitable number of bits cause hypoglycemia and increasing the peak of blood glucose in diabetic patients. System Generator and Integrated Software Environment (ISE are used for creating Bitstream file that can be downloaded into FPGA device. The results show that implementation of PID controller on FPGA using System Generator is compact and high speed and causes the designer can evaluate and implement different designs simply.

  20. Automated synthesis of an FPGA-based controller for vehicle lateral control

    Directory of Open Access Journals (Sweden)

    Economakos Christoforos

    2016-01-01

    Full Text Available The purpose of this paper is to demonstrate the use of an integrated methodology, which was introduced by the authors in previous publications. The purpose of the methodology is to facilitate the automated implementation of FPGA-based industrial controllers using modern high-level synthesis tools. In previous papers the methodology was used for rather simple applications. Here it is applied in a more demanding problem, namely the on-line optimization of a PID controller for the automatic lateral control of a highway vehicle.

  1. A Specialized Lightweight Metamorphic Function for KASUMI Metamorphic Cipher and Its FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Rabie A. Mahmoud

    2016-08-01

    Full Text Available To enhance the performance of the KASUMI Metamorphic Cipher, we apply a lightweight Metamorphic Structure. The proposed structure uses four lightweight bit-balanced operations in the function Meta-FO of the KASUMI Metamorphic Cipher. These operations are: XOR, INV, XNOR, and NOP for bitwise XOR, invert, XNOR, and no operation respectively building blocks of the Specialized Crypto Logic Unit (SCLU. In this work, we present a lightweight KASUMI Specialized-Metamorphic Cipher. In addition, we provide a Field Programmable Gate Array (FPGA implementation of the proposed algorithm modification.

  2. Stick Based Speckle Reduction for Real-Time Processing of OCT Images on an FPGA

    Directory of Open Access Journals (Sweden)

    H. Luecken

    2007-01-01

    Full Text Available This paper presents an FPGA based real-time implementation of an adaptive speckle reduction algorithm. Applied to the log-compressed image of a high-resolution optical coherence tomography (OCT system, all related signal processing steps from envelope detection to VGA video signal generation are executed on a single chip. Images from measured OCT data show that the chosen algorithm produces a smooth, detailed image with fewer image artifacts than comparable approaches. An estimation of the hardware effort, the possible throughput rate and the resulting image frame rate is given for different window sizes used here in speckle reduction. 

  3. Research of Delay-Fault Testing Technology in FPGA%FPGA 时延故障检测技术研究磁

    Institute of Scientific and Technical Information of China (English)

    杨士宁; 顾颖; 石雪梅

    2015-01-01

    With the fast application of FPGA devices ,the FPGA device fault testing and fault diagnosis method for a more comprehensive study is of great significance .The delay‐fault is an important type of FPGA interior faults .The FPGA delay‐fault includes interior logic resources delay and interior routing resources delay .Therefore ,the inter structure and de‐lay‐fault of FPGA are analyzed ,and the fault testing method for interior logic resources delay and interior routing resources delay are researched .The test approach is successfully implemented using one Virtex‐ Ⅱ FPGA of Xilinx .The realization of Delay‐Fault Testing technology in FPGAs is proved .%随着 FPGA 器件的应用越来越广泛,FPGA 的测试和故障诊断技术得到了广泛重视和研究。 FPGA 的时延故障是 FPGA 内部故障中非常重要的一类故障类型,主要包含器件内部逻辑资源时延故障和连线资源时延故障。论文通过分析 FPGA 的内部结构和时延故障特性,研究 FPGA 内部逻辑资源时延和连线资源时延故障检测方法。利用 Xilinx 公司Virtex‐Ⅱ系列 FPGA 完成时延故障检测方法验证,证明了 FPGA 时延故障检测的可实现性。

  4. Energy efficiency analysis and implementation of AES on an FPGA

    Science.gov (United States)

    Kenney, David

    The Advanced Encryption Standard (AES) was developed by Joan Daemen and Vincent Rjimen and endorsed by the National Institute of Standards and Technology in 2001. It was designed to replace the aging Data Encryption Standard (DES) and be useful for a wide range of applications with varying throughput, area, power dissipation and energy consumption requirements. Field Programmable Gate Arrays (FPGAs) are flexible and reconfigurable integrated circuits that are useful for many different applications including the implementation of AES. Though they are highly flexible, FPGAs are often less efficient than Application Specific Integrated Circuits (ASICs); they tend to operate slower, take up more space and dissipate more power. There have been many FPGA AES implementations that focus on obtaining high throughput or low area usage, but very little research done in the area of low power or energy efficient FPGA based AES; in fact, it is rare for estimates on power dissipation to be made at all. This thesis presents a methodology to evaluate the energy efficiency of FPGA based AES designs and proposes a novel FPGA AES implementation which is highly flexible and energy efficient. The proposed methodology is implemented as part of a novel scripting tool, the AES Energy Analyzer, which is able to fully characterize the power dissipation and energy efficiency of FPGA based AES designs. Additionally, this thesis introduces a new FPGA power reduction technique called Opportunistic Combinational Operand Gating (OCOG) which is used in the proposed energy efficient implementation. The AES Energy Analyzer was able to estimate the power dissipation and energy efficiency of the proposed AES design during its most commonly performed operations. It was found that the proposed implementation consumes less energy per operation than any previous FPGA based AES implementations that included power estimations. Finally, the use of Opportunistic Combinational Operand Gating on an AES cipher

  5. Evaluation of CHO Benchmarks on the Arria 10 FPGA using Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-05-23

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. Benchmarking of OpenCL-based framework is an effective way for analyzing the performance of system by studying the execution of the benchmark applications. CHO is a suite of benchmark applications that provides support for OpenCL [1]. The authors presented CHO as an OpenCL port of the CHStone benchmark. Using Altera OpenCL (AOCL) compiler to synthesize the benchmark applications, they listed the resource usage and performance of each kernel that can be successfully synthesized by the compiler. In this report, we evaluate the resource usage and performance of the CHO benchmark applications using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board that features an Arria 10 FPGA device. The focus of the report is to have a better understanding of the resource usage and performance of the kernel implementations using Arria-10 FPGA devices compared to Stratix-5 FPGA devices. In addition, we also gain knowledge about the limitations of the current compiler when it fails to synthesize a benchmark

  6. Fast semivariogram computation using FPGA architectures

    Science.gov (United States)

    Lagadapati, Yamuna; Shirvaikar, Mukul; Dong, Xuanliang

    2015-02-01

    The semivariogram is a statistical measure of the spatial distribution of data and is based on Markov Random Fields (MRFs). Semivariogram analysis is a computationally intensive algorithm that has typically seen applications in the geosciences and remote sensing areas. Recently, applications in the area of medical imaging have been investigated, resulting in the need for efficient real time implementation of the algorithm. The semivariogram is a plot of semivariances for different lag distances between pixels. A semi-variance, γ(h), is defined as the half of the expected squared differences of pixel values between any two data locations with a lag distance of h. Due to the need to examine each pair of pixels in the image or sub-image being processed, the base algorithm complexity for an image window with n pixels is O(n2). Field Programmable Gate Arrays (FPGAs) are an attractive solution for such demanding applications due to their parallel processing capability. FPGAs also tend to operate at relatively modest clock rates measured in a few hundreds of megahertz, but they can perform tens of thousands of calculations per clock cycle while operating in the low range of power. This paper presents a technique for the fast computation of the semivariogram using two custom FPGA architectures. The design consists of several modules dedicated to the constituent computational tasks. A modular architecture approach is chosen to allow for replication of processing units. This allows for high throughput due to concurrent processing of pixel pairs. The current implementation is focused on isotropic semivariogram computations only. Anisotropic semivariogram implementation is anticipated to be an extension of the current architecture, ostensibly based on refinements to the current modules. The algorithm is benchmarked using VHDL on a Xilinx XUPV5-LX110T development Kit, which utilizes the Virtex5 FPGA. Medical image data from MRI scans are utilized for the experiments

  7. Single Event Analysis and Fault Injection Techniques Targeting Complex Designs Implemented in Xilinx-Virtex Family Field Programmable Gate Array (FPGA) Devices

    Science.gov (United States)

    Berg, Melanie D.; LaBel, Kenneth; Kim, Hak

    2014-01-01

    An informative session regarding SRAM FPGA basics. Presenting a framework for fault injection techniques applied to Xilinx Field Programmable Gate Arrays (FPGAs). Introduce an overlooked time component that illustrates fault injection is impractical for most real designs as a stand-alone characterization tool. Demonstrate procedures that benefit from fault injection error analysis.

  8. FPGA Implementation of Complex Multiplier Using Urdhva Tiryakbham Sutra of Vedic Mathematics

    Directory of Open Access Journals (Sweden)

    Rupa A. Tomaskar

    2014-05-01

    Full Text Available In this work VHDL implementation of complex number multiplier using ancient Vedic mathematics is presented, also the FPGA implementation of 4-bit complex multiplier using Vedic sutra is done on SPARTAN 3 FPGA kit. The idea for designing the multiplier unit is adopted from ancient Indian mathematics "Vedas". The Urdhva Tiryakbhyam sutra (method was selected for implementation since it is applicable to all cases of multiplication. The feature of this method is any multi-bit multiplication can be reduced down to single bit multiplication and addition. On account of these formulas, the partial products and sums are generated in one step which reduces the carry propagation from LSB to MSB. The implementation of the Vedic mathematics and their application to the complex multiplier ensure substantial reduction of propagation delay. The simulation results for 4-bit, 8-bit, 16-bit and 32 bit complex number multiplication using Vedic sutra are illustrated. The results show that Urdhva Tiryakbhyam sutra with less number of bits may be used to implement multiplier efficiently in signal processing algorithms.

  9. Multi-Softcore Architecture on FPGA

    Directory of Open Access Journals (Sweden)

    Mouna Baklouti

    2014-01-01

    Full Text Available To meet the high performance demands of embedded multimedia applications, embedded systems are integrating multiple processing units. However, they are mostly based on custom-logic design methodology. Designing parallel multicore systems using available standards intellectual properties yet maintaining high performance is also a challenging issue. Softcore processors and field programmable gate arrays (FPGAs are a cheap and fast option to develop and test such systems. This paper describes a FPGA-based design methodology to implement a rapid prototype of parametric multicore systems. A study of the viability of making the SoC using the NIOS II soft-processor core from Altera is also presented. The NIOS II features a general-purpose RISC CPU architecture designed to address a wide range of applications. The performance of the implemented architecture is discussed, and also some parallel applications are used for testing speedup and efficiency of the system. Experimental results demonstrate the performance of the proposed multicore system, which achieves better speedup than the GPU (29.5% faster for the FIR filter and 23.6% faster for the matrix-matrix multiplication.

  10. Fpga-based control of piezoelectric actuators

    Directory of Open Access Journals (Sweden)

    Juhász László

    2011-01-01

    Full Text Available In many industrial applications like semiconductor production and optical inspection systems, the availability of positioning systems capable to follow trajectory paths in the range of several centimetres, featuring at the same time a nanometre-range precision, is demanding. Pure piezoelectric stages and standard positioning systems with motor and spindle are not able to meet such requirements, because of the small operation range and inadequacies like backlash and friction. One concept for overcoming these problems consists of a hybrid positioning system built through the integration of a DC-drive in series with a piezoelectric actuator. The wide range of potential applications enables a considerable market potential for such an actuator, but due to the high variety of possible positioned objects and dynamic requirements, the required control complexity may be significant. In this paper, a real-time capable state-space control concept for the piezoelectric actuators, embedded in such a hybrid micropositioning system, is presented. The implementation of the controller together with a real-time capable hysteresis compensation measure is performed using a low-budget FPGA-board, whereas the superimposed integrated controller is realized with a dSPACE RCP-system. The advantages of the designed control over a traditional proportional-integral control structure are proven through experimental results using a commercially available hybrid micropositioning system. Positioning results by different dynamic requirements featuring positioning velocities from 1 μm/s up to 5 cm/s are given.

  11. Stego on FPGA: An IWT Approach

    Directory of Open Access Journals (Sweden)

    Balakrishnan Ramalingam

    2014-01-01

    Full Text Available A reconfigurable hardware architecture for the implementation of integer wavelet transform (IWT based adaptive random image steganography algorithm is proposed. The Haar-IWT was used to separate the subbands namely, LL, LH, HL, and HH, from 8×8 pixel blocks and the encrypted secret data is hidden in the LH, HL, and HH blocks using Moore and Hilbert space filling curve (SFC scan patterns. Either Moore or Hilbert SFC was chosen for hiding the encrypted data in LH, HL, and HH coefficients, whichever produces the lowest mean square error (MSE and the highest peak signal-to-noise ratio (PSNR. The fixated random walk’s verdict of all blocks is registered which is nothing but the furtive key. Our system took 1.6 µs for embedding the data in coefficient blocks and consumed 34% of the logic elements, 22% of the dedicated logic register, and 2% of the embedded multiplier on Cyclone II field programmable gate array (FPGA.

  12. IMPLEMENTATION OF NEURAL - CRYPTOGRAPHIC SYSTEM USING FPGA

    Directory of Open Access Journals (Sweden)

    KARAM M. Z. OTHMAN

    2011-08-01

    Full Text Available Modern cryptography techniques are virtually unbreakable. As the Internet and other forms of electronic communication become more prevalent, electronic security is becoming increasingly important. Cryptography is used to protect e-mail messages, credit card information, and corporate data. The design of the cryptography system is a conventional cryptography that uses one key for encryption and decryption process. The chosen cryptography algorithm is stream cipher algorithm that encrypt one bit at a time. The central problem in the stream-cipher cryptography is the difficulty of generating a long unpredictable sequence of binary signals from short and random key. Pseudo random number generators (PRNG have been widely used to construct this key sequence. The pseudo random number generator was designed using the Artificial Neural Networks (ANN. The Artificial Neural Networks (ANN providing the required nonlinearity properties that increases the randomness statistical properties of the pseudo random generator. The learning algorithm of this neural network is backpropagation learning algorithm. The learning process was done by software program in Matlab (software implementation to get the efficient weights. Then, the learned neural network was implemented using field programmable gate array (FPGA.

  13. FPGA Architecture for Kriging Image Interpolation

    Directory of Open Access Journals (Sweden)

    Maciej Wielgosz

    2013-01-01

    Full Text Available This paper proposes an ultrafast scalable embedded image compression scheme based on discrete cosine transform. It is designed for general network architecture that guarantees maximum end-to-end delay (EED, in particular the Distributed Multimedia Plays (DMP architecture. DMP is designed to enable people to perform delay-sensitive real-time collaboration from remote places via their own collaboration space (CS. It requires much lower EED to achieve good synchronization than that in existing teleconference systems. A DMP node can drop packets from networked CSs intelligently to guarantee its local delay and degrade visual quality gracefully. The transmitter classifies visual information in an input image into priority ranks. Included in the bitstream as side information, the ranks enable intelligent packet dropping. The receiver reconstructs the image from the remaining packets. Four priority ranks for dropping are provided. Our promising results reveal that, with the proposed compression technique, maximum EED can be guaranteed with graceful degradation of image quality. The given parallel designs for its hardware implementation in FPGA shows its technical feasibility as a module in the DMP architecture.

  14. FPGA Congestion-Driven Placement Refinement

    Energy Technology Data Exchange (ETDEWEB)

    Vicente de, J.

    2005-07-01

    The routing congestion usually limits the complete proficiency of the FPGA logic resources. A key question can be formulated regarding the benefits of estimating the congestion at placement stage. In the last years, it is gaining acceptance the idea of a detailed placement taking into account congestion. In this paper, we resort to the Thermodynamic Simulated Annealing (TSA) algorithm to perform a congestion-driven placement refinement on the top of the common Bounding-Box pre optimized solution. The adaptive properties of TSA allow the search to preserve the solution quality of the pre optimized solution while improving other fine-grain objectives. Regarding the cost function two approaches have been considered. In the first one Expected Occupation (EO), a detailed probabilistic model to account for channel congestion is evaluated. We show that in spite of the minute detail of EO, the inherent uncertainty of this probabilistic model impedes to relieve congestion beyond the sole application of the Bounding-Box cost function. In the second approach we resort to the fast Rectilinear Steiner Regions algorithm to perform not an estimation but a measurement of the global routing congestion. This second strategy allows us to successfully reduce the requested channel width for a set of benchmark circuits with respect to the widespread Versatile Place and Route (VPR) tool. (Author) 31 refs.

  15. FPGA IMPLEMENTATION OF LOW POWER DIGITAL FREQUENCY

    Directory of Open Access Journals (Sweden)

    K. R. Rekha,

    2010-10-01

    Full Text Available In this Paper we are presenting a new FPGA approach to design an optimized use a Digital Frequency Synthesizer (DDFS in our system to generate a sampled sinusoidal wave of frequency. The major advantage of Digital Frequency Synthesizer (DFS is that its output frequency, phase and amplitude can be precisely and rapidly manipulated under the control of a DSP. Other inherent DFS attributes include the ability to tune with extremely fine frequency and phase resolution and to rapidly “hop” between the frequencies. These combined characteristics have made this technology popular in military, radar and communications systems. The digital circuits used to implementsignal processing functions do not suffer the effects of thermal drifts, aging and component variations associated with their analog counterparts. The implementation of digital functional blocks makes it possible to achieve a high degree of system integration. Recent advances in IC fabrication technology, particularly the CMOS technology coupled with advanced DSP algorithms and architectures provide possible single chip solutions to complex communication and signal processing sub-systems such as modulators, demodulators, local oscillators, and programmable clock generators, cellular base stations, up converters, down converters, power line communication,wireless local loop base stations etc .

  16. Novel cascade FPGA accelerator for support vector machines classification.

    Science.gov (United States)

    Papadonikolakis, Markos; Bouganis, Christos-Savvas

    2012-07-01

    Support vector machines (SVMs) are a powerful machine learning tool, providing state-of-the-art accuracy to many classification problems. However, SVM classification is a computationally complex task, suffering from linear dependencies on the number of the support vectors and the problem's dimensionality. This paper presents a fully scalable field programmable gate array (FPGA) architecture for the acceleration of SVM classification, which exploits the device heterogeneity and the dynamic range diversities among the dataset attributes. An adaptive and fully-customized processing unit is proposed, which utilizes the available heterogeneous resources of a modern FPGA device in efficient way with respect to the problem's characteristics. The implementation results demonstrate the efficiency of the heterogeneous architecture, presenting a speed-up factor of 2-3 orders of magnitude, compared to the CPU implementation. The proposed architecture outperforms other proposed FPGA and graphic processor unit approaches by more than seven times. Furthermore, based on the special properties of the heterogeneous architecture, this paper introduces the first FPGA-oriented cascade SVM classifier scheme, which exploits the FPGA reconfigurability and intensifies the custom-arithmetic properties of the heterogeneous architecture. The results show that the proposed cascade scheme is able to increase the heterogeneous classifier throughput even further, without introducing any penalty on the resource utilization.

  17. FPGA design and implementation for EIT data acquisition.

    Science.gov (United States)

    Yue, Xicai; McLeod, Chris

    2008-10-01

    OXBACT-5 was designed to meet the challenges involved in working in the intensive care hospital environment focussed particularly on thoracic imaging of patients with respiratory distress and chronic heart failure (CHF). The FPGA-based wireless LAN linked multi-channel EIT data acquisition system (DAS) providing 16 programmable excitation current channels and 64 voltage measurement channels is presented. It contains function modules of a PCI bus interface, direct digital synthesizers, dual-port memory blocks, digital demodulation and all the command and control logic in the FPGA. The whole EIT data acquisition system is fully programmable and reconfigurable from the host PC. The excitation frequency, excitation patterns, the measuring sequence and the gain of each measurement channel can be set from the host PC before each measurement. The demodulation is implemented in the FPGA chip to reduce the data rate between the DAS and the host PC. In addition, measurement process management is achieved in this FPGA chip. Complemented by analogue devices such as ADCs, DACs, analogue buffers and analogue multiplexers, the new FPGA-based EIT DAS system is implemented in a very compact way for bedside use in intensive care units of hospitals. It is intended for applications such as continuous respiration monitoring with data collection at 25 frames per second. Image reconstruction times depend on the choice of 2D or 3D imaging algorithms and the available processing power.

  18. FPGA-Based Pulse Parameter Discovery for Positron Emission Tomography.

    Science.gov (United States)

    Haselman, Michael; Hauck, Scott; Lewellen, Thomas K; Miyaoka, Robert S

    2009-10-24

    Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex digital signal processing algorithms with clock rates well above 100MHz. This, combined with FPGA's low expense and ease of use make them an ideal technology for a data acquisition system for a positron emission tomography (PET) scanner. The University of Washington is producing a series of high-resolution, small-animal PET scanners that utilize FPGAs as the core of the front-end electronics. For these next generation scanners, functions that are typically performed in dedicated circuits, or offline, are being migrated to the FPGA. This will not only simplify the electronics, but the features of modern FPGAs can be utilizes to add significant signal processing power to produce higher resolution images. In this paper we report how we utilize the reconfigurable property of an FPGA to self-calibrate itself to determine pulse parameters necessary for some of the pulse processing steps. Specifically, we show how the FPGA can generate a reference pulse based on actual pulse data instead of a model. We also report how other properties of the photodetector pulse (baseline, pulse length, average pulse energy and event triggers) can be determined automatically by the FPGA.

  19. Real-time panoramic infrared imaging system based on FPGA

    Science.gov (United States)

    Zhang, Hao-Jun; Shen, Yong-Ge

    2010-11-01

    During the past decades, signal processing architecture, which is based on FPGA, conventional DSP processor and host computer, is popular for infrared or other electro-optical systems. With the increasing processing requirement, the former architecture starts to show its limitation in several respects. This paper elaborates a solution based on FPGA for panoramic imaging system as our first step of upgrading the processing module to System-on-Chip (SoC) solution. Firstly, we compare this new architecture with the traditional to show its superiority mainly in the video processing ability, reduction in the development workload and miniaturization of the system architecture. Afterwards, this paper provides in-depth description of this imaging system, including the system architecture and its function, and addresses several related issues followed by the future development. FPGA has developed so rapidly during the past years, not only in silicon device but also in the design flow and tools. In the end, we briefly present our future system development and introduce those new design tools to make up the limitation of the traditional FPGA design methodology. The advanced design flow through Simulink and Xilinx System Generator (Sysgen) has been elaborated, which enables engineers to develop sophisticated DSP algorithms and implement them in FPGA more efficiently. It is believed that this new design approach can shorten system design cycle by allowing rapid prototyping and refining design process.

  20. FPGA-Based Implementation Direct Torque Control of Induction Motor

    Directory of Open Access Journals (Sweden)

    Saber Krim

    2015-02-01

    Full Text Available This paper proposes a digital implementation of the direct torque control (DTC of an Induction Motor (IM with an observation strategy on the Field Programmable Gate Array (FPGA. The hardware solution based on the FPGA is caracterised by fast processing speed due to the parallel processing. In this study the FPGA is used to overcome the limitation of the software solutions (Digital Signal Processor (DSP and Microcontroller. Also, the DTC of IM has many drawbacks such as for example; The open loop pure integration has from the problems of integration especially at the low speed and the variation of the stator resistance due to the temperature. To tackle these problems we use the Sliding Mode Observer (SMO. This observer is used estimate the stator flux, the stator current and the stator resistance. The hardware implementation method is based on Xilinx System Generator (XSG which a modeling tool developed by Xilinx for the design of implemented systems on FPGA; from the design of the DTC with SMO from XSG we can automatically generate the VHDL code. The model of the DTC with SMO has been designed and simulated using XSG blocks, synthesized with Xilinx ISE 12.4 tool and implemented on Xilinx Virtex-V FPGA.

  1. An Auto ranging Data Converter Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    Jithin Krishnan

    2013-06-01

    Full Text Available A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA - i.e. an all-digital analog to digital (A/D converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range detection unit with 7 bits and a sign bit for polarity detection. The analog part of the modulator is done utilizing the LVDS transceiver in the FPGA making it a real digital one. The digital section of sigma delta ADC containing the decimation filter banks is done in a cascaded filter structure form including a CIC decimation filter, droop compensation and half-band filters. The top level module was coded using VHDL and the simulation was carried out with ModelSim and MATLAB.

  2. FPGA Prototyping of RNN Decoder for Convolutional Codes

    Directory of Open Access Journals (Sweden)

    Salcic Zoran

    2006-01-01

    Full Text Available This paper presents prototyping of a recurrent type neural network (RNN convolutional decoder using system-level design specification and design flow that enables easy mapping to the target FPGA architecture. Implementation and the performance measurement results have shown that an RNN decoder for hard-decision decoding coupled with a simple hard-limiting neuron activation function results in a very low complexity, which easily fits into standard Altera FPGA. Moreover, the design methodology allowed modeling of complete testbed for prototyping RNN decoders in simulation and real-time environment (same FPGA, thus enabling evaluation of BER performance characteristics of the decoder for various conditions of communication channel in real time.

  3. Design of a FPGA based ABWR feedwater controller

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hsuanhan; Chou, Hwaipwu; Lin, Chaung [Dept. of Institute of Nuclear Engineering and Science, National Tsing Hua University, Hsinchu (China)

    2012-05-15

    A feedwater controller targeted for an ABWR has been implemented using a modern field programmable gate array (FPGA), and verified using the full scope simulator at Taipower's Lungmen nuclear power station. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulation model of the simulator was employed for verification and validation of the controller design under various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy logic control algorithm is a flexible yet feasible approach for feedwater controller design in nuclear power plant applications.

  4. A Multi-Gigabit Parallel Demodulator and Its FPGA Implementation

    Science.gov (United States)

    Lin, Changxing; Zhang, Jian; Shao, Beibei

    This letter presents the architecture of multi-gigabit parallel demodulator suitable for demodulating high order QAM modulated signal and easy to implement on FPGA platform. The parallel architecture is based on frequency domain implementation of matched filter and timing phase correction. Parallel FIFO based delete-keep algorithm is proposed for timing synchronization, while a kind of reduced constellation phase-frequency detector based parallel decision feedback PLL is designed for carrier synchronization. A fully pipelined parallel adaptive blind equalization algorithm is also proposed. Their parallel implementation structures suitable for FPGA platform are investigated. Besides, in the demonstration of 2Gbps demodulator for 16QAM modulation, the architecture is implemented and validated on a Xilinx V6 FPGA platform with performance loss less than 2dB.

  5. Simple generation of threshold for images binarization on FPGA

    Directory of Open Access Journals (Sweden)

    Egidio Ieno

    2015-12-01

    Full Text Available This paper proposes the FPGA implementation of a threshold algorithm used in the process of image binarization by simple mathematical calculations. The implementation need only one image iteration and its processing time depends on the size of the image. The threshold values of different images obtained through the FPGA implementation are compared with those obtained by Otsu’s method, showing the differences and the visual results of binarization using both methods. The hardware implementation of the algorithm is performed by model-based design supported by the MATLAB®/Simulink® and Xilinx System Generator® tools. The results of the implementation proposal are presented in terms of resource consumption and maximum operating frequency in a Spartan-6 FPGA-based development board. The experimental results are obtained in co-simulation system and show the effectiveness of the proposed method.

  6. Design of A FPGA Based ABWR Feedwater Controller

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hsuan Han; Chou, Hwai Pwu; Lin, Chaung [National Tsing Hua University, Hsinchu (China)

    2011-08-15

    A feedwater controller for the Taipower's Lungmen nuclear power station has been implemented using the modern field programmable gate array (FPGA) and verified using a full scope engineering simulator. The adopted control algorithm is a rule-based fuzzy logic. Point to point validation of the FPGA circuit board has been executed using a digital pattern generator. The simulator was employed for the verification and validation of the controller design with various plant initial conditions. The transient response and the steady state tracking ability were evaluated and showed satisfactory results. The present work has demonstrated that the FPGA based approach incorporated with a rule-based fuzzy control algorithm is a flexible yet feasible approach for controller design in nuclear power plant applications.

  7. Developments of FPGA-based digital back-ends for low frequency antenna arrays at Medicina radio telescopes

    Science.gov (United States)

    Naldi, G.; Bartolini, M.; Mattana, A.; Pupillo, G.; Hickish, J.; Foster, G.; Bianchi, G.; Lingua, A.; Monari, J.; Montebugnoli, S.; Perini, F.; Rusticelli, S.; Schiaffino, M.; Virone, G.; Zarb Adami, K.

    In radio astronomy Field Programmable Gate Array (FPGA) technology is largely used for the implementation of digital signal processing techniques applied to antenna arrays. This is mainly due to the good trade-off among computing resources, power consumption and cost offered by FPGA chip compared to other technologies like ASIC, GPU and CPU. In the last years several digital backend systems based on such devices have been developed at the Medicina radio astronomical station (INAF-IRA, Bologna, Italy). Instruments like FX correlator, direct imager, beamformer, multi-beam system have been successfully designed and realized on CASPER (Collaboration for Astronomy Signal Processing and Electronics Research, https://casper.berkeley.edu) processing boards. In this paper we present the gained experience in this kind of applications.

  8. FPGA Circuit Design Based on Xilinx ISE%基于Xilinx ISE平台的FPGA电路设计

    Institute of Scientific and Technical Information of China (English)

    于东阳; 苏彬

    2012-01-01

    Xilinx ISE is a tool set to design FPGA digital circuit. This tool set can make CPLD/FP-GA digital circuit layout facilely and fleetly. A calculate unit controlled by microinstruction is introduced to describe how to apply VHDL to designing FPGA circuit based on Xilinx.%Xilinx ISE集成综合环境是Xilinx公司的现场可编程逻辑器件数字电路开发工具集.其集成的工具可以使设计人员方便的完成CPLD/FPGA数字电路开发全过程.通过设计一个微指令控制的计算单元,描述基于ISE平台使用VHDL语言进行FPGA电路设计的原理和方法.

  9. Exploring the energy consumption of lightweight blockciphers in FPGA

    DEFF Research Database (Denmark)

    Banik, Subhadeep; Bogdanov, Andrey; Regazzoni, Francesco

    2015-01-01

    . Concentrating on applications that require a number of parallel encryptions, we instantiate several designs on the target FPGA and we analyze how the energy consumption varies in each algorithm when changing the amount of unrolled rounds. Our results, obtained on the Xc6slx45t device of the Spartan6 family......, demonstrate that Present is the most energy efficient algorithm and that the relation between the energy consumption and the number of unrolled rounds measured on FPGA is similar to the one measured on dedicated hardware....

  10. Logic Foundry: Rapid Prototyping for FPGA-Based DSP Systems

    Directory of Open Access Journals (Sweden)

    Bhattacharyya Shuvra S

    2003-01-01

    Full Text Available We introduce the Logic Foundry, a system for the rapid creation and integration of FPGA-based digital signal processing systems. Recognizing that some of the greatest challenges in creating FPGA-based systems occur in the integration of the various components, we have proposed a system that targets the following four areas of integration: design flow integration, component integration, platform integration, and software integration. Using the Logic Foundry, a system can be easily specified, and then automatically constructed and integrated with system level software.

  11. Design and Implementation of Car Parking System on FPGA

    Directory of Open Access Journals (Sweden)

    Ramneet Kaur

    2013-06-01

    Full Text Available As, the number of vehicles are increased day by day in rapid manner. It causes the problem of traffic congestion, pollution (noise and air. To overcome this problem A FPGA based parking system has been proposed. In this paper, parking system is implemented using Finite State Machine modelling. The system has two main modules i.e. identification module and slot checking module. Identification module identifies the visitor. Slot checking module checks the slot status. These modules are modelled in HDL and implemented on FPGA. A prototype of parking system is designed with various interfaces like sensor interfacing, stepper motor and LCD.

  12. Logic synthesis for FPGA-based finite state machines

    CERN Document Server

    Barkalov, Alexander; Kolopienczyk, Malgorzata; Mielcarek, Kamil; Bazydlo, Grzegorz

    2016-01-01

    This book discusses control units represented by the model of a finite state machine (FSM). It contains various original methods and takes into account the peculiarities of field-programmable gate arrays (FPGA) chips and a FSM model. It shows that one of the peculiarities of FPGA chips is the existence of embedded memory blocks (EMB). The book is devoted to the solution of problems of logic synthesis and reduction of hardware amount in control units. The book will be interesting and useful for researchers and PhD students in the area of Electrical Engineering and Computer Science, as well as for designers of modern digital systems.

  13. FPGA prototyping by Verilog examples Xilinx Spartan-3 version

    CERN Document Server

    Chu, Pong P

    2008-01-01

    FPGA Prototyping Using Verilog Examples will provide you with a hands-on introduction to Verilog synthesis and FPGA programming through a "learn by doing" approach. By following the clear, easy-to-understand templates for code development and the numerous practical examples, you can quickly develop and simulate a sophisticated digital circuit, realize it on a prototyping device, and verify the operation of its physical implementation. This introductory text that will provide you with a solid foundation, instill confidence with rigorous examples for complex systems and prepare you for future development tasks.

  14. FPGA-based implementation of sorting networks in MMC applications

    DEFF Research Database (Denmark)

    Ricco, Mattia; Máthé, Lászlo; Teodorescu, Remus

    2016-01-01

    , and they are usually implemented in microcontrollers or DSPs. However, they are not convenient for hardware implementation due to their inherent sequential operation. Instead, the proposed SNs, are suitable for FPGA devices thanks to their fixed parallel structure that allows improving the timing performance......In this paper an implementation technique for Field Programmable Gate Array (FPGA) devices of two Sorting Networks (SNs) used for control of Modular Multilevel Converter (MMC) is presented. In such applications, the classical sorting algorithms are based on repetitive/recursive loops...

  15. FPGA Implementation of a Frame Synchronization Algorithm for Powerline Communications

    Directory of Open Access Journals (Sweden)

    S. Tsakiris

    2009-09-01

    Full Text Available This paper presents an FPGA implementation of a pilot–based time synchronization scheme employing orthogonal frequency division multiplexing for powerline communication channels. The functionality of the algorithm is analyzed and tested over a real powerline residential network. For this purpose, an appropriate transmitter circuit, implemented by an FPGA, and suitable coupling circuits are constructed. The system has been developed using VHDL language on Nallatech XtremeDSP development kits. The communication system operates in the baseband up to 30 MHz. Measurements of the algorithm's good performance in terms of the number of detected frames and timing offset error are taken and compared to simulations of existing algorithms.

  16. Application of Integrated Verification Approach to FPGA-based Safety-Critical I and C System of Nuclear Power Plant

    Energy Technology Data Exchange (ETDEWEB)

    Ahmed, Ibrahim; Heo, Gyunyoung [Kyunghee Univ., Yongin (Korea, Republic of); Jung, Jaecheon [KEPCO, Ulsan (Korea, Republic of)

    2016-10-15

    Safety-critical instrumentation and control (I and C) system in nuclear power plant (NPP) implemented on programmable logic controllers (PLCs) plays a vital role in safe operation of the plant. The challenges such as fast obsolescence, the vulnerability to cyber-attack, and other related issues of software systems have currently led to the consideration of field programmable gate arrays (FPGAs) as an alternative to PLCs because of their advantages and hardware related benefits. Generally in FPGA design verification, the designers make use of verification techniques by writing the test benches which involved various stages of verification activities of register-transfer level (RTL), gate-level, and place and route. Writing the test benches is considerably time consuming and require a lot of efforts to achieve a satisfied desire results. Furthermore, performing the verification at each stage is a major bottleneck and demanded much activities and time. In addition, verification is conceivably, the most difficult and complicated aspect of any design. Therefore, in view of these, this work applied an integrated verification approach to the verification of FPGA-based I and C system in NPP that simultaneously verified the whole design modules using MATLAB/Simulink HDL Co-simulation models. Verification is conceivably, the most difficult and complicated aspect of any design, and an FPGA design is not an exception. Therefore, in this work, we introduced and discussed how an application of integrated verification technique to the verification and testing of FPGA-based I and C system design in NPP can facilitate the verification processes, and verify the entire design modules of the system simultaneously using MATLAB/Simulink HDL co-simulation models. In conclusion, the results showed that, the integrated verification approach through MATLAB/Simulink models, if applied to any design to be verified, could speed up the design verification and reduce the V and V tasks.

  17. Reconfiguration-based implementation of SVM classifier on FPGA for Classifying Microarray data.

    Science.gov (United States)

    Hussain, Hanaa M; Benkrid, Khaled; Seker, Huseyin

    2013-01-01

    Classifying Microarray data, which are of high dimensional nature, requires high computational power. Support Vector Machines-based classifier (SVM) is among the most common and successful classifiers used in the analysis of Microarray data but also requires high computational power due to its complex mathematical architecture. Implementing SVM on hardware exploits the parallelism available within the algorithm kernels to accelerate the classification of Microarray data. In this work, a flexible, dynamically and partially reconfigurable implementation of the SVM classifier on Field Programmable Gate Array (FPGA) is presented. The SVM architecture achieved up to 85× speed-up over equivalent general purpose processor (GPP) showing the capability of FPGAs in enhancing the performance of SVM-based analysis of Microarray data as well as future bioinformatics applications.

  18. 用局部冻结法修复损坏的地铁隧道%Partial Freezing Method Applied in the Restoration of Damaged Subway Tunnels

    Institute of Scientific and Technical Information of China (English)

    孙闯; 周兴旺; 韩玉福

    2011-01-01

    京沪高铁桩基施工中造成上海某地铁隧道管片破损,大量淤泥流入隧道内部,工程采用台阶式封堵墙对隧道内部土体进行封堵,并对破损隧道内部进行注浆充填.隧道上部土体采用地面充填加固注浆的方法加固扰动土层;修复段采用“地面垂直冻结加固土体,结合隧道内水平冻结加固土体,隧道内开挖构筑”的施工方案;在破损隧道上部及四周3 m范围内进行局部冻结,形成强度高,封闭性好的冻土帷幕.冻土帷幕形成后采用暗挖矿山法进行修复段隧道的开挖构筑施工,对破损管片采用原位修复方案,施工取得圆满成功.通过介绍隧道修复设计方案,并对现场监测数据进行分析,为类似工程提供借鉴.%The construction of the pile foundation of Beijing-Shanghai high-speed railway damaged the tunnel lining of a segment of Shanghai subway with large amounts of sludge silted into the tunnel. This paper introduces the re pairing of the damaged tunnel and analyzes the site monitoring data to provide reference for alike projects. Firstly, stepped plugging wall was used to plug the solum in the tunnel, and the internal of the damaged tunnel was grou ted. The upper solum in the tunnel was treated by ground filling and grouting to reinforce the turbulent solum. Mo reover, the restoration segment was reinforced by vertical freezing on the ground and horizontal freezing as well as excavation construction inside the tunnel. Freezing soil curtain with high strength and good sealing property was produced by partial freezing in the upper damaged tunnel and in its surrounding 3 meters area. Subsequently, min ing method was employed in the excavation and the damaged lining was repaired by in-situ restoration. The restora tion finally achieved great success.

  19. DESIGN AND IMPLEMENTATION OF FPGA BASED SIGNAL PROCESSING CARD

    Directory of Open Access Journals (Sweden)

    Priya Gupta

    2011-09-01

    Full Text Available This paper describes the design of FPGA based signal processing card. An on board real time digital signal processing system is designed using FPGA. The platform can decode process of various kinds of digital and analog signals simultaneously. The design trend in this card is towards small size, high integration and fast real time processing. For the optimum performance a 16 bit 1 MSPS ADC is used which is interfaced with FPGA to make all the data processing on board in real time. This card can be used in many signal processing based applications like audio signal processing, audio compression, digital image processing, video compression, speech processing, speech recognition, digital communications by interfacing several separate board using inbuilt I/O’s, each with a number of input channels that will communicate with each other in real time over a high speed communication link. The resulting images can be displayed directly on LCD or OLED panel displays using I/O’s peripherals. The project introduces many challenging issues, which are being addressed in turn with different prototype designs. These issues are the ADC performance, interfacing the ADCs to the FPGA, implementing the flexible processing algorithms and high speed interconnection between the boards.

  20. Single Event Effects in FPGA Devices 2015-2016

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    This presentation provides an overview of single event effects in FPGA devices 2015-2016 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing, mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  1. Single Event Effects in FPGA Devices 2014-2015

    Science.gov (United States)

    Berg, Melanie D.; LaBel, Kenneth A.; Pellish, Jonathan

    2015-01-01

    This presentation provides an overview of single event effects in FPGA devices 2014-2015 including commercial Xilinx V5 heavy ion accelerated testing, Xilinx Kintex-7 heavy ion accelerated testing. Mitigation study, and investigation of various types of triple modular redundancy (TMR) for commercial SRAM based FPGAs.

  2. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    Science.gov (United States)

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  3. Energy Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Kenn Toft, Jakob; Nannarelli, Alberto

    2014-01-01

    Field Programmable Gate Arrays (FPGAs) based accelerators are very suitable to implement application-specific processors using uncommon operations or number systems. In this work, we design FPGA-based accelerators for two financial computations with different characteristics and we compare...

  4. Junction Temperature Aware Energy Efficient Router Design on FPGA

    DEFF Research Database (Denmark)

    Thind, Vandana; Sharma, Shivani; Minwer, M H

    2015-01-01

    Energy, Power and efficiency are very much related to each other. To make any system efficient, Power consumed by it must be minimized or we can say that power dissipation should be less. In our research we tried to make a energy efficient router design on FPGA by varying junction temperature...

  5. FPGA design best practices for team-based reuse

    CERN Document Server

    Simpson, Philip Andrew

    2015-01-01

    This book describes best practices for successful FPGA design. It is the result of the author’s meetings with hundreds of customers on the challenges facing each of their FPGA design teams. By gaining an understanding into their design environments, processes, what works and what does not work, key areas of concern in implementing system designs have been identified and a recommended design methodology to overcome these challenges has been developed. This book’s content has a strong focus on design teams that are spread across sites. The goal being to increase the productivity of FPGA design teams by establishing a common methodology across design teams; enabling the exchange of design blocks across teams. Coverage includes the complete FPGA design flow, from the basics to advanced techniques.  This new edition has been enhanced to include new sections on System modeling, embedded design and high level design. The original sections on Design Environment, RTL design and timing closure have all been expand...

  6. FPGA Mezzanine Cards for CERN’s Accelerator Control System

    CERN Document Server

    Alvarez, P R; Lewis, J; Serrano, J; Wlostowski, T

    2009-01-01

    Field Programmable Gate Arrays (FPGAs) have become a key player in modern real time control systems. They offer determinism, simple design, high performance and versatility. A typical hardware architecture consists of an FPGA interfaced with a control bus and a variable number of digital IOs, ADCs and DACs depending on the application. Until recently the low-cost hardware paradigm has been using mezzanines containing a front end interface plus custom logic (typically an FPGA) and a local bus that interfaces the mezzanine to a carrier. As FPGAs grow in size and shrink in price, hardware reuse, testability and bus access speed could be improved if the user logic is moved to the carrier. The new FPGA Mezzanine Card (FMC) Vita 57 standard is a good example of this new paradigm. In this paper we present a standard kit of FPGA carriers and IO mezzanines for accelerator control. Carriers form factors will be VME, PCI and PCIe. The carriers will feature White Rabbit support for accurate synchronization of distributed...

  7. Pipelined CPU Design with FPGA in Teaching Computer Architecture

    Science.gov (United States)

    Lee, Jong Hyuk; Lee, Seung Eun; Yu, Heon Chang; Suh, Taeweon

    2012-01-01

    This paper presents a pipelined CPU design project with a field programmable gate array (FPGA) system in a computer architecture course. The class project is a five-stage pipelined 32-bit MIPS design with experiments on the Altera DE2 board. For proper scheduling, milestones were set every one or two weeks to help students complete the project on…

  8. FPGA based fast synchronous serial multi-wire links synchronization

    Science.gov (United States)

    Pozniak, Krzysztof T.

    2013-10-01

    The paper debates synchronization method of multi-wire, serial link of constant latency, by means of pseudo-random numbers generators. The solution was designed for various families of FPGA circuits. There were debated synchronization algorithm and functional structure of parameterized transmitter and receiver modules. The modules were realized in VHDL language in a behavioral form.

  9. FPGA implementation of filtered image using 2D Gaussian filter

    Directory of Open Access Journals (Sweden)

    Leila kabbai

    2016-07-01

    Full Text Available Image filtering is one of the very useful techniques in image processing and computer vision. It is used to eliminate useless details and noise from an image. In this paper, a hardware implementation of image filtered using 2D Gaussian Filter will be present. The Gaussian filter architecture will be described using a different way to implement convolution module. Thus, multiplication is in the heart of convolution module, for this reason, three different ways to implement multiplication operations will be presented. The first way is done using the standard method. The second way uses Field Programmable Gate Array (FPGA features Digital Signal Processor (DSP to ensure and make fast the scalability of the effective FPGA resource and then to speed up calculation. The third way uses real multiplier for more precision and a the maximum uses of FPGA resources. In this paper, we compare the image quality of hardware (VHDL and software (MATLAB implementation using the Peak Signal-to-Noise Ratio (PSNR. Also, the FPGA resource usage for different sizes of Gaussian kernel will be presented in order to provide a comparison between fixed-point and floating point implementations.

  10. A displacement sensor of dual-light based on FPGA

    Institute of Scientific and Technical Information of China (English)

    2007-01-01

    The dual-light displacement sensor is presented to obtain a higher accuracy compared with the single. The structure and principle of the system are also introduced, and the hardware and software are brought in too. The function of the system is feasible through the experiments and simulating the data process based on FPGA.

  11. Field-Programmable Gate Array (FPGA) Emulation for Computer Architecture

    Science.gov (United States)

    2009-08-01

    Inside the FPGA, we currently use a single-channel 233 MHz DDR2 memory controller based on the BEE3 memory controller [1]. It supports up to a 2GB dual...pages between cores. 28 13.0 REFERENCES [1] DDR2 DRAM Controller for BEE3, online at http://research.microsoft.com/en-us/projects/BEE3/, 2008

  12. Wide dynamic range FPGA-based TDC for monitoring a trigger timing distribution system in linear accelerators

    Science.gov (United States)

    Suwada, T.; Miyahara, F.; Furukawa, K.; Shoji, M.; Ikeno, M.; Tanaka, M.

    2015-06-01

    A new field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with a wide dynamic range greater than 20 ms has been developed to monitor the timing of various pulsed devices in the trigger timing distribution system of the KEKB injector linac for the Super KEK B-factory project. The pulsed devices are driven by feeding regular as well as any irregular (or event-based) timing pulses. The timing pulses are distributed to these pulsed devices along the linac beam line with fiber-optic links on the basis of the parameters to be set pulse-by-pulse in the event-based timing and control system within 20 ms. For monitoring the timing as precisely as possible, a 16-ch FPGA-based TDC has been developed on a Xilinx Spartan-6 FPGA equipped on VME board with a resolution of 1 ns. The resolution was achieved by applying a multisampling technique, and the accuracies were 2.6 ns (rms) and less than 1 ns (rms) within the dynamic ranges of 20 ms and 7.5 ms, respectively. The various nonlinear effects were improved by implementing a high-precision external clock with a built-in temperature-compensated crystal oscillator.

  13. Wide dynamic range FPGA-based TDC for monitoring a trigger timing distribution system in linear accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Suwada, T., E-mail: tsuyoshi.suwada@kek.jp [Accelerator Laboratory, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Department of Accelerator Science, Graduate University for Advanced Studies (SOKENDAI), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Miyahara, F.; Furukawa, K. [Accelerator Laboratory, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Department of Accelerator Science, Graduate University for Advanced Studies (SOKENDAI), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Shoji, M.; Ikeno, M.; Tanaka, M. [Institute of Particle and Nuclear Studies, High Energy Accelerator Research Organization (KEK), 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan)

    2015-06-21

    A new field-programmable gate array (FPGA)-based time-to-digital converter (TDC) with a wide dynamic range greater than 20 ms has been developed to monitor the timing of various pulsed devices in the trigger timing distribution system of the KEKB injector linac for the Super KEK B-factory project. The pulsed devices are driven by feeding regular as well as any irregular (or event-based) timing pulses. The timing pulses are distributed to these pulsed devices along the linac beam line with fiber-optic links on the basis of the parameters to be set pulse-by-pulse in the event-based timing and control system within 20 ms. For monitoring the timing as precisely as possible, a 16-ch FPGA-based TDC has been developed on a Xilinx Spartan-6 FPGA equipped on VME board with a resolution of 1 ns. The resolution was achieved by applying a multisampling technique, and the accuracies were 2.6 ns (rms) and less than 1 ns (rms) within the dynamic ranges of 20 ms and 7.5 ms, respectively. The various nonlinear effects were improved by implementing a high-precision external clock with a built-in temperature-compensated crystal oscillator.

  14. SEU mitigation exploratory tests in a ITER related FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Batista, Antonio J.N., E-mail: toquim@ipfn.tecnico.ulisboa.pt [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Leong, Carlos [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Santos, Bruno; Fernandes, Ana [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal); Ramos, Ana Rita; Santos, Joana P.; Marques, José G. [Centro de Ciências e Tecnologias Nucleares (C2TN), Instituto Superior Técnico (IST), Universidade de Lisboa - UL, 2695-066 Bobadela (Portugal); Teixeira, Isabel C.; Teixeira, João P. [Instituto de Engenharia de Sistemas e Computadores – Investigação e Desenvolvimento (INESC-ID), 1000-029 Lisboa (Portugal); Sousa, Jorge; Gonçalves, Bruno [Instituto de Plasmas e Fusão Nuclear, Instituto Superior Técnico, Universidade de Lisboa, 1049-001 Lisboa (Portugal)

    2017-05-15

    Data acquisition hardware of ITER diagnostics if located in the port cells of the tokamak, as an example, will be irradiated with neutrons during the fusion reactor operation. Due to this reason the majority of the hardware containing Field Programmable Gate Arrays (FPGA) will be placed after the ITER bio-shield, such as the cubicles instrumentation room. Nevertheless, it is worth to explore real-time mitigation of soft-errors caused by neutrons radiation in ITER related FPGAs. A Virtex-6 FPGA from Xilinx (XC6VLX365T-1FFG1156C) is used on the ATCA-IO-PROCESSOR board, included in the ITER Catalog of Instrumentation & Control (I & C) products – Fast Controllers. The Virtex-6 is a re-programmable logic device where the configuration is stored in Static RAM (SRAM), the functional data is stored in dedicated Block RAM (BRAM) and the functional state logic in Flip-Flops. Single Event Upsets (SEU) due to the ionizing radiation of neutrons cause soft errors, unintended changes (bit-flips) of the logic values stored in the state elements of the FPGA. Real-time SEU monitoring and soft errors repairing, when possible, were explored in this work. An FPGA built-in Soft Error Mitigation (SEM) controller detects and corrects soft errors in the FPGA Configuration Memory (CM). BRAM based SEU sensors with Error Correction Code (ECC) detect and repair the respective BRAM contents. Real-time mitigation of SEU can increase reliability and availability of data acquisition hardware for nuclear applications. The results of the tests performed using the SEM controller and the SEU sensors are presented for a Virtex-6 FPGA (XC6VLX240T-1FFG1156C) when irradiated with neutrons from the Portuguese Research Reactor (RPI), a 1 MW nuclear fission reactor, operated by IST in the neighborhood of Lisbon. Results show that the proposed SEU mitigation technique is able to repair the majority of the detected SEU soft-errors in the FPGA memory.

  15. Photoelectric radar servo control system based on ARM+FPGA

    Science.gov (United States)

    Wu, Kaixuan; Zhang, Yue; Li, Yeqiu; Dai, Qin; Yao, Jun

    2016-01-01

    In order to get smaller, faster, and more responsive requirements of the photoelectric radar servo control system. We propose a set of core ARM + FPGA architecture servo controller. Parallel processing capability of FPGA to be used for the encoder feedback data, PWM carrier modulation, A, B code decoding processing and so on; Utilizing the advantage of imaging design in ARM Embedded systems achieves high-speed implementation of the PID algorithm. After the actual experiment, the closed-loop speed of response of the system cycles up to 2000 times/s, in the case of excellent precision turntable shaft, using a PID algorithm to achieve the servo position control with the accuracy of + -1 encoder input code. Firstly, This article carry on in-depth study of the embedded servo control system hardware to determine the ARM and FPGA chip as the main chip with systems based on a pre-measured target required to achieve performance requirements, this article based on ARM chip used Samsung S3C2440 chip of ARM7 architecture , the FPGA chip is chosen xilinx's XC3S400 . ARM and FPGA communicate by using SPI bus, the advantage of using SPI bus is saving a lot of pins for easy system upgrades required thereafter. The system gets the speed datas through the photoelectric-encoder that transports the datas to the FPGA, Then the system transmits the datas through the FPGA to ARM, transforms speed datas into the corresponding position and velocity data in a timely manner, prepares the corresponding PWM wave to control motor rotation by making comparison between the position data and the velocity data setted in advance . According to the system requirements to draw the schematics of the photoelectric radar servo control system and PCB board to produce specially. Secondly, using PID algorithm to control the servo system, the datas of speed obtained from photoelectric-encoder is calculated position data and speed data via high-speed digital PID algorithm and coordinate models. Finally, a

  16. Partial priapism

    DEFF Research Database (Denmark)

    Høyerup, Peter; Dahl, Claus; Azawi, Nessn Htum

    2014-01-01

    Partial priapism, also called partial segmental thrombosis of the corpus cavernosum, is a rare urological condition. Factors such as bicycle riding, drug usage, penile trauma and haematological diseases have been associated with the condition. Medical treatment with low molecular weight heparin (...... (LMWH) or acetylsalicylic acid is first choice treatment, and surgery is preserved for patients unresponsive to analgesics. In this report we describe the case of a 70-year-old man with partial priapism after blood transfusions treated successfully with LMWH....

  17. In-house development of an FPGA-based MCA8K for gamma-ray spectrometer.

    Science.gov (United States)

    Lanh, Dang; Son, Pham Ngoc; Son, Nguyen An

    2014-01-01

    The objective of this work is domestic development of electronics instruments. It used for measuring ionization radiation and practical training at Nuclear Research Institute (NRI), Dalat, Vietnam. The aim of this work is to study and develop a novel MCA8k for Gamma-ray spectrometer concerning experimental nuclear physics. An approach for design and construction of the aforementioned instrument is to apply logic integrating techniques via Field Programmable Gate Arrays (FPGA) under Max + PlusII, Altera. The instrument allows interfacing to PC with self-developed application software. Scientific significance of this work is partly to contribute to opening a research direction in the field of nuclear electronics science for design and construction of radiation measurement instruments with the advanced IC technology in Vietnam. Practical significance of this work is partly to contribute to enhancement of capabilities in developing radiation measurement instruments for experimental research as well as practical training in nuclear physics. The advantages of FPGA: overcoming ballistic deficit, decrement of serial and parallel noise, flexible in programming, control of the system by software without an interfere of hardware. The disadvantages of FPGA: requirement of good knowledge of VHDL and professional tools for development of a expected project. A new electronics module of MCA8k has been achieved. Some main results obtained from the experimental testing are as follows: differential nonlinearity (DNL) of FPGA-MCA8k approximately 1.27%, integral nonlinearity (INL) = 0.607%, time conversion ≈ 2.2 μs, deadtime (DT) is 0.75%. Data Acquisition Program MCANRI written in VC (+ +)6.0, self-executed under Windows XP environment.

  18. Compact FPGA-based beamformer using oversampled 1-bit A/D converters.

    Science.gov (United States)

    Tomov, Borislav Gueorguiev; Jensen, Jørgen Arendt

    2005-05-01

    A compact medical ultrasound beamformer architecture that uses oversampled 1-bit analog-to-digital (A/D) converters is presented. Sparse sample processing is used, as the echo signal for the image lines is reconstructed in 512 equidistant focal points along the line through its in-phase and quadrature components. That information is sufficient for presenting a B-mode image and creating a color flow map. The high sampling rate provides the necessary delay resolution for the focusing. The low channel data width (1-bit) makes it possible to construct a compact beamformer logic. The signal reconstruction is done using finite impulse reponse (FIR) filters, applied on selected bit sequences of the delta-sigma modulator output stream. The approach allows for a multichannel beamformer to fit in a single field programmable gate array (FPGA) device. A 32-channel beamformer is estimated to occupy 50% of the available logic resources in a commercially available mid-range FPGA, and to be able to operate at 129 MHz. Simulation of the architecture at 140 MHz provides images with a dynamic range approaching 60 dB for an excitation frequency of 3 MHz.

  19. Performance Evaluation and Implementation of FPGA Based SGSF in Smart Diagnostic Applications.

    Science.gov (United States)

    Agarwal, Shivangi; Rani, Asha; Singh, Vijander; Mittal, A P

    2016-03-01

    The main objective of the paper is to implement Savitzky Golay Smoothing Filter (SGSF) so as to apply in pre-processing of real time smart medical diagnostic systems. As very important information of EEG and ECG waveforms lies in the peak of the signal, hence it becomes absolutely necessary to filter noise and artifacts from the signal. The implemented filter should be able to reject the noise efficiently along with the least distortion from the original signal. The shape preserving characteristics of the filter are determined by introducing different noise levels in the signal. The designed filter is tested on synthetic signals of EEG and ECG by adding different types of noise and the performance is analysed on various parameters, i.e., SNR, SSNR, SNRI, MSE, COR and signal distortion of the final output. The smoothing performance comparison of SGSF with the most commonly used Moving Average Filter (MAF) proves that SGSF is more efficient. Hence it is suggested that MAF can be replaced by SGSF. For real time issues, it is further implemented on reconfigurable architectures so as to achieve high speed, low cost, low power consumption and less area. Therefore SGSF is realized on FPGA platform to combine the advantages of both. Real time EEG and ECG signals are also considered for experimentation. The experimental results show that the proposed methodology (FPGA-SGSF) significantly reduces the processing time and preserves the actual features of the signal.

  20. Acceleration of EM-Based 3D CT Reconstruction Using FPGA.

    Science.gov (United States)

    Choi, Young-Kyu; Cong, Jason

    2016-06-01

    Reducing radiation doses is one of the key concerns in computed tomography (CT) based 3D reconstruction. Although iterative methods such as the expectation maximization (EM) algorithm can be used to address this issue, applying this algorithm to practice is difficult due to the long execution time. Our goal is to decrease this long execution time to an order of a few minutes, so that low-dose 3D reconstruction can be performed even in time-critical events. In this paper we introduce a novel parallel scheme that takes advantage of numerous block RAMs on field-programmable gate arrays (FPGAs). Also, an external memory bandwidth reduction strategy is presented to reuse both the sinogram and the voxel intensity. Moreover, a customized processing engine based on the FPGA is presented to increase overall throughput while reducing the logic consumption. Finally, a hardware and software flow is proposed to quickly construct a design for various CT machines. The complete reconstruction system is implemented on an FPGA-based server-class node. Experiments on actual patient data show that a 26.9 × speedup can be achieved over a 16-thread multicore CPU implementation.

  1. Cost-efficient FPGA implementation of basal ganglia and their Parkinsonian analysis.

    Science.gov (United States)

    Yang, Shuangming; Wang, Jiang; Li, Shunan; Deng, Bin; Wei, Xile; Yu, Haitao; Li, Huiyan

    2015-11-01

    The basal ganglia (BG) comprise multiple subcortical nuclei, which are responsible for cognition and other functions. Developing a brain-machine interface (BMI) demands a suitable solution for the real-time implementation of a portable BG. In this study, we used a digital hardware implementation of a BG network containing 256 modified Izhikevich neurons and 2048 synapses to reliably reproduce the biological characteristics of BG on a single field programmable gate array (FPGA) core. We also highlighted the role of Parkinsonian analysis by considering neural dynamics in the design of the hardware-based architecture. Thus, we developed a multi-precision architecture based on a precise analysis using the FPGA-based platform with fixed-point arithmetic. The proposed embedding BG network can be applied to intelligent agents and neurorobotics, as well as in BMI projects with clinical applications. Although we only characterized the BG network with Izhikevich models, the proposed approach can also be extended to more complex neuron models and other types of functional networks.

  2. FFT Splitting for Improved FPGA-Based Acquisition of GNSS Signals

    Directory of Open Access Journals (Sweden)

    Jérôme Leclère

    2015-01-01

    Full Text Available With modern global navigation satellite system (GNSS signals, the FFT-based parallel code search acquisition must handle the frequent sign transitions due to the data or the secondary code. There is a straightforward solution to this problem, which consists in doubling the length of the FFTs, leading to a significant increase of the complexity. The authors already proposed a method to reduce the complexity without impairing the probability of detection. In particular, this led to a 50% memory reduction for an FPGA implementation. In this paper, the authors propose another approach, namely, the splitting of a large FFT into three or five smaller FFTs, providing better performances and higher flexibility. For an FPGA implementation, compared to the previously proposed approach, at the expense of a slight increase of the logic and multiplier resources, the splitting into three and five allows, respectively, a reduction of 40% and 64% of the memory, and of 25% and 37.5% of the processing time. Moreover, with the splitting into three FFTs, the algorithm is applicable for sampling frequencies up to 24.576 MHz for L5 band signals, against 21.846 MHz with the previously proposed algorithm. The algorithm is applied here to the GPS L5 and Galileo E5a, E5b, and E1 signals.

  3. An FPGA Scalable Software Defined Radio Platform Design for Educational and Research Purposes

    Directory of Open Access Journals (Sweden)

    Marcos Hervás

    2016-06-01

    Full Text Available In a digital modem design, the integration of the Analog to Digital Converters (ADC and Digital to Analog Converters (DAC with the core processor is usually a major issue for the designer. In this paper an FPGA scalable Software Defined Radio platform based on a Spartan-6 as a control unit is presented, developed for both educational and research purposes, which can fit the different application requirements in terms of analog front-end performance, processing unit and cost. The resolution and sampling frequency of the analog front-end are its main adjustable parameters. The processing core requirements involve the FPGA and the communication ports. A multidisciplinary working group was required to design a high performance system for both analog front-end and digital processing core in terms of signal integrity and electromagnetic compatibility. The platform has 5 different peripheral ports ranging from 16 kbps to 2.5 Gbps. The communication ports allow our students to develop a high range of applications for both on-site and online courses applying teaching methodology based on learning by doing using a real system to help them to reach other transversal skills.

  4. FPGA-based real-time simulation of power converters of renewable energy sources

    Energy Technology Data Exchange (ETDEWEB)

    Kokenyesi, Tamas; Varjasi, Istvan [Budapest University of Technology and Economics, Department of Automation and Applied Informatics (Hungary)], e-mail: kokenyesi.tamas@gmail.com, email: varjasi@aut.bme.hu

    2011-07-01

    This paper presents a hardware-in-the-loop testing (HIL) approach based on a field programmable gate array (FPGA) real-time simulation with real measured signals designed to reduce the cost and time for testing the main circuit of a power converter significantly. This method allows the control unit to measure its outputs on the same signal level in a completely transparent way, unlike other computer based simulation methods. As an example, a simulator for a three-phase inverter used for DC/AC conversion or frequency control is described and the simulated network illustrated. The calculation procedure and relative equations are also detailed, with simulation parameters and some measurement results being presented. It was found that the main advantage of this method is speed, which was only limited by the actual capabilities of the FPGA used. This method can be applied to a wide variety of analog circuits, reducing time to market. More complex circuits and higher frequencies could be simulated in the future with the evolution of FPGAs.

  5. Study of FPGA and GPU based pixel calibration for ATLAS IBL

    CERN Document Server

    Dopke, J; The ATLAS collaboration; Flick, T; Gabrielli, A; Grosse-Knetter, J; Krieger, N; Kugel, A; Polini, A; Schroer, N

    2010-01-01

    The insertable B-layer (IBL) is a new stage of the ATLAS pixel detector to be installed around 2014. 12 million pixel are attached to new FE-I4 readout ASICs, each controlling 26680 pixel. Compared to the existing FE-I3 based detector the new system features higher readout speed of 160Mbit/s per ASIC and simplified control. For calibration defined charges are applied to all pixels and the resulting time-over-threshold values are evaluated. In the present system multiple sets of two custom VME cards which employ a combination of FPGA and DSP technology are used for I/O interfacing, formatting and processing. The execution time of 51s to perform a threshold scan on a FE-I3 module of 46080 pixel is composed of 8s control, 29s transfer, 7.5s histogramming and 7s analysis. Extrapolating to FE-I4 the times per module of 53760 pixels are 12ms, 5.8s, 9.4s and 8.3s, a total of 23.5s. We present a proposal for a novel approach to the dominant tasks for FE-I4: histogramming and ananlysis. An FPGA-based histogramming uni...

  6. Hyperbolic partial differential equations

    CERN Document Server

    Witten, Matthew

    1986-01-01

    Hyperbolic Partial Differential Equations III is a refereed journal issue that explores the applications, theory, and/or applied methods related to hyperbolic partial differential equations, or problems arising out of hyperbolic partial differential equations, in any area of research. This journal issue is interested in all types of articles in terms of review, mini-monograph, standard study, or short communication. Some studies presented in this journal include discretization of ideal fluid dynamics in the Eulerian representation; a Riemann problem in gas dynamics with bifurcation; periodic M

  7. Adaptation of a Fault-Tolerant Fpga-Based Launch Sequencer as a Cubesat Payload Processor

    Science.gov (United States)

    2014-06-01

    FAULT–TOLERANT FPGA –BASED LAUNCH SEQUENCER AS A CUBESAT PAYLOAD PROCESSOR by Jordan K. Goff June 2014 Thesis Co-Advisors: Herschel H...TYPE AND DATES COVERED Master’s Thesis 4. TITLE AND SUBTITLE ADAPTATION OF A FAULT–TOLERANT FPGA –BASED LAUNCH SEQUENCER AS A CUBESAT PAYLOAD...set. This processor is implemented on a field programmable gate array ( FPGA ) and will be used as the foundation for a payload processor on a cube

  8. HSTL IO Standard Based Energy Efficient Multiplier Design using Nikhilam Navatashcaramam Dashatah on 28nm FPGA

    DEFF Research Database (Denmark)

    Madhok, Shivani; Pandey, Bishwajeet; Kaur, Amanpreet

    2015-01-01

    standards. Frequency scaling is one of the best energy efficient techniques for FPGA based VLSI design and is used in this paper. At the end we can conclude that we can conclude that there is 23-40% saving of total power dissipation by using SSTL IO standard at 25 degree Celsius. The main reason for power...... consumption is leakage power at different IO Standards and at different frequencies. In this research work only FPGA work has been performed not ultra scale FPGA....

  9. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    Directory of Open Access Journals (Sweden)

    D. K.M. Al-Aubidy

    2007-01-01

    Full Text Available This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemented to write assembly programs in this teaching tool. In addition to the micro-operation simulation, the complete configuration can be run on Xilinx Spartan-3 FPGA board. Such implementation offers good code density, easy customization, easily developed software, small area, and high performance at low cost.

  10. Sigma Delta Modulation Based Ternary FIR Filter Mapping on FPGA

    Directory of Open Access Journals (Sweden)

    Tayabuddin Memon

    2011-07-01

    Full Text Available In this paper single-bit SDM (Sigma Delta Modulation based TFF (Ternary FIR Filter with balanced ternary coefficients (i.e. -1/0/+1 has been mapped on small commercially available FPGAs (Field Programmable Gate Arrays. Filter coefficients were obtained using second order sigma delta modulator. The filter structure is based on a hierarchical adder tree that can easily be pipelined for high performance purpose. Filter structure was coded in VHDL (Very High Speed Integrated Circuit Hardware Description Language and simulated in Quartus-II software. The filter exhibits low I/O (Input Output and core area usage and high performance-achieving clock speeds close to 200MHz on a low-cost FPGA and over 500MHz on a latest FPGA commercially available device. This single-bit ternary filter is intended to support video and audio processing applications in mobile communication systems.

  11. FPGA Implementation of a SAR Two-dimensional Autofocus Approach

    Directory of Open Access Journals (Sweden)

    Guo Jiangzhe

    2016-08-01

    Full Text Available For real-time autofocus of defocused images produced by Synthetic Aperture Radar (SAR, the twodimensional autofocus approach proposed in this study is used to correct the residual range cell migration and compensate for the phase error. Next, a block-wise Phase Gradient Autofocus (PGA is used to correct the space-variant phase error. The Field-Programmable Gate Array (FPGA design procedures, resource utilization, processing speed, accuracy, and autofocus are discussed in detail. The system is able to autofocus an 8K × 8K complex image with single precision within 5.7 s when the FPGA works at 200 MHz. The processing of the measured data verifies the effectiveness and real-time capability of the proposed method.

  12. High-Performance CCSDS Encapsulation Service Implementation in FPGA

    Science.gov (United States)

    Clare, Loren P.; Torgerson, Jordan L.; Pang, Jackson

    2010-01-01

    The Consultative Committee for Space Data Systems (CCSDS) Encapsulation Service is a convergence layer between lower-layer space data link framing protocols, such as CCSDS Advanced Orbiting System (AOS), and higher-layer networking protocols, such as CFDP (CCSDS File Delivery Protocol) and Internet Protocol Extension (IPE). CCSDS Encapsulation Service is considered part of the data link layer. The CCSDS AOS implementation is described in the preceding article. Recent advancement in RF modem technology has allowed multi-megabit transmission over space links. With this increase in data rate, the CCSDS Encapsulation Service needs to be optimized to both reduce energy consumption and operate at a high rate. CCSDS Encapsulation Service has been implemented as an intellectual property core so that the aforementioned problems are solved by way of operating the CCSDS Encapsulation Service inside an FPGA. The CCSDS En capsula tion Service in FPGA implementation consists of both packetizing and de-packetizing features

  13. FPGA Simulation Engine for Customized Construction of Neural Microcircuits.

    Science.gov (United States)

    Blair, Hugh T; Cong, Jason; Wu, Di

    2013-04-01

    In this paper we describe an FPGA-based platform for high-performance and low-power simulation of neural microcircuits composed from integrate-and-fire (IAF) neurons. Based on high-level synthesis, our platform uses design templates to map hierarchies of neuron model to logic fabrics. This approach bypasses high design complexity and enables easy optimization and design space exploration. We demonstrate the benefits of our platform by simulating a variety of neural microcircuits that perform oscillatory path integration, which evidence suggests may be a critical building block of the navigation system inside a rodent's brain. Experiments show that our FPGA simulation engine for oscillatory neural microcircuits can achieve up to 39× speedup compared to software benchmarks on commodity CPU, and 232× energy reduction compared to embedded ARM core.

  14. FPGA-based digital convolution for wireless applications

    CERN Document Server

    Guan, Lei

    2017-01-01

    This book presents essential perspectives on digital convolutions in wireless communications systems and illustrates their corresponding efficient real-time field-programmable gate array (FPGA) implementations. Covering these digital convolutions from basic concept to vivid simulation/illustration, the book is also supplemented with MS PowerPoint presentations to aid in comprehension. FPGAs or generic all programmable devices will soon become widespread, serving as the “brains” of all types of real-time smart signal processing systems, like smart networks, smart homes and smart cities. The book examines digital convolution by bringing together the following main elements: the fundamental theory behind the mathematical formulae together with corresponding physical phenomena; virtualized algorithm simulation together with benchmark real-time FPGA implementations; and detailed, state-of-the-art case studies on wireless applications, including popular linear convolution in digital front ends (DFEs); nonlinear...

  15. Architecture exploration of FPGA based accelerators for bioinformatics applications

    CERN Document Server

    Varma, B Sharat Chandra; Balakrishnan, M

    2016-01-01

    This book presents an evaluation methodology to design future FPGA fabrics incorporating hard embedded blocks (HEBs) to accelerate applications. This methodology will be useful for selection of blocks to be embedded into the fabric and for evaluating the performance gain that can be achieved by such an embedding. The authors illustrate the use of their methodology by studying the impact of HEBs on two important bioinformatics applications: protein docking and genome assembly. The book also explains how the respective HEBs are designed and how hardware implementation of the application is done using these HEBs. It shows that significant speedups can be achieved over pure software implementations by using such FPGA-based accelerators. The methodology presented in this book may also be used for designing HEBs for accelerating software implementations in other domains besides bioinformatics. This book will prove useful to students, researchers, and practicing engineers alike.

  16. Reduced Precision Redundancy for Satellite Telecommand Receiver Module on FPGA

    Directory of Open Access Journals (Sweden)

    Salman Sadruddin

    2013-01-01

    Full Text Available A novel and highly efficient design of a software defined radiation tolerant baseband module for a LEO satellite telecommand receiver using FPGA is presented. FPGAs in space are subject to single event upsets (SEUs due to high radiation environment. Traditionally, triple modular redundancy (TMR is used for mitigating Single Event Upsets (SEUs. The drawback of using TMR is that it consumes a lot of hardware resources and requires more power. Reduced precision redundancy (RPR can be a viable alternative of TMR in digital systems for arithmetic operations. This paper uses the combination of RPR and TMR for mitigating SEUs. The designed module consumes less resources on FPGA and has bit error rate (BER identical to theoretical results, apart from degradation due to implementation losses. An improved Costas loop and timing recovery algorithm are implemented for achieving carrier recovery and bit synchronization. The hybrid approach mitigates SEUs while consuming 26% less resources than a customary TMR protected receiver.

  17. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    Science.gov (United States)

    Liang, Yutie; Ye, Hua; Galuska, Martin J.; Gessler, Thomas; Kuhn, Wolfgang; Lange, Jens Soren; Wagner, Milan N.; Liu, Zhen'an; Zhao, Jingzhou

    2017-06-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  18. A fast and accurate FPGA based QRS detection system.

    Science.gov (United States)

    Shukla, Ashish; Macchiarulo, Luca

    2008-01-01

    An accurate Field Programmable Gate Array (FPGA) based ECG Analysis system is described in this paper. The design, based on a popular software based QRS detection algorithm, calculates the threshold value for the next peak detection cycle, from the median of eight previously detected peaks. The hardware design has accuracy in excess of 96% in detecting the beats correctly when tested with a subset of five 30 minute data records obtained from the MIT-BIH Arrhythmia database. The design, implemented using a proprietary design tool (System Generator), is an extension of our previous work and uses 76% resources available in a small-sized FPGA device (Xilinx Spartan xc3s500), has a higher detection accuracy as compared to our previous design and takes almost half the analysis time in comparison to software based approach.

  19. Colorimetric Sensor Arrays System Based on FPGA for Image Recognition

    Institute of Scientific and Technical Information of China (English)

    Rui Chen; Jian-Hua Xu; Ya-Dong Jiang

    2009-01-01

    A FPGA-based image recognition system is designed for colorimetric sensor array in order to recognize a wide range of volatile organic compounds. The gas molecule is detected by the responsive sensor array and the responsive image is obtained. The image is decomposed to RGB color components using CMOS image sensor. An embedded image recognition archi- tecture based on Xilinx Spartan-3 FPGA is designed to implement the algorithms of image recognition. The algorithm of color coherence vector is discussed in detail[X1] compared with the algorithm of color histograms, and experimental results demonstrate that both of the two algorithms could be analyzed effectively to represent different volatile organic compounds according to their different responsive images in this system.

  20. Linux embebido en FPGA para sistemas de monitoreo industrial

    Directory of Open Access Journals (Sweden)

    José F. Carmona Martínez

    2013-03-01

    Full Text Available Actualmente la obtención en FPGA (Field Programmable Gate Array de módulos independientes para aplicaciones específicas de monitoreo industrial, ha hecho que su reutilización e integración sea compleja y que los tiempos de desarrollo y puesta a punto de los mismos sean considerablemente elevados. En este trabajo se propone una solución a este problema basada en embeber Linux en un FPGA, específicamente utilizando el kit Spartan3AN. Las herramientas de codiseño hardware/software utilizadas para lograr este objetivo han permitido tener resultados a corto plazo, que indican el enfoque para futuras investigaciones. De manera que se logró ejecutar aplicaciones de uso general para el control de ip-cores empotrados en hardware reconfigurable. La plataforma obtenida es estable y flexible a futuras implementaciones tanto de software como de hardware.

  1. FPGA-based amplitude and phase detection in DLLRF

    Institute of Scientific and Technical Information of China (English)

    LIU Rong; WANG Zheng; PAN Wei-Min; WANG Guang-Wei; LIN Hai-Ying; SHA Peng; ZENG Ri-Hua

    2009-01-01

    The new generation particle accelerator requires a highly stable radio frequency (RF) system. The stability of the RF system is realized by the Low Level RF (LLRF) subsystem which controls the amplitude and phase of the RF signal. The detection of the RF signal's amplitude and phase is fundamental to LLRF controls. High-speed ADC (Analog to Digital Converter), DAC (Digital to Analog Converter) and FPGA (Field Programmable Gate Array) play very important roles in digital LLRF control systems. This paper describes the implementation of real-time amplitude and phase detection based of the FPGA with an analysis of the main factors that affect the detection accuracy such as jitter, algorithm's defects and non-linearity of devices, which is helpful for future work on high precision detection and control.

  2. A digital coincidence measurement system using FPGA techniques

    Energy Technology Data Exchange (ETDEWEB)

    Zhu Fengming; Hsieh, S.C.; Yen, W.W. [Department of Engineering and System Science, National Tsing Hua University, Hsinchu, 30043, Taiwan (China); Chou, H.P., E-mail: hpc@ess.nthu.edu.tw [Department of Engineering and System Science, National Tsing Hua University, Hsinchu, 30043, Taiwan (China)

    2011-10-01

    A field programmable gate array (FPGA) based digital coincidence system has been developed to use with NaI scintillators for field applications. The analog output signal from the photomultiplier anode is directly transferred into digital signals by pulse height for pulse width conversion. The digital signal contains the energy and timing information of the radiation events. The pulse width is then measured by a vernier type of time-to-digital converter (TDC). The timing information of radiation events is recorded and analyzed by a coincidence unit. Both the TDC unit and the coincidence unit are implemented using a commercial available FPGA board. The measured data is then sent to a personal computer for spectrum display. Efficiency as well as energy calibration has been performed. The system showed a timing resolution about 13 ns and an energy resolution of 12% for 0.511 MeV annihilation gammas; it also successfully demonstrated the background rejection ability through coincidence measurement.

  3. FPGA-based Controller for a Mobile Robot

    CERN Document Server

    Kale, Shilpa

    2009-01-01

    With application in the robotics and automation, more and more it becomes necessary the development of applications based on methodologies that facilitate future modifications, updates and enhancements in the original projected system. This project presents a conception of mobile robots using rapid prototyping, distributing the several control actions in growing levels of complexity and computing proposal oriented to embed systems implementation. This kind of controller can be tested on different platform representing the mobile robots using reprogrammable logic components (FPGA). This mobile robot will detect obstacle and also be able to control the speed. Different modules will be Actuators, Sensors, wireless transmission. All this modules will be interfaced using FPGA controller. I would like to construct a mechanically simple robot model, which can measure the distance from obstacle with the aid of sensor and accordingly should able to control the speed of motor. I would like to construct a mechanically s...

  4. Application of FPGA technology to performance limitations in radiation therapy

    Science.gov (United States)

    DeMarco, John J.; Smathers, J. B.; Solberg, Tim D.; Casselman, Steve

    1996-10-01

    The field programmable gate array (FPGA) is a promising technology for increasing computation performance by providing for the design of custom chips through programmable logic blocks. This technology was used to implement and test a hardware random number generator (RNG) versus four software algorithms. The custom hardware consists of a sun SBus-based board (EVC) which has been designed around a Xilinx FPGA. A timing analysis indicates the Sun/EVC hardware generator computes 1 multiplied by 106 random numbers approximately 50 times faster than the multiplicative congruential algorithm. The hardware and software RNGs were also compare using a Monte Carlo photon transport algorithm. For this comparison the Sun/EVC generator produces a performance increase of approximately 2.0 versus the software generators. This comparison is based upon 1 multiplied by 105 photon histories.

  5. New Techniques for Implementation of Hardware Algorithms inside FPGA Circuits

    Directory of Open Access Journals (Sweden)

    IOAN, A. D.

    2010-05-01

    Full Text Available This work presents a less known theoretical method for the synthesis of complex hardware automata by using the transition matrix, together with a new practical method for visual implementation inside FPGA circuits, with library schematic symbols from the "Altium Designer" software environment. Because these techniques need to be presented by example, the classical shift and add unsigned multiply algorithm was chosen for review. Obviously, this is not the most efficient algorithm, but it serves the declared purpose and it can still be used in a real system when the hardware must be minimal. Furthermore, an essential correction to the optimal version of this algorithm was made. The techniques are exemplified by doing an original implementation: starting from the initial organigram, passing through transition matrix synthesis stage and reaching to the final fully functional system on a "Digilent Spartan-3" FPGA development board, which includes the user interface too.

  6. OCTAD-S: digital fast Fourier transform spectrometers by FPGA

    Science.gov (United States)

    Iwai, Kazumasa; Kubo, Yûki; Ishibashi, Hiromitsu; Naoi, Takahiro; Harada, Kenichi; Ema, Kenji; Hayashi, Yoshinori; Chikahiro, Yuichi

    2017-07-01

    We have developed a digital fast Fourier transform spectrometer made of an analog-to-digital converter (ADC) and a field-programmable gate array (FPGA). The base instrument has independent ADC and FPGA modules, which allow us to implement different spectrometers in a relatively easy manner. Two types of spectrometers have been instrumented: one with 4.096 GS/s sampling speed and 2048 frequency channels and the other with 2.048 GS/s sampling speed and 32,768 frequency channels. The signal processing in these spectrometers has no dead time, and the accumulated spectra are recorded in external media every 8 ms. A direct sampling spectroscopy up to 8 GHz is achieved by a microwave track-and-hold circuit, which can reduce the analog receiver in front of the spectrometer. Highly stable spectroscopy with a wide dynamic range was demonstrated in a series of laboratory experiments and test observations of solar radio bursts.

  7. Intermediate Frequency Digital Receiver Based on Multi-FPGA System

    Directory of Open Access Journals (Sweden)

    Chengchang Zhang

    2016-01-01

    Full Text Available Aiming at high-cost, large-size, and inflexibility problems of traditional analog intermediate frequency receiver in the aerospace telemetry, tracking, and command (TTC system, we have proposed a new intermediate frequency (IF digital receiver based on Multi-FPGA system in this paper. Digital beam forming (DBF is realized by coordinated rotation digital computer (CORDIC algorithm. An experimental prototype has been developed on a compact Multi-FPGA system with three FPGAs to receive 16 channels of IF digital signals. Our experimental results show that our proposed scheme is able to provide a great convenience for the design of IF digital receiver, which offers a valuable reference for real-time, low power, high density, and small size receiver design.

  8. Flexible, fpga-based electronics for modular robots

    DEFF Research Database (Denmark)

    Brandt, David; Larsen, Jørgen Christian; Christensen, David Johan

    2008-01-01

    In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays (FPGAs). The immediate advantage of using FPGAs is that some of the module’s electronics can be moved into the FPGA, thereby the number of components can be reduced. In the case...... consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible and therefore may make them more suitable for real applications. AB - In this paper we introduce electronics for the ATRON self-reconfigurable robot based on field programmable gate arrays...... the electronics for specific tasks. The disadvantages of an FPGA-based design include the cost of FPGAs, the extra layer of complexity in programming, and a limited increase in power consumption compared to micro-controllers. However, overall FPGAs make the electronics of modular robots more flexible...

  9. FPGA Online Tracking Algorithm for the PANDA Straw Tube Tracker

    CERN Document Server

    Liang, Yutie; Galuska, Martin J; Gessler, Thomas; Kühn, Wolfgang; Lange, Jens Sören; Wagner, Milan N; Liu, Zhen'an; Zhao, Jingzhou

    2016-01-01

    A novel FPGA based online tracking algorithm for helix track reconstruction in a solenoidal field, developed for the PANDA spectrometer, is described. Employing the Straw Tube Tracker detector with 4636 straw tubes, the algorithm includes a complex track finder, and a track fitter. Implemented in VHDL, the algorithm is tested on a Xilinx Virtex-4 FX60 FPGA chip with different types of events, at different event rates. A processing time of 7 $\\mu$s per event for an average of 6 charged tracks is obtained. The momentum resolution is about 3\\% (4\\%) for $p_t$ ($p_z$) at 1 GeV/c. Comparing to the algorithm running on a CPU chip (single core Intel Xeon E5520 at 2.26 GHz), an improvement of 3 orders of magnitude in processing time is obtained. The algorithm can handle severe overlapping of events which are typical for interaction rates above 10 MHz.

  10. Introduction to FPGA Devices and The Challenges for Critical Application - A User's Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth

    2015-01-01

    This presentation is an introduction to Field Programmable Gate Array (FPGA) devices and the challenges of critical application including: safety, reliability, availability, recoverability, and security.

  11. New Developments in FPGA Devices: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie; LaBel, Kenneth; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  12. New Developments in FPGA: SEUs and Fail-Safe Strategies from the NASA Goddard Perspective

    Science.gov (United States)

    Berg, Melanie D.; Label, Kenneth A.; Pellish, Jonathan

    2016-01-01

    It has been shown that, when exposed to radiation environments, each Field Programmable Gate Array (FPGA) device has unique error signatures. Subsequently, fail-safe and mitigation strategies will differ per FPGA type. In this session several design approaches for safe systems will be presented. It will also explore the benefits and limitations of several mitigation techniques. The intention of the presentation is to provide information regarding FPGA types, their susceptibilities, and proven fail-safe strategies; so that users can select appropriate mitigation and perform the required trade for system insertion. The presentation will describe three types of FPGA devices and their susceptibilities in radiation environments.

  13. DAILY DYNAMICS OF THE ELEMENTS OF MULE DUCKS BEHAVIOR AT A DIFFERENT AGE, BRED IN INTEGRATED FISH PONDS UNDER DIFFERENT NUTRIENT REGIMES. II. AT APPLYING THE SCHEME OF FEEDING WITH PARTIAL RESTRICTION.

    Directory of Open Access Journals (Sweden)

    Lyudmila NIKOLOVA

    2010-12-01

    Full Text Available An investigation upon the daily dynamics of the separate elements of mule ducks behavior has been carried out at the Institute of Fisheries and Acuaculture Plovdiv, Bulgaria, applying the schedule of feeding with partial restriction, at conditions of integrated fish-ducks technology. Our investigation has shown that the fishponds have been suitable for mule ducks rearing – the birds have had a good plumage status without demonstrations of cannibalism and aggressiveness. Together with the fattening period advance, ducks have spent less time for feeding and have reacted rather weakly to forage supply; the dry land stay time has been on the account of the fish-pond stay, having in mind that the swimming time has increased, as well as the rest time in the fish-pond together with the advance in age.

  14. FPGA applications for single dish activity at Medicina radio telescopes

    Science.gov (United States)

    Bartolin, M.; Nald, G.; Mattan, A.; Maccaferr, A.; De Biagg, M.

    FPGA technologies are gaining major attention in the recent years in the field of radio astronomy. At Medicina radio telescopes, FPGAs have been used in the last ten years for a number of purposes and in this article we will take into exam the applications developed and installed for the Medicina Single Dish 32m Antenna: these range from high performance digital signal processing to instrument control developed on top of smaller FPGAs.

  15. DNA Assembly with De Bruijn Graphs Using an FPGA Platform.

    Science.gov (United States)

    Poirier, Carl; Gosselin, Benoit; Fortier, Paul

    2017-04-24

    This paper presents an FPGA implementation of a DNA assembly algorithm, called Ray, initially developed to run on parallel CPUs. The OpenCL language is used and the focus is placed on modifying and optimizing the original algorithm to better suit the new parallelization tool and the radically different hardware architecture. The results show that the execution time is roughly one fourth that of the CPU and factoring energy consumption yields a tenfold savings.

  16. FPGA-oriented synthesis of multivalued logical networks

    Science.gov (United States)

    Deniziak, S.; Wiśniewski, M.; Kurczyna, K.

    2016-12-01

    Multivalued logical network consists of modules connected by multivalued signals. During synthesis each module is decomposed into smaller ones using the symbolic decomposition. Since the efficiency of the decomposition strongly depends on encoding of multivalued signals, the result of synthesis depends on the order, in which the consecutive modules are implemented. This paper presents the method of FPGA-oriented synthesis of multivalued logical networks. Experimental results showed that our approach significantly reduces the cost of implementation.

  17. Reconfiguring an FPGA-based RISC for LNS arithmetic

    Science.gov (United States)

    Arnold, Mark G.; Winkel, Mark D.

    2001-07-01

    Field Programmable Gate Arrays (FPGAs) have some difficulty with the implementation of floating-point operations. In particular, devoting the large number of slices needed by floating-point multipliers prohibits incorporating floating point into smaller, less expensive FPGAs. An alternative is the Logarithmic Number System (LNS), where multiplication and division are easy and fast. LNS also has the advantage of lower power consumption than fixed point. The problem with LNS has been the implementation of addition. There are many price/performance tradeoffs in the LNS design space between pure software and specialised-high-speed hardware. This paper focuses on a compromise between these extremes. We report on a small RISC core of our own design (loosely inspired by the popular ARM processor) in which only 4 percent additional investment in FPGA resources beyond that required for the integer RISC core more than doubles the speed of LNS addition compared to a pure software approach. Our approach shares resources in the datapath of the non-LNS parts of the RISC so that the only significant cost is the decoding and control for the LNS instruction. Since adoption of LNS depends on its cost effectiveness (e.g., FLOPs/slice), we compare our design against an earlier LNS ALU implemented in a similar FPGA. Our preliminary experiments suggest modest LNS-FPGA implementations, like ours, are more cost effective than pure software and can be as cost effective as more expensive LNS-FPGA implementations that attempt to maximise speed. Thus, our LNS-RISC fits in the Virtex-300, which is not possible for a comparable design.

  18. Teaching Computer Organization and Architecture Using Simulation and FPGA Applications

    OpenAIRE

    2007-01-01

    This paper presents the design concepts and realization of incorporating micro-operation simulation and FPGA implementation into a teaching tool for computer organization and architecture. This teaching tool helps computer engineering and computer science students to be familiarized practically with computer organization and architecture through the development of their own instruction set, computer programming and interfacing experiments. A two-pass assembler has been designed and implemente...

  19. FPGA-based adaptive backstepping fuzzy control for a micro-positioning Scott-Russell mechanism

    Science.gov (United States)

    Fung, Rong-Fong; Weng, Ming-Hong; Kung, Ying-Shieh

    2009-11-01

    This paper utilizes the field programmable gate array (FPGA) and Nios II embedded processor technologies to design a controller IC for a micro-positioning Scott-Russell (SR) mechanism, which is driven by a piezoelectric actuator (PA) and its hysteresis phenomenon is described by Bouc-Wen hysteresis model. For the controller design, the adaptive backstepping fuzzy control (ABFC) method is developed to compensate the PA's hysteresis and achieve the motion tracking control. The fuzzy logic method (FLM) is utilized to find the best adaptation gain of the adaptation law and control gain of the stabilization controls. This ABFC controller method can improve the transient and asymptotic tracking performances, and make the SR mechanism keep good working performance when external disturbances is added in the control system. Finally, we successfully apply the system-on-a-programmable-chip (SoPC) technologies to develop the motion controller IC, and achieve the advantages of reduced space, high performance and low cost.

  20. An FPGA Implementation of (3,6-Regular Low-Density Parity-Check Code Decoder

    Directory of Open Access Journals (Sweden)

    Tong Zhang

    2003-05-01

    Full Text Available Because of their excellent error-correcting performance, low-density parity-check (LDPC codes have recently attracted a lot of attention. In this paper, we are interested in the practical LDPC code decoder hardware implementations. The direct fully parallel decoder implementation usually incurs too high hardware complexity for many real applications, thus partly parallel decoder design approaches that can achieve appropriate trade-offs between hardware complexity and decoding throughput are highly desirable. Applying a joint code and decoder design methodology, we develop a high-speed (3,k-regular LDPC code partly parallel decoder architecture based on which we implement a 9216-bit, rate-1/2(3,6-regular LDPC code decoder on Xilinx FPGA device. This partly parallel decoder supports a maximum symbol throughput of 54 Mbps and achieves BER 10−6 at 2 dB over AWGN channel while performing maximum 18 decoding iterations.

  1. Round-Off Noise of Multiplicative FIR Filters Implemented on an FPGA Platform

    Directory of Open Access Journals (Sweden)

    Jean-Jacques Vandenbussche

    2014-03-01

    Full Text Available The paper analyzes the effects of round-off noise on Multiplicative Finite Impulse Response (MFIR filters used to approximate the behavior of pole filters. General expressions to calculate the signal to round-off noise ratio of a cascade structure of Finite Impulse Response (FIR filters are obtained and applied on the special case of MFIR filters. The analysis is based on fixed-point implementations, which are most common in digital signal processing algorithms implemented in Field-Programmable Gate-Array (FPGA technology. Three well known scaling methods, i.e., L2 bound; infinity bound and absolute bound scaling are considered and compared. The paper shows that the ordering of the MFIR stages, in combination with the scaling methods, have an important impact on the round-off noise. An optimal ordering of the stages for a chosen scaling method can improve the round-off noise performance by 20 dB.

  2. Design and Implementation of a FPGA and DSP Based MIMO Radar Imaging System

    Directory of Open Access Journals (Sweden)

    Wei Wang

    2015-06-01

    Full Text Available The work presented in this paper is aimed at the implementation of a real-time multiple-input multiple-output (MIMO imaging radar used for area surveillance. In this radar, the equivalent virtual array method and time-division technique are applied to make 16 virtual elements synthesized from the MIMO antenna array. The chirp signal generater is based on a combination of direct digital synthesizer (DDS and phase locked loop (PLL. A signal conditioning circuit is used to deal with the coupling effect within the array. The signal processing platform is based on an efficient field programmable gates array (FPGA and digital signal processor (DSP pipeline where a robust beamforming imaging algorithm is running on. The radar system was evaluated through a real field experiment. Imaging capability and real-time performance shown in the results demonstrate the practical feasibility of the implementation.

  3. Neural harmonic detection approaches for FPGA area efficient implementation

    Science.gov (United States)

    Dzondé, S. R. N.; Kom, C.-H.; Berviller, H.; Blondé, J.-P.; Flieller, D.; Kom, M.; Braun, F.

    2011-12-01

    This paper deals with new neural networks based harmonics detection approaches to minimize hardware resources needed for FPGA implementation. A simple type of neural network called Adaline is used to build an intelligent Active Power Filter control unit for harmonics current elimination and reactive power compensation. For this purpose, two different approaches called Improved Three-Monophase (ITM) and Two-Phase Flow (TPF) methods are proposed. The ITM method corresponds to a simplified structure of the three-monophase method whereas the TPF method derives from the Synchronous Reference Frame method. Indeed, for both proposed methods, only 50% of Adalines with regard to the original methods is used. The corresponding designs were implemented on a FPGA Stratix II platform through Altera DSP Builder® development tool. After analyzing those two methods with respect to performance and size criteria, a comparative study with the popular p-q and also the direct method is reported. From there, one can notice that the p-q is still the most powerful method for three-phase compensation but the TPF method is the fastest and the most compact in terms of size. An experimental result is shown to validate the feasibility of FPGA implementation of ANN-based harmonics extraction algorithms.

  4. FPGA Based Quadruple Precision Floating Point Arithmetic for Scientific Computations

    Directory of Open Access Journals (Sweden)

    Mamidi Nagaraju

    2012-09-01

    Full Text Available In this project we explore the capability and flexibility of FPGA solutions in a sense to accelerate scientific computing applications which require very high precision arithmetic, based on IEEE 754 standard 128-bit floating-point number representations. Field Programmable Gate Arrays (FPGA is increasingly being used to design high end computationally intense microprocessors capable of handling floating point mathematical operations. Quadruple Precision Floating-Point Arithmetic is important in computational fluid dynamics and physical modelling, which require accurate numerical computations. However, modern computers perform binary arithmetic, which has flaws in representing and rounding the numbers. As the demand for quadruple precision floating point arithmetic is predicted to grow, the IEEE 754 Standard for Floating-Point Arithmetic includes specifications for quadruple precision floating point arithmetic. We implement quadruple precision floating point arithmetic unit for all the common operations, i.e. addition, subtraction, multiplication and division. While previous work has considered circuits for low precision floating-point formats, we consider the implementation of 128-bit quadruple precision circuits. The project will provide arithmetic operation, simulation result, hardware design, Input via PS/2 Keyboard interface and results displayed on LCD using Xilinx virtex5 (XC5VLX110TFF1136 FPGA device.

  5. Design of transient light signal simulator based on FPGA

    Science.gov (United States)

    Kang, Jing; Chen, Rong-li; Wang, Hong

    2014-11-01

    A design scheme of transient light signal simulator based on Field Programmable gate Array (FPGA) was proposed in this paper. Based on the characteristics of transient light signals and measured feature points of optical intensity signals, a fitted curve was created in MATLAB. And then the wave data was stored in a programmed memory chip AT29C1024 by using SUPERPRO programmer. The control logic was realized inside one EP3C16 FPGA chip. Data readout, data stream cache and a constant current buck regulator for powering high-brightness LEDs were all controlled by FPGA. A 12-Bit multiplying CMOS digital-to-analog converter (DAC) DAC7545 and an amplifier OPA277 were used to convert digital signals to voltage signals. A voltage-controlled current source constituted by a NPN transistor and an operational amplifier controlled LED array diming to achieve simulation of transient light signal. LM3405A, 1A Constant Current Buck Regulator for Powering LEDs, was used to simulate strong background signal in space. Experimental results showed that the scheme as a transient light signal simulator can satisfy the requests of the design stably.

  6. An FPGA implementation to detect selective cationic antibacterial peptides.

    Science.gov (United States)

    Polanco González, Carlos; Nuño Maganda, Marco Aurelio; Arias-Estrada, Miguel; del Rio, Gabriel

    2011-01-01

    Exhaustive prediction of physicochemical properties of peptide sequences is used in different areas of biological research. One example is the identification of selective cationic antibacterial peptides (SCAPs), which may be used in the treatment of different diseases. Due to the discrete nature of peptide sequences, the physicochemical properties calculation is considered a high-performance computing problem. A competitive solution for this class of problems is to embed algorithms into dedicated hardware. In the present work we present the adaptation, design and implementation of an algorithm for SCAPs prediction into a Field Programmable Gate Array (FPGA) platform. Four physicochemical properties codes useful in the identification of peptide sequences with potential selective antibacterial activity were implemented into an FPGA board. The speed-up gained in a single-copy implementation was up to 108 times compared with a single Intel processor cycle for cycle. The inherent scalability of our design allows for replication of this code into multiple FPGA cards and consequently improvements in speed are possible. Our results show the first embedded SCAPs prediction solution described and constitutes the grounds to efficiently perform the exhaustive analysis of the sequence-physicochemical properties relationship of peptides.

  7. The current state of FPGA technology in the nuclear domain

    Energy Technology Data Exchange (ETDEWEB)

    Ranta, J.

    2012-07-01

    Field programmable gate arrays are a form of programmable electronic device used in various applications including automation systems. In recent years, there has been a growing interest in the use of FPGA-based systems also for safety automation of nuclear power plants. The interest is driven by the need for reliable new alternatives to replace, on one hand, the aging technology currently in use and, on the other hand, microprocessor and software-based systems, which are seen as overly complex from the safety evaluation point of view. This report presents an overview of FPGA technology, including hardware aspects, the application development process, risks and advantages of the technology, and introduces some of the current systems. FPGAs contain an interesting combination of features from software-based and fully hardware-based systems. Application development has a great deal in common with software development, but the final product is a hardware component without the operating system and other platform functions on which software would execute. Currently the number of FPGA-based applications used for safety functions of nuclear power plants is rather limited, but it is growing. So far there is little experience or common solid understanding between different parties on how FPGAs should be evaluated and handled in the licensing process. (orig.)

  8. Estimation of channel impulse response and FPGA simulation

    Directory of Open Access Journals (Sweden)

    YU Longjie

    2015-02-01

    Full Text Available Wideband code division multiple access (WCDMA is a 3G wireless communication network.The common pilot channel in downlink of WCDMA provides an effective method to estimate the channel impulse response.In this paper,universal software radio peripheral (USRP is utilized to sample and process WCDMA signal which is emitted by China Unicom base station.Firstly,the received signal is pre-processed with filtering and down-sampling.Secondly,fast algorithm of WCDMA cell search is fulfilled.Thirdly,frequency shift caused by USRP′s crystal oscillator is checked and compensated.Eventually,channel impulse response is estimated.In this paper,MATLAB is used to describe the above algorithm and field programmable gate array (FPGA is used to simulate algorithm.In the process of simulation,pipeline and IP core multiplexing are introduced.In the case of 32 MHz clock frequency,FPGA simulation time is 80.861 ms.Simulation results show that FPGA is able to estimate the channel impulse response quickly and accurately with less hardware resources.

  9. 航空高度 FPGA 单粒子翻转飞行实验及失效分析%Flight experiments and failure analysis of FPGA for anti-SEU at aviation altitudes

    Institute of Scientific and Technical Information of China (English)

    薛茜男; 张道阳; 李颖; 芦浩; 王鹏

    2016-01-01

    随着微电子工艺的发展,小尺寸、高密度及低电压的器件越来越多地应用于航空电子设备。许多科研人员发现高层大气及外太空的带电粒子带来的粒子辐射会对航空电子器件产生严重的影响。基于民用航空局方的要求,鉴于机载设备对单粒子翻转效应的隐患以及航空机载设备国产化的迫切需求,开展 FPGA器件用于机载电子设备可能遭遇的单粒子翻转效应的风险问题研究。分析了主流 FPGA 在航空飞行高度的飞行实验数据,进一步论证其是否满足民用航空的需求。大量数据的分析结果证明,以当下主流 FPGA 芯片的工艺尺寸、工作电压的条件,单粒子翻转效应是一个不容忽视的问题。即便是航空飞行高度甚至是地面高度,FPGA 芯片因单粒子翻转导致失效也是无法满足民用航空设备的安全性要求。%With the development of microelectronics technology,small size,high integration density and low voltage devices are increasingly used in avionics.Many researchers found that the particle radiation caused by the charged particles in upper at-mosphere have a significant impact on avionic devices.In consideration of the potential safety hazard by single event upsets and the urgent demand of airborne equipment localization,this paper reports the research and analysis of the single event upset problems of FPGA devices applied in the airborne electronic equipment.Firstly,the flight experimental data of mainstream FPGAs at the a-viation flight altitudes are analyzed.Then,further demonstration is made about whether these FPGA devices meet the needs of civil aviation.The analysis results show that single event upset is an indispensable problem according to the conditions of main-stream FPGA chip with the small size and working voltage.Even the FPGA devices are working at the air flight altitude or near the ground,the failure caused by single event upset would make them unable to meet

  10. A FPGA-Based Integrated Controller for Liquid Crystal Display%基于FPGA的液晶控制器设计

    Institute of Scientific and Technical Information of China (English)

    汪金辉; 张健; 宫娜; 吴武臣; 董利民

    2008-01-01

    介绍了一种基于 FPGA 的集成液晶控制器.系统由显示模块和控制模块组成,显示模块(LEM101)为10 bit 多功能通用型器件,内含看门狗(WDT)/时钟发生器,2 种频率的蜂鸣驱动电路,内置显示RAM,及3-4线串行接口.控制器基于1.5万门 FPGA 芯片(Xilinx XC3S1500),易于扩展和升级.利用 Verilog 语言,在 FPGA 芯片中实现了控制模块的设计,通过 GR-XC3S-1500 开发板验证,本设计完全满足对液晶模块的控制要求,并成功应用于光栅测量显示控制系统中.控制模块由四部分组成:存储、译码、串并转换器、输出控制.文章讨论了设计方法和设计过程,给出了部分 Verilog 代码.此外,本设计还创造性地在电源和 FPGA 芯片间插入低成本元件,满足了液晶上电后,初始化命令的延迟要求,从而节约了 FPGA 的硬件资源.%This paper presents a FPGA-based integrated controller for liquid crystal display system. The system consists of a display module and a controlling module. The former (LCM101 chip) is 10 bit multi-functional device with a WDT(watch dog timer), a dual frequency driving circuit, a display RAM and seri-al interface. The later is an integrated display controller using a FPGA chip of 1. 5million gate (Xilinx XC3S1500), so being easy to extend and upgrade. Integrated controller design in FPGA chip has been im-plemented by using Verilog language coding and verified in Xilinx Development Board. The design fits the requirements to control liquid crystal display entirely, and is successfully applied in a grating measurement system. The controller module includes four parts: storage, decoding, serial-parallel interface translation,and output controlling. This paper discusses the design method and the design process of each part above,providing Verilog codes partly. What's more a low-cost accessory is originally located between FPGA chip and power supply in hardware design to satisfy delay after liquid crystal electrify

  11. Assessment of Proper Bonding Methods and Mechanical Characterization FPGA CQFPs

    Science.gov (United States)

    Davis, Milton C.

    2008-01-01

    This presentation discusses fractured leads on field-programmable gate array (FPGA) during flight vibration. Actions taken to determine root cause and resolution of the failure include finite element analysis (FEA) and vibration testing and scanning electron microscopy (with X-ray microanalysis) and energy dispersive spectrometry (SEM/EDS) failure assessment. Bonding methods for surface mount parts is assessed, including critical analysis and assessment of random fatigue damage. Regarding ceramic quad flat pack (CQFP) lead fracture, after disassembling the attitude control electronics (ACE) configuration, photographs showed six leads cracked on FPGA RTSX72SU-1 CQ208B package located on the RWIC card. An identical package (FPGA RTSX32SU-1 CQ208B) mounted on the RWIC did not results in cracked pins due to vibration. FPGA lead failure theories include workmanship issues in the lead-forming, material defect in the leads of the FPGA packages, and the insecure mounting of the board in the card guides, among other theories. Studies were conducted using simple calculations to determine the response and fatigue life of the package. Shorter packages exhibited more response when loaded by out-of-plane displacement of PCB while taller packages exhibit more response when loaded by in-plane acceleration of PCB. Additionally, under-fill did not contribute to reducing stress in leads due to out-of-plane PCB loading or from component twisting, as much as corner bonding. The combination of corner bond and under-fill is best to address mechanical and thermal S/C environment. Test results of bonded parts showed reduced (dampened) amplitude and slightly shifted peaks at the un-bonded natural frequency and an additional response at the bonded frequency. Stress due to PCBB out-of-plane loading was decreased on in the corners when only a corner bond was used. Future work may address CQFP fatigue assessment, including the investigation of discrepancy in predicted fatigue damage, as well as

  12. SAD5 Stereo Correlation Line-Striping in an FPGA

    Science.gov (United States)

    Villalpando, Carlos Y.; Morfopoulos, Arin C.

    2011-01-01

    High precision SAD5 stereo computations can be performed in an FPGA (field-programmable gate array) at much higher speeds than possible in a conventional CPU (central processing unit), but this uses large amounts of FPGA resources that scale with image size. Of the two key resources in an FPGA, Slices and BRAM (block RAM), Slices scale linearly in the new algorithm with image size, and BRAM scales quadratically with image size. An approach was developed to trade latency for BRAM by sub-windowing the image vertically into overlapping strips and stitching the outputs together to create a single continuous disparity output. In stereo, the general rule of thumb is that the disparity search range must be 1/10 the image size. In the new algorithm, BRAM usage scales linearly with disparity search range and scales again linearly with line width. So a doubling of image size, say from 640 to 1,280, would in the previous design be an effective 4 of BRAM usage: 2 for line width, 2 again for disparity search range. The minimum strip size is twice the search range, and will produce an output strip width equal to the disparity search range. So assuming a disparity search range of 1/10 image width, 10 sequential runs of the minimum strip size would produce a full output image. This approach allowed the innovators to fit 1280 960 wide SAD5 stereo disparity in less than 80 BRAM, 52k Slices on a Virtex 5LX330T, 25% and 24% of resources, respectively. Using a 100-MHz clock, this build would perform stereo at 39 Hz. Of particular interest to JPL is that there is a flight qualified version of the Virtex 5: this could produce stereo results even for very large image sizes at 3 orders of magnitude faster than could be computed on the PowerPC 750 flight computer. The work covered in the report allows the stereo algorithm to run on much larger images than before, and using much less BRAM. This opens up choices for a smaller flight FPGA (which saves power and space), or for other algorithms

  13. Diseño e implementación con FPGA de un demodulador para comunicaciones digitales

    OpenAIRE

    Guerrero Balmori, Juan Antonio

    2006-01-01

    Haciendo uso de un kit de desarrollo de FPGA's de Xilinx se deberá programar una FPGA para implementar un demodulador digital que formará parte de un sistema linealizador de amplificadores de radiofrecuencia.

  14. Diseño e implementación con FPGA de un demodulador para comunicaciones digitales

    OpenAIRE

    Guerrero Balmori, Juan Antonio

    2006-01-01

    Haciendo uso de un kit de desarrollo de FPGA's de Xilinx se deberá programar una FPGA para implementar un demodulador digital que formará parte de un sistema linealizador de amplificadores de radiofrecuencia.

  15. Partially Hidden Markov Models

    DEFF Research Database (Denmark)

    Forchhammer, Søren Otto; Rissanen, Jorma

    1996-01-01

    Partially Hidden Markov Models (PHMM) are introduced. They differ from the ordinary HMM's in that both the transition probabilities of the hidden states and the output probabilities are conditioned on past observations. As an illustration they are applied to black and white image compression wher...

  16. A Floating Point Multiplier based FPGA Synthesis for Neural Networks Enhancement

    Directory of Open Access Journals (Sweden)

    F. BENREKIA,

    2010-05-01

    Full Text Available FPGA (Field Programmable Gate Array implementation of Artificial Neural Networks (ANNs calls for multipliers of various word lengths. In this paper, a new approach for designing a FloatingPoint Multiplier(FPM is developed and tested using VHDL. With VHDL (Very High Description Language analyzer and logic synthesis software, hardware prototypes could be implemented in FPGA.

  17. An Update on ConSys Including a New LabVIEW FPGA Based LLRF System

    DEFF Research Database (Denmark)

    Worm, Torben; Nielsen, Jørgen S.

    . This system use a National Instruments NI-PCIe7852R DAQ card, which includes an on-board FPGA and are hosted in a standard PC. The fast (50 kHz) amplitude loop has been implemented on the FPGA, whereas the slower tuning and phase loops are implemented in the real-time system. An operator interface including...

  18. Analysis of Thermal Stability of Different Counter on 28nm FPGA

    DEFF Research Database (Denmark)

    Gupta, Daizy; Yadav, Amit; Hussain, Dil muhammed Akbar

    2016-01-01

    In this paper we are presenting the power analysis for thermal awareness of different counters. The technique we are using to do the analysis is based on 28 nm FPGA tech-nique. In this work during implementation on FPGA, we are going to analyze thermal stability of different counters in temperature...

  19. Analysis of Thermal Stability of Different Counter on 28nm FPGA

    DEFF Research Database (Denmark)

    Gupta, Daizy; Yadav, Amit; Hussain, Dil muhammed Akbar

    2016-01-01

    In this paper we are presenting the power analysis for thermal awareness of different counters. The technique we are using to do the analysis is based on 28 nm FPGA tech-nique. In this work during implementation on FPGA, we are going to analyze thermal stability of different counters in temperature...

  20. FPGA-based Signal Processor for Detection and Interpretationof Pulsed Laser Radiation

    Directory of Open Access Journals (Sweden)

    A. K. Maini

    2007-07-01

    Full Text Available A novel design technique for detection and interpretation of pulsed laser radiationimplemented on Xilinx Spartan-III field programmable gate arrays (FPGA is presented. The designarchitecture is modular with high performance and unparalleled flexibility that simplifies designchanges. The design gives superior accuracy and scalability and is applicable to a range ofFPGA technologies.

  1. FPGA-accelerated simulation of computer systems

    CERN Document Server

    Angepat, Hari; Chung, Eric S; Hoe, James C; Chung, Eric S

    2014-01-01

    To date, the most common form of simulators of computer systems are software-based running on standard computers. One promising approach to improve simulation performance is to apply hardware, specifically reconfigurable hardware in the form of field programmable gate arrays (FPGAs). This manuscript describes various approaches of using FPGAs to accelerate software-implemented simulation of computer systems and selected simulators that incorporate those techniques. More precisely, we describe a simulation architecture taxonomy that incorporates a simulation architecture specifically designed f

  2. Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator

    Science.gov (United States)

    Asaad, Sameth W.; Kapur, Mohit

    2016-01-05

    A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.

  3. FHAST: FPGA-Based Acceleration of Bowtie in Hardware.

    Science.gov (United States)

    Fernandez, Edward B; Villarreal, Jason; Lonardi, Stefano; Najjar, Walid A

    2015-01-01

    While the sequencing capability of modern instruments continues to increase exponentially, the computational problem of mapping short sequenced reads to a reference genome still constitutes a bottleneck in the analysis pipeline. A variety of mapping tools (e.g., Bowtie, BWA) is available for general-purpose computer architectures. These tools can take many hours or even days to deliver mapping results, depending on the number of input reads, the size of the reference genome and the number of allowed mismatches or insertion/deletions, making the mapping problem an ideal candidate for hardware acceleration. In this paper, we present FHAST (FPGA hardware accelerated sequence-matching tool), a drop-in replacement for Bowtie that uses a hardware design based on field programmable gate arrays (FPGA). Our architecture masks memory latency by executing multiple concurrent hardware threads accessing memory simultaneously. FHAST is composed by multiple parallel engines to exploit the parallelism available to us on an FPGA. We have implemented and tested FHAST on the Convey HC-1 and later ported on the Convey HC-2ex, taking advantage of the large memory bandwidth available to these systems and the shared memory image between hardware and software. A preliminary version of FHAST running on the Convey HC-1 achieved up to 70x speedup compared to Bowtie (single-threaded). An improved version of FHAST running on the Convey HC-2ex FPGAs achieved up to 12x fold speed gain compared to Bowtie running eight threads on an eight-core conventional architecture, while maintaining almost identical mapping accuracy. FHAST is a drop-in replacement for Bowtie, so it can be incorporated in any analysis pipeline that uses Bowtie (e.g., TopHat).

  4. Real-time windowing in imaging radar using FPGA technique

    Science.gov (United States)

    Ponomaryov, Volodymyr I.; Escamilla-Hernandez, Enrique

    2005-02-01

    The imaging radar uses the high frequency electromagnetic waves reflected from different objects for estimating of its parameters. Pulse compression is a standard signal processing technique used to minimize the peak transmission power and to maximize SNR, and to get a better resolution. Usually the pulse compression can be achieved using a matched filter. The level of the side-lobes in the imaging radar can be reduced using the special weighting function processing. There are very known different weighting functions: Hamming, Hanning, Blackman, Chebyshev, Blackman-Harris, Kaiser-Bessel, etc., widely used in the signal processing applications. Field Programmable Gate Arrays (FPGAs) offers great benefits like instantaneous implementation, dynamic reconfiguration, design, and field programmability. This reconfiguration makes FPGAs a better solution over custom-made integrated circuits. This work aims at demonstrating a reasonably flexible implementation of FM-linear signal and pulse compression using Matlab, Simulink, and System Generator. Employing FPGA and mentioned software we have proposed the pulse compression design on FPGA using classical and novel windows technique to reduce the side-lobes level. This permits increasing the detection ability of the small or nearly placed targets in imaging radar. The advantage of FPGA that can do parallelism in real time processing permits to realize the proposed algorithms. The paper also presents the experimental results of proposed windowing procedure in the marine radar with such the parameters: signal is linear FM (Chirp); frequency deviation DF is 9.375MHz; the pulse width T is 3.2μs taps number in the matched filter is 800 taps; sampling frequency 253.125*106 MHz. It has been realized the reducing of side-lobes levels in real time permitting better resolution of the small targets.

  5. Design and implementation of Kalman filter based on FPGA%基于FPGA的Kalman滤波器实现研究

    Institute of Scientific and Technical Information of China (English)

    赵大建; 赵伟; 张兆亮; 宋国安; 刘建业

    2012-01-01

    卡尔曼(Kalman)滤波计算精度和速度是工程应用中是否成功的决定性条件,为进一步提高Kalman滤波算法在更复杂的环境下使用的性能,并能够同时满足实时性和精度的要求,采用现场可编程逻辑阵列(FPGA)技术,设计了Kalman滤波算法在FPGA上的实现方案,选择了一种可以同时满足精度和实时性的方案进行实现,对算法中的矩阵相乘、状态机的应用以及资源分时复用等关键技术进行了设计.通过与Matlab及DSP的计算结果相对比,验证了在FPGA内实现Kalman滤波器的优势.%The calculation precision and speed of Kalman filtering are the key factors in application. Aiming to improve the performance of Kalman filtering algorithm applied to a more complex condition and meet the requirements of high accuracy and real-time performance, a scheme for implementing the Kalman filtering algorithm was designed with FPGA technology. Some key techniques such as the multiplication of matrixes, the application of finite state machine and the same source usage at different time were designed. The superiority of implementing the Kalman filter in FPGA was validated by comparing the verified results of Kalman filter implemented in FPGA with the calculated results of Matlab and DSP respectively.

  6. FPGA Based Low Power ROM Design Using Capacitance Scaling

    DEFF Research Database (Denmark)

    Bansal, Meenakshi; Bansal, Neha; Saini, Rishita

    2015-01-01

    An ideal capacitor will not dissipate any power, but a real capacitor wil l have some power dissipation. In this work, we are going to design capacitance scaling based low power ROM design. In order to test the compatibility of this ROM design with latest i7 Processor, we are operating this ROM w...... in I/O Power, saving of 0.2% occur in Leakage Power, there will be a saving of 11.54% occur in Total Power. This design is implemented on Virtex-5 FPGA using Xilinx ISE and Verilog....

  7. Enhanced Temperature Control Method Using ANFIS with FPGA

    Directory of Open Access Journals (Sweden)

    Chiung-Wei Huang

    2014-01-01

    Full Text Available Temperature control in etching process is important for semiconductor manufacturing technology. However, pressure variations in vacuum chamber results in a change in temperature, worsening the accuracy of the temperature of the wafer and the speed and quality of the etching process. This work develops an adaptive network-based fuzzy inference system (ANFIS using a field-programmable gate array (FPGA to improve the effectiveness. The proposed method adjusts every membership function to keep the temperature in the chamber stable. The improvement of the proposed algorithm is confirmed using a medium vacuum (MV inductively-coupled plasma- (ICP- type etcher.

  8. The FPGA based L1 track finding Tracklet approach

    Science.gov (United States)

    Kyriacou, Savvas; CMS Collaboration

    2017-01-01

    The High Luminosity upgraded LHC is expected to deliver proton-proton collisions per 25ns with an estimated 140-200 pile up interactions per bunch crossing. Ultrafast track finding is vital for handling trigger rates in such conditions. An FPGA based road search algorithm is developed, the Tracklet approach one of a few currently under consideration, for the CMS L1 trigger system. Based on low/high transverse momentum track discrimination and designed for the HL upgraded outer tracker, the algorithm achieves microsecond scale track reconstruction in the expected high track multiplicity environment. The Tracklet method overview, implementation, hardware demonstrator and performance results are presented and discussed.

  9. FPGA Implementation of Video Transmission System Based on LTE

    Directory of Open Access Journals (Sweden)

    Lu Yan

    2015-01-01

    Full Text Available In order to support high-definition video transmission, an implementation of video transmission system based on Long Term Evolution is designed. This system is developed on Xilinx Virtex-6 FPGA ML605 Evaluation Board. The paper elaborates the features of baseband link designed in Xilinx ISE and protocol stack designed in Xilinx SDK, and introduces the process of setting up hardware and software platform in Xilinx XPS. According to test, this system consumes less hardware resource and is able to transmit bidirectional video clearly and stably.

  10. FPGA Implementation of Decimal Processors for Hardware Acceleration

    DEFF Research Database (Denmark)

    Borup, Nicolas; Dindorp, Jonas; Nannarelli, Alberto

    2011-01-01

    Applications in non-conventional number systems can benefit from accelerators implemented on reconfigurable platforms, such as Field Programmable Gate-Arrays (FPGAs). In this paper, we show that applications requiring decimal operations, such as the ones necessary in accounting or financial...... transactions, can be accelerated by Application Specific Processors (ASPs) implemented on FPGAs. For the case of a telephone billing application, we demonstrate that by accelerating the program execution on a FPGA board connected to the computer by a standard bus, we obtain a significant speed-up over its...

  11. FPGA Implementation of Adaptive Filter and its Performance Analysis

    Directory of Open Access Journals (Sweden)

    J. Malarmannan

    2013-06-01

    Full Text Available Adaptive filters are used in various real-time applications such as echo cancellation, noise cancellation, system identification and prediction. Field -programmable gate arrays (FPGAs are alsoused most widely for applications where timing requirements are strict. Thus implementation of filter in real-time is needed. The objective of this paper is to design and implement an Adaptive filter which is robust to impulsive noise using hardware description language (HDL design. The design implementation and its performance analysis are presented. The targeted FPGA is Altera CycloneIV. The obtained design results in superior performance, greater data sample frequency and less logic occupation.

  12. FPGA-Based Efficient Programmable Polyphase FIR Filter

    Institute of Scientific and Technical Information of China (English)

    CHEN He; XIONG Cheng-huan; ZHONG Shu-nan; WANG Hua

    2005-01-01

    The modelling, design and implementation of a high-speed programmable polyphase finite impulse response (FIR) filter with field programmable gate array (FPGA) technology are described. This FIR filter can run automatically according to the programmable configuration word including symmetry/asymmetry, odd/even taps, from 32 taps up to 256 taps. The filter with 12 bit signal and 12 bit coefficient word-length has been realized on a Xilinx VirtexⅡ-v1500 device and operates at the maximum sampling frequency of 160 MHz.

  13. FPGA based data acquisition system for COMPASS experiment

    CERN Document Server

    Bodlak, M; Jary, V; Huber, S; Konorov, I; Levit, D; Novy, J; Paul, S; Salac, R; Virius, M

    2014-01-01

    This paper discusses the present data acquisition system (DAQ) of the COMPASS experiment at CERN and presents development of a new DAQ. The new DAQ must preserve present data format and be able to communicate with FPGA cards. Parts of the new DAQ are based on state machines and they are implemented in C++ with usage of the QT framework, the DIM library, and the IPBus technology. Prototype of the system is prepared and communication through DIM between parts was tested. An implementation of the IPBus technology was prepared and tested. The new DAQ proved to be able to fulfill requirements.

  14. FPGA Based Assembling of Facial Components for Human Face Construction

    CERN Document Server

    Halder, Santanu; Nasipuri, Mita; Basu, Dipak Kumar; Kundu, Mahantapas

    2010-01-01

    This paper aims at VLSI realization for generation of a new face from textual description. The FASY (FAce SYnthesis) System is a Face Database Retrieval and new Face generation System that is under development. One of its main features is the generation of the requested face when it is not found in the existing database. The new face generation system works in three steps - searching phase, assembling phase and tuning phase. In this paper the tuning phase using hardware description language and its implementation in a Field Programmable Gate Array (FPGA) device is presented.

  15. Phase correction on FPGA for TOTEM clock distribution system

    CERN Document Server

    Bellina, Alessandra

    2017-01-01

    A phase correction module has been implemented on FPGA, to control the delay of the clock at TOTEM timing detectors. The module consists of two parts: a phase shifter and a phase detector. The design of the phase shifter has been completed and was tested in the laboratory. The output jitter was measured and met the requirements. The phase detector design has also been completed and tested with a behavioural simulation, which outlined some weaknesses due to intrinsic limitations of FPGAs. The obtained resolution, although below ns scale, could not satisfy the requirements. A discussion on how to improve the performance of the phase detector is included.

  16. Research of Pipelined CORDIC Algorithm and Implementation Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    Zhongming JI; Xiaochen ZHAN

    2011-01-01

    CORDIC algorithm can transform the complex operations, which are difficult to be directly implemented by hardware circuits, into the simple addition and shift operations uniformly, then gradually approach the accurate result. The study gives a brief introduction of the ultimate principle and computing method of CORDIC algorithm. Taking sine and cosine as examples, the method of realization on FPGA is presented and it. is of good arithmetic speed as a result of using pipeline. The design has been provided correct by simulating and verification through Quartus II and Modelsim.

  17. Development of Integral Environment in Matlab/Simulink for FPGA

    Directory of Open Access Journals (Sweden)

    Dejan Jokic

    2014-01-01

    Full Text Available In this paper is presented realization of integral environment which consists of software and hardware components for the purpose of programming Altera DE boards. Software component is Toolbox FPGA Real Time which enables simple use of Matlab/Simulink with DSP Builder for the purpose of realization of control structures. Hardware component are Interface cards that make connection of DE board with object of control possible. Simulation and experimental results of DC motor control indicate the usefulness of the proposed concept.

  18. Design and Implementations of Linear Congruential Generator into FPGA

    Directory of Open Access Journals (Sweden)

    Zulfikar

    2014-07-01

    Full Text Available This paper exposes circuit design of linear congruential generator (LCG and implementation in FPGA. The circuit is derived from LCG algorithm proposed by Lehmer. Wordlengths reduction technique has been used to simplify the circuit. Several nets connection among the blocks of the circuit are ignored or disconnected. Simulation either behavior or timing have been done successfully. Four best Xilinx chips are chosen to gather comparison data of maximum speed and area occupied. Kintex 7 is the fastest chip among all it is about 309 MHz and Spartan 6 is slowest one which is only 73 MHz. The area occupied is similar among all of the selected chips.

  19. LAPACKrc: Fast linear algebra kernels/solvers for FPGA accelerators

    Energy Technology Data Exchange (ETDEWEB)

    Gonzalez, Juan; Nunez, Rafael C, E-mail: juan.gonzalez@accelogic.co [Accelogic, 1830 Main Street, Suite 204, Weston, FL (United States)

    2009-07-01

    We present LAPACKrc, a family of FPGA-based linear algebra solvers able to achieve more than 100x speedup per commodity processor on certain problems. LAPACKrc subsumes some of the LAPACK and ScaLAPACK functionalities, and it also incorporates sparse direct and iterative matrix solvers. Current LAPACKrc prototypes demonstrate between 40x-150x speedup compared against top-of-the-line hardware/software systems. A technology roadmap is in place to validate current performance of LAPACKrc in HPC applications, and to increase the computational throughput by factors of hundreds within the next few years.

  20. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    . Zulfikar

    2012-10-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  1. Novel Area Optimization in FPGA Implementation Using Efficient VHDL Code

    Directory of Open Access Journals (Sweden)

    Zulfikar Zulfikar

    2015-05-01

    Full Text Available A new novel method for area efficiency in FPGA implementation is presented. The method is realized through flexibility and wide capability of VHDL coding. This method exposes the arithmetic operations such as addition, subtraction and others. The design technique aim to reduce occupies area for multi stages circuits by selecting suitable range of all value involved in every step of calculations. Conventional and efficient VHDL coding methods are presented and the synthesis result is compared. The VHDL code which limits range of integer values is occupies less area than the one which is not. This VHDL coding method is suitable for multi stage circuits.

  2. DSP algorithms in FPGA: proposition of a new architecture

    Science.gov (United States)

    Kolasinski, Piotr; Zabolotny, Wojciech

    2008-01-01

    This paper presents a new reconfigurable architecture created in FPGA which is optimized for DSP algorithms like digital filters or digital transforms. The architecture tries to combine advantages of typical architectures like DSP processors and datapath architecture, while avoiding their drawbacks. The architecture is built from blocks called Operational Units (OU). Each Operational Unit contains the Control Unit (CU), which controls its operation. The Operational Units may operate in parallel, which shortens the processing time. This structure is also highly flexible, because all OUs may operate independently, executing their own programs. User may customize connections between units and modify architecture by adding new modules.

  3. An Optimal Implementation on FPGA of a Hopfield Neural Network

    Directory of Open Access Journals (Sweden)

    W. Mansour

    2011-01-01

    Full Text Available The associative Hopfield memory is a form of recurrent Artificial Neural Network (ANN that can be used in applications such as pattern recognition, noise removal, information retrieval, and combinatorial optimization problems. This paper presents the implementation of the Hopfield Neural Network (HNN parallel architecture on a SRAM-based FPGA. The main advantage of the proposed implementation is its high performance and cost effectiveness: it requires O(1 multiplications and O(log⁡ N additions, whereas most others require O(N multiplications and O(N additions.

  4. ECG signal analysis with wavelets and neural networks in FPGA

    OpenAIRE

    Klaus Raizer

    2010-01-01

    Resumo: Este trabalho apresenta a implementação de um sistema de análise de sinais de ECGs (eletrocardiogramas) embarcado em FPGA (field programmable gate array), capaz de classificar cardiopatias. A análise de ECGs é de grande importância devido a sua natureza potencialmente não-invasiva, baixo custo e alta eficiência na identificação de patologias cardíacas. Visto que um sinal de ECG pode ser composto por horas de gravação da atividade cardíaca, uma abordagem computacional para a sua anális...

  5. FPGA implementation of a pyramidal Weightless Neural Networks learning system.

    Science.gov (United States)

    Al-Alawi, Raida

    2003-08-01

    A hardware architecture of a Probabilistic Logic Neuron (PLN) is presented. The suggested model facilitates the on-chip learning of pyramidal Weightless Neural Networks using a modified probabilistic search reward/penalty training algorithm. The penalization strategy of the training algorithm depends on a predefined parameter called the probabilistic search interval. A complete Weightless Neural Network (WNN) learning system is modeled and implemented on Xilinx XC4005E Field Programmable Gate Array (FPGA), allowing its architecture to be configurable. Various experiments have been conducted to examine the feasibility and performance of the WNN learning system. Results show that the system has a fast convergence rate and good generalization ability.

  6. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain

    Directory of Open Access Journals (Sweden)

    Guillermo A. Jaquenod

    2014-01-01

    Full Text Available In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.

  7. 基于 FPGA 的 JPEG 编解码设计%JPEG coding and decoding design based on FPGA

    Institute of Scientific and Technical Information of China (English)

    张绪珩; 王淑仙

    2014-01-01

    JPEG ( Joint Photographic Experts Group )作为一个基本的图像压缩方式,已经得到了广泛的运用。而FPGA具有的并行计算特点,使得越来越多的设备利用FPGA对jpeg文件进行编解码。从整体上介绍JPEG编解码的基本算法,并着重介绍了在DCT和Huffman两个模块中使用的方法。在DCT/IDCT模块中,为了提高处理速度,充分利用FPGA并行处理的特点。对于Huff-man解码模块,采用附加码位宽的查找表方法,并利用综合工具将查找表综合到片内存储器中这一特点来减少资源。%JPEG ( Joint Photographic Experts Group ) , as a basic way of image compression , has been widely used .There are more and more devices processing jpeg files based on FPGA since its parallel processing feature .This paper provides a whole view of the JPEG encoding and decoding and gives out more attention to the DCT/IDCT and Huffman modules .In the DCT/IDCT module , thanks to the parallel processing of the FPGA , the improvement of processing speed can be achieved; as in the Huffman module , additional code length is used , and it costs less resource as the FPGA synthesis tool put the looking up table into the memory within the chip .

  8. Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

    Directory of Open Access Journals (Sweden)

    Marko Hännikäinen

    2006-10-01

    Full Text Available High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC. The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

  9. Scalable MPEG-4 Encoder on FPGA Multiprocessor SOC

    Directory of Open Access Journals (Sweden)

    Kulmala Ari

    2006-01-01

    Full Text Available High computational requirements combined with rapidly evolving video coding algorithms and standards are a great challenge for contemporary encoder implementations. Rapid specification changes prefer full programmability and configurability both for software and hardware. This paper presents a novel scalable MPEG-4 video encoder on an FPGA-based multiprocessor system-on-chip (MPSOC. The MPSOC architecture is truly scalable and is based on a vendor-independent intellectual property (IP block interconnection network. The scalability in video encoding is achieved by spatial parallelization where images are divided to horizontal slices. A case design is presented with up to four synthesized processors on an Altera Stratix 1S40 device. A truly portable ANSI-C implementation that supports an arbitrary number of processors gives 11 QCIF frames/s at 50 MHz without processor specific optimizations. The parallelization efficiency is 97% for two processors and 93% with three. The FPGA utilization is 70%, requiring 28 797 logic elements. The implementation effort is significantly lower compared to traditional multiprocessor implementations.

  10. An FPGA based Preprocessor for the ALICE high level trigger

    Energy Technology Data Exchange (ETDEWEB)

    Alt, T.; Lindenstruth, V.; Painke, F.; Peschek, J.; Steinbeck, T.M. [Kirchhoff Inst. of Physics, Ruprecht-Karls-Univ., Heidelberg (Germany)

    2007-07-01

    The H-RORC (High Level Trigger ReadOut Receiver Card) is an FPGA based PCI card designed to receive raw detector data from ALICE, transfer it into the online processing framework of the HLT cluster farm and transmit the processed data out of the HLT to the DAQ. Each RORC can be equipped with two optical receiver/transmitter units and transfer up to 400 Mbyte/s via PCI. For online processing in hardware the Virtex4 LX40 FPGA is supported by four independent modules of fast DDR-SDRAM providing up to 512 Mbyte total storage at a bandwidth of 2.3 Gbyte/s and two fast serial, full-duplex links which can be used as an direct interconnect in order to exchange data between several RORCs. In replay mode the onboard memory can be loaded with real or simulated events thus giving a real-time test-bench for the HLT framework. A special configuration scheme suits the requirements of a cluster environment and allows a safe and remote upgrade of the firmware. The H-RORC was used successfully in the first time run of the HLT during the TPC commissioning 2006. (orig.)

  11. Smart Capture Modules for Direct Sensor-to-FPGA Interfaces.

    Science.gov (United States)

    Oballe-Peinado, Óscar; Vidal-Verdú, Fernando; Sánchez-Durán, José A; Castellanos-Ramos, Julián; Hidalgo-López, José A

    2015-12-16

    Direct sensor-digital device interfaces measure time dependent variables of simple circuits to implement analog-to-digital conversion. Field Programmable Gate Arrays (FPGAs) are devices whose hardware can be reconfigured to work in parallel. They usually do not have analog-to-digital converters, but have many general purpose I/O pins. Therefore, direct sensor-FPGA connection is a good choice in complex systems with many sensors because several capture modules can be implemented to perform parallel analog data acquisition. The possibility to work in parallel and with high frequency clock signals improves the bandwidth compared to sequential devices such as conventional microcontrollers. The price to pay is usually the resolution of measurements. This paper proposes capture modules implemented in an FPGA which are able to perform smart acquisition that filter noise and achieve high precision. A calibration technique is also proposed to improve accuracy. Resolutions of 12 effective number of bits are obtained for the reading of resistors in the range of an example piezoresistive tactile sensor.

  12. A Sea-of-Gates Style FPGA Placement Algorithm

    Directory of Open Access Journals (Sweden)

    Kalapi Roy

    1996-01-01

    Full Text Available Field Programmable Gate Arrays (FPGAs have a pre-defined chip boundary with fixed cell locations and routing resources. Placement objectives for flexible architectures (e.g., the standard cell design style such as minimization of chip area do not reflect the primary placement goals for FPGAs. For FPGAs, the layout tools must seek 100% routability within the architectural constraints. Routability and congestion estimates must be made directly based on the demand and availability of routing resources for detailed routing of the particular FPGA. We. present a hierarchical placement approach consisting of two phases: a global placement phase followed by a detailed placement phase. The global placement phase minimizes congestion estimates of the global routing regions and satisfies all constraints at a coarser level. The detailed placer seeks to maximize the routability of the FPGA by considering factors which cause congestion at the detailed routing level and to precisely satisfy all of the constraints. Despite having limited knowledge about the gate level architectural details, we have achieved a 90%reduction in the number of unrouted nets in comparison to an industrial tool (the only other tool developed specifically for this architecture.

  13. An FPGA-based rapid wheezing detection system.

    Science.gov (United States)

    Lin, Bor-Shing; Yen, Tian-Shiue

    2014-01-29

    Wheezing is often treated as a crucial indicator in the diagnosis of obstructive pulmonary diseases. A rapid wheezing detection system may help physicians to monitor patients over the long-term. In this study, a portable wheezing detection system based on a field-programmable gate array (FPGA) is proposed. This system accelerates wheezing detection, and can be used as either a single-process system, or as an integrated part of another biomedical signal detection system. The system segments sound signals into 2-second units. A short-time Fourier transform was used to determine the relationship between the time and frequency components of wheezing sound data. A spectrogram was processed using 2D bilateral filtering, edge detection, multithreshold image segmentation, morphological image processing, and image labeling, to extract wheezing features according to computerized respiratory sound analysis (CORSA) standards. These features were then used to train the support vector machine (SVM) and build the classification models. The trained model was used to analyze sound data to detect wheezing. The system runs on a Xilinx Virtex-6 FPGA ML605 platform. The experimental results revealed that the system offered excellent wheezing recognition performance (0.912). The detection process can be used with a clock frequency of 51.97 MHz, and is able to perform rapid wheezing classification.

  14. A new FPGA architecture suitable for DSP applications

    Energy Technology Data Exchange (ETDEWEB)

    Wang Liyun; Lai Jinmei; Tong Jiarong; Tang Pushan; Chen Xing; Duan Xueyan; Chen Liguang; Wang Jian; Wang Yuan, E-mail: 071021037@fudan.edu.cn [ASIC and System State Key Laboratory, Fudan University, Shanghai 201203 (China)

    2011-05-15

    A new FPGA architecture suitable for digital signal processing applications is presented. DSP modules can be inserted into FPGA conveniently with the proposed architecture, which is much faster when used in the field of digital signal processing compared with traditional FPGAs. An advanced 2-level MUX (multiplexer) is also proposed. With the added SLEEP MODE PASS to traditional 2-level MUX, static leakage is reduced. Furthermore, buffers are inserted at early returns of long lines. With this kind of buffer, the delay of the long line is improved by 9.8% while the area increases by 4.37%. The layout of this architecture has been taped out in standard 0.13 {mu}m CMOS technology successfully. The die size is 6.3 x 4.5 mm{sup 2} with the QFP208 package. Test results show that performances of presented classical DSP cases are improved by 28.6%-302% compared with traditional FPGAs. (semiconductor integrated circuits)

  15. An FPGA Implementation of Secured Steganography Communication System

    Directory of Open Access Journals (Sweden)

    Ahlam Mahmood

    2014-04-01

    Full Text Available Steganography is the idea of hiding secret message in multimedia cover which will be transmitted through the Internet. The cover carriers can be image, video, sound or text data. This paper presents an implementation of color image steganographic system on Field Programmable Gate Array and the information hiding/extracting techniques in various images. The proposed algorithm is based on merge between the idea from the random pixel manipulation methods and the Least Significant Bit (LSB matching of Steganography embedding and extracting method.  In a proposed steganography hardware approach, Linear Feedback Shift Register (LFSR method has been used in stego architecture to hide the information in the image. The LFSRs are utilized in this approach as address generators. Different LFSR arrangements using different connection unit have been implemented at the hardware level for hiding/extracting the secret data. Multilayer embedding is implemented in parallel manner with a three-stage pipeline on FPGA.  This work showed attractive results especially in the high throughputs, better stego-image quality, requires little calculation and less utilization of FPGA area. The imperceptibility of the technique combined with high payload, robustness of embedded data and accurate data retrieval renders the proposed Steganography system is suitable for covert communication and secure data transmission applications

  16. FPGA Implementation of a Simple 3D Graphics Pipeline

    Directory of Open Access Journals (Sweden)

    Vladimir Kasik

    2015-01-01

    Full Text Available Conventional methods for computing 3D projects are nowadays usually implemented on standard or graphics processors. The performance of these devices is limited especially by the used architecture, which to some extent works in a sequential manner. In this article we describe a project which utilizes parallel computation for simple projection of a wireframe 3D model. The algorithm is optimized for a FPGA-based implementation. The design of the numerical logic is described in VHDL with the use of several basic IP cores used especially for computing trigonometric functions. The implemented algorithms allow smooth rotation of the model in two axes (azimuth and elevation and a change of the viewing angle. Tests carried out on a FPGA Xilinx Spartan-6 development board have resulted in real-time rendering at over 5000fps. In the conclusion of the article, we discuss additional possibilities for increasing the computational output in graphics applications via the use of HPC (High Performance Computing.

  17. Design of extensible meteorological data acquisition system based on FPGA

    Science.gov (United States)

    Zhang, Wen; Liu, Yin-hua; Zhang, Hui-jun; Li, Xiao-hui

    2015-02-01

    In order to compensate the tropospheric refraction error generated in the process of satellite navigation and positioning. Temperature, humidity and air pressure had to be used in concerned models to calculate the value of this error. While FPGA XC6SLX16 was used as the core processor, the integrated silicon pressure sensor MPX4115A and digital temperature-humidity sensor SHT75 are used as the basic meteorological parameter detection devices. The core processer was used to control the real-time sampling of ADC AD7608 and to acquire the serial output data of SHT75. The data was stored in the BRAM of XC6SLX16 and used to generate standard meteorological parameters in NEMA format. The whole design was based on Altium hardware platform and ISE software platform. The system was described in the VHDL language and schematic diagram to realize the correct detection of temperature, humidity, air pressure. The 8-channel synchronous sampling characteristics of AD7608 and programmable external resources of FPGA laid the foundation for the increasing of analog or digital meteorological element signal. The designed meteorological data acquisition system featured low cost, high performance, multiple expansions.

  18. Multidimensional-DSP Beamformers Using the ROACH-2 FPGA Platform

    Directory of Open Access Journals (Sweden)

    Vishwa Seneviratne

    2017-07-01

    Full Text Available Antenna array-based multi-dimensional infinite-impulse response (IIR digital beamformers are employed in a multitude of radio frequency (RF applications ranging from electronically-scanned radar, radio telescopes, long-range detection and target tracking. A method to design 3D IIR beam filters using 2D IIR beam filters is described. A cascaded 2D IIR beam filter architecture is proposed based on systolic array architecture as an alternative for an existing radar application. Differential-form transfer function and polyphase structures are employed in the design to gain an increase in the speed of operation to gigahertz range. The feasibility of practical implementation of a 4-phase polyphase 2D IIR beam filter is explored. A digital hardware prototype is designed, implemented and tested using a ROACH-2 Field Programmable Gate Array (FPGA platform fitted with a Xilinx Virtex-6 SX475T FPGA chip and multi-input analog-to-digital converters (ADC boards set to a maximum sampling rate of 960 MHz. The article describes a method to build a 3D IIR beamformer using polyphase structures. A comparison of technical specifications of an existing radar application based on phased-array and the proposed 3D IIR beamformer is also explained to illustrate the proposed method to be a better alternative for such applications.

  19. FPGA Implementation of OFDM Transceiver using FFT Algorithm

    Directory of Open Access Journals (Sweden)

    Rajesh Mehra

    2012-04-01

    Full Text Available Orthogonal Frequency Division Multiplexing (OFDM is the most promising modulation technique. It has been adopted by most wireless and wired communication standards. The idea is to utilize a number of carriers, spread regularly over a frequency band, in such a way so that the available bandwidth is utilized to maximal efficiency. In this paper the design and implementation of OFDM on a Field Programmable Gate Array (FPGA device has been presented. This attractive architecture uses Radix-2 serialized 512-point FFT (Fast Fourier Transform algorithm that enhances its speed. The system design is optimized in terms of both area and speed. The implementation was made on FPGA since it allows flexibility in design and also it can achieve higher computing speed than digital signal processors. ASIC-like performance with lower development time and risks can also be achieved. The results show that the design has been simulated up to 227.355 MHz and it achieves higher speed and lower area.

  20. Anti Theft Mechanism Through Face recognition Using FPGA

    Science.gov (United States)

    Sundari, Y. B. T.; Laxminarayana, G.; Laxmi, G. Vijaya

    2012-11-01

    The use of vehicle is must for everyone. At the same time, protection from theft is also very important. Prevention of vehicle theft can be done remotely by an authorized person. The location of the car can be found by using GPS and GSM controlled by FPGA. In this paper, face recognition is used to identify the persons and comparison is done with the preloaded faces for authorization. The vehicle will start only when the authorized personís face is identified. In the event of theft attempt or unauthorized personís trial to drive the vehicle, an MMS/SMS will be sent to the owner along with the location. Then the authorized person can alert the security personnel for tracking and catching the vehicle. For face recognition, a Principal Component Analysis (PCA) algorithm is developed using MATLAB. The control technique for GPS and GSM is developed using VHDL over SPTRAN 3E FPGA. The MMS sending method is written in VB6.0. The proposed application can be implemented with some modifications in the systems wherever the face recognition or detection is needed like, airports, international borders, banking applications etc.

  1. A Model of FPGA-based Direct Torque Controller

    Directory of Open Access Journals (Sweden)

    Auzani Jidin

    2013-02-01

    Full Text Available This paper presents a generic model of a fully FPGA-based direct torque controller. This model is developed using two’s-complement fixed-point format approaches, in register-transfer-level (RTL VHDL abstraction for minimizing calculation errors and consuming hardware resource usage. Therefore, the model is universal and can be implemented for all FPGA types. The model is prepared for fast computation, without using of CORDIC algorithm, a soft-core CPU, a transformation from Cartesian-to-polar coordinates, and without the help of third-party applications. To get simpler implementation and fast computation, several methods were introduced: i the backward-Euler approach to calculate the discrete-integration operation of stator flux, ii the modified non-restoring method to calculate complicated square-root operation of stator flux, iii a new sector analysis method. The design, which was coded in synthesizable VHDL in RTL abstraction for implementation on Altera DE2-board has produced very-precise calculations, with minimal error when being compared to MATLAB/Simulink double-precision calculation.

  2. Optimizing latency in Xilinx FPGA implementations of the GBT

    CERN Document Server

    Muschter, S; Bohm, C; Cachemiche, J-P; Baron, S

    2010-01-01

    The GigaBit Transceiver (GBT) {[}1] system has been developed to replace the Timing, Trigger and Control (TTC) system {[}2], currently used by LHC, as well as to provide data transmission between on-detector and off-detector components in future sLHC detectors. A VHDL version of the GBT-SERDES, designed for FPGAs, was released in March 2010 as a GBT-FPGA Starter Kit for future GBT users and for off-detector GBT implementation {[}3]. This code was optimized for resource utilization {[}4], as the GBT protocol is very demanding. It was not, however, optimized for latency - which will be a critical parameter when used in the trigger path. The GBT-FPGA Starter Kit firmware was first analyzed in terms of latency by looking at the separate components of the VHDL version. Once the parts which contribute most to the latency were identified and modified, two possible optimizations were chosen, resulting in a latency reduced by a factor of three. The modifications were also analyzed in terms of logic utilization. The la...

  3. FPGA based algorithms for data reduction at Belle II

    Energy Technology Data Exchange (ETDEWEB)

    Muenchow, David; Gessler, Thomas; Kuehn, Wolfgang; Lange, Jens Soeren; Liu, Ming; Spruck, Bjoern [II. Physikalisches Institut, Universitaet Giessen (Germany)

    2011-07-01

    Belle II, the upgrade of the existing Belle experiment at Super-KEKB in Tsukuba, Japan, is an asymmetric e{sup +}e{sup -} collider with a design luminosity of 8.10{sup 35}cm{sup -2}s{sup -1}. At Belle II the estimated event rate is {<=}30 kHz. The resulting data rate at the Pixel Detector (PXD) will be {<=}7.2 GB/s. This data rate needs to be reduced to be able to process and store the data. A region of interest (ROI) selection is based upon two mechanisms. a.) a tracklet finder using the silicon strip detector and b.) the HLT using all other Belle II subdetectors. These ROIs and the pixel data are forwarded to an FPGA based Compute Node for processing. Here a VHDL based algorithm on FPGA with the benefit of pipelining and parallelisation will be implemented. For a fast data handling we developed a dedicated memory management system for buffering and storing the data. The status of the implementation and performance tests of the memory manager and data reduction algorithm is presented.

  4. Design and Implementation of Quintuple Processor Architecture Using FPGA

    Directory of Open Access Journals (Sweden)

    P.Annapurna

    2014-09-01

    Full Text Available The advanced quintuple processor core is a design philosophy that has become a mainstream in Scientific and engineering applications. Increasing performance and gate capacity of recent FPGA devices permit complex logic systems to be implemented on a single programmable device. The embedded multiprocessors face a new problem with thread synchronization. It is caused by the distributed memory, when thread synchronization is violated the processors can access the same value at the same time. Basically the processor performance can be increased by adopting clock scaling technique and micro architectural Enhancements. Therefore, Designed a new Architecture called Advanced Concurrent Computing. This is implemented on the FPGA chip using VHDL. The advanced Concurrent Computing architecture performs a simultaneous use of both parallel and distributed computing. The full architecture of quintuple processor core designed for realistic to perform arithmetic, logical, shifting and bit manipulation operations. The proposed advanced quintuple processor core contains Homogeneous RISC processors, added with pipelined processing units, multi bus organization and I/O ports along with the other functional elements required to implement embedded SOC solutions. The designed quintuple performance issues like area, speed and power dissipation and propagation delay are analyzed at 90nm process technology using Xilinx tool.

  5. Renormalizing Partial Differential Equations

    OpenAIRE

    Bricmont, J.; Kupiainen, A.

    1994-01-01

    In this review paper, we explain how to apply Renormalization Group ideas to the analysis of the long-time asymptotics of solutions of partial differential equations. We illustrate the method on several examples of nonlinear parabolic equations. We discuss many applications, including the stability of profiles and fronts in the Ginzburg-Landau equation, anomalous scaling laws in reaction-diffusion equations, and the shape of a solution near a blow-up point.

  6. Real time mitigation of atmospheric turbulence in long distance imaging using the lucky region fusion algorithm with FPGA and GPU hardware acceleration

    Science.gov (United States)

    Jackson, Christopher Robert

    "Lucky-region" fusion (LRF) is a synthetic imaging technique that has proven successful in enhancing the quality of images distorted by atmospheric turbulence. The LRF algorithm selects sharp regions of an image obtained from a series of short exposure frames, and fuses the sharp regions into a final, improved image. In previous research, the LRF algorithm had been implemented on a PC using the C programming language. However, the PC did not have sufficient sequential processing power to handle real-time extraction, processing and reduction required when the LRF algorithm was applied to real-time video from fast, high-resolution image sensors. This thesis describes two hardware implementations of the LRF algorithm to achieve real-time image processing. The first was created with a VIRTEX-7 field programmable gate array (FPGA). The other developed using the graphics processing unit (GPU) of a NVIDIA GeForce GTX 690 video card. The novelty in the FPGA approach is the creation of a "black box" LRF video processing system with a general camera link input, a user controller interface, and a camera link video output. We also describe a custom hardware simulation environment we have built to test the FPGA LRF implementation. The advantage of the GPU approach is significantly improved development time, integration of image stabilization into the system, and comparable atmospheric turbulence mitigation.

  7. Design of a real-time system of moving ship tracking on-board based on FPGA in remote sensing images

    Science.gov (United States)

    Yang, Tie-jun; Zhang, Shen; Zhou, Guo-qing; Jiang, Chuan-xian

    2015-12-01

    With the broad attention of countries in the areas of sea transportation and trade safety, the requirements of efficiency and accuracy of moving ship tracking are becoming higher. Therefore, a systematic design of moving ship tracking onboard based on FPGA is proposed, which uses the Adaptive Inter Frame Difference (AIFD) method to track a ship with different speed. For the Frame Difference method (FD) is simple but the amount of computation is very large, it is suitable for the use of FPGA to implement in parallel. But Frame Intervals (FIs) of the traditional FD method are fixed, and in remote sensing images, a ship looks very small (depicted by only dozens of pixels) and moves slowly. By applying invariant FIs, the accuracy of FD for moving ship tracking is not satisfactory and the calculation is highly redundant. So we use the adaptation of FD based on adaptive extraction of key frames for moving ship tracking. A FPGA development board of Xilinx Kintex-7 series is used for simulation. The experiments show that compared with the traditional FD method, the proposed one can achieve higher accuracy of moving ship tracking, and can meet the requirement of real-time tracking in high image resolution.

  8. MicroBlaze implementation of GPS/INS integrated system on Virtex-6 FPGA.

    Science.gov (United States)

    Bhogadi, Lokeswara Rao; Gottapu, Sasi Bhushana Rao; Konala, Vvs Reddy

    2015-01-01

    The emphasis of this paper is on MicroBlaze implementation of GPS/INS integrated system on Virtex-6 field programmable gate array (FPGA). Issues related to accuracy of position, resource usage of FPGA in terms of slices, DSP48, block random access memory, computation time, latency and power consumption are presented. An improved design of a loosely coupled GPS/INS integrated system is described in this paper. The inertial navigation solution and Kalman filter computations are provided by the MicroBlaze on Virtex-6 FPGA. The real time processed navigation solutions are updated with a rate of 100 Hz.

  9. FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG

    Science.gov (United States)

    2014-06-01

    Document Number: SET 2014-0043 412TW-PA-14298 FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG June 2014 Final Report Test...To) 9/11 -- 8/14 4. TITLE AND SUBTITLE FPGA Implementation of Burst-Mode Synchronization for SOQSPK-TG 5a. CONTRACT NUMBER: W900KK-11-C-0032 5b...CA: Air Force Flight Test Center Edwards AFB CA CC: 012100 14. ABSTRACT In this paper, we present an FPGA implementation for

  10. High Speed Fault Injection Tool Implemented With Verilog HDL on FPGA for Testing Fault Tolerance Designs

    Directory of Open Access Journals (Sweden)

    G. Gopinath Reddy

    2013-11-01

    Full Text Available This paper presents an FPGA-based fault injection tool, called FITO that supports several synthesizable fault models for dependability analysis of digital systems modeled by Verilog HDL. Using the FITO, experiments can be performed in real-time with good controllability and observability. As a case study, an Open RISC 1200 microprocessor was evaluated using an FPGA circuit. About 4000 permanent, transient, and SEUfaults were injected into this microprocessor. The results show that the FITO tool is more than 79 times faster than a pure simulation-based fault injection with only 2.5% FPGA area overhead.

  11. FPGA-based floating-point datapath design for geometry processing

    Science.gov (United States)

    Xing, Shanzhen; Yu, William W.

    1998-10-01

    Geometry processing comprises of a great many computationally intensive floating-point operations. Real- time graphics systems generally use application-specific custom designed parallel hardware to provide the high performance computation power. When designing a graphics engine on a FPGA-based configurable computing system, cost- effectiveness is important. This paper investigates and proposes a cost-effective FPGA-based floating-point datapath for geometry process. It is designed to be a basic building block for FPGA-based geometry processors. The implemented datapath operates at a frequency of 6.25 Mhz and has an average floating-point operation time of 10.2 microseconds.

  12. FPGA-Based Approach to Level-1 Track Finding at CMS for the HL-LHC

    CERN Document Server

    Bartz, Edward Hugo; Gershtein, Yury; Halkiadakis, Eva; Hildreth, Michael; Kyriacou, Savvas; Lannon, Kevin Patrick; Lefeld, Anthony James; Ryd, Anders Per Erik; Skinnari, Louise; Stone, Robert; Strohman, Charles Ralph; Tao, Zhengcheng; Winer, Brian; Wittich, Peter; Zientek, Margaret Eldridge

    2017-01-01

    During the High Luminosity LHC, to maintain a manageable trigger rate and achieve its physics goals, the CMS detector will need charged particle tracking at the hardware trigger level. The tracklet approach is a track-finding algorithm based on a road-search algorithm that has been implemented on commercially available FPGA technology. This algorithm has achieved high performance in track-finding and completes tracking within 3.4 $\\mu$s on a Xilinx Virtex-7 FPGA. An overview of the algorithm and its implementation on an FPGA is given, results are shown from a demonstrator test stand and system performance studies are presented.

  13. FPGA-based rate-adaptive LDPC-coded modulation for the next generation of optical communication systems.

    Science.gov (United States)

    Zou, Ding; Djordjevic, Ivan B

    2016-09-05

    In this paper, we propose a rate-adaptive FEC scheme based on LDPC codes together with its software reconfigurable unified FPGA architecture. By FPGA emulation, we demonstrate that the proposed class of rate-adaptive LDPC codes based on shortening with an overhead from 25% to 42.9% provides a coding gain ranging from 13.08 dB to 14.28 dB at a post-FEC BER of 10-15 for BPSK transmission. In addition, the proposed rate-adaptive LDPC coding combined with higher-order modulations have been demonstrated including QPSK, 8-QAM, 16-QAM, 32-QAM, and 64-QAM, which covers a wide range of signal-to-noise ratios. Furthermore, we apply the unequal error protection by employing different LDPC codes on different bits in 16-QAM and 64-QAM, which results in additional 0.5dB gain compared to conventional LDPC coded modulation with the same code rate of corresponding LDPC code.

  14. FPGA based, DSP integrated, 8-channel SIMCON, ver. 3.0. Initial results for 8-channel algorithm

    Energy Technology Data Exchange (ETDEWEB)

    Giergusiewicz, W.; Koprek, W.; Jalmuzna, W.; Pozniak, K.T.; Romaniuk, R.S. [Warsaw Univ. of Technology (Poland). Inst. of Electronic Systems

    2005-07-01

    The paper describes design, construction and initial measurements of an eight channel electronic LLRF device predicted for building of the control system for the VUV-FEL accelerator at DESY (Hamburg). The device, referred in the paper to as the SIMCON 3.0 (from the SC cavity simulator and controller) consists of a 16 layer, VME size, PCB, a large FPGA chip (VirtexII-4000 by Xilinx), eight fast ADCs and four DACs (by Analog Devices). To our knowledge, the proposed device is the first of this kind for the accelerator technology in which there was achieved (the FPGA based) DSP latency below 200 ns. With the optimized data transmission system, the overall LLRF system latency can be as low as 500 ns. The SIMCON 3.0 sub-system was applied for initial tests with the ACC1 module of the VUV FEL accelerator (eight channels) and with the CHECHIA test stand (single channel), both at the DESY. The promising results with the SIMCON 3.0. encouraged us to enter the design of SIMCON 3.1. possessing 10 measurement and control channels and some additional features to be reported in the next technical note. SIMCON 3.0. is a modular solution, while SIMCON 3.1. will be an integrated board of the all-in-one type. Two design approaches - modular and all-in-one, after branching off in this version of the Simcon, will be continued. (orig.)

  15. A New High-Performance Digital FM Modulator and Demodulator for Software-Defined Radio and Its FPGA Implementation

    Directory of Open Access Journals (Sweden)

    Indranil Hatai

    2011-01-01

    Full Text Available This paper deals with an FPGA implementation of a high performance FM modulator and demodulator for software defined radio (SDR system. The individual component of proposed FM modulator and demodulator has been optimized in such a way that the overall design consists of a high-speed, area optimized and low-power features. The modulator and demodulator contain an optimized direct digital frequency synthesizer (DDFS based on quarter-wave symmetry technique for generating the carrier frequency with spurious free dynamic range (SFDR of more than 64 dB. The FM modulator uses pipelined version of the DDFS to support the up conversion in the digital domain. The proposed FM modulator and demodulator has been implemented and tested using XC2VP30-7ff896 FPGA as a target device and can operate at a maximum frequency of 334.5 MHz and 131 MHz involving around 1.93 K and 6.4 K equivalent gates for FM modulator and FM demodulator respectively. After applying a 10 KHz triangular wave input and by setting the system clock frequency to 100 MHz using Xpower the power has been calculated. The FM modulator consumes 107.67 mW power while FM demodulator consumes 108.67 mW power for the same input running at same data rate.

  16. Controlador empotrado en FPGA para Sistema Inteligente de Transporte

    Directory of Open Access Journals (Sweden)

    Alejandro José Cabrera Sarmiento

    2011-11-01

    Full Text Available 1024x768 Normal 0 21 false false false ES X-NONE X-NONE /* Style Definitions */ table.MsoNormalTable {mso-style-name:"Tabla normal"; mso-tstyle-rowband-size:0; mso-tstyle-colband-size:0; mso-style-noshow:yes; mso-style-priority:99; mso-style-qformat:yes; mso-style-parent:""; mso-padding-alt:0cm 5.4pt 0cm 5.4pt; mso-para-margin:0cm; mso-para-margin-bottom:.0001pt; mso-pagination:widow-orphan; font-size:11.0pt; font-family:"Calibri","sans-serif"; mso-ascii-font-family:Calibri; mso-ascii-theme-font:minor-latin; mso-fareast-font-family:"Times New Roman"; mso-fareast-theme-font:minor-fareast; mso-hansi-font-family:Calibri; mso-hansi-theme-font:minor-latin; mso-bidi-font-family:"Times New Roman"; mso-bidi-theme-font:minor-bidi;} En el presente trabajo se expone la concepción, desarrollo e implementación de un controlador empotrado en un FPGA de Xilinx para ser utilizado en un Sistema Inteligente de Transporte (SIT. La estructura hardware del controlador está basada en la utilización de diversos módulos de propiedad intelectual del sistema de procesamiento MicroBlaze y el soporte de software está basado en la utilización del sistema operativo Petalinux. El controlador empotrado dispone de interfaces Ethernet, USB, UART, SPI e I2C para la comunicación con los diferentes niveles jerárquicos del SIT. Ha sido implementado sobre una placa de desarrollo basada en un FPGA Spartan3E de 1.200 k compuertas, ocupando un 59% de sus recursos configurables. El resto de los recursos disponibles en el FPGA permite, además de la posible actualización del controlador, la implementación hardware de algoritmos que requieren una alta velocidad de procesamiento.

  17. Version control friendly project management system for FPGA designs

    Science.gov (United States)

    Zabołotny, Wojciech M.

    2016-09-01

    In complex FPGA designs, usage of version control system is a necessity. It is especially important in the case of designs developed by many developers or even by many teams. The standard development mode, however, offered by most FPGA vendors is the GUI based project mode. It is very convenient for a single developer, who can easily experiment with project settings, browse and modify the sources hierarchy, compile and test the design. Unfortunately, the project configuration is stored in files which are not suited for use with Version Control System (VCS). Another important problem in big FPGA designs is reuse of IP cores. Even though there are standard solutions like IEEE 1685-2014, they suffer from some limitations particularly significant for complex systems (e.g. only simple types are allowed for IP-core ports, it is not possible to use parametrized instances of IP-cores). Additionally, the overhead associated with packaging of IP-cores is significant and not justified for simple reusable blocks. This paper presents a system aimed at storing the whole design in a VCS oriented form. The hierarchy of sources is described with textual "extended project (EPRJ) files" which are fully controlled by the user and may also be put in a VCS. The IP blocks may be easily added to the project just by including the accompanying EPRJ file. Both absolute and relative file paths may be used which allows the flexible structure of directories. The sources of locally developed IP blocks may be stored in directories located inside the main source tree, while sources of independently developed blocks, using separate VCS repositories, may be located outside that tree. The environment allows splitting the design into smaller parts, which are synthesized independently. That reduces the time needed to recompile the whole design if only a few blocks are modified. The system creates the standard project, which can be used for convenient interactive work with the design. After the

  18. Efficient and side-channel resistant authenticated encryption of FPGA bitstreams

    DEFF Research Database (Denmark)

    Bogdanov, Andrey; Moradi, Amir; Yalcin, Tolga

    2013-01-01

    State-of-the-art solutions for FPGA bitstream protection rely on encryption and authentication of the bitstream to both ensure its confidentiality, thwarting unauthorized copying and reverse engineering, and prevent its unauthorized modification, maintaining a root of trust in the field. Adequate...... protection of the FPGA bitstream is of paramount importance to sustain the central functionality of dynamic reconfiguration in a hostile environment. In this work, we propose a new solution for authenticated encryption (AE) tailored for FPGA bitstream protection. It is based on the recent proposal presented...... AE modes of operation with the same countermeasure. We conclude that the deployment of dedicated AE schemes such as ALE significantly facilitates the real-world efficiency and security of FPGA bitstream protection in practice: Not only our solution enables authenticated encryption for bitstream...

  19. Extreme environment, rad hard, high performance, low power FPGA for space applications Project

    Data.gov (United States)

    National Aeronautics and Space Administration — To enable NASA's next-generation missions, there is a critical need for a reconfigurable FPGA that can withstand the wide temperatures ranges and radiation of the...

  20. Evaluating system for SRAM-based FPGA single event upset rate

    Science.gov (United States)

    Wang, Yunlong; Bao, Bin

    2016-09-01

    This paper takes static random-access-memory (SRAM)-based field-programmable-gate-array (FPGA) as the research object. Attention is focused on the configuration memory of this kind of FPGA, and the research has been devoted to the contents of the configuration memory and the configuration circuit to manage its contents. The single event upset (SEU) happening in the configuration memory doesn't lead to a functional failure necessarily. The dynamic SEU is SEU which happens in the configuration memory and causes necessarily function failure. This paper introduces a test method of dynamic SUE rate for the SRAM-based FPGA by designing a FPGA with self-test function.

  1. Variable Correlation Digital Noise Source on FPGA — A Versatile Tool for Debugging Radio Telescope Backends

    Science.gov (United States)

    Buch, Kaushal D.; Gupta, Yashwant; Ajith Kumar, B.

    Contemporary wideband radio telescope backends are generally developed on Field Programmable Gate Arrays (FPGA) or hybrid (FPGA+GPU) platforms. One of the challenges faced while developing such instruments is the functional verification of the signal processing backend at various stages of development. In the case of an interferometer or pulsar backend, the typical requirement is for one independent noise source per input, with provision for a common, correlated signal component across all the inputs, with controllable level of correlation. This paper describes the design of a FPGA-based variable correlation Digital Noise Source (DNS), and its applications to built-in testing and debugging of correlators and beamformers. This DNS uses the Central Limit Theorem-based approach for generation of Gaussian noise, and the architecture is optimized for resource requirements and ease of integration with existing signal processing blocks on FPGA.

  2. A High Performance FPGA-Based Sorting Accelerator with a Data Compression Mechanism

    National Research Council Canada - National Science Library

    KOBAYASHI, Ryohei; KISE, Kenji

    2017-01-01

    ... performance machines like embedded systems. In this paper, we present an FPGA-based sorting accelerator combining Sorting Network and Merge Sorter Tree, which is customizable by means of tuning design parameters...

  3. Implementing kinematics computation in FPGA co-processor for a 6-DOF space manipulator

    Institute of Scientific and Technical Information of China (English)

    Zheng Yili; Sun Hanxu; Jia Qingxuan; Shi Guozhen

    2009-01-01

    Based on the coordinate rotation digital computer (CORDIC) algorithm, the high-speed kinematics calculation for a six degree of freedom (DOF) space manipulator is implemented in a field programmable gate array (FPGA) co-processor. A pipeline architecture is adopted to reduce the complexity and time-consumption of the kinematics calculation. The CORDIC soft-core and the CORDIC-based pipelined kinematics calculation co-processor are described with the very-high-speed integrated circuit hardware description language (VHDL) language and realized in the FPGA. Finally, the feasibility of the design is validated in the Spartan-3 FPGA of Xilinx Inc., and the performance specifications of FPGA co-processor are discussed. The results show that time-consumption of the kinematics calculation is greatly reduced.

  4. FPGA Implementation of a Reconfigurable Viterbi Decoder for WiMAX Receiver

    CERN Document Server

    Shaker, Sherif Welsen; Shehata, Khaled Ali; 10.1109/ICM.2009.5418636

    2010-01-01

    Field Programmable Gate Array technology (FPGA) is a highly configurable option for implementing many sophisticated signal processing tasks in Software Defined Radios (SDRs). Those types of radios are realized using highly configurable hardware platforms. Convolutional codes are used in every robust digital communication system and Viterbi algorithm is employed in wireless communications to decode the convolutional codes. Such decoders are complex and dissipate large amount of power. In this paper, a low power-reconfigurable Viterbi decoder for WiMAX receiver is described using a VHDL code for FPGA implementation. The proposed design is implemented on Xilinx Virtex-II Pro, XC2vpx30 FPGA using the FPGA Advantage Pro package provided by Mentor Graphics and ISE 10.1 by Xilinx.

  5. 160-fold acceleration of the Smith-Waterman algorithm using a field programmable gate array (FPGA

    Directory of Open Access Journals (Sweden)

    Truong Kevin

    2007-06-01

    Full Text Available Abstract Background To infer homology and subsequently gene function, the Smith-Waterman (SW algorithm is used to find the optimal local alignment between two sequences. When searching sequence databases that may contain hundreds of millions of sequences, this algorithm becomes computationally expensive. Results In this paper, we focused on accelerating the Smith-Waterman algorithm by using FPGA-based hardware that implemented a module for computing the score of a single cell of the SW matrix. Then using a grid of this module, the entire SW matrix was computed at the speed of field propagation through the FPGA circuit. These modifications dramatically accelerated the algorithm's computation time by up to 160 folds compared to a pure software implementation running on the same FPGA with an Altera Nios II softprocessor. Conclusion This design of FPGA accelerated hardware offers a new promising direction to seeking computation improvement of genomic database searching.

  6. Dilemmas of partial cooperation.

    Science.gov (United States)

    Stark, Hans-Ulrich

    2010-08-01

    Related to the often applied cooperation models of social dilemmas, we deal with scenarios in which defection dominates cooperation, but an intermediate fraction of cooperators, that is, "partial cooperation," would maximize the overall performance of a group of individuals. Of course, such a solution comes at the expense of cooperators that do not profit from the overall maximum. However, because there are mechanisms accounting for mutual benefits after repeated interactions or through evolutionary mechanisms, such situations can constitute "dilemmas" of partial cooperation. Among the 12 ordinally distinct, symmetrical 2 x 2 games, three (barely considered) variants are correspondents of such dilemmas. Whereas some previous studies investigated particular instances of such games, we here provide the unifying framework and concisely relate it to the broad literature on cooperation in social dilemmas. Complementing our argumentation, we study the evolution of partial cooperation by deriving the respective conditions under which coexistence of cooperators and defectors, that is, partial cooperation, can be a stable outcome of evolutionary dynamics in these scenarios. Finally, we discuss the relevance of such models for research on the large biodiversity and variation in cooperative efforts both in biological and social systems.

  7. A FPGA Architecture for Foraging Behavior in Simulation and Colonies

    Directory of Open Access Journals (Sweden)

    Cristian David Rodríguez Rodríguez

    2015-08-01

    Full Text Available This paper presents some results regarding the desing and implementation of an architecture that supports an experimental platform for simulating the foraging process of ant colonies. Both the Ant-System and the Ant-Cycle algorithms model the behavior of ants. The platform allows to change parameters like the quantity and speed of ants, the amount and location of food and the ratio and difussion frequency of ant pheromone. These parameters are visualized through a VGA interface. The hardware implementation is carried out over FPGA Xilinx© technology. Theory behind this design considers that complex behaviors can emerge from systems with simple structure. This work confronts the question about global complexity emerging from a system whose structural complexity is minimal or inexistent.

  8. FPGA realization of Farrow structure for sampling rate change

    Directory of Open Access Journals (Sweden)

    Marković Bogdan

    2016-01-01

    Full Text Available In numerous implementations of modern telecommunications and digital audio systems there is a need for sampling rate change of the system input signal. When the relation between signal input and output sampling frequencies is a fraction of two large integer numbers, Lagrange interpolation based on Farrow structure can be used for the efficient realization of the resample block. This paper highlights efficient realization and estimation of necessary resources for polynomial cubic Lagrange interpolation in the case of the demand for the signal sampling rate change with the factor 160/147 on Field-Programmable Gate Array architecture (FPGA. [Projekat Ministarstva nauke Republike Srbije, br. TR-32023 i br. TR-32028

  9. FPGA implementation of Generalized Hebbian Algorithm for texture classification.

    Science.gov (United States)

    Lin, Shiow-Jyu; Hwang, Wen-Jyi; Lee, Wei-Hao

    2012-01-01

    This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA) because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA). It is embedded in a System-On-Programmable-Chip (SOPC) platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance and low area costs.

  10. FPGA-Based Multiprocessor System for Injection Molding Control

    Directory of Open Access Journals (Sweden)

    Roque A. Osornio-Rios

    2012-10-01

    Full Text Available The plastic industry is a very important manufacturing sector and injection molding is a widely used forming method in that industry. The contribution of this work is the development of a strategy to retrofit control of an injection molding machine based on an embedded system microprocessors sensor network on a field programmable gate array (FPGA device. Six types of embedded processors are included in the system: a smart-sensor processor, a micro fuzzy logic controller, a programmable logic controller, a system manager, an IO processor and a communication processor. Temperature, pressure and position are controlled by the proposed system and experimentation results show its feasibility and robustness. As validation of the present work, a particular sample was successfully injected.

  11. Implementation of FPGA-Based Diverse Protection System

    Energy Technology Data Exchange (ETDEWEB)

    Hwang, Soo Yun; Lee, Yoon Hee; Shon, Se Do; Baek, Seung Min [KEPCO Engineering and Construction Company Inc., Daejeon (Korea, Republic of)

    2015-10-15

    Obsolete analog and digital hardware platforms in NPPs are commonly replaced with programmable logic controller (PLC) and distributed control system (DCS). Field programmable gate arrays (FPGAs) are highlighted as an alternative to obsolete hardware platforms. FPGAs are digital integrated circuits (ICs) that contain the configurable (programmable) blocks of logic along with configurable interconnections among these blocks. Designers can configure (program) such devices to perform a tremendous variety of tasks. FPGAs have been evolved from the technology of programmable logic device (PLD). Nowadays, they can contain millions of logic gates by nanotechnology and can be used to implement extremely large and complex functions that previously could be realized only using application specific integrated circuits (ASICs). This paper presents the implementation of an FPGA-based diverse protection system (DPS) which executes the protective functions in NPP when the protective functions of the plant protection system (PPS) fails.

  12. Parallel Matrix Implementation of an Integer Division Algorithm Using FPGA

    Directory of Open Access Journals (Sweden)

    Eshwararao. Boddepalli

    2011-12-01

    Full Text Available This paper presents a method for fast, parallel matrix implementation of an integer division algorithm inside FPGA that can be used for real-time control systems. An essential improvement over the known matrix structure was made, with all the matrix lines having the same width which leads to equal and reduced propagation time. The alignment was also improved by reducing one algorithm step and eliminating one matrix line. Both fully combinational and pipelined versions of the algorithm were designed and tested until a functional physical implementation was obtained, including a user interface. The paper also presents new way to implement hardware structures inside programmable circuits, using portable schematic design from “Altium Designer” software environment instead textual description with HDL languages

  13. Research on FPGA-based Programmable Logic Controllers’ Technology

    Directory of Open Access Journals (Sweden)

    Zhu Huabing

    2013-07-01

    Full Text Available This paper introduces a scheme which implements the programmable logic controllers’ (PLCs function based on FPGA. This scheme follows the IEC61131-3 standard, selects Ladder Diagram (LD to write the PLC programs and selects VHDL as target language. Based on VS2005 platform, this scheme implements the construction of Ladder Diagram, compilation, simulation and other functions. This paper focuses on researching the construction method of Ladder Diagram, converting Ladder Diagram into Boolean equation and generating VHDL program by Boolean equivalence. The construction method of Ladder Diagram based on parallel-series hierarchical nested list and the implementing method of Boolean equivalence based on double-layer lists are proposed. Finally the correctness of the scheme is verified through an example.    

  14. Efficient implementation of 90° phase shifter in FPGA

    Directory of Open Access Journals (Sweden)

    Duraiswamy Punithavathi

    2011-01-01

    Full Text Available Abstract In this article, we present an efficient way of implementing 90° phase shifter using Hilbert transformer with canonic signed digit (CSD coefficients in FPGA. It is implemented using 27-tap symmetric finite impulse response (FIR filter. Representing the filter coefficients by CSD eliminates the need for multipliers and the filter is implemented using shifters and adders/subtractors. The simulated results for the frequency response of the Hilbert transformer with infinite precision coefficients and CSD coefficients agree with each other. The proposed architecture requires less hardware as one adder is saved for the realization of every negative coefficient compared to convectional CSD FIR filter implementation. Also, it offers a high accuracy of phase shift.

  15. QPSK Modulator and Demodulator Using FPGA for SDR

    Directory of Open Access Journals (Sweden)

    Mandadkar Mukesh

    2014-04-01

    Full Text Available A software-defined radio (SDR allows for digital communication systems to simply accept more complicated coding and modulation technologies, which is enormously vital in meeting the ever-increasing demands of the wireless communication industry. An SDR has been constructed, using the Simulink tool, and implemented on the SPARTEN-3E Field Programmable Gate Array (FPGA development kit. The modulation scheme used in the system is Quadrature Phase-Shift Keying (QPSK. In the first step to realize the whole modulation and demodulation schemes using MATLAB Simulink. The format of a VHDL program is built around the concept of BLOCKS which are the basic building units of a VHDL design. The results showed that the proposed method can greatly improve the developing efficiency, shorten developing period and reduce costs.

  16. Wavelet transform based ECG signal filtering implemented on FPGA

    Directory of Open Access Journals (Sweden)

    Germán-Salló Zoltán

    2011-12-01

    Full Text Available Filtering electrocardiographic (ECG signals is always a challenge because the accuracy of their interpretation depends strongly on filtering results. The Discrete Wavelet Transform (DWT is an efficient, new and useful tool for signal processing applications and it’s adopted in many domains as biomedical signal filtering. This transform came about from different fields, including mathematics, physics and signal processing, it has a growing applicability due to its so-called multiresolution analyzing capabilities. FPGAs are reconfigurable logic devices made up of arrays of logic cells and routing channels having some specific characteristics which allow to use them in signal processing applications. This paper presents a DWT based ECG signal denoising method implemented on FPGA, using Matlab specific Xilinx tool, as System Generator, the procedure is simulated and evaluated through filtering specific parameters.

  17. Two Methods of AES Implementation Based on CPLD/FPGA

    Institute of Scientific and Technical Information of China (English)

    刘常澍; 彭艮鹏; 王晓卓

    2004-01-01

    This paper describes two single-chip--complex programmable logic devices/field programmable gate arrays(CPLD/FPGA)--implementations of the new advanced encryption standard (AES) algorithm based on the basic iteration architecture (design [A]) and the hybrid pipelining architecture (design [B]). Design [A] is an encryption-and-decryption implementation based on the basic iteration architecture. This design not only supports 128-bit, 192-bit, 256-bit keys, but saves hardware resources because of the iteration architecture and sharing technology. Design [B] is a method of the 2×2 hybrid pipelining architecture. Based on the AES interleaved mode of operation, the design successfully accomplishes the algorithm, which operates in the feedback mode (cipher block chaining). It not only guarantees security of encryption/decryption, but obtains high data throughput of 1.05 Gb/s. The two designs have been realized on Aitera's EP20k300EBC652-1 devices.

  18. FPGA-based Accelerators for Parallel Data Sort

    Directory of Open Access Journals (Sweden)

    Sklyarov Valery

    2014-12-01

    Full Text Available The paper is dedicated to parallel data sort based on sorting networks. The proposed methods and circuits have the following characteristics: 1 using two-level parallel comparators in even-odd transition networks with feedback to a register keeping input/intermediate data; 2 parallel merging of many sorted sequences; 3 using even-odd transition networks built from other sorting networks; 4 rational reuse of comparators in different types of networks, namely even-odd transition and for discovering maximum/minimum values. The experiments in FPGA, which were done for up to 16×220 32-bit data items, demonstrate very good results (as fast as 3-5 ns per data item.

  19. FPGA Implementation of Generalized Hebbian Algorithm for Texture Classification

    Directory of Open Access Journals (Sweden)

    Wei-Hao Lee

    2012-05-01

    Full Text Available This paper presents a novel hardware architecture for principal component analysis. The architecture is based on the Generalized Hebbian Algorithm (GHA because of its simplicity and effectiveness. The architecture is separated into three portions: the weight vector updating unit, the principal computation unit and the memory unit. In the weight vector updating unit, the computation of different synaptic weight vectors shares the same circuit for reducing the area costs. To show the effectiveness of the circuit, a texture classification system based on the proposed architecture is physically implemented by Field Programmable Gate Array (FPGA. It is embedded in a System-On-Programmable-Chip (SOPC platform for performance measurement. Experimental results show that the proposed architecture is an efficient design for attaining both high speed performance andlow area costs.

  20. Researching and implementation of reconfigurable Hash chip based on FPGA

    Institute of Scientific and Technical Information of China (English)

    Yang Xiaohui; Dai Zibin; Liu Yuanfeng; Wang Ting

    2007-01-01

    The reconfigurable cryptographic chip is an integrated circuit that is designed by means of the method of reconfigurable architecture, and is used for encryption and decryption. Many different cipher algorithms can be flexibly implemented with the aid of a reconfigurable cryptographic chip and can be used in many fields. This article takes an example for the SHA-1/224/256 algorithms, and then designs a reconfigurable cryptographic chip based on the thought and method of the reconfigurable architecture. Finally, this paper gives the implementation result based on the FPGA of the family of Stratix II of Altera Corporation, and presents a good research trend for resolving the storage in hardware implementation using FPGAs.

  1. FPGA Implementations of Bireciprocal Lattice Wave Discrete Wavelet Filter Banks

    Directory of Open Access Journals (Sweden)

    Jassim M. Abdul-Jabbar

    2012-06-01

    Full Text Available In this paper, a special type of IIR filter banks; that is the bireciprocal lattice wave digital filter (BLWDF bank, is presented to simulate scaling and wavelet functions of six-level wavelet transform. 1st order all-pass sections are utilized for the realization of such filter banks in wave lattice structures. The resulting structures are a bireciprocal lattice wave discrete wavelet filter banks (BLW-DWFBs. Implementation of these BLW-DWFBs are accomplished on Spartan-3E FPGA kit. Implementation complexity and operating frequency characteristics of such discrete wavelet 5th order filter bank is proved to be comparable to the corresponding characteristics of the lifting scheme implementation of Bio. 5/3 wavelet filter bank. On the other hand, such IIR filter banks possess superior band discriminations and perfect roll-off frequency characteristics when compared to their Bio. 5/3 wavelet FIR counterparts.

  2. A Scalable Unsegmented Multiport Memory for FPGA-Based Systems

    Directory of Open Access Journals (Sweden)

    Kevin R. Townsend

    2015-01-01

    Full Text Available On-chip multiport memory cores are crucial primitives for many modern high-performance reconfigurable architectures and multicore systems. Previous approaches for scaling memory cores come at the cost of operating frequency, communication overhead, and logic resources without increasing the storage capacity of the memory. In this paper, we present two approaches for designing multiport memory cores that are suitable for reconfigurable accelerators with substantial on-chip memory or complex communication. Our design approaches tackle these challenges by banking RAM blocks and utilizing interconnect networks which allows scaling without sacrificing logic resources. With banking, memory congestion is unavoidable and we evaluate our multiport memory cores under different memory access patterns to gain insights about different design trade-offs. We demonstrate our implementation with up to 256 memory ports using a Xilinx Virtex-7 FPGA. Our experimental results report high throughput memories with resource usage that scales with the number of ports.

  3. FPGA Implementation of Real-Time Ethernet for Motion Control

    Directory of Open Access Journals (Sweden)

    Chen Youdong

    2013-01-01

    Full Text Available This paper provides an applicable implementation of real-time Ethernet named CASNET, which modifies the Ethernet medium access control (MAC to achieve the real-time requirement for motion control. CASNET is the communication protocol used for motion control system. Verilog hardware description language (VHDL has been used in the MAC logic design. The designed MAC serves as one of the intellectual properties (IPs and is applicable to various industrial controllers. The interface of the physical layer is RJ45. The other layers have been implemented by using C programs. The real-time Ethernet has been implemented by using field programmable gate array (FPGA technology and the proposed solution has been tested through the cycle time, synchronization accuracy, and Wireshark testing.

  4. Fast FPGA Implementation of EBCOT block in JPEG2000 Standard

    Directory of Open Access Journals (Sweden)

    Anass Mansouri

    2011-09-01

    Full Text Available Embedded block coding with optimized truncation (EBCOT is an important feature of the latest digital still-image compression standard, JPEG2000; however, it consumes more than 50% of the computation time in the compression process. In this paper, we propose a new high speed VLSI implementation of the EBCOT algorithm. The main concept of the proposed architecture is based on parallel access to memories, and uses an efficient design of the context generator block. The proposed architecture is described in VHDL language, verified by simulation and successfully implemented in a Cyclone II and Stratix III FPGA. It provides a major reduction in memory access requirements, as well as a net increase of the processing speed as shown by the simulations.

  5. Design and tuning of FPGA implementations of neural networks

    Science.gov (United States)

    Clare, Peter J. C.; Gulley, J. W.; Hickman, Duncan; Smith, Moira I.

    1997-06-01

    Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

  6. A Digitalized Silicon Microgyroscope Based on Embedded FPGA

    Directory of Open Access Journals (Sweden)

    Dunzhu Xia

    2012-09-01

    Full Text Available This paper presents a novel digital miniaturization method for a prototype silicon micro-gyroscope (SMG with the symmetrical and decoupled structure. The schematic blocks of the overall system consist of high precision analog front-end interface, high-speed 18-bit analog to digital convertor, a high-performance core Field Programmable Gate Array (FPGA chip and other peripherals such as high-speed serial ports for transmitting data. In drive mode, the closed-loop drive circuit are implemented by automatic gain control (AGC loop and software phase-locked loop (SPLL based on the Coordinated Rotation Digital Computer (CORDIC algorithm. Meanwhile, the sense demodulation module based on varying step least mean square demodulation (LMSD are addressed in detail. All kinds of algorithms are simulated by Simulink and DSPbuilder tools, which is in good agreement with the theoretical design. The experimental results have fully demonstrated the stability and flexibility of the system.

  7. Reconfigurable Gabor Filter For Fingerprint Recognition Using FPGA Verilog

    Science.gov (United States)

    Rosshidi, H. T.; Hadi, A. R.

    2009-06-01

    This paper present the implementations of Gabor filter for fingerprint recognition using Verilog HDL. This work demonstrates the application of Gabor Filter technique to enhance the fingerprint image. The incoming signal in form of image pixel will be filter out or convolute by the Gabor filter to define the ridge and valley regions of fingerprint. This is done with the application of a real time convolve based on Field Programmable Gate Array (FPGA) to perform the convolution operation. The main characteristic of the proposed approach are the usage of memory to store the incoming image pixel and the coefficient of the Gabor filter before the convolution matrix take place. The result was the signal convoluted with the Gabor coefficient.

  8. Parity Codes Used for On-Line Testing in FPGA

    Directory of Open Access Journals (Sweden)

    P. Kubalík

    2005-01-01

    Full Text Available This paper deals with on-line error detection in digital circuits implemented in FPGAs. Error detection codes have been used to ensure the self-checking property. The adopted fault model is discussed. A fault in a given combinational circuit must be detected and signalized at the time of its appearance and before further distribution of errors. Hence safe operation of the designed system is guaranteed. The check bits generator and the checker were added to the original combinational circuit to detect an error during normal circuit operation. This concurrent error detection ensures the Totally Self-Checking property. Combinational circuit benchmarks have been used in this work in order to compute the quality of the proposed codes. The description of the benchmarks is based on equations and tables. All of our experimental results are obtained by XILINX FPGA implementation EDA tools. A possible TSC structure consisting of several TSC blocks is presented. 

  9. A Neuron Model for FPGA Spiking Neuronal Network Implementation

    Directory of Open Access Journals (Sweden)

    BONTEANU, G.

    2011-11-01

    Full Text Available We propose a neuron model, able to reproduce the basic elements of the neuronal dynamics, optimized for digital implementation of Spiking Neural Networks. Its architecture is structured in two major blocks, a datapath and a control unit. The datapath consists of a membrane potential circuit, which emulates the neuronal dynamics at the soma level, and a synaptic circuit used to update the synaptic weight according to the spike timing dependent plasticity (STDP mechanism. The proposed model is implemented into a Cyclone II-Altera FPGA device. Our results indicate the neuron model can be used to build up 1K Spiking Neural Networks on reconfigurable logic suport, to explore various network topologies.

  10. Wireless Secured Data Transmission using Cryptographic Techniques through FPGA

    Directory of Open Access Journals (Sweden)

    I.Rama Satya Nageswara Rao

    2016-02-01

    Full Text Available The need to protect the data disturbances and unauthorized access in communication has led to development of several cryptographic algorithms. Current issue in modern world as popularity of internet, e-commerce and communication technologies has emerging and they became the medium to security threats. Due to advancement in cryptographic techniques the DNA technique is a new crypto algorithm to encrypt and decrypt data. It consists of two stage encryption based on DNA sequence enhances the data security compared to conventional methods. In encryption process the former stage will encrypt the data (plain text with a random key generated by random DNA sequence generator. Latter and final stage the encrypted data is re-encrypted with DNA translation to generate cipher. The cryptographic techniques (symmetric algorithm is designed and simulated using Xilinx ISE and targeted on Spartan-3E FPGA interfaced with ZigBee for wireless communication.

  11. Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

    Science.gov (United States)

    Jamot, Robert F.; Monroe, Ryan M.

    2012-01-01

    With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

  12. FPGA-based prototype of portable environmental radiation monitor

    Energy Technology Data Exchange (ETDEWEB)

    Benahmed, A.; Elkarch, H. [CNESTEN -Centre National de l' Energie des Sciences et Techniques Nucleaires (Morocco)

    2015-07-01

    This new portable radiological environmental monitor consists of 2 main components, Gamma ionization chamber and a FPGA-based electronic enclosure linked to convivial software for treatment and analyzing. The HPIC ion chamber is the heart of this radiation measurement system and is running in range from 0 to 100 mR/h, so that the sensitivity at the output is 20 mV/μR/h, with a nearly flat energy response from 0,07 to 10 MEV. This paper presents a contribution for developing a new nuclear measurement data acquisition system based on Cyclone III FPGA Starter Kit ALTERA, and a user-friendly software to run real-time control and data processing. It was developed to substitute the older radiation monitor RSS-112 PIC installed in CNESTEN's Laboratory in order to improve some of its functionalities related to acquisition time and data memory capacity. As for the associated acquisition software, it was conceived under the virtual LabView platform from National Instrument, and offers a variety of system setup for radiation environmental monitoring. It gives choice to display both the statistical data and the dose rate. Statistical data shows a summary of current data, current time/date and dose integrator values, and the dose rate displays the current dose rate in large numbers for viewing from a distance as well as the date and time. The prototype version of this new instrument and its data processing software has been successfully tested and validated for viewing and monitoring the environmental radiation of Moroccan nuclear center. (authors)

  13. Architectural Design Space Exploration of an FPGA-based Compressed Sampling Engine

    DEFF Research Database (Denmark)

    El-Sayed, Mohammad; Koch, Peter; Le Moullec, Yannick

    2015-01-01

    We present the architectural design space exploration of a compressed sampling engine for use in a wireless heart-rate monitoring system. We show how parallelism affects execution time at the register transfer level. Furthermore, two example solutions (modified semi-parallel and full-parallel) se......-parallel) selected from the design space are prototyped on an Altera Cyclone III FPGA platform; in both cases the FPGA resource usage is less than 1% and the maximum frequency is 250 MHz....

  14. The Design of A Kind of Electrical Appartus Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    <正>This paper deisgns a new kind of electrical appartus which developed by programmable logic devices FPGA and produce 2Hz,100Hz sine and rectangular wave signals based on the direct digital frequency synthesis principle.By testing,the frequency of output signal is precise,the output waveforms are stable.Because of using FPGA,the Peripheral equipments are fewer,with design flexible,field programmable,easy debugged and small volume.

  15. Time and Power Optimizations in FPGA-Based Architectures for Polyphase Channelizers

    DEFF Research Database (Denmark)

    Awan, Mehmood-Ur-Rehman; Harris, Fred; Koch, Peter

    2012-01-01

    This paper presents the time and power optimization considerations for Field Programmable Gate Array (FPGA) based architectures for a polyphase filter bank channelizer with an embedded square root shaping filter in its polyphase engine. This configuration performs two different re-sampling tasks......% slice register resources of a Xilinx Virtex-5 FPGA, operating at 400 and 480 MHz, and consuming 1.9 and 2.6 Watts of dynamic power, respectively....

  16. Design of Power Efficient FPGA based Hardware Accelerators for Financial Applications

    DEFF Research Database (Denmark)

    Hegner, Jonas Stenbæk; Sindholt, Joakim; Nannarelli, Alberto

    2012-01-01

    Using Field Programmable Gate Arrays (FPGAs) to accelerate financial derivative calculations is becoming very common. In this work, we implement an FPGA-based specific processor for European option pricing using Monte Carlo simulations, and we compare its performance and power dissipation...... to the execution on a CPU. The experimental results show that impressive results, in terms of speed-up and energy savings, can be obtained by using FPGA-based accelerators at expenses of a longer development time....

  17. Performance analysis and acceleration of cross-correlation computation using FPGA implementation for digital signal processing

    Science.gov (United States)

    Selma, R.

    2016-09-01

    Paper describes comparison of cross-correlation computation speed of most commonly used computation platforms (CPU, GPU) with an FPGA-based design. It also describes the structure of cross-correlation unit implemented for testing purposes. Speedup of computations was achieved using FPGA-based design, varying between 16 and 5400 times compared to CPU computations and between 3 and 175 times compared to GPU computations.

  18. 基于 FPGA 的SPI 总线接口的实现

    Institute of Scientific and Technical Information of China (English)

    黄威; 于梦磊

    2012-01-01

      FPGA 具有快速稳定、高效率等优点.SPI 接口具有全双工操作、协议简单、数据传输速率较高等优点.将FPGA 编程的灵活性和 SPI 总线的易用性结合,利用 Verilog 语言编程实 SPI 的接口功能.

  19. Design and implementation of a low-cost FPGA-Based bioimpedance measurement system

    OpenAIRE

    González Gutiérrez, Miguel

    2014-01-01

    Currently, many impedance measurement systems have been developed. This project details the design, implementation and characterization of a FPGA-based bioimpedance measurement system, whose goal is obtaining good performance at low costs. Signal generation and processing circuits were implemented within the FPGA, as well as the NIOS II embedded processor. An ADA conversion board as well as a front-end previously designed and implemented by the group of instrumentation and biomedical engineer...

  20. COTS FPGA/SRAM Irradiations Using a Dedicated Testing Infrastructure for Characterization of Large Component Batches

    CERN Document Server

    Slawosz, Uznanski; Johannes, Walter; Andrea, Vilar-Villanueva

    2015-01-01

    This paper introduces a new testing platform for irradiation of large batches of COTS FPGA and SRAMs. The main objective is measurement of component radiation response and assessment of component-to-component variability within one batch. The first validation and test results using the testing platform are presented for 150nm TFT SRAM (Renesas) and different sizes of the 130nm ProASIC3 FPGA (Microsemi).

  1. An area-efficient 2-D convolution implementation on FPGA for space applications

    OpenAIRE

    Gambardella, Giulio; Tiotto, Gabriele; Prinetto, Paolo Ernesto; Di Carlo, Stefano; Indaco, Marco; Rolfo, Daniele

    2011-01-01

    The 2-D Convolution is an algorithm widely used in image and video processing. Although its computation is simple, its implementation requires a high computational power and an intensive use of memory. Field Programmable Gate Arrays (FPGA) architectures were proposed to accelerate calculations of 2-D Convolution and the use of buffers implemented on FPGAs are used to avoid direct memory access. In this paper we present an implementation of the 2-D Convolution algorithm on a FPGA architecture ...

  2. Advantages Of Implementing Digital Receivers In Field Programmable Gate Arrays (FPGA)

    CERN Document Server

    Bremec, S; Mavric, U

    2003-01-01

    Today’s state-of-the-art FPGA technology allows designers to satisfy almost any demand for high-speed data processing needed in DSP applications and fast data transfers. Dedicated FPGA resources are used in DSP applications to perform down conversion, filtering and data formatting. New trends in system architecture favor serial data transfer rather than parallel by using FPGA’s internal resources, BRAMs, high speed serial IOs and hard core processors.

  3. The Monte Carlo validation framework for the discriminant partial least squares model extended with variable selection methods applied to authenticity studies of Viagra® based on chromatographic impurity profiles.

    Science.gov (United States)

    Krakowska, B; Custers, D; Deconinck, E; Daszykowski, M

    2016-02-07

    The aim of this work was to develop a general framework for the validation of discriminant models based on the Monte Carlo approach that is used in the context of authenticity studies based on chromatographic impurity profiles. The performance of the validation approach was applied to evaluate the usefulness of the diagnostic logic rule obtained from the partial least squares discriminant model (PLS-DA) that was built to discriminate authentic Viagra® samples from counterfeits (a two-class problem). The major advantage of the proposed validation framework stems from the possibility of obtaining distributions for different figures of merit that describe the PLS-DA model such as, e.g., sensitivity, specificity, correct classification rate and area under the curve in a function of model complexity. Therefore, one can quickly evaluate their uncertainty estimates. Moreover, the Monte Carlo model validation allows balanced sets of training samples to be designed, which is required at the stage of the construction of PLS-DA and is recommended in order to obtain fair estimates that are based on an independent set of samples. In this study, as an illustrative example, 46 authentic Viagra® samples and 97 counterfeit samples were analyzed and described by their impurity profiles that were determined using high performance liquid chromatography with photodiode array detection and further discriminated using the PLS-DA approach. In addition, we demonstrated how to extend the Monte Carlo validation framework with four different variable selection schemes: the elimination of uninformative variables, the importance of a variable in projections, selectivity ratio and significance multivariate correlation. The best PLS-DA model was based on a subset of variables that were selected using the variable importance in the projection approach. For an independent test set, average estimates with the corresponding standard deviation (based on 1000 Monte Carlo runs) of the correct

  4. FPGA-core defibrillator using wavelet-fuzzy ECG arrhythmia classification.

    Science.gov (United States)

    Nambakhsh, Mohammad; Tavakoli, Vahid; Sahba, Nima

    2008-01-01

    An electrocardiogram (ECG) feature extraction and classification system has been developed and evaluated using Quartus II 7.1 belong to Altera Ltd. In wavelet domain QRS complexes were detected and each complex was used to locate the peaks of the individual waves. Then, fuzzy classifier block used these features to classify ECG beats. Three types of arrhythmias and abnormalities were detected using the procedure. The completed algorithm was embedded into Field Programmable Gate Array (FPGA). The completed prototype was tested through software-generated signals, in which test scenarios covering several kinds of ECG signals on MIT-BIH Database. For the purpose of feeding signals into the FPGA, a software was designed to read signal files and import them to the LPT port of computer that was connected to FPGA. From the results, it was achieved that the proposed prototype could do real time monitoring of ECG signal for arrhythmia detection. We also implemented algorithm in a sequential structure device like AVR microcontroller with 16 MHZ clock for the same purpose. External clock of FPGA is 50 MHZ and by utilizing of Phase Lock Loop (PLL) component inside device, it was possible to increase the clock up to 1.2 GHZ in internal blocks. Final results compare speed and cost of resource usage in both devices. It shows that in cost of more resource usage, FPGA provides higher speed of computation; because FPGA makes the algorithm able to compute most parts in parallel manner.

  5. FPGA-Based Channel Coding Architectures for 5G Wireless Using High-Level Synthesis

    Directory of Open Access Journals (Sweden)

    Swapnil Mhaske

    2017-01-01

    Full Text Available We propose strategies to achieve a high-throughput FPGA architecture for quasi-cyclic low-density parity-check codes based on circulant-1 identity matrix construction. By splitting the node processing operation in the min-sum approximation algorithm, we achieve pipelining in the layered decoding schedule without utilizing additional hardware resources. High-level synthesis compilation is used to design and develop the architecture on the FPGA hardware platform. To validate this architecture, an IEEE 802.11n compliant 608 Mb/s decoder is implemented on the Xilinx Kintex-7 FPGA using the LabVIEW FPGA Compiler in the LabVIEW Communication System Design Suite. Architecture scalability was leveraged to accomplish a 2.48 Gb/s decoder on a single Xilinx Kintex-7 FPGA. Further, we present rapidly prototyped experimentation of an IEEE 802.16 compliant hybrid automatic repeat request system based on the efficient decoder architecture developed. In spite of the mixed nature of data processing—digital signal processing and finite-state machines—LabVIEW FPGA Compiler significantly reduced time to explore the system parameter space and to optimize in terms of error performance and resource utilization. A 4x improvement in the system throughput, relative to a CPU-based implementation, was achieved to measure the error-rate performance of the system over large, realistic data sets using accelerated, in-hardware simulation.

  6. Programming and Runtime Support to Blaze FPGA Accelerator Deployment at Datacenter Scale.

    Science.gov (United States)

    Huang, Muhuan; Wu, Di; Yu, Cody Hao; Fang, Zhenman; Interlandi, Matteo; Condie, Tyson; Cong, Jason

    2016-10-01

    With the end of CPU core scaling due to dark silicon limitations, customized accelerators on FPGAs have gained increased attention in modern datacenters due to their lower power, high performance and energy efficiency. Evidenced by Microsoft's FPGA deployment in its Bing search engine and Intel's 16.7 billion acquisition of Altera, integrating FPGAs into datacenters is considered one of the most promising approaches to sustain future datacenter growth. However, it is quite challenging for existing big data computing systems-like Apache Spark and Hadoop-to access the performance and energy benefits of FPGA accelerators. In this paper we design and implement Blaze to provide programming and runtime support for enabling easy and efficient deployments of FPGA accelerators in datacenters. In particular, Blaze abstracts FPGA accelerators as a service (FaaS) and provides a set of clean programming APIs for big data processing applications to easily utilize those accelerators. Our Blaze runtime implements an FaaS framework to efficiently share FPGA accelerators among multiple heterogeneous threads on a single node, and extends Hadoop YARN with accelerator-centric scheduling to efficiently share them among multiple computing tasks in the cluster. Experimental results using four representative big data applications demonstrate that Blaze greatly reduces the programming efforts to access FPGA accelerators in systems like Apache Spark and YARN, and improves the system throughput by 1.7 × to 3× (and energy efficiency by 1.5× to 2.7×) compared to a conventional CPU-only cluster.

  7. A digital frequency stabilization system of external cavity diode laser based on LabVIEW FPGA

    Science.gov (United States)

    Liu, Zhuohuan; Hu, Zhaohui; Qi, Lu; Wang, Tao

    2015-10-01

    Frequency stabilization for external cavity diode laser has played an important role in physics research. Many laser frequency locking solutions have been proposed by researchers. Traditionally, the locking process was accomplished by analog system, which has fast feedback control response speed. However, analog system is susceptible to the effects of environment. In order to improve the automation level and reliability of the frequency stabilization system, we take a grating-feedback external cavity diode laser as the laser source and set up a digital frequency stabilization system based on National Instrument's FPGA (NI FPGA). The system consists of a saturated absorption frequency stabilization of beam path, a differential photoelectric detector, a NI FPGA board and a host computer. Many functions, such as piezoelectric transducer (PZT) sweeping, atomic saturation absorption signal acquisition, signal peak identification, error signal obtaining and laser PZT voltage feedback controlling, are totally completed by LabVIEW FPGA program. Compared with the analog system, the system built by the logic gate circuits, performs stable and reliable. User interface programmed by LabVIEW is friendly. Besides, benefited from the characteristics of reconfiguration, the LabVIEW program is good at transplanting in other NI FPGA boards. Most of all, the system periodically checks the error signal. Once the abnormal error signal is detected, FPGA will restart frequency stabilization process without manual control. Through detecting the fluctuation of error signal of the atomic saturation absorption spectrum line in the frequency locking state, we can infer that the laser frequency stability can reach 1MHz.

  8. Design Verification Enhancement of FPGA-based Plant Protection System Trip Logics for Nuclear Power Plant

    Energy Technology Data Exchange (ETDEWEB)

    Ahmed, Ibrahim; Jung, Jae Cheon [KEPCO, Ulsan (Korea, Republic of); Heo, Gyun Young [Kyunghee University, Yongin (Korea, Republic of)

    2016-05-15

    As part of strengthening the application of FPGA technology and find solution to its challenges in NPPs, international atomic energy agency (IAEA) has indicated interest by joining sponsorship of Topical Group on FPGA Applications in NPPs (TG-FAN) that hold meetings up to 7th times until now, in form of workshop (International workshop on the application of FPGAs in NPPs) annually since 2008. The workshops attracted a significant interest and had a broad representation of stakeholders such as regulators, utilities, research organizations, system designers, and vendors, from various countries that converge to discuss the current issues regarding instrumentation and control (I and C) systems as well as FPGA applications. Two out of many technical issues identified by the group are lifecycle of FPGA-based platforms, systems, and applications; and methods and tools for V and V. Therefore, in this work, several design steps that involved the use of model-based systems engineering process as well as MATLAB/SIMULINK model which lead to the enhancement of design verification are employed. The verified and validated design output works correctly and effectively. Conclusively, the model-based systems engineering approach and the structural step-by-step design modeling techniques including SIMULINK model utilized in this work have shown how FPGA PPS trip logics design verification can be enhanced. If these design approaches are employ in the design of FPGA-based I and C systems, the design can be easily verified and validated.

  9. FPGA in-the-loop simulations of cardiac excitation model under voltage clamp conditions

    Science.gov (United States)

    Othman, Norliza; Adon, Nur Atiqah; Mahmud, Farhanahani

    2017-01-01

    Voltage clamp technique allows the detection of single channel currents in biological membranes in identifying variety of electrophysiological problems in the cellular level. In this paper, a simulation study of the voltage clamp technique has been presented to analyse current-voltage (I-V) characteristics of ion currents based on Luo-Rudy Phase-I (LR-I) cardiac model by using a Field Programmable Gate Array (FPGA). Nowadays, cardiac models are becoming increasingly complex which can cause a vast amount of time to run the simulation. Thus, a real-time hardware implementation using FPGA could be one of the best solutions for high-performance real-time systems as it provides high configurability and performance, and able to executes in parallel mode operation. For shorter time development while retaining high confidence results, FPGA-based rapid prototyping through HDL Coder from MATLAB software has been used to construct the algorithm for the simulation system. Basically, the HDL Coder is capable to convert the designed MATLAB Simulink blocks into hardware description language (HDL) for the FPGA implementation. As a result, the voltage-clamp fixed-point design of LR-I model has been successfully conducted in MATLAB Simulink and the simulation of the I-V characteristics of the ionic currents has been verified on Xilinx FPGA Virtex-6 XC6VLX240T development board through an FPGA-in-the-loop (FIL) simulation.

  10. Wavelet-Based Digital Image Fusion on Reconfigurable FPGA Using Handel-C Language

    Directory of Open Access Journals (Sweden)

    Dr. G. Mohan

    2013-07-01

    Full Text Available Field Programmable Gate Array (FPGA technology has become a viable target for the implementation of real time algorithms in different fusion methods have been proposed mainly in the fields of remote sensing and computer vision. Image fusion is basically a process where multiple images (more than one are combined to form a single resultant fused image. This fused image is more productive as compared to its original input images. In most paper image fusion algorithms were implemented in simulation level only. In this paper Wavelet based Image fusion algorithm is employed and implemented on a Field-Programmable-Gate-Array-based hardware system using a Xilinx Platform Studio EDK 11.1 FPGA Spartan 3E is implemented. The FPGA technologies offer basic digital blocks with flexible interconnections to achieve high speed digital hardware realization. The FPGA consists of a system of logic blocks, such as Look up Tables, gates, or flip-flops and some amount of memory. The algorithm will be transferred from computer to FPGA board using JTAG cable. In this proposed work algorithm is developed by using Handle –C language to performing wavelet based image fusion. The result will be transferred back to system to analyze hardware resource taken by FPGA

  11. 基于 FPGA 的报文分类技术%Packet classification based on FPGA

    Institute of Scientific and Technical Information of China (English)

    王敏; 邰铭

    2015-01-01

    Since the hierarchical intelligent cuttings (HiCuts)classification algorithms need to cut the search space into numbers of sub-spaces,which brings about the reproduction of rules and consumes large memory.Although HyperCuts allows cuttings of multi-dimen-sions at each step,it fails to eliminate duplicating rules.Based on HyperCuts,two optimization techniques were adopted for minimizing the rule duplication called rule overlap reduction and precisely cutting ranges.The simulation results on Xilinx Virtex-6 FPGA platforms shows that on-chip memory can store 10 K real-life rules and sustain 100 Gbps throughput for 40 bytes packets.%HiCuts (hierarchical intelligent cuttings)算法需要对搜索空间进行切割,导致规则的复制,消耗过多存储空间, HyperCuts 算法虽然允许每一步对多个维同时进行切割,降低了决策树的高度,但没有消除规则的复制。在 HyperCuts 算法的基础上,针对规则复制的两个来源,做两方面的改进,一是减少互相重叠的规则数,二是精确范围切割。在 Xilinx Virtex-6 FPGA 平台上对该优化算法进行仿真,布局布线结果表明,在单个芯片上能够存储10 K 的分类规则,当报文长度为40字节时,能够维持100 Gbps 的吞吐量。

  12. FPGA-based real-time embedded system for RISS/GPS integrated navigation.

    Science.gov (United States)

    Abdelfatah, Walid Farid; Georgy, Jacques; Iqbal, Umar; Noureldin, Aboelmagd

    2012-01-01

    Navigation algorithms integrating measurements from multi-sensor systems overcome the problems that arise from using GPS navigation systems in standalone mode. Algorithms which integrate the data from 2D low-cost reduced inertial sensor system (RISS), consisting of a gyroscope and an odometer or wheel encoders, along with a GPS receiver via a Kalman filter has proved to be worthy in providing a consistent and more reliable navigation solution compared to standalone GPS receivers. It has been also shown to be beneficial, especially in GPS-denied environments such as urban canyons and tunnels. The main objective of this paper is to narrow the idea-to-implementation gap that follows the algorithm development by realizing a low-cost real-time embedded navigation system capable of computing the data-fused positioning solution. The role of the developed system is to synchronize the measurements from the three sensors, relative to the pulse per second signal generated from the GPS, after which the navigation algorithm is applied to the synchronized measurements to compute the navigation solution in real-time. Employing a customizable soft-core processor on an FPGA in the kernel of the navigation system, provided the flexibility for communicating with the various sensors and the computation capability required by the Kalman filter integration algorithm.

  13. Research on the Key Technique of SPC Exchange Equipment Based on FPGA

    Directory of Open Access Journals (Sweden)

    Liu Yuansheng

    2013-07-01

    Full Text Available In the program controlled exchange technology college course, the signal transmission and voice data exchange for the communication system were usually achieved by utilizing the program controlled telephone exchange equipment choosing MT8980 series chip as the processing core which was limited to the numbers of communication channels and inflexibility of information interchange manners. A variety of extern circuits, taking time slice generation circuit and tone signal generation circuit as examples, will even be required which directly causes the complexity of the whole structure. Considering the disadvantages referred above, a new method of SPC (Stored Program Control exchange exploiting FPGA (Field Programmable Gate Array is proposed in this paper. The time slice generation, signal tone generation, user calls, voice data exchange functions, as well as other secondary functions, were realized by applying the new approach which allows the further development through hardware in-system programming. The superiority of the means is furnished in the end via comparing the experimental data in detail.  

  14. Control electronic platform based on floating-point DSP and FPGA for a NPC multilevel back-to-back converter

    Energy Technology Data Exchange (ETDEWEB)

    Rodriguez, Francisco J.; Cobreces, Santiago; Bueno, Emilio J.; Hernandez, Alvaro; Mateos, Raul; Espinosa, Felipe [Department of Electronics, University of Alcala, Alcala de Henares, Madrid (Spain)

    2008-09-15

    Modern energy concepts as Distributed Power Generation are changing the appearance of electric distribution and transmission and challenging power electronics researchers, which try to develop new solutions of electronic controllers. The aim is to enable the implementation of new and more complex control algorithms to verify the last standards related to the grid energy quality for new power converters, and, also, for equipments which nowadays are operating. This paper presents the design, implementation and test of a novel real-time controller for a Neutral Point Clamped (NPC) (three-level) multilevel converter based on a floating-point Digital Signal Processor (DSP) and on a Field-Programmable Gate Array (FPGA), by operating in a cooperative way. Although the proposed system can be readily applied to any power electronic application, in this work, it is focused on the next system: a 150 kVA back-to-back three-level NPC Voltage Source Converter (VSC) for wind power applications. (author)

  15. Partially ordered algebraic systems

    CERN Document Server

    Fuchs, Laszlo

    2011-01-01

    Originally published in an important series of books on pure and applied mathematics, this monograph by a distinguished mathematician explores a high-level area in algebra. It constitutes the first systematic summary of research concerning partially ordered groups, semigroups, rings, and fields. The self-contained treatment features numerous problems, complete proofs, a detailed bibliography, and indexes. It presumes some knowledge of abstract algebra, providing necessary background and references where appropriate. This inexpensive edition of a hard-to-find systematic survey will fill a gap i

  16. FPGA-based distributed computing microarchitecture for complex physical dynamics investigation.

    Science.gov (United States)

    Borgese, Gianluca; Pace, Calogero; Pantano, Pietro; Bilotta, Eleonora

    2013-09-01

    In this paper, we present a distributed computing system, called DCMARK, aimed at solving partial differential equations at the basis of many investigation fields, such as solid state physics, nuclear physics, and plasma physics. This distributed architecture is based on the cellular neural network paradigm, which allows us to divide the differential equation system solving into many parallel integration operations to be executed by a custom multiprocessor system. We push the number of processors to the limit of one processor for each equation. In order to test the present idea, we choose to implement DCMARK on a single FPGA, designing the single processor in order to minimize its hardware requirements and to obtain a large number of easily interconnected processors. This approach is particularly suited to study the properties of 1-, 2- and 3-D locally interconnected dynamical systems. In order to test the computing platform, we implement a 200 cells, Korteweg-de Vries (KdV) equation solver and perform a comparison between simulations conducted on a high performance PC and on our system. Since our distributed architecture takes a constant computing time to solve the equation system, independently of the number of dynamical elements (cells) of the CNN array, it allows us to reduce the elaboration time more than other similar systems in the literature. To ensure a high level of reconfigurability, we design a compact system on programmable chip managed by a softcore processor, which controls the fast data/control communication between our system and a PC Host. An intuitively graphical user interface allows us to change the calculation parameters and plot the results.

  17. FPGA连接检测方法%The Connection Test Method of FPGA

    Institute of Scientific and Technical Information of China (English)

    陈新之; 陈旻

    2013-01-01

    目前大容量的FPGA多采用BGA封装,当其焊接到电路板上后,引脚连接情况很难检测。本文根据单板上除了FPGA外是否使用其他处理器为依据,将使用了FPGA的单板分为仅有FPGA的单板和包含处理器的单板,根据不同类型单板的特点,给出了FPGA方波输出法和MCU地址数据总线扫描法两种切实可行的检测方法,将这两种方法配合在一起,可以检测出大部分FPGA连接问题。文章还以Altera公司的Cyclone Ⅳ系列FPGA为例,说明了这些检测方法的实现方式。这些检测方法在单板返修中取得了良好的效果。%The common package of large scale FPGA is BGA. After the FPGA is soldered on the target board, the connection of FPGA is dififcult to test.. This article classiifes the target board with FPGA in two types by using or not using MCU. Then this article describes two methods to test the connection of FPGA on different types of target boards. One is FPGA square wave generation method, the other is MCU address bus and data bus scanning method. At last, this article give two actual examples of testing connection using Altera’s Cyclone IV FPGA. These methods work well on repairing fault target boards.

  18. Analysis of FPGA filter in Computed Tomography Images for Radioactive Dose Reduction; Analisis del Filtro FPGA en Imagenes de Tomografia Computarizada para la Reduccion de Dosis Radiactiva

    Energy Technology Data Exchange (ETDEWEB)

    Parcero, E.; Vidal, V.; Verdu, G.; Arnal, J.; Mayo, P.

    2014-07-01

    In this study, different filtering methods are compared on an image of mini-MIAS database (consisting of a collection of mammographic images). Methods employees are PGFM (Peer Group Fuzzy Metric), NDF (Non-linear Diffusion Method) a combination of these two, and FPGA (Fuzzy Peer Group Average). (Author)

  19. 基于 FPGA 的煤矿井下监控分站设计%Design the Monitoring Substation of Coal Mine Underground Based on FPGA

    Institute of Scientific and Technical Information of China (English)

    辛永祥; 张小波; 刘京威

    2015-01-01

    针对现有煤矿安全监控系统中越来越多传感器支持485/C A N智能通信,分站支持接口个数少、采用单一的微处理器对传感器的数据进行采集,从而导致现有分站组网成本高、数据响应实时性差等问题。提出一种基于 FPGA 的煤矿井下监控分站设计方案。详细介绍分站的软件和硬件总体架构设计;FPGA 关键信号采集和信号处理技术;部分关键电路详细设计;双口 FIFO 完成 FPGA 与 MCU 之间的通信,解决了 FPGA 与 MCU 工作时钟不一致的问题;同时可以采用红外遥控,灵活设置 FPGA 工作参数,完成人机交互等任务。该方案设计的分站具有数据响应实时性好、485接口个数多、布局布线成本低、适用不同传输接口类型的传感器接入监控系统等优点。%In view of more and more sensors support 485/CAN intelligent communication in the coal mine safety monitoring system ,the substation has few interfaces ,using a single microprocessor for sensor data acquisition ,leads to the existing substation network of high cost ,poor real-time data re-sponse problems. The paper put forward a design scheme of based on FPGA monitoring substation of coal mine underground. Detailed introduction of software and hardware architecture of substation de-sign ;The FPGA key signal acquisition and signal processing technology ;detailed introduction some key circuits design ;use the Dual port FIFO to complete the communication between FPGA and MCU , solve the problem of between FPGA and MCU inconsistent work clock ;At the same time can use the infrared remote control ,flexible setting of FPGA parameters to complete the work ,such as human-computer interaction task. The scheme design of the substation has the advantages of good real-time performance ,response data interface layout and wiring ,485 more low cost ,suitable for different transmission interface type sensor access monitoring system.

  20. Cast Partial Denture versus Acrylic Partial Denture for Replacement of Missing Teeth in Partially Edentulous Patients

    Directory of Open Access Journals (Sweden)

    Pramita Suwal

    2017-03-01

    Full Text Available Aim: To compare the effects of cast partial denture with conventional all acrylic denture in respect to retention, stability, masticatory efficiency, comfort and periodontal health of abutments. Methods: 50 adult partially edentulous patient seeking for replacement of missing teeth having Kennedy class I and II arches with or without modification areas were selected for the study. Group-A was treated with cast partial denture and Group-B with acrylic partial denture. Data collected during follow-up visit of 3 months, 6 months, and 1 year by evaluating retention, stability, masticatory efficiency, comfort, periodontal health of abutment. Results: Chi-square test was applied to find out differences between the groups at 95% confidence interval where p = 0.05. One year comparison shows that cast partial denture maintained retention and stability better than acrylic partial denture (p< 0.05. The masticatory efficiency was significantly compromising from 3rd month to 1 year in all acrylic partial denture groups (p< 0.05. The comfort of patient with cast partial denture was maintained better during the observation period (p< 0.05. Periodontal health of abutment was gradually deteriorated in all acrylic denture group (p

  1. FPGA design of correlation-based pattern recognition

    Science.gov (United States)

    Jridi, Maher; Alfalou, Ayman

    2017-05-01

    Optical/Digital pattern recognition and tracking based on optical/digital correlation are a well-known techniques to detect, identify and localize a target object in a scene. Despite the limited number of treatments required by the correlation scheme, computational time and resources are relatively high. The most computational intensive treatment required by the correlation is the transformation from spatial to spectral domain and then from spectral to spatial domain. Furthermore, these transformations are used on optical/digital encryption schemes like the double random phase encryption (DRPE). In this paper, we present a VLSI architecture for the correlation scheme based on the fast Fourier transform (FFT). One interesting feature of the proposed scheme is its ability to stream image processing in order to perform correlation for video sequences. A trade-off between the hardware consumption and the robustness of the correlation can be made in order to understand the limitations of the correlation implementation in reconfigurable and portable platforms. Experimental results obtained from HDL simulations and FPGA prototype have demonstrated the advantages of the proposed scheme.

  2. FPGA-specific decimal sign-magnitude addition and subtraction

    Science.gov (United States)

    Vázquez, Martín; Todorovich, Elías

    2016-07-01

    The interest in sign-magnitude (SM) representation in decimal numbers lies in the IEEE 754-2008 standard, where the significand in floating-point numbers is coded as SM. However, software implementations do not meet performance constraints in some applications and more development is required in programmable logic, a key technology for hardware acceleration. Thus, in this work, two strategies for SM decimal adder/subtractors are studied and six new Field Programmable Gate Array (FPGA)-specific circuits are derived from these strategies. The first strategy is based on ten's complement (C10) adder/subtractors and the second one is based on parallel computation of an unsigned adder and an unsigned subtractor. Four of these alternative circuits are useful for at least one area-time-trade-off and specific operand size. For example, the fastest SM adder/subtractor for operand sizes of 7 and 16 decimal digits is based on the second proposed strategy with delays of 3.43 and 4.33 ns, respectively, but the fastest circuit for 34-digit operands is one of the three specific implementations based on C10 adder/subtractors with a delay of 4.65 ns.

  3. FPGA Control System for the Automated Test of Microshutters

    Science.gov (United States)

    Lyness, Eric; Rapchun, David A.; Moseley, S. Harvey

    2008-01-01

    The James Webb Space Telescope, scheduled to replace the Hubble in 2013, must simultaneously observe hundreds of faint galaxies. This requirement has led to the development of a programmable transmission mask which can be adapted to admit light with arbitrary pattern of galaxies into its spectrograph. This programmable mask will contain a large array of micro-electromechanical (MEMs) devices called MicroShutters. These microscopic shutters physically open and close like the shutter on a camera, except each shutter is microscopic in size and an array 365 by 171 is used to select the objects under spectroscopic observation at a given time, and to block the unwanted background light from other areas. NASA developed and is currently refining the exceptionally difficult process of manufacturing these shutters. This paper describes how the authors used LabVIEW FPGA and a reconfigurable I/O board to control the shutters in a test chamber and how the flexibility of the system allows us to continue to modify the control algorithms as NASA optimizes the performance of the MicroShutter arrays.

  4. A Fast Floating Point Double Precision Implementation on Fpga

    Directory of Open Access Journals (Sweden)

    Monika Maan

    2016-06-01

    Full Text Available In the modern day digital systems, floating point units are an important component in many signal and image processing applications. Many approaches of the floating point units have been proposed and compared with their counterparts in recent years. IEEE 754 floating point standard allows two types of precision units for floating point operations, single and double. In the proposed architecture double precision floating point unit is used and basic arithmetic operations are performed. A parallel architecture is proposed along with the high speed adder, which is shared among other operations and can perform operations independently as a separate unit. To improve the area efficiency of the unit, carry select adder is designed with the novel resource sharing technique which allows performing the operations with the minimum usage of the resources while computing the carry and sum for „0‟ and „1‟. The design is implemented using the Xilinx Spartan 6 FPGA and the results show the 23% improvement in the speed of the designed circuit.

  5. Fast neuromimetic object recognition using FPGA outperforms GPU implementations.

    Science.gov (United States)

    Orchard, Garrick; Martin, Jacob G; Vogelstein, R Jacob; Etienne-Cummings, Ralph

    2013-08-01

    Recognition of objects in still images has traditionally been regarded as a difficult computational problem. Although modern automated methods for visual object recognition have achieved steadily increasing recognition accuracy, even the most advanced computational vision approaches are unable to obtain performance equal to that of humans. This has led to the creation of many biologically inspired models of visual object recognition, among them the hierarchical model and X (HMAX) model. HMAX is traditionally known to achieve high accuracy in visual object recognition tasks at the expense of significant computational complexity. Increasing complexity, in turn, increases computation time, reducing the number of images that can be processed per unit time. In this paper we describe how the computationally intensive and biologically inspired HMAX model for visual object recognition can be modified for implementation on a commercial field-programmable aate Array, specifically the Xilinx Virtex 6 ML605 evaluation board with XC6VLX240T FPGA. We show that with minor modifications to the traditional HMAX model we can perform recognition on images of size 128 × 128 pixels at a rate of 190 images per second with a less than 1% loss in recognition accuracy in both binary and multiclass visual object recognition tasks.

  6. FPGA based digital backend system for the Gauribidanur Radioheliograph

    Science.gov (United States)

    Barve, Indrajit V.; Sarpotadar, Mayuresh; Sundara Rajan, M. S.; Ramesh, R.; Kathiravan, C.

    The Indian Institute of Astrophysics operates a low frequency (radio observatory (≈ 77°E 14°N) located about 100 km north of Bangalore (Ramesh et al. 1998; Ramesh 2011). The basic receiving element in the radioheliograph (called the Gauribidanur RAdioheliograPH, GRAPH) is a log-periodic dipole (LPD). The array has 384 of them arranged in a 'T' configuration. The arms of the `T' are in the east-west and north-south directions. The LPDs in the each of the above two arms are subdivided into 32 groups. RF signal from the 64 antenna groups in the array are presently correlated using a 4096-channel correlator system comprising of discrete digital circuit elements (Ramesh et al. 2006). Taking advantage of the developments in the field of signal processing, a FPGA based digital backend system is being developed for the GRAPH. To this date, a prototype 8-channel system has been designed and fabricated. All possible correlations between signals from 8 different antenna groups can be performed with this system either online or offline. http://www.iiap.res.in/centers/radio

  7. Reliability Tests of the LHC Beam Loss Monitoring FPGA Firmware

    CERN Document Server

    Hajdu, C F; Dehning, B; Jackson, S

    2010-01-01

    The LHC Beam Loss Monitoring (BLM) system is one of the most complex instrumentation systems deployed in the LHC. In addition to protecting the collider, the system also needs to provide a means of diagnosing machine faults and deliver a feedback of losses to the control room as well as to several systems for their setup and analysis. It has to transmit and process signals from almost 4’000 monitors, and has nearly 3 million configurable parameters. In a system of such complexity, firmware reliability is a critical issue. The integrity of the signal chain of the LHC BLM system and its ability to correctly detect unwanted scenarios and thus provide the required protection level must be ensured. In order to analyze the reliability and functionality, an advanced verification environment has been developed to evaluate the performance and response of the FPGA-based data analysis firmware. This paper will report on the numerous tests that have been performed and on how the results are used to quantify the reliabi...

  8. Cryogenic loss monitors with FPGA TDC signal processing

    Energy Technology Data Exchange (ETDEWEB)

    Warner, A.; Wu, J.; /Fermilab

    2011-09-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highlight the processing techniques used.

  9. Electronic readout for THGEM detectors based on FPGA TDCs

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Koenigsmann, Kay; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany); Collaboration: COMPASS-II RICH upgrade Group

    2013-07-01

    In the framework of the RD51 programme the characteristics of a new detector design, called THGEM, which is based on multi-layer arrangements of printed circuit board material, is investigated. The THGEMs combine the advantages for covering gains up to 10{sup 6} in electron multiplication at large detector areas and low material budget. Studies are performed by extending the design to a hybrid gas detector by adding a Micromega layer, which significantly improves the ion back flow ratio of the chamber. With the upgrade of the COMPASS experiment at CERN a MWPC plane of the RICH-1 detector will be replaced by installing THGEM chambers. This summarizes to 40k channels of electronic readout, including amplification, discrimination and time-to-digital conversion of the anode signals. Due to the expected hit rate of the detector we design a cost-efficient TDC, based on Artix7 FPGA technology, with time resolution below 100 ps and sufficient hit buffer depth. To cover the large readout area the data is transferred via optical fibres to a central readout system which is part of the GANDALF framework.

  10. Low resource FPGA-based Time to Digital Converter

    CERN Document Server

    Balla, A; Ciambrone, P; Gatta, M; Gonnella, F; Iafolla, L; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2...

  11. Cryogenic loss monitors with FPGA TDC signal processing

    CERN Document Server

    Warner, A

    2012-01-01

    Radiation hard helium gas ionization chambers capable of operating in vacuum at temperatures ranging from 5K to 350K have been designed, fabricated and tested and will be used inside the cryostats at Fermilab's Superconducting Radiofrequency beam test facility. The chamber vessels are made of stainless steel and all materials used including seals are known to be radiation hard and suitable for operation at 5K. The chambers are designed to measure radiation up to 30 kRad/hr with sensitivity of approximately 1.9 pA/(Rad/hr). The signal current is measured with a recycling integrator current-to-frequency converter to achieve a required measurement capability for low current and a wide dynamic range. A novel scheme of using an FPGA-based time-to-digital converter (TDC) to measure time intervals between pulses output from the recycling integrator is employed to ensure a fast beam loss response along with a current measurement resolution better than 10-bit. This paper will describe the results obtained and highligh...

  12. The FPGA Implementation of Short—Wave Channel Model

    Institute of Scientific and Technical Information of China (English)

    GANLiangcai; LIYuanyuan

    2003-01-01

    Based on the characteristic of timevariance,short-wave channel can be modeled as a real-time tors of fllter in frequency domain,the model can simulate short-wave channel exactly,such as delay spread,Doppler shift and Doppler spread.In the design,the bandwidth of short-wave channel model is 768kHz,and the frequency interval is 3kHz.A kind of Overlap-Discard algorithm based on the fast Fourier transform (FFT)is utilized to design the real-time FIR filter,and an architectural design structure based on Field Programmable Gate Arrays(FPGA)chip is adopted to implement 512-point FFT.The channel transfer function and the noise and interference function are periodically updated in real-time,which are stored in ROM in advance.The simulation result shows that the hardware implementation is simple and feasible and the wideband short-wave systems,such as frequency-hopping,direct sequence spread spectrum systems.

  13. Area Efficient Turbo Encoder for Wireless Applications on FPGA

    Directory of Open Access Journals (Sweden)

    Mansi Rastogi

    2014-03-01

    Full Text Available Error control is the major insistence in today’s wireless communication systems. In this era parallel concatenated convolutional codes known as turbo codes plays a crucial role. These codes have been chosen as error control approach for various wireless applications such as UMTS (Universal Mobile Telecommunication System,DVB (Digital Video Broadcasting etc. In this paper an area efficient turbo encoder (2, 1, 3 is proposed to suffice the elevated demand of miniaturization in future wireless communication. The proposed design is simulated using matlab and synthesized on Xilinx Virtex-2p (xc2vp30-ff896-5 FPGA. During simulation the proposed design is compared with the matlab model of RSC encoder. The performance of proposed Turbo encoder will be compared for FPGAs in terms of number of slices, number of slice Flip-flops and the number of registers. The Synthesis results show a 7% improvement in the utilized no. of slices and slice flip-flop. So an area efficient, cost effective Parallel Concatenated Convolutional Code Encoder has been proposed in this paper

  14. Functional verification of dynamically reconfigurable FPGA-based systems

    CERN Document Server

    Gong, Lingkan

    2015-01-01

    This book analyzes the challenges in verifying Dynamically Reconfigurable Systems (DRS) with respect to the user design and the physical implementation of such systems. The authors describe the use of a simulation-only layer to emulate the behavior of target FPGAs and accurately model the characteristic features of reconfiguration. Readers are enabled with this simulation-only layer to maintain verification productivity by abstracting away the physical details of the FPGA fabric.  Two implementations of the simulation-only layer are included: Extended ReChannel is a SystemC library that can be used to check DRS designs at a high level; ReSim is a library to support RTL simulation of a DRS reconfiguring both its logic and state. Through a number of case studies, the authors demonstrate how their approach integrates seamlessly with existing, mainstream DRS design flows and with well-established verification methodologies such as top-down modeling and coverage-driven verification. Provides researchers with an i...

  15. An FPGA computing demo core for space charge simulation

    Energy Technology Data Exchange (ETDEWEB)

    Wu, Jinyuan; Huang, Yifei; /Fermilab

    2009-01-01

    In accelerator physics, space charge simulation requires large amount of computing power. In a particle system, each calculation requires time/resource consuming operations such as multiplications, divisions, and square roots. Because of the flexibility of field programmable gate arrays (FPGAs), we implemented this task with efficient use of the available computing resources and completely eliminated non-calculating operations that are indispensable in regular micro-processors (e.g. instruction fetch, instruction decoding, etc.). We designed and tested a 16-bit demo core for computing Coulomb's force in an Altera Cyclone II FPGA device. To save resources, the inverse square-root cube operation in our design is computed using a memory look-up table addressed with nine to ten most significant non-zero bits. At 200 MHz internal clock, our demo core reaches a throughput of 200 M pairs/s/core, faster than a typical 2 GHz micro-processor by about a factor of 10. Temperature and power consumption of FPGAs were also lower than those of micro-processors. Fast and convenient, FPGAs can serve as alternatives to time-consuming micro-processors for space charge simulation.

  16. Evaluation of ATM Functioning Using VHDL and FPGA

    Directory of Open Access Journals (Sweden)

    Manali Dhar

    2015-06-01

    Full Text Available It has been almost four decades that banks and other financial organizations have been gradually computerised, in order to improve service and efficiency and to reduce cost. The birth of Electronic Fund Transfer and Automated Teller Machines has given rise to 24-hour banking and a greater variety of services for the customer. This method uses a computer to transfer debits and credits, with the help of electronic pulses, which are carried through wires either to a magnetic disk or tape. ATM (Automated Teller Machine has become an important part in our daily lives. People use ATM for various purposes such as money withdrawal, checking balance, changing password etc. Since it mainly deals with people's money, it has to be a secure system on which we can rely. We have taken a step towards increasing this security and integrity by trying to implement the functioning of an ATM using VLSI-based programming, HDL(Hardware Description Language.The conventional coding languages such as C,C++ are replaced by VHDL(Very High Speed Integrated Circuit Hardware Description Language so that the code cannot be easily hacked or changed. This article consists of an insight into the various functions that can be performed using an ATM, a brief description of the Coding and the obtained simulation results. It also consists of the implementation of the code using FPGA Kit (Spartan3; Model no.-XC 3S50.

  17. Implementation Of Path Length Control For RLG Using FPGA

    Directory of Open Access Journals (Sweden)

    Prasanthi.Pasula

    2012-02-01

    Full Text Available Ring Laser Gyro(RLG is used to sense angular information accurately and precisely.In a RLG,an optical ring is formed,and two laser beams are directed around the ring in opposite directions.When the beams are combined ,rotation of the ring appears as an interference shift in the combined beams.The amplitude of modulation of the light intensity is less .When RLG is operating at its peak, in comparison to when it is operating with pathlength which is either under or over the peak path length.It is difficult to detect,modulations at peak.The analog components are used to form a phase comparator.The voltage produced by a photo detector actuated by a small sample of light which is picked off by the laser beam.If two signals are in phase ,then the voltage to the PZT is increased,if it is out of phase ,it is decreased.The analog phase comparator and voltage feedback device suffers from the drawbacks of analog devices radiation softness bulk,weight, lack of tolerence.To overcome the above problem, path length control using FPGA is implemented.

  18. Implementation of Wireless Communications Systems on FPGA-Based Platforms

    Directory of Open Access Journals (Sweden)

    Voros NS

    2007-01-01

    Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

  19. Implementation of Wireless Communications Systems on FPGA-Based Platforms

    Directory of Open Access Journals (Sweden)

    N. S. Voros

    2007-02-01

    Full Text Available Wireless communications are a very popular application domain. The efficient implementation of their components (access points and mobile terminals/network interface cards in terms of hardware cost and design time is of great importance. This paper describes the design and implementation of the HIPERLAN/2 WLAN system on a platform including general purpose microprocessors and FPGAs. Detailed implementation results (performance, code size, and FPGA resources utilization are presented. The main goal of the design case presented is to provide insight into the design aspects of a complex system based on FPGAs. The results prove that an implementation based on microprocessors and FPGAs is adequate for the access point part of the system where the expected volumes are rather small. At the same time, such an implementation serves as a prototyping of an integrated implementation (System-on-Chip, which is necessary for the mobile terminals of a HIPERLAN/2 system. Finally, firmware upgrades were developed allowing the implementation of an outdoor wireless communication system on the same platform.

  20. The design and application of multi-channel PWM pulse generator based on OMAPL138+FPGA%基于 OMAPL138+FPGA 的多路 PWM 发生器设计及应用

    Institute of Scientific and Technical Information of China (English)

    窦亚力; 乔海强; 钱帆; 李龙光; 李子久

    2016-01-01

    In order to meet the inverter of trigger requirements applied to the power electronic , this paper primarily presents a novel method of using OMAPL 138 and FPGA to implement multi-channel PWM pulse generator with three-level PWM inverters .The pulse generator receives the PWM pattern parameters and setting parameters from OMA-PL138 processor through a built-in parallel interface , and produces the three-phase PWM driven signals by FPGA without the OMAPL138 intervention .The hardware architecture , basic principles , implementation method of the pulse generator described in this paper is verified by simulation and experiment .Three phase PWM generators have the fea-tures of simplifying circuit-design, improving reliability of system and guaranteeing concurrent triggering of power de-vices.%为了满足一种新能源发电领域的电力电子变换装置上逆变器触发的要求,研制了利用OMAPL138和FP-GA实现的多路PWM脉冲发生器。该脉冲发生器利用接口单元接收OMAPL138写入的PWM脉冲占空比和设置参数等数据,利用FPGA产生PWM波形,达到其工作不受OMAPL138影响的效果。同时介绍了脉冲发生器的硬件架构、基本原理和实现方法,并通过仿真和实验得到验证。该PWM发生器既简化了电路的设计,提高了系统的可靠性,又可保证逆变器功率元件触发的同步。

  1. OpenACC to FPGA: A Framework for Directive-based High-Performance Reconfigurable Computing

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Seyong [ORNL; Kim, Jungwon [ORNL; Vetter, Jeffrey S [ORNL

    2016-01-01

    This paper presents a directive-based, high-level programming framework for high-performance reconfigurable computing. It takes a standard, portable OpenACC C program as input and generates a hardware configuration file for execution on FPGAs. We implemented this prototype system using our open-source OpenARC compiler; it performs source-to-source translation and optimization of the input OpenACC program into an OpenCL code, which is further compiled into a FPGA program by the backend Altera Offline OpenCL compiler. Internally, the design of OpenARC uses a high- level intermediate representation that separates concerns of program representation from underlying architectures, which facilitates portability of OpenARC. In fact, this design allowed us to create the OpenACC-to-FPGA translation framework with minimal extensions to our existing system. In addition, we show that our proposed FPGA-specific compiler optimizations and novel OpenACC pragma extensions assist the compiler in generating more efficient FPGA hardware configuration files. Our empirical evaluation on an Altera Stratix V FPGA with eight OpenACC benchmarks demonstrate the benefits of our strategy. To demonstrate the portability of OpenARC, we show results for the same benchmarks executing on other heterogeneous platforms, including NVIDIA GPUs, AMD GPUs, and Intel Xeon Phis. This initial evidence helps support the goal of using a directive-based, high-level programming strategy for performance portability across heterogeneous HPC architectures.

  2. Design and Implementation of Novel Smart Battery Management System for FPGA Based Portable Electronic Devices

    Directory of Open Access Journals (Sweden)

    Fangrong Xue

    2017-02-01

    Full Text Available This paper presents the analysis and design of a smart battery management system for Field Programmable Gate Array (FPGA based portable electronic devices. It is a novel concept of incorporating the functionality of a smart battery management system into the FPGA used by portable electronic devices, which provides the following advantages. (1 It lowers cost since the conventional commercial independent battery management circuit can be eliminated; (2 It offers more flexibility because FPGA based battery management algorithms can be specifically designed for different battery chemistries of different devices and can provide the flexibility of algorithms and functionalities updating as well. Smart battery management system concepts include four aspects: (1 smart charging; (2 battery balancing; (3 smart discharging; and (4 safety operating. One novel charging algorithm, which combines the merits of multistage charging and pulse charging, is proposed to charge a Li-ion battery pack smartly. A Proportional Integral (PI control method is introduced to achieve the current control of charging circuit with considerable close loop stability. Simulation results from the PSIM 9.0.4 software package and experimental results from the prototype built in the lab are demonstrated to verify the effectiveness of smart charging. The realizations of battery balancing, smart discharging, and safety operating are also briefly described by taking advantage of the proposed FPGA based smart battery management system topology, which verify the feasibility of the proposed FPGA based smart battery management system for portable electronic devices.

  3. OPENCORE NMR: open-source core modules for implementing an integrated FPGA-based NMR spectrometer.

    Science.gov (United States)

    Takeda, Kazuyuki

    2008-06-01

    A tool kit for implementing an integrated FPGA-based NMR spectrometer [K. Takeda, A highly integrated FPGA-based nuclear magnetic resonance spectrometer, Rev. Sci. Instrum. 78 (2007) 033103], referred to as the OPENCORE NMR spectrometer, is open to public. The system is composed of an FPGA chip and several peripheral boards for USB communication, direct-digital synthesis (DDS), RF transmission, signal acquisition, etc. Inside the FPGA chip have been implemented a number of digital modules including three pulse programmers, the digital part of DDS, a digital quadrature demodulator, dual digital low-pass filters, and a PC interface. These FPGA core modules are written in VHDL, and their source codes are available on our website. This work aims at providing sufficient information with which one can, given some facility in circuit board manufacturing, reproduce the OPENCORE NMR spectrometer presented here. Also, the users are encouraged to modify the design of spectrometer according to their own specific needs. A home-built NMR spectrometer can serve complementary roles to a sophisticated commercial spectrometer, should one comes across such new ideas that require heavy modification to hardware inside the spectrometer. This work can lower the barrier of building a handmade NMR spectrometer in the laboratory, and promote novel and exciting NMR experiments.

  4. Multi-Objective Memetic Algorithm for FPGA Placement Using Parallel Genetic Annealing

    Directory of Open Access Journals (Sweden)

    Praveen T.

    2016-04-01

    Full Text Available Due to advancement in reconfigurable computing, Field Programmable Gate Array (FPGA has gained significance due to its low cost and fast prototyping. Parallelism, specialization, and hardware level adaptation, are the key features of reconfigurable computing. FPGA is a programmable chip that can be configured or reconfigured by the designer, to implement any digital circuit. One major challenge in FPGA design is the Placement problem. In this placement phase, the logic functions are assigned to specific cells of the circuit. The quality of the placement of the logic blocks determines the overall performance of the logic implemented in the circuits. The Placement of FPGA is a Multi-Objective Optimization problem that primarily involves minimization of three or more objective functions. In this paper, we propose a novel strategy to solve the FPGA placement problem using Non-dominated Sorting Genetic Algorithm (NSGA-II and Simulated Annealing technique. Experiments were conducted in Multicore Processors and metrics such as CPU time were measured to test the efficiency of the proposed algorithm. From the experimental results, it is evident that the proposed algorithm reduces the CPU consumption time to an average of 15% as compared to the Genetic Algorithm, 12% as compared to the Simulated Annealing, and approximately 6% as compared to the Genetic Annealing algorithm.

  5. Constructivist Multi-Access Lab Approach in Teaching FPGA Systems Design with LabVIEW

    Directory of Open Access Journals (Sweden)

    Walid Balid

    2013-05-01

    Full Text Available Embedded systems play vital role in modern applications [1]. They can be found in autos, washing machines, electrical appliances and even in toys. FPGAs are the most recent computing technology that is used in embedded systems. There is an increasing demand on FPGA based embedded systems, in particular, for applications that require rapid time responses. Engineering education curricula needs to respond to the increasing industrial demand of using FPGAs by introducing new syllabus for teaching and learning this subject. This paper describes the development of new course material for teaching FPGA-based embedded systems design by using ‘G’ Programming Language of LabVIEW. A general overview of FPGA role in engineering education is provided. A survey of available Hardware Programming Languages for FPGAs is presented. A survey about LabVIEW utilization in engineering education is investigated; this is followed by a motivation section of why to use LabVIEW graphical programming in teaching and its capabilities. Then, a section of choosing a suitable kit for the course is laid down. Later, constructivist closed-loop model the FPGA course has been proposed in accordance with [2-4; 80,86,89,92]. The paper is proposing a pedagogical framework for FPGA teaching; pedagogical evaluation will be conducted in future studies. The complete study has been done at the Faculty of Electrical and Electronic Engineering, Aleppo University.

  6. Design and implementation of an FPGA-based timing pulse programmer for pulsed-electron paramagnetic resonance applications.

    Science.gov (United States)

    Sun, Li; Savory, Joshua J; Warncke, Kurt

    2013-08-01

    The design, construction and implementation of a field-programmable gate array (FPGA) -based pulse programmer for pulsed-electron paramagnetic resonance (EPR) experiments is described. The FPGA pulse programmer offers advantages in design flexibility and cost over previous pulse programmers, that are based on commercial digital delay generators, logic pattern generators, and application-specific integrated circuit (ASIC) designs. The FPGA pulse progammer features a novel transition-based algorithm and command protocol, that is optimized for the timing structure required for most pulsed magnetic resonance experiments. The algorithm was implemented by using a Spartan-6 FPGA (Xilinx), which provides an easily accessible and cost effective solution for FPGA interfacing. An auxiliary board was designed for the FPGA-instrument interface, which buffers the FPGA outputs for increased power consumption and capacitive load requirements. Device specifications include: Nanosecond pulse formation (transition edge rise/fall times, ≤3 ns), low jitter (≤150 ps), large number of channels (16 implemented; 48 available), and long pulse duration (no limit). The hardware and software for the device were designed for facile reconfiguration to match user experimental requirements and constraints. Operation of the device is demonstrated and benchmarked by applications to 1-D electron spin echo envelope modulation (ESEEM) and 2-D hyperfine sublevel correlation (HYSCORE) experiments. The FPGA approach is transferrable to applications in nuclear magnetic resonance (NMR; magnetic resonance imaging, MRI), and to pulse perturbation and detection bandwidths in spectroscopies up through the optical range.

  7. Leakage Power Reduction with Various IO Standards and Dynamic Voltage Scaling in Vedic Multiplier on Virtex-6 FPGA

    DEFF Research Database (Denmark)

    Pandey, Bishwajeet; Rehman, M. Atiqur; Hussain, Dil muhammed Akbar

    2016-01-01

    , SSTL and LVCMOS family respectively. Device static power and design static power are two types of static power dissipation. Device static power is also known as Leakage power when the device is on but not configured. Design static power is power dissipation when bit file of design is downloaded on FPGA......nm FPGA....

  8. Clock Gating Based Energy Efficient and Thermal Aware Design of Latin Unicode Reader for Natural Language Processing on FPGA

    DEFF Research Database (Denmark)

    Singh, Ritu; Kalia, Kartik; Minver, M. H.

    2016-01-01

    Abstract-In this paper we have aimed to design an energy efficient and thermally aware Latin Unicode Reader. Our design is based on 28nm FPGA (Kintex-7) and 40nm FPGA (Artix-7). In order to test the portability of our design, we are operating our design with respective frequency of different mobi...

  9. Evaluation of the OpenCL AES Kernel using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    The OpenCL standard is an open programming model for accelerating algorithms on heterogeneous computing system. OpenCL extends the C-based programming language for developing portable codes on different platforms such as CPU, Graphics processing units (GPUs), Digital Signal Processors (DSPs) and Field Programmable Gate Arrays (FPGAs). The Intel FPGA SDK for OpenCL is a suite of tools that allows developers to abstract away the complex FPGA-based development flow for a high-level software development flow. Users can focus on the design of hardware-accelerated kernel functions in OpenCL and then direct the tools to generate the low-level FPGA implementations. The approach makes the FPGA-based development more accessible to software users as the needs for hybrid computing using CPUs and FPGAs are increasing. It can also significantly reduce the hardware development time as users can evaluate different ideas with high-level language without deep FPGA domain knowledge. In this report, we evaluate the performance of the kernel using the Intel FPGA SDK for OpenCL and Nallatech 385A FPGA board. Compared to the M506 module, the board provides more hardware resources for a larger design exploration space. The kernel performance is measured with the compute kernel throughput, an upper bound to the FPGA throughput. The report presents the experimental results in details. The Appendix lists the kernel source code.

  10. Evaluation of the Single-precision Floatingpoint Vector Add Kernel Using the Intel FPGA SDK for OpenCL

    Energy Technology Data Exchange (ETDEWEB)

    Jin, Zheming [Argonne National Lab. (ANL), Argonne, IL (United States); Yoshii, Kazutomo [Argonne National Lab. (ANL), Argonne, IL (United States); Finkel, Hal [Argonne National Lab. (ANL), Argonne, IL (United States); Cappello, Franck [Argonne National Lab. (ANL), Argonne, IL (United States)

    2017-04-20

    Open Computing Language (OpenCL) is a high-level language that enables software programmers to explore Field Programmable Gate Arrays (FPGAs) for application acceleration. The Intel FPGA software development kit (SDK) for OpenCL allows a user to specify applications at a high level and explore the performance of low-level hardware acceleration. In this report, we present the FPGA performance and power consumption results of the single-precision floating-point vector add OpenCL kernel using the Intel FPGA SDK for OpenCL on the Nallatech 385A FPGA board. The board features an Arria 10 FPGA. We evaluate the FPGA implementations using the compute unit duplication and kernel vectorization optimization techniques. On the Nallatech 385A FPGA board, the maximum compute kernel bandwidth we achieve is 25.8 GB/s, approximately 76% of the peak memory bandwidth. The power consumption of the FPGA device when running the kernels ranges from 29W to 42W.

  11. Direct Measurement of Power Dissipated by Monte Carlo Simulations on CPU and FPGA Platforms

    DEFF Research Database (Denmark)

    Albicocco, Pietro; Papini, Davide; Nannarelli, Alberto

    In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which is a popu......In this technical report, we describe how power dissipation measurements on different computing platforms (a desktop computer and an FPGA board) are performed by using a Hall effectbased current sensor. The chosen application is a Monte Carlo simulation for European option pricing which...... is a popular algorithm used in financial computations. The Hall effect probe measurements complement the measurements performed on the core of the FPGA by a built-in Xilinx power monitoring system....

  12. An optimized ultrasound digital beamformer with dynamic focusing implemented on FPGA.

    Science.gov (United States)

    Almekkawy, Mohamed; Xu, Jingwei; Chirala, Mohan

    2014-01-01

    We present a resource-optimized dynamic digital beamformer for an ultrasound system based on a field-programmable gate array (FPGA). A comprehensive 64-channel receive beamformer with full dynamic focusing is embedded in the Altera Arria V FPGA chip. To improve spatial and contrast resolution, full dynamic beamforming is implemented by a novel method with resource optimization. This was conceived using the implementation of the delay summation through a bulk (coarse) delay and fractional (fine) delay. The sampling frequency is 40 MHz and the beamformer includes a 240 MHz polyphase filter that enhances the temporal resolution of the system while relaxing the Analog-to-Digital converter (ADC) bandwidth requirement. The results indicate that our 64-channel dynamic beamformer architecture is amenable for a low power FPGA-based implementation in a portable ultrasound system.

  13. A Real-Time System for Lane Detection Based on FPGA and DSP

    Science.gov (United States)

    Xiao, Jing; Li, Shutao; Sun, Bin

    2016-12-01

    This paper presents a real-time lane detection system including edge detection and improved Hough Transform based lane detection algorithm and its hardware implementation with field programmable gate array (FPGA) and digital signal processor (DSP). Firstly, gradient amplitude and direction information are combined to extract lane edge information. Then, the information is used to determine the region of interest. Finally, the lanes are extracted by using improved Hough Transform. The image processing module of the system consists of FPGA and DSP. Particularly, the algorithms implemented in FPGA are working in pipeline and processing in parallel so that the system can run in real-time. In addition, DSP realizes lane line extraction and display function with an improved Hough Transform. The experimental results show that the proposed system is able to detect lanes under different road situations efficiently and effectively.

  14. Asynchronous cellular automaton-based neuron: theoretical analysis and on-FPGA learning.

    Science.gov (United States)

    Matsubara, Takashi; Torikai, Hiroyuki

    2013-05-01

    A generalized asynchronous cellular automaton-based neuron model is a special kind of cellular automaton that is designed to mimic the nonlinear dynamics of neurons. The model can be implemented as an asynchronous sequential logic circuit and its control parameter is the pattern of wires among the circuit elements that is adjustable after implementation in a field-programmable gate array (FPGA) device. In this paper, a novel theoretical analysis method for the model is presented. Using this method, stabilities of neuron-like orbits and occurrence mechanisms of neuron-like bifurcations of the model are clarified theoretically. Also, a novel learning algorithm for the model is presented. An equivalent experiment shows that an FPGA-implemented learning algorithm enables an FPGA-implemented model to automatically reproduce typical nonlinear responses and occurrence mechanisms observed in biological and model neurons.

  15. FPGA implementation of hardware processing modules as coprocessors in brain-machine interfaces.

    Science.gov (United States)

    Wang, Dong; Hao, Yaoyao; Zhu, Xiaoping; Zhao, Ting; Wang, Yiwen; Chen, Yaowu; Chen, Weidong; Zheng, Xiaoxiang

    2011-01-01

    Real-time computation, portability and flexibility are crucial for practical brain-machine interface (BMI) applications. In this work, we proposed Hardware Processing Modules (HPMs) as a method for accelerating BMI computation. Two HPMs have been developed. One is the field-programmable gate array (FPGA) implementation of spike sorting based on probabilistic neural network (PNN), and the other is the FPGA implementation of neural ensemble decoding based on Kalman filter (KF). These two modules were configured under the same framework and tested with real data from motor cortex recording in rats performing a lever-pressing task for water rewards. Due to the parallelism feature of FPGA, the computation time was reduced by several dozen times, while the results are almost the same as those from Matlab implementations. Such HPMs provide a high performance coprocessor for neural signal computation.

  16. An FPGA-based ultrasound imaging system using capacitive micromachined ultrasonic transducers.

    Science.gov (United States)

    Wong, Lawrence L P; Chen, Albert I; Logan, Andrew S; Yeow, John T W

    2012-07-01

    We report the design and experimental results of a field-programmable gate array (FPGA)-based real-time ultrasound imaging system that uses a 16-element phased-array capacitive micromachined ultrasonic transducer fabricated using a fusion bonding process. The imaging system consists of the transducer, discrete analog components situated on a custom-made circuit board, the FPGA, and a monitor. The FPGA program consists of five functional blocks: a main counter, transmit and receive beamformer, receive signal pre-processing, envelope detection, and display. No dedicated digital signal processor or personal computer is required for the imaging system. An experiment is carried out to obtain the sector B-scan of a 4-wire target. The ultrasound imaging system demonstrates the possibility of an integrated system-in-a-package solution.

  17. FPGA Implementation of Blue Whale Calls Classifier Using High-Level Programming Tool

    Directory of Open Access Journals (Sweden)

    Mohammed Bahoura

    2016-02-01

    Full Text Available In this paper, we propose a hardware-based architecture for automatic blue whale calls classification based on short-time Fourier transform and multilayer perceptron neural network. The proposed architecture is implemented on field programmable gate array (FPGA using Xilinx System Generator (XSG and the Nexys-4 Artix-7 FPGA board. This high-level programming tool allows us to design, simulate and execute the compiled design in Matlab/Simulink environment quickly and easily. Intermediate signals obtained at various steps of the proposed system are presented for typical blue whale calls. Classification performances based on the fixed-point XSG/FPGA implementation are compared to those obtained by the floating-point Matlab simulation, using a representative database of the blue whale calls.

  18. Improved Approach for Utilization of FPGA Technology into DAQ, DSP, and Computing Applications

    Energy Technology Data Exchange (ETDEWEB)

    Isenhower, Larry Donald

    2009-01-28

    Innovation Partners proposed and successfully demonstrated in this SBIR Phase I grant a software/hardware co-design approach to reduce both the difficulty and time to implement Field Programmable Gate Array (FPGA) solutions to data acquisition and specialized computational applications. FPGAs can require excessive time for programming and require specialized knowledge that will be greatly reduced by the company's solution. Not only are FPGAs ideal for DAQ and embedded solutions, they can also be the best solution to specialized signal processing to replace Digital Signal Processors (DSPs). By allowing FPGA programming to be done in C with the equivalent of a simple compilation, algorithm changes and improvements can be implemented decreasing the life-cycle costs and allow subsitution of new FPGA designs staying above the technological details.

  19. Implementation of total focusing method for phased array ultrasonic imaging on FPGA

    Science.gov (United States)

    Guo, JianQiang; Li, Xi; Gao, Xiaorong; Wang, Zeyong; Zhao, Quanke

    2015-02-01

    This paper describes a multi-FPGA imaging system dedicated for the real-time imaging using the Total Focusing Method (TFM) and Full Matrix Capture (FMC). The system was entirely described using Verilog HDL language and implemented on Altera Stratix IV GX FPGA development board. The whole algorithm process is to: establish a coordinate system of image and divide it into grids; calculate the complete acoustic distance of array element between transmitting array element and receiving array element, and transform it into index value; then index the sound pressure values from ROM and superimpose sound pressure values to get pixel value of one focus point; and calculate the pixel values of all focus points to get the final imaging. The imaging result shows that this algorithm has high SNR of defect imaging. And FPGA with parallel processing capability can provide high speed performance, so this system can provide the imaging interface, with complete function and good performance.

  20. ICE: a scalable, low-cost FPGA-based telescope signal processing and networking system

    CERN Document Server

    Bandura, K; Cliche, J F; de Haan, T; Dobbs, M A; Gilbert, A J; Griffin, S; Hsyu, G; Ittah, D; Parra, J Mena; Montgomery, J; Pinsonneault-Marotte, T; Siegel, S; Smecher, G; Tang, Q Y; Vanderlinde, K; Whitehorn, N

    2016-01-01

    We present an overview of the 'ICE' hardware and software framework that implements large arrays of interconnected FPGA-based data acquisition, signal processing and networking nodes economically. The system was conceived for application to radio, millimeter and sub-millimeter telescope readout systems that have requirements beyond typical off-the-shelf processing systems, such as careful control of interference signals produced by the digital electronics, and clocking of all elements in the system from a single precise observatory-derived oscillator. A new generation of telescopes operating at these frequency bands and designed with a vastly increased emphasis on digital signal processing to support their detector multiplexing technology or high-bandwidth correlators---data rates exceeding a terabyte per second---are becoming common. The ICE system is built around a custom FPGA motherboard that makes use of an Xilinx Kintex-7 FPGA and ARM-based co-processor. The system is specialized for specific application...

  1. RADIOMETRIC CALIBRATION OF MARS HiRISE HIGH RESOLUTION IMAGERY BASED ON FPGA

    Directory of Open Access Journals (Sweden)

    Y. Hou

    2016-06-01

    Full Text Available Due to the large data amount of HiRISE imagery, traditional radiometric calibration method is not able to meet the fast processing requirements. To solve this problem, a radiometric calibration system of HiRISE imagery based on field program gate array (FPGA is designed. The montage gap between two channels caused by gray inconsistency is removed through histogram matching. The calibration system is composed of FPGA and DSP, which makes full use of the parallel processing ability of FPGA and fast computation as well as flexible control characteristic of DSP. Experimental results show that the designed system consumes less hardware resources and the real-time processing ability of radiometric calibration of HiRISE imagery is improved.

  2. A Novel Architecture for Real Time Implementation of Edge Detectors on FPGA

    Directory of Open Access Journals (Sweden)

    Sudeep K C

    2011-01-01

    Full Text Available With the introduction of reconfigurable platform such as Field Programmable Gate Arrays (FPGA and advent of new high level tools to configure them, image processing on FPGA has emerged as a practical solutions for most of computer vision and image processing problems. This paper briefly explains the implementation of several edge detection algorithms like Sobel, Prewitt, Robert and Compass edge detectors on FPGA and makes a comparative study of their performance. The design utilizes powerful design tool System Generator (SysGen and Embedded Development Kit (EDK for hardware-software codesign and integrates the edge detection hardware as a peripheral to the Microblaze 32 bit soft RISC processor with an input from a CMOS camera and output to a DVI display and verified the results video in real time.

  3. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    Millar James

    2006-01-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  4. FPGA-based prototyping of IEEE 802.11a base band processor

    Directory of Open Access Journals (Sweden)

    Dramićanin Dejan M.

    2004-01-01

    Full Text Available In technical literature and especially in domestic, predominant way to examine performance of 802.11a-based systems are experiments in simulations. In this paper, we present FPGA based 802.11a prototype, which gave us a possibility to gain closer insight into the problems of OFDM system implementation. A specific design of base band modem physical layer is discussed, along with the presentation of the FPGA prototyping platform on which it was developed. Prototype is implemented on the latest generation of FPGA chips, using state-of-the-art tools for DSP development. Custom made development environment, and design flow optimized for rapid prototyping of software defined radios, are also presented in the paper.

  5. FPGA-Based Communications Receivers for Smart Antenna Array Embedded Systems

    Directory of Open Access Journals (Sweden)

    James Millar

    2006-10-01

    Full Text Available Field-programmable gate arrays (FPGAs are drawing ever increasing interest from designers of embedded wireless communications systems. They outpace digital signal processors (DSPs, through hardware execution of a wide range of parallelizable communications transceiver algorithms, at a fraction of the design and implementation effort and cost required for application-specific integrated circuits (ASICs. In our study, we employ an Altera Stratix FPGA development board, along with the DSP Builder software tool which acts as a high-level interface to the powerful Quartus II environment. We compare single- and multibranch FPGA-based receiver designs in terms of error rate performance and power consumption. We exploit FPGA operational flexibility and algorithm parallelism to design eigenmode-monitoring receivers that can adapt to variations in wireless channel statistics, for high-performing, inexpensive, smart antenna array embedded systems.

  6. Interfacing the Analog Camera with FPGA Board for Real-time Video Acquisition

    Directory of Open Access Journals (Sweden)

    Sanjay Singh

    2014-03-01

    Full Text Available Advances in FPGA technology have dramatically increased the use of FPGAs for computer vision applications. The primary task for development of such FPGAs based systems is the interfacing of the analog camera with FPGA board. This paper describes the design and implementation of camera interface module required for connecting analog camera with Xilinx ML510 (Virtex–5 FXT FPGA board having no video input port. Digilent VDEC1 video daughter card is used for digitizing the analog video into digital form. The necessary control logics for video acquisition and video display are designed using VHDL and Verilog, simulated in ModelSim, and synthesized using Xilinx ISE 12.1. Designed and implemented interfaces provide the real-time video acquisition and display.

  7. Hardware Implementation of TDES Crypto System with On Chip Verification in FPGA

    CERN Document Server

    Ghosal, Prasun; Biswas, Manish

    2010-01-01

    Security issues are playing dominant role in today's high speed communication systems. A fast and compact FPGA based implementation of the Data Encryption Standard (DES) and Triple DES algorithm is presented in this paper that is widely used in cryptography for securing the Internet traffic in modern day communication systems. The design of the digital cryptographic circuit was implemented in a Vertex 5 series (XCVLX5110T) target device with the use of VHDL as the hardware description language. In order to confirm the expected behavior of these algorithms, the proposed design was extensively simulated, synthesized for different FPGA devices both in Spartan and Virtex series from Xilinx viz. Spartan 3, Spartan 3AN, Virtex 5, Virtex E device families. The novelty and contribution of this work is in three folds: (i) Extensive simulation and synthesis of the proposed design targeted for various FPGA devices, (ii) Complete hardware implementation of encryption and decryption algorithms onto Virtex 5 series device ...

  8. Development of fuzzy control of a fuel cell generation system using FPGA

    Institute of Scientific and Technical Information of China (English)

    杨帆; 朱新坚; 李浩

    2006-01-01

    A fuzzy controller based on improved Generalized-Membership-Function(GMF) algorithm for a fuel cell generation system was introduced. Under the demands on control in application of the converter, a Field Programmable Gate Array (FPGA) realization method to manage the power flow was given. This control system based on the proposed modified GMF was proved to be a universal approximation system in theory. The fuzzy control technique was combined with Eletronic Design Automatic(EDA)technique and a paralleling fuzzy controller was implemented in FPGA. Paralleling fuzzy controller based on improved GMF algorithm was implemented on a Cyclone FPGA. The result of simulation based on QuartusⅡ confirmed the validity of the proposed method.

  9. FPGA Implementation of Secure Force (64-Bit Low Complexity Encryption Algorithm

    Directory of Open Access Journals (Sweden)

    Shujaat Khan

    2015-11-01

    Full Text Available Field-Programmable Gate Arrays (FPGAs have turned out to be a well-liked target for implementing cryptographic block ciphers, a well-designed FPGA solution can combine some of the algorithmic flexibility and cost efficiency of an equivalent software implementation with throughputs that are comparable to custom ASIC designs. The recently proposed Secure Force (SF shows good results in terms of resource utilization compared to older ciphers. SF appears as a promising choice for power and resource constrained secure systems and is well suited to an FPGA implementation. In this paper we explore the design decisions that lead to area/delay tradeoffs in a full loop-unroll implementation of SF-64 on FPGA. This work provides hardware characteristics of SF along with implementation results that are optimal in terms of throughput, latency, power utilization and area efficiency.

  10. High Accuracy Speed-fed Grating Angular Acceleration Measurement System Based on FPGA

    Directory of Open Access Journals (Sweden)

    Hao Zhao

    2012-09-01

    Full Text Available Shaft angular acceleration is one of the most important parameter of rotary machines, the error of angular acceleration increased when the shaft speed up. For this problem, a new high accuracy angular acceleration measurement system is presented, the principle of measurement is self-regulating the period of speed sampling signal according to the proportion of the shaft speed up. This measurement system combined FPGA and SCM, the speed of shaft is received by the timer of SCM responding the interrupts of FPGA, and then set the parameter of frequency divider in FPGA, so as to make the period of speed sampling consistent with the proportion of the speed up. This measurement system could overcome the error when system speed up according to the experiment.

  11. Robotic Partial Nephrectomy Using Robotic Bulldog Clamps

    OpenAIRE

    2011-01-01

    Background and Objectives: The need for a skilled assistant to perform hilar clamping during robotic partial nephrectomy is a potential limitation of the technique. We describe our experience using robotic bulldog clamps applied by the console surgeon for hilar clamping. Methods: A total of 60 consecutive patients underwent robotic partial nephrectomy, 30 using laparoscopic bulldog clamps applied by the assistant and 30 using robotic bulldog clamps applied with the robotic Prograsp instrument...

  12. Software-based high-level synthesis design of FPGA beamformers for synthetic aperture imaging.

    Science.gov (United States)

    Amaro, Joao; Yiu, Billy Y S; Falcao, Gabriel; Gomes, Marco A C; Yu, Alfred C H

    2015-05-01

    Field-programmable gate arrays (FPGAs) can potentially be configured as beamforming platforms for ultrasound imaging, but a long design time and skilled expertise in hardware programming are typically required. In this article, we present a novel approach to the efficient design of FPGA beamformers for synthetic aperture (SA) imaging via the use of software-based high-level synthesis techniques. Software kernels (coded in OpenCL) were first developed to stage-wise handle SA beamforming operations, and their corresponding FPGA logic circuitry was emulated through a high-level synthesis framework. After design space analysis, the fine-tuned OpenCL kernels were compiled into register transfer level descriptions to configure an FPGA as a beamformer module. The processing performance of this beamformer was assessed through a series of offline emulation experiments that sought to derive beamformed images from SA channel-domain raw data (40-MHz sampling rate, 12 bit resolution). With 128 channels, our FPGA-based SA beamformer can achieve 41 frames per second (fps) processing throughput (3.44 × 10(8) pixels per second for frame size of 256 × 256 pixels) at 31.5 W power consumption (1.30 fps/W power efficiency). It utilized 86.9% of the FPGA fabric and operated at a 196.5 MHz clock frequency (after optimization). Based on these findings, we anticipate that FPGA and high-level synthesis can together foster rapid prototyping of real-time ultrasound processor modules at low power consumption budgets.

  13. FPGA-Based Reconfigurable Processor for Ultrafast Interlaced Ultrasound and Photoacoustic Imaging

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2016-01-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models. PMID:22828830

  14. FPGA-based reconfigurable processor for ultrafast interlaced ultrasound and photoacoustic imaging.

    Science.gov (United States)

    Alqasemi, Umar; Li, Hai; Aguirre, Andrés; Zhu, Quing

    2012-07-01

    In this paper, we report, to the best of our knowledge, a unique field-programmable gate array (FPGA)-based reconfigurable processor for real-time interlaced co-registered ultrasound and photoacoustic imaging and its application in imaging tumor dynamic response. The FPGA is used to control, acquire, store, delay-and-sum, and transfer the data for real-time co-registered imaging. The FPGA controls the ultrasound transmission and ultrasound and photoacoustic data acquisition process of a customized 16-channel module that contains all of the necessary analog and digital circuits. The 16-channel module is one of multiple modules plugged into a motherboard; their beamformed outputs are made available for a digital signal processor (DSP) to access using an external memory interface (EMIF). The FPGA performs a key role through ultrafast reconfiguration and adaptation of its structure to allow real-time switching between the two imaging modes, including transmission control, laser synchronization, internal memory structure, beamforming, and EMIF structure and memory size. It performs another role by parallel accessing of internal memories and multi-thread processing to reduce the transfer of data and the processing load on the DSP. Furthermore, because the laser will be pulsing even during ultrasound pulse-echo acquisition, the FPGA ensures that the laser pulses are far enough from the pulse-echo acquisitions by appropriate time-division multiplexing (TDM). A co-registered ultrasound and photoacoustic imaging system consisting of four FPGA modules (64-channels) is constructed, and its performance is demonstrated using phantom targets and in vivo mouse tumor models.

  15. Servo motor control application research based on Xilinx FPGA system generator%Xilinx FPGA system generator 在伺服电机控制中的应用

    Institute of Scientific and Technical Information of China (English)

    程龙; 王卫兵; 王挺峰; 陈娟; 郭劲

    2015-01-01

    In order to avoid the FPGA language HDL code cumbersome,in this paper,by using Simulink integrated toolkit Xilinx FPGA unique System Generator module series,around three servo motor control application has carried on the simulation and experimental research.First of all,according to three kinds of servo motor control PWM signal waveform,the Simulink block diagram was established based on System Generator;Second,the Simulink simulation results correctly generated on the basis of HDL code;Then,using the ISE ModelSim simulation supporting software of HDL code test;Finally,on the basis of the ModelSim simulation results right code to load the FPGA hardware,and by using the ChipScope Pro PWM signal test.Accordance with the experimental results and simulation results,show that the method is simple,has a certain practical application value.%为了避免编写 FPGA 语言 HDL 代码的烦琐性,借助于 Simulink 集成工具箱中 Xilinx 系列 FPGA 独有的System Generator 模块,围绕3种伺服电机控制应用进行了仿真和实验研究。首先,根据3种伺服电机控制所需PWM 信号波形,利用 System Generator 建立 Simulink 仿真框图;其次,在 Simulink 仿真结果正确的基础上生成 HDL代码;然后,利用 ISE 的仿真配套软件 ModelSim 对 HDL 代码仿真测试;最后,在 ModelSim 仿真结果正确的基础上将代码载入 FPGA 硬件,并利用 ChipScope Pro 对 PWM 信号进行实验测试。实验结果与仿真结果的吻合,表明此方法简单易行,具有一定的实际应用价值。

  16. Design exploration and verification platform, based on high-level modeling and FPGA prototyping, for fast and flexible digital communication in physics experiments

    Science.gov (United States)

    Magazzù, G.; Borgese, G.; Costantino, N.; Fanucci, L.; Incandela, J.; Saponara, S.

    2013-02-01

    In many research fields as high energy physics (HEP), astrophysics, nuclear medicine or space engineering with harsh operating conditions, the use of fast and flexible digital communication protocols is becoming more and more important. The possibility to have a smart and tested top-down design flow for the design of a new protocol for control/readout of front-end electronics is very useful. To this aim, and to reduce development time, costs and risks, this paper describes an innovative design/verification flow applied as example case study to a new communication protocol called FF-LYNX. After the description of the main FF-LYNX features, the paper presents: the definition of a parametric SystemC-based Integrated Simulation Environment (ISE) for high-level protocol definition and validation; the set up of figure of merits to drive the design space exploration; the use of ISE for early analysis of the achievable performances when adopting the new communication protocol and its interfaces for a new (or upgraded) physics experiment; the design of VHDL IP cores for the TX and RX protocol interfaces; their implementation on a FPGA-based emulator for functional verification and finally the modification of the FPGA-based emulator for testing the ASIC chipset which implements the rad-tolerant protocol interfaces. For every step, significant results will be shown to underline the usefulness of this design and verification approach that can be applied to any new digital protocol development for smart detectors in physics experiments.

  17. Instrumentation and control of harmonic oscillators via a single-board microprocessor-FPGA device

    Science.gov (United States)

    Picone, Rico A. R.; Davis, Solomon; Devine, Cameron; Garbini, Joseph L.; Sidles, John A.

    2017-04-01

    We report the development of an instrumentation and control system instantiated on a microprocessor-field programmable gate array (FPGA) device for a harmonic oscillator comprising a portion of a magnetic resonance force microscope. The specific advantages of the system are that it minimizes computation, increases maintainability, and reduces the technical barrier required to enter the experimental field of magnetic resonance force microscopy. Heterodyne digital control and measurement yields computational advantages. A single microprocessor-FPGA device improves system maintainability by using a single programming language. The system presented requires significantly less technical expertise to instantiate than the instrumentation of previous systems, yet integrity of performance is retained and demonstrated with experimental data.

  18. FPGA Implementations of Feed Forward Neural Network by using Floating Point Hardware Accelerators

    Directory of Open Access Journals (Sweden)

    Gabriele-Maria Lozito

    2014-01-01

    Full Text Available This paper documents the research towards the analysis of different solutions to implement a Neural Network architecture on a FPGA design by using floating point accelerators. In particular, two different implementations are investigated: a high level solution to create a neural network on a soft processor design, with different strategies for enhancing the performance of the process; a low level solution, achieved by a cascade of floating point arithmetic elements. Comparisons of the achieved performance in terms of both time consumptions and FPGA resources employed for the architectures are presented.

  19. Embedded 3D Graphics Core for FPGA-based System-on-Chip Applications

    DEFF Research Database (Denmark)

    Holten-Lund, Hans Erik

    2005-01-01

    This paper presents a 3D graphics accelerator core for an FPGA based system, and illustrates how to build a System-on-Chip containing a Xilinx MicroBlaze soft-core CPU and our 3D graphics accelerator core. The system is capable of running uClinux and hardware accelerated 3D graphics applications...... consumption is reduced as well. We show how an FPGA based embedded system is capable of most tasks in a single chip solution, without requiring additional CPU or graphics chips....

  20. Parallel fixed point implementation of a radial basis function network in an FPGA.

    Science.gov (United States)

    de Souza, Alisson C D; Fernandes, Marcelo A C

    2014-09-29

    This paper proposes a parallel fixed point radial basis function (RBF) artificial neural network (ANN), implemented in a field programmable gate array (FPGA) trained online with a least mean square (LMS) algorithm. The processing time and occupied area were analyzed for various fixed point formats. The problems of precision of the ANN response for nonlinear classification using the XOR gate and interpolation using the sine function were also analyzed in a hardware implementation. The entire project was developed using the System Generator platform (Xilinx), with a Virtex-6 xc6vcx240t-1ff1156 as the target FPGA.