WorldWideScience

Sample records for application-specific integrated circuit

  1. Application specific integrated circuits and hybrid micro circuits for nuclear instrumentation

    International Nuclear Information System (INIS)

    Chandratre, V.B.; Sukhwani, Menka; Mukhopadhyay, P.K.; Shastrakar, R.S.; Sudheer, M.; Shedam, V.; Keni, Anubha

    2009-01-01

    Rapid development in semiconductor technology, sensors, detectors and requirements of high energy physics experiments as well as advances in commercially available nuclear instruments have lead to challenges for instrumentation. These challenges are met with development of Application Specific Integrated Circuits and Hybrid Micro Circuits. This paper discusses various activities in ASIC and HMC development in Bhabha Atomic Research Centre. (author)

  2. Application specific integrated circuit for high temperature oil well applications

    Energy Technology Data Exchange (ETDEWEB)

    Fallet, T.; Gakkestad, J.; Forre, G.

    1994-12-31

    This paper describes the design of an integrated BiCMOS circuit for high temperature applications. The circuit contains Pierce oscillators with automatic gain control, and measurements show that it is operating up to 266{sup o}C. The relative frequency variation up to 200 {sup o}C is less than 60 ppm caused mainly by the crystal element itself. 4 refs., 7 figs.

  3. Test and verification of a reactor protection system application-specific integrated circuit

    International Nuclear Information System (INIS)

    Battle, R.E.; Turner, G.W.; Vandermolen, R.I.; Vitalbo, C.

    1997-01-01

    Application-specific integrated circuits (ASICs) were utilized in the design of nuclear plant safety systems because they have certain advantages over software-based systems and analog-based systems. An advantage they have over software-based systems is that an ASIC design can be simple enough to not include branch statements and also can be thoroughly tested. A circuit card on which an ASIC is mounted can be configured to replace various versions of older analog equipment with fewer design types required. The approach to design and testing of ASICs for safety system applications is discussed in this paper. Included are discussions of the ASIC architecture, how it is structured to assist testing, and of the functional and enhanced circuit testing

  4. Design and Verification of Application Specific Integrated Circuits in a Network of Online Labs

    Directory of Open Access Journals (Sweden)

    A.Y. Al-Zoubi

    2009-08-01

    Full Text Available A solution to implement a remote laboratory for testing and designing analog Application-Specific Integrated Circuits of the type (ispPAC10 is presented. The application allows electrical engineering students to access and perform measurements and conduct analog electronics experiments over the internet. PAC-Designer software, running on a Citrix server, is used in the circuit design in which the signals are generated and the responses are acquired by a data acquisition board controlled by LabVIEW. Three interconnected remote labs located in three different continents will be implementing the proposed system.

  5. Application-specific integrated circuit design for a typical pressurized water reactor pressure channel trip

    International Nuclear Information System (INIS)

    Battle, R.E.; Manges, W.W.; Emery, M.S.; Vendermolen, R.I.; Bhatt, S.

    1994-01-01

    This article discusses the use of application-specific integrated circuits (ASICs) in nuclear plant safety systems. ASICs have certain advantages over software-based systems because they can be simple enough to be thoroughly tested, and they can be tailored to replace existing equipment. An architecture to replace a pressurized water reactor pressure channel trip is presented. Methods of implementing digital algorithms are also discussed

  6. Smart Power: New power integrated circuit technologies and their applications

    Science.gov (United States)

    Kuivalainen, Pekka; Pohjonen, Helena; Yli-Pietilae, Timo; Lenkkeri, Jaakko

    1992-05-01

    Power Integrated Circuits (PIC) is one of the most rapidly growing branches of the semiconductor technology. The PIC markets has been forecast to grow from 660 million dollars in 1990 to 1658 million dollars in 1994. It has even been forecast that at the end of the 1990's the PIC markets would correspond to the value of the whole semiconductor production in 1990. Automotive electronics will play the leading role in the development of the standard PIC's. Integrated motor drivers (36 V/4 A), smart integrated switches (60 V/30 A), solenoid drivers, integrated switch-mode power supplies and regulators are the latest standard devices of the PIC manufactures. ASIC (Application Specific Integrated Circuits) PIC solutions are needed for the same reasons as other ASIC devices: there are no proper standard devices, a company has a lot of application knowhow, which should be kept inside the company, the size of the product must be reduced, and assembly costs are wished to be reduced by decreasing the number of discrete devices. During the next few years the most probable ASIC PIC applications in Finland will be integrated solenoid and motor drivers, an integrated electronic lamp ballast circuit and various sensor interface circuits. Application of the PIC technologies to machines and actuators will strongly be increased all over the world. This means that various PIC's, either standard PIC's or full custom ASIC circuits, will appear in many products which compete with the corresponding Finnish products. Therefore the development of the PIC technologies must be followed carefully in order to immediately be able to apply the latest development in the smart power technologies and their design methods.

  7. An application specific integrated circuit and data acquisition system for digital X-ray imaging

    Energy Technology Data Exchange (ETDEWEB)

    Beuville, E.; Cederstroem, B.; Danielsson, M.; Luo, L.; Nygren, D.; Oltman, E.; Vestlund, J. [Lawrence Berkeley National Lab., CA (United States)

    1998-04-01

    We have developed an application specific integrated circuit (ASIC) and data acquisition system for digital X-ray imaging. The chip consists of 16 parallel channels, each containing preamplifier, shaper, comparator and a 16 bit counter. We have demonstrated noiseless single-photon counting over a threshold of 7.2 keV using Silicon detectors and are presently capable of maximum counting rates of 2 MHz per channel. The ASIC is controlled by a personal computer through a commercial PCI card, which is also used for data acquisition. The content of the 16 bit counters are loaded into a shift register and transferred to the PC at any time at a rate of 20 MHz. The system is non-complicated, low cost and high performance and is optimised for digital X-ray imaging applications. (orig.). 11 refs.

  8. An application specific integrated circuit and data acquisition system for digital X-ray imaging

    International Nuclear Information System (INIS)

    Beuville, E.; Cederstroem, B.; Danielsson, M.; Luo, L.; Nygren, D.; Oltman, E.; Vestlund, J.

    1998-01-01

    We have developed an application specific integrated circuit (ASIC) and data acquisition system for digital X-ray imaging. The chip consists of 16 parallel channels, each containing preamplifier, shaper, comparator and a 16 bit counter. We have demonstrated noiseless single-photon counting over a threshold of 7.2 keV using Silicon detectors and are presently capable of maximum counting rates of 2 MHz per channel. The ASIC is controlled by a personal computer through a commercial PCI card, which is also used for data acquisition. The content of the 16 bit counters are loaded into a shift register and transferred to the PC at any time at a rate of 20 MHz. The system is non-complicated, low cost and high performance and is optimised for digital X-ray imaging applications. (orig.)

  9. Operational Excellence through Schedule Optimization and Production Simulation of Application Specific Integrated Circuits.

    Energy Technology Data Exchange (ETDEWEB)

    Flory, John Andrew [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Padilla, Denise D. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Gauthier, John H. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Zwerneman, April Marie [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Miller, Steven P [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2016-05-01

    Upcoming weapon programs require an aggressive increase in Application Specific Integrated Circuit (ASIC) production at Sandia National Laboratories (SNL). SNL has developed unique modeling and optimization tools that have been instrumental in improving ASIC production productivity and efficiency, identifying optimal operational and tactical execution plans under resource constraints, and providing confidence in successful mission execution. With ten products and unprecedented levels of demand, a single set of shared resources, highly variable processes, and the need for external supplier task synchronization, scheduling is an integral part of successful manufacturing. The scheduler uses an iterative multi-objective genetic algorithm and a multi-dimensional performance evaluator. Schedule feasibility is assessed using a discrete event simulation (DES) that incorporates operational uncertainty, variability, and resource availability. The tools provide rapid scenario assessments and responses to variances in the operational environment, and have been used to inform major equipment investments and workforce planning decisions in multiple SNL facilities.

  10. Microwave integrated circuits for space applications

    Science.gov (United States)

    Leonard, Regis F.; Romanofsky, Robert R.

    1991-01-01

    Monolithic microwave integrated circuits (MMIC), which incorporate all the elements of a microwave circuit on a single semiconductor substrate, offer the potential for drastic reductions in circuit weight and volume and increased reliability, all of which make many new concepts in electronic circuitry for space applications feasible, including phased array antennas. NASA has undertaken an extensive program aimed at development of MMICs for space applications. The first such circuits targeted for development were an extension of work in hybrid (discrete component) technology in support of the Advanced Communication Technology Satellite (ACTS). It focused on power amplifiers, receivers, and switches at ACTS frequencies. More recent work, however, focused on frequencies appropriate for other NASA programs and emphasizes advanced materials in an effort to enhance efficiency, power handling capability, and frequency of operation or noise figure to meet the requirements of space systems.

  11. Application specific integrated circuit (ASIC) readout technologies for future ion beam analytical instruments

    Energy Technology Data Exchange (ETDEWEB)

    Whitlow, Harry J. E-mail: harry_j.whitlow@nuclear.lu.se

    2000-03-01

    New possibilities for ion beam analysis (IBA) are afforded by recent developments in detector technology which facilitate the parallel collection of data from a large number of channels. Application specific integrated circuit (ASIC) technologies, which have been widely employed for multi-channel readout systems in nuclear and particle physics, are more net-cost effective (160/channel for 1000 channels) and a more rational solution for readout of a large number of channels than afforded by conventional electronics. Based on results from existing and on-going chip designs, the possibilities and issues of ASIC readout technology are considered from the IBA viewpoint. Consideration is given to readout chip architecture and how the stringent resolution, linearity and stability requirements for IBA may be met. In addition the implications of the restrictions imposed by ASIC technology are discussed.

  12. Issues of verification and validation of application-specific integrated circuits in reactor trip systems

    International Nuclear Information System (INIS)

    Battle, R.E.; Alley, G.T.

    1993-01-01

    Concepts of using application-specific integrated circuits (ASICs) in nuclear reactor safety systems are evaluated. The motivation for this evaluation stems from the difficulty of proving that software-based protection systems are adequately reliable. Important issues concerning the reliability of computers and software are identified and used to evaluate features of ASICS. These concepts indicate that ASICs have several advantages over software for simple systems. The primary advantage of ASICs over software is that verification and validation (V ampersand V) of ASICs can be done with much higher confidence than can be done with software. A method of performing this V ampersand V on ASICS is being developed at Oak Ridge National Laboratory. The purpose of the method's being developed is to help eliminate design and fabrication errors. It will not solve problems with incorrect requirements or specifications

  13. Reactor protection system design using application specific integrated circuits

    International Nuclear Information System (INIS)

    Battle, R.E.; Bryan, W.L.; Kisner, R.A.; Wilson, T.L. Jr.

    1992-01-01

    Implementing reactor protection systems (RPS) or other engineering safeguard systems with application specific integrated circuits (ASICs) offers significant advantages over conventional analog or software based RPSs. Conventional analog RPSs suffer from setpoints drifts and large numbers of discrete analog electronics, hardware logic, and relays which reduce reliability because of the large number of potential failures of components or interconnections. To resolve problems associated with conventional discrete RPSs and proposed software based RPS systems, a hybrid analog and digital RPS system implemented with custom ASICs is proposed. The actual design of the ASIC RPS resembles a software based RPS but the programmable software portion of each channel is implemented in a fixed digital logic design including any input variable computations. Set point drifts are zero as in proposed software systems, but the verification and validation of the computations is made easier since the computational logic an be exhaustively tested. The functionality is assured fixed because there can be no future changes to the ASIC without redesign and fabrication. Subtle error conditions caused by out of order evaluation or time dependent evaluation of system variables against protection criteria are eliminated by implementing all evaluation computations in parallel for simultaneous results. On- chip redundancy within each RPS channel and continuous self-testing of all channels provided enhanced assurance that a particular channel is available and faults are identified as soon as possible for corrective actions. The use of highly integrated ASICs to implement channel electronics rather than the use of discrete electronics greatly reduces the total number of components and interconnections in the RPS to further increase system reliability. A prototype ASIC RPS channel design and the design environment used for ASIC RPS systems design is discussed

  14. RD53A Integrated Circuit Specifications

    OpenAIRE

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with...

  15. Thermal Radiometer Signal Processing Using Radiation Hard CMOS Application Specific Integrated Circuits for Use in Harsh Planetary Environments

    Science.gov (United States)

    Quilligan, G.; DuMonthier, J.; Aslam, S.; Lakew, B.; Kleyner, I.; Katz, R.

    2015-01-01

    Thermal radiometers such as proposed for the Europa Clipper flyby mission require low noise signal processing for thermal imaging with immunity to Total Ionizing Dose (TID) and Single Event Latchup (SEL). Described is a second generation Multi- Channel Digitizer (MCD2G) Application Specific Integrated Circuit (ASIC) that accurately digitizes up to 40 thermopile pixels with greater than 50 Mrad (Si) immunity TID and 174 MeV-sq cm/mg SEL. The MCD2G ASIC uses Radiation Hardened By Design (RHBD) techniques with a 180 nm CMOS process node.

  16. Addressable-Matrix Integrated-Circuit Test Structure

    Science.gov (United States)

    Sayah, Hoshyar R.; Buehler, Martin G.

    1991-01-01

    Method of quality control based on use of row- and column-addressable test structure speeds collection of data on widths of resistor lines and coverage of steps in integrated circuits. By use of straightforward mathematical model, line widths and step coverages deduced from measurements of electrical resistances in each of various combinations of lines, steps, and bridges addressable in test structure. Intended for use in evaluating processes and equipment used in manufacture of application-specific integrated circuits.

  17. MOS integrated circuit design

    CERN Document Server

    Wolfendale, E

    2013-01-01

    MOS Integral Circuit Design aims to help in the design of integrated circuits, especially large-scale ones, using MOS Technology through teaching of techniques, practical applications, and examples. The book covers topics such as design equation and process parameters; MOS static and dynamic circuits; logic design techniques, system partitioning, and layout techniques. Also featured are computer aids such as logic simulation and mask layout, as well as examples on simple MOS design. The text is recommended for electrical engineers who would like to know how to use MOS for integral circuit desi

  18. RD53A Integrated Circuit Specifications

    CERN Document Server

    Garcia-Sciveres, Mauricio

    2015-01-01

    Specifications for the RD53 collaboration’s first engineering wafer run of an integrated circuit (IC) for hybrid pixel detector readout, called RD53A. RD53A is intended to demonstrate in a large format IC the suitability of the technology (including radiation tolerance), the stable low threshold operation, and the high hit and trigger rate capabilities, required for HL-LHC upgrades of ATLAS and CMS. The wafer scale production will permit the experiments to prototype bump bonding assembly with realistic sensors in this new technology and to measure the performance of hybrid assemblies. RD53A is not intended to be a final production IC for use in an experiment, and will contain design variations for testing purposes, making the pixel matrix non-uniform.

  19. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1983-09-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technologie or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented

  20. Radiation effects in semiconductors: technologies for hardened integrated circuits

    International Nuclear Information System (INIS)

    Charlot, J.M.

    1984-01-01

    Various technologies are used to manufacture integrated circuits for electronic systems. But for specific applications, including those with radiation environment, it is necessary to choose an appropriate technology or to improve a specific one in order to reach a definite hardening level. The aim of this paper is to present the main effects induced by radiation (neutrons and gamma rays) into the basic semiconductor devices, to explain some physical degradation mechanisms and to propose solutions for hardened integrated circuit fabrication. The analysis involves essentially the monolithic structure of the integrated circuits and the isolation technology of active elements. In conclusion, the advantages of EPIC and SOS technologies are described and the potentialities of new technologies (GaAs and SOI) are presented. (author)

  1. Design optimization of radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    1975-01-01

    Ionizing-radiation-induced threshold voltage shifts in CMOS integrated circuits will drastically degrade circuit performance unless the design parameters related to the fabrication process are properly chosen. To formulate an approach to CMOS design optimization, experimentally observed analytical relationships showing strong dependences between threshold voltage shifts and silicon dioxide thickness are utilized. These measurements were made using radiation-hardened aluminum-gate CMOS inverter circuits and have been corroborated by independent data taken from MOS capacitor structures. Knowledge of these relationships allows one to define ranges of acceptable CMOS design parameters based upon radiation-hardening capabilities and post-irradiation performance specifications. Furthermore, they permit actual design optimization of CMOS integrated circuits which results in optimum pre- and post-irradiation performance with respect to speed, noise margins, and quiescent power consumption. Theoretical and experimental results of these procedures, the applications of which can mean the difference between failure and success of a CMOS integrated circuit in a radiation environment, are presented

  2. A Framework for Robust Multivariable Optimization of Integrated Circuits in Space Applications

    Science.gov (United States)

    DuMonthier, Jeffrey; Suarez, George

    2013-01-01

    Application Specific Integrated Circuit (ASIC) design for space applications involves multiple challenges of maximizing performance, minimizing power and ensuring reliable operation in extreme environments. This is a complex multidimensional optimization problem which must be solved early in the development cycle of a system due to the time required for testing and qualification severely limiting opportunities to modify and iterate. Manual design techniques which generally involve simulation at one or a small number of corners with a very limited set of simultaneously variable parameters in order to make the problem tractable are inefficient and not guaranteed to achieve the best possible results within the performance envelope defined by the process and environmental requirements. What is required is a means to automate design parameter variation, allow the designer to specify operational constraints and performance goals, and to analyze the results in a way which facilitates identifying the tradeoffs defining the performance envelope over the full set of process and environmental corner cases. The system developed by the Mixed Signal ASIC Group (MSAG) at the Goddard Space Flight Center is implemented as framework of software modules, templates and function libraries. It integrates CAD tools and a mathematical computing environment, and can be customized for new circuit designs with only a modest amount of effort as most common tasks are already encapsulated. Customization is required for simulation test benches to determine performance metrics and for cost function computation. Templates provide a starting point for both while toolbox functions minimize the code required. Once a test bench has been coded to optimize a particular circuit, it is also used to verify the final design. The combination of test bench and cost function can then serve as a template for similar circuits or be re-used to migrate the design to different processes by re-running it with the

  3. Vertically integrated circuit development at Fermilab for detectors

    International Nuclear Information System (INIS)

    Yarema, R; Deptuch, G; Hoff, J; Khalid, F; Lipton, R; Shenai, A; Trimpl, M; Zimmerman, T

    2013-01-01

    Today vertically integrated circuits, (a.k.a. 3D integrated circuits) is a popular topic in many trade journals. The many advantages of these circuits have been described such as higher speed due to shorter trace lenghts, the ability to reduce cross talk by placing analog and digital circuits on different levels, higher circuit density without the going to smaller feature sizes, lower interconnect capacitance leading to lower power, reduced chip size, and different processing for the various layers to optimize performance. There are some added advantages specifically for MAPS (Monolithic Active Pixel Sensors) in High Energy Physics: four side buttable pixel arrays, 100% diode fill factor, the ability to move PMOS transistors out of the diode sensing layer, and a increase in channel density. Fermilab began investigating 3D circuits in 2006. Many different bonding processes have been described for fabricating 3D circuits [1]. Fermilab has used three different processes to fabricate several circuits for specific applications in High Energy Physics and X-ray imaging. This paper covers some of the early 3D work at Fermilab and then moves to more recent activities. The major processes we have used are discussed and some of the problems encountered are described. An overview of pertinent 3D circuit designs is presented along with test results thus far.

  4. Macromodels of digital integrated circuits for program packages of circuit engineering design

    Science.gov (United States)

    Petrenko, A. I.; Sliusar, P. B.; Timchenko, A. P.

    1984-04-01

    Various aspects of the generation of macromodels of digital integrated circuits are examined, and their effective application in program packages of circuit engineering design is considered. Three levels of macromodels are identified, and the application of such models to the simulation of circuit outputs is discussed.

  5. Report on application specific integrated circuits for relativistic heavy ion detectors

    International Nuclear Information System (INIS)

    Platner, E.D.

    1988-01-01

    Detector systems for RHIC experiments are invariably going to be large and complex. Thus it behooves the planners to incorporate elements that have little need for adjustment, calibration and correction to the produced data. For example, if power, size and cost considerations permit, time can be digitized directly (i.e. with counters, shift registers, etc.) where no adjustments, calibrations or corrections are required. The circuit either works correctly or not at all. This kind of circuit behavior is extremely valuable in detectors with 10 5 or more channel elements. In analog to digital conversion applications, direct conversion (i.e. flash ADC) may be prohibitive in cost, size and power. Here major effort must be given to minimize the magnitude of offset and conversion gain variance. Where possible self correction and adjustment should be applied at the subsystem level

  6. Integrated coherent matter wave circuits

    International Nuclear Information System (INIS)

    Ryu, C.; Boshier, M. G.

    2015-01-01

    An integrated coherent matter wave circuit is a single device, analogous to an integrated optical circuit, in which coherent de Broglie waves are created and then launched into waveguides where they can be switched, divided, recombined, and detected as they propagate. Applications of such circuits include guided atom interferometers, atomtronic circuits, and precisely controlled delivery of atoms. We report experiments demonstrating integrated circuits for guided coherent matter waves. The circuit elements are created with the painted potential technique, a form of time-averaged optical dipole potential in which a rapidly moving, tightly focused laser beam exerts forces on atoms through their electric polarizability. Moreover, the source of coherent matter waves is a Bose-Einstein condensate (BEC). Finally, we launch BECs into painted waveguides that guide them around bends and form switches, phase coherent beamsplitters, and closed circuits. These are the basic elements that are needed to engineer arbitrarily complex matter wave circuitry

  7. Secure integrated circuits and systems

    CERN Document Server

    Verbauwhede, Ingrid MR

    2010-01-01

    On any advanced integrated circuit or 'system-on-chip' there is a need for security. In many applications the actual implementation has become the weakest link in security rather than the algorithms or protocols. The purpose of the book is to give the integrated circuits and systems designer an insight into the basics of security and cryptography from the implementation point of view. As a designer of integrated circuits and systems it is important to know both the state-of-the-art attacks as well as the countermeasures. Optimizing for security is different from optimizations for speed, area,

  8. Printed organic thin-film transistor-based integrated circuits

    International Nuclear Information System (INIS)

    Mandal, Saumen; Noh, Yong-Young

    2015-01-01

    Organic electronics is moving ahead on its journey towards reality. However, this technology will only be possible when it is able to meet specific criteria including flexibility, transparency, disposability and low cost. Printing is one of the conventional techniques to deposit thin films from solution-based ink. It is used worldwide for visual modes of information, and it is now poised to enter into the manufacturing processes of various consumer electronics. The continuous progress made in the field of functional organic semiconductors has achieved high solubility in common solvents as well as high charge carrier mobility, which offers ample opportunity for organic-based printed integrated circuits. In this paper, we present a comprehensive review of all-printed organic thin-film transistor-based integrated circuits, mainly ring oscillators. First, the necessity of all-printed organic integrated circuits is discussed; we consider how the gap between printed electronics and real applications can be bridged. Next, various materials for printed organic integrated circuits are discussed. The features of these circuits and their suitability for electronics using different printing and coating techniques follow. Interconnection technology is equally important to make this product industrially viable; much attention in this review is placed here. For high-frequency operation, channel length should be sufficiently small; this could be achievable with a combination of surface treatment-assisted printing or laser writing. Registration is also an important issue related to printing; the printed gate should be perfectly aligned with the source and drain to minimize parasitic capacitances. All-printed organic inverters and ring oscillators are discussed here, along with their importance. Finally, future applications of all-printed organic integrated circuits are highlighted. (paper)

  9. Note: A 102 dB dynamic-range charge-sampling readout for ionizing particle/radiation detectors based on an application-specific integrated circuit (ASIC)

    Science.gov (United States)

    Pullia, A.; Zocca, F.; Capra, S.

    2018-02-01

    An original technique for the measurement of charge signals from ionizing particle/radiation detectors has been implemented in an application-specific integrated circuit form. The device performs linear measurements of the charge both within and beyond its output voltage swing. The device features an unprecedented spectroscopic dynamic range of 102 dB and is suitable for high-resolution ion and X-γ ray spectroscopy. We believe that this approach may change a widespread paradigm according to which no high-resolution spectroscopy is possible when working close to or beyond the limit of the preamplifier's output voltage swing.

  10. Long-wavelength III-V/silicon photonic integrated circuits

    NARCIS (Netherlands)

    Roelkens, G.C.; Kuyken, B.; Leo, F.; Hattasan, N.; Ryckeboer, E.M.P.; Muneeb, M.; Hu, C.L.; Malik, A.; Hens, Z.; Baets, R.G.F.; Shimura, Y.; Gencarelli, F.; Vincent, B.; Loo, van de R.; Verheyen, P.A.; Lepage, G.; Campenhout, van J.; Cerutti, L.; Rodriquez, J.B.; Tournie, E.; Chen, X; Nedeljkovic, G.; Mashanovich, G.; Liu, X.; Green, W.S.

    2013-01-01

    We review our work in the field of short-wave infrared and mid-infrared photonic integrated circuits for applications in spectroscopic sensing systems. Passive silicon waveguide circuits, GeSn photodetectors, the integration of III-V and IV-VI semiconductors on these circuits, and silicon nonlinear

  11. An Energy efficient application specific integrated circuit for electrocardiogram feature detection and its potential for ambulatory cardiovascular disease detection.

    Science.gov (United States)

    Jain, Sanjeev Kumar; Bhaumik, Basabi

    2016-03-01

    A novel algorithm based on forward search is developed for real-time electrocardiogram (ECG) signal processing and implemented in application specific integrated circuit (ASIC) for QRS complex related cardiovascular disease diagnosis. The authors have evaluated their algorithm using MIT-BIH database and achieve sensitivity of 99.86% and specificity of 99.93% for QRS complex peak detection. In this Letter, Physionet PTB diagnostic ECG database is used for QRS complex related disease detection. An ASIC for cardiovascular disease detection is fabricated using 130-nm CMOS high-speed process technology. The area of the ASIC is 0.5 mm(2). The power dissipation is 1.73 μW at the operating frequency of 1 kHz with a supply voltage of 0.6 V. The output from the ASIC is fed to their Android application that generates diagnostic report and can be sent to a cardiologist through email. Their ASIC result shows average failed detection rate of 0.16% for six leads data of 290 patients in PTB diagnostic ECG database. They also have implemented a low-leakage version of their ASIC. The ASIC dissipates only 45 pJ with a supply voltage of 0.9 V. Their proposed ASIC is most suitable for energy efficient telemetry cardiovascular disease detection system.

  12. Photonic Integrated Circuits

    Science.gov (United States)

    Krainak, Michael; Merritt, Scott

    2016-01-01

    Integrated photonics generally is the integration of multiple lithographically defined photonic and electronic components and devices (e.g. lasers, detectors, waveguides passive structures, modulators, electronic control and optical interconnects) on a single platform with nanometer-scale feature sizes. The development of photonic integrated circuits permits size, weight, power and cost reductions for spacecraft microprocessors, optical communication, processor buses, advanced data processing, and integrated optic science instrument optical systems, subsystems and components. This is particularly critical for small spacecraft platforms. We will give an overview of some NASA applications for integrated photonics.

  13. Thermionic integrated circuit technology for high power space applications

    International Nuclear Information System (INIS)

    Yadavalli, S.R.

    1984-01-01

    Thermionic triode and integrated circuit technology is in its infancy and it is emerging. The Thermionic triode can operate at relatively high voltages (up to 2000V) and at least tens of amperes. These devices, including their use in integrated circuitry, operate at high temperatures (800 0 C) and are very tolerant to nuclear and other radiations. These properties can be very useful in large space power applications such as that represented by the SP-100 system which uses a nuclear reactor. This paper presents an assessment of the application of thermionic integrated circuitry with space nuclear power system technology. A comparison is made with conventional semiconductor circuitry considering a dissipative shunt regulator for SP-100 type nuclear power system rated at 100 kW. The particular advantages of thermionic circuitry are significant reductions in size and mass of heat dissipation and radiation shield subsystems

  14. Development of wide range charge integration application specified integrated circuit for photo-sensor

    Energy Technology Data Exchange (ETDEWEB)

    Katayose, Yusaku, E-mail: katayose@ynu.ac.jp [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan); Ikeda, Hirokazu [Institute of Space and Astronautical Science (ISAS)/Japan Aerospace Exploration Agency (JAXA), 3-1-1 Yoshinodai, Chuo-ku, Sagamihara, Kanagawa 252-5210 (Japan); Tanaka, Manobu [National Laboratory for High Energy Physics, KEK, 1-1 Oho, Tsukuba, Ibaraki 305-0801 (Japan); Shibata, Makio [Department of Physics, Yokohama National University, 79-5 Tokiwadai, Hodogaya-ku, Yokohama, Kanagawa 240-8501 (Japan)

    2013-01-21

    A front-end application specified integrated circuit (ASIC) is developed with a wide dynamic range amplifier (WDAMP) to read-out signals from a photo-sensor like a photodiode. The WDAMP ASIC consists of a charge sensitive preamplifier, four wave-shaping circuits with different amplification factors and Wilkinson-type analog-to-digital converter (ADC). To realize a wider range, the integrating capacitor in the preamplifier can be changed from 4 pF to 16 pF by a two-bit switch. The output of a preamplifier is shared by the four wave-shaping circuits with four gains of 1, 4, 16 and 64 to adapt the input range of ADC. A 0.25-μm CMOS process (of UMC electronics CO., LTD) is used to fabricate the ASIC with four-channels. The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC and the noise performance of 0.46 fC + 6.4×10{sup −4} fC/pF. -- Highlights: ► A front-end ASIC is developed with a wide dynamic range amplifier. ► The ASIC consists of a CSA, four wave-shaping circuits and pulse-height-to-time converters. ► The dynamic range of four orders of magnitude is achieved with the maximum range over 20 pC.

  15. Analog integrated circuits design for processing physiological signals.

    Science.gov (United States)

    Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

    2010-01-01

    Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

  16. Predictive Direct Torque Control Application-Specific Integrated Circuit of an Induction Motor Drive with a Fuzzy Controller

    Directory of Open Access Journals (Sweden)

    Guo-Ming Sung

    2017-06-01

    Full Text Available This paper proposes a modified predictive direct torque control (PDTC application-specific integrated circuit (ASIC of a motor drive with a fuzzy controller for eliminating sampling and calculating delay times in hysteresis controllers. These delay times degrade the control quality and increase both torque and flux ripples in a motor drive. The proposed fuzzy PDTC ASIC calculates the stator’s magnetic flux and torque by detecting the three-phase current, three-phase voltage, and rotor speed, and eliminates the ripples in the torque and flux by using a fuzzy controller and predictive scheme. The Verilog hardware description language was used to implement the hardware architecture, and the ASIC was fabricated by the Taiwan Semiconductor Manufacturing Company through a 0.18-μm 1P6M CMOS process that involved a cell-based design method. The measurements revealed that the proposed fuzzy PDTC ASIC of the three-phase induction motor yielded a test coverage of 96.03%, fault coverage of 95.06%, chip area of 1.81 × 1.81 mm2, and power consumption of 296 mW, at an operating frequency of 50 MHz and a supply voltage of 1.8 V.

  17. Signal Digitizer and Cross-Correlation Application Specific Integrated Circuit

    Science.gov (United States)

    Baranauskas, Dalius (Inventor); Baranauskas, Gytis (Inventor); Zelenin, Denis (Inventor); Kangaslahti, Pekka (Inventor); Tanner, Alan B. (Inventor); Lim, Boon H. (Inventor)

    2017-01-01

    According to one embodiment, a cross-correlator comprises a plurality of analog front ends (AFEs), a cross-correlation circuit and a data serializer. Each of the AFEs comprises a variable gain amplifier (VGA) and a corresponding analog-to-digital converter (ADC) in which the VGA receives and modifies a unique analog signal associates with a measured analog radio frequency (RF) signal and the ADC produces digital data associated with the modified analog signal. Communicatively coupled to the AFEs, the cross-correlation circuit performs a cross-correlation operation on the digital data produced from different measured analog RF signals. The data serializer is communicatively coupled to the summing and cross-correlating matrix and continuously outputs a prescribed amount of the correlated digital data.

  18. Vertically Integrated Circuits at Fermilab

    International Nuclear Information System (INIS)

    Deptuch, Grzegorz; Demarteau, Marcel; Hoff, James; Lipton, Ronald; Shenai, Alpana; Trimpl, Marcel; Yarema, Raymond; Zimmerman, Tom

    2009-01-01

    The exploration of the vertically integrated circuits, also commonly known as 3D-IC technology, for applications in radiation detection started at Fermilab in 2006. This paper examines the opportunities that vertical integration offers by looking at various 3D designs that have been completed by Fermilab. The emphasis is on opportunities that are presented by through silicon vias (TSV), wafer and circuit thinning and finally fusion bonding techniques to replace conventional bump bonding. Early work by Fermilab has led to an international consortium for the development of 3D-IC circuits for High Energy Physics. The consortium has submitted over 25 different designs for the Fermilab organized MPW run organized for the first time.

  19. Materials Integration and Doping of Carbon Nanotube-based Logic Circuits

    Science.gov (United States)

    Geier, Michael

    Over the last 20 years, extensive research into the structure and properties of single- walled carbon nanotube (SWCNT) has elucidated many of the exceptional qualities possessed by SWCNTs, including record-setting tensile strength, excellent chemical stability, distinctive optoelectronic features, and outstanding electronic transport characteristics. In order to exploit these remarkable qualities, many application-specific hurdles must be overcome before the material can be implemented in commercial products. For electronic applications, recent advances in sorting SWCNTs by electronic type have enabled significant progress towards SWCNT-based integrated circuits. Despite these advances, demonstrations of SWCNT-based devices with suitable characteristics for large-scale integrated circuits have been limited. The processing methodologies, materials integration, and mechanistic understanding of electronic properties developed in this dissertation have enabled unprecedented scales of SWCNT-based transistor fabrication and integrated circuit demonstrations. Innovative materials selection and processing methods are at the core of this work and these advances have led to transistors with the necessary transport properties required for modern circuit integration. First, extensive collaborations with other research groups allowed for the exploration of SWCNT thin-film transistors (TFTs) using a wide variety of materials and processing methods such as new dielectric materials, hybrid semiconductor materials systems, and solution-based printing of SWCNT TFTs. These materials were integrated into circuit demonstrations such as NOR and NAND logic gates, voltage-controlled ring oscillators, and D-flip-flops using both rigid and flexible substrates. This dissertation explores strategies for implementing complementary SWCNT-based circuits, which were developed by using local metal gate structures that achieve enhancement-mode p-type and n-type SWCNT TFTs with widely separated and

  20. SiGe Integrated Circuit Developments for SQUID/TES Readout

    Science.gov (United States)

    Prêle, D.; Voisin, F.; Beillimaz, C.; Chen, S.; Piat, M.; Goldwurm, A.; Laurent, P.

    2018-03-01

    SiGe integrated circuits dedicated to the readout of superconducting bolometer arrays for astrophysics have been developed since more than 10 years at APC. Whether for Cosmic Microwave Background (CMB) observations with the QUBIC ground-based experiment (Aumont et al. in astro-ph.IM, 2016. arXiv:1609.04372) or for the Hot and Energetic Universe science theme with the X-IFU instrument on-board of the ATHENA space mission (Barret et al. in SPIE 9905, space telescopes & instrumentation 2016: UV to γ Ray, 2016. https://doi.org/10.1117/12.2232432), several kinds of Transition Edge Sensor (TES) (Irwin and Hilton, in ENSS (ed) Cryogenic particle detection, Springer, Berlin, 2005) arrays have been investigated. To readout such superconducting detector arrays, we use time or frequency domain multiplexers (TDM, FDM) (Prêle in JINST 10:C08015, 2016. https://doi.org/10.1088/1748-0221/10/08/C08015) with Superconducting QUantum Interference Devices (SQUID). In addition to the SQUID devices, low-noise biasing and amplification are needed. These last functions can be obtained by using BiCMOS SiGe technology in an Application Specific Integrated Circuit (ASIC). ASIC technology allows integration of highly optimised circuits specifically designed for a unique application. Moreover, we could reach very low-noise and wide band amplification using SiGe bipolar transistor either at room or cryogenic temperatures (Cressler in J Phys IV 04(C6):C6-101, 1994. https://doi.org/10.1051/jp4:1994616). This paper discusses the use of SiGe integrated circuits for SQUID/TES readout and gives an update of the last developments dedicated to the QUBIC telescope and to the X-IFU instrument. Both ASIC called SQmux128 and AwaXe are described showing the interest of such SiGe technology for SQUID multiplexer controls.

  1. Trends in integrated circuit design for particle physics experiments

    International Nuclear Information System (INIS)

    Atkin, E V

    2017-01-01

    Integrated circuits are one of the key complex units available to designers of multichannel detector setups. A whole number of factors makes Application Specific Integrated Circuits (ASICs) valuable for Particle Physics and Astrophysics experiments. Among them the most important ones are: integration scale, low power dissipation, radiation tolerance. In order to make possible future experiments in the intensity, cosmic, and energy frontiers today ASICs should provide new level of functionality at a new set of constraints and trade-offs, like low-noise high-dynamic range amplification and pulse shaping, high-speed waveform sampling, low power digitization, fast digital data processing, serialization and data transmission. All integrated circuits, necessary for physical instrumentation, should be radiation tolerant at an earlier not reached level (hundreds of Mrad) of total ionizing dose and allow minute almost 3D assemblies. The paper is based on literary source analysis and presents an overview of the state of the art and trends in nowadays chip design, using partially own ASIC lab experience. That shows a next stage of ising micro- and nanoelectronics in physical instrumentation. (paper)

  2. Microwaves integrated circuits: hybrids and monolithics - fabrication technology

    International Nuclear Information System (INIS)

    Cunha Pinto, J.K. da

    1983-01-01

    Several types of microwave integrated circuits are presented together with comments about technologies and fabrication processes; advantages and disadvantages in their utilization are analysed. Basic structures, propagation modes, materials used and major steps in the construction of hybrid thin film and monolithic microwave integrated circuits are described. Important technological applications are revised and main activities of the microelectronics lab. of the University of Sao Paulo (Brazil) in the field of hybrid and monolithic microwave integrated circuits are summarized. (C.L.B.) [pt

  3. Photonic Integrated Circuit (PIC) Device Structures: Background, Fabrication Ecosystem, Relevance to Space Systems Applications, and Discussion of Related Radiation Effects

    Science.gov (United States)

    Alt, Shannon

    2016-01-01

    Electronic integrated circuits are considered one of the most significant technological advances of the 20th century, with demonstrated impact in their ability to incorporate successively higher numbers transistors and construct electronic devices onto a single CMOS chip. Photonic integrated circuits (PICs) exist as the optical analog to integrated circuits; however, in place of transistors, PICs consist of numerous scaled optical components, including such "building-block" structures as waveguides, MMIs, lasers, and optical ring resonators. The ability to construct electronic and photonic components on a single microsystems platform offers transformative potential for the development of technologies in fields including communications, biomedical device development, autonomous navigation, and chemical and atmospheric sensing. Developing on-chip systems that provide new avenues for integration and replacement of bulk optical and electro-optic components also reduces size, weight, power and cost (SWaP-C) limitations, which are important in the selection of instrumentation for specific flight projects. The number of applications currently emerging for complex photonics systems-particularly in data communications-warrants additional investigations when considering reliability for space systems development. This Body of Knowledge document seeks to provide an overview of existing integrated photonics architectures; the current state of design, development, and fabrication ecosystems in the United States and Europe; and potential space applications, with emphasis given to associated radiation effects and reliability.

  4. Enabling the Internet of Things from integrated circuits to integrated systems

    CERN Document Server

    2017-01-01

    This book offers the first comprehensive view on integrated circuit and system design for the Internet of Things (IoT), and in particular for the tiny nodes at its edge. The authors provide a fresh perspective on how the IoT will evolve based on recent and foreseeable trends in the semiconductor industry, highlighting the key challenges, as well as the opportunities for circuit and system innovation to address them. This book describes what the IoT really means from the design point of view, and how the constraints imposed by applications translate into integrated circuit requirements and design guidelines. Chapter contributions equally come from industry and academia. After providing a system perspective on IoT nodes, this book focuses on state-of-the-art design techniques for IoT applications, encompassing the fundamental sub-systems encountered in Systems on Chip for IoT: ultra-low power digital architectures and circuits low- and zero-leakage memories (including emerging technologies) circuits for hardwar...

  5. Progress in radiation immune thermionic integrated circuits

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs

  6. Progress in radiation immune thermionic integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Lynn, D.K.; McCormick, J.B. (comps.)

    1985-08-01

    This report describes the results of a program directed at evaluating the thermionic integrated circuit (TIC) technology for applicability to military systems. Previous programs under the sponsorship of the Department of Energy, Office of Basic Energy Sciences, have developed an initial TIC technology base and demonstrated operation in high-temperature and high-radiation environments. The program described in this report has two parts: (1) a technical portion in which experiments and analyses were conducted to refine perceptions of near-term as well as ultimate performance levels of the TIC technology and (2) an applications portion in which the technical conclusions were to be evaluated against potential military applications. This report draws several conclusions that strongly suggest that (1) useful radiation-hard/high-temperature operable integrated circuits can be developed using the TIC technology; (2) because of their ability to survive and operate in hostile environments, a variety of potential military applications have been projected for this technology; and (3) based on the above two conclusions, an aggressive TIC development program should be initiated to provide the designers of future systems with integrated circuits and devices with the unique features of the TICs.

  7. Integrated circuit and method of arbitration in a network on an integrated circuit.

    NARCIS (Netherlands)

    2011-01-01

    The invention relates to an integrated circuit and to a method of arbitration in a network on an integrated circuit. According to the invention, a method of arbitration in a network on an integrated circuit is provided, the network comprising a router unit, the router unit comprising a first input

  8. An analog integrated circuit design laboratory

    OpenAIRE

    Mondragon-Torres, A.F.; Mayhugh, Jr.; Pineda de Gyvez, J.; Silva-Martinez, J.; Sanchez-Sinencio, E.

    2003-01-01

    We present the structure of an analog integrated circuit design laboratory to instruct at both, senior undergraduate and entry graduate levels. The teaching material includes: a laboratory manual with analog circuit design theory, pre-laboratory exercises and circuit design specifications; a reference web page with step by step instructions and examples; the use of mathematical tools for automation and analysis; and state of the art CAD design tools in use by industry. Upon completion of the ...

  9. How complex can integrated optical circuits become?

    NARCIS (Netherlands)

    Smit, M.K.; Hill, M.T.; Baets, R.G.F.; Bente, E.A.J.M.; Dorren, H.J.S.; Karouta, F.; Koenraad, P.M.; Koonen, A.M.J.; Leijtens, X.J.M.; Nötzel, R.; Oei, Y.S.; Waardt, de H.; Tol, van der J.J.G.M.; Khoe, G.D.

    2007-01-01

    The integration scale in Photonic Integrated Circuits will be pushed to VLSI-level in the coming decade. This will bring major changes in both application and manufacturing. In this paper developments in Photonic Integration are reviewed and the limits for reduction of device demensions are

  10. Parallel sparse direct solver for integrated circuit simulation

    CERN Document Server

    Chen, Xiaoming; Yang, Huazhong

    2017-01-01

    This book describes algorithmic methods and parallelization techniques to design a parallel sparse direct solver which is specifically targeted at integrated circuit simulation problems. The authors describe a complete flow and detailed parallel algorithms of the sparse direct solver. They also show how to improve the performance by simple but effective numerical techniques. The sparse direct solver techniques described can be applied to any SPICE-like integrated circuit simulator and have been proven to be high-performance in actual circuit simulation. Readers will benefit from the state-of-the-art parallel integrated circuit simulation techniques described in this book, especially the latest parallel sparse matrix solution techniques. · Introduces complicated algorithms of sparse linear solvers, using concise principles and simple examples, without complex theory or lengthy derivations; · Describes a parallel sparse direct solver that can be adopted to accelerate any SPICE-like integrated circuit simulato...

  11. Materials issues in silicon integrated circuit processing

    International Nuclear Information System (INIS)

    Wittmer, M.; Stimmell, J.; Strathman, M.

    1986-01-01

    The symposium on ''Materials Issues in Integrated Circuit Processing'' sought to bring together all of the materials issued pertinent to modern integrated circuit processing. The inherent properties of the materials are becoming an important concern in integrated circuit manufacturing and accordingly research in materials science is vital for the successful implementation of modern integrated circuit technology. The session on Silicon Materials Science revealed the advanced stage of knowledge which topics such as point defects, intrinsic and extrinsic gettering and diffusion kinetics have achieved. Adaption of this knowledge to specific integrated circuit processing technologies is beginning to be addressed. The session on Epitaxy included invited papers on epitaxial insulators and IR detectors. Heteroepitaxy on silicon is receiving great attention and the results presented in this session suggest that 3-d integrated structures are an increasingly realistic possibility. Progress in low temperature silicon epitaxy and epitaxy of thin films with abrupt interfaces was also reported. Diffusion and Ion Implantation were well presented. Regrowth of implant-damaged layers and the nature of the defects which remain after regrowth were discussed in no less than seven papers. Substantial progress was also reported in the understanding of amorphising boron implants and the use of gallium implants for the formation of shallow p/sup +/ -layers

  12. Microwave integrated circuit for Josephson voltage standards

    Science.gov (United States)

    Holdeman, L. B.; Toots, J.; Chang, C. C. (Inventor)

    1980-01-01

    A microwave integrated circuit comprised of one or more Josephson junctions and short sections of microstrip or stripline transmission line is fabricated from thin layers of superconducting metal on a dielectric substrate. The short sections of transmission are combined to form the elements of the circuit and particularly, two microwave resonators. The Josephson junctions are located between the resonators and the impedance of the Josephson junctions forms part of the circuitry that couples the two resonators. The microwave integrated circuit has an application in Josephson voltage standards. In this application, the device is asymmetrically driven at a selected frequency (approximately equal to the resonance frequency of the resonators), and a d.c. bias is applied to the junction. By observing the current voltage characteristic of the junction, a precise voltage, proportional to the frequency of the microwave drive signal, is obtained.

  13. The Software Reliability of Large Scale Integration Circuit and Very Large Scale Integration Circuit

    OpenAIRE

    Artem Ganiyev; Jan Vitasek

    2010-01-01

    This article describes evaluation method of faultless function of large scale integration circuits (LSI) and very large scale integration circuits (VLSI). In the article there is a comparative analysis of factors which determine faultless of integrated circuits, analysis of already existing methods and model of faultless function evaluation of LSI and VLSI. The main part describes a proposed algorithm and program for analysis of fault rate in LSI and VLSI circuits.

  14. Microwave GaAs Integrated Circuits On Quartz Substrates

    Science.gov (United States)

    Siegel, Peter H.; Mehdi, Imran; Wilson, Barbara

    1994-01-01

    Integrated circuits for use in detecting electromagnetic radiation at millimeter and submillimeter wavelengths constructed by bonding GaAs-based integrated circuits onto quartz-substrate-based stripline circuits. Approach offers combined advantages of high-speed semiconductor active devices made only on epitaxially deposited GaAs substrates with low-dielectric-loss, mechanically rugged quartz substrates. Other potential applications include integration of antenna elements with active devices, using carrier substrates other than quartz to meet particular requirements using lifted-off GaAs layer in membrane configuration with quartz substrate supporting edges only, and using lift-off technique to fabricate ultrathin discrete devices diced separately and inserted into predefined larger circuits. In different device concept, quartz substrate utilized as transparent support for GaAs devices excited from back side by optical radiation.

  15. On-chip enzymatic microbiofuel cell-powered integrated circuits.

    Science.gov (United States)

    Mark, Andrew G; Suraniti, Emmanuel; Roche, Jérôme; Richter, Harald; Kuhn, Alexander; Mano, Nicolas; Fischer, Peer

    2017-05-16

    A variety of diagnostic and therapeutic medical technologies rely on long term implantation of an electronic device to monitor or regulate a patient's condition. One proposed approach to powering these devices is to use a biofuel cell to convert the chemical energy from blood nutrients into electrical current to supply the electronics. We present here an enzymatic microbiofuel cell whose electrodes are directly integrated into a digital electronic circuit. Glucose oxidizing and oxygen reducing enzymes are immobilized on microelectrodes of an application specific integrated circuit (ASIC) using redox hydrogels to produce an enzymatic biofuel cell, capable of harvesting electrical power from just a single droplet of 5 mM glucose solution. Optimisation of the fuel cell voltage and power to match the requirements of the electronics allow self-powered operation of the on-board digital circuitry. This study represents a step towards implantable self-powered electronic devices that gather their energy from physiological fluids.

  16. Integrated circuit for processing a low-frequency signal from a seismic detector

    Energy Technology Data Exchange (ETDEWEB)

    Malashevich, N. I.; Roslyakov, A. S.; Polomoshnov, S. A., E-mail: S.Polomoshnov@tsen.ru; Fedorov, R. A. [Research and Production Complex ' Technological Center' of the Moscow Institute of Electronic Technology (Russian Federation)

    2011-12-15

    Specific features for the detection and processing of a low-frequency signal from a seismic detector are considered in terms of an integrated circuit based on a large matrix crystal of the 5507 series. This integrated circuit is designed for the detection of human movements. The specific features of the information signal, obtained at the output of the seismic detector, and the main characteristics of the integrated circuit and its structure are reported.

  17. Lateral power transistors in integrated circuits

    CERN Document Server

    Erlbacher, Tobias

    2014-01-01

    This book details and compares recent advancements in the development of novel lateral power transistors (LDMOS devices) for integrated circuits in power electronic applications. It includes the state-of-the-art concept of double-acting RESURF topologies.

  18. Development of integrated thermionic circuits for high-temperature applications

    International Nuclear Information System (INIS)

    McCormick, J.B.; Wilde, D.; Depp, S.; Hamilton, D.J.; Kerwin, W.; Derouin, C.; Roybal, L.; Dooley, R.

    1981-01-01

    A class of devices known as integrated thermionic circuits (ITC) capable of extended operation in ambient temperatures up to 500 0 C is described. The evolution of the ITC concept is discussed. A set of practical design and performance equations is demonstrated. Recent experimental results are discussed in which both devices and simple circuits have successfully operated in 500 0 C environments for extended periods of time

  19. Refractory silicides for integrated circuits

    International Nuclear Information System (INIS)

    Murarka, S.P.

    1980-01-01

    Transition metal silicides have, in the past, attracted attention because of their usefulness as high temperature materials and in integrated circuits as Schottky barrier and ohmic contacts. More recently, with the increasing silicon integrated circuits (SIC) packing density, the line widths get narrower and the sheet resistance contribution to the RC delay increases. The possibility of using low resistivity silicides, which can be formed directly on the polysilicon, makes these silicides highly attractive. The usefulness of a silicide metallization scheme for integrated circuits depends, not only on the desired low resistivity, but also on the ease with which the silicide can be formed and patterned and on the stability of the silicides throughout device processing and during actual device usage. In this paper, various properties and the formation techniques of the silicides have been reviewed. Correlations between the various properties and the metal or silicide electronic or crystallographic structure have been made to predict the more useful silicides for SIC applications. Special reference to the silicide resistivity, stress, and oxidizability during the formation and subsequent processing has been given. Various formation and etching techniques are discussed

  20. Integrated circuits with emitter coupling and their application in nanosecond nuclear electronics

    International Nuclear Information System (INIS)

    Basiladze, S.G.

    1976-01-01

    Principal static and dynamic characteristics are considered of integrated circuits with emitter coupling, as well as problems of signal transmission. Diagrams are given of amplifiers, discriminators, time interval drivers, generators, etc. Systems and units of nanosecond electronics employing integrated circuits with emitter coupling are briefly described

  1. Speech recognition by means of a three-integrated-circuit set

    Energy Technology Data Exchange (ETDEWEB)

    Zoicas, A.

    1983-11-03

    The author uses pattern recognition methods for detecting word boundaries, and monitors incoming speech at 12 millisecond intervals. Frequency is divided into eight bands and analysis is achieved in an analogue interface integrated circuit, a pipeline digital processor and a control integrated circuit. Applications are suggested, including speech input to personal computers. 3 references.

  2. CMOS analog integrated circuits high-speed and power-efficient design

    CERN Document Server

    Ndjountche, Tertulien

    2011-01-01

    High-speed, power-efficient analog integrated circuits can be used as standalone devices or to interface modern digital signal processors and micro-controllers in various applications, including multimedia, communication, instrumentation, and control systems. New architectures and low device geometry of complementary metaloxidesemiconductor (CMOS) technologies have accelerated the movement toward system on a chip design, which merges analog circuits with digital, and radio-frequency components. CMOS: Analog Integrated Circuits: High-Speed and Power-Efficient Design describes the important tren

  3. An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

    Energy Technology Data Exchange (ETDEWEB)

    Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

    2015-07-15

    We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

  4. High-voltage integrated transmitting circuit with differential driving for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Færch, Kjartan Ullitz

    2016-01-01

    In this paper, a high-voltage integrated differential transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is presented. Due to its application, area and power consumption are critical and need to be minimized. The circuitry...... is designed and implemented in AMS 0.35 μ m high-voltage process. Measurements are performed on the fabricated integrated circuit in order to assess its performance. The transmitting circuit consists of a low-voltage control logic, pulse-triggered level shifters and a differential output stage that generates...... conditions is 0.936 mW including the load. The integrated circuits measured prove to be consistent and robust to local process variations by measurements....

  5. Linear integrated circuits

    CERN Document Server

    Carr, Joseph

    1996-01-01

    The linear IC market is large and growing, as is the demand for well trained technicians and engineers who understand how these devices work and how to apply them. Linear Integrated Circuits provides in-depth coverage of the devices and their operation, but not at the expense of practical applications in which linear devices figure prominently. This book is written for a wide readership from FE and first degree students, to hobbyists and professionals.Chapter 1 offers a general introduction that will provide students with the foundations of linear IC technology. From chapter 2 onwa

  6. Carbon Nanotube Self-Gating Diode and Application in Integrated Circuits.

    Science.gov (United States)

    Si, Jia; Liu, Lijun; Wang, Fanglin; Zhang, Zhiyong; Peng, Lian-Mao

    2016-07-26

    A nano self-gating diode (SGD) based on nanoscale semiconducting material is proposed, simulated, and realized on semiconducting carbon nanotubes (CNTs) through a doping-free fabrication process. The relationships between the performance and material/structural parameters of the SGD are explored through numerical simulation and verified by experiment results. Based on these results, performance optimization strategy is outlined, and high performance CNT SGDs are fabricated and demonstrated to surpass other published CNT diodes. In particular the CNT SGD exhibits high rectifier factor of up to 1.4 × 10(6) while retains large on-state current. Benefiting from high yield and stability, CNT SGDs are used for constructing logic and analog integrated circuits. Two kinds of basic digital gates (AND and OR) have been realized on chip through using CNT SGDs and on-chip Ti wire resistances, and a full wave rectifier circuit has been demonstrated through using two CNT SGDs. Although demonstrated here using CNT SGDs, this device structure may in principle be implemented using other semiconducting nanomaterials, to provide ideas and building blocks for electronic applications based on nanoscale materials.

  7. InP-based three-dimensional photonic integrated circuits

    Science.gov (United States)

    Tsou, Diana; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volumes require high data communication bandwidth over longer distances than short wavelength (850 nm) multi-mode fiber systems can provide. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low cost, high-speed laser modules at 1310 and 1550 nm wavelengths are required. The great success of GaAs 850 nm VCSELs for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with available intrinsic materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits, which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits (PICs) have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform for fabricating InP-based photonic integrated circuits compatible with surface-emitting laser technology. Employing InP transparency at 1310 and 1550 nm wavelengths, we have created 3-D photonic integrated circuits (PICs) by utilizing light beams in both surface normal and in-plane directions within the InP-based structure

  8. Integrated Circuits for Analog Signal Processing

    CERN Document Server

    2013-01-01

      This book presents theory, design methods and novel applications for integrated circuits for analog signal processing.  The discussion covers a wide variety of active devices, active elements and amplifiers, working in voltage mode, current mode and mixed mode.  This includes voltage operational amplifiers, current operational amplifiers, operational transconductance amplifiers, operational transresistance amplifiers, current conveyors, current differencing transconductance amplifiers, etc.  Design methods and challenges posed by nanometer technology are discussed and applications described, including signal amplification, filtering, data acquisition systems such as neural recording, sensor conditioning such as biomedical implants, actuator conditioning, noise generators, oscillators, mixers, etc.   Presents analysis and synthesis methods to generate all circuit topologies from which the designer can select the best one for the desired application; Includes design guidelines for active devices/elements...

  9. Thermionic integrated circuits: electronics for hostile environments

    International Nuclear Information System (INIS)

    Lynn, D.K.; McCormick, J.B.; MacRoberts, M.D.J.; Wilde, D.K.; Dooley, G.R.; Brown, D.R.

    1985-01-01

    Thermionic integrated circuits combine vacuum tube technology with integrated circuit techniques to form integrated vacuum triode circuits. These circuits are capable of extended operation in both high-temperature and high-radiation environments

  10. Plasmonic nanopatch array for optical integrated circuit applications.

    Science.gov (United States)

    Qu, Shi-Wei; Nie, Zai-Ping

    2013-11-08

    Future plasmonic integrated circuits with the capability of extremely high-speed data processing at optical frequencies will be dominated by the efficient optical emission (excitation) from (of) plasmonic waveguides. Towards this goal, plasmonic nanoantennas, currently a hot topic in the field of plasmonics, have potential to bridge the mismatch between the wave vector of free-space photonics and that of the guided plasmonics. To manipulate light at will, plasmonic nanoantenna arrays will definitely be more efficient than isolated nanoantennas. In this article, the concepts of microwave antenna arrays are applied to efficiently convert plasmonic waves in the plasmonic waveguides into free-space optical waves or vice versa. The proposed plasmonic nanoantenna array, with nanopatch antennas and a coupled wedge plasmon waveguide, can also act as an efficient spectrometer to project different wavelengths into different directions, or as a spatial filter to absorb a specific wavelength at a specified incident angle.

  11. Variational integrators for electric circuits

    International Nuclear Information System (INIS)

    Ober-Blöbaum, Sina; Tao, Molei; Cheng, Mulin; Owhadi, Houman; Marsden, Jerrold E.

    2013-01-01

    In this contribution, we develop a variational integrator for the simulation of (stochastic and multiscale) electric circuits. When considering the dynamics of an electric circuit, one is faced with three special situations: 1. The system involves external (control) forcing through external (controlled) voltage sources and resistors. 2. The system is constrained via the Kirchhoff current (KCL) and voltage laws (KVL). 3. The Lagrangian is degenerate. Based on a geometric setting, an appropriate variational formulation is presented to model the circuit from which the equations of motion are derived. A time-discrete variational formulation provides an iteration scheme for the simulation of the electric circuit. Dependent on the discretization, the intrinsic degeneracy of the system can be canceled for the discrete variational scheme. In this way, a variational integrator is constructed that gains several advantages compared to standard integration tools for circuits; in particular, a comparison to BDF methods (which are usually the method of choice for the simulation of electric circuits) shows that even for simple LCR circuits, a better energy behavior and frequency spectrum preservation can be observed using the developed variational integrator

  12. Implantable neurotechnologies: a review of integrated circuit neural amplifiers.

    Science.gov (United States)

    Ng, Kian Ann; Greenwald, Elliot; Xu, Yong Ping; Thakor, Nitish V

    2016-01-01

    Neural signal recording is critical in modern day neuroscience research and emerging neural prosthesis programs. Neural recording requires the use of precise, low-noise amplifier systems to acquire and condition the weak neural signals that are transduced through electrode interfaces. Neural amplifiers and amplifier-based systems are available commercially or can be designed in-house and fabricated using integrated circuit (IC) technologies, resulting in very large-scale integration or application-specific integrated circuit solutions. IC-based neural amplifiers are now used to acquire untethered/portable neural recordings, as they meet the requirements of a miniaturized form factor, light weight and low power consumption. Furthermore, such miniaturized and low-power IC neural amplifiers are now being used in emerging implantable neural prosthesis technologies. This review focuses on neural amplifier-based devices and is presented in two interrelated parts. First, neural signal recording is reviewed, and practical challenges are highlighted. Current amplifier designs with increased functionality and performance and without penalties in chip size and power are featured. Second, applications of IC-based neural amplifiers in basic science experiments (e.g., cortical studies using animal models), neural prostheses (e.g., brain/nerve machine interfaces) and treatment of neuronal diseases (e.g., DBS for treatment of epilepsy) are highlighted. The review concludes with future outlooks of this technology and important challenges with regard to neural signal amplification.

  13. Graphene radio frequency receiver integrated circuit.

    Science.gov (United States)

    Han, Shu-Jen; Garcia, Alberto Valdes; Oida, Satoshi; Jenkins, Keith A; Haensch, Wilfried

    2014-01-01

    Graphene has attracted much interest as a future channel material in radio frequency electronics because of its superior electrical properties. Fabrication of a graphene integrated circuit without significantly degrading transistor performance has proven to be challenging, posing one of the major bottlenecks to compete with existing technologies. Here we present a fabrication method fully preserving graphene transistor quality, demonstrated with the implementation of a high-performance three-stage graphene integrated circuit. The circuit operates as a radio frequency receiver performing signal amplification, filtering and downconversion mixing. All circuit components are integrated into 0.6 mm(2) area and fabricated on 200 mm silicon wafers, showing the unprecedented graphene circuit complexity and silicon complementary metal-oxide-semiconductor process compatibility. The demonstrated circuit performance allow us to use graphene integrated circuit to perform practical wireless communication functions, receiving and restoring digital text transmitted on a 4.3-GHz carrier signal.

  14. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array-Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique.

    Science.gov (United States)

    Yang, Chen; Li, Bingyi; Chen, Liang; Wei, Chunpeng; Xie, Yizhuang; Chen, He; Yu, Wenyue

    2017-06-24

    With the development of satellite load technology and very large scale integrated (VLSI) circuit technology, onboard real-time synthetic aperture radar (SAR) imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS) SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT), which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array-application-specific integrated circuit (FPGA-ASIC) hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS) technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  15. A Spaceborne Synthetic Aperture Radar Partial Fixed-Point Imaging System Using a Field- Programmable Gate Array−Application-Specific Integrated Circuit Hybrid Heterogeneous Parallel Acceleration Technique

    Directory of Open Access Journals (Sweden)

    Chen Yang

    2017-06-01

    Full Text Available With the development of satellite load technology and very large scale integrated (VLSI circuit technology, onboard real-time synthetic aperture radar (SAR imaging systems have become a solution for allowing rapid response to disasters. A key goal of the onboard SAR imaging system design is to achieve high real-time processing performance with severe size, weight, and power consumption constraints. In this paper, we analyse the computational burden of the commonly used chirp scaling (CS SAR imaging algorithm. To reduce the system hardware cost, we propose a partial fixed-point processing scheme. The fast Fourier transform (FFT, which is the most computation-sensitive operation in the CS algorithm, is processed with fixed-point, while other operations are processed with single precision floating-point. With the proposed fixed-point processing error propagation model, the fixed-point processing word length is determined. The fidelity and accuracy relative to conventional ground-based software processors is verified by evaluating both the point target imaging quality and the actual scene imaging quality. As a proof of concept, a field- programmable gate array−application-specific integrated circuit (FPGA-ASIC hybrid heterogeneous parallel accelerating architecture is designed and realized. The customized fixed-point FFT is implemented using the 130 nm complementary metal oxide semiconductor (CMOS technology as a co-processor of the Xilinx xc6vlx760t FPGA. A single processing board requires 12 s and consumes 21 W to focus a 50-km swath width, 5-m resolution stripmap SAR raw data with a granularity of 16,384 × 16,384.

  16. Ultra-low power integrated circuit design circuits, systems, and applications

    CERN Document Server

    Li, Dongmei; Wang, Zhihua

    2014-01-01

    This book describes the design of CMOS circuits for ultra-low power consumption including analog, radio frequency (RF), and digital signal processing circuits (DSP). The book addresses issues from circuit and system design to production design, and applies the ultra-low power circuits described to systems for digital hearing aids and capsule endoscope devices. Provides a valuable introduction to ultra-low power circuit design, aimed at practicing design engineers; Describes all key building blocks of ultra-low power circuits, from a systems perspective; Applies circuits and systems described to real product examples such as hearing aids and capsule endoscopes.

  17. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Derbenwick, G.F.; Hughes, R.C.

    1977-01-01

    Electronic circuits that operate properly after exposure to ionizing radiation are necessary for nuclear weapon systems, satellites, and apparatus designed for use in radiation environments. The program to develop and theoretically model radiation-tolerant integrated circuit components has resulted in devices that show an improvement in hardness up to a factor of ten thousand over earlier devices. An inverter circuit produced functions properly after an exposure of 10 6 Gy (Si) which, as far as is known, is the record for an integrated circuit

  18. Design and application of multilayer monolithic microwave integrated circuit transformers

    Energy Technology Data Exchange (ETDEWEB)

    Economides, S.B

    1999-07-01

    The design and performance of planar spiral transformers, using multilayer GaAs and silicon MMIC technology, are presented. This multilayer technology gives new opportunities for improving the performance of planar transformers, couplers and baluns. Planar transformers have high parasitic resistance and capacitance and low levels of coupling. Using multilayer technology these problems are overcome by applying a multilayer structure of three metal layers separated by two polyimide dielectric layers. The improvements gained by placing the conductors on different metal layers, and using conductors raised on polyimide layers for low capacitance, have been investigated. The circuits were fabricated using a novel experimental fabrication process, which uses entirely standard materials and techniques and is compatible with BJT's and silicon-germanium HBT's. The transformers were all characterised up to 20 GHz using RF-on-wafer measurements. They demonstrated good performance, considering the experimental nature of in-house multilayer technology and the difficulties in simulating these three-dimensional new geometries. With high resistivity substrates, the silicon components achieved virtually the same performance as their gallium arsenide counterparts. The transformers were then used in simulations of transformer-coupled HBT amplifier circuits, to demonstrate their capabilities. It was shown that these circuits present good performance compared to standard off-the shelf component circuits and are very promising for use in most multilayer MMIC applications. The structures were further used in coupling configurations, and applied in balun circuits and pushpull amplifiers. The spiral transformer coupler can operate at low frequencies without using up much chip area. In a balun configuration, the balun can compensate for coupling and phase imbalance and operates over 5 to 15 GHz. The spiral coupler does not always need multilayer processing, so the balun may be

  19. Photonic integrated circuits : a new approach to laser technology

    NARCIS (Netherlands)

    Piramidowicz, R.; Stopinski, S.T.; Lawniczuk, K.; Welikow, K.; Szczepanski, P.; Leijtens, X.J.M.; Smit, M.K.

    2012-01-01

    In this work a brief review on photonic integrated circuits (PICs) is presented with a specific focus on integrated lasers and amplifiers. The work presents the history of development of the integration technology in photonics and its comparison to microelectronics. The major part of the review is

  20. Investigation for connecting waveguide in off-planar integrated circuits.

    Science.gov (United States)

    Lin, Jie; Feng, Zhifang

    2017-09-01

    The transmission properties of a vertical waveguide connected by different devices in off-planar integrated circuits are designed, investigated, and analyzed in detail by the finite-difference time-domain method. The results show that both guide bandwidth and transmission efficiency can be adjusted effectively by shifting the vertical waveguide continuously. Surprisingly, the wide guide band (0.385[c/a]∼0.407[c/a]) and well transmission (-6  dB) are observed simultaneously in several directions when the vertical waveguide is located at a specific location. The results are very important for all-optical integrated circuits, especially in compact integration.

  1. Medium-scale carbon nanotube thin-film integrated circuits on flexible plastic substrates.

    Science.gov (United States)

    Cao, Qing; Kim, Hoon-sik; Pimparkar, Ninad; Kulkarni, Jaydeep P; Wang, Congjun; Shim, Moonsub; Roy, Kaushik; Alam, Muhammad A; Rogers, John A

    2008-07-24

    The ability to form integrated circuits on flexible sheets of plastic enables attributes (for example conformal and flexible formats and lightweight and shock resistant construction) in electronic devices that are difficult or impossible to achieve with technologies that use semiconductor wafers or glass plates as substrates. Organic small-molecule and polymer-based materials represent the most widely explored types of semiconductors for such flexible circuitry. Although these materials and those that use films or nanostructures of inorganics have promise for certain applications, existing demonstrations of them in circuits on plastic indicate modest performance characteristics that might restrict the application possibilities. Here we report implementations of a comparatively high-performance carbon-based semiconductor consisting of sub-monolayer, random networks of single-walled carbon nanotubes to yield small- to medium-scale integrated digital circuits, composed of up to nearly 100 transistors on plastic substrates. Transistors in these integrated circuits have excellent properties: mobilities as high as 80 cm(2) V(-1) s(-1), subthreshold slopes as low as 140 m V dec(-1), operating voltages less than 5 V together with deterministic control over the threshold voltages, on/off ratios as high as 10(5), switching speeds in the kilohertz range even for coarse (approximately 100-microm) device geometries, and good mechanical flexibility-all with levels of uniformity and reproducibility that enable high-yield fabrication of integrated circuits. Theoretical calculations, in contexts ranging from heterogeneous percolative transport through the networks to compact models for the transistors to circuit level simulations, provide quantitative and predictive understanding of these systems. Taken together, these results suggest that sub-monolayer films of single-walled carbon nanotubes are attractive materials for flexible integrated circuits, with many potential areas of

  2. Monolithic microwave integrated circuit with integral array antenna

    International Nuclear Information System (INIS)

    Stockton, R.J.; Munson, R.E.

    1984-01-01

    A monolithic microwave integrated circuit including an integral array antenna. The system includes radiating elements, feed network, phasing network, active and/or passive semiconductor devices, digital logic interface circuits and a microcomputer controller simultaneously incorporated on a single substrate by means of a controlled fabrication process sequence

  3. 3D circuit integration for Vertex and other detectors

    Energy Technology Data Exchange (ETDEWEB)

    Yarema, Ray; /Fermilab

    2007-09-01

    High Energy Physics continues to push the technical boundaries for electronics. There is no area where this is truer than for vertex detectors. Lower mass and power along with higher resolution and radiation tolerance are driving forces. New technologies such as SOI CMOS detectors and three dimensional (3D) integrated circuits offer new opportunities to meet these challenges. The fundamentals for SOI CMOS detectors and 3D integrated circuits are discussed. Examples of each approach for physics applications are presented. Cost issues and ways to reduce development costs are discussed.

  4. Deeply-etched DBR mirrors for photonic integrated circuits and tunable lasers

    NARCIS (Netherlands)

    Docter, B.

    2009-01-01

    Deeply-etched Distributed Bragg Reflector (DBR) mirrors are a new versatile building block for Photonic Integrated Circuits that allows us to create more complex circuits for optical telecommunication applications. The DBR mirrors increase the device design flexibility because the mirrors can be

  5. Radio-frequency integrated-circuit engineering

    CERN Document Server

    Nguyen, Cam

    2015-01-01

    Radio-Frequency Integrated-Circuit Engineering addresses the theory, analysis and design of passive and active RFIC's using Si-based CMOS and Bi-CMOS technologies, and other non-silicon based technologies. The materials covered are self-contained and presented in such detail that allows readers with only undergraduate electrical engineering knowledge in EM, RF, and circuits to understand and design RFICs. Organized into sixteen chapters, blending analog and microwave engineering, Radio-Frequency Integrated-Circuit Engineering emphasizes the microwave engineering approach for RFICs. Provide

  6. Silicon-based optical integrated circuits for terabit communication networks

    International Nuclear Information System (INIS)

    Svidzinsky, K K

    2003-01-01

    A brief review is presented of the development of silicon-based optical integrated circuits used as components in modern all-optical communication networks with the terabit-per-second transmission capacity. The designs and technologies for manufacturing these circuits are described and the problems related to their development and application in WDM communication systems are considered. (special issue devoted to the memory of academician a m prokhorov)

  7. Insulator photocurrents: Application to dose rate hardening of CMOS/SOI integrated circuits

    International Nuclear Information System (INIS)

    Dupont-Nivet, E.; Coiec, Y.M.; Flament, O.; Tinel, F.

    1998-01-01

    Irradiation of insulators with a pulse of high energy x-rays can induce photocurrents in the interconnections of integrated circuits. The authors present, here, a new method to measure and analyze this effect together with a simple model. They also demonstrate that these insulator photocurrents have to be taken into account to obtain high levels of dose-rate hardness with CMOS on SOI integrated circuits, especially flip-flops or memory blocks of ASICs. They show that it explains some of the upsets observed in a SRAM embedded in an ASIC

  8. Substrate optimization for integrated circuit antennas

    OpenAIRE

    Alexopoulos, N. G.; Katehi, P. B.; Rutledge, D. B.

    1982-01-01

    Imaging systems in microwaves, millimeter and submillimeter wave applications employ printed circuit antenna elements. The effect of substrate properties is analyzed in this paper by both reciprocity theorem as well as integral equation approach for infinitesimally short as well as finite length dipole and slot elements. Radiation efficiency and substrate surface wave guidance is studied for practical substrate materials as GaAs, Silicon, Quartz and Duroid.

  9. High-precision analog circuit technology for power supply integrated circuits; Dengen IC yo koseido anarogu kairo gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Nakamori, A.; Suzuki, T.; Mizoe, K. [Fuji Electric Corporate Research and Development,Ltd., Kanagawa (Japan)

    2000-08-10

    With the recent rapid spread of portable electronic appliances, specification requirements such as compact power supply and long operation with batteries have become severer. Power supply ICs (integrated circuits) are required to reduce power consumption in the circuit and perform high-precision control. To meet these requirements, Fuji Electric develops high-precision CMOS (complementary metal-oxide semiconductor) analog technology. This paper describes three analog circuit technologies of a voltage reference, an operational amplifier and a comparator as circuit components particularly important for the precision of power supply ICs. (author)

  10. Experimental Device for Learning of Logical Circuit Design using Integrated Circuits

    OpenAIRE

    石橋, 孝昭

    2012-01-01

    This paper presents an experimental device for learning of logical circuit design using integrated circuits and breadboards. The experimental device can be made at a low cost and can be used for many subjects such as logical circuits, computer engineering, basic electricity, electrical circuits and electronic circuits. The proposed device is effective to learn the logical circuits than the usual lecture.

  11. Monolithic Microwave Integrated Circuit (MMIC) technology for space communications applications

    Science.gov (United States)

    Connolly, Denis J.; Bhasin, Kul B.; Romanofsky, Robert R.

    1987-01-01

    Future communications satellites are likely to use gallium arsenide (GaAs) monolithic microwave integrated-circuit (MMIC) technology in most, if not all, communications payload subsystems. Multiple-scanning-beam antenna systems are expected to use GaAs MMIC's to increase functional capability, to reduce volume, weight, and cost, and to greatly improve system reliability. RF and IF matrix switch technology based on GaAs MMIC's is also being developed for these reasons. MMIC technology, including gigabit-rate GaAs digital integrated circuits, offers substantial advantages in power consumption and weight over silicon technologies for high-throughput, on-board baseband processor systems. For the more distant future pseudomorphic indium gallium arsenide (InGaAs) and other advanced III-V materials offer the possibility of MMIC subsystems well up into the millimeter wavelength region. All of these technology elements are in NASA's MMIC program. Their status is reviewed.

  12. Commercialisation of CMOS Integrated Circuit Technology in Multi-Electrode Arrays for Neuroscience and Cell-Based Biosensors

    Directory of Open Access Journals (Sweden)

    Chris R. Bowen

    2011-05-01

    Full Text Available The adaptation of standard integrated circuit (IC technology as a transducer in cell-based biosensors in drug discovery pharmacology, neural interface systems and electrophysiology requires electrodes that are electrochemically stable, biocompatible and affordable. Unfortunately, the ubiquitous Complementary Metal Oxide Semiconductor (CMOS IC technology does not meet the first of these requirements. For devices intended only for research, modification of CMOS by post-processing using cleanroom facilities has been achieved. However, to enable adoption of CMOS as a basis for commercial biosensors, the economies of scale of CMOS fabrication must be maintained by using only low-cost post-processing techniques. This review highlights the methodologies employed in cell-based biosensor design where CMOS-based integrated circuits (ICs form an integral part of the transducer system. Particular emphasis will be placed on the application of multi-electrode arrays for in vitro neuroscience applications. Identifying suitable IC packaging methods presents further significant challenges when considering specific applications. The various challenges and difficulties are reviewed and some potential solutions are presented.

  13. Semiconductors integrated circuit design for manufacturability

    CERN Document Server

    Balasinki, Artur

    2011-01-01

    Because of the continuous evolution of integrated circuit manufacturing (ICM) and design for manufacturability (DfM), most books on the subject are obsolete before they even go to press. That's why the field requires a reference that takes the focus off of numbers and concentrates more on larger economic concepts than on technical details. Semiconductors: Integrated Circuit Design for Manufacturability covers the gradual evolution of integrated circuit design (ICD) as a basis to propose strategies for improving return-on-investment (ROI) for ICD in manufacturing. Where most books put the spotl

  14. A full feature FASTBUS slave interface using semicustom integrated circuits

    International Nuclear Information System (INIS)

    Skegg, R.; Daviel, A.; Downing, R.

    1986-01-01

    Two semi-custom integrated circuits have been designed and manufactured which enable the construction of a full featured FASTBUS slave interface without the need for a detailed knowledge of the FASTBUS protocol. A relatively small amount of board space is required compared to implementations using conventional circuits. The semi-custom devices are described in detail, and an application example is given. (orig.)

  15. Design of Integrated Circuits Approaching Terahertz Frequencies

    DEFF Research Database (Denmark)

    Yan, Lei

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also...... heterodyne receivers with requirements of room temperature operation, low system complexity, and high sensitivity, monolithic integrated Schottky diode technology is chosen for the implementation of submillimeterwave components. The corresponding subharmonic mixer and multiplier for a THz radiometer system...

  16. Semiconductor integrated circuits

    International Nuclear Information System (INIS)

    Michel, A.E.; Schwenker, R.O.; Ziegler, J.F.

    1979-01-01

    An improved method involving ion implantation to form non-epitaxial semiconductor integrated circuits. These are made by forming a silicon substrate of one conductivity type with a recessed silicon dioxide region extending into the substrate and enclosing a portion of the silicon substrate. A beam of ions of opposite conductivity type impurity is directed at the substrate at an energy and dosage level sufficient to form a first region of opposite conductivity within the silicon dioxide region. This impurity having a concentration peak below the surface of the substrate forms a region of the one conductivity type which extends from the substrate surface into the first opposite type region to a depth between the concentration peak and the surface and forms a second region of opposite conductivity type. The method, materials and ion beam conditions are detailed. Vertical bipolar integrated circuits can be made this way when the first opposite type conductivity region will function as a collector. Also circuits with inverted bipolar devices when this first region functions as a 'buried'' emitter region. (U.K.)

  17. Silicon integrated circuit process

    International Nuclear Information System (INIS)

    Lee, Jong Duck

    1985-12-01

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  18. Silicon integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Jong Duck

    1985-12-15

    This book introduces the process of silicon integrated circuit. It is composed of seven parts, which are oxidation process, diffusion process, ion implantation process such as ion implantation equipment, damage, annealing and influence on manufacture of integrated circuit and device, chemical vapor deposition process like silicon Epitaxy LPCVD and PECVD, photolithography process, including a sensitizer, spin, harden bake, reflection of light and problems related process, infrared light bake, wet-etch, dry etch, special etch and problems of etching, metal process like metal process like metal-silicon connection, aluminum process, credibility of aluminum and test process.

  19. Design of analog integrated circuits and systems

    CERN Document Server

    Laker, Kenneth R

    1994-01-01

    This text is designed for senior or graduate level courses in analog integrated circuits or design of analog integrated circuits. This book combines consideration of CMOS and bipolar circuits into a unified treatment. Also included are CMOS-bipolar circuits made possible by BiCMOS technology. The text progresses from MOS and bipolar device modelling to simple one and two transistor building block circuits. The final two chapters present a unified coverage of sample-data and continuous-time signal processing systems.

  20. Miniaturized Ultrasound Imaging Probes Enabled by CMUT Arrays with Integrated Frontend Electronic Circuits

    Science.gov (United States)

    Khuri-Yakub, B. (Pierre) T.; Oralkan, Ömer; Nikoozadeh, Amin; Wygant, Ira O.; Zhuang, Steve; Gencel, Mustafa; Choe, Jung Woo; Stephens, Douglas N.; de la Rama, Alan; Chen, Peter; Lin, Feng; Dentinger, Aaron; Wildes, Douglas; Thomenius, Kai; Shivkumar, Kalyanam; Mahajan, Aman; Seo, Chi Hyung; O’Donnell, Matthew; Truong, Uyen; Sahn, David J.

    2010-01-01

    Capacitive micromachined ultrasonic transducer (CMUT) arrays are conveniently integrated with frontend integrated circuits either monolithically or in a hybrid multichip form. This integration helps with reducing the number of active data processing channels for 2D arrays. This approach also preserves the signal integrity for arrays with small elements. Therefore CMUT arrays integrated with electronic circuits are most suitable to implement miniaturized probes required for many intravascular, intracardiac, and endoscopic applications. This paper presents examples of miniaturized CMUT probes utilizing 1D, 2D, and ring arrays with integrated electronics. PMID:21097106

  1. Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Arun Kaintura

    2018-02-01

    Full Text Available Advances in manufacturing process technology are key ensembles for the production of integrated circuits in the sub-micrometer region. It is of paramount importance to assess the effects of tolerances in the manufacturing process on the performance of modern integrated circuits. The polynomial chaos expansion has emerged as a suitable alternative to standard Monte Carlo-based methods that are accurate, but computationally cumbersome. This paper provides an overview of the most recent developments and challenges in the application of polynomial chaos-based techniques for uncertainty quantification in integrated circuits, with particular focus on high-dimensional problems.

  2. A CMOS integrated timing discriminator circuit for fast scintillation counters

    International Nuclear Information System (INIS)

    Jochmann, M.W.

    1998-01-01

    Based on a zero-crossing discriminator using a CR differentiation network for pulse shaping, a new CMOS integrated timing discriminator circuit is proposed for fast (t r ≥ 2 ns) scintillation counters at the cooler synchrotron COSY-Juelich. By eliminating the input signal's amplitude information by means of an analog continuous-time divider, a normalized pulse shape at the zero-crossing point is gained over a wide dynamic input amplitude range. In combination with an arming comparator and a monostable multivibrator this yields in a highly precise timing discriminator circuit, that is expected to be useful in different time measurement applications. First measurement results of a CMOS integrated logarithmic amplifier, which is part of the analog continuous-time divider, agree well with the corresponding simulations. Moreover, SPICE simulations of the integrated discriminator circuit promise a time walk well below 200 ps (FWHM) over a 40 dB input amplitude dynamic range

  3. Flexible and low-voltage integrated circuits constructed from high-performance nanocrystal transistors.

    Science.gov (United States)

    Kim, David K; Lai, Yuming; Diroll, Benjamin T; Murray, Christopher B; Kagan, Cherie R

    2012-01-01

    Colloidal semiconductor nanocrystals are emerging as a new class of solution-processable materials for low-cost, flexible, thin-film electronics. Although these colloidal inks have been shown to form single, thin-film field-effect transistors with impressive characteristics, the use of multiple high-performance nanocrystal field-effect transistors in large-area integrated circuits has not been shown. This is needed to understand and demonstrate the applicability of these discrete nanocrystal field-effect transistors for advanced electronic technologies. Here we report solution-deposited nanocrystal integrated circuits, showing nanocrystal integrated circuit inverters, amplifiers and ring oscillators, constructed from high-performance, low-voltage, low-hysteresis CdSe nanocrystal field-effect transistors with electron mobilities of up to 22 cm(2) V(-1) s(-1), current modulation >10(6) and subthreshold swing of 0.28 V dec(-1). We fabricated the nanocrystal field-effect transistors and nanocrystal integrated circuits from colloidal inks on flexible plastic substrates and scaled the devices to operate at low voltages. We demonstrate that colloidal nanocrystal field-effect transistors can be used as building blocks to construct complex integrated circuits, promising a viable material for low-cost, flexible, large-area electronics.

  4. RF microwave circuit design for wireless applications

    CERN Document Server

    Rohde, Ulrich L

    2012-01-01

    Provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling the newest IC technologies Revised and completely updated, RF/Microwave Circuit Design for Wireless Applications, Second Edition is a unique, state-of-the-art guide to wireless integrated circuit design that provides researchers and engineers with a complete set of modeling, design, and implementation tools for tackling even the newest IC technologies. It emphasizes practical design solutions for high-performance devices and circuitry, incorporating ample exa

  5. Performance of an optical encoder based on a nondiffractive beam implemented with a specific photodetection integrated circuit and a diffractive optical element.

    Science.gov (United States)

    Quintián, Fernando Perez; Calarco, Nicolás; Lutenberg, Ariel; Lipovetzky, José

    2015-09-01

    In this paper, we study the incremental signal produced by an optical encoder based on a nondiffractive beam (NDB). The NDB is generated by means of a diffractive optical element (DOE). The detection system is composed by an application specific integrated circuit (ASIC) sensor. The sensor consists of an array of eight concentric annular photodiodes, each one provided with a programmable gain amplifier. In this way, the system is able to synthesize a nonuniform detectivity. The contrast, amplitude, and harmonic content of the sinusoidal output signal are analyzed. The influence of the cross talk among the annular photodiodes is placed in evidence through the dependence of the signal contrast on the wavelength.

  6. A High-Performance Application Specific Integrated Circuit for Electrical and Neurochemical Traumatic Brain Injury Monitoring.

    Science.gov (United States)

    Pagkalos, Ilias; Rogers, Michelle L; Boutelle, Martyn G; Drakakis, Emmanuel M

    2018-05-22

    This paper presents the first application specific integrated chip (ASIC) for the monitoring of patients who have suffered a Traumatic Brain Injury (TBI). By monitoring the neurophysiological (ECoG) and neurochemical (glucose, lactate and potassium) signals of the injured human brain tissue, it is possible to detect spreading depolarisations, which have been shown to be associated with poor TBI patient outcome. This paper describes the testing of a new 7.5 mm 2 ASIC fabricated in the commercially available AMS 0.35 μm CMOS technology. The ASIC has been designed to meet the demands of processing the injured brain tissue's ECoG signals, recorded by means of depth or brain surface electrodes, and neurochemical signals, recorded using microdialysis coupled to microfluidics-based electrochemical biosensors. The potentiostats use switchedcapacitor charge integration to record currents with 100 fA resolution, and allow automatic gain changing to track the falling sensitivity of a biosensor. This work supports the idea of a "behind the ear" wireless microplatform modality, which could enable the monitoring of currently non-monitored mobile TBI patients for the onset of secondary brain injury. ©2018 The Authors. Published by Wiley-VCH Verlag GmbH & Co. KGaA.

  7. Active components for integrated plasmonic circuits

    DEFF Research Database (Denmark)

    Krasavin, A.V.; Bolger, P.M.; Zayats, A.V.

    2009-01-01

    We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides.......We present a comprehensive study of highly efficient and compact passive and active components for integrated plasmonic circuit based on dielectric-loaded surface plasmon polariton waveguides....

  8. Thermally-induced voltage alteration for integrated circuit analysis

    Energy Technology Data Exchange (ETDEWEB)

    Cole, E.I. Jr.

    2000-06-20

    A thermally-induced voltage alteration (TIVA) apparatus and method are disclosed for analyzing an integrated circuit (IC) either from a device side of the IC or through the IC substrate to locate any open-circuit or short-circuit defects therein. The TIVA apparatus uses constant-current biasing of the IC while scanning a focused laser beam over electrical conductors (i.e. a patterned metallization) in the IC to produce localized heating of the conductors. This localized heating produces a thermoelectric potential due to the Seebeck effect in any conductors with open-circuit defects and a resistance change in any conductors with short-circuit defects, both of which alter the power demand by the IC and thereby change the voltage of a source or power supply providing the constant-current biasing. By measuring the change in the supply voltage and the position of the focused and scanned laser beam over time, any open-circuit or short-circuit defects in the IC can be located and imaged. The TIVA apparatus can be formed in part from a scanning optical microscope, and has applications for qualification testing or failure analysis of ICs.

  9. The RD53A Integrated Circuit

    CERN Document Server

    Garcia-Sciveres, Maurice

    2017-01-01

    Implementation details for the RD53A pixel readout integrated circuit designed by the RD53 Collaboration. This is a companion to the specifications document and will eventually become a reference for chip users. RD53A is not intended to be a final production IC for use in an experiment, and contains design variations for testing purposes, making the pixel matrix non-uniform. The chip size is 20.0 mm by 11.8 mm.

  10. Integrated optical circuits for numerical computation

    Science.gov (United States)

    Verber, C. M.; Kenan, R. P.

    1983-01-01

    The development of integrated optical circuits (IOC) for numerical-computation applications is reviewed, with a focus on the use of systolic architectures. The basic architecture criteria for optical processors are shown to be the same as those proposed by Kung (1982) for VLSI design, and the advantages of IOCs over bulk techniques are indicated. The operation and fabrication of electrooptic grating structures are outlined, and the application of IOCs of this type to an existing 32-bit, 32-Mbit/sec digital correlator, a proposed matrix multiplier, and a proposed pipeline processor for polynomial evaluation is discussed. The problems arising from the inherent nonlinearity of electrooptic gratings are considered. Diagrams and drawings of the application concepts are provided.

  11. Biosignal integrated circuit with simultaneous acquisition of ECG and PPG for wearable healthcare applications.

    Science.gov (United States)

    Kim, Hyungseup; Park, Yunjong; Ko, Youngwoon; Mun, Yeongjin; Lee, Sangmin; Ko, Hyoungho

    2018-01-01

    Wearable healthcare systems require measurements from electrocardiograms (ECGs) and photoplethysmograms (PPGs), and the blood pressure of the user. The pulse transit time (PTT) can be calculated by measuring the ECG and PPG simultaneously. Continuous-time blood pressure without using an air cuff can be estimated by using the PTT. This paper presents a biosignal acquisition integrated circuit (IC) that can simultaneously measure the ECG and PPG for wearable healthcare applications. Included in this biosignal acquisition circuit are a voltage mode instrumentation amplifier (IA) for ECG acquisition and a current mode transimpedance amplifier for PPG acquisition. The analog outputs from the ECG and PPG channels are muxed and converted to digital signals using 12-bit successive approximation register (SAR) analog-to-digital converter (ADC). The proposed IC is fabricated by using a standard 0.18 μm CMOS process with an active area of 14.44 mm2. The total current consumption for the multichannel IC is 327 μA with a 3.3 V supply. The measured input referred noise of ECG readout channel is 1.3 μVRMS with a bandwidth of 0.5 Hz to 100 Hz. And the measured input referred current noise of the PPG readout channel is 0.122 nA/√Hz with a bandwidth of 0.5 Hz to 100 Hz. The proposed IC, which is implemented using various circuit techniques, can measure ECG and PPG signals simultaneously to calculate the PTT for wearable healthcare applications.

  12. Silicon integrated circuits part A : supplement 2

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Applied Solid State Science, Supplement 2: Silicon Integrated Circuits, Part A focuses on MOS device physics. This book is divided into three chapters-physics of the MOS transistor; nonvolatile memories; and properties of silicon-on-sapphire substrates devices, and integrated circuits. The topics covered include the short channel effects, MOSFET structures, floating gate devices, technology for nonvolatile semiconductor memories, sapphire substrates, and SOS integrated circuits and systems. The MOS capacitor, MIOS devices, and SOS process and device technology are also deliberated. This public

  13. Thermally-isolated silicon-based integrated circuits and related methods

    Science.gov (United States)

    Wojciechowski, Kenneth; Olsson, Roy H.; Clews, Peggy J.; Bauer, Todd

    2017-05-09

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  14. Method of making thermally-isolated silicon-based integrated circuits

    Science.gov (United States)

    Wojciechowski, Kenneth; Olsson, Roy; Clews, Peggy J.; Bauer, Todd

    2017-11-21

    Thermally isolated devices may be formed by performing a series of etches on a silicon-based substrate. As a result of the series of etches, silicon material may be removed from underneath a region of an integrated circuit (IC). The removal of the silicon material from underneath the IC forms a gap between remaining substrate and the integrated circuit, though the integrated circuit remains connected to the substrate via a support bar arrangement that suspends the integrated circuit over the substrate. The creation of this gap functions to release the device from the substrate and create a thermally-isolated integrated circuit.

  15. Development of 3D integrated circuits for HEP

    International Nuclear Information System (INIS)

    Yarema, R.; Fermilab

    2006-01-01

    Three dimensional integrated circuits are well suited to improving circuit bandwidth and increasing effective circuit density. Recent advances in industry have made 3D integrated circuits an option for HEP. The 3D technology is discussed in this paper and several examples are shown. Design of a 3D demonstrator chip for the ILC is presented

  16. Disposable photonic integrated circuits for evanescent wave sensors by ultra-high volume roll-to-roll method.

    Science.gov (United States)

    Aikio, Sanna; Hiltunen, Jussi; Hiitola-Keinänen, Johanna; Hiltunen, Marianne; Kontturi, Ville; Siitonen, Samuli; Puustinen, Jarkko; Karioja, Pentti

    2016-02-08

    Flexible photonic integrated circuit technology is an emerging field expanding the usage possibilities of photonics, particularly in sensor applications, by enabling the realization of conformable devices and introduction of new alternative production methods. Here, we demonstrate that disposable polymeric photonic integrated circuit devices can be produced in lengths of hundreds of meters by ultra-high volume roll-to-roll methods on a flexible carrier. Attenuation properties of hundreds of individual devices were measured confirming that waveguides with good and repeatable performance were fabricated. We also demonstrate the applicability of the devices for the evanescent wave sensing of ambient refractive index. The production of integrated photonic devices using ultra-high volume fabrication, in a similar manner as paper is produced, may inherently expand methods of manufacturing low-cost disposable photonic integrated circuits for a wide range of sensor applications.

  17. Phased-array-based photonic integrated circuits for wavelength division multiplexing applications

    NARCIS (Netherlands)

    Staring, A.A.M.; Smit, M.K.

    1997-01-01

    Wavelength division multiplexing (WDM) technology provides many options to the design of flexible all-optical networks. In order to exploit these options to their full potential, photonic integrated circuits (PICs) for wavelength routing and switching will be indispensable. One of the basic building

  18. Semi-custom integrated circuit amplifier and level discriminator for nuclear and space instruments

    International Nuclear Information System (INIS)

    Hahn, S.F.; Cafferty, M.M.

    1991-01-01

    This paper reports on the development an extra fast current feedback amplifier and a level discriminator employing a dielectrically-isolated bipolar, semi-custom Application Specific Integrated Circuit (ASIC) process. These devices are specifically designed for instruments aboard spacecrafts or in portable packages requiring low power and weight. The amplifier adopts current feedback for a unity-gain bandwidth of 90 MHz while consuming 50 mW. The level discriminator uses a complementary output driver for balanced positive and negative response times. The power consumption of these devices can be programmed by external resistors for optimal speed and power trade-off

  19. Semi-custom integrated circuit amplifier and level discriminator for nuclear and space instruments

    International Nuclear Information System (INIS)

    Hahn, S.F.; Cafferty, M.M.

    1990-01-01

    This paper reports an extra fast current feedback amplifier and a level discriminator developed employing a dielectrically isolated bipolar, semi-custom Application Specific Integrated Circuit (ASIC) process. These devices are specifically designed for instruments aboard spacecrafts or in portable packages requiring low power and weight. The amplifier adopts current feedback for a unity- gain bandwidth of 90 MHz while consuming 50 mW. The level discriminator uses a complementary output driver for balanced positive and negative response times. The power consumption of these devices can be programmed by external resistors for optimal speed and power trade-off

  20. A Fault Tolerant Integrated Circuit Memory

    OpenAIRE

    Barton, Anthony Francis

    1980-01-01

    Most commercially produced integrated circuits are incapable of tolerating manufacturing defects. The area and function of the circuits is thus limited by the probability of faults occurring within the circuit. This thesis examines techniques for using redundancy in memory circuits to provide fault tolerance and to increase storage capacity. A hierarchical memory architecture using multiple Hamming codes is introduced and analysed to determine its resistance to manufa...

  1. Flexible, Photopatterned, Colloidal CdSe Semiconductor Nanocrystal Integrated Circuits

    Science.gov (United States)

    Stinner, F. Scott

    As semiconductor manufacturing pushes towards smaller and faster transistors, a parallel goal exists to create transistors which are not nearly as small. These transistors are not intended to match the performance of traditional crystalline semiconductors; they are designed to be significantly lower in cost and manufactured using methods that can make them physically flexible for applications where form is more important than speed. One of the developing technologies for this application is semiconductor nanocrystals. We first explore methods to develop CdSe nanocrystal semiconducting "inks" into large-scale, high-speed integrated circuits. We demonstrate photopatterned transistors with mobilities of 10 cm2/Vs on Kapton substrates. We develop new methods for vertical interconnect access holes to demonstrate multi-device integrated circuits including inverting amplifiers with 7 kHz bandwidths, ring oscillators with NFC) link. The device draws its power from the NFC transmitter common on smartphones and eliminates the need for a fixed battery. This allows for the mass deployment of flexible, interactive displays on product packaging.

  2. Arithmetic circuits for DSP applications

    CERN Document Server

    Stouraitis, Thanos

    2017-01-01

    Arithmetic Circuits for DSP Applications is a complete resource on arithmetic circuits for digital signal processing (DSP). It covers the key concepts, designs and developments of different types of arithmetic circuits, which can be used for improving the efficiency of implementation of a multitude of DSP applications. Each chapter includes various applications of the respective class of arithmetic circuits along with information on the future scope of research. Written for students, engineers, and researchers in electrical and computer engineering, this comprehensive text offers a clear understanding of different types of arithmetic circuits used for digital signal processing applications. The text includes contributions from noted researchers on a wide range of topics, including a review o circuits used in implementing basic operations like additions and multiplications; distributed arithmetic as a technique for the multiplier-less implementation of inner products for DSP applications; discussions on look ...

  3. INTEGRATED SENSOR EVALUATION CIRCUIT AND METHOD FOR OPERATING SAID CIRCUIT

    OpenAIRE

    Krüger, Jens; Gausa, Dominik

    2015-01-01

    WO15090426A1 Sensor evaluation device and method for operating said device Integrated sensor evaluation circuit for evaluating a sensor signal (14) received from a sensor (12), having a first connection (28a) for connection to the sensor and a second connection (28b) for connection to the sensor. The integrated sensor evaluation circuit comprises a configuration data memory (16) for storing configuration data which describe signal properties of a plurality of sensor control signals (26a-c). T...

  4. Hybdrid integral circuit for proportional chambers

    International Nuclear Information System (INIS)

    Yanik, R.; Khudy, M.; Povinets, P.; Strmen', P.; Grabachek, Z.; Feshchenko, A.A.

    1978-01-01

    Outlined briefly are a hybrid integrated circuit of the channel. One channel contains an input amplifier, delay circuit, and memory register on the base of the D-type flip-flop and controlled by the recording gate pulse. Provided at the output of the channel is a readout gating circuit. Presented are the flowsheet of the channel, the shaper amplifier and logical channel. At present the logical circuit was accepted for manufacture

  5. Integrated circuits, and design and manufacture thereof

    Science.gov (United States)

    Auracher, Stefan; Pribbernow, Claus; Hils, Andreas

    2006-04-18

    A representation of a macro for an integrated circuit layout. The representation may define sub-circuit cells of a module. The module may have a predefined functionality. The sub-circuit cells may include at least one reusable circuit cell. The reusable circuit cell may be configured such that when the predefined functionality of the module is not used, the reusable circuit cell is available for re-use.

  6. Integrated optical circuit comprising a polarization convertor

    NARCIS (Netherlands)

    1998-01-01

    An integrated optical circuit includes a first device and a second device, which devices are connected by a polarization convertor. The polarization convertor includes a curved section of a waveguide, integrated in the optical circuit. The curved section may have several differently curved

  7. Transistor and integrated circuit manufacture

    Energy Technology Data Exchange (ETDEWEB)

    Colman, D

    1978-09-27

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry.

  8. Integrated circuit devices in control systems of coal mining complexes

    Energy Technology Data Exchange (ETDEWEB)

    1983-01-01

    Systems of automatic monitoring and control of coal mining complexes developed in the 1960's used electromagnetic relays, thyristors, and flip-flops on transistors of varying conductivity. The circuits' designers, devoted much attention to ensuring spark safety, lowering power consumption, and raising noise immunity and repairability of functional devices. The fast development of integrated circuitry led to the use of microelectronic components in most devices of mine automation. An analysis of specifications and experimental research into integrated circuits (IMS) shows that the series K 176 IMS components made by CMOS technology best meet mine conditions of operation. The use of IMS devices under mine conditions has demonstrated their high reliability. Further development of integrated circuitry involve using microprocessors and microcomputers. (SC)

  9. Transistor and integrated circuit manufacture

    International Nuclear Information System (INIS)

    Colman, D.

    1978-01-01

    This invention relates to the manufacture of transistors and integrated circuits by ion bombardment techniques and is particularly, but not exclusively, of value in the manufacture of so-called integrated injection logic circuitry. (author)

  10. Design of 3D integrated circuits and systems

    CERN Document Server

    Sharma, Rohit

    2014-01-01

    Three-dimensional (3D) integration of microsystems and subsystems has become essential to the future of semiconductor technology development. 3D integration requires a greater understanding of several interconnected systems stacked over each other. While this vertical growth profoundly increases the system functionality, it also exponentially increases the design complexity. Design of 3D Integrated Circuits and Systems tackles all aspects of 3D integration, including 3D circuit and system design, new processes and simulation techniques, alternative communication schemes for 3D circuits and sys

  11. Diamond electro-optomechanical resonators integrated in nanophotonic circuits

    Energy Technology Data Exchange (ETDEWEB)

    Rath, P.; Ummethala, S.; Pernice, W. H. P., E-mail: wolfram.pernice@kit.edu [Institute of Nanotechnology, Karlsruhe Institute of Technology, 76344 Eggenstein-Leopoldshafen (Germany); Diewald, S. [Center for Functional Nanostructures, Karlsruhe Institute of Technology, 76131 Karlsruhe (Germany); Lewes-Malandrakis, G.; Brink, D.; Heidrich, N.; Nebel, C. [Fraunhofer Institute for Applied Solid State Physics, Tullastr. 72, 79108 Freiburg (Germany)

    2014-12-22

    Diamond integrated photonic devices are promising candidates for emerging applications in nanophotonics and quantum optics. Here, we demonstrate active modulation of diamond nanophotonic circuits by exploiting mechanical degrees of freedom in free-standing diamond electro-optomechanical resonators. We obtain high quality factors up to 9600, allowing us to read out the driven nanomechanical response with integrated optical interferometers with high sensitivity. We are able to excite higher order mechanical modes up to 115 MHz and observe the nanomechanical response also under ambient conditions.

  12. Computer-aided engineering of semiconductor integrated circuits

    Science.gov (United States)

    Meindl, J. D.; Dutton, R. W.; Gibbons, J. F.; Helms, C. R.; Plummer, J. D.; Tiller, W. A.; Ho, C. P.; Saraswat, K. C.; Deal, B. E.; Kamins, T. I.

    1980-07-01

    Economical procurement of small quantities of high performance custom integrated circuits for military systems is impeded by inadequate process, device and circuit models that handicap low cost computer aided design. The principal objective of this program is to formulate physical models of fabrication processes, devices and circuits to allow total computer-aided design of custom large-scale integrated circuits. The basic areas under investigation are (1) thermal oxidation, (2) ion implantation and diffusion, (3) chemical vapor deposition of silicon and refractory metal silicides, (4) device simulation and analytic measurements. This report discusses the fourth year of the program.

  13. Design of Integrated Circuits Approaching Terahertz Frequencies

    OpenAIRE

    Yan, Lei; Johansen, Tom Keinicke

    2013-01-01

    In this thesis, monolithic microwave integrated circuits(MMICs) are presented for millimeter-wave and submillimeter-wave or terahertz(THz) applications. Millimeter-wave power generation from solid state devices is not only crucial for the emerging high data rate wireless communications but also important for driving THz signal sources. To meet the requirement of high output power, amplifiers based on InP double heterojunction bipolar transistor (DHBT) devices from the III-V Lab in Marcoussic,...

  14. Integrated circuit cooled turbine blade

    Science.gov (United States)

    Lee, Ching-Pang; Jiang, Nan; Um, Jae Y.; Holloman, Harry; Koester, Steven

    2017-08-29

    A turbine rotor blade includes at least two integrated cooling circuits that are formed within the blade that include a leading edge circuit having a first cavity and a second cavity and a trailing edge circuit that includes at least a third cavity located aft of the second cavity. The trailing edge circuit flows aft with at least two substantially 180-degree turns at the tip end and the root end of the blade providing at least a penultimate cavity and a last cavity. The last cavity is located along a trailing edge of the blade. A tip axial cooling channel connects to the first cavity of the leading edge circuit and the penultimate cavity of the trailing edge circuit. At least one crossover hole connects the penultimate cavity to the last cavity substantially near the tip end of the blade.

  15. Monolithically Integrated Flexible Black Phosphorus Complementary Inverter Circuits.

    Science.gov (United States)

    Liu, Yuanda; Ang, Kah-Wee

    2017-07-25

    Two-dimensional (2D) inverters are a fundamental building block for flexible logic circuits which have previously been realized by heterogeneously wiring transistors with two discrete channel materials. Here, we demonstrate a monolithically integrated complementary inverter made using a homogeneous black phosphorus (BP) nanosheet on flexible substrates. The digital logic inverter circuit is demonstrated via effective threshold voltage tuning within a single BP material, which offers both electron and hole dominated conducting channels with nearly symmetric pinch-off and current saturation. Controllable electron concentration is achieved by accurately modulating the aluminum (Al) donor doping, which realizes BP n-FET with a room-temperature on/off ratio >10 3 . Simultaneously, work function engineering is employed to obtain a low Schottky barrier contact electrode that facilities hole injection, thus enhancing the current density of the BP p-FET by 9.4 times. The flexible inverter circuit shows a clear digital logic voltage inversion operation along with a larger-than-unity direct current voltage gain, while exhibits alternating current dynamic signal switching at a record high frequency up to 100 kHz and remarkable electrical stability upon mechanical bending with a radii as small as 4 mm. Our study demonstrates a practical monolithic integration strategy for achieving functional logic circuits on one material platform, paving the way for future high-density flexible electronic applications.

  16. Gigahertz flexible graphene transistors for microwave integrated circuits.

    Science.gov (United States)

    Yeh, Chao-Hui; Lain, Yi-Wei; Chiu, Yu-Chiao; Liao, Chen-Hung; Moyano, David Ricardo; Hsu, Shawn S H; Chiu, Po-Wen

    2014-08-26

    Flexible integrated circuits with complex functionalities are the missing link for the active development of wearable electronic devices. Here, we report a scalable approach to fabricate self-aligned graphene microwave transistors for the implementation of flexible low-noise amplifiers and frequency mixers, two fundamental building blocks of a wireless communication receiver. A devised AlOx T-gate structure is used to achieve an appreciable increase of device transconductance and a commensurate reduction of the associated parasitic resistance, thus yielding a remarkable extrinsic cutoff frequency of 32 GHz and a maximum oscillation frequency of 20 GHz; in both cases the operation frequency is an order of magnitude higher than previously reported. The two frequencies work at 22 and 13 GHz even when subjected to a strain of 2.5%. The gigahertz microwave integrated circuits demonstrated here pave the way for applications which require high flexibility and radio frequency operations.

  17. High-precision high-sensitivity clock recovery circuit for a mobile payment application

    International Nuclear Information System (INIS)

    Sun Lichong; Yan Na; Min Hao; Ren Wenliang

    2011-01-01

    This paper presents a fully integrated carrier clock recovery circuit for a mobile payment application. The architecture is based on a sampling-detection module and a charge pump phase locked loop. Compared with clock recovery in conventional 13.56 MHz transponders, this circuit can recover a high-precision consecutive carrier clock from the on/off keying (OOK) signal sent by interrogators. Fabricated by a SMIC 0.18-μm EEPROM CMOS process, this chip works from a single power supply as low as 1.5 V Measurement results show that this circuit provides 0.34% frequency deviation and 8 mV sensitivity. (semiconductor integrated circuits)

  18. A High-Temperature Piezoresistive Pressure Sensor with an Integrated Signal-Conditioning Circuit

    Directory of Open Access Journals (Sweden)

    Zong Yao

    2016-06-01

    Full Text Available This paper focuses on the design and fabrication of a high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit, which consists of an encapsulated pressure-sensitive chip, a temperature compensation circuit and a signal-conditioning circuit. A silicon on insulation (SOI material and a standard MEMS process are used in the pressure-sensitive chip fabrication, and high-temperature electronic components are adopted in the temperature-compensation and signal-conditioning circuits. The entire pressure sensor achieves a hermetic seal and can be operated long-term in the range of −50 °C to 220 °C. Unlike traditional pressure sensor output voltage ranges (in the dozens to hundreds of millivolts, the output voltage of this sensor is from 0 V to 5 V, which can significantly improve the signal-to-noise ratio and measurement accuracy in practical applications of long-term transmission based on experimental verification. Furthermore, because this flexible sensor’s output voltage is adjustable, general follow-up pressure transmitter devices for voltage converters need not be used, which greatly reduces the cost of the test system. Thus, the proposed high-temperature piezoresistive pressure sensor with an integrated signal-conditioning circuit is expected to be highly applicable to pressure measurements in harsh environments.

  19. Method of manufacturing Josephson junction integrated circuits

    International Nuclear Information System (INIS)

    Jillie, D.W. Jr.; Smith, L.N.

    1985-01-01

    Josephson junction integrated circuits of the current injection type and magnetically controlled type utilize a superconductive layer that forms both Josephson junction electrode for the Josephson junction devices on the integrated circuit as well as a ground plane for the integrated circuit. Large area Josephson junctions are utilized for effecting contact to lower superconductive layers and islands are formed in superconductive layers to provide isolation between the groudplane function and the Josephson junction electrode function as well as to effect crossovers. A superconductor-barrier-superconductor trilayer patterned by local anodization is also utilized with additional layers formed thereover. Methods of manufacturing the embodiments of the invention are disclosed

  20. Design and testing of integrated circuits for reactor protection channels

    International Nuclear Information System (INIS)

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.; Rana, I.

    1995-01-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. Purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing

  1. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Directory of Open Access Journals (Sweden)

    Heck Martijn J.R.

    2016-06-01

    Full Text Available Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  2. Highly integrated optical phased arrays: photonic integrated circuits for optical beam shaping and beam steering

    Science.gov (United States)

    Heck, Martijn J. R.

    2017-01-01

    Technologies for efficient generation and fast scanning of narrow free-space laser beams find major applications in three-dimensional (3D) imaging and mapping, like Lidar for remote sensing and navigation, and secure free-space optical communications. The ultimate goal for such a system is to reduce its size, weight, and power consumption, so that it can be mounted on, e.g. drones and autonomous cars. Moreover, beam scanning should ideally be done at video frame rates, something that is beyond the capabilities of current opto-mechanical systems. Photonic integrated circuit (PIC) technology holds the promise of achieving low-cost, compact, robust and energy-efficient complex optical systems. PICs integrate, for example, lasers, modulators, detectors, and filters on a single piece of semiconductor, typically silicon or indium phosphide, much like electronic integrated circuits. This technology is maturing fast, driven by high-bandwidth communications applications, and mature fabrication facilities. State-of-the-art commercial PICs integrate hundreds of elements, and the integration of thousands of elements has been shown in the laboratory. Over the last few years, there has been a considerable research effort to integrate beam steering systems on a PIC, and various beam steering demonstrators based on optical phased arrays have been realized. Arrays of up to thousands of coherent emitters, including their phase and amplitude control, have been integrated, and various applications have been explored. In this review paper, I will present an overview of the state of the art of this technology and its opportunities, illustrated by recent breakthroughs.

  3. Radiation-hardened CMOS integrated circuits

    International Nuclear Information System (INIS)

    Pikor, A.; Reiss, E.M.

    1980-01-01

    Substantial effort has been directed at radiation-hardening CMOS integrated circuits using various oxide processes. While most of these integrated circuits have been successful in demonstrating megarad hardness, further investigations have shown that the 'wet-oxide process' is most compatible with the RCA CD4000 Series process. This article describes advances in the wet-oxide process that have resulted in multimegarad hardness and yield to MIL-M-38510 screening requirements. The implementation of these advances into volume manufacturing is geared towards supplying devices for aerospace requirements such as the Defense Meterological Satellite program (DMSP) and the Global Positioning Satellite (GPS). (author)

  4. Highly efficient integrated rectifier and voltage boosting circuits for energy harvesting applications

    Directory of Open Access Journals (Sweden)

    D. Maurath

    2008-05-01

    Full Text Available This paper presents novel circuit concepts for integrated rectifiers and voltage converting interfaces for energy harvesting micro-generators. In the context of energy harvesting, usually only small voltages are supplied by vibration-driven generators. Therefore, rectification with minimum voltage losses and low reverse currents is an important issue. This is realized by novel integrated rectifiers which were fabricated and are presented in this article. Additionally, there is a crucial need for dynamic load adaptation as well as voltage up-conversion. A circuit concept is presented, which is able to obtain both requirements. This generator interface adapts its input impedance for an optimal energy transfer efficiency. Furthermore, this generator interface provides implicit voltage up-conversion, whereas the generator output energy is stored on a buffer, which is connected to the output of the voltage converting interface. As simulations express, this fully integrated converter is able to boost ac-voltages greater than |0.35 V| to an output dc-voltage of 2.0 V–2.5 V. Thereby, high harvesting efficiencies above 80% are possible within the entire operational range.

  5. Fully Integrated Solar Energy Harvester and Sensor Interface Circuits for Energy-Efficient Wireless Sensing Applications

    Directory of Open Access Journals (Sweden)

    Maher Kayal

    2013-02-01

    Full Text Available This paper presents an energy-efficient solar energy harvesting and sensing microsystem that harvests solar energy from a micro-power photovoltaic module for autonomous operation of a gas sensor. A fully integrated solar energy harvester stores the harvested energy in a rechargeable NiMH microbattery. Hydrogen concentration and temperature are measured and converted to a digital value with 12-bit resolution using a fully integrated sensor interface circuit, and a wireless transceiver is used to transmit the measurement results to a base station. As the harvested solar energy varies considerably in different lighting conditions, in order to guarantee autonomous operation of the sensor, the proposed area- and energy-efficient circuit scales the power consumption and performance of the sensor. The power management circuit dynamically decreases the operating frequency of digital circuits and bias currents of analog circuits in the sensor interface circuit and increases the idle time of the transceiver under reduced light intensity. The proposed microsystem has been implemented in a 0.18 µm complementary metal-oxide-semiconductor (CMOS process and occupies a core area of only 0.25 mm2. This circuit features a low power consumption of 2.1 µW when operating at its highest performance. It operates with low power supply voltage in the 0.8V to 1.6 V range.

  6. Integrated circuit design using design automation

    International Nuclear Information System (INIS)

    Gwyn, C.W.

    1976-09-01

    Although the use of computer aids to develop integrated circuits is relatively new at Sandia, the program has been very successful. The results have verified the utility of the in-house CAD design capability. Custom IC's have been developed in much shorter times than available through semiconductor device manufacturers. In addition, security problems were minimized and a saving was realized in circuit cost. The custom CMOS IC's were designed at less than half the cost of designing with conventional techniques. In addition to the computer aided design, the prototype fabrication and testing capability provided by the semiconductor development laboratory and microelectronics computer network allows the circuits to be fabricated and evaluated before the designs are transferred to the commercial semiconductor manufacturers for production. The Sandia design and prototype fabrication facilities provide the capability of complete custom integrated circuit development entirely within the ERDA laboratories

  7. Post irradiation effects (PIE) in integrated circuits

    International Nuclear Information System (INIS)

    Barnes, C.E.; Shaw, D.C.; Fleetwood, D.M.; Winokur, P.S.

    1992-01-01

    Post Irradiation Effects (PIE) ranging from normal recovery catastrophic failure have been observed in integrated circuits during the PIE period. These variations indicate that a rebound or PIE recipe used for radiation hardness assurance must be chosen with care. In this paper, the authors provide examples of PIE in a variety of integrated circuits of importance to spacecraft electronics

  8. Integrated microchannel cooling in a three dimensional integrated circuit: A thermal management

    Directory of Open Access Journals (Sweden)

    Wang Kang-Jia

    2016-01-01

    Full Text Available Microchannel cooling is a promising technology for solving the three-dimensional integrated circuit thermal problems. However, the relationship between the microchannel cooling parameters and thermal behavior of the three dimensional integrated circuit is complex and difficult to understand. In this paper, we perform a detailed evaluation of the influence of the microchannel structure and the parameters of the cooling liquid on steady-state temperature profiles. The results presented in this paper are expected to aid in the development of thermal design guidelines for three dimensional integrated circuit with microchannel cooling.

  9. Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits

    Science.gov (United States)

    2017-03-01

    Despite all actions and concerns, this problem continues to escalate due to offshore fabrication of the integrated circuits ICs [1]. In order to...diagnosis and fault isolation in ICs, as well as the characterization of the functionality of ICs including malicious circuitry. Integrated circuits ...Innovative Magnetic-Field Array Probe for TRUST Integrated Circuits   contains the RF-switch matrix and broad-band (BB) low noise amplifiers (LNAs

  10. An integrated circuit switch

    Science.gov (United States)

    Bonin, E. L.

    1969-01-01

    Multi-chip integrated circuit switch consists of a GaAs photon-emitting diode in close proximity with S1 phototransistor. A high current gain is obtained when the transistor has a high forward common-emitter current gain.

  11. Wide-band polarization controller for Si photonic integrated circuits.

    Science.gov (United States)

    Velha, P; Sorianello, V; Preite, M V; De Angelis, G; Cassese, T; Bianchi, A; Testa, F; Romagnoli, M

    2016-12-15

    A circuit for the management of any arbitrary polarization state of light is demonstrated on an integrated silicon (Si) photonics platform. This circuit allows us to adapt any polarization into the standard fundamental TE mode of a Si waveguide and, conversely, to control the polarization and set it to any arbitrary polarization state. In addition, the integrated thermal tuning allows kilohertz speed which can be used to perform a polarization scrambler. The circuit was used in a WDM link and successfully used to adapt four channels into a standard Si photonic integrated circuit.

  12. Development of high speed integrated circuit for very high resolution timing measurements

    International Nuclear Information System (INIS)

    Mester, Christian

    2009-10-01

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  13. Development of high speed integrated circuit for very high resolution timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Mester, Christian

    2009-10-15

    A multi-channel high-precision low-power time-to-digital converter application specific integrated circuit for high energy physics applications has been designed and implemented in a 130 nm CMOS process. To reach a target resolution of 24.4 ps, a novel delay element has been conceived. This nominal resolution has been experimentally verified with a prototype, with a minimum resolution of 19 ps. To further improve the resolution, a new interpolation scheme has been described. The ASIC has been designed to use a reference clock with the LHC bunch crossing frequency of 40 MHz and generate all required timing signals internally, to ease to use within the framework of an LHC upgrade. Special care has been taken to minimise the power consumption. (orig.)

  14. [Flexible print circuit technology application in biomedical engineering].

    Science.gov (United States)

    Jiang, Lihua; Cao, Yi; Zheng, Xiaolin

    2013-06-01

    Flexible print circuit (FPC) technology has been widely applied in variety of electric circuits with high precision due to its advantages, such as low-cost, high specific fabrication ability, and good flexibility, etc. Recently, this technology has also been used in biomedical engineering, especially in the development of microfluidic chip and microelectrode array. The high specific fabrication can help making microelectrode and other micro-structure equipment. And good flexibility allows the micro devices based on FPC technique to be easily packaged with other parts. In addition, it also reduces the damage of microelectrodes to the tissue. In this paper, the application of FPC technology in biomedical engineering is introduced. Moreover, the important parameters of FPC technique and the development trend of prosperous applications is also discussed.

  15. Universal discrete Fourier optics RF photonic integrated circuit architecture.

    Science.gov (United States)

    Hall, Trevor J; Hasan, Mehedi

    2016-04-04

    This paper describes a coherent electro-optic circuit architecture that generates a frequency comb consisting of N spatially separated orders using a generalised Mach-Zenhder interferometer (MZI) with its N × 1 combiner replaced by an optical N × N Discrete Fourier Transform (DFT). Advantage may be taken of the tight optical path-length control, component and circuit symmetries and emerging trimming algorithms offered by photonic integration in any platform that offers linear electro-optic phase modulation such as LiNbO3, silicon, III-V or hybrid technology. The circuit architecture subsumes all MZI-based RF photonic circuit architectures in the prior art given an appropriate choice of output port(s) and dimension N although the principal application envisaged is phase correlated subcarrier generation for all optical orthogonal frequency division multiplexing. A transfer matrix approach is used to model the operation of the architecture. The predictions of the model are validated by simulations performed using an industry standard software tool. Implementation is found to be practical.

  16. Mouldable all-carbon integrated circuits.

    Science.gov (United States)

    Sun, Dong-Ming; Timmermans, Marina Y; Kaskela, Antti; Nasibulin, Albert G; Kishimoto, Shigeru; Mizutani, Takashi; Kauppinen, Esko I; Ohno, Yutaka

    2013-01-01

    A variety of plastic products, ranging from those for daily necessities to electronics products and medical devices, are produced by moulding techniques. The incorporation of electronic circuits into various plastic products is limited by the brittle nature of silicon wafers. Here we report mouldable integrated circuits for the first time. The devices are composed entirely of carbon-based materials, that is, their active channels and passive elements are all fabricated from stretchable and thermostable assemblies of carbon nanotubes, with plastic polymer dielectric layers and substrates. The all-carbon thin-film transistors exhibit a mobility of 1,027 cm(2) V(-1) s(-1) and an ON/OFF ratio of 10(5). The devices also exhibit extreme biaxial stretchability of up to 18% when subjected to thermopressure forming. We demonstrate functional integrated circuits that can be moulded into a three-dimensional dome. Such mouldable electronics open new possibilities by allowing for the addition of electronic/plastic-like functionalities to plastic/electronic products, improving their designability.

  17. Characterization of Novel Thin-Films and Structures for Integrated Circuit and Photovoltaic Applications

    Science.gov (United States)

    Zhao, Zhao

    Thin films have been widely used in various applications. This research focuses on the characterization of novel thin films in the integrated circuits and photovoltaic techniques. The ion implanted layer in silicon can be treated as ion implanted thin film, which plays an essential role in the integrated circuits fabrication. Novel rapid annealing methods, i.e. microwave annealing and laser annealing, are conducted to activate ion dopants and repair the damages, and then are compared with the conventional rapid thermal annealing (RTA). In terms of As+ and P+ implanted Si, the electrical and structural characterization confirms that the microwave and laser annealing can achieve more efficient dopant activation and recrystallization than conventional RTA. The efficient dopant activation in microwave annealing is attributed to ion hopping under microwave field, while the liquid phase growth in laser annealing provides its efficient dopant activation. The characterization of dopants diffusion shows no visible diffusion after microwave annealing, some extent of end range of diffusion after RTA, and significant dopant diffusion after laser annealing. For photovoltaic applications, an indium-free novel three-layer thin-film structure (transparent composited electrode (TCE)) is demonstrated as a promising transparent conductive electrode for solar cells. The characterization of TCE mainly focuses on its optical and electrical properties. Transfer matrix method for optical transmittance calculation is validated and proved to be a desirable method for predicting transmittance of TCE containing continuous metal layer, and can estimate the trend of transmittance as the layer thickness changes. TiO2/Ag/TiO2 (TAgT) electrode for organic solar cells (OSCs) is then designed using numerical simulation and shows much higher Haacke figure of merit than indium tin oxide (ITO). In addition, TAgT based OSC shows better performance than ITO based OSC when compatible hole transfer layer

  18. Test and Diagnosis of Integrated Circuits

    OpenAIRE

    Bosio , Alberto

    2015-01-01

    The ever-increasing growth of the semiconductor market results in an increasing complexity of digital circuits. Smaller, faster, cheaper and low-power consumption are the main challenges in semiconductor industry. The reduction of transistor size and the latest packaging technology (i.e., System-On-a-Chip, System-In-Package, Trough Silicon Via 3D Integrated Circuits) allows the semiconductor industry to satisfy the latest challenges. Although producing such advanced circuits can benefit users...

  19. On-chip synthesis of circularly polarized emission of light with integrated photonic circuits.

    Science.gov (United States)

    He, Li; Li, Mo

    2014-05-01

    The helicity of circularly polarized (CP) light plays an important role in the light-matter interaction in magnetic and quantum material systems. Exploiting CP light in integrated photonic circuits could lead to on-chip integration of novel optical helicity-dependent devices for applications ranging from spintronics to quantum optics. In this Letter, we demonstrate a silicon photonic circuit coupled with a 2D grating emitter operating at a telecom wavelength to synthesize vertically emitting, CP light from a quasi-TE waveguide mode. Handedness of the emitted circular polarized light can be thermally controlled with an integrated microheater. The compact device footprint enables a small beam diameter, which is desirable for large-scale integration.

  20. Metal contact engineering and registration-free fabrication of complementary metal-oxide semiconductor integrated circuits using aligned carbon nanotubes.

    Science.gov (United States)

    Wang, Chuan; Ryu, Koungmin; Badmaev, Alexander; Zhang, Jialu; Zhou, Chongwu

    2011-02-22

    Complementary metal-oxide semiconductor (CMOS) operation is very desirable for logic circuit applications as it offers rail-to-rail swing, larger noise margin, and small static power consumption. However, it remains to be a challenging task for nanotube-based devices. Here in this paper, we report our progress on metal contact engineering for n-type nanotube transistors and CMOS integrated circuits using aligned carbon nanotubes. By using Pd as source/drain contacts for p-type transistors, small work function metal Gd as source/drain contacts for n-type transistors, and evaporated SiO(2) as a passivation layer, we have achieved n-type transistor, PN diode, and integrated CMOS inverter with an air-stable operation. Compared with other nanotube n-doping techniques, such as potassium doping, PEI doping, hydrazine doping, etc., using low work function metal contacts for n-type nanotube devices is not only air stable but also integrated circuit fabrication compatible. Moreover, our aligned nanotube platform for CMOS integrated circuits shows significant advantage over the previously reported individual nanotube platforms with respect to scalability and reproducibility and suggests a practical and realistic approach for nanotube-based CMOS integrated circuit applications.

  1. Integrated differential high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Farch, Kjartan

    2015-01-01

    In this paper an integrated differential high-voltage transmitting circuit for capacitive micromachined ultrasonic transducers (CMUTs) used in portable ultrasound scanners is designed and implemented in a 0.35 μm high-voltage process. Measurements are performed on the integrated circuit in order...... to assess its performance. The circuit generates pulses at differential voltage levels of 60V, 80V and 100 V, a frequency up to 5MHz and a measured driving strength of 1.75 V/ns with the CMUT connected. The total on-chip area occupied by the transmitting circuit is 0.18 mm2 and the power consumption...

  2. Integrated circuit structure

    International Nuclear Information System (INIS)

    1981-01-01

    The invention describes the fabrication of integrated circuit structures, such as read-only memory components of field-effect transistors, which may be fabricated and then maintained in inventory, and later selectively modified in accordance with a desired pattern. It is claimed that MOS depletion-mode devices in accordance with the invention can be fabricated at lower cost and at higher yields. (U.K.)

  3. Conductus makes high-Tc integrated circuit

    International Nuclear Information System (INIS)

    Anon.

    1991-01-01

    This paper reports that researchers at Conductus have successfully demonstrated what the company says is the world's first integrated circuit containing active devices made from high-temperature superconductors. The circuit is a SQUID magnetometer made from seven layers of material: three layers of yttrium-barium-copper oxide, two layers of insulating material, a seed layer to create grain boundaries for the Josephson junctions, and a layer of silver for making electrical contact to the device. The chip also contains vias, or pathways that make a superconducting contact between the superconducting layers otherwise separated by insulators. Conductus had previously announced the development of a SQUID magnetometer that featured a SQUID sensor and a flux transformer manufactured on separate chips. What makes this achievement important is that the company was able to put both components on the same chip, thus creating a simple integrated circuit on a single chip. This is still a long way from conventional semiconductor technology, with as many as a million components per chip, or even the sophisticated low-Tc superconducting chips made by the Japanese, but the SQUID magnetometer demonstrates all the elements and techniques necessary to build more complex high-temperature superconductor integrated circuits, making this an important first step

  4. Integral Battery Power Limiting Circuit for Intrinsically Safe Applications

    Science.gov (United States)

    Burns, Bradley M.; Blalock, Norman N.

    2010-01-01

    A circuit topology has been designed to guarantee the output of intrinsically safe power for the operation of electrical devices in a hazardous environment. This design uses a MOSFET (metal oxide semiconductor field-effect transistor) as a switch to connect and disconnect power to a load. A test current is provided through a separate path to the load for monitoring by a comparator against a preset threshold level. The circuit is configured so that the test current will detect a fault in the load and open the switch before the main current can respond. The main current passes through the switch and then an inductor. When a fault occurs in the load, the current through the inductor cannot change immediately, but the voltage drops immediately to safe levels. The comparator detects this drop and opens the switch before the current in the inductor has a chance to respond. This circuit protects both the current and voltage from exceeding safe levels. Typically, this type of protection is accomplished by a fuse or a circuit breaker, but in order for a fuse or a circuit breaker to blow or trip, the current must exceed the safe levels momentarily, which may be just enough time to ignite anything in a hazardous environment. To prevent this from happening, a fuse is typically current-limited by the addition of the resistor to keep the current within safe levels while the fuse reacts. The use of a resistor is acceptable for non-battery applications where the wasted energy and voltage drop across the resistor can be tolerated. The use of the switch and inductor minimizes the wasted energy. For example, a circuit runs from a 3.6-V battery that must be current-limited to 200 mA. If the circuit normally draws 10 mA, then an 18-ohm resistor would drop 180 mV during normal operation, while a typical switch (0.02 ohm) and inductor (0.97 ohm) would only drop 9.9 mV. From a power standpoint, the current-limiting resistor protection circuit wastes about 18 times more power than the

  5. Circuit engineering principles for construction of bipolar large-scale integrated circuit storage devices and very large-scale main memory

    Science.gov (United States)

    Neklyudov, A. A.; Savenkov, V. N.; Sergeyez, A. G.

    1984-06-01

    Memories are improved by increasing speed or the memory volume on a single chip. The most effective means for increasing speeds in bipolar memories are current control circuits with the lowest extraction times for a specific power consumption (1/4 pJ/bit). The control current circuitry involves multistage current switches and circuits accelerating transient processes in storage elements and links. Circuit principles for the design of bipolar memories with maximum speeds for an assigned minimum of circuit topology are analyzed. Two main classes of storage with current control are considered: the ECL type and super-integrated injection type storage with data capacities of N = 1/4 and N 4/16, respectively. The circuits reduce logic voltage differentials and the volumes of lexical and discharge buses and control circuit buses. The limiting speed is determined by the antiinterference requirements of the memory in storage and extraction modes.

  6. Reverse Engineering Integrated Circuits Using Finite State Machine Analysis

    Energy Technology Data Exchange (ETDEWEB)

    Oler, Kiri J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Miller, Carl H. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

    2016-04-12

    In this paper, we present a methodology for reverse engineering integrated circuits, including a mathematical verification of a scalable algorithm used to generate minimal finite state machine representations of integrated circuits.

  7. Heat management in integrated circuits on-chip and system-level monitoring and cooling

    CERN Document Server

    Ogrenci-Memik, Seda

    2016-01-01

    This essential overview covers the subject of thermal monitoring and management in integrated circuits. Specifically, it focuses on devices and materials that are intimately integrated on-chip (as opposed to in-package or on-board) for the purposes of thermal monitoring and thermal management.

  8. Micro-relay technology for energy-efficient integrated circuits

    CERN Document Server

    Kam, Hei

    2015-01-01

    This book describes the design of relay-based circuit systems from device fabrication to circuit micro-architectures. This book is ideal for both device engineers as well as circuit system designers and highlights the importance of co-design across design hierarchies when optimizing system performance (in this case, energy-efficiency). This book is ideal for researchers and engineers focused on semiconductors, integrated circuits, and energy efficient electronics. This book also: ·         Covers microsystem fabrication, MEMS device design, circuit design, circuit micro-architecture, and CAD ·         Describes work previously done in the field and also lays the groundwork and criteria for future energy-efficient device and system design ·         Maximizes reader insights into the design and modeling of micro-relay, micro-relay reliability, integrated circuit design with micro-relays, and more

  9. Study of the interaction between heavy ions and integrated circuits using a pulsed laser beam

    International Nuclear Information System (INIS)

    Lewis, D.; Fouillat, P.; Pouget, V.; Lapuyade, H.

    2002-01-01

    A new pulsed laser beam equipment dedicated to the characterization of integrated circuit is presented. Using ultra-short laser pulses is a convenient way to simulate experimentally the spatial environment of integrated circuits when interactions with heavy ions occur. This experimental set-up can be considered as a complementary tool for particle accelerators to evaluate the hardness assurance of integrated circuits for space applications. These particles generate temporally electrical disturbance called Single Event Effect (SEE). The theoretical approach of an equivalence between heavy ions and a laser pulses is discussed. The experimental set-up and some relevant operational methodologies are presented. Experimental results demonstrate that the induced electrical responses due to an heavy ion or a laser pulse are quite similar. Some sensitivity mappings of integrated circuits provided by this test bench illustrate the capabilities and the limitations of this laser-based technique. Contrary to the particle accelerators, it provides useful information concerning the spatial and temporal dependences of SEE mechanisms. (authors)

  10. Arbitrary modeling of TSVs for 3D integrated circuits

    CERN Document Server

    Salah, Khaled; El-Rouby, Alaa

    2014-01-01

    This book presents a wide-band and technology independent, SPICE-compatible RLC model for through-silicon vias (TSVs) in 3D integrated circuits. This model accounts for a variety of effects, including skin effect, depletion capacitance and nearby contact effects. Readers will benefit from in-depth coverage of concepts and technology such as 3D integration, Macro modeling, dimensional analysis and compact modeling, as well as closed form equations for the through silicon via parasitics. Concepts covered are demonstrated by using TSVs in applications such as a spiral inductor?and inductive-based

  11. Pulsed laser-induced SEU in integrated circuits

    International Nuclear Information System (INIS)

    Buchner, S.; Kang, K.; Stapor, W.J.; Campbell, A.B.; Knudson, A.R.; McDonald, P.; Rivet, S.

    1990-01-01

    The authors have used a pulsed picosecond laser to measure the threshold for single event upset (SEU) and single event latchup (SEL) for two different kinds of integrated circuits. The relative thresholds show good agreement with published ion upset data. The consistency of the results together with the advantages of using a laser system suggest that the pulsed laser can be used for SEU/SEL hardness assurance of integrated circuits

  12. Accurate Models for Evaluating the Direct Conducted and Radiated Emissions from Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Domenico Capriglione

    2018-03-01

    Full Text Available This paper deals with the electromagnetic compatibility (EMC issues related to the direct and radiated emissions from a high-speed integrated circuits (ICs. These emissions are evaluated here by means of circuital and electromagnetic models. As for the conducted emission, an equivalent circuit model is derived to describe the IC and the effect of its loads (package, printed circuit board, decaps, etc., based on the Integrated Circuit Emission Model template (ICEM. As for the radiated emission, an electromagnetic model is proposed, based on the superposition of the fields generated in the far field region by the loop currents flowing into the IC and the package pins. A custom experimental setup is designed for validating the models. Specifically, for the radiated emission measurement, a custom test board is designed and realized, able to highlight the contribution of the direct emission from the IC, usually hidden by the indirect emission coming from the printed circuit board. Measurements of the package currents and of the far-field emitted fields are carried out, providing a satisfactory agreement with the model predictions.

  13. New readout integrated circuit using continuous time fixed pattern noise correction

    Science.gov (United States)

    Dupont, Bertrand; Chammings, G.; Rapellin, G.; Mandier, C.; Tchagaspanian, M.; Dupont, Benoit; Peizerat, A.; Yon, J. J.

    2008-04-01

    LETI has been involved in IRFPA development since 1978; the design department (LETI/DCIS) has focused its work on new ROIC architecture since many years. The trend is to integrate advanced functions into the CMOS design to achieve cost efficient sensors production. Thermal imaging market is today more and more demanding of systems with instant ON capability and low power consumption. The purpose of this paper is to present the latest developments of fixed pattern noise continuous time correction. Several architectures are proposed, some are based on hardwired digital processing and some are purely analog. Both are using scene based algorithms. Moreover a new method is proposed for simultaneous correction of pixel offsets and sensitivities. In this scope, a new architecture of readout integrated circuit has been implemented; this architecture is developed with 0.18μm CMOS technology. The specification and the application of the ROIC are discussed in details.

  14. Novel Low Loss Wide-Band Multi-Port Integrated Circuit Technology for RF/Microwave Applications

    Science.gov (United States)

    Simons, Rainee N.; Goverdhanam, Kavita; Katehi, Linda P. B.; Burke, Thomas P. (Technical Monitor)

    2001-01-01

    In this paper, novel low loss, wide-band coplanar stripline technology for radio frequency (RF)/microwave integrated circuits is demonstrated on high resistivity silicon wafer. In particular, the fabrication process for the deposition of spin-on-glass (SOG) as a dielectric layer, the etching of microvias for the vertical interconnects, the design methodology for the multiport circuits and their measured/simulated characteristics are graphically illustrated. The study shows that circuits with very low loss, large bandwidth, and compact size are feasible using this technology. This multilayer planar technology has potential to significantly enhance RF/microwave IC performance when combined with semi-conductor devices and microelectromechanical systems (MEMS).

  15. Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

    Science.gov (United States)

    Leonard, Regis F. (Editor); Bhasin, Kul B. (Editor)

    1991-01-01

    Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure.

  16. Optimization of Segmentation Quality of Integrated Circuit Images

    Directory of Open Access Journals (Sweden)

    Gintautas Mušketas

    2012-04-01

    Full Text Available The paper presents investigation into the application of genetic algorithms for the segmentation of the active regions of integrated circuit images. This article is dedicated to a theoretical examination of the applied methods (morphological dilation, erosion, hit-and-miss, threshold and describes genetic algorithms, image segmentation as optimization problem. The genetic optimization of the predefined filter sequence parameters is carried out. Improvement to segmentation accuracy using a non optimized filter sequence makes 6%.Artcile in Lithuanian

  17. Lithography for enabling advances in integrated circuits and devices.

    Science.gov (United States)

    Garner, C Michael

    2012-08-28

    Because the transistor was fabricated in volume, lithography has enabled the increase in density of devices and integrated circuits. With the invention of the integrated circuit, lithography enabled the integration of higher densities of field-effect transistors through evolutionary applications of optical lithography. In 1994, the semiconductor industry determined that continuing the increase in density transistors was increasingly difficult and required coordinated development of lithography and process capabilities. It established the US National Technology Roadmap for Semiconductors and this was expanded in 1999 to the International Technology Roadmap for Semiconductors to align multiple industries to provide the complex capabilities to continue increasing the density of integrated circuits to nanometre scales. Since the 1960s, lithography has become increasingly complex with the evolution from contact printers, to steppers, pattern reduction technology at i-line, 248 nm and 193 nm wavelengths, which required dramatic improvements of mask-making technology, photolithography printing and alignment capabilities and photoresist capabilities. At the same time, pattern transfer has evolved from wet etching of features, to plasma etch and more complex etching capabilities to fabricate features that are currently 32 nm in high-volume production. To continue increasing the density of devices and interconnects, new pattern transfer technologies will be needed with options for the future including extreme ultraviolet lithography, imprint technology and directed self-assembly. While complementary metal oxide semiconductors will continue to be extended for many years, these advanced pattern transfer technologies may enable development of novel memory and logic technologies based on different physical phenomena in the future to enhance and extend information processing.

  18. Adaptive control of power supply for integrated circuits

    NARCIS (Netherlands)

    2012-01-01

    The present invention relates to a circuit arrangement and method for controlling power supply in an integrated circuit wherein at least one working parameter of at least one electrically isolated circuit region (10) is monitored, and the conductivity of a variable resistor means is locally

  19. International Conference on Integrated Optical Circuit Engineering, 1st, Cambridge, MA, October 23-25, 1984, Proceedings

    Science.gov (United States)

    Ostrowsky, D. B.; Sriram, S.

    Aspects of waveguide technology are explored, taking into account waveguide fabrication techniques in GaAs/GaAlAs, the design and fabrication of AlGaAs/GaAs phase couplers for optical integrated circuit applications, ion implanted GaAs integrated optics fabrication technology, a direct writing electron beam lithography based process for the realization of optoelectronic integrated circuits, and advances in the development of semiconductor integrated optical circuits for telecommunications. Other subjects examined are related to optical signal processing, optical switching, and questions of optical bistability and logic. Attention is given to acousto-optic techniques in integrated optics, acousto-optic Bragg diffraction in proton exchanged waveguides, optical threshold logic architectures for hybrid binary/residue processors, integrated optical modulation and switching, all-optic logic devices for waveguide optics, optoelectronic switching, high-speed photodetector switching, and a mechanical optical switch.

  20. Design and testing of integrated circuits for reactor protection channels

    International Nuclear Information System (INIS)

    Battle, R.E.; Vandermolen, R.I.; Jagadish, U.; Swail, B.K.; Naser, J.

    1995-01-01

    Custom and semicustom application-specific integrated circuit design and testing methods are investigated for use in research and commercial nuclear reactor safety systems. The Electric Power Research Institute and Oak Ridge National Laboratory are working together through a cooperative research and development agreement to apply modern technology to a nuclear reactor protection system. The purpose of this project is to demonstrate to the nuclear industry an alternative approach for new or upgrade reactor protection and safety system signal processing and voting logic. Motivation for this project stems from (1) the difficulty of proving that software-based protection systems are adequately reliable, (2) the obsolescence of the original equipment, and (3) the improved performance of digital processing. A demonstration model for protection system of PWR reactor has been designed and built

  1. Monolithic Microwave Integrated Circuits Based on GaAs Mesfet Technology

    Science.gov (United States)

    Bahl, Inder J.

    Advanced military microwave systems are demanding increased integration, reliability, radiation hardness, compact size and lower cost when produced in large volume, whereas the microwave commercial market, including wireless communications, mandates low cost circuits. Monolithic Microwave Integrated Circuit (MMIC) technology provides an economically viable approach to meeting these needs. In this paper the design considerations for several types of MMICs and their performance status are presented. Multifunction integrated circuits that advance the MMIC technology are described, including integrated microwave/digital functions and a highly integrated transceiver at C-band.

  2. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience; Conception et test d`un circuit integre (ASIC): application aux chambres multifils et aux photomultiplicateurs de l`experience GRAAL

    Energy Technology Data Exchange (ETDEWEB)

    Bugnet, H.

    1995-11-21

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs.

  3. Chip-integrated ultrawide-band all-optical logic comparator in plasmonic circuits.

    Science.gov (United States)

    Lu, Cuicui; Hu, Xiaoyong; Yang, Hong; Gong, Qihuang

    2014-01-27

    Optical computing opens up the possibility for the realization of ultrahigh-speed and ultrawide-band information processing. Integrated all-optical logic comparator is one of the indispensable core components of optical computing systems. Unfortunately, up to now, no any nanoscale all-optical logic comparator suitable for on-chip integration applications has been realized experimentally. Here, we report a subtle and effective technical solution to circumvent the obstacles of inherent Ohmic losses of metal and limited propagation length of SPPs. A nanoscale all-optical logic comparator suitable for on-chip integration applications is realized in plasmonic circuits directly. The incident single-bit (or dual-bit) logic signals can be compared and the comparison results are endowed with different logic encodings. An ultrabroad operating wavelength range from 700 to 1000 nm, and an ultrahigh output logic-state contrast-ratio of more than 25 dB are realized experimentally. No high power requirement is needed. Though nanoscale SPP light source and the logic comparator device are integrated into the same plasmonic chip, an ultrasmall feature size is maintained. This work not only paves a way for the realization of complex logic device such as adders and multiplier, but also opens up the possibility for realizing quantum solid chips based on plasmonic circuits.

  4. Nanophotonic integrated circuits from nanoresonators grown on silicon.

    Science.gov (United States)

    Chen, Roger; Ng, Kar Wei; Ko, Wai Son; Parekh, Devang; Lu, Fanglu; Tran, Thai-Truong D; Li, Kun; Chang-Hasnain, Connie

    2014-07-07

    Harnessing light with photonic circuits promises to catalyse powerful new technologies much like electronic circuits have in the past. Analogous to Moore's law, complexity and functionality of photonic integrated circuits depend on device size and performance scale. Semiconductor nanostructures offer an attractive approach to miniaturize photonics. However, shrinking photonics has come at great cost to performance, and assembling such devices into functional photonic circuits has remained an unfulfilled feat. Here we demonstrate an on-chip optical link constructed from InGaAs nanoresonators grown directly on a silicon substrate. Using nanoresonators, we show a complete toolkit of circuit elements including light emitters, photodetectors and a photovoltaic power supply. Devices operate with gigahertz bandwidths while consuming subpicojoule energy per bit, vastly eclipsing performance of prior nanostructure-based optoelectronics. Additionally, electrically driven stimulated emission from an as-grown nanostructure is presented for the first time. These results reveal a roadmap towards future ultradense nanophotonic integrated circuits.

  5. Quantum dash based single section mode locked lasers for photonic integrated circuits.

    Science.gov (United States)

    Joshi, Siddharth; Calò, Cosimo; Chimot, Nicolas; Radziunas, Mindaugas; Arkhipov, Rostislav; Barbet, Sophie; Accard, Alain; Ramdane, Abderrahim; Lelarge, Francois

    2014-05-05

    We present the first demonstration of an InAs/InP Quantum Dash based single-section frequency comb generator designed for use in photonic integrated circuits (PICs). The laser cavity is closed using a specifically designed Bragg reflector without compromising the mode-locking performance of the self pulsating laser. This enables the integration of single-section mode-locked laser in photonic integrated circuits as on-chip frequency comb generators. We also investigate the relations between cavity modes in such a device and demonstrate how the dispersion of the complex mode frequencies induced by the Bragg grating implies a violation of the equi-distance between the adjacent mode frequencies and, therefore, forbids the locking of the modes in a classical Bragg Device. Finally we integrate such a Bragg Mirror based laser with Semiconductor Optical Amplifier (SOA) to demonstrate the monolithic integration of QDash based low phase noise sources in PICs.

  6. Dual-function photonic integrated circuit for frequency octo-tupling or single-side-band modulation.

    Science.gov (United States)

    Hasan, Mehedi; Maldonado-Basilio, Ramón; Hall, Trevor J

    2015-06-01

    A dual-function photonic integrated circuit for microwave photonic applications is proposed. The circuit consists of four linear electro-optic phase modulators connected optically in parallel within a generalized Mach-Zehnder interferometer architecture. The photonic circuit is arranged to have two separate output ports. A first port provides frequency up-conversion of a microwave signal from the electrical to the optical domain; equivalently single-side-band modulation. A second port provides tunable millimeter wave carriers by frequency octo-tupling of an appropriate amplitude RF carrier. The circuit exploits the intrinsic relative phases between the ports of multi-mode interference couplers to provide substantially all the static optical phases needed. The operation of the proposed dual-function photonic integrated circuit is verified by computer simulations. The performance of the frequency octo-tupling and up-conversion functions is analyzed in terms of the electrical signal to harmonic distortion ratio and the optical single side band to unwanted harmonics ratio, respectively.

  7. Monolithic microwave integrated circuits for sensors, radar, and communications systems; Proceedings of the Meeting, Orlando, FL, Apr. 2-4, 1991

    Science.gov (United States)

    Leonard, Regis F.; Bhasin, Kul B.

    Consideration is given to MMICs for airborne phased arrays, monolithic GaAs integrated circuit millimeter wave imaging sensors, accurate design of multiport low-noise MMICs up to 20 GHz, an ultralinear low-noise amplifier technology for space communications, variable-gain MMIC module for space applications, a high-efficiency dual-band power amplifier for radar applications, a high-density circuit approach for low-cost MMIC circuits, coplanar SIMMWIC circuits, recent advances in monolithic phased arrays, and system-level integrated circuit development for phased-array antenna applications. Consideration is also given to performance enhancement in future communications satellites with MMIC technology insertion, application of Ka-band MMIC technology for an Orbiter/ACTS communications experiment, a space-based millimeter wave debris tracking radar, low-noise high-yield octave-band feedback amplifiers to 20 GHz, quasi-optical MESFET VCOs, and a high-dynamic-range mixer using novel balun structure. (For individual items see A93-25777 to A93-25814)

  8. Monolithic microwave integrated circuit technology for advanced space communication

    Science.gov (United States)

    Ponchak, George E.; Romanofsky, Robert R.

    1988-01-01

    Future Space Communications subsystems will utilize GaAs Monolithic Microwave Integrated Circuits (MMIC's) to reduce volume, weight, and cost and to enhance system reliability. Recent advances in GaAs MMIC technology have led to high-performance devices which show promise for insertion into these next generation systems. The status and development of a number of these devices operating from Ku through Ka band will be discussed along with anticipated potential applications.

  9. Design structure for in-system redundant array repair in integrated circuits

    Science.gov (United States)

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Quellette, Michael R.; Strissel, Scott A.

    2008-11-25

    A design structure for repairing an integrated circuit during operation of the integrated circuit. The integrated circuit comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The design structure provides the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The design structure further passes the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  10. Topology Optimization of Building Blocks for Photonic Integrated Circuits

    DEFF Research Database (Denmark)

    Jensen, Jakob Søndergaard; Sigmund, Ole

    2005-01-01

    Photonic integrated circuits are likely candidates as high speed replacements for the standard electrical integrated circuits of today. However, in order to obtain a satisfactorily performance many design prob- lems that up until now have resulted in too high losses must be resolved. In this work...... we demonstrate how the method of topology optimization can be used to design a variety of high performance building blocks for the future circuits....

  11. Energy-efficient neuron, synapse and STDP integrated circuits.

    Science.gov (United States)

    Cruz-Albrecht, Jose M; Yung, Michael W; Srinivasa, Narayan

    2012-06-01

    Ultra-low energy biologically-inspired neuron and synapse integrated circuits are presented. The synapse includes a spike timing dependent plasticity (STDP) learning rule circuit. These circuits have been designed, fabricated and tested using a 90 nm CMOS process. Experimental measurements demonstrate proper operation. The neuron and the synapse with STDP circuits have an energy consumption of around 0.4 pJ per spike and synaptic operation respectively.

  12. Application-specific architectures of CMOS monolithic active pixel sensors

    Energy Technology Data Exchange (ETDEWEB)

    Szelezniak, Michal [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]. E-mail: michal.szelezniak@ires.in2p3.fr; Besson, Auguste [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Claus, Gilles; Colledani, Claude; [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Degerli, Yavuz [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Deptuch, Grzegorz [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Deveaux, Michael [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Dorokhov, Andrei [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Dulinski, Wojciech [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Fourches, Nicolas [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Goffe, Mathieu [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Grandjean, Damien; Guilloux, Fabrice [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Heini, Sebastien [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)]|[GSI, Planckstrasse 1, Darmstadt 64291 (Germany); Himmi, Abdelkader [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Hu, Christine [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France); Jaaskelainen, Kimmo; Li, Yan; Lutz, Pierre; Orsini, Fabienne [CEA Saclay, DAPNIA, Gif-sur-Yvette Cedex (France); Pellicioli, Michel; Shabetai, Alexandre; Valin, Isabelle; Winter, Marc [Institute de Recherches Subatomiques, 23 rue du Loess, Strasbourg 67037 Cedex 02 (France)

    2006-11-30

    Several development directions intended to adapt and optimize monolithic active pixel sensors for specific applications are presented in this work. The first example, compatible with the STAR microvertex upgrade, is based on a simple two-transistor pixel circuitry. It is suited for a long integration time, room-temperature operation and minimum power dissipation. In another approach for this application, a specific readout method is proposed, allowing optimization of the integration time independently of the full frame-readout time. The circuit consists of an in-pixel front-end voltage amplifier, with a gain on the order of five, followed by two analog memory cells. The extended version of this scheme, based on the implementation of more memory cells per pixel, is the solution considered for the outer layers of a microvertex detector at the international linear collider. For the two innermost layers, a circuit allowing fast frame scans together with on-line, on-chip data sparsification is proposed. The first results of this prototype demonstrate that the fixed pattern dispersion is reduced below a noise level of 15 e{sup -}, allowing the use of a single comparator or a low-resolution ADC per pixel column. A common element for most of the mentioned readout schemes is a low-noise, low power consumption, layout efficient in-pixel amplifier. A review of possible solutions for this element together with some experimental results is presented.

  13. Control strategy and hardware implementation for DC–DC boost power circuit based on proportional–integral compensator for high voltage application

    Directory of Open Access Journals (Sweden)

    Sanjeevikumar Padmanaban

    2015-06-01

    Full Text Available For high-voltage (HV applications, the designers mostly prefer the classical DC–DC boost converter. However, it lacks due to the limitation of the output voltage by the gain transfer ratio, decreased efficiency and its requirement of two sensors for feedback signals, which creates complex control scheme with increased overall cost. Furthermore, the output voltage and efficiency are reduced due to the self-parasitic behavior of power circuit components. To overcome these drawbacks, this manuscript provides, the theoretical development and hardware implementation of DC–DC step-up (boost power converter circuit for obtaining extra output-voltage high-performance. The proposed circuit substantially improves the high output-voltage by voltage-lift technology with a closed loop proportional–integral controller. This complete numerical model of the converter circuit including closed loop P-I controller is developed in simulation (Matlab/Simulink software and the hardware prototype model is implemented with digital signal processor (DSP TMS320F2812. A detailed performance analysis was carried out under both line and load regulation conditions. Numerical simulation and its verification results provided in this paper, prove the good agreement of the circuit with theoretical background.

  14. A multiply-add engine with monolithically integrated 3D memristor crossbar/CMOS hybrid circuit.

    Science.gov (United States)

    Chakrabarti, B; Lastras-Montaño, M A; Adam, G; Prezioso, M; Hoskins, B; Payvand, M; Madhavan, A; Ghofrani, A; Theogarajan, L; Cheng, K-T; Strukov, D B

    2017-02-14

    Silicon (Si) based complementary metal-oxide semiconductor (CMOS) technology has been the driving force of the information-technology revolution. However, scaling of CMOS technology as per Moore's law has reached a serious bottleneck. Among the emerging technologies memristive devices can be promising for both memory as well as computing applications. Hybrid CMOS/memristor circuits with CMOL (CMOS + "Molecular") architecture have been proposed to combine the extremely high density of the memristive devices with the robustness of CMOS technology, leading to terabit-scale memory and extremely efficient computing paradigm. In this work, we demonstrate a hybrid 3D CMOL circuit with 2 layers of memristive crossbars monolithically integrated on a pre-fabricated CMOS substrate. The integrated crossbars can be fully operated through the underlying CMOS circuitry. The memristive devices in both layers exhibit analog switching behavior with controlled tunability and stable multi-level operation. We perform dot-product operations with the 2D and 3D memristive crossbars to demonstrate the applicability of such 3D CMOL hybrid circuits as a multiply-add engine. To the best of our knowledge this is the first demonstration of a functional 3D CMOL hybrid circuit.

  15. Test Structures For Bumpy Integrated Circuits

    Science.gov (United States)

    Buehler, Martin G.; Sayah, Hoshyar R.

    1989-01-01

    Cross-bridge resistors added to comb and serpentine patterns. Improved combination of test structures built into integrated circuit used to evaluate design rules, fabrication processes, and quality of interconnections. Consist of meshing serpentines and combs, and cross bridge. Structures used to make electrical measurements revealing defects in design or fabrication. Combination of test structures includes three comb arrays, two serpentine arrays, and cross bridge. Made of aluminum or polycrystalline silicon, depending on material in integrated-circuit layers evaluated. Aluminum combs and serpentine arrays deposited over steps made by polycrystalline silicon and diffusion layers, while polycrystalline silicon versions of these structures used to cross over steps made by thick oxide layer.

  16. Reconfigurable SDM Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    -division multiplexing switching using silicon photonic integrated circuit, which is fabricated on a novel silicon-oninsulator platform with buried Al mirror. The silicon photonic integrated circuit is composed of a 7x7 switch and low loss grating coupler array based multicore fiber couplers. Thanks to the Al mirror......, grating couplers with ultra-low coupling loss with optical multicore fibers is achieved. The lowest total insertion loss of the silicon integrated circuit is as low as 4.5 dB, with low crosstalk lower than -30 dB. Excellent performances in terms of low insertion loss and low crosstalk are obtained...

  17. Integrated Reconfigurable High-Voltage Transmitting Circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2014-01-01

    -out and measurements are performed on the integrated circuit. The transmitting circuit is reconfigurable externally making it able to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes, pulse voltages up to 100 V, maximum pulse range of 50 V and frequencies up to 5 MHz. The area...

  18. Integrated Circuit-Based Biofabrication with Common Biomaterials for Probing Cellular Biomechanics.

    Science.gov (United States)

    Sung, Chun-Yen; Yang, Chung-Yao; Yeh, J Andrew; Cheng, Chao-Min

    2016-02-01

    Recent advances in bioengineering have enabled the development of biomedical tools with modifiable surface features (small-scale architecture) to mimic extracellular matrices and aid in the development of well-controlled platforms that allow for the application of mechanical stimulation for studying cellular biomechanics. An overview of recent developments in common biomaterials that can be manufactured using integrated circuit-based biofabrication is presented. Integrated circuit-based biofabrication possesses advantages including mass and diverse production capacities for fabricating in vitro biomedical devices. This review highlights the use of common biomaterials that have been most frequently used to study cellular biomechanics. In addition, the influence of various small-scale characteristics on common biomaterial surfaces for a range of different cell types is discussed. Copyright © 2015 Elsevier Ltd. All rights reserved.

  19. Micromachined integrated quantum circuit containing a superconducting qubit

    Science.gov (United States)

    Brecht, Teresa; Chu, Yiwen; Axline, Christopher; Pfaff, Wolfgang; Blumoff, Jacob; Chou, Kevin; Krayzman, Lev; Frunzio, Luigi; Schoelkopf, Robert

    We demonstrate a functional multilayer microwave integrated quantum circuit (MMIQC). This novel hardware architecture combines the high coherence and isolation of three-dimensional structures with the advantages of integrated circuits made with lithographic techniques. We present fabrication and measurement of a two-cavity/one-qubit prototype, including a transmon coupled to a three-dimensional microwave cavity micromachined in a silicon wafer. It comprises a simple MMIQC with competitive lifetimes and the ability to perform circuit QED operations in the strong dispersive regime. Furthermore, the design and fabrication techniques that we have developed are extensible to more complex quantum information processing devices.

  20. A new integrated microwave SQUID circuit design

    International Nuclear Information System (INIS)

    Erne, S.N.; Finnegan, T.F.

    1980-01-01

    In this paper we consider the design and operation of a planar thin-film rf-SQUID circuit which can be realized via microwave-integrated-circuit (MIC) techniques and which differs substantially from pervious microwave SQUID configurations involving either mechanical point-contact or cylindrical thin-film micro-bridge geometries. (orig.)

  1. Integrated Circuit Immunity

    Science.gov (United States)

    Sketoe, J. G.; Clark, Anthony

    2000-01-01

    This paper presents a DOD E3 program overview on integrated circuit immunity. The topics include: 1) EMI Immunity Testing; 2) Threshold Definition; 3) Bias Tee Function; 4) Bias Tee Calibration Set-Up; 5) EDM Test Figure; 6) EMI Immunity Levels; 7) NAND vs. and Gate Immunity; 8) TTL vs. LS Immunity Levels; 9) TP vs. OC Immunity Levels; 10) 7805 Volt Reg Immunity; and 11) Seventies Chip Set. This paper is presented in viewgraph form.

  2. Integrated circuit amplifiers for multi-electrode intracortical recording.

    Science.gov (United States)

    Jochum, Thomas; Denison, Timothy; Wolf, Patrick

    2009-02-01

    Significant progress has been made in systems that interpret the electrical signals of the brain in order to control an actuator. One version of these systems senses neuronal extracellular action potentials with an array of up to 100 miniature probes inserted into the cortex. The impedance of each probe is high, so environmental electrical noise is readily coupled to the neuronal signal. To minimize this noise, an amplifier is placed close to each probe. Thus, the need has arisen for many amplifiers to be placed near the cortex. Commercially available integrated circuits do not satisfy the area, power and noise requirements of this application, so researchers have designed custom integrated-circuit amplifiers. This paper presents a comprehensive survey of the neural amplifiers described in publications prior to 2008. Methods to achieve high input impedance, low noise and a large time-constant high-pass filter are reviewed. A tutorial on the biological, electrochemical, mechanical and electromagnetic phenomena that influence amplifier design is provided. Areas for additional research, including sub-nanoampere electrolysis and chronic cortical heating, are discussed. Unresolved design concerns, including teraohm circuitry, electrical overstress and component failure, are identified.

  3. Large microwave tunability of GaAs-based multiferroic heterostructure for applications in monolithic microwave integrated circuits

    International Nuclear Information System (INIS)

    Chen Yajie; Gao Jinsheng; Vittoria, C; Harris, V G; Heiman, D

    2010-01-01

    Microwave magnetoelectric coupling in a ferroelectric/ferromagnetic/semiconductor multiferroic (MF) heterostructure, consisting of a Co 2 MnAl epitaxial film grown on a GaAs substrate bonded to a lead magnesium niobate-lead titanate (PMN-PT) crystal, is reported. Ferromagnetic resonance measurements were carried out at X-band under the application of electric fields. Results indicate a frequency tuning of 125 MHz for electric field strength of 8 kV cm -1 resulting in a magnetoelectric coupling coefficient of 3.4 Oe cm kV -1 . This work explores the potential of electronically controlled MF devices for use in future monolithic microwave integrated circuits.

  4. GaAs Photonic Integrated Circuit (PIC) development for high performance communications

    Energy Technology Data Exchange (ETDEWEB)

    Sullivan, C.T.

    1998-03-01

    Sandia has established a foundational technology in photonic integrated circuits (PICs) based on the (Al,Ga,In)As material system for optical communication, radar control and testing, and network switching applications at the important 1.3{mu}m/1.55{mu}m wavelengths. We investigated the optical, electrooptical, and microwave performance characteristics of the fundamental building-block PIC elements designed to be as simple and process-tolerant as possible, with particular emphasis placed on reducing optical insertion loss. Relatively conventional device array and circuit designs were built using these PIC elements: (1) to establish a baseline performance standard; (2) to assess the impact of epitaxial growth accuracy and uniformity, and of fabrication uniformity and yield; (3) to validate our theoretical and numerical models; and (4) to resolve the optical and microwave packaging issues associated with building fully packaged prototypes. Novel and more complex PIC designs and fabrication processes, viewed as higher payoff but higher risk, were explored in a parallel effort with the intention of meshing those advances into our baseline higher-yield capability as they mature. The application focus targeted the design and fabrication of packaged solitary modulators meeting the requirements of future wideband and high-speed analog and digital data links. Successfully prototyped devices are expected to feed into more complex PICs solving specific problems in high-performance communications, such as optical beamforming networks for phased array antennas.

  5. Vertically integrated, three-dimensional nanowire complementary metal-oxide-semiconductor circuits.

    Science.gov (United States)

    Nam, SungWoo; Jiang, Xiaocheng; Xiong, Qihua; Ham, Donhee; Lieber, Charles M

    2009-12-15

    Three-dimensional (3D), multi-transistor-layer, integrated circuits represent an important technological pursuit promising advantages in integration density, operation speed, and power consumption compared with 2D circuits. We report fully functional, 3D integrated complementary metal-oxide-semiconductor (CMOS) circuits based on separate interconnected layers of high-mobility n-type indium arsenide (n-InAs) and p-type germanium/silicon core/shell (p-Ge/Si) nanowire (NW) field-effect transistors (FETs). The DC voltage output (V(out)) versus input (V(in)) response of vertically interconnected CMOS inverters showed sharp switching at close to the ideal value of one-half the supply voltage and, moreover, exhibited substantial DC gain of approximately 45. The gain and the rail-to-rail output switching are consistent with the large noise margin and minimal static power consumption of CMOS. Vertically interconnected, three-stage CMOS ring oscillators were also fabricated by using layer-1 InAs NW n-FETs and layer-2 Ge/Si NW p-FETs. Significantly, measurements of these circuits demonstrated stable, self-sustained oscillations with a maximum frequency of 108 MHz, which represents the highest-frequency integrated circuit based on chemically synthesized nanoscale materials. These results highlight the flexibility of bottom-up assembly of distinct nanoscale materials and suggest substantial promise for 3D integrated circuits.

  6. Monolitic integrated circuit for the strobed charge-to-time converter

    International Nuclear Information System (INIS)

    Bel'skij, V.I.; Bushnin, Yu.B.; Zimin, S.A.; Punzhin, Yu.N.; Sen'ko, V.A.; Soldatov, M.M.; Tokarchuk, V.P.

    1985-01-01

    The developed and comercially produced semiconducting circuit - gating charge-to-time converter KR1101PD1 is described. The considered integrated circuit is a short pulse charge-to-time converter with integration of input current. The circuit is designed for construction of time-to-pulse analog-to-digital converters utilized in multichannel detection systems when studying complex topology processes. Input resistance of the circuit is 0.1 Ω permissible input current is 50 mA, maximum measured charge is 300-1000 pC

  7. Integrated electric circuit CAD system in Minolta Camera Co. Ltd

    Energy Technology Data Exchange (ETDEWEB)

    Nakagami, Tsuyoshi; Hirata, Sumiaki; Matsumura, Fumihiko

    1988-08-26

    Development background, fundamental concept, details and future plan of the integrated electric circuit CAD system for OA equipment are presented. The central integrated database is basically intended to store experiences or know-hows, to cover the wide range of data required for designs, and to provide a friendly interface. This easy-to-use integrated database covers the drawing data, parts information, design standards, know-hows and system data. The system contains the circuit design function to support drawing circuit diagrams, the wiring design function to support the wiring and arrangement of printed circuit boards and various parts integratedly, and the function to verify designs, to make full use of parts or technical information, to maintain the system security. In the future, as the system will be wholly in operation, the design period reduction, quality improvement and cost saving will be attained by this integrated design system. (19 figs, 2 tabs)

  8. Power management techniques for integrated circuit design

    CERN Document Server

    Chen, Ke-Horng

    2016-01-01

    This book begins with the premise that energy demands are directing scientists towards ever-greener methods of power management, so highly integrated power control ICs (integrated chip/circuit) are increasingly in demand for further reducing power consumption. * A timely and comprehensive reference guide for IC designers dealing with the increasingly widespread demand for integrated low power management * Includes new topics such as LED lighting, fast transient response, DVS-tracking and design with advanced technology nodes * Leading author (Chen) is an active and renowned contributor to the power management IC design field, and has extensive industry experience * Accompanying website includes presentation files with book illustrations, lecture notes, simulation circuits, solution manuals, instructors manuals, and program downloads.

  9. High transition temperature superconducting integrated circuit

    International Nuclear Information System (INIS)

    DiIorio, M.S.

    1985-01-01

    This thesis describes the design and fabrication of the first superconducting integrated circuit capable of operating at over 10K. The primary component of the circuit is a dc SQUID (Superconducting QUantum Interference Device) which is extremely sensitive to magnetic fields. The dc SQUID consists of two superconductor-normal metal-superconductor (SNS) Josephson microbridges that are fabricated using a novel step-edge process which permits the use of high transition temperature superconductors. By utilizing electron-beam lithography in conjunction with ion-beam etching, very small microbridges can be produced. Such microbridges lead to high performance dc SQUIDs with products of the critical current and normal resistance reaching 1 mV at 4.2 K. These SQUIDs have been extensively characterized, and exhibit excellent electrical characteristics over a wide temperature range. In order to couple electrical signals into the SQUID in a practical fashion, a planar input coil was integrated for efficient coupling. A process was developed to incorporate the technologically important high transition temperature superconducting materials, Nb-Sn and Nb-Ge, using integrated circuit techniques. The primary obstacles were presented by the metallurgical idiosyncrasies of the various materials, such as the need to deposit the superconductors at elevated temperatures, 800-900 0 C, in order to achieve a high transition temperature

  10. Integrated coincidence circuits

    International Nuclear Information System (INIS)

    Borejko, V.F.; Grebenyuk, V.M.; Zinov, V.G.

    1976-01-01

    The description is given of two coincidence units employing integral circuits in the VISHNYA standard. The units are distinguished for the coincidence selection element which is essentially a combination of a tunnel diode and microcircuits. The output fast response of the units is at least 90 MHz in the mode of the output signal unshaped in duration and 50 MHz minimum in the mode of the output signal shaping. The resolution time of the units is dependent upon the duration of input signals

  11. Scaling of graphene integrated circuits.

    Science.gov (United States)

    Bianchi, Massimiliano; Guerriero, Erica; Fiocco, Marco; Alberti, Ruggero; Polloni, Laura; Behnam, Ashkan; Carrion, Enrique A; Pop, Eric; Sordan, Roman

    2015-05-07

    The influence of transistor size reduction (scaling) on the speed of realistic multi-stage integrated circuits (ICs) represents the main performance metric of a given transistor technology. Despite extensive interest in graphene electronics, scaling efforts have so far focused on individual transistors rather than multi-stage ICs. Here we study the scaling of graphene ICs based on transistors from 3.3 to 0.5 μm gate lengths and with different channel widths, access lengths, and lead thicknesses. The shortest gate delay of 31 ps per stage was obtained in sub-micron graphene ROs oscillating at 4.3 GHz, which is the highest oscillation frequency obtained in any strictly low-dimensional material to date. We also derived the fundamental Johnson limit, showing that scaled graphene ICs could be used at high frequencies in applications with small voltage swing.

  12. Radiation-Hard Complementary Integrated Circuits Based on Semiconducting Single-Walled Carbon Nanotubes.

    Science.gov (United States)

    McMorrow, Julian J; Cress, Cory D; Gaviria Rojas, William A; Geier, Michael L; Marks, Tobin J; Hersam, Mark C

    2017-03-28

    Increasingly complex demonstrations of integrated circuit elements based on semiconducting single-walled carbon nanotubes (SWCNTs) mark the maturation of this technology for use in next-generation electronics. In particular, organic materials have recently been leveraged as dopant and encapsulation layers to enable stable SWCNT-based rail-to-rail, low-power complementary metal-oxide-semiconductor (CMOS) logic circuits. To explore the limits of this technology in extreme environments, here we study total ionizing dose (TID) effects in enhancement-mode SWCNT-CMOS inverters that employ organic doping and encapsulation layers. Details of the evolution of the device transport properties are revealed by in situ and in operando measurements, identifying n-type transistors as the more TID-sensitive component of the CMOS system with over an order of magnitude larger degradation of the static power dissipation. To further improve device stability, radiation-hardening approaches are explored, resulting in the observation that SWNCT-CMOS circuits are TID-hard under dynamic bias operation. Overall, this work reveals conditions under which SWCNTs can be employed for radiation-hard integrated circuits, thus presenting significant potential for next-generation satellite and space applications.

  13. Active Trimming of Hybrid Integrated Circuits

    OpenAIRE

    Németh, P.; Krémer, P.

    1984-01-01

    One of the more important fields of the microelectronics industry is the manufacturing of hybrid integrated circuits.An important part of the manufacturing process is concerned with the trimming of the hybrid integratedl circuits. This article deals with the basic principles of active trimming and introduces a microprocessor controlled trimming machine. By comparing active trimming with passive techniques, it can be shown that the active system has some advantages. This article outlines these...

  14. Integrated circuit implementation of fuzzy controllers

    OpenAIRE

    Huertas Díaz, José Luis; Sánchez Solano, Santiago; Baturone Castillo, María Iluminada; Barriga Barros, Ángel

    1996-01-01

    This paper presents mixed-signal current-mode CMOS circuits to implement programmable fuzzy controllers that perform the singleton or zero-order Sugeno’s method. Design equations to characterize these circuits are provided to explain the precision and speed that they offer. This analysis is illustrated with the experimental results of prototypes integrated in standard CMOS technologies. These tests show that an equivalent precision of 6 bits is achieved. The connection of these...

  15. The integrated circuit IC EMP transient state disturbance effect experiment method investigates

    International Nuclear Information System (INIS)

    Li Xiaowei

    2004-01-01

    Transient state disturbance characteristic study on the integrated circuit, IC, need from its coupling path outset. Through cable (aerial) coupling, EMP converts to an pulse current voltage and results in the impact to the integrated circuit I/O orifice passing the cable. Aiming at the armament system construction feature, EMP effect to the integrated circuit, IC inside the system is analyzed. The integrated circuit, IC EMP effect experiment current injection method is investigated and a few experiments method is given. (authors)

  16. An integrated circuit/packet switched video conferencing system

    Energy Technology Data Exchange (ETDEWEB)

    Kippenhan Junior, H.A.; Lidinsky, W.P.; Roediger, G.A. [Fermi National Accelerator Lab., Batavia, IL (United States). HEP Network Resource Center; Waits, T.A. [Rutgers Univ., Piscataway, NJ (United States). Dept. of Physics and Astronomy

    1996-07-01

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

  17. An integrated circuit/packet switched video conferencing system

    International Nuclear Information System (INIS)

    Kippenhan Junior, H.A.; Lidinsky, W.P.; Roediger, G.A.; Waits, T.A.

    1996-01-01

    The HEP Network Resource Center (HEPNRC) at Fermilab and the Collider Detector Facility (CDF) collaboration have evolved a flexible, cost-effective, widely accessible video conferencing system for use by high energy physics collaborations and others wishing to use video conferencing. No current systems seemed to fully meet the needs of high energy physics collaborations. However, two classes of video conferencing technology: circuit-switched and packet-switched, if integrated, might encompass most of HEPS's needs. It was also realized that, even with this integration, some additional functions were needed and some of the existing functions were not always wanted. HEPNRC with the help of members of the CDF collaboration set out to develop such an integrated system using as many existing subsystems and components as possible. This system is called VUPAC (Video conferencing Using Packets and Circuits). This paper begins with brief descriptions of the circuit-switched and packet-switched video conferencing systems. Following this, issues and limitations of these systems are considered. Next the VUPAC system is described. Integration is accomplished primarily by a circuit/packet video conferencing interface. Augmentation is centered in another subsystem called MSB (Multiport MultiSession Bridge). Finally, there is a discussion of the future work needed in the evolution of this system. (author)

  18. RF and microwave integrated circuit development technology, packaging and testing

    CERN Document Server

    Gamand, Patrice; Kelma, Christophe

    2018-01-01

    RF and Microwave Integrated Circuit Development bridges the gap between existing literature, which focus mainly on the 'front-end' part of a product development (system, architecture, design techniques), by providing the reader with an insight into the 'back-end' part of product development. In addition, the authors provide practical answers and solutions regarding the choice of technology, the packaging solutions and the effects on the performance on the circuit and to the industrial testing strategy. It will also discuss future trends and challenges and includes case studies to illustrate examples. * Offers an overview of the challenges in RF/microwave product design * Provides practical answers to packaging issues and evaluates its effect on the performance of the circuit * Includes industrial testing strategies * Examines relevant RF MIC technologies and the factors which affect the choice of technology for a particular application, e.g. technical performance and cost * Discusses future trends and challen...

  19. Using NCAP to predict RFI effects in linear bipolar integrated circuits

    Science.gov (United States)

    Fang, T.-F.; Whalen, J. J.; Chen, G. K. C.

    1980-11-01

    Applications of the Nonlinear Circuit Analysis Program (NCAP) to calculate RFI effects in electronic circuits containing discrete semiconductor devices have been reported upon previously. The objective of this paper is to demonstrate that the computer program NCAP also can be used to calcuate RFI effects in linear bipolar integrated circuits (IC's). The IC's reported upon are the microA741 operational amplifier (op amp) which is one of the most widely used IC's, and a differential pair which is a basic building block in many linear IC's. The microA741 op amp was used as the active component in a unity-gain buffer amplifier. The differential pair was used in a broad-band cascode amplifier circuit. The computer program NCAP was used to predict how amplitude-modulated RF signals are demodulated in the IC's to cause undesired low-frequency responses. The predicted and measured results for radio frequencies in the 0.050-60-MHz range are in good agreement.

  20. Design and Test of Application-Specific Integrated Circuits by use of Mobile Clients

    Directory of Open Access Journals (Sweden)

    Michael Auer

    2009-02-01

    Full Text Available The aim of this work is to develop a simultaneous multi user access system – READ (Remote ASIC Design and Test that allows users to perform test and measurements remotely via clients running on mobile devices as well as on standard PCs. The system also facilitates the remote design of circuits with the PAC-Designer The system is controlled by LabVIEW and was implemented using a Data Acquisition Card from National instruments. Such systems are specially suited for manufacturing process monitoring and control. The performance of the simultaneous access was tested under load with a variable number of users. The server implements a queue that processes user’s commands upon request.

  1. Silicon Compatible Materials, Processes, and Technologies for Advanced Integrated Circuits and Emerging Applications 6

    NARCIS (Netherlands)

    Roozeboom, F.; Narayanan, V.; Kakushima, K.; Timans, P.J.; Gusev, E.P.; Karim, Z.; Gendt, S. De

    2016-01-01

    The topics of this annual symposium continue to describe the evolution of traditional scaling in CMOS integrated circuit manufacturing (More Moore for short), combined with the opportunities from growing diversification and embedded functionality (More than Moore). Once again, the main objective was

  2. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  3. Microwave plasmatrons for giant integrated circuit processing

    Energy Technology Data Exchange (ETDEWEB)

    Petrin, A.B.

    2000-02-01

    A method for calculating the interaction of a powerful microwave with a plane layer of magnetoactive low-pressure plasma under conditions of electron cyclotron resonance is presented. In this paper, the plasma layer is situated between a plane dielectric layer and a plane metal screen. The calculation model contains the microwave energy balance, particle balance, and electron energy balance. The equation that expressed microwave properties of nonuniform magnetoactive plasma is found. The numerical calculations of the microwave-plasma interaction for a one-dimensional model of the problem are considered. Applications of the results for microwave plasmatrons designed for processing giant integrated circuits are suggested.

  4. Technique for selection of transient radiation-hard junction-isolated integrated circuits

    International Nuclear Information System (INIS)

    Crowley, J.L.; Junga, F.A.; Stultz, T.J.

    1976-01-01

    A technique is presented which demonstrates the feasibility of selecting junction-isolated integrated circuits (JI/ICS) for use in transient radiation environments. The procedure guarantees that all PNPN paths within the integrated circuit are identified and describes the methods used to determine whether the paths represent latchup susceptible structures. Two examples of the latchup analysis are given involving an SSI and an LSI bipolar junction-isolated integrated circuit

  5. Study and characterization of an integrated circuit-deposited hydrogenated amorphous silicon sensor for the detection of particles and radiations; Etude et caracterisation d'un capteur en silicium amorphe hydrogene depose sur circuit integre pour la detection de particules et de rayonnements

    Energy Technology Data Exchange (ETDEWEB)

    Despeisse, M

    2006-03-15

    Next generation experiments at the European laboratory of particle physics (CERN) require particle detector alternatives to actual silicon detectors. This thesis presents a novel detector technology, which is based on the deposition of a hydrogenated amorphous silicon sensor on top of an integrated circuit. Performance and limitations of this technology have been assessed for the first time in this thesis in the context of particle detectors. Specific integrated circuits have been designed and the detector segmentation, the interface sensor-chip and the sensor leakage current have been studied in details. The signal induced by the track of an ionizing particle in the sensor has been characterized and results on the signal speed, amplitude and on the sensor resistance to radiation are presented. The results are promising regarding the use of this novel technology for radiation detection, though limitations have been shown for particle physics application. (author)

  6. Organic-inorganic hybrid material SUNCONNECT® for photonic integrated circuit

    Science.gov (United States)

    Nawata, Hideyuki; Oshima, Juro; Kashino, Tsubasa

    2018-02-01

    In this paper, we report the feature and properties about organic-inorganic hybrid material, "SUNCONNECT®" for photonic integrated circuit. "SUNCONNECT®" materials have low propagation loss at 1310nm (0.29dB/cm) and 1550nm (0.45dB/cm) respectively. In addition, the material has high thermal resistance both high temperature annealing test at 300°C and also 260°C solder heat resistance test. For actual device application, high reliability is required. 85°C /85% test was examined by using multi-mode waveguide. As a result, it indicated that variation of insertion loss property was not changed significantly after high temperature / high humidity test. For the application to photonic integrated circuit, it was demonstrated to fabricate polymer optical waveguide by using three different methods. Single-micron core pattern can be fabricated on cladding layer by using UV lithography with proximity gap exposure. Also, single-mode waveguide can be also fabricated with over cladding. On the other hands, "Mosquito method" and imprint method can be applied to fabricate polymer optical waveguide. Remarkably, these two methods can fabricate gradedindex type optical waveguide without using photo mask. In order to evaluate the optical performance, NFP's observation, measurement of insertion loss and propagation loss by cut-back methods were carried out by using each waveguide sample.

  7. Integrated circuits for multimedia applications

    DEFF Research Database (Denmark)

    Vandi, Luca

    2007-01-01

    , and it is applied to a broad-band dual-loop receiver architecture in order to boost the linearity performances of the stage. A simplified noise- and linearity analysis of the circuit is derived, and a comparison is provided with a more traditional dual-loop topology (a broad-band stage based on shunt...... the impact of substrate-induced currents. Basic models are derived in the design phase, and the technological limits of the device are considered. Measurement results show that a very compact coil can provide ~1nH inductance up to 20GHz (physical limit for the measurement equipment), with a peak quality...

  8. 116 dB dynamic range CMOS readout circuit for MEMS capacitive accelerometer

    International Nuclear Information System (INIS)

    Long Shanli; Liu Yan; He Kejun; Tang Xinggang; Chen Qian

    2014-01-01

    A high stability in-circuit reprogrammable technique control system for a capacitive MEMS accelerometer is presented. Modulation and demodulation are used to separate the signal from the low frequency noise. A low-noise low-offset charge integrator is employed in this circuit to implement a capacitance-to-voltage converter and minimize the noise and offset. The application-specific integrated circuit (ASIC) is fabricated in a 0.5 μm one-ploy three-metal CMOS process. The measured results of the proposed circuit show that the noise floor of the ASIC is −116 dBV, the sensitivity of the accelerometer is 66 mV/g with a nonlinearity of 0.5%. The chip occupies 3.5 × 2.5 mm 2 and the current is 3.5 mA. (semiconductor integrated circuits)

  9. Manipulator techniques and problems of their application in primary circuit maintenance

    International Nuclear Information System (INIS)

    Kertscher, F.; Popp, P.

    1985-01-01

    The fundamental structure and specifications of manipulators (in particular of industrial robots) are presented in order to derive the application conditions and fields for manipulators in primary circuit maintenance. The necessity of applying process-specific manipulator technique in the primary circuit maintenance is based on nuclear safety requirements and on decreasing of the radiation exposure of maintenance personnel. Synchronous manipulators and industrial robots are the types of manipulators used in materials testing, repairing and scrapping. The technical requirements of manipulators are discussed

  10. Chemical sensors fabricated by a photonic integrated circuit foundry

    Science.gov (United States)

    Stievater, Todd H.; Koo, Kee; Tyndall, Nathan F.; Holmstrom, Scott A.; Kozak, Dmitry A.; Goetz, Peter G.; McGill, R. Andrew; Pruessner, Marcel W.

    2018-02-01

    We describe the detection of trace concentrations of chemical agents using waveguide-enhanced Raman spectroscopy in a photonic integrated circuit fabricated by AIM Photonics. The photonic integrated circuit is based on a five-centimeter long silicon nitride waveguide with a trench etched in the top cladding to allow access to the evanescent field of the propagating mode by analyte molecules. This waveguide transducer is coated with a sorbent polymer to enhance detection sensitivity and placed between low-loss edge couplers. The photonic integrated circuit is laid-out using the AIM Photonics Process Design Kit and fabricated on a Multi-Project Wafer. We detect chemical warfare agent simulants at sub parts-per-million levels in times of less than a minute. We also discuss anticipated improvements in the level of integration for photonic chemical sensors, as well as existing challenges.

  11. Study and characterization of an integrated circuit-deposited hydrogenated amorphous silicon sensor for the detection of particles and radiations

    International Nuclear Information System (INIS)

    Despeisse, M.

    2006-03-01

    Next generation experiments at the European laboratory of particle physics (CERN) require particle detector alternatives to actual silicon detectors. This thesis presents a novel detector technology, which is based on the deposition of a hydrogenated amorphous silicon sensor on top of an integrated circuit. Performance and limitations of this technology have been assessed for the first time in this thesis in the context of particle detectors. Specific integrated circuits have been designed and the detector segmentation, the interface sensor-chip and the sensor leakage current have been studied in details. The signal induced by the track of an ionizing particle in the sensor has been characterized and results on the signal speed, amplitude and on the sensor resistance to radiation are presented. The results are promising regarding the use of this novel technology for radiation detection, though limitations have been shown for particle physics application. (author)

  12. Engineering integrated digital circuits with allosteric ribozymes for scaling up molecular computation and diagnostics.

    Science.gov (United States)

    Penchovsky, Robert

    2012-10-19

    Here we describe molecular implementations of integrated digital circuits, including a three-input AND logic gate, a two-input multiplexer, and 1-to-2 decoder using allosteric ribozymes. Furthermore, we demonstrate a multiplexer-decoder circuit. The ribozymes are designed to seek-and-destroy specific RNAs with a certain length by a fully computerized procedure. The algorithm can accurately predict one base substitution that alters the ribozyme's logic function. The ability to sense the length of RNA molecules enables single ribozymes to be used as platforms for multiple interactions. These ribozymes can work as integrated circuits with the functionality of up to five logic gates. The ribozyme design is universal since the allosteric and substrate domains can be altered to sense different RNAs. In addition, the ribozymes can specifically cleave RNA molecules with triplet-repeat expansions observed in genetic disorders such as oculopharyngeal muscular dystrophy. Therefore, the designer ribozymes can be employed for scaling up computing and diagnostic networks in the fields of molecular computing and diagnostics and RNA synthetic biology.

  13. Common-signal-induced synchronization in photonic integrated circuits and its application to secure key distribution.

    Science.gov (United States)

    Sasaki, Takuma; Kakesu, Izumi; Mitsui, Yusuke; Rontani, Damien; Uchida, Atsushi; Sunada, Satoshi; Yoshimura, Kazuyuki; Inubushi, Masanobu

    2017-10-16

    We experimentally achieve common-signal-induced synchronization in two photonic integrated circuits with short external cavities driven by a constant-amplitude random-phase light. The degree of synchronization can be controlled by changing the optical feedback phase of the two photonic integrated circuits. The change in the optical feedback phase leads to a significant redistribution of the spectral energy of optical and RF spectra, which is a unique characteristic of PICs with the short external cavity. The matching of the RF and optical spectra is necessary to achieve synchronization between the two PICs, and stable synchronization can be obtained over an hour in the presence of optical feedback. We succeed in generating information-theoretic secure keys and achieving the final key generation rate of 184 kb/s using the PICs.

  14. Simultaneous detection of lactate and glucose by integrated printed circuit board based array sensing chip

    Energy Technology Data Exchange (ETDEWEB)

    Li, Xuelian [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Zang, Jianfeng [Department of Mechanical Engineering and Materials Science, Duke University, Durham, NC 27708 (United States); Liu, Yingshuai; Lu, Zhisong [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China); Li, Qing, E-mail: Qli@swu.edu.cn [School of Chemistry and Chemical Engineering, Southwest University, Chongqing 400715 (China); Li, Chang Ming, E-mail: ecmli@swu.edu.cn [Institute for Clean Energy and Advanced Materials, Southwest University, Chongqing 400715 (China)

    2013-04-10

    Highlights: ► An integrated printed circuit board (PCB) based array sensing chip was developed. ► Simultaneous detection of lactate and glucose in serum has been demonstrated. ► The array electronic biochip has high signal to noise ratio and high sensitivity. ► Additional electrodes were designed on the chip to correct interferences. -- Abstract: An integrated printed circuit board (PCB) based array sensing chip was developed to simultaneously detect lactate and glucose in mouse serum. The novelty of the chip relies on a concept demonstration of inexpensive high-throughput electronic biochip, a chip design for high signal to noise ratio and high sensitivity by construction of positively charged chitosan/redox polymer Polyvinylimidazole-Os (PVI-Os)/carbon nanotube (CNT) composite sensing platform, in which the positively charged chitosan/PVI-Os is mediator and electrostatically immobilizes the negatively charged enzyme, while CNTs function as an essential cross-linker to network PVI-Os and chitosan due to its negative charged nature. Additional electrodes on the chip with the same sensing layer but without enzymes were prepared to correct the interferences for high specificity. Low detection limits of 0.6 μM and 5 μM were achieved for lactate and glucose, respectively. This work could be extended to inexpensive array sensing chips with high sensitivity, good specificity and high reproducibility for various sensor applications.

  15. Diagnosis of soft faults in analog integrated circuits based on fractional correlation

    International Nuclear Information System (INIS)

    Deng Yong; Shi Yibing; Zhang Wei

    2012-01-01

    Aiming at the problem of diagnosing soft faults in analog integrated circuits, an approach based on fractional correlation is proposed. First, the Volterra series of the circuit under test (CUT) decomposed by the fractional wavelet packet are used to calculate the fractional correlation functions. Then, the calculated fractional correlation functions are used to form the fault signatures of the CUT. By comparing the fault signatures, the different soft faulty conditions of the CUT are identified and the faults are located. Simulations of benchmark circuits illustrate the proposed method and validate its effectiveness in diagnosing soft faults in analog integrated circuits. (semiconductor integrated circuits)

  16. A space-qualified experiment integrating HTS digital circuits and small cryocoolers

    International Nuclear Information System (INIS)

    Silver, A.; Akerling, G.; Auten, R.

    1996-01-01

    High temperature superconductors (HTS) promise to achieve electrical performance superior to that of conventional electronics. For application in space systems, HTS systems must simultaneously achieve lower power, weight, and volume than conventional electronics, and meet stringent space qualification and reliability requirements. Most effort to date has focused on passive RF/microwave applications. However, incorporation of active microwave components such as amplifiers, mixers, and phase shifters, and on-board high data rate digital signal processing is limited by the power and weight of their spacecraft electronic and support modules. Absence of data on active HTS components will prevent their utilization in space. To validate the feasibility in space of HTS circuits and components based on Josephson junctions, one needs to demonstrate HTS circuits and critical supporting technologies, such as space-qualified packaging and interconnects, closed-cycle cryocooling, and interface electronics. This paper describes the packaging, performance, and space test plan of an integrated, space-qualified experimental package consisting of HTS Josephson junction circuits and all the supporting components for NRL's high temperature superconductor space experiment (HTSSE-II). Most of the technical challenges and approaches are equally applicable to passive and active RF/microwave and digital electronic components, and this experiment will provide valuable validation data

  17. LSI microprocessor circuit families based on integrated injection logic. Mikroprotsessornyye komplekty bis na osnove integral'noy inzhektsionnoy logiki

    Energy Technology Data Exchange (ETDEWEB)

    Borisov, V.S.; Vlasov, F.S.; Kaloshkin, E.P.; Serzhanovich, D.S.; Sukhoparov, A.I.

    1984-01-01

    Progress in developing microprocessor computer hardware is based on progress and improvement in systems engineering, circuit engineering and manufacturing process methods of design and development of large-scale integrated circuits (BIS). Development of these methods with widespread use of computer-aided design (CAD) systems has allowed developing 4- and 8-bit microprocessor families (MPK) of LSI circuits based on integrated injection logic (I/sup 2/L), characterized by relatively high speed and low dissipated power. The emergence of LSI and VLSI microprocessor circuits required computer system developers to make changes to theory and practice of computer system design. Progress in technology upset the established relation between hardware and software component development costs in systems being designed. A characteristic feature of using LSI circuits is also the necessity of building devices from standard modules with large functional complexity. The existing directions of forming compositions of LSI microprocessor families allow the system developer to choose a particular methodology of design, proceeding from the efficiency function and field of application of the system being designed. The efficiency of using microprocessor families is largely governed by the user's understanding in depth of the structure of LSI microprocessor family circuits and the features of using them to implement a broad class of computer devices and modules being developed. This book is devoted to solving this problem.

  18. CMOS analog integrated circuit design technology; CMOS anarogu IC sekkei gijutsu

    Energy Technology Data Exchange (ETDEWEB)

    Fujimoto, H.; Fujisawa, A. [Fuji Electric Co. Ltd., Tokyo (Japan)

    2000-08-10

    In the field of the LSI (large scale integrated circuit) in rapid progress toward high integration and advanced functions, CAD (computer-aided design) technology has become indispensable to LSI development within a short period. Fuji Electric has developed design technologies and automatic design system to develop high-quality analog ICs (integrated circuits), including power supply ICs. within a short period. This paper describes CMOS (complementary metal-oxide semiconductor) analog macro cell, circuit simulation, automatic routing, and backannotation technologies. (author)

  19. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

    Science.gov (United States)

    Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed

    2017-01-01

    This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz. PMID:28763043

  20. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit

    Directory of Open Access Journals (Sweden)

    Yuharu Shinki

    2017-08-01

    Full Text Available This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for −4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

  1. Impedance Matching Antenna-Integrated High-Efficiency Energy Harvesting Circuit.

    Science.gov (United States)

    Shinki, Yuharu; Shibata, Kyohei; Mansour, Mohamed; Kanaya, Haruichi

    2017-08-01

    This paper describes the design of a high-efficiency energy harvesting circuit with an integrated antenna. The circuit is composed of series resonance and boost rectifier circuits for converting radio frequency power into boosted direct current (DC) voltage. The measured output DC voltage is 5.67 V for an input of 100 mV at 900 MHz. Antenna input impedance matching is optimized for greater efficiency and miniaturization. The measured efficiency of this antenna-integrated energy harvester is 60% for -4.85 dBm input power and a load resistance equal to 20 kΩ at 905 MHz.

  2. A TDC integrated circuit for drift chamber readout

    International Nuclear Information System (INIS)

    Passaseo, M.; Petrolo, E.; Veneziano, S.

    1995-01-01

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 μm CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.)

  3. A TDC integrated circuit for drift chamber readout

    Energy Technology Data Exchange (ETDEWEB)

    Passaseo, M. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Petrolo, E. [Istituto Nazionale di Fisica Nucleare, Rome (Italy); Veneziano, S. [Istituto Nazionale di Fisica Nucleare, Rome (Italy)

    1995-12-11

    A custom integrated circuit for the measurement of the signal drift-time coming from the KLOE chamber developed by INFN Sezione di Roma is presented. The circuit is a multichannel common start/stop TDC, with 32 channels per chip. The TDC integrated circuit will be developed as a full-custom device in 0.5 {mu}m CMOS technology, with 1 ns LSB realized using a Gray counter working at the frequency of 1 GHz. The circuit is capable of detecting rising/falling edges, with a double edge resolution of 8 ns; the hits are recorded as 16 bit words, hits older than a programmable time window are discarded, if not confirmed by a stop signal. The chip has four event-buffers, which are used only if at least one hit is present in one of the 32 channels. The readout of the data passes through the I/O port at a speed of 33 MHz; empty channels are automatically skipped during the readout phase. (orig.).

  4. Latch-up in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Estreich, D.B.; Dutton, R.W.

    1978-04-01

    An analysis is presented of latch-up in CMOS integrated circuits. A latch-up prediction algorithm has been developed and used to evaluate methods to control latch-up. Experimental verification of the algorithm is demonstrated

  5. A fast charge integrating and shaping circuit

    International Nuclear Information System (INIS)

    Kulka, Z.; Szoncso, F.

    1990-01-01

    The development of a low cost fast charge integrating and shaping circuit (FCISC) was motivated by the need for an interface between the photomultipliers of an existing hadronic calorimeter and recently developed new readout electronics designed to match the output of small ionization chambers for the upgraded UA1 detector at the CERN proton-antiproton collider. This paper describes the design principles of gated and ungated charge integrating and shaping circuits. An FCISC prototype using discrete components was made and its properties were determined with a computerized test setup. Finally an SMD implementation of the FCISC is presented and the performance is reported. (orig.)

  6. The FE-I4 pixel readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Garcia-Sciveres, M., E-mail: mgarcia-sciveres@bl.gov [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Arutinov, D.; Barbero, M. [University of Bonn, Bonn (Germany); Beccherle, R. [Istituto Nazionale di Fisica Nucleare Sezione di Genova, Genova (Italy); Dube, S.; Elledge, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Fleury, J. [Laboratoire de l' Accelerateur Lineaire, Orsay (France); Fougeron, D.; Gensolen, F. [Centre de Physique des Particules de Marseille, Marseille (France); Gnani, D. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Gromov, V. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Hemperek, T.; Karagounis, M. [University of Bonn, Bonn (Germany); Kluit, R. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands); Kruth, A. [University of Bonn, Bonn (Germany); Mekkaoui, A. [Lawrence Berkeley National Laboratory, Berkeley, CA (United States); Menouni, M. [Centre de Physique des Particules de Marseille, Marseille (France); Schipper, J.-D. [Nationaal Instituut voor Subatomaire Fysica, Amsterdam (Netherlands)

    2011-04-21

    A new pixel readout integrated circuit denominated FE-I4 is being designed to meet the requirements of ATLAS experiment upgrades. It will be the largest readout IC produced to date for particle physics applications, filling the maximum allowed reticle area. This will significantly reduce the cost of future hybrid pixel detectors. In addition, FE-I4 will have smaller pixels and higher rate capability than the present generation of LHC pixel detectors. Design features are described along with simulation and test results, including low power and high rate readout architecture, mixed signal design strategy, and yield hardening.

  7. Neuromorphic Silicon Neuron Circuits

    Science.gov (United States)

    Indiveri, Giacomo; Linares-Barranco, Bernabé; Hamilton, Tara Julia; van Schaik, André; Etienne-Cummings, Ralph; Delbruck, Tobi; Liu, Shih-Chii; Dudek, Piotr; Häfliger, Philipp; Renaud, Sylvie; Schemmel, Johannes; Cauwenberghs, Gert; Arthur, John; Hynna, Kai; Folowosele, Fopefolu; Saighi, Sylvain; Serrano-Gotarredona, Teresa; Wijekoon, Jayawan; Wang, Yingxue; Boahen, Kwabena

    2011-01-01

    Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain–machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance-based Hodgkin–Huxley models to bi-dimensional generalized adaptive integrate and fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips. PMID:21747754

  8. Neuromorphic silicon neuron circuits

    Directory of Open Access Journals (Sweden)

    Giacomo eIndiveri

    2011-05-01

    Full Text Available Hardware implementations of spiking neurons can be extremely useful for a large variety of applications, ranging from high-speed modeling of large-scale neural systems to real-time behaving systems, to bidirectional brain-machine interfaces. The specific circuit solutions used to implement silicon neurons depend on the application requirements. In this paper we describe the most common building blocks and techniques used to implement these circuits, and present an overview of a wide range of neuromorphic silicon neurons, which implement different computational models, ranging from biophysically realistic and conductance based Hodgkin-Huxley models to bi-dimensional generalized adaptive Integrate and Fire models. We compare the different design methodologies used for each silicon neuron design described, and demonstrate their features with experimental results, measured from a wide range of fabricated VLSI chips.

  9. Conception and test of an integrated circuit (ASIC): application to multiwire chambers and photomultipliers of the GRAAL experience

    International Nuclear Information System (INIS)

    Bugnet, H.

    1995-01-01

    The nuclear physics project GRAAL (GRenoble Anneau Accelerateur Laser) located at the European Synchrotron Radiation Facility (ESRF) in Grenoble produces a high energy photon beam with a maximum energy of 1.5 GeV. This gamma beam is obtained by Compton backscattering and can be polarized easily. It permits to probe, in an original way, the structure of the nucleon. The associated detector system includes multiwire proportional chambers and scintillator hodoscopes. A kit of six ASICs (Application Specific Integrated Circuit) has been developed and used for the signal processing and data conditioning up to the level of the data acquisition. This integrated electronics can be mounted right on the detectors. Obvious advantages, due to the reduction of the length of the wires and the number of connections, are an improvement of the signal quality and an increase of the reliability. The Wire Processor (WP), ASIC designed and tested during this thesis, treats the signals from the chamber wires and the photomultipliers. In one chip, there are two identical channels permitting the amplification, the amplitude discrimination, the generation of a programmable delay and the writing in a two state memory in case of coincidence with an external strobe signal. The measurement of the multiwire chamber efficiency demonstrates the functioning of the WP, the data conditioning electronics, the data acquisition and the chamber itself. (author). 62 refs., 111 figs., 13 tabs

  10. InP HEMT Integrated Circuits for Submillimeter Wave Radiometers in Earth Remote Sensing

    Science.gov (United States)

    Deal, William R.; Chattopadhyay, Goutam

    2012-01-01

    The operating frequency of InP integrated circuits has pushed well into the Submillimeter Wave frequency band, with amplification reported as high as 670 GHz. This paper provides an overview of current performance and potential application of InP HEMT to Submillimeter Wave radiometers for earth remote sensing.

  11. Specification and verification of gate-level VHDL models of synchronous and asynchronous circuits

    Science.gov (United States)

    Russinoff, David M.

    1995-01-01

    We present a mathematical definition of hardware description language (HDL) that admits a semantics-preserving translation to a subset of VHDL. Our HDL includes the basic VHDL propagation delay mechanisms and gate-level circuit descriptions. We also develop formal procedures for deriving and verifying concise behavioral specifications of combinational and sequential devices. The HDL and the specification procedures have been formally encoded in the computational logic of Boyer and Moore, which provides a LISP implementation as well as a facility for mechanical proof-checking. As an application, we design, specify, and verify a circuit that achieves asynchronous communication by means of the biphase mark protocol.

  12. Standard high-reliability integrated circuit logic packaging. [for deep space tracking stations

    Science.gov (United States)

    Slaughter, D. W.

    1977-01-01

    A family of standard, high-reliability hardware used for packaging digital integrated circuits is described. The design transition from early prototypes to production hardware is covered and future plans are discussed. Interconnections techniques are described as well as connectors and related hardware available at both the microcircuit packaging and main-frame level. General applications information is also provided.

  13. Maximum Temperature Detection System for Integrated Circuits

    Science.gov (United States)

    Frankiewicz, Maciej; Kos, Andrzej

    2015-03-01

    The paper describes structure and measurement results of the system detecting present maximum temperature on the surface of an integrated circuit. The system consists of the set of proportional to absolute temperature sensors, temperature processing path and a digital part designed in VHDL. Analogue parts of the circuit where designed with full-custom technique. The system is a part of temperature-controlled oscillator circuit - a power management system based on dynamic frequency scaling method. The oscillator cooperates with microprocessor dedicated for thermal experiments. The whole system is implemented in UMC CMOS 0.18 μm (1.8 V) technology.

  14. Design of CMOS analog integrated fractional-order circuits applications in medicine and biology

    CERN Document Server

    Tsirimokou, Georgia; Elwakil, Ahmed

    2017-01-01

    This book describes the design and realization of analog fractional-order circuits, which are suitable for on-chip implementation, capable of low-voltage operation and electronic adjustment of their characteristics. The authors provide a brief introduction to fractional-order calculus, followed by design issues for fractional-order circuits of various orders and types. The benefits of this approach are demonstrated with current-mode and voltage-mode filter designs. Electronically tunable emulators of fractional-order capacitors and inductors are presented, where the behavior of the corresponding chips fabricated using the AMS 0.35um CMOS process has been experimentally verified. Applications of fractional-order circuits are demonstrated, including a pre-processing stage suitable for the implementation of the Pan-Tompkins algorithm for detecting the QRS complexes of an electrocardiogram (ECG), a fully tunable implementation of the Cole-Cole model used for the modeling of biological tissues, and a simple, non-i...

  15. Radio frequency integrated circuit design for cognitive radio systems

    CERN Document Server

    Fahim, Amr

    2015-01-01

    This book fills a disconnect in the literature between Cognitive Radio systems and a detailed account of the circuit implementation and architectures required to implement such systems.  Throughout the book, requirements and constraints imposed by cognitive radio systems are emphasized when discussing the circuit implementation details.  In addition, this book details several novel concepts that advance state-of-the-art cognitive radio systems.  This is a valuable reference for anybody with background in analog and radio frequency (RF) integrated circuit design, needing to learn more about integrated circuits requirements and implementation for cognitive radio systems. ·         Describes in detail cognitive radio systems, as well as the circuit implementation and architectures required to implement them; ·         Serves as an excellent reference to state-of-the-art wideband transceiver design; ·         Emphasizes practical requirements and constraints imposed by cognitive radi...

  16. Charge Yield at Low Electric Fields: Considerations for Bipolar Integrated Circuits

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2013-01-01

    A significant reduction in total dose damage is observed when bipolar integrated circuits are irradiated at low temperature. This can be partially explained by the Onsager theory of recombination, which predicts a strong temperature dependence for charge yield under low-field conditions. Reduced damage occurs for biased as well as unbiased devices because the weak fringing field in thick bipolar oxides only affects charge yield near the Si/SiO2 interface, a relatively small fraction of the total oxide thickness. Lowering the temperature of bipolar ICs - either continuously, or for time periods when they are exposed to high radiation levels - provides an additional degree of freedom to improve total dose performance of bipolar circuits, particularly in space applications.

  17. Monolithic microwave integrated circuit water vapor radiometer

    Science.gov (United States)

    Sukamto, L. M.; Cooley, T. W.; Janssen, M. A.; Parks, G. S.

    1991-01-01

    A proof of concept Monolithic Microwave Integrated Circuit (MMIC) Water Vapor Radiometer (WVR) is under development at the Jet Propulsion Laboratory (JPL). WVR's are used to remotely sense water vapor and cloud liquid water in the atmosphere and are valuable for meteorological applications as well as for determination of signal path delays due to water vapor in the atmosphere. The high cost and large size of existing WVR instruments motivate the development of miniature MMIC WVR's, which have great potential for low cost mass production. The miniaturization of WVR components allows large scale deployment of WVR's for Earth environment and meteorological applications. Small WVR's can also result in improved thermal stability, resulting in improved calibration stability. Described here is the design and fabrication of a 31.4 GHz MMIC radiometer as one channel of a thermally stable WVR as a means of assessing MMIC technology feasibility.

  18. Reverse Engineering Camouflaged Sequential Integrated Circuits Without Scan Access

    OpenAIRE

    Massad, Mohamed El; Garg, Siddharth; Tripunitara, Mahesh

    2017-01-01

    Integrated circuit (IC) camouflaging is a promising technique to protect the design of a chip from reverse engineering. However, recent work has shown that even camouflaged ICs can be reverse engineered from the observed input/output behaviour of a chip using SAT solvers. However, these so-called SAT attacks have so far targeted only camouflaged combinational circuits. For camouflaged sequential circuits, the SAT attack requires that the internal state of the circuit is controllable and obser...

  19. Ion-beam apparatus and method for analyzing and controlling integrated circuits

    Science.gov (United States)

    Campbell, Ann N.; Soden, Jerry M.

    1998-01-01

    An ion-beam apparatus and method for analyzing and controlling integrated circuits. The ion-beam apparatus comprises a stage for holding one or more integrated circuits (ICs); a source means for producing a focused ion beam; and a beam-directing means for directing the focused ion beam to irradiate a predetermined portion of the IC for sufficient time to provide an ion-beam-generated electrical input signal to a predetermined element of the IC. The apparatus and method have applications to failure analysis and developmental analysis of ICs and permit an alteration, control, or programming of logic states or device parameters within the IC either separate from or in combination with applied electrical stimulus to the IC for analysis thereof. Preferred embodiments of the present invention including a secondary particle detector and an electron floodgun further permit imaging of the IC by secondary ions or electrons, and allow at least a partial removal or erasure of the ion-beam-generated electrical input signal.

  20. Design and test results of a low-noise readout integrated circuit for high-energy particle detectors

    International Nuclear Information System (INIS)

    Zhang Mingming; Chen Zhongjian; Zhang Yacong; Lu Wengao; Ji Lijiu

    2010-01-01

    A low-noise readout integrated circuit for high-energy particle detector is presented. The noise of charge sensitive amplifier was suppressed by using single-side amplifier and resistors as source degeneration. Continuous-time semi-Gaussian filter is chosen to avoid switch noise. The peaking time of pulse shaper and the gain can be programmed to satisfy multi-application. The readout integrated circuit has been designed and fabricated using a 0.35 μm double-poly triple-metal CMOS technology. Test results show the functions of the readout integrated circuit are correct. The equivalent noise charge with no detector connected is 500-700 e in the typical mode, the gain is tunable within 13-130 mV/fC and the peaking time varies from 0.7 to 1.6 μs, in which the average gain is about 20.5 mV/fC, and the linearity reaches 99.2%. (authors)

  1. Integration trends in monolithic power ICs: Application and technology challenges

    NARCIS (Netherlands)

    Rose, M.; Bergveld, H.J.

    2016-01-01

    This paper highlights the general trend towards further monolithic integration in power applications by enabling power management and interfacing solutions in advanced CMOS nodes. The need to combine high-density digital circuits, power-management circuits, and robust interfaces in a single

  2. An adjustable RF tuning element for microwave, millimeter wave, and submillimeter wave integrated circuits

    Science.gov (United States)

    Lubecke, Victor M.; Mcgrath, William R.; Rutledge, David B.

    1991-01-01

    Planar RF circuits are used in a wide range of applications from 1 GHz to 300 GHz, including radar, communications, commercial RF test instruments, and remote sensing radiometers. These circuits, however, provide only fixed tuning elements. This lack of adjustability puts severe demands on circuit design procedures and materials parameters. We have developed a novel tuning element which can be incorporated into the design of a planar circuit in order to allow active, post-fabrication tuning by varying the electrical length of a coplanar strip transmission line. It consists of a series of thin plates which can slide in unison along the transmission line, and the size and spacing of the plates are designed to provide a large reflection of RF power over a useful frequency bandwidth. Tests of this structure at 1 GHz to 3 Ghz showed that it produced a reflection coefficient greater than 0.90 over a 20 percent bandwidth. A 2 GHz circuit incorporating this tuning element was also tested to demonstrate practical tuning ranges. This structure can be fabricated for frequencies as high as 1000 GHz using existing micromachining techniques. Many commercial applications can benefit from this micromechanical RF tuning element, as it will aid in extending microwave integrated circuit technology into the high millimeter wave and submillimeter wave bands by easing constraints on circuit technology.

  3. LC Quadrature Generation in Integrated Circuits

    DEFF Research Database (Denmark)

    Christensen, Kåre Tais

    2001-01-01

    Today quadrature signals for IQ demodulation are provided through RC polyphase networks, quadrature oscillators or double frequency VCOs. This paper presents a new method for generating quadrature signals in integrated circuits using only inductors and capacitors. This LC quadrature generation...

  4. Focused ion beam damage to MOS integrated circuits

    International Nuclear Information System (INIS)

    Fleetwood, D.M.; Campbell, Ann N.; Hembree, Charles E.; Tangyunyong, Paiboon; Jessing, Jeffrey R.; Soden, Jerry M.

    2000-01-01

    Commercial focused ion beam (FIB) systems are commonly used to image integrated circuits (ICS) after device processing, especially in failure analysis applications. FIB systems are also often employed to repair faults in metal lines for otherwise functioning ICS, and are being evaluated for applications in film deposition and nanofabrication. A problem that is often seen in FIB imaging and repair is that ICS can be damaged during the exposure process. This can result in degraded response or out-right circuit failure. Because FIB processes typically require the surface of an IC to be exposed to an intense beam of 30--50 keV Ga + ions, both charging and secondary radiation damage are potential concerns. In previous studies, both types of effects have been suggested as possible causes of device degradation, depending on the type of device examined and/or the bias conditions. Understanding the causes of this damage is important for ICS that are imaged or repaired by a FIB between manufacture and operation, since the performance and reliability of a given IC is otherwise at risk in subsequent system application. In this summary, the authors discuss the relative roles of radiation damage and charging effects during FIB imaging. Data from exposures of packaged parts under controlled bias indicate the possibility for secondary radiation damage during FIB exposure. On the other hand, FIB exposure of unbiased wafers (a more common application) typically results in damage caused by high-voltage stress or electrostatic discharge. Implications for FIB exposure and subsequent IC use are discussed

  5. Dictionary-based image reconstruction for superresolution in integrated circuit imaging.

    Science.gov (United States)

    Cilingiroglu, T Berkin; Uyar, Aydan; Tuysuzoglu, Ahmet; Karl, W Clem; Konrad, Janusz; Goldberg, Bennett B; Ünlü, M Selim

    2015-06-01

    Resolution improvement through signal processing techniques for integrated circuit imaging is becoming more crucial as the rapid decrease in integrated circuit dimensions continues. Although there is a significant effort to push the limits of optical resolution for backside fault analysis through the use of solid immersion lenses, higher order laser beams, and beam apodization, signal processing techniques are required for additional improvement. In this work, we propose a sparse image reconstruction framework which couples overcomplete dictionary-based representation with a physics-based forward model to improve resolution and localization accuracy in high numerical aperture confocal microscopy systems for backside optical integrated circuit analysis. The effectiveness of the framework is demonstrated on experimental data.

  6. Heavy ions testing experimental results on programmable integrated circuits

    International Nuclear Information System (INIS)

    Velazco, R.; Provost-Grellier, A.

    1988-01-01

    The natural radiation environment in space has been shown to produce anomalies in satellite-borne microelectronics. It becomes then mandatory to define qualification strategies allowing to choose the less vulnerable circuits. In this paper, is presented a strategy devoted to one of the most critical effects, the soft errors (so called upset). The method addresses programmable integrated circuits i.e. circuits able to execute an instruction or command set. Experimental results on representative circuits will illustrate the approach. 11 refs [fr

  7. Interconnect rise time in superconducting integrating circuits

    International Nuclear Information System (INIS)

    Preis, D.; Shlager, K.

    1988-01-01

    The influence of resistive losses on the voltage rise time of an integrated-circuit interconnection is reported. A distribution-circuit model is used to present the interconnect. Numerous parametric curves are presented based on numerical evaluation of the exact analytical expression for the model's transient response. For the superconducting case in which the series resistance of the interconnect approaches zero, the step-response rise time is longer but signal strength increases significantly

  8. Latch-up control in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Ochoa, A.; Dawes, W.; Estreich, D.; Packard, H.

    1979-01-01

    The potential for latch-up, a pnpn self-sustaining low impedance state, is inherent in standard bulk CMOS-integrated circuit structures. Under normal bias, the parasitic SCR is in its blocking state but, if subjected to a large voltage spike or if exposed to an ionizing environment, triggering may occur. This may result in device burn-out or loss of state. The problem has been extensively studied for space and weapons applications. Prevention of latch-up has been achieved in conservative design (approx. 9 μm p-well depths) by the use of minority lifetime control methods such as gold doping and neutron irradiation and by modifying the base transport factor with buried layers. The push toward VLSI densities will enhance parasitic action sufficiently so that the problem will become of more universal concern. The paper will surveys latch-up control methods presently employed for weapons and space applications on present (approx. 9 μm p-well) CMOS and indicates the extent of their applicability to VLSI designs

  9. Silicon Photonic Integrated Circuit Mode Multiplexer

    DEFF Research Database (Denmark)

    Ding, Yunhong; Ou, Haiyan; Xu, Jing

    2013-01-01

    We propose and demonstrate a novel silicon photonic integrated circuit enabling multiplexing of orthogonal modes in a few-mode fiber (FMF). By selectively launching light to four vertical grating couplers, all six orthogonal spatial and polarization modes supported by the FMF are successfully...

  10. Integrated optical switch circuit operating under FPGA control

    NARCIS (Netherlands)

    Stabile, R.; Zal, M.; Williams, K.A.; Bienstman, P.; Morthier, G.; Roelkens, G.; et al., xx

    2011-01-01

    Integrated photonic circuits are enabling an abrupt step change in networking systems providing massive bandwidth and record transmission. The increasing complexity of high connectivity photonic integrated switches requires sophisticated control planes and more intimate high speed electronics. Here

  11. A new approach of optimization procedure for superconducting integrated circuits

    International Nuclear Information System (INIS)

    Saitoh, K.; Soutome, Y.; Tarutani, Y.; Takagi, K.

    1999-01-01

    We have developed and tested a new circuit simulation procedure for superconducting integrated circuits which can be used to optimize circuit parameters. This method reveals a stable operation region in the circuit parameter space in connection with the global bias margin by means of a contour plot of the global bias margin versus the circuit parameters. An optimal set of parameters with margins larger than these of the initial values has been found in the stable region. (author)

  12. Assessment of Durable SiC JFET Technology for +600 C to -125 C Integrated Circuit Operation

    Science.gov (United States)

    Neudeck, P. G.; Krasowski, M. J.; Prokop, N. F.

    2011-01-01

    Electrical characteristics and circuit design considerations for prototype 6H-SiC JFET integrated circuits (ICs) operating over the broad temperature range of -125 C to +600 C are described. Strategic implementation of circuits with transistors and resistors in the same 6H-SiC n-channel layer enabled ICs with nearly temperature-independent functionality to be achieved. The frequency performance of the circuits declined at temperatures increasingly below or above room temperature, roughly corresponding to the change in 6H-SiC n-channel resistance arising from incomplete carrier ionization at low temperature and decreased electron mobility at high temperature. In addition to very broad temperature functionality, these simple digital and analog demonstration integrated circuits successfully operated with little change in functional characteristics over the course of thousands of hours at 500 C before experiencing interconnect-related failures. With appropriate further development, these initial results establish a new technology foundation for realizing durable 500 C ICs for combustion engine sensing and control, deep-well drilling, and other harsh-environment applications.

  13. CMOS-based carbon nanotube pass-transistor logic integrated circuits

    Science.gov (United States)

    Ding, Li; Zhang, Zhiyong; Liang, Shibo; Pei, Tian; Wang, Sheng; Li, Yan; Zhou, Weiwei; Liu, Jie; Peng, Lian-Mao

    2012-01-01

    Field-effect transistors based on carbon nanotubes have been shown to be faster and less energy consuming than their silicon counterparts. However, ensuring these advantages are maintained for integrated circuits is a challenge. Here we demonstrate that a significant reduction in the use of field-effect transistors can be achieved by constructing carbon nanotube-based integrated circuits based on a pass-transistor logic configuration, rather than a complementary metal-oxide semiconductor configuration. Logic gates are constructed on individual carbon nanotubes via a doping-free approach and with a single power supply at voltages as low as 0.4 V. The pass-transistor logic configurarion provides a significant simplification of the carbon nanotube-based circuit design, a higher potential circuit speed and a significant reduction in power consumption. In particular, a full adder, which requires a total of 28 field-effect transistors to construct in the usual complementary metal-oxide semiconductor circuit, uses only three pairs of n- and p-field-effect transistors in the pass-transistor logic configuration. PMID:22334080

  14. A numerical integration-based yield estimation method for integrated circuits

    International Nuclear Information System (INIS)

    Liang Tao; Jia Xinzhang

    2011-01-01

    A novel integration-based yield estimation method is developed for yield optimization of integrated circuits. This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal, the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation (BCT). In order to reduce the estimation variances of the model parameters of the density function, orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations. The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed. Two yield estimation examples, a fourth-order OTA-C filter and a three-dimensional (3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values. Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases. Therefore, our method is more suitable for parametric yield optimization. (semiconductor integrated circuits)

  15. A numerical integration-based yield estimation method for integrated circuits

    Energy Technology Data Exchange (ETDEWEB)

    Liang Tao; Jia Xinzhang, E-mail: tliang@yahoo.cn [Key Laboratory of Ministry of Education for Wide Bandgap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi' an 710071 (China)

    2011-04-15

    A novel integration-based yield estimation method is developed for yield optimization of integrated circuits. This method tries to integrate the joint probability density function on the acceptability region directly. To achieve this goal, the simulated performance data of unknown distribution should be converted to follow a multivariate normal distribution by using Box-Cox transformation (BCT). In order to reduce the estimation variances of the model parameters of the density function, orthogonal array-based modified Latin hypercube sampling (OA-MLHS) is presented to generate samples in the disturbance space during simulations. The principle of variance reduction of model parameters estimation through OA-MLHS together with BCT is also discussed. Two yield estimation examples, a fourth-order OTA-C filter and a three-dimensional (3D) quadratic function are used for comparison of our method with Monte Carlo based methods including Latin hypercube sampling and importance sampling under several combinations of sample sizes and yield values. Extensive simulations show that our method is superior to other methods with respect to accuracy and efficiency under all of the given cases. Therefore, our method is more suitable for parametric yield optimization. (semiconductor integrated circuits)

  16. Integrated Circuit Electromagnetic Immunity Handbook

    Science.gov (United States)

    Sketoe, J. G.

    2000-08-01

    This handbook presents the results of the Boeing Company effort for NASA under contract NAS8-98217. Immunity level data for certain integrated circuit parts are discussed herein, along with analytical techniques for applying the data to electronics systems. This handbook is built heavily on the one produced in the seventies by McDonnell Douglas Astronautics Company (MDAC, MDC Report E1929 of 1 August 1978, entitled Integrated Circuit Electromagnetic Susceptibility Handbook, known commonly as the ICES Handbook, which has served countless systems designers for over 20 years). Sections 2 and 3 supplement the device susceptibility data presented in section 4 by presenting information on related material required to use the IC susceptibility information. Section 2 concerns itself with electromagnetic susceptibility analysis and serves as a guide in using the information contained in the rest of the handbook. A suggested system hardening requirements is presented in this chapter. Section 3 briefly discusses coupling and shielding considerations. For conservatism and simplicity, a worst case approach is advocated to determine the maximum amount of RF power picked up from a given field. This handbook expands the scope of the immunity data in this Handbook is to of 10 MHz to 10 GHz. However, the analytical techniques provided are applicable to much higher frequencies as well. It is expected however, that the upper frequency limit of concern is near 10 GHz. This is due to two factors; the pickup of microwave energy on system cables and wiring falls off as the square of the wavelength, and component response falls off at a rapid rate due to the effects of parasitic shunt paths for the RF energy. It should be noted also that the pickup on wires and cables does not approach infinity as the frequency decreases (as would be expected by extrapolating the square law dependence of the high frequency roll-off to lower frequencies) but levels off due to mismatch effects.

  17. 76 FR 58041 - Certain Digital Televisions Containing Integrated Circuit Devices and Components Thereof; Notice...

    Science.gov (United States)

    2011-09-19

    ... Integrated Circuit Devices and Components Thereof; Notice of Institution of Investigation; Institution of... integrated circuit devices and components thereof by reason of infringement of certain claims of U.S. Patent... after importation of certain digital televisions containing integrated circuit devices and components...

  18. Integrated optical circuit engineering IV; Proceedings of the Meeting, Cambridge, MA, Sept. 16, 17, 1986

    Science.gov (United States)

    Mentzer, Mark A.; Sriram, S.

    The design and implementation of integrated optical circuits are discussed in reviews and reports. Topics addressed include lithium niobate devices, silicon integrated optics, waveguide phenomena, coupling considerations, processing technology, nonlinear guided-wave optics, integrated optics for fiber systems, and systems considerations and applications. Also included are eight papers and a panel discussion from an SPIE conference on the processing of guided-wave optoelectronic materials (held in Los Angeles, CA, on January 21-22, 1986).

  19. Oscillator circuits frontiers in design, analysis and applications

    CERN Document Server

    2016-01-01

    This book surveys recent developments in the design, analysis and applications of oscillator circuit design. It highlights developments in the analysis of synchronization and wave phenomena, new analytical and design methods and their application, and novel engineering applications of oscillator circuits.

  20. Nano integrated circuit process

    International Nuclear Information System (INIS)

    Yoon, Yung Sup

    2004-02-01

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  1. Nano integrated circuit process

    Energy Technology Data Exchange (ETDEWEB)

    Yoon, Yung Sup

    2004-02-15

    This book contains nine chapters, which are introduction of manufacture of semiconductor chip, oxidation such as Dry-oxidation, wet oxidation, oxidation model and oxide film, diffusion like diffusion process, diffusion equation, diffusion coefficient and diffusion system, ion implantation, including ion distribution, channeling, multiimplantation and masking and its system, sputtering such as CVD and PVD, lithography, wet etch and dry etch, interconnection and flattening like metal-silicon connection, silicide, multiple layer metal process and flattening, an integrated circuit process, including MOSFET and CMOS.

  2. An optoelectronic integrated device including a laser and its driving circuit

    Energy Technology Data Exchange (ETDEWEB)

    Matsueda, H.; Nakano, H.; Tanaka, T.P.

    1984-10-01

    A monolithic optoelectronic integrated circuit (OEIC) including a laser diode, photomonitor and driving and detecting circuits has been fabricated on a semi-insulating GaAs substrate. The OEIC has a horizontal integrating structure which is suitable for realising high-density multifunctional devices. The fabricating process and the static and dynamic characteristics of the optical and electronic elements are described. The preliminary results of the co-operative operation of the laser and its driving circuit are also presented.

  3. Controller with an ispLS1016 circuit for the utilization of a TV fifo in spectrometric

    International Nuclear Information System (INIS)

    Arista Romeu, E.; Osorio Deliz, J.F.; Toledo Acosta, R.B.

    1997-01-01

    It is described the design of a controller based in the integrated circuit ispLS1016 for the utilization of a 256K x 8 FIFO originally for digital video applications in spectroscopy., Co, Zn, Sn, U and Th (deposited in filter paper) are The design was based upon an integrated circuit of the ispLSI family, which allowed drastically to diminish the quantity of utilized components, to obtain a flexible design in less time and to fulfill other specific requirements for spectroscopy applications

  4. Electromechanical modeling of a honeycomb core integrated vibration energy converter with increased specific power for energy harvesting applications

    Science.gov (United States)

    Chandrasekharan, Nataraj

    Innovation in integrated circuit technology along with improved manufacturing processes has resulted in considerable reduction in power consumption of electromechanical devices. Majority of these devices are currently powered by batteries. However, the issues posed by batteries, including the need for frequent battery recharge/replacement has resulted in a compelling need for alternate energy to achieve self-sufficient device operation or to supplement battery power. Vibration based energy harvesting methods through piezoelectric transduction provides with a promising potential towards replacing or supplementing battery power source. However, current piezoelectric energy harvesters generate low specific power (power-to-weight ratio) when compared to batteries that the harvesters seek to replace or supplement. In this study, the potential of integrating lightweight cellular honeycomb structures with existing piezoelectric device configurations (bimorph) to achieve higher specific power is investigated. It is shown in this study that at low excitation frequency ranges, replacing the solid continuous substrate of a conventional piezoelectric bimorph with honeycomb structures of the same material results in a significant increase in power-to-weight ratio of the piezoelectric harvester. In order to maximize the electrical response of vibration based power harvesters, the natural frequency of these harvesters is designed to match the input driving frequency. The commonly used technique of adding a tip mass is employed to lower the natural frequency (to match driving frequency) of both, solid and honeycomb substrate bimorphs. At higher excitation frequency, the natural frequency of the traditional solid substrate bimorph can only be altered (to match driving frequency) through a change in global geometric design parameters, typically achieved by increasing the thickness of the harvester. As a result, the size of the harvester is increased and can be disadvantageous

  5. Programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-04-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  6. Empty substrate integrated waveguide technology for E plane high-frequency and high-performance circuits

    Science.gov (United States)

    Belenguer, Angel; Cano, Juan Luis; Esteban, Héctor; Artal, Eduardo; Boria, Vicente E.

    2017-01-01

    Substrate integrated circuits (SIC) have attracted much attention in the last years because of their great potential of low cost, easy manufacturing, integration in a circuit board, and higher-quality factor than planar circuits. A first suite of SIC where the waves propagate through dielectric have been first developed, based on the well-known substrate integrated waveguide (SIW) and related technological implementations. One step further has been made with a new suite of empty substrate integrated waveguides, where the waves propagate through air, thus reducing the associated losses. This is the case of the empty substrate integrated waveguide (ESIW) or the air-filled substrate integrated waveguide (air-filled SIW). However, all these SIC are H plane structures, so classical H plane solutions in rectangular waveguides have already been mapped to most of these new SIC. In this paper a novel E plane empty substrate integrated waveguide (ESIW-E) is presented. This structure allows to easily map classical E plane solutions in rectangular waveguide to this new substrate integrated solution. It is similar to the ESIW, although more layers are needed to build the structure. A wideband transition (covering the frequency range between 33 GHz and 50 GHz) from microstrip to ESIW-E is designed and manufactured. Measurements are successfully compared with simulation, proving the validity of this new SIC. A broadband high-frequency phase shifter (for operation from 35 GHz to 47 GHz) is successfully implemented in ESIW-E, thus proving the good performance of this new SIC in a practical application.

  7. Removal of Gross Air Embolization from Cardiopulmonary Bypass Circuits with Integrated Arterial Line Filters: A Comparison of Circuit Designs.

    Science.gov (United States)

    Reagor, James A; Holt, David W

    2016-03-01

    Advances in technology, the desire to minimize blood product transfusions, and concerns relating to inflammatory mediators have lead many practitioners and manufacturers to minimize cardiopulmonary bypass (CBP) circuit designs. The oxygenator and arterial line filter (ALF) have been integrated into one device as a method of attaining a reduction in prime volume and surface area. The instructions for use of a currently available oxygenator with integrated ALF recommends incorporating a recirculation line distal to the oxygenator. However, according to an unscientific survey, 70% of respondents utilize CPB circuits incorporating integrated ALFs without a path of recirculation distal to the oxygenator outlet. Considering this circuit design, the ability to quickly remove a gross air bolus in the blood path distal to the oxygenator may be compromised. This in vitro study was designed to determine if the time required to remove a gross air bolus from a CPB circuit without a path of recirculation distal to the oxygenator will be significantly longer than that of a circuit with a path of recirculation distal to the oxygenator. A significant difference was found in the mean time required to remove a gross air bolus between the circuit designs (p = .0003). Additionally, There was found to be a statistically significant difference in the mean time required to remove a gross air bolus between Trial 1 and Trials 4 (p = .015) and 5 (p =.014) irrespective of the circuit design. Under the parameters of this study, a recirculation line distal to an oxygenator with an integrated ALF significantly decreases the time it takes to remove an air bolus from the CPB circuit and may be safer for clinical use than the same circuit without a recirculation line.

  8. Historical overview and future approach on integrated photonic circuit technologies; Shusekiko gijutsu no ayumi to korekara no tenkai

    Energy Technology Data Exchange (ETDEWEB)

    Nakajima, H. [Waseda University, Tokyo (Japan). School of Science and Engineering

    1997-08-01

    Integration of optical circuits is discussed. A number of devices used in optical communication even today treat light beams emitted by optical fibers or by semiconductor lasers as spatial beams. In making preparations for mass production in the future, the effect of mere miniaturization of optical systems on optical substrates is quite limited. Realizing the presence of such a limit is one of the motivations to endeavor to embody integrated photonic circuits. In this report, comments will be focused only on the technology of waveguide type integration. Integrated circuits on a compound semiconductor substrate are quite difficult to deal with, more difficult than generally supposed. This is a task with a bright future when reviewed from the viewpoint of the effective use of the quantum effect. If integration is to be effected on a Si substrate, possibilities are high that the effort will bear fruit now that the substrate can withstand the full application of micro-machining. An LiNbO3 wave path, however, wants a breakthrough in the switching technology. As for the material to coat substrates with, polymer based nonlinear optical materials are not satisfying. The integrated photonic circuit technology can be said to be on the stage where questions limitlessly surface also in the science of materials. 14 refs., 2 tabs.

  9. Contribution to the study of ionizing radiation effects on bipolar technologies: application to the hardening of integrated circuits

    International Nuclear Information System (INIS)

    Briand, R.

    2001-01-01

    The use of analog integrated circuits in radiation environments raises the problem of their behaviour with respect to the different effects induced by particles and radiations. The first chapter of this thesis presents the origins of radiations and the different topologies of bipolar transistors. The effects of ionizing radiations on bipolar components, like cumulative dose, dose rates, and single events, are detailed in three distinct chapters with the same scientifical approach. The simulation of the physical degradation phenomena of the components allows to establish original electrical models coming from the understanding of the induced mechanisms. These models are used to evaluate the degradations occurring in linear analogic circuits. Common and original hardening methods are presented, some of which are applied to bipolar integrated circuit technologies. Finally, experimental laser beam test techniques are presented, which are used to reproduce the dose rate and the single events. (J.S.)

  10. Organic printed photonics: From microring lasers to integrated circuits.

    Science.gov (United States)

    Zhang, Chuang; Zou, Chang-Ling; Zhao, Yan; Dong, Chun-Hua; Wei, Cong; Wang, Hanlin; Liu, Yunqi; Guo, Guang-Can; Yao, Jiannian; Zhao, Yong Sheng

    2015-09-01

    A photonic integrated circuit (PIC) is the optical analogy of an electronic loop in which photons are signal carriers with high transport speed and parallel processing capability. Besides the most frequently demonstrated silicon-based circuits, PICs require a variety of materials for light generation, processing, modulation, and detection. With their diversity and flexibility, organic molecular materials provide an alternative platform for photonics; however, the versatile fabrication of organic integrated circuits with the desired photonic performance remains a big challenge. The rapid development of flexible electronics has shown that a solution printing technique has considerable potential for the large-scale fabrication and integration of microsized/nanosized devices. We propose the idea of soft photonics and demonstrate the function-directed fabrication of high-quality organic photonic devices and circuits. We prepared size-tunable and reproducible polymer microring resonators on a wafer-scale transparent and flexible chip using a solution printing technique. The printed optical resonator showed a quality (Q) factor higher than 4 × 10(5), which is comparable to that of silicon-based resonators. The high material compatibility of this printed photonic chip enabled us to realize low-threshold microlasers by doping organic functional molecules into a typical photonic device. On an identical chip, this construction strategy allowed us to design a complex assembly of one-dimensional waveguide and resonator components for light signal filtering and optical storage toward the large-scale on-chip integration of microscopic photonic units. Thus, we have developed a scheme for soft photonic integration that may motivate further studies on organic photonic materials and devices.

  11. Electronic circuits fundamentals & applications

    CERN Document Server

    Tooley, Mike

    2015-01-01

    Electronics explained in one volume, using both theoretical and practical applications.New chapter on Raspberry PiCompanion website contains free electronic tools to aid learning for students and a question bank for lecturersPractical investigations and questions within each chapter help reinforce learning Mike Tooley provides all the information required to get to grips with the fundamentals of electronics, detailing the underpinning knowledge necessary to appreciate the operation of a wide range of electronic circuits, including amplifiers, logic circuits, power supplies and oscillators. The

  12. Power electronics handbook components, circuits and applications

    CERN Document Server

    Mazda, F F

    1993-01-01

    Power Electronics Handbook: Components, Circuits, and Applications is a collection of materials about power components, circuit design, and applications. Presented in a practical form, theoretical information is given as formulae. The book is divided into three parts. Part 1 deals with the usual components found in power electronics such as semiconductor devices and power semiconductor control components, their electronic compatibility, and protection. Part 2 tackles parts and principles related to circuits such as switches; link frequency chargers; converters; and AC line control, and Part 3

  13. Integrated circuits and logic operations based on single-layer MoS2.

    Science.gov (United States)

    Radisavljevic, Branimir; Whitwick, Michael Brian; Kis, Andras

    2011-12-27

    Logic circuits and the ability to amplify electrical signals form the functional backbone of electronics along with the possibility to integrate multiple elements on the same chip. The miniaturization of electronic circuits is expected to reach fundamental limits in the near future. Two-dimensional materials such as single-layer MoS(2) represent the ultimate limit of miniaturization in the vertical dimension, are interesting as building blocks of low-power nanoelectronic devices, and are suitable for integration due to their planar geometry. Because they are less than 1 nm thin, 2D materials in transistors could also lead to reduced short channel effects and result in fabrication of smaller and more power-efficient transistors. Here, we report on the first integrated circuit based on a two-dimensional semiconductor MoS(2). Our integrated circuits are capable of operating as inverters, converting logical "1" into logical "0", with room-temperature voltage gain higher than 1, making them suitable for incorporation into digital circuits. We also show that electrical circuits composed of single-layer MoS(2) transistors are capable of performing the NOR logic operation, the basis from which all logical operations and full digital functionality can be deduced.

  14. SEMICONDUCTOR INTEGRATED CIRCUITS: A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth

    Science.gov (United States)

    Tao, Tong; Baoyong, Chi; Ziqiang, Wang; Ying, Zhang; Hanjun, Jiang; Zhihua, Wang

    2010-05-01

    A reconfigurable analog baseband circuit for WLAN, WCDMA, and Bluetooth in 0.35 μm CMOS is presented. The circuit consists of two variable gain amplifiers (VGA) in cascade and a Gm-C elliptic low-pass filter (LPF). The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption, the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application. Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN, 8.9 mW for WCDMA and only 6.5 mW for Bluetooth, all with a 3 V power supply. The analog baseband circuit could provide -10 to +40 dB variable gain, third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth, fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN, respectively.

  15. Silicon integrated circuits advances in materials and device research

    CERN Document Server

    Kahng, Dawon

    1981-01-01

    Silicon Integrated Circuits, Part B covers the special considerations needed to achieve high-power Si-integrated circuits. The book presents articles about the most important operations needed for the high-power circuitry, namely impurity diffusion and oxidation; crystal defects under thermal equilibrium in silicon and the development of high-power device physics; and associated technology. The text also describes the ever-evolving processing technology and the most promising approaches, along with the understanding of processing-related areas of physics and chemistry. Physicists, chemists, an

  16. Long-wavelength photonic integrated circuits and avalanche photodetectors

    Science.gov (United States)

    Tsou, Yi-Jen D.; Zaytsev, Sergey; Pauchard, Alexandre; Hummel, Steve; Lo, Yu-Hwa

    2001-10-01

    Fast-growing internet traffic volume require high data communication bandwidth over longer distances. Access network bottlenecks put pressure on short-range (SR) telecommunication systems. To effectively address these datacom and telecom market needs, low-cost, high-speed laser modules at 1310 to 1550 nm wavelengths and avalanche photodetectors are required. The great success of GaAs 850nm VCSEls for Gb/s Ethernet has motivated efforts to extend VCSEL technology to longer wavelengths in the 1310 and 1550 nm regimes. However, the technological challenges associated with materials for long wavelength VCSELs are tremendous. Even with recent advances in this area, it is believed that significant additional development is necessary before long wavelength VCSELs that meet commercial specifications will be widely available. In addition, the more stringent OC192 and OC768 specifications for single-mode fiber (SMF) datacom may require more than just a long wavelength laser diode, VCSEL or not, to address numerous cost and performance issues. We believe that photonic integrated circuits (PICs), which compactly integrate surface-emitting lasers with additional active and passive optical components with extended functionality, will provide the best solutions to today's problems. Photonic integrated circuits have been investigated for more than a decade. However, they have produced limited commercial impact to date primarily because the highly complicated fabrication processes produce significant yield and device performance issues. In this presentation, we will discuss a new technology platform of InP-based PICs compatible with surface-emitting laser technology, as well as a high data rate externally modulated laser module. Avalanche photodetectors (APDs) are the key component in the receiver to achieve high data rate over long transmission distance because of their high sensitivity and large gain- bandwidth product. We have used wafer fusion technology to achieve In

  17. Leaky Integrate-and-Fire Neuron Circuit Based on Floating-Gate Integrator

    Science.gov (United States)

    Kornijcuk, Vladimir; Lim, Hyungkwang; Seok, Jun Yeong; Kim, Guhyun; Kim, Seong Keun; Kim, Inho; Choi, Byung Joon; Jeong, Doo Seok

    2016-01-01

    The artificial spiking neural network (SNN) is promising and has been brought to the notice of the theoretical neuroscience and neuromorphic engineering research communities. In this light, we propose a new type of artificial spiking neuron based on leaky integrate-and-fire (LIF) behavior. A distinctive feature of the proposed FG-LIF neuron is the use of a floating-gate (FG) integrator rather than a capacitor-based one. The relaxation time of the charge on the FG relies mainly on the tunnel barrier profile, e.g., barrier height and thickness (rather than the area). This opens up the possibility of large-scale integration of neurons. The circuit simulation results offered biologically plausible spiking activity (circuit was subject to possible types of noise, e.g., thermal noise and burst noise. The simulation results indicated remarkable distributional features of interspike intervals that are fitted to Gamma distribution functions, similar to biological neurons in the neocortex. PMID:27242416

  18. Superconducting quantum circuits theory and application

    OpenAIRE

    Deng, Xiuhao

    2015-01-01

    Superconducting quantum circuit models are widely used to understand superconducting devices. This thesis consists of four studies wherein the superconducting quantum circuit is used to illustrate challenges related to quantum information encoding and processing, quantum simulation, quantum signal detection and amplification.The existence of scalar Aharanov-Bohm phase has been a controversial topic for decades. Scalar AB phase, defined as time integral of electric potential, gives rises to a...

  19. Integrated digital superconducting logic circuits for the quantum synthesizer. Report

    International Nuclear Information System (INIS)

    Buchholz, F.I.; Kohlmann, J.; Khabipov, M.; Brandt, C.M.; Hagedorn, D.; Balashov, D.; Maibaum, F.; Tolkacheva, E.; Niemeyer, J.

    2006-11-01

    This report presents the results, which were reached in the framework of the BMBF cooperative plan ''Quantum Synthesizer'' in the partial plan ''Integrated Digital Superconducting Logic Circuits''. As essential goal of the plan a novel instrument on the base of quantum-coherent superconducting circuits should be developed. which allows to generate praxis-relevant wave forms with quantum accuracy, the quantum synthesizer. The main topics of development of the reported partial plan lied at the one hand in the development of integrated, digital, superconducting circuit in rapid-single-flux (RSFQ) quantum logics for the pattern generator of the quantum synthesizer, at the other hand in the further development of the fabrication technology for the aiming of high circuit complexity. In order to fulfil these requirements at the PTB a new design system was implemented, based on the software of Cadence. Together with the required RSFQ extensions for the design of digital superconducting circuits was a platform generated, on which the reachable circuit complexity is exclusively limited by the technology parameters of the available fabrication technology: Physical simulations are with PSCAN up to a complexity of more than 1000 circuit elements possible; furthermore VHDL allows the verification of arbitrarily large circuit architectures. In accordance for this the production line at the PTB was brought to a level, which allows in Nb/Al-Al x O y /Nb SIS technology implementation the fabrication of highly integrable RSFQ circuit architectures. The developed and fabricated basic circuits of the pattern generator have proved correct functionality and reliability in the measuring operation. Thereby for the circular RSFQ shift registers a key role as local memories in the construction of the pattern generator is devolved upon. The registers were realized with the aimed bit lengths up to 128 bit and with reachable signal-processing speeds of above 10 GHz. At the interface RSFQ

  20. Nano devices and circuit techniques for low-energy applications and energy harvesting

    CERN Document Server

    2016-01-01

    This book describes the development of core technologies to address two of the most challenging issues in research for future IT platform development, namely innovative device design and reduction of energy consumption. Three key devices, the FinFET, the TunnelFET, and the electromechanical nanoswitch are described with extensive details of use for practical applications. Energy issues are also covered in a tutorial fashion from material physics, through device technology, to innovative circuit design. The strength of this book lies in its holistic approach dealing with material trends, state-of-the-art of key devices, new examples of circuits and systems applications.    This is the first of three books based on the Integrated Smart Sensors research project, which describe the development of innovative devices, circuits, and system-level enabling technologies.  The aim of the project was to develop common platforms on which various devices and sensors can be loaded, and to create systems offering signific...

  1. Multislice imaging of integrated circuits by precession X-ray ptychography.

    Science.gov (United States)

    Shimomura, Kei; Hirose, Makoto; Takahashi, Yukio

    2018-01-01

    A method for nondestructively visualizing multisection nanostructures of integrated circuits by X-ray ptychography with a multislice approach is proposed. In this study, tilt-series ptychographic diffraction data sets of a two-layered circuit with a ∼1.4 µm gap at nine incident angles are collected in a wide Q range and then artifact-reduced phase images of each layer are successfully reconstructed at ∼10 nm resolution. The present method has great potential for the three-dimensional observation of flat specimens with thickness on the order of 100 µm, such as three-dimensional stacked integrated circuits based on through-silicon vias, without laborious sample preparation.

  2. Dielectric isolation for power integrated circuits; Isolation dielectrique enterree pour les circuits integres de puissance

    Energy Technology Data Exchange (ETDEWEB)

    Zerrouk, D.

    1997-07-18

    Considerable efforts have been recently directed towards integrating onto the same chip, sense or protection elements that is low voltage analog and/or digital control circuitry together with high voltage/high current devices. Most of these so called `smart power` devices use either self isolation, junction isolation or Silicon-On-Insulator (SOI) to integrate low voltage elements with vertical power devices. Dielectric isolation is superior to the other isolation techniques such as self isolation or junction isolation. Thesis work consists of the study of the feasibility of a dielectric technology based on the melting and the solidification in a Rapid Thermal Processing furnace (RTP), of thick polysilicon films deposited on oxide. The purpose of this technique is to obtain substrate with localized SOI structures for smart power applications. SOI technology offers significant potential advantages, such as non-occurrence of latch-up in CMOS structures, high packaging density, low parasitic capacitance and the possibility of 3D structures. In addition, SOI technology using thick silicon films (10-100 {mu}m) offers special advantages for high voltage integrated circuits. Several techniques have been developed to form SOI films. Zone melting recrystallization is one of the most promising for localized SOI. The SOI structures have first been analyzed in term of extended defects. N-channel MOSFET`s transistors have also been fabricated in the SOI substrates and electrically characterized (threshold voltages, off-state leakage current, mobilities,...). The SOI transistors exhibit good characteristics, although inferior to witness transistors. The recrystallized silicon films are therefore found to be suitable for the fabrication of SOI devices. (author) 106 refs.

  3. 60-GHz integrated-circuit high data rate quadriphase shift keying exciter and modulator

    Science.gov (United States)

    Grote, A.; Chang, K.

    1984-01-01

    An integrated-circuit quadriphase shift keying (QPSK) exciter and modulator have demonstrated excellent performance directly modulating a carrier frequency of 60 GHz with an output phase error of less than 3 degrees and maximum amplitude error of 0.5 dB. The circuit consists of a 60-GHz Gunn VCO phase-locked to a low-frequency reference source, a 4th subharmonic mixer, and a QPSK modlator packaged into a small volume of 1.8 x 2.5 x 0.35 in. The use of microstrip has the advantages of small size, light-weight, and low-cost fabrication. The unit has the potential for multigigabit data rate applications.

  4. Electronic logic circuits

    CERN Document Server

    Gibson, J

    2013-01-01

    Most branches of organizing utilize digital electronic systems. This book introduces the design of such systems using basic logic elements as the components. The material is presented in a straightforward manner suitable for students of electronic engineering and computer science. The book is also of use to engineers in related disciplines who require a clear introduction to logic circuits. This third edition has been revised to encompass the most recent advances in technology as well as the latest trends in components and notation. It includes a wide coverage of application specific integrate

  5. Hybrid planar lightwave circuits for defense and aerospace applications

    Science.gov (United States)

    Zhang, Hua; Bidnyk, Serge; Yang, Shiquan; Balakrishnan, Ashok; Pearson, Matt; O'Keefe, Sean

    2010-04-01

    We present innovations in Planar Lightwave Circuits (PLCs) that make them ideally suited for use in advanced defense and aerospace applications. We discuss PLCs that contain no micro-optic components, no moving parts, pose no spark or fire hazard, are extremely small and lightweight, and are capable of transporting and processing a range of optical signals with exceptionally high performance. This PLC platform is designed for on-chip integration of active components such as lasers and detectors, along with transimpedance amplifiers and other electronics. These active components are hybridly integrated with our silica-on-silicon PLCs using fully-automated robotics and image recognition technology. This PLC approach has been successfully applied to the design and fabrication of multi-channel transceivers for aerospace applications. The chips contain hybrid DFB lasers and high-efficiency detectors, each capable of running over 10 Gb/s, with mixed digital and analog traffic multiplexed to a single optical fiber. This highlyintegrated functionality is combined onto a silicon chip smaller than 4 x 10 mm, weighing failures after extreme temperature cycling through a range of > 125 degC, and more than 2,000 hours operating at 95 degC ambient air temperature. We believe that these recent advancements in planar lightwave circuits are poised to revolutionize optical communications and interconnects in the aerospace and defense industries.

  6. Single-event effects in analog and mixed-signal integrated circuits

    International Nuclear Information System (INIS)

    Turflinger, T.L.

    1996-01-01

    Analog and mixed-signal integrated circuits are also susceptible to single-event effects, but they have rarely been tested. Analog circuit single-particle transients require modified test techniques and data analysis. Existing work is reviewed and future concerns are outlined

  7. Ultra low-power integrated circuit design for wireless neural interfaces

    CERN Document Server

    Holleman, Jeremy; Otis, Brian

    2014-01-01

    Presenting results from real prototype systems, this volume provides an overview of ultra low-power integrated circuits and systems for neural signal processing and wireless communication. Topics include analog, radio, and signal processing theory and design for ultra low-power circuits.

  8. Heterogeneous integration of lithium niobate and silicon nitride waveguides for wafer-scale photonic integrated circuits on silicon.

    Science.gov (United States)

    Chang, Lin; Pfeiffer, Martin H P; Volet, Nicolas; Zervas, Michael; Peters, Jon D; Manganelli, Costanza L; Stanton, Eric J; Li, Yifei; Kippenberg, Tobias J; Bowers, John E

    2017-02-15

    An ideal photonic integrated circuit for nonlinear photonic applications requires high optical nonlinearities and low loss. This work demonstrates a heterogeneous platform by bonding lithium niobate (LN) thin films onto a silicon nitride (Si3N4) waveguide layer on silicon. It not only provides large second- and third-order nonlinear coefficients, but also shows low propagation loss in both the Si3N4 and the LN-Si3N4 waveguides. The tapers enable low-loss-mode transitions between these two waveguides. This platform is essential for various on-chip applications, e.g., modulators, frequency conversions, and quantum communications.

  9. Hybrid integrated circuit for charge-to-time interval conversion

    Energy Technology Data Exchange (ETDEWEB)

    Basiladze, S.G.; Dotsenko, Yu.Yu.; Man' yakov, P.K.; Fedorchenko, S.N. (Joint Inst. for Nuclear Research, Dubna (USSR))

    The hybrid integrated circuit for charge-to time interval conversion with nanosecond input fast response is described. The circuit can be used in energy measuring channels, time-to-digital converters and in the modified variant in amplitude-to-digital converters. The converter described consists of a buffer amplifier, a linear transmission circuit, a direct current source and a unit of time interval separation. The buffer amplifier represents a current follower providing low input and high output resistances by the current feedback. It is concluded that the described converter excelled the QT100B circuit analogous to it in a number of parameters especially, in thermostability.

  10. A statistical-based material and process guidelines for design of carbon nanotube field-effect transistors in gigascale integrated circuits.

    Science.gov (United States)

    Ghavami, Behnam; Raji, Mohsen; Pedram, Hossein

    2011-08-26

    Carbon nanotube field-effect transistors (CNFETs) show great promise as building blocks of future integrated circuits. However, synthesizing single-walled carbon nanotubes (CNTs) with accurate chirality and exact positioning control has been widely acknowledged as an exceedingly complex task. Indeed, density and chirality variations in CNT growth can compromise the reliability of CNFET-based circuits. In this paper, we present a novel statistical compact model to estimate the failure probability of CNFETs to provide some material and process guidelines for the design of CNFETs in gigascale integrated circuits. We use measured CNT spacing distributions within the framework of detailed failure analysis to demonstrate that both the CNT density and the ratio of metallic to semiconducting CNTs play dominant roles in defining the failure probability of CNFETs. Besides, it is argued that the large-scale integration of these devices within an integrated circuit will be feasible only if a specific range of CNT density with an acceptable ratio of semiconducting to metallic CNTs can be adjusted in a typical synthesis process.

  11. Package Holds Five Monolithic Microwave Integrated Circuits

    Science.gov (United States)

    Mysoor, Narayan R.; Decker, D. Richard; Olson, Hilding M.

    1996-01-01

    Packages protect and hold monolithic microwave integrated circuit (MMIC) chips while providing dc and radio-frequency (RF) electrical connections for chips undergoing development. Required to be compact, lightweight, and rugged. Designed to minimize undesired resonances, reflections, losses, and impedance mismatches.

  12. Integration of aerial imaging and variable-rate technology for site-specific aerial herbicide application

    Science.gov (United States)

    As remote sensing and variable rate technology are becoming more available for aerial applicators, practical methodologies on effective integration of these technologies are needed for site-specific aerial applications of crop production and protection materials. The objectives of this study were to...

  13. Integrated Circuit Interconnect Lines on Lossy Silicon Substrate with Finite Element Method

    OpenAIRE

    Sarhan M. Musa,; Matthew N. O. Sadiku

    2014-01-01

    The silicon substrate has a significant effect on the inductance parameter of a lossy interconnect line on integrated circuit. It is essential to take this into account in determining the transmission line electrical parameters. In this paper, a new quasi-TEM capacitance and inductance analysis of multiconductor multilayer interconnects is successfully demonstrated using finite element method (FEM). We specifically illustrate the electrostatic modeling of single and coupled in...

  14. Microwave RF antennas and circuits nonlinearity applications in engineering

    CERN Document Server

    Aluf, Ofer

    2017-01-01

    This book describes a new concept for analyzing RF/microwave circuits, which includes RF/microwave antennas. The book is unique in its emphasis on practical and innovative microwave RF engineering applications. The analysis is based on nonlinear dynamics and chaos models and shows comprehensive benefits and results. All conceptual RF microwave circuits and antennas are innovative and can be broadly implemented in engineering applications. Given the dynamics of RF microwave circuits and antennas, they are suitable for use in a broad range of applications. The book presents analytical methods for microwave RF antennas and circuit analysis, concrete examples, and geometric examples. The analysis is developed systematically, starting with basic differential equations and their bifurcations, and subsequently moving on to fixed point analysis, limit cycles and their bifurcations. Engineering applications include microwave RF circuits and antennas in a variety of topological structures, RFID ICs and antennas, micros...

  15. Lithographic technology for microwave integrated circuits

    OpenAIRE

    Shepherd, PR; Evans, PSA; Ramsey, BJ; Harrison, DJ

    1997-01-01

    Conductive lithographic films (CLFs) have been developed primarily as substitutes for resin/laminate boards, which share properties with the metallisation patterns used in planar microwave integrated circuits (MICs). The authors examine the microwave properties of the films and show that, although the losses are greater, they have potential as an alternative to the traditional manufacturing process of MICs.

  16. Performance of digital integrated circuit technologies at very high temperatures

    Energy Technology Data Exchange (ETDEWEB)

    Prince, J.L.; Draper, B.L.; Rapp, E.A.; Kromberg, J.N.; Fitch, L.T.

    1980-01-01

    Results of investigations of the performance and reliability of digital bipolar and CMOS integrated circuits over the 25 to 340/sup 0/C range are reported. Included in these results are both parametric variation information and analysis of the functional failure mechanisms. Although most of the work was done using commercially available circuits (TTL and CMOS) and test chips from commercially compatible processes, some results of experimental simulations of dielectrically isolated CMOS are also discussed. It was found that commercial Schottky clamped TTL, and dielectrically isolated, low power Schottky-clamped TTL, functioned to junction temperatures in excess of 325/sup 0/C. Standard gold doped TTL functioned only to 250/sup 0/C, while commercial, isolated I/sup 2/L functioned to the range 250/sup 0/C to 275/sup 0/C. Commercial junction isolated CMOS, buffered and unbuffered, functioned to the range 280/sup 0/C to 310/sup 0/C/sup +/, depending on the manufacturer. Experimental simulations of simple dielectrically isolated CMOS integrated circuits, fabricated with heavier doping levels than normal, functioned to temperatures in excess of 340/sup 0/C. High temperature life testing of experimental, silicone-encapsulated simple TTL and CMOS integrated circuits have shown no obvious life limiting problems to date. No barrier to reliable functionality of TTL bipolar or CMOS integrated ciruits at temperatures in excess of 300/sup 0/C has been found.

  17. FDTD-SPICE for Characterizing Metamaterials Integrated with Electronic Circuits

    Directory of Open Access Journals (Sweden)

    Zhengwei Hao

    2012-01-01

    Full Text Available A powerful time-domain FDTD-SPICE simulator is implemented and applied to the broadband analysis of metamaterials integrated with active and tunable circuit elements. First, the FDTD-SPICE modeling theory is studied and details of interprocess communication and hybridization of the two techniques are discussed. To verify the model, some simple cases are simulated with results in both time domain and frequency domain. Then, simulation of a metamaterial structure constructed from periodic resonant loops integrated with lumped capacitor elements is studied, which demonstrates tuning resonance frequency of medium by changing the capacitance of the integrated elements. To increase the bandwidth of the metamaterial, non-Foster transistor configurations are integrated with the loops and FDTD-SPICE is applied to successfully bridge the physics of electromagnetic and circuit topologies and to model the whole composite structure. Our model is also applied to the design and simulation of a metasurface integrated with nonlinear varactors featuring tunable reflection phase characteristic.

  18. Accurate Electromagnetic Modeling Methods for Integrated Circuits

    NARCIS (Netherlands)

    Sheng, Z.

    2010-01-01

    The present development of modern integrated circuits (IC’s) is characterized by a number of critical factors that make their design and verification considerably more difficult than before. This dissertation addresses the important questions of modeling all electromagnetic behavior of features on

  19. Electron commutator on integrated circuits

    International Nuclear Information System (INIS)

    Demidenko, V.V.

    1975-01-01

    The scheme and the parameters of an electron 16-channel contactless commutator based entirely on integrated circuits are described. The device consists of a unit of analog keys based on field-controlled metal-insulator-semiconductor (m.i.s.) transistors, operation amplifier comparators controlling these keys, and a level distributor. The distributor is based on a ''matrix'' scheme and comprises two ring-shaped shift registers plugged in series and a decoder base on two-input logical elements I-NE. The principal dynamical parameters of the circuit are as follows: the control signal delay in the distributor. 50 nsec; the total channel switch-over time, 500-600 nsec. The commutator transmits both constant signals and pulses whose duration reaches tens of nsec. The commutator can be used in data acquisition and processing systems, for shaping complicated signals (for example), (otherwise signals), for simultaneous oscillographing of several signals, and so forth [ru

  20. Integrated circuit cell library

    Science.gov (United States)

    Whitaker, Sterling R. (Inventor); Miles, Lowell H. (Inventor)

    2005-01-01

    According to the invention, an ASIC cell library for use in creation of custom integrated circuits is disclosed. The ASIC cell library includes some first cells and some second cells. Each of the second cells includes two or more kernel cells. The ASIC cell library is at least 5% comprised of second cells. In various embodiments, the ASIC cell library could be 10% or more, 20% or more, 30% or more, 40% or more, 50% or more, 60% or more, 70% or more, 80% or more, 90% or more, or 95% or more comprised of second cells.

  1. A programmable delay unit incorporating a semi-custom integrated circuit

    International Nuclear Information System (INIS)

    Linstadt, E.

    1985-01-01

    The synchronization of SLC accelerator control and monitoring functions is realized by a CAMAC module, the PDU II (Programmable Delay Unit II, SLAC 253-002), which includes a semi-custom gate array integrated circuit. The PDU II distributes 16 channels of independently programmable delayed pulses to other modules within the same CAMAC crate. The delays are programmable in increments of 8.4 ns. Functional descriptions of both the module and the semi-custom integrated circuit used to generate the output pulses are given

  2. High-performance packaging for monolithic microwave and millimeter-wave integrated circuits

    Science.gov (United States)

    Shalkhauser, K. A.; Li, K.; Shih, Y. C.

    1992-01-01

    Packaging schemes are developed that provide low-loss, hermetic enclosure for enhanced monolithic microwave and millimeter-wave integrated circuits. These package schemes are based on a fused quartz substrate material offering improved RF performance through 44 GHz. The small size and weight of the packages make them useful for a number of applications, including phased array antenna systems. As part of the packaging effort, a test fixture was developed to interface the single chip packages to conventional laboratory instrumentation for characterization of the packaged devices.

  3. Integrated Circuits in the Introductory Electronics Laboratory

    Science.gov (United States)

    English, Thomas C.; Lind, David A.

    1973-01-01

    Discusses the use of an integrated circuit operational amplifier in an introductory electronics laboratory course for undergraduate science majors. The advantages of this approach and the implications for scientific instrumentation are identified. Describes a number of experiments suitable for the undergraduate laboratory. (Author/DF)

  4. An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

    Science.gov (United States)

    Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

    2017-07-01

    This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

  5. 76 FR 41521 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2011-07-14

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-786] In the Matter of Certain Integrated Circuits... sale within the United States after importation of certain integrated circuits, chipsets, and products... after importation of certain integrated circuits, chipsets, and products containing same including...

  6. 75 FR 5804 - In the Matter of: Certain Semiconductor Integrated Circuits and Products Containing Same; Notice...

    Science.gov (United States)

    2010-02-04

    ... Semiconductor Integrated Circuits and Products Containing Same; Notice of Commission Determination To Review in... importation of certain semiconductor integrated circuits and products containing same by reason of... (collectively ``Seagate''). Qimonda accuses of infringement certain LSI integrated circuits, as well as certain...

  7. 77 FR 35426 - Certain Radio Frequency Integrated Circuits and Devices Containing Same; Institution of...

    Science.gov (United States)

    2012-06-13

    ... of certain radio frequency integrated circuits and devices containing same by reason of infringement... importation of certain radio frequency integrated circuits and devices containing same that infringe one or... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-848] Certain Radio Frequency Integrated...

  8. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit

    Directory of Open Access Journals (Sweden)

    Lisa eMapelli

    2015-05-01

    Full Text Available The way long-term potentiation (LTP and depression (LTD are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network , in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei and correspondingly regulate the function of their three main neurons: granule cells (GrCs, Purkinje cells (PCs and deep cerebellar nuclear (DCN cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  9. Integrated plasticity at inhibitory and excitatory synapses in the cerebellar circuit.

    Science.gov (United States)

    Mapelli, Lisa; Pagani, Martina; Garrido, Jesus A; D'Angelo, Egidio

    2015-01-01

    The way long-term potentiation (LTP) and depression (LTD) are integrated within the different synapses of brain neuronal circuits is poorly understood. In order to progress beyond the identification of specific molecular mechanisms, a system in which multiple forms of plasticity can be correlated with large-scale neural processing is required. In this paper we take as an example the cerebellar network, in which extensive investigations have revealed LTP and LTD at several excitatory and inhibitory synapses. Cerebellar LTP and LTD occur in all three main cerebellar subcircuits (granular layer, molecular layer, deep cerebellar nuclei) and correspondingly regulate the function of their three main neurons: granule cells (GrCs), Purkinje cells (PCs) and deep cerebellar nuclear (DCN) cells. All these neurons, in addition to be excited, are reached by feed-forward and feed-back inhibitory connections, in which LTP and LTD may either operate synergistically or homeostatically in order to control information flow through the circuit. Although the investigation of individual synaptic plasticities in vitro is essential to prove their existence and mechanisms, it is insufficient to generate a coherent view of their impact on network functioning in vivo. Recent computational models and cell-specific genetic mutations in mice are shedding light on how plasticity at multiple excitatory and inhibitory synapses might regulate neuronal activities in the cerebellar circuit and contribute to learning and memory and behavioral control.

  10. Integrated biocircuits: engineering functional multicellular circuits and devices

    Science.gov (United States)

    Prox, Jordan; Smith, Tory; Holl, Chad; Chehade, Nick; Guo, Liang

    2018-04-01

    Objective. Implantable neurotechnologies have revolutionized neuromodulatory medicine for treating the dysfunction of diseased neural circuitry. However, challenges with biocompatibility and lack of full control over neural network communication and function limits the potential to create more stable and robust neuromodulation devices. Thus, we propose a platform technology of implantable and programmable cellular systems, namely Integrated Biocircuits, which use only cells as the functional components of the device. Approach. We envision the foundational principles for this concept begins with novel in vitro platforms used for the study and reconstruction of cellular circuitry. Additionally, recent advancements in organoid and 3D culture systems account for microenvironment factors of cytoarchitecture to construct multicellular circuits as they are normally formed in the brain. We explore the current state of the art of these platforms to provide knowledge of their advancements in circuit fabrication and identify the current biological principles that could be applied in designing integrated biocircuit devices. Main results. We have highlighted the exemplary methodologies and techniques of in vitro circuit fabrication and propose the integration of selected controllable parameters, which would be required in creating suitable biodevices. Significance. We provide our perspective and propose new insights into the future of neuromodulaion devices within the scope of living cellular systems that can be applied in designing more reliable and biocompatible stimulation-based neuroprosthetics.

  11. Flexible, High-Speed CdSe Nanocrystal Integrated Circuits.

    Science.gov (United States)

    Stinner, F Scott; Lai, Yuming; Straus, Daniel B; Diroll, Benjamin T; Kim, David K; Murray, Christopher B; Kagan, Cherie R

    2015-10-14

    We report large-area, flexible, high-speed analog and digital colloidal CdSe nanocrystal integrated circuits operating at low voltages. Using photolithography and a newly developed process to fabricate vertical interconnect access holes, we scale down device dimensions, reducing parasitic capacitances and increasing the frequency of circuit operation, and scale up device fabrication over 4 in. flexible substrates. We demonstrate amplifiers with ∼7 kHz bandwidth, ring oscillators with <10 μs stage delays, and NAND and NOR logic gates.

  12. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    Science.gov (United States)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    1984-01-01

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  13. Monolithic microwave integrated circuits: Interconnections and packaging considerations

    Science.gov (United States)

    Bhasin, K. B.; Downey, A. N.; Ponchak, G. E.; Romanofsky, R. R.; Anzic, G.; Connolly, D. J.

    Monolithic microwave integrated circuits (MMIC's) above 18 GHz were developed because of important potential system benefits in cost reliability, reproducibility, and control of circuit parameters. The importance of interconnection and packaging techniques that do not compromise these MMIC virtues is emphasized. Currently available microwave transmission media are evaluated to determine their suitability for MMIC interconnections. An antipodal finline type of microstrip waveguide transition's performance is presented. Packaging requirements for MMIC's are discussed for thermal, mechanical, and electrical parameters for optimum desired performance.

  14. 75 FR 16837 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2010-04-02

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-709] In the Matter of Certain Integrated Circuits... importation of certain integrated circuits, chipsets, and products containing same including televisions... importation, or the sale within the United States after importation of certain integrated circuits, chipsets...

  15. Processing and Characterization of Thousand-Hour 500 C Durable 4H-SiC JFET Integrated Circuits

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Chen, Liangyu; Lukco, Dorothy; Chang, Carl W.; Beheim, Glenn M.; Krasowski, Michael J.; Prokop, Norman F.

    2016-01-01

    This work reports fabrication and testing of integrated circuits (ICs) with two levels of interconnect that consistently achieve greater than 1000 hours of stable electrical operation at 500 C in air ambient. These ICs are based on 4H-SiC junction field effect transistor (JFET) technology that integrates hafnium ohmic contacts with TaSi2 interconnects and SiO2 and Si3N4 dielectric layers over 1-m scale vertical topology. Following initial burn-in, important circuit parameters remain stable for more than 1000 hours of 500 C operational testing. These results advance the technology foundation for realizing long-term durable 500 C ICs with increased functional capability for sensing and control combustion engine, planetary, deep-well drilling, and other harsh-environment applications.

  16. Monolithic integration of micromachined sensors and CMOS circuits based on SOI technologies

    International Nuclear Information System (INIS)

    Yu Xiaomei; Tang Yaquan; Zhang Haitao

    2008-01-01

    This note presents a novel way to monolithically integrate micro-cantilever sensors and signal conditioning circuits by combining SOI CMOS and SOI micromachining technologies. In order to improve the sensor performance and reduce the system volume, an integrated sensor system composed of a piezoresistive cantilever array, a temperature-compensation current reference, a digitally controlled multiplexer and an instrument amplifier is designed and finally fabricated. A post-SOI CMOS process is developed to realize the integrated sensor system which is based on a standard CMOS process with one more mask to define the cantilever structure at the end of the process. Measurements on the finished SOI CMOS devices and circuits show that the integration process has good compatibility both for the cantilever sensors and for the CMOS circuits, and the SOI CMOS integration process can decrease about 25% sequences compared with the bulk silicon CMOS process. (note)

  17. Microcontroller based Integrated Circuit Tester

    OpenAIRE

    Yousif Taha Yousif Elamin; Abdelrasoul Jabar Alzubaidi

    2015-01-01

    The digital integrated circuit (IC) tester is implemented by using the ATmega32 microcontroller . The microcontroller processes the inputs and outputs and displays the results on a Liquid Crystal Display (LCD). The basic function of the digital IC tester is to test a digital IC for correct logical functioning as described in the truth table and/or function table. The designed model can test digital ICs having 14 pins. Since it is programmable, any number of ICs can be tested . Thi...

  18. Status of readout integrated circuits for radiation detector

    International Nuclear Information System (INIS)

    Moon, B. S.; Hong, S. B.; Cheng, J. E. and others

    2001-09-01

    In this report, we describe the current status of readout integrated circuits developed for radiation detectors, along with new technologies being applied to this field. The current status of ASCIC chip development related to the readout electronics is also included in this report. Major sources of this report are from product catalogs and web sites of the related industries. In the field of semiconductor process technology in Korea, the current status of the multi-project wafer(MPW) of IDEC, the multi-project chip(MPC) of ISRC and other domestic semiconductor process industries is described. In the case of other countries, the status of the MPW of MOSIS in USA and the MPW of EUROPRACTICE in Europe is studied. This report also describes the technologies and products of readout integrated circuits of industries worldwide

  19. Integrated reconfigurable high-voltage transmitting circuit for CMUTs

    DEFF Research Database (Denmark)

    Llimos Muntal, Pere; Larsen, Dennis Øland; Jørgensen, Ivan Harald Holger

    2015-01-01

    In this paper a high-voltage transmitting circuit aimed for capacitive micromachined ultrasonic transducers (CMUTs) used in scanners for medical applications is designed and implemented in a 0.35 μm high-voltage CMOS process. The transmitting circuit is reconfigurable externally making it able...... to drive a wide variety of CMUTs. The transmitting circuit can generate several pulse shapes with voltages up to 100 V, maximum pulse range of 50 V, frequencies up to 5 MHz and different driving slew rates. Measurements are performed on the circuit in order to assess its functionality and power consumption...... performance. The design occupies an on-chip area of 0.938 mm2 and the power consumption of a 128-element transmitting circuit array that would be used in an portable ultrasound scanner is found to be a maximum of 181 mW....

  20. Foundry fabricated photonic integrated circuit optical phase lock loop.

    Science.gov (United States)

    Bałakier, Katarzyna; Fice, Martyn J; Ponnampalam, Lalitha; Graham, Chris S; Wonfor, Adrian; Seeds, Alwyn J; Renaud, Cyril C

    2017-07-24

    This paper describes the first foundry-based InP photonic integrated circuit (PIC) designed to work within a heterodyne optical phase locked loop (OPLL). The PIC and an external electronic circuit were used to phase-lock a single-line semiconductor laser diode to an incoming reference laser, with tuneable frequency offset from 4 GHz to 12 GHz. The PIC contains 33 active and passive components monolithically integrated on a single chip, fully demonstrating the capability of a generic foundry PIC fabrication model. The electronic part of the OPLL consists of commercially available RF components. This semi-packaged system stabilizes the phase and frequency of the integrated laser so that an absolute frequency, high-purity heterodyne signal can be generated when the OPLL is in operation, with phase noise lower than -100 dBc/Hz at 10 kHz offset from the carrier. This is the lowest phase noise level ever demonstrated by monolithically integrated OPLLs.

  1. Highly localized distributed Brillouin scattering response in a photonic integrated circuit

    Science.gov (United States)

    Zarifi, Atiyeh; Stiller, Birgit; Merklein, Moritz; Li, Neuton; Vu, Khu; Choi, Duk-Yong; Ma, Pan; Madden, Stephen J.; Eggleton, Benjamin J.

    2018-03-01

    The interaction of optical and acoustic waves via stimulated Brillouin scattering (SBS) has recently reached on-chip platforms, which has opened new fields of applications ranging from integrated microwave photonics and on-chip narrow-linewidth lasers, to phonon-based optical delay and signal processing schemes. Since SBS is an effect that scales exponentially with interaction length, on-chip implementation on a short length scale is challenging, requiring carefully designed waveguides with optimized opto-acoustic overlap. In this work, we use the principle of Brillouin optical correlation domain analysis to locally measure the SBS spectrum with high spatial resolution of 800 μm and perform a distributed measurement of the Brillouin spectrum along a spiral waveguide in a photonic integrated circuit. This approach gives access to local opto-acoustic properties of the waveguides, including the Brillouin frequency shift and linewidth, essential information for the further development of high quality photonic-phononic waveguides for SBS applications.

  2. Highly localized distributed Brillouin scattering response in a photonic integrated circuit

    Directory of Open Access Journals (Sweden)

    Atiyeh Zarifi

    2018-03-01

    Full Text Available The interaction of optical and acoustic waves via stimulated Brillouin scattering (SBS has recently reached on-chip platforms, which has opened new fields of applications ranging from integrated microwave photonics and on-chip narrow-linewidth lasers, to phonon-based optical delay and signal processing schemes. Since SBS is an effect that scales exponentially with interaction length, on-chip implementation on a short length scale is challenging, requiring carefully designed waveguides with optimized opto-acoustic overlap. In this work, we use the principle of Brillouin optical correlation domain analysis to locally measure the SBS spectrum with high spatial resolution of 800 μm and perform a distributed measurement of the Brillouin spectrum along a spiral waveguide in a photonic integrated circuit. This approach gives access to local opto-acoustic properties of the waveguides, including the Brillouin frequency shift and linewidth, essential information for the further development of high quality photonic-phononic waveguides for SBS applications.

  3. Data readout system utilizing photonic integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Stopiński, S., E-mail: S.Stopinski@tue.nl [COBRA Research Institute, Eindhoven University of Technology (Netherlands); Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Malinowski, M.; Piramidowicz, R. [Institute of Microelectronics and Optoelectronics, Warsaw University of Technology (Poland); Smit, M.K.; Leijtens, X.J.M. [COBRA Research Institute, Eindhoven University of Technology (Netherlands)

    2013-10-11

    We describe a novel optical solution for data readout systems. The core of the system is an Indium-Phosphide photonic integrated circuit performing as a front-end readout unit. It functions as an optical serializer in which the serialization of the input signal is provided by means of on-chip optical delay lines. The circuit employs electro-optic phase shifters to build amplitude modulators, power splitters for signal distribution, semiconductor optical amplifiers for signal amplification as well as on-chip reflectors. We present the concept of the system, the design and first characterization results of the devices that were fabricated in a multi-project wafer run.

  4. High-frequency analog integrated circuit design

    CERN Document Server

    1995-01-01

    To learn more about designing analog integrated circuits (ICs) at microwave frequencies using GaAs materials, turn to this text and reference. It addresses GaAs MESFET-based IC processing. Describes the newfound ability to apply silicon analog design techniques to reliable GaAs materials and devices which, until now, was only available through technical papers scattered throughout hundred of articles in dozens of professional journals.

  5. Viewing Integrated-Circuit Interconnections By SEM

    Science.gov (United States)

    Lawton, Russel A.; Gauldin, Robert E.; Ruiz, Ronald P.

    1990-01-01

    Back-scattering of energetic electrons reveals hidden metal layers. Experiment shows that with suitable operating adjustments, scanning electron microscopy (SEM) used to look for defects in aluminum interconnections in integrated circuits. Enables monitoring, in situ, of changes in defects caused by changes in temperature. Gives truer picture of defects, as etching can change stress field of metal-and-passivation pattern, causing changes in defects.

  6. Programmable dispersion on a photonic integrated circuit for classical and quantum applications.

    Science.gov (United States)

    Notaros, Jelena; Mower, Jacob; Heuck, Mikkel; Lupo, Cosmo; Harris, Nicholas C; Steinbrecher, Gregory R; Bunandar, Darius; Baehr-Jones, Tom; Hochberg, Michael; Lloyd, Seth; Englund, Dirk

    2017-09-04

    We demonstrate a large-scale tunable-coupling ring resonator array, suitable for high-dimensional classical and quantum transforms, in a CMOS-compatible silicon photonics platform. The device consists of a waveguide coupled to 15 ring-based dispersive elements with programmable linewidths and resonance frequencies. The ability to control both quality factor and frequency of each ring provides an unprecedented 30 degrees of freedom in dispersion control on a single spatial channel. This programmable dispersion control system has a range of applications, including mode-locked lasers, quantum key distribution, and photon-pair generation. We also propose a novel application enabled by this circuit - high-speed quantum communications using temporal-mode-based quantum data locking - and discuss the utility of the system for performing the high-dimensional unitary optical transformations necessary for a quantum data locking demonstration.

  7. Toolbox for the design of LiNbO3-based passive and active integrated quantum circuits

    Science.gov (United States)

    Sharapova, P. R.; Luo, K. H.; Herrmann, H.; Reichelt, M.; Meier, T.; Silberhorn, C.

    2017-12-01

    We present and discuss perspectives of current developments on advanced quantum optical circuits monolithically integrated in the lithium niobate platform. A set of basic components comprising photon pair sources based on parametric down conversion (PDC), passive routing elements and active electro-optically controllable switches and polarisation converters are building blocks of a toolbox which is the basis for a broad range of diverse quantum circuits. We review the state-of-the-art of these components and provide models that properly describe their performance in quantum circuits. As an example for applications of these models we discuss design issues for a circuit providing on-chip two-photon interference. The circuit comprises a PDC section for photon pair generation followed by an actively controllable modified mach-Zehnder structure for observing Hong-Ou-Mandel interference. The performance of such a chip is simulated theoretically by taking even imperfections of the properties of the individual components into account.

  8. Integration of Descending Command Systems for the Generation of Context-Specific Locomotor Behaviors

    Directory of Open Access Journals (Sweden)

    Linda H. Kim

    2017-10-01

    Full Text Available Over the past decade there has been a renaissance in our understanding of spinal cord circuits; new technologies are beginning to provide key insights into descending circuits which project onto spinal cord central pattern generators. By integrating work from both the locomotor and animal behavioral fields, we can now examine context-specific control of locomotion, with an emphasis on descending modulation arising from various regions of the brainstem. Here we examine approach and avoidance behaviors and the circuits that lead to the production and arrest of locomotion.

  9. Multi-Objective Optimization in Physical Synthesis of Integrated Circuits

    CERN Document Server

    A Papa, David

    2013-01-01

    This book introduces techniques that advance the capabilities and strength of modern software tools for physical synthesis, with the ultimate goal to improve the quality of leading-edge semiconductor products.  It provides a comprehensive introduction to physical synthesis and takes the reader methodically from first principles through state-of-the-art optimizations used in cutting edge industrial tools. It explains how to integrate chip optimizations in novel ways to create powerful circuit transformations that help satisfy performance requirements. Broadens the scope of physical synthesis optimization to include accurate transformations operating between the global and local scales; Integrates groups of related transformations to break circular dependencies and increase the number of circuit elements that can be jointly optimized to escape local minima;  Derives several multi-objective optimizations from first observations through complete algorithms and experiments; Describes integrated optimization te...

  10. Analysis of the capability to effectively design complementary metal oxide semiconductor integrated circuits

    Science.gov (United States)

    McConkey, M. L.

    1984-12-01

    A complete CMOS/BULK design cycle has been implemented and fully tested to evaluate its effectiveness and a viable set of computer-aided design tools for the layout, verification, and simulation of CMOS/BULK integrated circuits. This design cycle is good for p-well, n-well, or twin-well structures, although current fabrication technique available limit this to p-well only. BANE, an integrated layout program from Stanford, is at the center of this design cycle and was shown to be simple to use in the layout of CMOS integrated circuits (it can be also used to layout NMOS integrated circuits). A flowchart was developed showing the design cycle from initial layout, through design verification, and to circuit simulation using NETLIST, PRESIM, and RNL from the University of Washington. A CMOS/BULK library was designed and includes logic gates that were designed and completely tested by following this flowchart. Also designed was an arithmetic logic unit as a more complex test of the CMOS/BULK design cycle.

  11. Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications.

    Science.gov (United States)

    Vidor, Fábio F; Meyers, Thorsten; Hilleringmann, Ulrich

    2016-08-23

    Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs) are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high- k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the I ON / I OFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V / V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

  12. Inverter Circuits Using ZnO Nanoparticle Based Thin-Film Transistors for Flexible Electronic Applications

    Directory of Open Access Journals (Sweden)

    Fábio F. Vidor

    2016-08-01

    Full Text Available Innovative systems exploring the flexibility and the transparency of modern semiconducting materials are being widely researched by the scientific community and by several companies. For a low-cost production and large surface area applications, thin-film transistors (TFTs are the key elements driving the system currents. In order to maintain a cost efficient integration process, solution based materials are used as they show an outstanding tradeoff between cost and system complexity. In this paper, we discuss the integration process of ZnO nanoparticle TFTs using a high-k resin as gate dielectric. The performance in dependence on the transistor structure has been investigated, and inverted staggered setups depict an improved performance over the coplanar device increasing both the field-effect mobility and the ION/IOFF ratio. Aiming at the evaluation of the TFT characteristics for digital circuit applications, inverter circuits using a load TFT in the pull-up network and an active TFT in the pull-down network were integrated. The inverters show reasonable switching characteristics and V/V gains. Conjointly, the influence of the geometry ratio and the supply voltage on the devices have been analyzed. Moreover, as all integration steps are suitable to polymeric templates, the fabrication process is fully compatible to flexible substrates.

  13. Method and apparatus for in-system redundant array repair on integrated circuits

    Science.gov (United States)

    Bright, Arthur A.; Crumley, Paul G.; Dombrowa, Marc B.; Douskey, Steven M.; Haring, Rudolf A.; Oakland, Steven F.; Ouellette, Michael R.; Strissel, Scott A.

    2007-12-18

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  14. Method and apparatus for in-system redundant array repair on integrated circuits

    Science.gov (United States)

    Bright, Arthur A [Croton-on-Hudson, NY; Crumley, Paul G [Yorktown Heights, NY; Dombrowa, Marc B [Bronx, NY; Douskey, Steven M [Rochester, MN; Haring, Rudolf A [Cortlandt Manor, NY; Oakland, Steven F [Colchester, VT; Ouellette, Michael R [Westford, VT; Strissel, Scott A [Byron, MN

    2008-07-29

    Disclosed is a method of repairing an integrated circuit of the type comprising of a multitude of memory arrays and a fuse box holding control data for controlling redundancy logic of the arrays. The method comprises the steps of providing the integrated circuit with a control data selector for passing the control data from the fuse box to the memory arrays; providing a source of alternate control data, external of the integrated circuit; and connecting the source of alternate control data to the control data selector. The method comprises the further step of, at a given time, passing the alternate control data from the source thereof, through the control data selector and to the memory arrays to control the redundancy logic of the memory arrays.

  15. Back End of Line Nanorelays for Ultra-low Power Monolithic Integrated NEMS-CMOS Circuits

    KAUST Repository

    Lechuga Aranda, Jesus Javier

    2016-05-01

    Since the introduction of Complementary-Metal-Oxide-Semiconductor (CMOS) technology, the chip industry has enjoyed many benefits of transistor feature size scaling, including higher speed and device density and improved energy efficiency. However, in the recent years, the IC designers have encountered a few roadblocks, namely reaching the physical limits of scaling and also increased device leakage which has resulted in a slow-down of supply voltage and power density scaling. Therefore, there has been an extensive hunt for alternative circuit architectures and switching devices that can alleviate or eliminate the current crisis in the semiconductor industry. The Nano-Electro-Mechanical (NEM) relay is a promising alternative switch that offers zero leakage and abrupt turn-on behaviour. Even though these devices are intrinsically slower than CMOS transistors, new circuit design techniques tailored for the electromechanical properties of such devices can be leveraged to design medium performance, ultra-low power integrated circuits. In this thesis, we deal with a new generation of such devices that is built in the back end of line (BEOL) CMOS process and is an ideal option for full integration with current CMOS transistor technology. Simulation and verification at the circuit and system level is a critical step in the design flow of microelectronic circuits, and this is especially important for new technologies that lack the standard design infrastructure and well-known verification platforms. Although most of the physical and electrical properties of NEM structures can be simulated using standard electronic automation software, there is no report of a reliable behavioural model for NEMS switches that enable large circuit simulations. In this work, we present an optimised model of a BEOL nano relay that encompasses all the electromechanical characteristics of the device and is robust and lightweight enough for VLSI applications that require simulation of thousands of

  16. Wireless transceiver circuits system perspectives and design aspects

    CERN Document Server

    Rhee, Woogeun

    2015-01-01

    This cutting-edge work contains comprehensive coverage of integrated circuit (IC) design for modern transceiver circuits and wireless systems. Ranging in scope from system perspectives to practical circuit design for emerging wireless applications, the book includes detailed discussions of transceiver architectures and system parameters, mm-wave circuits, ultra-low-power radios for biomedical and sensor applications, and the latest circuit techniques. Written by renowned international experts in IC industry and academia, the text is an ideal reference for engineers and researchers in the area

  17. AMIC: an expandable integrated analog front-end for light distribution moments analysis

    OpenAIRE

    SPAGGIARI, MICHELE; Herrero Bosch, Vicente; Lerche, Christoph Werner; Aliaga Varea, Ramón José; Monzó Ferrer, José María; Gadea Gironés, Rafael

    2011-01-01

    In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a cop...

  18. Transient-induced latchup in CMOS integrated circuits

    CERN Document Server

    Ker, Ming-Dou

    2009-01-01

    "Transient-Induced Latchup in CMOS Integrated Circuits equips the practicing engineer with all the tools needed to address this regularly occurring problem while becoming more proficient at IC layout. Ker and Hsu introduce the phenomenon and basic physical mechanism of latchup, explaining the critical issues that have resurfaced for CMOS technologies. Once readers can gain an understanding of the standard practices for TLU, Ker and Hsu discuss the physical mechanism of TLU under a system-level ESD test, while introducing an efficient component-level TLU measurement setup. The authors then present experimental methodologies to extract safe and area-efficient compact layout rules for latchup prevention, including layout rules for I/O cells, internal circuits, and between I/O and internal circuits. The book concludes with an appendix giving a practical example of extracting layout rules and guidelines for latchup prevention in a 0.18-micrometer 1.8V/3.3V silicided CMOS process."--Publisher's description.

  19. Sub-10 nm colloidal lithography for circuit-integrated spin-photo-electronic devices

    Directory of Open Access Journals (Sweden)

    Adrian Iovan

    2012-12-01

    Full Text Available Patterning of materials at sub-10 nm dimensions is at the forefront of nanotechnology and employs techniques of various complexity, efficiency, areal scale, and cost. Colloid-based patterning is known to be capable of producing individual sub-10 nm objects. However, ordered, large-area nano-arrays, fully integrated into photonic or electronic devices have remained a challenging task. In this work, we extend the practice of colloidal lithography to producing large-area sub-10 nm point-contact arrays and demonstrate their circuit integration into spin-photo-electronic devices. The reported nanofabrication method should have broad application areas in nanotechnology as it allows ballistic-injection devices, even for metallic materials with relatively short characteristic relaxation lengths.

  20. Silicon photonics integrated circuits: a manufacturing platform for high density, low power optical I/O's.

    Science.gov (United States)

    Absil, Philippe P; Verheyen, Peter; De Heyn, Peter; Pantouvaki, Marianna; Lepage, Guy; De Coster, Jeroen; Van Campenhout, Joris

    2015-04-06

    Silicon photonics integrated circuits are considered to enable future computing systems with optical input-outputs co-packaged with CMOS chips to circumvent the limitations of electrical interfaces. In this paper we present the recent progress made to enable dense multiplexing by exploiting the integration advantage of silicon photonics integrated circuits. We also discuss the manufacturability of such circuits, a key factor for a wide adoption of this technology.

  1. Amorphous Zinc Oxide Integrated Wavy Channel Thin Film Transistor Based High Performance Digital Circuits

    KAUST Repository

    Hanna, Amir

    2015-12-04

    High performance thin film transistor (TFT) can be a great driving force for display, sensor/actuator, integrated electronics, and distributed computation for Internet of Everything applications. While semiconducting oxides like zinc oxide (ZnO) present promising opportunity in that regard, still wide area of improvement exists to increase the performance further. Here, we show a wavy channel (WC) architecture for ZnO integrated TFT which increases transistor width without chip area penalty, enabling high performance in material agnostic way. We further demonstrate digital logic NAND circuit using the WC architecture and compare it to the conventional planar architecture. The WC architecture circuits have shown 2× higher peak-to-peak output voltage for the same input voltage. They also have 3× lower high-to-low propagation delay times, respectively, when compared to the planar architecture. The performance enhancement is attributed to both extra device width and enhanced field effect mobility due to higher gate field electrostatics control.

  2. Vacuum die attach for integrated circuits

    Science.gov (United States)

    Schmitt, E.H.; Tuckerman, D.B.

    1991-09-10

    A thin film eutectic bond for attaching an integrated circuit die to a circuit substrate is formed by coating at least one bonding surface on the die and substrate with an alloying metal, assembling the die and substrate under compression loading, and heating the assembly to an alloying temperature in a vacuum. A very thin bond, 10 microns or less, which is substantially void free, is produced. These bonds have high reliability, good heat and electrical conduction, and high temperature tolerance. The bonds are formed in a vacuum chamber, using a positioning and loading fixture to compression load the die, and an IR lamp or other heat source. For bonding a silicon die to a silicon substrate, a gold silicon alloy bond is used. Multiple dies can be bonded simultaneously. No scrubbing is required. 1 figure.

  3. Integrated neuron circuit for implementing neuromorphic system with synaptic device

    Science.gov (United States)

    Lee, Jeong-Jun; Park, Jungjin; Kwon, Min-Woo; Hwang, Sungmin; Kim, Hyungjin; Park, Byung-Gook

    2018-02-01

    In this paper, we propose and fabricate Integrate & Fire neuron circuit for implementing neuromorphic system. Overall operation of the circuit is verified by measuring discrete devices and the output characteristics of the circuit. Since the neuron circuit shows asymmetric output characteristic that can drive synaptic device with Spike-Timing-Dependent-Plasticity (STDP) characteristic, the autonomous weight update process is also verified by connecting the synaptic device and the neuron circuit. The timing difference of the pre-neuron and the post-neuron induce autonomous weight change of the synaptic device. Unlike 2-terminal devices, which is frequently used to implement neuromorphic system, proposed scheme of the system enables autonomous weight update and simple configuration by using 4-terminal synapse device and appropriate neuron circuit. Weight update process in the multi-layer neuron-synapse connection ensures implementation of the hardware-based artificial intelligence, based on Spiking-Neural- Network (SNN).

  4. Integrated all optical transmodulator circuits with non-linear gain elements and tunable optical fibers

    NARCIS (Netherlands)

    Kuindersma, P.I.; Leijtens, X.J.M.; Zantvoort, van J.H.C.; Waardt, de H.

    2012-01-01

    We characterize integrated InP circuits for high speed ‘all-optical’ signal processing. Single chip circuits act as optical transistors. Transmodulation is performed by non-linear gain sections. Integrated tunable filters give signal equalization in time domain.

  5. Gallium arsenide digital integrated circuits for controlling SLAC CW-RF systems

    International Nuclear Information System (INIS)

    Ronan, M.T.; Lee, K.L.; Corredoura, P.; Judkins, J.G.

    1989-01-01

    In order to fill the PEP and SPEAR storage rings with beams from the SLC linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Recently several companies have developed resettable GaAs master/slave D-type flip-flops which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase shift the SLAC CW-RF systems to optimize the timing for filling the storage rings. The authors have evaluated the performance of integrated circuits from two vendors for our particular application. Using microstrip circuit techniques, they have built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856 GHz RF and to phase shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350 psec bucket required for filling

  6. Gallium arsenide digital integrated circuits for controlling SLAC CW-RF systems

    International Nuclear Information System (INIS)

    Ronan, M.T.; Lee, K.L.; Corredoura, P.; Judkins, J.G.

    1988-10-01

    In order to fill the PEP and SPEAR storage rings with beams from the SLC linac and damping rings, precise control of the linac subharmonic buncher and the damping ring RF is required. Recently several companies have developed resettable GaAs master/slave D-type flip-flops which are capable of operating at frequencies of 3 GHz and higher. Using these digital devices as frequency dividers, one can phase shift the SLAC CW-RF systems to optimize the timing for filling the storage rings. We have evaluated the performance of integrated circuits from two vendors for our particular application. Using microstrip circuit techniques, we have built and operated in the accelerator several chassis to synchronize a reset signal from the storage rings to the SLAC 2.856 GHz RF and to phase shift divide-by-four and divide-by-sixteen frequency dividers to the nearest 350 psec bucket required for filling. 4 refs., 4 figs., 2 tabs

  7. 20 CFR 405.515 - Application of circuit court law.

    Science.gov (United States)

    2010-04-01

    ... 20 Employees' Benefits 2 2010-04-01 2010-04-01 false Application of circuit court law. 405.515 Section 405.515 Employees' Benefits SOCIAL SECURITY ADMINISTRATION ADMINISTRATIVE REVIEW PROCESS FOR ADJUDICATING INITIAL DISABILITY CLAIMS Judicial Review § 405.515 Application of circuit court law. We will...

  8. Measurements of complex impedance in microwave high power systems with a new bluetooth integrated circuit.

    Science.gov (United States)

    Roussy, Georges; Dichtel, Bernard; Chaabane, Haykel

    2003-01-01

    By using a new integrated circuit, which is marketed for bluetooth applications, it is possible to simplify the method of measuring the complex impedance, complex reflection coefficient and complex transmission coefficient in an industrial microwave setup. The Analog Devices circuit AD 8302, which measures gain and phase up to 2.7 GHz, operates with variable level input signals and is less sensitive to both amplitude and frequency fluctuations of the industrial magnetrons than are mixers and AM crystal detectors. Therefore, accurate gain and phase measurements can be performed with low stability generators. A mechanical setup with an AD 8302 is described; the calibration procedure and its performance are presented.

  9. 77 FR 42764 - Certain Integrated Circuits, Chipsets, & Products Containing Same Including Televisions; Notice...

    Science.gov (United States)

    2012-07-20

    ...Notice is hereby given that the presiding administrative law judge has issued a Final Initial Determination and Recommended Determination on Remedy and Bonding in the above-captioned investigation. The Commission is soliciting comments on public interest issues raised by the recommended relief, specifically a limited exclusion order against certain integrated circuits, chipsets, and products containing the same including televisions, imported by respondents MediaTek Inc. of Hsinchu City, Taiwan and Zoran Corporation of Sunnyvale, California.

  10. On-chip multi-wavelength laser sources fabricated using generic photonic integration technology

    NARCIS (Netherlands)

    Latkowski, S.; Williams, K.A.; Bente, E.A.J.M.

    Generic photonic integration technology platforms allow for design and fabrication of large complexity application specific photonic integrated circuits. Monolithic active-passive integration on indium phosphide substrate naturally enables a reliable co-integration of optical gain elements and

  11. Investigation of SFQ integrated circuits using Nb fabrication technology

    International Nuclear Information System (INIS)

    Numata, H.; Tanaka, M.; Kitagawa, Y.; Tahara, S.

    1999-01-01

    In NEC's standard process, the minimum junction size is 2 μm and the critical current density (J C ) is 2.5 kA cm -2 . In the process, i-line stepper lithography and reactive ion etching with SF 6 gas are used and the standard deviation (σ) of the critical current (I C ) was 0.9% for the 2 μm junctions. This junction uniformity enables integration of more than 10M junctions if an I C variation of ±10% permits correct circuit operation. A 512-bit shift register was designed and fabricated by our standard process. Correct 512-bit delay operation was obtained. These results are promising for the large-scale integration of single flux quantum circuits. (author)

  12. Optoisolation circuits nonlinearity applications in engineering : optoisolation nonlinear dynamics and chaos, application in engineering

    CERN Document Server

    Aluf, Ofer

    2012-01-01

    This book describes a new concept in analyzing circuits, which includes optoisolation elements. The analysis is based on nonlinear dynamics and chaos models and shows comprehensive benefits and results. All conceptual optoisolation circuits are innovative and can be broadly implemented in engineering applications. The dynamics of optoisolation circuits provides several ways to use them in a variety of applications covering wide areas. The presentation fills the gap of analytical methods for optoisolation circuits analysis, concrete examples, and geometric examples. The optoisolation circuits analysis is developed systematically, starting with basic optoisolation circuits differential equations and their bifurcations, followed by Fixed points analysis, limit cycles and their bifurcations. Optoisolation circuits can be characterized as Lorenz equations, chaos, iterated maps, period doubling and attractors. This book is aimed at electrical and electronic engineers, students and researchers in physics as well. A ...

  13. Radiation sensitivity of integrated circuits Pt. 1

    International Nuclear Information System (INIS)

    Bereczkine Kerenyi, Ilona

    1986-01-01

    The cosmic ray sensitivity of CMOS integrated circuits are overviewed in three parts. The aim is to analyze the effects of ionizing radiation on the degradation of electronic parameters, the effects of the electric state during irradiation, and the radiation hardening of ICs. In this Part 1 a general introduction of the response of semiconductors to cosmic radiation is given, and the radiation tolerance and hardening of small-scale integrated CMOS ICs is analyzed in detail. The devices include various basic inverters and simple gate ICs. (R.P.)

  14. Silicon wafers for integrated circuit process

    OpenAIRE

    Leroy , B.

    1986-01-01

    Silicon as a substrate material will continue to dominate the market of integrated circuits for many years. We first review how crystal pulling procedures impact the quality of silicon. We then investigate how thermal treatments affect the behaviour of oxygen and carbon, and how, as a result, the quality of silicon wafers evolves. Gettering techniques are then presented. We conclude by detailing the requirements that wafers must satisfy at the incoming inspection.

  15. 77 FR 25747 - Certain Semiconductor Integrated Circuit Devices and Products Containing Same; Institution of...

    Science.gov (United States)

    2012-05-01

    ... INTERNATIONAL TRADE COMMISSION [Inv. No. 337-TA-840] Certain Semiconductor Integrated Circuit... States after importation of certain semiconductor integrated circuit devices and products containing same... No. 6,847,904 (``the '904 patent''). The complaint further alleges that an industry in the United...

  16. Integrated genomic and gene expression profiling identifies two major genomic circuits in urothelial carcinoma.

    Directory of Open Access Journals (Sweden)

    David Lindgren

    Full Text Available Similar to other malignancies, urothelial carcinoma (UC is characterized by specific recurrent chromosomal aberrations and gene mutations. However, the interconnection between specific genomic alterations, and how patterns of chromosomal alterations adhere to different molecular subgroups of UC, is less clear. We applied tiling resolution array CGH to 146 cases of UC and identified a number of regions harboring recurrent focal genomic amplifications and deletions. Several potential oncogenes were included in the amplified regions, including known oncogenes like E2F3, CCND1, and CCNE1, as well as new candidate genes, such as SETDB1 (1q21, and BCL2L1 (20q11. We next combined genome profiling with global gene expression, gene mutation, and protein expression data and identified two major genomic circuits operating in urothelial carcinoma. The first circuit was characterized by FGFR3 alterations, overexpression of CCND1, and 9q and CDKN2A deletions. The second circuit was defined by E3F3 amplifications and RB1 deletions, as well as gains of 5p, deletions at PTEN and 2q36, 16q, 20q, and elevated CDKN2A levels. TP53/MDM2 alterations were common for advanced tumors within the two circuits. Our data also suggest a possible RAS/RAF circuit. The tumors with worst prognosis showed a gene expression profile that indicated a keratinized phenotype. Taken together, our integrative approach revealed at least two separate networks of genomic alterations linked to the molecular diversity seen in UC, and that these circuits may reflect distinct pathways of tumor development.

  17. Design of two digital radiation tolerant integrated circuits for high energy physics experiments data readout

    CERN Document Server

    Bonacini, Sandro

    2003-01-01

    High Energy Physics research (HEP) involves the design of readout electron- ics for its experiments, which generate a high radiation ¯eld in the detectors. The several integrated circuits placed in the future Large Hadron Collider (LHC) experiments' environment have to resist the radiation and carry out their normal operation. In this thesis I will describe in detail what, during my 10-months partic- ipation in the digital section of the Microelectronics group at CERN, I had the possibility to work on: - The design of a radiation-tolerant data readout digital integrated cir- cuit in a 0.25 ¹m CMOS technology, called \\the Kchip", for the CMS preshower front-end system. This will be described in Chapter 3. - The design of a radiation-tolerant SRAM integrated circuit in a 0.13 ¹m CMOS technology, for technology radiation testing purposes and fu- ture applications in the HEP ¯eld. The SRAM will be described in Chapter 4. All the work has carried out under the supervision and with the help of Dr. Kostas Klouki...

  18. Designing charge-sensitive preamplifiers based on low-noise analog integrated circuits

    International Nuclear Information System (INIS)

    Agakhanyan, T.M.

    1998-01-01

    The methodology for designing charge-sensitive preamplifiers on the low-noise analog integral circuits, including all the stages: the mathematical synthesis with optimization of the intermediate function; the scheme-technical synthesis with parametric optimization of the scheme and analysis of draft projects with the parameter verification is presented. The designing is conducted on the basis of requirements for signal parameters and noise indices of the preamplifier. The system of automated designing of the charge-sensitive preamplifiers on the low-noise analog integral circuits is developed [ru

  19. High-Performance WSe2 Complementary Metal Oxide Semiconductor Technology and Integrated Circuits.

    Science.gov (United States)

    Yu, Lili; Zubair, Ahmad; Santos, Elton J G; Zhang, Xu; Lin, Yuxuan; Zhang, Yuhao; Palacios, Tomás

    2015-08-12

    Because of their extraordinary structural and electrical properties, two-dimensional materials are currently being pursued for applications such as thin-film transistors and integrated circuit. One of the main challenges that still needs to be overcome for these applications is the fabrication of air-stable transistors with industry-compatible complementary metal oxide semiconductor (CMOS) technology. In this work, we experimentally demonstrate a novel high performance air-stable WSe2 CMOS technology with almost ideal voltage transfer characteristic, full logic swing and high noise margin with different supply voltages. More importantly, the inverter shows large voltage gain (∼38) and small static power (picowatts), paving the way for low power electronic system in 2D materials.

  20. Progress in complementary metal–oxide–semiconductor silicon photonics and optoelectronic integrated circuits

    International Nuclear Information System (INIS)

    Chen Hongda; Zhang Zan; Huang Beiju; Mao Luhong; Zhang Zanyun

    2015-01-01

    Silicon photonics is an emerging competitive solution for next-generation scalable data communications in different application areas as high-speed data communication is constrained by electrical interconnects. Optical interconnects based on silicon photonics can be used in intra/inter-chip interconnects, board-to-board interconnects, short-reach communications in datacenters, supercomputers and long-haul optical transmissions. In this paper, we present an overview of recent progress in silicon optoelectronic devices and optoelectronic integrated circuits (OEICs) based on a complementary metal–oxide–semiconductor-compatible process, and focus on our research contributions. The silicon optoelectronic devices and OEICs show good characteristics, which are expected to benefit several application domains, including communication, sensing, computing and nonlinear systems. (review)

  1. Experimental Demonstration of 7 Tb/s Switching Using Novel Silicon Photonic Integrated Circuit

    DEFF Research Database (Denmark)

    Ding, Yunhong; Kamchevska, Valerija; Dalgaard, Kjeld

    2016-01-01

    We demonstrate BER performance <10^-9 for a 1 Tb/s/core transmission over 7-core fiber and SDM switching using a novel silicon photonic integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers.......We demonstrate BER performance integrated circuit composed of a 7x7 fiber switch and low loss SDM couplers....

  2. Active quenching circuit for a InGaAs single-photon avalanche diode

    International Nuclear Information System (INIS)

    Zheng Lixia; Wu Jin; Xi Shuiqing; Shi Longxing; Liu Siyang; Sun Weifeng

    2014-01-01

    We present a novel gated operation active quenching circuit (AQC). In order to simulate the quenching circuit a complete SPICE model of a InGaAs SPAD is set up according to the I–V characteristic measurement results of the detector. The circuit integrated with aROIC (readout integrated circuit) is fabricated in an CSMC 0.5 μm CMOS process and then hybrid packed with the detector. Chip measurement results show that the functionality of the circuit is correct and the performance is suitable for practical system applications. (semiconductor integrated circuits)

  3. Branch-specific plasticity of a bifunctional dopamine circuit encodes protein hunger.

    Science.gov (United States)

    Liu, Qili; Tabuchi, Masashi; Liu, Sha; Kodama, Lay; Horiuchi, Wakako; Daniels, Jay; Chiu, Lucinda; Baldoni, Daniel; Wu, Mark N

    2017-05-05

    Free-living animals must not only regulate the amount of food they consume but also choose which types of food to ingest. The shifting of food preference driven by nutrient-specific hunger can be essential for survival, yet little is known about the underlying mechanisms. We identified a dopamine circuit that encodes protein-specific hunger in Drosophila The activity of these neurons increased after substantial protein deprivation. Activation of this circuit simultaneously promoted protein intake and restricted sugar consumption, via signaling to distinct downstream neurons. Protein starvation triggered branch-specific plastic changes in these dopaminergic neurons, thus enabling sustained protein consumption. These studies reveal a crucial circuit mechanism by which animals adjust their dietary strategy to maintain protein homeostasis. Copyright © 2017, American Association for the Advancement of Science.

  4. Wafer-level testing and test during burn-in for integrated circuits

    CERN Document Server

    Bahukudumbi, Sudarshan

    2010-01-01

    Wafer-level testing refers to a critical process of subjecting integrated circuits and semiconductor devices to electrical testing while they are still in wafer form. Burn-in is a temperature/bias reliability stress test used in detecting and screening out potential early life device failures. This hands-on resource provides a comprehensive analysis of these methods, showing how wafer-level testing during burn-in (WLTBI) helps lower product cost in semiconductor manufacturing.Engineers learn how to implement the testing of integrated circuits at the wafer-level under various resource constrain

  5. Relay Protection and Automation Systems Based on Programmable Logic Integrated Circuits

    International Nuclear Information System (INIS)

    Lashin, A. V.; Kozyrev, A. V.

    2015-01-01

    One of the most promising forms of developing the apparatus part of relay protection and automation devices is considered. The advantages of choosing programmable logic integrated circuits to obtain adaptive technological algorithms in power system protection and control systems are pointed out. The technical difficulties in the problems which today stand in the way of using relay protection and automation systems are indicated and a new technology for solving these problems is presented. Particular attention is devoted to the possibility of reconfiguring the logic of these devices, using programmable logic integrated circuits

  6. Boson sampling with integrated optical circuits

    International Nuclear Information System (INIS)

    Bentivegna, M.

    2014-01-01

    Simulating the evolution of non-interacting bosons through a linear transformation acting on the system’s Fock state is strongly believed to be hard for a classical computer. This is commonly known as the Boson Sampling problem, and has recently got attention as the first possible way to demonstrate the superior computational power of quantum devices over classical ones. In this paper we describe the quantum optics approach to this problem, highlighting the role of integrated optical circuits.

  7. The single-event effect evaluation technology for nano integrated circuits

    International Nuclear Information System (INIS)

    Zheng Hongchao; Zhao Yuanfu; Yue Suge; Fan Long; Du Shougang; Chen Maoxin; Yu Chunqing

    2015-01-01

    Single-event effects of nano scale integrated circuits are investigated. Evaluation methods for single-event transients, single-event upsets, and single-event functional interrupts in nano circuits are summarized and classified in detail. The difficulties in SEE testing are discussed as well as the development direction of test technology, with emphasis placed on the experimental evaluation of a nano circuit under heavy ion, proton, and laser irradiation. The conclusions in this paper are based on many years of testing at accelerator facilities and our present understanding of the mechanisms for SEEs, which have been well verified experimentally. (paper)

  8. Optoelectronic integrated circuits utilising vertical-cavity surface-emitting semiconductor lasers

    International Nuclear Information System (INIS)

    Zakharov, S D; Fyodorov, V B; Tsvetkov, V V

    1999-01-01

    Optoelectronic integrated circuits with additional optical inputs/outputs, in which vertical-cavity surface-emitting (VCSE) lasers perform the data transfer functions, are considered. The mutual relationship and the 'affinity' between optical means for data transfer and processing, on the one hand, and the traditional electronic component base, on the other, are demonstrated in the case of implementation of three-dimensional interconnects with a high transmission capacity. Attention is drawn to the problems encountered when semiconductor injection lasers are used in communication lines. It is shown what role can be played by VCSE lasers in solving these problems. A detailed analysis is made of the topics relating to possible structural and technological solutions in the fabrication of single lasers and of their arrays, and also of the problems hindering integrating of lasers into emitter arrays. Considerable attention is given to integrated circuits with optoelectronic smart pixels. Various technological methods for vertical integration of GaAs VCSE lasers with the silicon substrate of a microcircuit (chip) are discussed. (review)

  9. Flexible circuits with integrated switches for robotic shape sensing

    Science.gov (United States)

    Harnett, C. K.

    2016-05-01

    Digital switches are commonly used for detecting surface contact and limb-position limits in robotics. The typical momentary-contact digital switch is a mechanical device made from metal springs, designed to connect with a rigid printed circuit board (PCB). However, flexible printed circuits are taking over from the rigid PCB in robotics because the circuits can bend while carrying signals and power through moving joints. This project is motivated by a previous work where an array of surface-mount momentary contact switches on a flexible circuit acted as an all-digital shape sensor compatible with the power resources of energy harvesting systems. Without a rigid segment, the smallest commercially-available surface-mount switches would detach from the flexible circuit after several bending cycles, sometimes violently. This report describes a low-cost, conductive fiber based method to integrate electromechanical switches into flexible circuits and other soft, bendable materials. Because the switches are digital (on/off), they differ from commercially-available continuous-valued bend/flex sensors. No amplification or analog-to-digital conversion is needed to read the signal, but the tradeoff is that the digital switches only give a threshold curvature value. Boundary conditions on the edges of the flexible circuit are key to setting the threshold curvature value for switching. This presentation will discuss threshold-setting, size scaling of the design, automation for inserting a digital switch into the flexible circuit fabrication process, and methods for reconstructing a shape from an array of digital switch states.

  10. In-situ fabrication of flexible vertically integrated electronic circuits by inkjet printing

    International Nuclear Information System (INIS)

    Wang Zhuo; Wu Wenwen; Yang Qunbao; Li Yongxiang; Noh, Chang-Ho

    2009-01-01

    In this paper, a facile approach for fabricating flexible vertically integrated electronic circuits is demonstrated. A desktop inkjet printer was modified and employed to print silver precursor on a polymer-coated buffer substrates. In-situ reaction was taken place and a conducting line was formed without need of a high temperature treatment. Through this process, several layers of metal integrated circuits were deposited sequentially with polymer buffer layers sandwiched between each layer. Hence, vertically integrated electronic components of diodes, solar cells, flexible flat panel displays, and electrochromic devices can be built with this simple and low-cost technique.

  11. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-01-01

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications. PMID:27073154

  12. Nanoscale on-chip all-optical logic parity checker in integrated plasmonic circuits in optical communication range.

    Science.gov (United States)

    Wang, Feifan; Gong, Zibo; Hu, Xiaoyong; Yang, Xiaoyu; Yang, Hong; Gong, Qihuang

    2016-04-13

    The nanoscale chip-integrated all-optical logic parity checker is an essential core component for optical computing systems and ultrahigh-speed ultrawide-band information processing chips. Unfortunately, little experimental progress has been made in development of these devices to date because of material bottleneck limitations and a lack of effective realization mechanisms. Here, we report a simple and efficient strategy for direct realization of nanoscale chip-integrated all-optical logic parity checkers in integrated plasmonic circuits in the optical communication range. The proposed parity checker consists of two-level cascaded exclusive-OR (XOR) logic gates that are realized based on the linear interference of surface plasmon polaritons propagating in the plasmonic waveguides. The parity of the number of logic 1s in the incident four-bit logic signals is determined, and the output signal is given the logic state 0 for even parity (and 1 for odd parity). Compared with previous reports, the overall device feature size is reduced by more than two orders of magnitude, while ultralow energy consumption is maintained. This work raises the possibility of realization of large-scale integrated information processing chips based on integrated plasmonic circuits, and also provides a way to overcome the intrinsic limitations of serious surface plasmon polariton losses for on-chip integration applications.

  13. Thermal measurement a requirement for monolithic microwave integrated circuit design

    OpenAIRE

    Hopper, Richard; Oxley, C. H.

    2008-01-01

    The thermal management of structures such as Monolithic Microwave Integrated Circuits (MMICs) is important, given increased circuit packing densities and RF output powers. The paper will describe the IR measurement technology necessary to obtain accurate temperature profiles on the surface of semiconductor devices. The measurement procedure will be explained, including the device mounting arrangement and emissivity correction technique. The paper will show how the measurement technique has be...

  14. Silicon CMOS optical receiver circuits with integrated thin-film compound semiconductor detectors

    Science.gov (United States)

    Brooke, Martin A.; Lee, Myunghee; Jokerst, Nan Marie; Camperi-Ginestet, C.

    1995-04-01

    While many circuit designers have tackled the problem of CMOS digital communications receiver design, few have considered the problem of circuitry suitable for an all CMOS digital IC fabrication process. Faced with a high speed receiver design the circuit designer will soon conclude that a high speed analog-oriented fabrication process provides superior performance advantages to a digital CMOS process. However, for applications where there are overwhelming reasons to integrate the receivers on the same IC as large amounts of conventional digital circuitry, the low yield and high cost of the exotic analog-oriented fabrication is no longer an option. The issues that result from a requirement to use a digital CMOS IC process cut across all aspects of receiver design, and result in significant differences in circuit design philosophy and topology. Digital ICs are primarily designed to yield small, fast CMOS devices for digital logic gates, thus no effort is put into providing accurate or high speed resistances, or capacitors. This lack of any reliable resistance or capacitance has a significant impact on receiver design. Since resistance optimization is not a prerogative of the digital IC process engineer, the wisest option is thus to not use these elements, opting instead for active circuitry to replace the functions normally ascribed to resistance and capacitance. Depending on the application receiver noise may be a dominant design constraint. The noise performance of CMOS amplifiers is different than bipolar or GaAs MESFET circuits, shot noise is generally insignificant when compared to channel thermal noise. As a result the optimal input stage topology is significantly different for the different technologies. It is found that, at speeds of operation approaching the limits of the digital CMOS process, open loop designs have noise-power-gain-bandwidth tradeoff performance superior to feedback designs. Furthermore, the lack of good resisters and capacitors

  15. A low-ripple chargepump circuit for high voltage applications

    NARCIS (Netherlands)

    Berkhout, M.; Berkhout, M.; van Steenwijk, G.; van Steenwijk, Gijs; van Tuijl, Adrianus Johannes Maria

    1995-01-01

    The subject of this paper is a fully integrated chargepump circuit with a very low output voltage ripple. At a supply voltage of 30V the chargepump can source 1mA at an output voltage of 40V. Two simple modifications to the classical chargepump circuit give a substantial reduction of the output

  16. Fabrication technology for lead-alloy Josephson devices for high-density integrated circuits

    International Nuclear Information System (INIS)

    Imamura, T.; Hoko, H.; Tamura, H.; Yoshida, A.; Suzuki, H.; Morohashi, S.; Ohara, S.; Hasuo, S.; Yamaoka, T.

    1986-01-01

    Fabrication technology for lead-alloy Josephson devices was evaluated from the viewpoint of application to large-scale integrated circuits. Metal and insulating layers used in the circuits were evaluated, and optimization of techniques for deposition or formation of these layers was investigated. Metallization of the Pb-In-Au base electrode and the Pb-Bi counterelectrode was studied in terms of optimizing the deposited films, to improve the reliability of junction electrodes. The formation of the oxide barrier was studied by in situ ellipsometry. SiO/sub x/ deposited in oxygen was developed as the insulation layer with less defect density than conventional SiO. A liftoff technique using toluene soaking was developed, and patterns with a minimum line width of 2 μm were consistently reproduced. The characteristics of each element in the circuits were evaluated for test vehicles. For the junction, the following items were evaluated: controllability of the critical current I/sub c/, junction quality, I/sub c/ uniformity, junction yield, and thermal cycling and storage stability. For the peripheral elements, integrity of lines and contacts, and characteristics of resistors were evaluated. 8-kbit memory cell arrays with a full vertical structure were fabricated to evaluate these technologies in combination. The continuity of each metal layer and insulation between metal layers were evaluated with an autoprober at room temperature. For selected chips, cell characteristics have been measured, and their I/sub c/ uniformity and production yields for cells are discussed. Normal operation of the memory cells was confirmed for all of the 24 accessible cells on a chip

  17. Generation of optical vortices in an integrated optical circuit

    Science.gov (United States)

    Tudor, Rebeca; Kusko, Mihai; Kusko, Cristian

    2017-09-01

    In this work, the generation of optical vortices in an optical integrated circuit is numerically demonstrated. The optical vortices with topological charge m = ±1 are obtained by the coherent superposition of the first order modes present in a waveguide with a rectangular cross section, where the phase delay between these two propagating modes is Δφ = ±π/2. The optical integrated circuit consists of an input waveguide continued with a y-splitter. The left and the right arms of the splitter form two coupling regions K1 and K2 with a multimode output waveguide. In each coupling region, the fundamental modes present in the arms of the splitter are selectively coupled into the output waveguide horizontal and vertical first order modes, respectively. We showed by employing the beam propagation method simulations that the fine tuning of the geometrical parameters of the optical circuit makes possible the generation of optical vortices in both transverse electric (TE) and transverse magnetic (TM) modes. Also, we demonstrated that by placing a thermo-optical element on one of the y-splitter arms, it is possible to switch the topological charge of the generated vortex from m = 1 to m = -1.

  18. Wireless neural recording with single low-power integrated circuit.

    Science.gov (United States)

    Harrison, Reid R; Kier, Ryan J; Chestek, Cynthia A; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V

    2009-08-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6- mum 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902-928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor.

  19. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Directory of Open Access Journals (Sweden)

    Huan-Yuan Chen

    2017-09-01

    Full Text Available This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting.

  20. An Efficient Hardware Circuit for Spike Sorting Based on Competitive Learning Networks

    Science.gov (United States)

    Chen, Huan-Yuan; Chen, Chih-Chang

    2017-01-01

    This study aims to present an effective VLSI circuit for multi-channel spike sorting. The circuit supports the spike detection, feature extraction and classification operations. The detection circuit is implemented in accordance with the nonlinear energy operator algorithm. Both the peak detection and area computation operations are adopted for the realization of the hardware architecture for feature extraction. The resulting feature vectors are classified by a circuit for competitive learning (CL) neural networks. The CL circuit supports both online training and classification. In the proposed architecture, all the channels share the same detection, feature extraction, learning and classification circuits for a low area cost hardware implementation. The clock-gating technique is also employed for reducing the power dissipation. To evaluate the performance of the architecture, an application-specific integrated circuit (ASIC) implementation is presented. Experimental results demonstrate that the proposed circuit exhibits the advantages of a low chip area, a low power dissipation and a high classification success rate for spike sorting. PMID:28956859

  1. Post-irradiation effects in CMOS integrated circuits

    International Nuclear Information System (INIS)

    Zietlow, T.C.; Barnes, C.E.; Morse, T.C.; Grusynski, J.S.; Nakamura, K.; Amram, A.; Wilson, K.T.

    1988-01-01

    The post-irradiation response of CMOS integrated circuits from three vendors has been measured as a function of temperature and irradiation bias. The author's have found that a worst-case anneal temperature for rebound testing is highly process dependent. At an anneal temperature of 80 0 C, the timing parameters of a 16K SRAM from vendor A quickly saturate at maximum values, and display no further changes at this temperature. At higher temperature, evidence for the anneal of interface state charge is observed. Dynamic bias during irradiation results in the same saturation value for the timing parameters, but the anneal time required to reach this value is longer. CMOS/SOS integrated circuits (vendor B) were also examined, and showed similar behavior, except that the saturation value for the timing parameters was stable up to 105 0 C. After irradiation to 10 Mrad(Si), a 16K SRAM (vendor C) was annealed at 80 0 C. In contrast to the results from the vendor A SRAM, the access time decreased toward prerad values during the anneal. Another part irradiated in the same manner but annealed at room temperature showed a slight increase during the anneal

  2. Integrated optical circuit engineering V; Proceedings of the Meeting, San Diego, CA, Aug. 17-20, 1987

    Science.gov (United States)

    Mentzer, Mark A.

    Recent advances in the theoretical and practical design and applications of optoelectronic devices and optical circuits are examined in reviews and reports. Topics discussed include system and market considerations, guided-wave phenomena, waveguide devices, processing technology, lithium niobate devices, and coupling problems. Consideration is given to testing and measurement, integrated optics for fiber-optic systems, optical interconnect technology, and optical computing.

  3. Analog Integrated Circuit Design for Spike Time Dependent Encoder and Reservoir in Reservoir Computing Processors

    Science.gov (United States)

    2018-01-01

    HAS BEEN REVIEWED AND IS APPROVED FOR PUBLICATION IN ACCORDANCE WITH ASSIGNED DISTRIBUTION STATEMENT. FOR THE CHIEF ENGINEER : / S / / S...bridged high-performance computing, nanotechnology , and integrated circuits & systems. 15. SUBJECT TERMS neuromorphic computing, neuron design, spike...multidisciplinary effort encompassed high-performance computing, nanotechnology , integrated circuits, and integrated systems. The project’s architecture was

  4. Application of Circuit Model for Photovoltaic Energy Conversion System

    Directory of Open Access Journals (Sweden)

    Natarajan Pandiarajan

    2012-01-01

    Full Text Available Circuit model of photovoltaic (PV module is presented in this paper that can be used as a common platform by material scientists and power electronic circuit designers to develop better PV power plant. Detailed modeling procedure for the circuit model with numerical dimensions is presented using power system blockset of MATLAB/Simulink. The developed model is integrated with DC-DC boost converter with closed-loop control of maximum power point tracking (MPPT algorithm. Simulation results are validated with the experimental setup.

  5. Prediction of ionizing radiation effects in integrated circuits using black-box models

    International Nuclear Information System (INIS)

    Williamson, P.W.

    1976-10-01

    A method is described which allows general black-box modelling of integrated circuits as distinct from the existing method of deriving the radiation induced response of the model from actual terminal measurements on the device during irradiation. Both digital and linear circuits are discussed. (author)

  6. A design concept for an MMIC (Monolithic Microwave Integrated Circuit) microstrip phased array

    Science.gov (United States)

    Lee, Richard Q.; Smetana, Jerry; Acosta, Roberto

    1987-01-01

    A conceptual design for a microstrip phased array with monolithic microwave integrated circuit (MMIC) amplitude and phase controls is described. The MMIC devices used are 20 GHz variable power amplifiers and variable phase shifters recently developed by NASA contractors for applications in future Ka proposed design, which concept is for a general NxN element array of rectangular lattice geometry. Subarray excitation is incorporated in the MMIC phased array design to reduce the complexity of the beam forming network and the number of MMIC components required.

  7. Radiation response of high speed CMOS integrated circuits

    International Nuclear Information System (INIS)

    Yue, H.; Davison, D.; Jennings, R.F.; Lothongkam, P.; Rinerson, D.; Wyland, D.

    1987-01-01

    This paper studies the total dose and dose rate radiation response of the FCT family of high speed CMOS integrated circuits. Data taken on the devices is used to establish the dominant failure modes, and this data is further analyzed using one-sided tolerance factors for normal distribution statistical analysis

  8. Digital integrated circuit design using Verilog and SystemVerilog

    CERN Document Server

    Mehler, Ronald W

    2014-01-01

    For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually

  9. Economic testing of large integrated switching circuits - a challenge to the test engineer

    International Nuclear Information System (INIS)

    Kreinberg, W.

    1978-01-01

    With reference to large integrated switching circuits, one can use an incoming standard programme test or the customer's switching circuits. The author describes the development of suitable, extensive and economical test programmes. (orig.) [de

  10. Wireless Data Transmission at Terahertz Carrier Waves Generated from a Hybrid InP-Polymer Dual Tunable DBR Laser Photonic Integrated Circuit.

    Science.gov (United States)

    Carpintero, Guillermo; Hisatake, Shintaro; de Felipe, David; Guzman, Robinson; Nagatsuma, Tadao; Keil, Norbert

    2018-02-14

    We report for the first time the successful wavelength stabilization of two hybrid integrated InP/Polymer DBR lasers through optical injection. The two InP/Polymer DBR lasers are integrated into a photonic integrated circuit, providing an ideal source for millimeter and Terahertz wave generation by optical heterodyne technique. These lasers offer the widest tuning range of the carrier wave demonstrated to date up into the Terahertz range, about 20 nm (2.5 THz) on a single photonic integrated circuit. We demonstrate the application of this source to generate a carrier wave at 330 GHz to establish a wireless data transmission link at a data rate up to 18 Gbit/s. Using a coherent detection scheme we increase the sensitivity by more than 10 dB over direct detection.

  11. Application of Cu-polyimide flex circuit and Al-on-glass pitch adapter for the ATLAS SCT barrel hybrid

    CERN Document Server

    Unno, Y; Ikegami, Y; Iwata, Y; Kohriki, T; Kondo, T; Nakano, I; Ohsugi, T; Takashima, R; Tanaka, R; Terada, S; Ujiie, N

    2005-01-01

    We applied the surface build-up Cu-polyimide flex-circuit technology with laser vias to the ATLAS SCT barrel hybrid to be made in one piece from the connector to the electronics sections including cables. The hybrids, reinforced with carbon-carbon substrates, provide mechanical strength, thermal conductivity, low-radiation length, and stability in application-specific integrated circuit (ASIC) operation. By following the design rules, we experienced little trouble in breaking the traces. The pitch adapter between the sensor and the ASICs was made of aluminum traces on glass substrate. We identified that the generation of whiskers around the wire-bonding feet was correlated with the hardness of metallized aluminum. The appropriate hardness has been achieved by keeping the temperature of the glasses as low as room temperature during the metallization. The argon plasma cleaning procedure cleaned the contamination on the gold pads of the hybrids for successful wire bonding, although it was unsuccessful in the alu...

  12. Effective and efficient circuit synthesis for LUT FPGAs : based on functional decomposition and information relationship measures

    NARCIS (Netherlands)

    Chojnacki, A.

    2004-01-01

    The narrowing opportunity window and the dramatically increasing development costs of deep sub-micron application specific integrated circuit (ASIC) designs have presented new challenges to the development process. The cost of ASICs development and fabrication is presently so high that more and more

  13. Micro-coolers fabricated as a component in an integrated circuit

    International Nuclear Information System (INIS)

    Glover, James; Oxley, Chris H; Khalid, Ata; Cumming, David; Stephen, Alex; Dunn, Geoff

    2015-01-01

    The packing density and power capacity of integrated electronics is increasing resulting in higher thermal flux densities. Improved thermal management techniques are required and one approach is to include thermoelectric coolers as part of the integrated circuit. An analysis will be described showing that the supporting substrate will have a large influence on the cooling capacity of the thermoelectric cooler. In particular, for materials with a low ZT figure of merit (for example gallium arsenide (GaAs) based compounds) the substrate will have to be substantially thinned to obtain cooling, which may preclude the use of thermoelectric coolers, for example, as part of a GaAs based integrated circuit. Further, using experimental techniques to measure only the small positive cooling temperature difference (ΔT) between the anode (T h ) and the cathode (T c ) contacts can be misinterpreted as cooling when in fact it is heating. (paper)

  14. Highly Uniform Carbon Nanotube Field-Effect Transistors and Medium Scale Integrated Circuits.

    Science.gov (United States)

    Chen, Bingyan; Zhang, Panpan; Ding, Li; Han, Jie; Qiu, Song; Li, Qingwen; Zhang, Zhiyong; Peng, Lian-Mao

    2016-08-10

    Top-gated p-type field-effect transistors (FETs) have been fabricated in batch based on carbon nanotube (CNT) network thin films prepared from CNT solution and present high yield and highly uniform performance with small threshold voltage distribution with standard deviation of 34 mV. According to the property of FETs, various logical and arithmetical gates, shifters, and d-latch circuits were designed and demonstrated with rail-to-rail output. In particular, a 4-bit adder consisting of 140 p-type CNT FETs was demonstrated with higher packing density and lower supply voltage than other published integrated circuits based on CNT films, which indicates that CNT based integrated circuits can reach to medium scale. In addition, a 2-bit multiplier has been realized for the first time. Benefitted from the high uniformity and suitable threshold voltage of CNT FETs, all of the fabricated circuits based on CNT FETs can be driven by a single voltage as small as 2 V.

  15. Logistic Regression Modeling of Diminishing Manufacturing Sources for Integrated Circuits

    National Research Council Canada - National Science Library

    Gravier, Michael

    1999-01-01

    .... This thesis draws on available data from the electronics integrated circuit industry to attempt to assess whether statistical modeling offers a viable method for predicting the presence of DMSMS...

  16. Experimental Study of WBFC method for testing electromagnetic immunity of integrated circuits

    OpenAIRE

    香川, 直己; カガワ, ナオキ; Naoki, KAGAWA

    2004-01-01

    The author made a workbench faraday cage, WBFC, in order to estimate performance of the WBFC method for the measurement of common mode noise immunity of integrated circuits. In this report, characteristics of the constructed workbench faraday cage and results of experimental study of effects of the common mode noise on a circuit board including an electronic device are shown. Selected DUT, LM324 is popular operational amplifier for electrical circuits in vehicles.

  17. Design automation for integrated nonlinear logic circuits (Conference Presentation)

    Science.gov (United States)

    Van Vaerenbergh, Thomas; Pelc, Jason; Santori, Charles; Bose, Ranojoy; Kielpinski, Dave; Beausoleil, Raymond G.

    2016-05-01

    A key enabler of the IT revolution of the late 20th century was the development of electronic design automation (EDA) tools allowing engineers to manage the complexity of electronic circuits with transistor counts now reaching into the billions. Recently, we have been developing large-scale nonlinear photonic integrated logic circuits for next generation all-optical information processing. At this time a sufficiently powerful EDA-style software tool chain to design this type of complex circuits does not yet exist. Here we describe a hierarchical approach to automating the design and validation of photonic integrated circuits, which can scale to several orders of magnitude higher complexity than the state of the art. Most photonic integrated circuits developed today consist of a small number of components, and only limited hierarchy. For example, a simple photonic transceiver may contain on the order of 10 building-block components, consisting of grating couplers for photonic I/O, modulators, and signal splitters/combiners. Because this is relatively easy to lay out by hand (or simple script) existing photonic design tools have relatively little automation in comparison to electronics tools. But demonstrating all-optical logic will require significantly more complex photonic circuits containing up to 1,000 components, hence becoming infeasible to design manually. Our design framework is based off Python-based software from Luceda Photonics which provides an environment to describe components, simulate their behavior, and export design files (GDS) to foundries for fabrication. At a fundamental level, a photonic component is described as a parametric cell (PCell) similarly to electronics design. PCells are described by geometric characteristics of their layout. A critical part of the design framework is the implementation of PCells as Python objects. PCell objects can then use inheritance to simplify design, and hierarchical designs can be made by creating composite

  18. Molecular annotation of integrative feeding neural circuits.

    Science.gov (United States)

    Pérez, Cristian A; Stanley, Sarah A; Wysocki, Robert W; Havranova, Jana; Ahrens-Nicklas, Rebecca; Onyimba, Frances; Friedman, Jeffrey M

    2011-02-02

    The identity of higher-order neurons and circuits playing an associative role to control feeding is unknown. We injected pseudorabies virus, a retrograde tracer, into masseter muscle, salivary gland, and tongue of BAC-transgenic mice expressing GFP in specific neural populations and identified several CNS regions that project multisynaptically to the periphery. MCH and orexin neurons were identified in the lateral hypothalamus, and Nurr1 and Cnr1 in the amygdala and insular/rhinal cortices. Cholera toxin β tracing showed that insular Nurr1(+) and Cnr1(+) neurons project to the amygdala or lateral hypothalamus, respectively. Finally, we show that cortical Cnr1(+) neurons show increased Cnr1 mRNA and c-Fos expression after fasting, consistent with a possible role for Cnr1(+) neurons in feeding. Overall, these studies define a general approach for identifying specific molecular markers for neurons in complex neural circuits. These markers now provide a means for functional studies of specific neuronal populations in feeding or other complex behaviors. Copyright © 2011 Elsevier Inc. All rights reserved.

  19. Organic membrane photonic integrated circuits (OMPICs).

    Science.gov (United States)

    Amemiya, Tomohiro; Kanazawa, Toru; Hiratani, Takuo; Inoue, Daisuke; Gu, Zhichen; Yamasaki, Satoshi; Urakami, Tatsuhiro; Arai, Shigehisa

    2017-08-07

    We propose the concept of organic membrane photonic integrated circuits (OMPICs), which incorporate various functions needed for optical signal processing into a flexible organic membrane. We describe the structure of several devices used within the proposed OMPICs (e.g., transmission lines, I/O couplers, phase shifters, photodetectors, modulators), and theoretically investigate their characteristics. We then present a method of fabricating the photonic devices monolithically in an organic membrane and demonstrate the operation of transmission lines and I/O couplers, the most basic elements of OMPICs.

  20. Integrated circuits and electrode interfaces for noninvasive physiological monitoring.

    Science.gov (United States)

    Ha, Sohmyung; Kim, Chul; Chi, Yu M; Akinin, Abraham; Maier, Christoph; Ueno, Akinori; Cauwenberghs, Gert

    2014-05-01

    This paper presents an overview of the fundamentals and state of the-art in noninvasive physiological monitoring instrumentation with a focus on electrode and optrode interfaces to the body, and micropower-integrated circuit design for unobtrusive wearable applications. Since the electrode/optrode-body interface is a performance limiting factor in noninvasive monitoring systems, practical interface configurations are offered for biopotential acquisition, electrode-tissue impedance measurement, and optical biosignal sensing. A systematic approach to instrumentation amplifier (IA) design using CMOS transistors operating in weak inversion is shown to offer high energy and noise efficiency. Practical methodologies to obviate 1/f noise, counteract electrode offset drift, improve common-mode rejection ratio, and obtain subhertz high-pass cutoff are illustrated with a survey of the state-of-the-art IAs. Furthermore, fundamental principles and state-of-the-art technologies for electrode-tissue impedance measurement, photoplethysmography, functional near-infrared spectroscopy, and signal coding and quantization are reviewed, with additional guidelines for overall power management including wireless transmission. Examples are presented of practical dry-contact and noncontact cardiac, respiratory, muscle and brain monitoring systems, and their clinical applications.

  1. High performance protection circuit for power electronics applications

    Energy Technology Data Exchange (ETDEWEB)

    Tudoran, Cristian D., E-mail: cristian.tudoran@itim-cj.ro; Dădârlat, Dorin N.; Toşa, Nicoleta; Mişan, Ioan [National Institute for Research and Development of Isotopic and Molecular Technologies, 67-103 Donat, PO 5 Box 700, 400293 Cluj-Napoca (Romania)

    2015-12-23

    In this paper we present a high performance protection circuit designed for the power electronics applications where the load currents can increase rapidly and exceed the maximum allowed values, like in the case of high frequency induction heating inverters or high frequency plasma generators. The protection circuit is based on a microcontroller and can be adapted for use on single-phase or three-phase power systems. Its versatility comes from the fact that the circuit can communicate with the protected system, having the role of a “sensor” or it can interrupt the power supply for protection, in this case functioning as an external, independent protection circuit.

  2. Circuit architecture derivation starting from a formal requirements specification considering a DDS as example

    Science.gov (United States)

    Garbe, H.; Richter, R.; Jentschel, H.-J.

    2004-05-01

    Based on a formal specification of a direct digital synthesis (DDS) and assuming the availability of a set of possible circuit architectures we derive a customised system configuration. e calculate the design parameters that can be used for the specification to synthesise the circuit components. We show how the derived parameters and the selected IC technology influence the complexity of the circuit implementation.

  3. Potential for integrated optical circuits in advanced aircraft with fiber optic control and monitoring systems

    Science.gov (United States)

    Baumbick, Robert J.

    1991-02-01

    Fiber optic technology is expected to be used in future advanced weapons platforms as well as commercial aerospace applications. Fiber optic waveguides will be used to transmit noise free high speed data between a multitude of computers as well as audio and video information to the flight crew. Passive optical sensors connected to control computers with optical fiber interconnects will serve both control and monitoring functions. Implementation of fiber optic technology has already begun. Both the military and NASA have several programs in place. A cooperative program called FOCSI (Fiber Optic Control System Integration) between NASA Lewis and the NAVY to build environmentally test and flight demonstrate sensor systems for propul sion and flight control systems is currently underway. Integrated Optical Circuits (IOC''s) are also being given serious consideration for use in advanced aircraft sys tems. IOC''s will result in miniaturization and localization of components to gener ate detect optical signals and process them for use by the control computers. In some complex systems IOC''s may be required to perform calculations optically if the technology is ready replacing some of the electronic systems used today. IOC''s are attractive because they will result in rugged components capable of withstanding severe environments in advanced aerospace vehicles. Manufacturing technology devel oped for microelectronic integrated circuits applied to IOC''s will result in cost effective manufacturing. This paper reviews the current FOCSI program and describes the role of IOC''s in FOCSI applications.

  4. DMILL circuits. The hardened electronics decuples its performances

    International Nuclear Information System (INIS)

    Anon.

    1998-01-01

    Thanks to the DMILL (mixed logic-linear hardening) technology under development at the CEA, MHS, a French company specialized in the fabrication of integrated circuits now produces hardened electronic circuits ten times more resistant to radiations than its competitors. Outside the initial market (several thousands of circuits for the LHC particle accelerator of Geneva), a broad choice of applications is opened to this technology: national defense, space, civil nuclear and medical engineering, and high temperature applications. Short paper. (J.S.)

  5. Microwave integrated circuit mask design, using computer aided microfilm techniques

    Energy Technology Data Exchange (ETDEWEB)

    Reymond, J.M.; Batliwala, E.R.; Ajose, S.O.

    1977-01-01

    This paper examines the possibility of using a computer interfaced with a precision film C.R.T. information retrieval system, to produce photomasks suitable for the production of microwave integrated circuits.

  6. Characterization of 6H-SiC JFET Integrated Circuits Over A Broad Temperature Range from -150 C to +500 C

    Science.gov (United States)

    Neudeck, Philip G.; Krasowski, Michael J.; Chen, Liang-Yu; Prokop, Norman F.

    2009-01-01

    The NASA Glenn Research Center has previously reported prolonged stable operation of simple prototype 6H-SiC JFET integrated circuits (logic gates and amplifier stages) for thousands of hours at +500 C. This paper experimentally investigates the ability of these 6H-SiC JFET devices and integrated circuits to also function at cold temperatures expected to arise in some envisioned applications. Prototype logic gate ICs experimentally demonstrated good functionality down to -125 C without changing circuit input voltages. Cascaded operation of gates at cold temperatures was verified by externally wiring gates together to form a 3-stage ring oscillator. While logic gate output voltages exhibited little change across the broad temperature range from -125 C to +500 C, the change in operating frequency and power consumption of these non-optimized logic gates as a function of temperature was much larger and tracked JFET channel conduction properties.

  7. Apparatus and method for defect testing of integrated circuits

    Science.gov (United States)

    Cole, Jr., Edward I.; Soden, Jerry M.

    2000-01-01

    An apparatus and method for defect and failure-mechanism testing of integrated circuits (ICs) is disclosed. The apparatus provides an operating voltage, V.sub.DD, to an IC under test and measures a transient voltage component, V.sub.DDT, signal that is produced in response to switching transients that occur as test vectors are provided as inputs to the IC. The amplitude or time delay of the V.sub.DDT signal can be used to distinguish between defective and defect-free (i.e. known good) ICs. The V.sub.DDT signal is measured with a transient digitizer, a digital oscilloscope, or with an IC tester that is also used to input the test vectors to the IC. The present invention has applications for IC process development, for the testing of ICs during manufacture, and for qualifying ICs for reliability.

  8. Wireless Neural Recording With Single Low-Power Integrated Circuit

    Science.gov (United States)

    Harrison, Reid R.; Kier, Ryan J.; Chestek, Cynthia A.; Gilja, Vikash; Nuyujukian, Paul; Ryu, Stephen; Greger, Bradley; Solzbacher, Florian; Shenoy, Krishna V.

    2010-01-01

    We present benchtop and in vivo experimental results from an integrated circuit designed for wireless implantable neural recording applications. The chip, which was fabricated in a commercially available 0.6-μm 2P3M BiCMOS process, contains 100 amplifiers, a 10-bit analog-to-digital converter (ADC), 100 threshold-based spike detectors, and a 902–928 MHz frequency-shift-keying (FSK) transmitter. Neural signals from a selected amplifier are sampled by the ADC at 15.7 kSps and telemetered over the FSK wireless data link. Power, clock, and command signals are sent to the chip wirelessly over a 2.765-MHz inductive (coil-to-coil) link. The chip is capable of operating with only two off-chip components: a power/command receiving coil and a 100-nF capacitor. PMID:19497825

  9. A novel readout integrated circuit for ferroelectric FPA detector

    Science.gov (United States)

    Bai, Piji; Li, Lihua; Ji, Yulong; Zhang, Jia; Li, Min; Liang, Yan; Hu, Yanbo; Li, Songying

    2017-11-01

    Uncooled infrared detectors haves some advantages such as low cost light weight low power consumption, and superior reliability, compared with cryogenically cooled ones Ferroelectric uncooled focal plane array(FPA) are being developed for its AC response and its high reliability As a key part of the ferroelectric assembly the ROIC determines the performance of the assembly. A top-down design model for uncooled ferroelectric readout integrated circuit(ROIC) has been developed. Based on the optical thermal and electrical properties of the ferroelectric detector the RTIA readout integrated circuit is designed. The noise bandwidth of RTIA readout circuit has been developed and analyzed. A novel high gain amplifier, a high pass filter and a low pass filter circuits are designed on the ROIC. In order to improve the ferroelectric FPA package performance and decrease of package cost a temperature sensor is designed on the ROIC chip At last the novel RTIA ROIC is implemented on 0.6μm 2P3M CMOS silicon techniques. According to the experimental chip test results the temporal root mean square(RMS)noise voltage is about 1.4mV the sensitivity of the on chip temperature sensor is 0.6 mV/K from -40°C to 60°C the linearity performance of the ROIC chip is better than 99% Based on the 320×240 RTIA ROIC, a 320×240 infrared ferroelectric FPA is fabricated and tested. Test results shows that the 320×240 RTIA ROIC meets the demand of infrared ferroelectric FPA.

  10. Review of Polynomial Chaos-Based Methods for Uncertainty Quantification in Modern Integrated Circuits

    OpenAIRE

    Arun Kaintura; Tom Dhaene; Domenico Spina

    2018-01-01

    Advances in manufacturing process technology are key ensembles for the production of integrated circuits in the sub-micrometer region. It is of paramount importance to assess the effects of tolerances in the manufacturing process on the performance of modern integrated circuits. The polynomial chaos expansion has emerged as a suitable alternative to standard Monte Carlo-based methods that are accurate, but computationally cumbersome. This paper provides an overview of the most recent developm...

  11. Testing Fixture For Microwave Integrated Circuits

    Science.gov (United States)

    Romanofsky, Robert; Shalkhauser, Kurt

    1989-01-01

    Testing fixture facilitates radio-frequency characterization of microwave and millimeter-wave integrated circuits. Includes base onto which two cosine-tapered ridge waveguide-to-microstrip transitions fastened. Length and profile of taper determined analytically to provide maximum bandwidth and minimum insertion loss. Each cosine taper provides transformation from high impedance of waveguide to characteristic impedance of microstrip. Used in conjunction with automatic network analyzer to provide user with deembedded scattering parameters of device under test. Operates from 26.5 to 40.0 GHz, but operation extends to much higher frequencies.

  12. Electronic meter with custom integrated circuit for electric energy measurement; Medidor eletronico de energia eletrica com circuito integrado dedicado

    Energy Technology Data Exchange (ETDEWEB)

    Caldas, Roberto Pereira

    1990-04-01

    The design and implementation of an electrical energy electronic meter for operation at low voltages, according to two steps of development carried out in Centro de Pesquisas de Energia Eletrica - CEPEL is described. In the first step, an electronic meter with discrete commercial components has been developed, in order to demonstrate to the Brazilian power suppliers the feasibility of such a device for electrical energy metering and charging. The second step was constituted by the design of an integrated circuit, aiming the reduction of the cost of the meter as well as the enhancement of its reliability. Several techniques of electrical energy measurement are presented. The meter with discrete components makes use of a time division multiplier (TDM), in order to determine the active power in the load. Voltage and current levels have been reduced through the use of voltage and current sensors compatible with the TDM's inputs. A V-F converter employing continuos integration, has been used for the determination of the energy consumed by the load through the integration of the TDM's output signal. Most of the discrete components of the meter have been replaced by the dedicated integrated circuit. The TDM has remained essentially the same, but the V-F converter has been changed into a dual-slope one, which is more adequate for implementation in a single chip. The tests performed with the prototypes of the meter including both the meter with discrete components and the meter with the custom-made integrated circuit have presented measurement errors of less the 0,2 %. The initial goal, according to Brazilian specifications of electromechanical meters and international specifications for electronic meters, was 1 %. (author)

  13. Electronic meter with custom integrated circuit for electric energy measurement; Medidor eletronico de energia eletrica com circuito integrado dedicado

    Energy Technology Data Exchange (ETDEWEB)

    Caldas, Roberto Pereira

    1990-04-01

    The design and implementation of an electrical energy electronic meter for operation at low voltages, according to two steps of development carried out in Centro de Pesquisas de Energia Eletrica - CEPEL is described. In the first step, an electronic meter with discrete commercial components has been developed, in order to demonstrate to the Brazilian power suppliers the feasibility of such a device for electrical energy metering and charging. The second step was constituted by the design of an integrated circuit, aiming the reduction of the cost of the meter as well as the enhancement of its reliability. Several techniques of electrical energy measurement are presented. The meter with discrete components makes use of a time division multiplier (TDM), in order to determine the active power in the load. Voltage and current levels have been reduced through the use of voltage and current sensors compatible with the TDM's inputs. A V-F converter employing continuos integration, has been used for the determination of the energy consumed by the load through the integration of the TDM's output signal. Most of the discrete components of the meter have been replaced by the dedicated integrated circuit. The TDM has remained essentially the same, but the V-F converter has been changed into a dual-slope one, which is more adequate for implementation in a single chip. The tests performed with the prototypes of the meter including both the meter with discrete components and the meter with the custom-made integrated circuit have presented measurement errors of less the 0,2 %. The initial goal, according to Brazilian specifications of electromechanical meters and international specifications for electronic meters, was 1 %. (author)

  14. Implantable neurotechnologies: bidirectional neural interfaces--applications and VLSI circuit implementations.

    Science.gov (United States)

    Greenwald, Elliot; Masters, Matthew R; Thakor, Nitish V

    2016-01-01

    A bidirectional neural interface is a device that transfers information into and out of the nervous system. This class of devices has potential to improve treatment and therapy in several patient populations. Progress in very large-scale integration has advanced the design of complex integrated circuits. System-on-chip devices are capable of recording neural electrical activity and altering natural activity with electrical stimulation. Often, these devices include wireless powering and telemetry functions. This review presents the state of the art of bidirectional circuits as applied to neuroprosthetic, neurorepair, and neurotherapeutic systems.

  15. Fabrication-process-induced variations of Nb/Al/AlOx/Nb Josephson junctions in superconductor integrated circuits

    International Nuclear Information System (INIS)

    Tolpygo, Sergey K; Amparo, Denis

    2010-01-01

    Currently, superconductor digital integrated circuits fabricated at HYPRES, Inc. can operate at clock frequencies approaching 40 GHz. The circuits present multilayered structures containing tens of thousands of Nb/Al/AlO x /Nb Josephson junctions (JJs) of various sizes interconnected by four Nb wiring layers, resistors, and other circuit elements. In order to be fully operational, the integrated circuits should be fabricated such that the critical currents of the JJs are within the tight design margins and the proper relationships between the critical currents of JJs of different sizes are preserved. We present experimental data and discuss mechanisms of process-induced variations of the critical current and energy gap of Nb/Al/AlO x /Nb JJs in integrated circuits. We demonstrate that the Josephson critical current may depend on the type and area of circuit elements connected to the junction, on the circuit pattern, and on the step in the fabrication process at which the connection is made. In particular, we discuss the influence of (a) the junction base electrode connection to the ground plane, (b) the junction counter electrode connection to the ground plane, and (c) the counter electrode connection to the Ti/Au or Ti/Pd/Au contact pads by Nb wiring. We show that the process-induced changes of the properties of Nb/Al/AlO x /Nb junctions are caused by migration of impurity atoms (hydrogen) between the different layers comprising the integrated circuits.

  16. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    International Nuclear Information System (INIS)

    Arefin, Md Shamsul; Redoute, Jean-Michel; Rasit Yuce, Mehmet; Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian

    2014-01-01

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  17. A microfabricated fringing field capacitive pH sensor with an integrated readout circuit

    Energy Technology Data Exchange (ETDEWEB)

    Arefin, Md Shamsul, E-mail: md.arefin@monash.edu; Redoute, Jean-Michel; Rasit Yuce, Mehmet [Electrical and Computer Systems Engineering, Monash University, Melbourne (Australia); Bulut Coskun, M.; Alan, Tuncay; Neild, Adrian [Mechanical and Aerospace Engineering, Monash University, Melbourne (Australia)

    2014-06-02

    This work presents a microfabricated fringe-field capacitive pH sensor using interdigitated electrodes and an integrated modulation-based readout circuit. The changes in capacitance of the sensor result from the permittivity changes due to pH variations and are converted to frequency shifts using a crossed-coupled voltage controlled oscillator readout circuit. The shift in resonant frequency of the readout circuit is 30.96 MHz for a change in pH of 1.0–5.0. The sensor can be used for the measurement of low pH levels, such as gastric acid, and can be integrated with electronic pills. The measurement results show high repeatability, low noise, and a stable output.

  18. Modeling the cosmic-ray-induced soft-error rate in integrated circuits: An overview

    International Nuclear Information System (INIS)

    Srinivasan, G.R.

    1996-01-01

    This paper is an overview of the concepts and methodologies used to predict soft-error rates (SER) due to cosmic and high-energy particle radiation in integrated circuit chips. The paper emphasizes the need for the SER simulation using the actual chip circuit model which includes device, process, and technology parameters as opposed to using either the discrete device simulation or generic circuit simulation that is commonly employed in SER modeling. Concepts such as funneling, event-by-event simulation, nuclear history files, critical charge, and charge sharing are examined. Also discussed are the relative importance of elastic and inelastic nuclear collisions, rare event statistics, and device vs. circuit simulations. The semi-empirical methodologies used in the aerospace community to arrive at SERs [also referred to as single-event upset (SEU) rates] in integrated circuit chips are reviewed. This paper is one of four in this special issue relating to SER modeling. Together, they provide a comprehensive account of this modeling effort, which has resulted in a unique modeling tool called the Soft-Error Monte Carlo Model, or SEMM

  19. Application of Memristors in Microwave Passive Circuits

    Directory of Open Access Journals (Sweden)

    M.Potrebic

    2015-06-01

    Full Text Available The recent implementation of the fourth fundamental electric circuit element, the memristor, opened new vistas in many fields of engineering applications. In this paper, we explore several RF/microwave passive circuits that might benefit from the memristor salient characteristics. We consider a power divider, coupled resonator bandpass filters, and a low-reflection quasi-Gaussian lowpass filter with lossy elements. We utilize memristors as configurable linear resistors and we propose memristor-based bandpass filters that feature suppression of parasitic frequency pass bands and widening of the desired rejection band. The simulations are performed in the time domain, using LTspice, and the RF/microwave circuits under consideration are modeled by ideal elements available in LTspice.

  20. Evolvable designs of experiments applications for circuits

    CERN Document Server

    Iordache, Octavian

    2009-01-01

    Adopting a groundbreaking approach, the highly regarded author shows how to design methods for planning increasingly complex experiments. He begins with a brief introduction to standard quality methods and the technology in standard electric circuits. The book then gives numerous examples of how to apply the proposed methodology in a series of real-life case studies. Although these case studies are taken from the printed circuit board industry, the methods are equally applicable to other fields of engineering.

  1. Silicon photonic integrated circuit swept-source optical coherence tomography receiver with dual polarization, dual balanced, in-phase and quadrature detection.

    Science.gov (United States)

    Wang, Zhao; Lee, Hsiang-Chieh; Vermeulen, Diedrik; Chen, Long; Nielsen, Torben; Park, Seo Yeon; Ghaemi, Allan; Swanson, Eric; Doerr, Chris; Fujimoto, James

    2015-07-01

    Optical coherence tomography (OCT) is a widely used three-dimensional (3D) optical imaging method with many biomedical and non-medical applications. Miniaturization, cost reduction, and increased functionality of OCT systems will be critical for future emerging clinical applications. We present a silicon photonic integrated circuit swept-source OCT (SS-OCT) coherent receiver with dual polarization, dual balanced, in-phase and quadrature (IQ) detection. We demonstrate multiple functional capabilities of IQ polarization resolved detection including: complex-conjugate suppressed full-range OCT, polarization diversity detection, and polarization-sensitive OCT. To our knowledge, this is the first demonstration of a silicon photonic integrated receiver for OCT. The integrated coherent receiver provides a miniaturized, low-cost solution for SS-OCT, and is also a key step towards a fully integrated high speed SS-OCT system with good performance and multi-functional capabilities. With further performance improvement and cost reduction, photonic integrated technology promises to greatly increase penetration of OCT systems in existing applications and enable new applications.

  2. 75 FR 49524 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2010-08-13

    ... the United States after importation of certain integrated circuits, chipsets, and products containing... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-709] In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Media Players, and Cameras; Notice...

  3. 76 FR 34101 - In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2011-06-10

    ... within the United States after importation of certain integrated circuits, chipsets, and products... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-709] In the Matter of Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Media Players, and Cameras; Notice...

  4. 75 FR 65654 - In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including...

    Science.gov (United States)

    2010-10-26

    ... within the United States after importation of certain integrated circuits, chipsets, and products... INTERNATIONAL TRADE COMMISSION [Investigation No. 337-TA-709] In the Matter of: Certain Integrated Circuits, Chipsets, and Products Containing Same Including Televisions, Media Players, and Cameras; Notice...

  5. Novel technique for reliability testing of silicon integrated circuits

    NARCIS (Netherlands)

    Le Minh, P.; Wallinga, Hans; Woerlee, P.H.; van den Berg, Albert; Holleman, J.

    2001-01-01

    We propose a simple, inexpensive technique with high resolution to identify the weak spots in integrated circuits by means of a non-destructive photochemical process in which photoresist is used as the photon detection tool. The experiment was done to localize the breakdown link of thin silicon

  6. Neural Circuit to Integrate Opposing Motions in the Visual Field.

    Science.gov (United States)

    Mauss, Alex S; Pankova, Katarina; Arenz, Alexander; Nern, Aljoscha; Rubin, Gerald M; Borst, Alexander

    2015-07-16

    When navigating in their environment, animals use visual motion cues as feedback signals that are elicited by their own motion. Such signals are provided by wide-field neurons sampling motion directions at multiple image points as the animal maneuvers. Each one of these neurons responds selectively to a specific optic flow-field representing the spatial distribution of motion vectors on the retina. Here, we describe the discovery of a group of local, inhibitory interneurons in the fruit fly Drosophila key for filtering these cues. Using anatomy, molecular characterization, activity manipulation, and physiological recordings, we demonstrate that these interneurons convey direction-selective inhibition to wide-field neurons with opposite preferred direction and provide evidence for how their connectivity enables the computation required for integrating opposing motions. Our results indicate that, rather than sharpening directional selectivity per se, these circuit elements reduce noise by eliminating non-specific responses to complex visual information. Copyright © 2015 Elsevier Inc. All rights reserved.

  7. Monolithic Microwave Integrated Circuit (MMIC) Phased Array Demonstrated With ACTS

    Science.gov (United States)

    1996-01-01

    Monolithic Microwave Integrated Circuit (MMIC) arrays developed by the NASA Lewis Research Center and the Air Force Rome Laboratory were demonstrated in aeronautical terminals and in mobile or fixed Earth terminals linked with NASA's Advanced Communications Technology Satellite (ACTS). Four K/Ka-band experimental arrays were demonstrated between May 1994 and May 1995. Each array had GaAs MMIC devices at each radiating element for electronic beam steering and distributed power amplification. The 30-GHz transmit array used in uplinks to ACTS was developed by Lewis and Texas Instruments. The three 20-GHz receive arrays used in downlinks from ACTS were developed in cooperation with the Air Force Rome Laboratory, taking advantage of existing Air Force integrated-circuit, active-phased-array development contracts with the Boeing Company and Lockheed Martin Corporation. Four demonstrations, each related to an application of high interest to both commercial and Department of Defense organizations, were conducted. The location, type of link, and the data rate achieved for each of the applications is shown. In one demonstration-- an aeronautical terminal experiment called AERO-X--a duplex voice link between an aeronautical terminal on the Lewis Learjet and ACTS was achieved. Two others demonstrated duplex voice links (and in one case, interactive video links as well) between ACTS and an Army high-mobility, multipurpose wheeled vehicle (HMMWV, or "humvee"). In the fourth demonstration, the array was on a fixed mount and was electronically steered toward ACTS. Lewis served as project manager for all demonstrations and as overall system integrator. Lewis engineers developed the array system including a controller for open-loop tracking of ACTS during flight and HMMWV motion, as well as a laptop data display and recording system used in all demonstrations. The Jet Propulsion Laboratory supported the AERO-X program, providing elements of the ACTS Mobile Terminal. The successful

  8. Circuit and interconnect design for high bit-rate applications

    NARCIS (Netherlands)

    Veenstra, H.

    2006-01-01

    This thesis presents circuit and interconnect design techniques and design flows that address the most difficult and ill-defined aspects of the design of ICs for high bit-rate applications. Bottlenecks in interconnect design, circuit design and on-chip signal distribution for high bit-rate

  9. Physical and electrical characterization of corundum substrates and epitaxial silicon layers in view of fabricating integrated circuits

    International Nuclear Information System (INIS)

    Trilhe, J.; Legal, H.; Rolland, G.

    1975-01-01

    The S.O.S. technology (silicon on insulating substrate) allows compact, radiation hard, fast integrated circuits to be fabricated. It is noticeable that complex integrated circuits on corundum substrates obtained with various fabrication processes have various electrical characteristics. Possible correlations between the macroscopic defects of the substrate and the electrical characteristics of the circuit were investigated [fr

  10. Thermoreflectance temperature imaging of integrated circuits: calibration technique and quantitative comparison with integrated sensors and simulations

    International Nuclear Information System (INIS)

    Tessier, G; Polignano, M-L; Pavageau, S; Filloy, C; Fournier, D; Cerutti, F; Mica, I

    2006-01-01

    Camera-based thermoreflectance microscopy is a unique tool for high spatial resolution thermal imaging of working integrated circuits. However, a calibration is necessary to obtain quantitative temperatures on the complex surface of integrated circuits. The spatial and temperature resolutions reached by thermoreflectance are excellent (360 nm and 2.5 x 10 -2 K in 1 min here), but the precision is more difficult to assess, notably due to the lack of comparable thermal techniques at submicron scales. We propose here a Peltier element control of the whole package temperature in order to obtain calibration coefficients simultaneously on several materials visible on the surface of the circuit. Under high magnifications, movements associated with thermal expansion are corrected using a piezo electric displacement and a software image shift. This calibration method has been validated by comparison with temperatures measured using integrated thermistors and diodes and by a finite volume simulation. We show that thermoreflectance measurements agree within a precision of ±2.3% with the on-chip sensors measurements. The diode temperature is found to underestimate the actual temperature of the active area by almost 70% due to the thermal contact of the diode with the substrate, acting as a heat sink

  11. Photonic crystal ring resonator based optical filters for photonic integrated circuits

    International Nuclear Information System (INIS)

    Robinson, S.

    2014-01-01

    In this paper, a two Dimensional (2D) Photonic Crystal Ring Resonator (PCRR) based optical Filters namely Add Drop Filter, Bandpass Filter, and Bandstop Filter are designed for Photonic Integrated Circuits (PICs). The normalized output response of the filters is obtained using 2D Finite Difference Time Domain (FDTD) method and the band diagram of periodic and non-periodic structure is attained by Plane Wave Expansion (PWE) method. The size of the device is minimized from a scale of few tens of millimeters to the order of micrometers. The overall size of the filters is around 11.4 μm × 11.4 μm which is highly suitable of photonic integrated circuits

  12. Printed circuits and their applications: Which way forward?

    Science.gov (United States)

    Cantatore, E.

    2015-09-01

    The continuous advancements in printed electronics make nowadays feasible the design of printed circuits which enable meaningful applications. Examples include ultra-low cost sensors embedded in food packaging, large-area sensing surfaces and biomedical assays. This paper offers an overview of state-of-the-art digital and analog circuit blocks, manufactured with a printed complementary organic TFT technology. An analog to digital converter and an RFID tag implemented exploiting these building blocks are also described. The main remaining drawbacks of the printed technology described are identified, and new approaches to further improve the state of the art, enabling more innovative applications are discussed.

  13. Heat sinking of highly integrated photonic and electronic circuits

    NARCIS (Netherlands)

    van Rijn, M.B.J.; Smit, M.K.

    2017-01-01

    Dense integration of photonic and electronic circuits poses high requirements on thermal management. In this paper we present analysis of temperature distributions in PICs in InP membranes on top of a BiCMOS chip, which contain hot spots in both the photonic and the electronic layer (lasers, optical

  14. Plasma Etching for Failure Analysis of Integrated Circuit Packages

    NARCIS (Netherlands)

    Tang, J.; Schelen, J.B.J.; Beenakker, C.I.M.

    2011-01-01

    Plastic integrated circuit packages with copper wire bonds are decapsulated by a Microwave Induced Plasma system. Improvements on microwave coupling of the system are achieved by frequency tuning and antenna modification. Plasmas with a mixture of O2 and CF4 showed a high etching rate around 2

  15. Split-cross-bridge resistor for testing for proper fabrication of integrated circuits

    Science.gov (United States)

    Buehler, M. G. (Inventor)

    1985-01-01

    An electrical testing structure and method is described whereby a test structure is fabricated on a large scale integrated circuit wafer along with the circuit components and has a van der Pauw cross resistor in conjunction with a bridge resistor and a split bridge resistor, the latter having two channels each a line width wide, corresponding to the line width of the wafer circuit components, and with the two channels separated by a space equal to the line spacing of the wafer circuit components. The testing structure has associated voltage and current contact pads arranged in a two by four array for conveniently passing currents through the test structure and measuring voltages at appropriate points to calculate the sheet resistance, line width, line spacing, and line pitch of the circuit components on the wafer electrically.

  16. Superconductor-insulator-normal-conductor-insulator-superconductor (Nb/Al{sub x}O{sub y}/Al/Al{sub x}O{sub y}/Nb) process development for integrated circuit applications

    Energy Technology Data Exchange (ETDEWEB)

    Balashov, D.; Buchholz, F.M.; Schulze, H.; Khabipov, M.I.; Kessel, W.; Niemeyer, J. [Physikalisch-Technische Bundesanstalt, Braunschweig (Germany)

    1998-12-01

    The paper reports on recent developments in a new technology process in LTS implementation to fabricate intrinsically shunted tunnel junctions. The process has been realized in SINIS Nb/Al{sub x}O{sub y}/Al/Al{sub x}O{sub y}/Nb multilayer thin-film technology. In various test series, circuits containing a large variety of single junctions and junction arrays of different contact areas and sizes were fabricated and measured. By variation of the oxidation parameters the fabrication process has been optimized for application in integrated circuits operating in RSFQ impulse logic. The junction parameter values realized for the critical current density j{sub c} range to up to about j{sub c} = 1000 A cm{sup -2}, those for the characteristic voltage V{sub c} to up to about V{sub c} = 230 {mu}V. The junctions show nearly non-hysteretic current-voltage characteristics; the intra-wafer parameter spread is below 10%. The junctions realized fulfil the requirements imposed for digital RSFQ circuit operation at clock frequencies in the lower GHz frequency range. (author)

  17. Design of a semi-custom integrated circuit for the SLAC SLC timing control system

    International Nuclear Information System (INIS)

    Linstadt, E.

    1984-10-01

    A semi-custom (gate array) integrated circuit has been designed for use in the SLAC Linear Collider timing and control system. The design process and SLAC's experiences during the phases of the design cycle are described. Issues concerning the partitioning of the design into semi-custom and standard components are discussed. Functional descriptions of the semi-custom integrated circuit and the timing module in which it is used are given

  18. LASER APPLICATIONS AND OTHER TOPICS IN QUANTUM ELECTRONICS: Laser-induced extreme UV radiation sources for manufacturing next-generation integrated circuits

    Science.gov (United States)

    Borisov, V. M.; Vinokhodov, A. Yu; Ivanov, A. S.; Kiryukhin, Yu B.; Mishchenko, V. A.; Prokof'ev, A. V.; Khristoforov, O. B.

    2009-10-01

    The development of high-power discharge sources emitting in the 13.5±0.135-nm spectral band is of current interest because they are promising for applications in industrial EUV (extreme ultraviolet) lithography for manufacturing integrated circuits according to technological precision standards of 22 nm and smaller. The parameters of EUV sources based on a laser-induced discharge in tin vapours between rotating disc electrodes are investigated. The properties of the discharge initiation by laser radiation at different wavelengths are established and the laser pulse parameters providing the maximum energy characteristics of the EUV source are determined. The EUV source developed in the study emits an average power of 276 W in the 13.5±0.135-nm spectral band on conversion to the solid angle 2π sr in the stationary regime at a pulse repetition rate of 3000 Hz.

  19. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    International Nuclear Information System (INIS)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A.; Bozler, Carl; Omenetto, Fiorenzo

    2015-01-01

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems

  20. Materials and fabrication sequences for water soluble silicon integrated circuits at the 90 nm node

    Energy Technology Data Exchange (ETDEWEB)

    Yin, Lan; Harburg, Daniel V.; Rogers, John A., E-mail: jrogers@illinois.edu [Department of Materials Science and Engineering, Beckman Institute for Advanced Science and Technology, and Frederick Seitz Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 S Goodwin Ave., Urbana, Illinois 61801 (United States); Bozler, Carl [Lincoln Laboratory, Massachusetts Institute of Technology, 244 Wood Street, Lexington, Massachusetts 02420 (United States); Omenetto, Fiorenzo [Department of Biomedical Engineering, Department of Physics, Tufts University, 4 Colby St., Medford, Massachusetts 02155 (United States)

    2015-01-05

    Tungsten interconnects in silicon integrated circuits built at the 90 nm node with releasable configurations on silicon on insulator wafers serve as the basis for advanced forms of water-soluble electronics. These physically transient systems have potential uses in applications that range from temporary biomedical implants to zero-waste environmental sensors. Systematic experimental studies and modeling efforts reveal essential aspects of electrical performance in field effect transistors and complementary ring oscillators with as many as 499 stages. Accelerated tests reveal timescales for dissolution of the various constituent materials, including tungsten, silicon, and silicon dioxide. The results demonstrate that silicon complementary metal-oxide-semiconductor circuits formed with tungsten interconnects in foundry-compatible fabrication processes can serve as a path to high performance, mass-produced transient electronic systems.

  1. Total Dose Effects on Bipolar Integrated Circuits at Low Temperature

    Science.gov (United States)

    Johnston, A. H.; Swimm, R. T.; Thorbourn, D. O.

    2012-01-01

    Total dose damage in bipolar integrated circuits is investigated at low temperature, along with the temperature dependence of the electrical parameters of internal transistors. Bandgap narrowing causes the gain of npn transistors to decrease far more at low temperature compared to pnp transistors, due to the large difference in emitter doping concentration. When irradiations are done at temperatures of -140 deg C, no damage occurs until devices are warmed to temperatures above -50 deg C. After warm-up, subsequent cooling shows that damage is then present at low temperature. This can be explained by the very strong temperature dependence of dispersive transport in the continuous-time-random-walk model for hole transport. For linear integrated circuits, low temperature operation is affected by the strong temperature dependence of npn transistors along with the higher sensitivity of lateral and substrate pnp transistors to radiation damage.

  2. Ka-band to L-band frequency down-conversion based on III-V-on-silicon photonic integrated circuits

    Science.gov (United States)

    Van Gasse, K.; Wang, Z.; Uvin, S.; De Deckere, B.; Mariën, J.; Thomassen, L.; Roelkens, G.

    2017-12-01

    In this work, we present the design, simulation and characterization of a frequency down-converter based on III-V-on-silicon photonic integrated circuit technology. We first demonstrate the concept using commercial discrete components, after which we demonstrate frequency conversion using an integrated mode-locked laser and integrated modulator. In our experiments, five channels in the Ka-band (27.5-30 GHz) with 500 MHz bandwidth are down-converted to the L-band (1.5 GHz). The breadboard demonstration shows a conversion efficiency of - 20 dB and a flat response over the 500 MHz bandwidth. The simulation of a fully integrated circuit indicates that a positive conversion gain can be obtained on a millimeter-sized photonic integrated circuit.

  3. Continuous surveillance of reactor coolant circuit integrity

    International Nuclear Information System (INIS)

    1986-01-01

    Continuous surveillance is important to assuring the integrity of a reactor coolant circuit. It can give pre-warning of structural degradation and indicate where off-line inspection should be focussed. These proceedings describe the state of development of several techniques which may be used. These involve measuring structural vibration, core neutron noise, acoustic emission from cracks, coolant leakage, or operating parameters such as coolant temperature and pressure. Twenty three papers have been abstracted and indexed separately for inclusion in the data base

  4. Minimizing time for test in integrated circuit

    OpenAIRE

    Andonova, A. S.; Dimitrov, D. G.; Atanasova, N. G.

    2004-01-01

    The cost for testing integrated circuits represents a growing percentage of the total cost for their production. The former strictly depends on the length of the test session, and its reduction has been the target of many efforts in the past. This paper proposes a new method for reducing the test length by adopting a new architecture and exploiting an evolutionary optimisation algorithm. A prototype of the proposed approach was tested on 1SCAS standard benchmarks and theexperimental results s...

  5. Operational amplifier circuits analysis and design

    CERN Document Server

    Nelson, J C C

    1995-01-01

    This book, a revised and updated version of the author's Basic Operational Amplifiers (Butterworths 1986), enables the non-specialist to make effective use of readily available integrated circuit operational amplifiers for a range of applications, including instrumentation, signal generation and processing.It is assumed the reader has a background in the basic techniques of circuit analysis, particularly the use of j notation for reactive circuits, with a corresponding level of mathematical ability. The underlying theory is explained with sufficient but not excessive, detail. A range of compu

  6. The neural circuits of innate fear: detection, integration, action, and memorization

    Science.gov (United States)

    Silva, Bianca A.; Gross, Cornelius T.

    2016-01-01

    How fear is represented in the brain has generated a lot of research attention, not only because fear increases the chances for survival when appropriately expressed but also because it can lead to anxiety and stress-related disorders when inadequately processed. In this review, we summarize recent progress in the understanding of the neural circuits processing innate fear in rodents. We propose that these circuits are contained within three main functional units in the brain: a detection unit, responsible for gathering sensory information signaling the presence of a threat; an integration unit, responsible for incorporating the various sensory information and recruiting downstream effectors; and an output unit, in charge of initiating appropriate bodily and behavioral responses to the threatful stimulus. In parallel, the experience of innate fear also instructs a learning process leading to the memorization of the fearful event. Interestingly, while the detection, integration, and output units processing acute fear responses to different threats tend to be harbored in distinct brain circuits, memory encoding of these threats seems to rely on a shared learning system. PMID:27634145

  7. Set of CAMAC modules on the base of large integrated circuits for an accelerator synchronization system

    International Nuclear Information System (INIS)

    Glejbman, Eh.M.; Pilyar, N.V.

    1986-01-01

    Parameters of functional moduli in the CAMAC standard developed for accelerator synchronization system are presented. They comprise BZN-8K and BZ-8K digital delay circuits, timing circuit and pulse selection circuit. In every module 3 large integral circuits of KR 580 VI53 type programmed timer, circuits of the given system bus bar interface with bus bars of crate, circuits of data recording control, 2 peripheric storage devices, circuits of initial regime setting, input and output shapers, circuits of installation and removal of blocking in channels are used

  8. Circuit for Communication Over Power Lines

    Science.gov (United States)

    Krasowski, Michael J.; Prokop, Normal F.; Greer, Lawrence C., III; Nappier, Jennifer

    2011-01-01

    Many distributed systems share common sensors and instruments along with a common power line supplying current to the system. A communication technique and circuit has been developed that allows for the simple inclusion of an instrument, sensor, or actuator node within any system containing a common power bus. Wherever power is available, a node can be added, which can then draw power for itself, its associated sensors, and actuators from the power bus all while communicating with other nodes on the power bus. The technique modulates a DC power bus through capacitive coupling using on-off keying (OOK), and receives and demodulates the signal from the DC power bus through the same capacitive coupling. The circuit acts as serial modem for the physical power line communication. The circuit and technique can be made of commercially available components or included in an application specific integrated circuit (ASIC) design, which allows for the circuit to be included in current designs with additional circuitry or embedded into new designs. This device and technique moves computational, sensing, and actuation abilities closer to the source, and allows for the networking of multiple similar nodes to each other and to a central processor. This technique also allows for reconfigurable systems by adding or removing nodes at any time. It can do so using nothing more than the in situ power wiring of the system.

  9. Graphene-on-silicon hybrid plasmonic-photonic integrated circuits.

    Science.gov (United States)

    Xiao, Ting-Hui; Cheng, Zhenzhou; Goda, Keisuke

    2017-06-16

    Graphene surface plasmons (GSPs) have shown great potential in biochemical sensing, thermal imaging, and optoelectronics. To excite GSPs, several methods based on the near-field optical microscope and graphene nanostructures have been developed in the past few years. However, these methods suffer from their bulky setups and low GSP-excitation efficiency due to the short interaction length between free-space vertical excitation light and the atomic layer of graphene. Here we present a CMOS-compatible design of graphene-on-silicon hybrid plasmonic-photonic integrated circuits that achieve the in-plane excitation of GSP polaritons as well as localized surface plasmon (SP) resonance. By employing a suspended membrane slot waveguide, our design is able to excite GSP polaritons on a chip. Moreover, by utilizing a graphene nanoribbon array, we engineer the transmission spectrum of the waveguide by excitation of localized SP resonance. Our theoretical and computational study paves a new avenue to enable, modulate, and monitor GSPs on a chip, potentially applicable for the development of on-chip electro-optic devices.

  10. PETRIC - A positron emission tomography readout integrated circuit

    Energy Technology Data Exchange (ETDEWEB)

    Pedrali-Noy, Marzio; Gruber, Gregory; Krieger, Bradley; Mandelli, Emmanuele; Meddeler, Gerrit; Moses, William; Rosso, Valeria

    2000-11-05

    We present architecture, critical design issues and performance measurements of PETRIC, a 64-channel mixed signal front-end integrated circuit (IC) for reading out a photodiode (PD) array coupled with LSO scintillator crystals for a medical imaging application (PET). Each channel consists of a low noise charge sensitive pre-amplifier (CSA), an RC-CR pulse shaper and a winner-take-all (WTA) multiplexer that selects the channel with the largest input signal. Triggered by an external timing signal, a switch opens and a capacitor stores the peak voltage of the winner channel. The shaper rise and fall times are adjustable by means of external current inputs over a continuous range of 0.7 (mu)s to 9 (mu)s. Power consumption is 5.4 mW per channel, measured Equivalent Noise Charge (ENC) at 1 (mu)s peaking time. Zero leakage current is 33 rms electrons plus 7.3 rms electrons per pF of input capacitance. Design is fabricated in 0.5 (mu)m 3.3V CMOS technology.

  11. Temporal integration and 1/f power scaling in a circuit model of cerebellar interneurons.

    Science.gov (United States)

    Maex, Reinoud; Gutkin, Boris

    2017-07-01

    Inhibitory interneurons interconnected via electrical and chemical (GABA A receptor) synapses form extensive circuits in several brain regions. They are thought to be involved in timing and synchronization through fast feedforward control of principal neurons. Theoretical studies have shown, however, that whereas self-inhibition does indeed reduce response duration, lateral inhibition, in contrast, may generate slow response components through a process of gradual disinhibition. Here we simulated a circuit of interneurons (stellate and basket cells) of the molecular layer of the cerebellar cortex and observed circuit time constants that could rise, depending on parameter values, to >1 s. The integration time scaled both with the strength of inhibition, vanishing completely when inhibition was blocked, and with the average connection distance, which determined the balance between lateral and self-inhibition. Electrical synapses could further enhance the integration time by limiting heterogeneity among the interneurons and by introducing a slow capacitive current. The model can explain several observations, such as the slow time course of OFF-beam inhibition, the phase lag of interneurons during vestibular rotation, or the phase lead of Purkinje cells. Interestingly, the interneuron spike trains displayed power that scaled approximately as 1/ f at low frequencies. In conclusion, stellate and basket cells in cerebellar cortex, and interneuron circuits in general, may not only provide fast inhibition to principal cells but also act as temporal integrators that build a very short-term memory. NEW & NOTEWORTHY The most common function attributed to inhibitory interneurons is feedforward control of principal neurons. In many brain regions, however, the interneurons are densely interconnected via both chemical and electrical synapses but the function of this coupling is largely unknown. Based on large-scale simulations of an interneuron circuit of cerebellar cortex, we

  12. Sensors, Circuits, and Satellites - NGSS at it's best: the integration of three dimensions with NASA science

    Science.gov (United States)

    Butcher, G. J.; Roberts-Harris, D.

    2013-12-01

    A set of innovative classroom lessons were developed based on informal learning activities in the 'Sensors, Circuits, and Satellites' kit manufactured by littleBits™ Electronics that are designed to lead students through a logical science content storyline about energy using sound and light and fully implements an integrated approach to the three dimensions of the Next Generation of Science Standards (NGSS). This session will illustrate the integration of NGSS into curriculum by deconstructing lesson design to parse out the unique elements of the 3 dimensions of NGSS. We will demonstrate ways in which we have incorporated the NGSS as we believe they were intended. According to the NGSS, 'The real innovation in the NGSS is the requirement that students are required to operate at the intersection of practice, content, and connection. Performance expectations are the right way to integrate the three dimensions. It provides specificity for educators, but it also sets the tone for how science instruction should look in classrooms. (p. 3). The 'Sensors, Circuits, and Satellites' series of lessons accomplishes this by going beyond just focusing on the conceptual knowledge (the disciplinary core ideas) - traditionally approached by mapping lessons to standards. These lessons incorporate the other 2 dimensions -cross-cutting concepts and the 8-practices of Sciences and Engineering-via an authentic and exciting connection to NASA science, thus implementing the NGSS in the way they were designed to be used: practices and content with the crosscutting concepts. When the NGSS are properly integrated, students are engaged in science and engineering content through the coupling of practice, content and connection. In the past, these two dimensions have been separated as distinct entities. We know now that coupling content and practices better demonstrates what goes on in real world science and engineering. We set out to accomplish what is called for in NGSS by integrating these

  13. Advanced field-solver techniques for RC extraction of integrated circuits

    CERN Document Server

    Yu, Wenjian

    2014-01-01

    Resistance and capacitance (RC) extraction is an essential step in modeling the interconnection wires and substrate coupling effect in nanometer-technology integrated circuits (IC). The field-solver techniques for RC extraction guarantee the accuracy of modeling, and are becoming increasingly important in meeting the demand for accurate modeling and simulation of VLSI designs. Advanced Field-Solver Techniques for RC Extraction of Integrated Circuits presents a systematic introduction to, and treatment of, the key field-solver methods for RC extraction of VLSI interconnects and substrate coupling in mixed-signal ICs. Various field-solver techniques are explained in detail, with real-world examples to illustrate the advantages and disadvantages of each algorithm. This book will benefit graduate students and researchers in the field of electrical and computer engineering, as well as engineers working in the IC design and design automation industries. Dr. Wenjian Yu is an Associate Professor at the Department of ...

  14. Highly focused ion beams in integrated circuit testing

    International Nuclear Information System (INIS)

    Horn, K.M.; Dodd, P.E.; Doyle, B.L.

    1996-01-01

    The nuclear microprobe has proven to be a useful tool in radiation testing of integrated circuits. This paper reviews single event upset (SEU) and ion beam induced charge collection (IBICC) imaging techniques, with special attention to damage-dependent effects. Comparisons of IBICC measurements with three-dimensional charge transport simulations of charge collection are then presented for isolated p-channel field effect transistors under conducting and non-conducting bias conditions

  15. Computing with networks of spiking neurons on a biophysically motivated floating-gate based neuromorphic integrated circuit.

    Science.gov (United States)

    Brink, S; Nease, S; Hasler, P

    2013-09-01

    Results are presented from several spiking network experiments performed on a novel neuromorphic integrated circuit. The networks are discussed in terms of their computational significance, which includes applications such as arbitrary spatiotemporal pattern generation and recognition, winner-take-all competition, stable generation of rhythmic outputs, and volatile memory. Analogies to the behavior of real biological neural systems are also noted. The alternatives for implementing the same computations are discussed and compared from a computational efficiency standpoint, with the conclusion that implementing neural networks on neuromorphic hardware is significantly more power efficient than numerical integration of model equations on traditional digital hardware. Copyright © 2013 Elsevier Ltd. All rights reserved.

  16. Multi-format all-optical processing based on a large-scale, hybridly integrated photonic circuit.

    Science.gov (United States)

    Bougioukos, M; Kouloumentas, Ch; Spyropoulou, M; Giannoulis, G; Kalavrouziotis, D; Maziotis, A; Bakopoulos, P; Harmon, R; Rogers, D; Harrison, J; Poustie, A; Maxwell, G; Avramopoulos, H

    2011-06-06

    We investigate through numerical studies and experiments the performance of a large scale, silica-on-silicon photonic integrated circuit for multi-format regeneration and wavelength-conversion. The circuit encompasses a monolithically integrated array of four SOAs inside two parallel Mach-Zehnder structures, four delay interferometers and a large number of silica waveguides and couplers. Exploiting phase-incoherent techniques, the circuit is capable of processing OOK signals at variable bit rates, DPSK signals at 22 or 44 Gb/s and DQPSK signals at 44 Gbaud. Simulation studies reveal the wavelength-conversion potential of the circuit with enhanced regenerative capabilities for OOK and DPSK modulation formats and acceptable quality degradation for DQPSK format. Regeneration of 22 Gb/s OOK signals with amplified spontaneous emission (ASE) noise and DPSK data signals degraded with amplitude, phase and ASE noise is experimentally validated demonstrating a power penalty improvement up to 1.5 dB.

  17. Design, Fabrication and Integration of a NaK-Cooled Circuit

    International Nuclear Information System (INIS)

    Garber, Anne; Godfroy, Thomas

    2006-01-01

    The Early Flight Fission Test Facilities (EFF-TF) team has been tasked by the NASA Marshall Space Flight Center Nuclear Systems Office to design, fabricate, and test an actively pumped alkali metal flow circuit. The system, which was originally designed for use with a eutectic mixture of sodium potassium (NaK), was redesigned for use with lithium. Due to a shift in focus, it is once again being prepared for use with NaK. Changes made to the actively pumped, high temperature circuit include the replacement of the expansion reservoir, addition of remotely operated valves, and modification of the support table. Basic circuit components include: reactor segment, NaK to gas heat exchanger, electromagnetic (EM) liquid metal pump, load/drain reservoir, expansion reservoir, instrumentation, and a spill reservoir. A 37-pin partial-array core (pin and flow path dimensions are the same as those in a full design) was selected for fabrication and test. This paper summarizes the integration and preparations for the fill of the pumped NaK circuit. (authors)

  18. Single-flux-quantum circuit technology for superconducting radiation detectors

    International Nuclear Information System (INIS)

    Fujimaki, Akira; Onogi, Masashi; Matsumoto, Tomohiro; Tanaka, Masamitsu; Sekiya, Akito; Hayakawa, Hisao; Yorozu, Shinichi; Terai, Hirotaka; Yoshikawa, Nobuyuki

    2003-01-01

    We discuss the application of the single-flux-quantum (SFQ) logic circuits to multi superconducting radiation detectors system. The SFQ-based analog-to-digital converters (ADCs) have the advantage in current sensitivity, which can reach less than 10 nA in a well-tuned ADC. We have also developed the design technology of the SFQ circuits. We demonstrate high-speed operation of large-scale integrated circuits such as a 2x2 cross/bar switch, arithmetic logic unit, indicating that our present SFQ technology is applicable to the multi radiation detectors system. (author)

  19. Recent advance in high manufacturing readiness level and high temperature CMOS mixed-signal integrated circuits on silicon carbide

    Science.gov (United States)

    Weng, M. H.; Clark, D. T.; Wright, S. N.; Gordon, D. L.; Duncan, M. A.; Kirkham, S. J.; Idris, M. I.; Chan, H. K.; Young, R. A. R.; Ramsay, E. P.; Wright, N. G.; Horsfall, A. B.

    2017-05-01

    A high manufacturing readiness level silicon carbide (SiC) CMOS technology is presented. The unique process flow enables the monolithic integration of pMOS and nMOS transistors with passive circuit elements capable of operation at temperatures of 300 °C and beyond. Critical to this functionality is the behaviour of the gate dielectric and data for high temperature capacitance-voltage measurements are reported for SiO2/4H-SiC (n and p type) MOS structures. In addition, a summary of the long term reliability for a range of structures including contact chains to both n-type and p-type SiC, as well as simple logic circuits is presented, showing function after 2000 h at 300 °C. Circuit data is also presented for the performance of digital logic devices, a 4 to 1 analogue multiplexer and a configurable timer operating over a wide temperature range. A high temperature micro-oven system has been utilised to enable the high temperature testing and stressing of units assembled in ceramic dual in line packages, including a high temperature small form-factor SiC based bridge leg power module prototype, operated for over 1000 h at 300 °C. The data presented show that SiC CMOS is a key enabling technology in high temperature integrated circuit design. In particular it provides the ability to realise sensor interface circuits capable of operating above 300 °C, accommodate shifts in key parameters enabling deployment in applications including automotive, aerospace and deep well drilling.

  20. Bridging the Gap: Towards a Cell-Type Specific Understanding of Neural Circuits Underlying Fear Behaviors

    Science.gov (United States)

    McCullough, KM; Morrison, FG; Ressler, KJ

    2016-01-01

    Fear and anxiety-related disorders are remarkably common and debilitating, and are often characterized by dysregulated fear responses. Rodent models of fear learning and memory have taken great strides towards elucidating the specific neuronal circuitries underlying the learning of fear responses. The present review addresses recent research utilizing optogenetic approaches to parse circuitries underlying fear behaviors. It also highlights the powerful advances made when optogenetic techniques are utilized in a genetically defined, cell-type specific, manner. The application of next-generation genetic and sequencing approaches in a cell-type specific context will be essential for a mechanistic understanding of the neural circuitry underlying fear behavior and for the rational design of targeted, circuit specific, pharmacologic interventions for the treatment and prevention of fear-related disorders. PMID:27470092

  1. Modular integration of electronics and microfluidic systems using flexible printed circuit boards.

    Science.gov (United States)

    Wu, Amy; Wang, Lisen; Jensen, Erik; Mathies, Richard; Boser, Bernhard

    2010-02-21

    Microfluidic systems offer an attractive alternative to conventional wet chemical methods with benefits including reduced sample and reagent volumes, shorter reaction times, high-throughput, automation, and low cost. However, most present microfluidic systems rely on external means to analyze reaction products. This substantially adds to the size, complexity, and cost of the overall system. Electronic detection based on sub-millimetre size integrated circuits (ICs) has been demonstrated for a wide range of targets including nucleic and amino acids, but deployment of this technology to date has been limited due to the lack of a flexible process to integrate these chips within microfluidic devices. This paper presents a modular and inexpensive process to integrate ICs with microfluidic systems based on standard printed circuit board (PCB) technology to assemble the independently designed microfluidic and electronic components. The integrated system can accommodate multiple chips of different sizes bonded to glass or PDMS microfluidic systems. Since IC chips and flex PCB manufacturing and assembly are industry standards with low cost, the integrated system is economical for both laboratory and point-of-care settings.

  2. Integrated Design Validation: Combining Simulation and Formal Verification for Digital Integrated Circuits

    Directory of Open Access Journals (Sweden)

    Lun Li

    2006-04-01

    Full Text Available The correct design of complex hardware continues to challenge engineers. Bugs in a design that are not uncovered in early design stages can be extremely expensive. Simulation is a predominantly used tool to validate a design in industry. Formal verification overcomes the weakness of exhaustive simulation by applying mathematical methodologies to validate a design. The work described here focuses upon a technique that integrates the best characteristics of both simulation and formal verification methods to provide an effective design validation tool, referred as Integrated Design Validation (IDV. The novelty in this approach consists of three components, circuit complexity analysis, partitioning based on design hierarchy, and coverage analysis. The circuit complexity analyzer and partitioning decompose a large design into sub-components and feed sub-components to different verification and/or simulation tools based upon known existing strengths of modern verification and simulation tools. The coverage analysis unit computes the coverage of design validation and improves the coverage by further partitioning. Various simulation and verification tools comprising IDV are evaluated and an example is used to illustrate the overall validation process. The overall process successfully validates the example to a high coverage rate within a short time. The experimental result shows that our approach is a very promising design validation method.

  3. High performance integer arithmetic circuit design on FPGA architecture, implementation and design automation

    CERN Document Server

    Palchaudhuri, Ayan

    2016-01-01

    This book describes the optimized implementations of several arithmetic datapath, controlpath and pseudorandom sequence generator circuits for realization of high performance arithmetic circuits targeted towards a specific family of the high-end Field Programmable Gate Arrays (FPGAs). It explores regular, modular, cascadable, and bit-sliced architectures of these circuits, by directly instantiating the target FPGA-specific primitives in the HDL. Every proposed architecture is justified with detailed mathematical analyses. Simultaneously, constrained placement of the circuit building blocks is performed, by placing the logically related hardware primitives in close proximity to one another by supplying relevant placement constraints in the Xilinx proprietary “User Constraints File”. The book covers the implementation of a GUI-based CAD tool named FlexiCore integrated with the Xilinx Integrated Software Environment (ISE) for design automation of platform-specific high-performance arithmetic circuits from us...

  4. Development of pixel readout integrated circuits for extreme rate and radiation

    CERN Document Server

    Garcia-Sciveres, M; CERN. Geneva. The LHC experiments Committee; LHCC

    2013-01-01

    Letter of Intent for RD Collaboration Proposal focused on development of a next generation pixel readout integrated circuits needed for high luminosity LHC detector upgrades. Brings together ATLAS and CMS pixel chip design communities.

  5. Toward printed integrated circuits based on unipolar or ambipolar polymer semiconductors.

    Science.gov (United States)

    Baeg, Kang-Jun; Caironi, Mario; Noh, Yong-Young

    2013-08-21

    For at least the past ten years printed electronics has promised to revolutionize our daily life by making cost-effective electronic circuits and sensors available through mass production techniques, for their ubiquitous applications in wearable components, rollable and conformable devices, and point-of-care applications. While passive components, such as conductors, resistors and capacitors, had already been fabricated by printing techniques at industrial scale, printing processes have been struggling to meet the requirements for mass-produced electronics and optoelectronics applications despite their great potential. In the case of logic integrated circuits (ICs), which constitute the focus of this Progress Report, the main limitations have been represented by the need of suitable functional inks, mainly high-mobility printable semiconductors and low sintering temperature conducting inks, and evoluted printing tools capable of higher resolution, registration and uniformity than needed in the conventional graphic arts printing sector. Solution-processable polymeric semiconductors are the best candidates to fulfill the requirements for printed logic ICs on flexible substrates, due to their superior processability, ease of tuning of their rheology parameters, and mechanical properties. One of the strongest limitations has been mainly represented by the low charge carrier mobility (μ) achievable with polymeric, organic field-effect transistors (OFETs). However, recently unprecedented values of μ ∼ 10 cm(2) /Vs have been achieved with solution-processed polymer based OFETs, a value competing with mobilities reported in organic single-crystals and exceeding the performances enabled by amorphous silicon (a-Si). Interestingly these values were achieved thanks to the design and synthesis of donor-acceptor copolymers, showing limited degree of order when processed in thin films and therefore fostering further studies on the reason leading to such improved charge

  6. Laser-induced extreme UV radiation sources for manufacturing next-generation integrated circuits

    International Nuclear Information System (INIS)

    Borisov, V M; Vinokhodov, A Yu; Ivanov, A S; Kiryukhin, Yu B; Mishchenko, V A; Prokof'ev, A V; Khristoforov, O B

    2009-01-01

    The development of high-power discharge sources emitting in the 13.5±0.135-nm spectral band is of current interest because they are promising for applications in industrial EUV (extreme ultraviolet) lithography for manufacturing integrated circuits according to technological precision standards of 22 nm and smaller. The parameters of EUV sources based on a laser-induced discharge in tin vapours between rotating disc electrodes are investigated. The properties of the discharge initiation by laser radiation at different wavelengths are established and the laser pulse parameters providing the maximum energy characteristics of the EUV source are determined. The EUV source developed in the study emits an average power of 276 W in the 13.5±0.135-nm spectral band on conversion to the solid angle 2π sr in the stationary regime at a pulse repetition rate of 3000 Hz. (laser applications and other topics in quantum electronics)

  7. CASTOR a VLSI CMOS mixed analog-digital circuit for low noise multichannel counting applications

    International Nuclear Information System (INIS)

    Comes, G.; Loddo, F.; Hu, Y.; Kaplon, J.; Ly, F.; Turchetta, R.; Bonvicini, V.; Vacchi, A.

    1996-01-01

    In this paper we present the design and first experimental results of a VLSI mixed analog-digital 1.2 microns CMOS circuit (CASTOR) for multichannel radiation detectors applications demanding low noise amplification and counting of radiation pulses. This circuit is meant to be connected to pixel-like detectors. Imaging can be obtained by counting the number of hits in each pixel during a user-controlled exposure time. Each channel of the circuit features an analog and a digital part. In the former one, a charge preamplifier is followed by a CR-RC shaper with an output buffer and a threshold discriminator. In the digital part, a 16-bit counter is present together with some control logic. The readout of the counters is done serially on a common tri-state output. Daisy-chaining is possible. A 4-channel prototype has been built. This prototype has been optimised for use in the digital radiography Syrmep experiment at the Elettra synchrotron machine in Trieste (Italy): its main design parameters are: shaping time of about 850 ns, gain of 190 mV/fC and ENC (e - rms)=60+17 C (pF). The counting rate per channel, limited by the analog part, can be as high as about 200 kHz. Characterisation of the circuit and first tests with silicon microstrip detectors are presented. They show the circuit works according to design specification and can be used for imaging applications. (orig.)

  8. Silicon photonic integrated circuits with electrically programmable non-volatile memory functions.

    Science.gov (United States)

    Song, J-F; Lim, A E-J; Luo, X-S; Fang, Q; Li, C; Jia, L X; Tu, X-G; Huang, Y; Zhou, H-F; Liow, T-Y; Lo, G-Q

    2016-09-19

    Conventional silicon photonic integrated circuits do not normally possess memory functions, which require on-chip power in order to maintain circuit states in tuned or field-configured switching routes. In this context, we present an electrically programmable add/drop microring resonator with a wavelength shift of 426 pm between the ON/OFF states. Electrical pulses are used to control the choice of the state. Our experimental results show a wavelength shift of 2.8 pm/ms and a light intensity variation of ~0.12 dB/ms for a fixed wavelength in the OFF state. Theoretically, our device can accommodate up to 65 states of multi-level memory functions. Such memory functions can be integrated into wavelength division mutiplexing (WDM) filters and applied to optical routers and computing architectures fulfilling large data downloading demands.

  9. Advance elements of optoisolation circuits nonlinearity applications in engineering

    CERN Document Server

    Aluf, Ofer

    2017-01-01

    This book on advanced optoisolation circuits for nonlinearity applications in engineering addresses two separate engineering and scientific areas, and presents advanced analysis methods for optoisolation circuits that cover a broad range of engineering applications. The book analyzes optoisolation circuits as linear and nonlinear dynamical systems and their limit cycles, bifurcation, and limit cycle stability by using Floquet theory. Further, it discusses a broad range of bifurcations related to optoisolation systems: cusp-catastrophe, Bautin bifurcation, Andronov-Hopf bifurcation, Bogdanov-Takens (BT) bifurcation, fold Hopf bifurcation, Hopf-Hopf bifurcation, Torus bifurcation (Neimark-Sacker bifurcation), and Saddle-loop or Homoclinic bifurcation. Floquet theory helps as to analyze advance optoisolation systems. Floquet theory is the study of the stability of linear periodic systems in continuous time. Another way to describe Floquet theory, it is the study of linear systems of differential equations with p...

  10. Mobile Learning Based Worked Example in Electric Circuit (WEIEC) Application to Improve the High School Students' Electric Circuits Interpretation Ability

    Science.gov (United States)

    Yadiannur, Mitra; Supahar

    2017-01-01

    This research aims to determine the feasibility and effectivity of mobile learning based Worked Example in Electric Circuits (WEIEC) application in improving the high school students' electric circuits interpretation ability on Direct Current Circuits materials. The research method used was a combination of Four-D Models and ADDIE model. The…

  11. Laser Direct Writing and Selective Metallization of Metallic Circuits for Integrated Wireless Devices.

    Science.gov (United States)

    Cai, Jinguang; Lv, Chao; Watanabe, Akira

    2018-01-10

    Portable and wearable devices have attracted wide research attention due to their intimate relations with human daily life. As basic structures in the devices, the preparation of high-conductive metallic circuits or micro-circuits on flexible substrates should be facile, cost-effective, and easily integrated with other electronic units. In this work, high-conductive carbon/Ni composite structures were prepared by using a facile laser direct writing method, followed by an electroless Ni plating process, which exhibit a 3-order lower sheet resistance of less than 0.1 ohm/sq compared to original structures before plating, showing the potential for practical use. The carbon/Ni composite structures exhibited a certain flexibility and excellent anti-scratch property due to the tight deposition of Ni layers on carbon surfaces. On the basis of this approach, a wireless charging and storage device on a polyimide film was demonstrated by integrating an outer rectangle carbon/Ni composite coil for harvesting electromagnetic waves and an inner carbon micro-supercapacitor for energy storage, which can be fast charged wirelessly by a commercial wireless charger. Furthermore, a near-field communication (NFC) tag was prepared by combining a carbon/Ni composite coil for harvesting signals and a commercial IC chip for data storage, which can be used as an NFC tag for practical application.

  12. High-dimensional quantum key distribution based on multicore fiber using silicon photonic integrated circuits

    DEFF Research Database (Denmark)

    Ding, Yunhong; Bacco, Davide; Dalgaard, Kjeld

    2017-01-01

    is intrinsically limited to 1 bit/photon. Here we propose and experimentally demonstrate, for the first time, a high-dimensional quantum key distribution protocol based on space division multiplexing in multicore fiber using silicon photonic integrated lightwave circuits. We successfully realized three mutually......-dimensional quantum states, and enables breaking the information efficiency limit of traditional quantum key distribution protocols. In addition, the silicon photonic circuits used in our work integrate variable optical attenuators, highly efficient multicore fiber couplers, and Mach-Zehnder interferometers, enabling...

  13. Optical electronics self-organized integration and applications

    CERN Document Server

    Yoshimura, Tetsuzo

    2012-01-01

    IntroductionFrom Electronics to Optical ElectronicsAnalysis Tools for Optical CircuitsSelf-Organized Optical Waveguides: Theoretical AnalysisSelf-Organized Optical Waveguides: Experimental DemonstrationsOptical Waveguide Films with Vertical Mirrors 3-D Optical Circuits with Stacked Waveguide Films Heterogeneous Thin-Film Device IntegrationOptical Switches OE Hardware Built by Optical ElectronicsIntegrated Solar Energy Conversion SystemsFuture Challenges.

  14. Prolonged 500 C Operation of 100+ Transistor Silicon Carbide Integrated Circuits

    Science.gov (United States)

    Spry, David J.; Neudeck, Philip G.; Lukco, Dorothy; Chen, Liangyu; Krasowski, Michael J.; Prokop, Norman F.; Chang, Carl W.; Beheim, Glenn M.

    2017-01-01

    This report describes more than 5000 hours of successful 500 C operation of semiconductor integrated circuits (ICs) with more than 100 transistors. Multiple packaged chips with two different 4H-SiC junction field effect transistor (JFET) technology demonstrator circuits have surpassed thousands of hours of oven-testing at 500 C. After 100 hours of 500 C burn-in, the circuits (except for 2 failures) exhibit less than 10 change in output characteristics for the remainder of 500C testing. We also describe the observation of important differences in IC materials durability when subjected to the first nine constituents of Venus-surface atmosphere at 9.4 MPa and 460C in comparison to what is observed for Earth-atmosphere oven testing at 500 C.

  15. Study of Piezoelectric Vibration Energy Harvester with non-linear conditioning circuit using an integrated model

    Science.gov (United States)

    Manzoor, Ali; Rafique, Sajid; Usman Iftikhar, Muhammad; Mahmood Ul Hassan, Khalid; Nasir, Ali

    2017-08-01

    Piezoelectric vibration energy harvester (PVEH) consists of a cantilever bimorph with piezoelectric layers pasted on its top and bottom, which can harvest power from vibrations and feed to low power wireless sensor nodes through some power conditioning circuit. In this paper, a non-linear conditioning circuit, consisting of a full-bridge rectifier followed by a buck-boost converter, is employed to investigate the issues of electrical side of the energy harvesting system. An integrated mathematical model of complete electromechanical system has been developed. Previously, researchers have studied PVEH with sophisticated piezo-beam models but employed simplistic linear circuits, such as resistor, as electrical load. In contrast, other researchers have worked on more complex non-linear circuits but with over-simplified piezo-beam models. Such models neglect different aspects of the system which result from complex interactions of its electrical and mechanical subsystems. In this work, authors have integrated the distributed parameter-based model of piezo-beam presented in literature with a real world non-linear electrical load. Then, the developed integrated model is employed to analyse the stability of complete energy harvesting system. This work provides a more realistic and useful electromechanical model having realistic non-linear electrical load unlike the simplistic linear circuit elements employed by many researchers.

  16. Oscillator circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for oscillator circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listing

  17. Measuring circuits

    CERN Document Server

    Graf, Rudolf F

    1996-01-01

    This series of circuits provides designers with a quick source for measuring circuits. Why waste time paging through huge encyclopedias when you can choose the topic you need and select any of the specialized circuits sorted by application?This book in the series has 250-300 practical, ready-to-use circuit designs, with schematics and brief explanations of circuit operation. The original source for each circuit is listed in an appendix, making it easy to obtain additional information.Ready-to-use circuits.Grouped by application for easy look-up.Circuit source listings

  18. Sequential circuit design for radiation hardened multiple voltage integrated circuits

    Science.gov (United States)

    Clark, Lawrence T [Phoenix, AZ; McIver, III, John K.

    2009-11-24

    The present invention includes a radiation hardened sequential circuit, such as a bistable circuit, flip-flop or other suitable design that presents substantial immunity to ionizing radiation while simultaneously maintaining a low operating voltage. In one embodiment, the circuit includes a plurality of logic elements that operate on relatively low voltage, and a master and slave latches each having storage elements that operate on a relatively high voltage.

  19. Triple inverter pierce oscillator circuit suitable for CMOS

    Science.gov (United States)

    Wessendorf,; Kurt, O [Albuquerque, NM

    2007-02-27

    An oscillator circuit is disclosed which can be formed using discrete field-effect transistors (FETs), or as a complementary metal-oxide-semiconductor (CMOS) integrated circuit. The oscillator circuit utilizes a Pierce oscillator design with three inverter stages connected in series. A feedback resistor provided in a feedback loop about a second inverter stage provides an almost ideal inverting transconductance thereby allowing high-Q operation at the resonator-controlled frequency while suppressing a parasitic oscillation frequency that is inherent in a Pierce configuration using a "standard" triple inverter for the sustaining amplifier. The oscillator circuit, which operates in a range of 10 50 MHz, has applications for use as a clock in a microprocessor and can also be used for sensor applications.

  20. A Alternative Analog Circuit Design Methodology Employing Integrated Artificial Intelligence Techniques

    Science.gov (United States)

    Tuttle, Jeffery L.

    In consideration of the computer processing power now available to the designer, an alternative analog circuit design methodology is proposed. Computer memory capacities no longer require the reduction of the transistor operational characteristics to an imprecise formulation. Therefore, it is proposed that transistor modelling be abandoned in favor of fully characterized transistor data libraries. Secondly, availability of the transistor libraries would facilitate an automated selection of the most appropriate device(s) for the circuit being designed. More specifically, a preprocessor computer program to a more sophisticated circuit simulator (e.g. SPICE) is developed to assist the designer in developing the basic circuit topology and the selection of the most appropriate transistor. Once this is achieved, the circuit topology and selected transistor data library would be downloaded to the simulator for full circuit operational characterization and subsequent design modifications. It is recognized that the design process is enhanced by the use of heuristics as applied to iterative design results. Accordingly, an artificial intelligence (AI) interface is developed to assist the designer in applying the preprocessor results. To demonstrate the retrofitability of the AI interface to established programs, the interface is specifically designed to be as non-intrusive to the host code as possible. Implementation of the proposed methodology offers the potential to speed the design process, since the preprocessor both minimizes the required number of simulator runs and provides a higher acceptance potential of the initial and subsequent simulator runs. Secondly, part count reductions may be realizable since the circuit topologies are not as strongly driven by transistor limitations. Thirdly, the predicted results should more closely match actual circuit operations since the inadequacies of the transistor models have been virtually eliminated. Finally, the AI interface