WorldWideScience

Sample records for analog to digital converters

  1. Optical analog-to-digital converter

    Science.gov (United States)

    Evanchuk, Vincent L. (Inventor)

    1984-01-01

    A method and apparatus for converting the intensity of an unknown optical signal (B) into an electrical signal in digital form utilizes two elongated optical attenuators (11, 13), one for the unknown optical signal from a source (10) and one for a known optical signal (A) from a variable source (12), a plurality of photodetectors (e.g., 17, 18) along each attenuator for detecting the intensity of the optical signals, and a plurality of comparators (e.g., 21) connected to the photodetectors in pairs to determine at what points being compared the attenuated known signal equals the attenuated unknown signal. The intensity of the unknown relative to the known is thus determined by the output of a particular comparator. That output is automatically encoded to a relative intensity value in digital form through a balancing feedback control (24) and encoder (23). The digital value may be converted to analog form in a D-to-A converter (27) and used to vary the source of the known signal so that the attenuated intensity of the known signal at a predetermined point (comparator 16) equals the attenuated intensity of the unknown signal at the predetermined point of comparison. If the known signal is then equal to the unknown, there is verification of the analog-to-digital conversion being complete. Otherwise the output of the comparator indicating equality at some other point along the attenuators will provide an output which is encoded and added, through an accumulator comprised of a register (25) and an adder (26), to a previous relative intensity value thereby to further vary the intensity of the known signal source. The steps are repeated until full conversion is verified.

  2. Photonic analog-to-digital converters

    Science.gov (United States)

    Valley, George C.

    2007-03-01

    This paper reviews over 30 years of work on photonic analog-to-digital converters. The review is limited to systems in which the input is a radio-frequency (RF) signal in the electronic domain and the output is a digital version of that signal also in the electronic domain, and thus the review excludes photonic systems directed towards digitizing images or optical communication signals. The state of the art in electronic ADCs, basic properties of ADCs and properties of analog optical links, which are found in many photonic ADCs, are reviewed as background information for understanding photonic ADCs. Then four classes of photonic ADCs are reviewed: 1) photonic assisted ADC in which a photonic device is added to an electronic ADC to improve performance, 2) photonic sampling and electronic quantizing ADC, 3) electronic sampling and photonic quantizing ADC, and 4) photonic sampling and quantizing ADC. It is noted, however, that all 4 classes of “photonic ADC” require some electronic sampling and quantization. After reviewing all known photonic ADCs in the four classes, the review concludes with a discussion of the potential for photonic ADCs in the future.

  3. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  4. Serial Pixel Analog-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Larson, E D

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and “one-hot” counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  5. Time interleaved counter analog to digital converters

    OpenAIRE

    Danesh, Seyed Amir Ali

    2011-01-01

    The work explores extending time interleaving in A/D converters, by applying a high-level of parallelism to one of the slowest and simplest types of data-converters, the counter ADC. The motivation for the work is to realise high-performance re-configurable A/D converters for use in multi-standard and multi-PHY communication receivers with signal bandwidths in the 10s to 100s of MHz. The counter ADC requires only a comparator, a ramp signal, and a digital counter, where the ...

  6. Error Models of the Analog to Digital Converters

    OpenAIRE

    Michaeli Linus; Šaliga Ján

    2014-01-01

    Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by t...

  7. High-speed and high-resolution analog-to-digital and digital-to-analog converters

    NARCIS (Netherlands)

    van de Plassche, R.J.

    1989-01-01

    Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog filte

  8. Reference-Free CMOS Pipeline Analog-to-Digital Converters

    CERN Document Server

    Figueiredo, Michael; Evans, Guiomar

    2013-01-01

    This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

  9. A Novel All-Optical Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    Xiaobo; Hou; Afshin; Daryoush; Warren; Rosen

    2003-01-01

    An all-optical analog-to-digital converter capable of sampling at 50GS/s is described. The ADC works in the frequency domain. The RF signal is sampled by electro-optically steerable gratings and quantized by a set of detectors with scalable apertures.

  10. Time-interleaved analog-to-digital converters

    CERN Document Server

    Louwsma, Simon; Nauta, Bram

    2010-01-01

    ""Time-interleaved Analog-to-Digital Converters"" describes the research performed on low-power time-interleaved ADCs. A detailed theoretical analysis is made of the time-interleaved Track & Hold, since it must be capable of handling signals in the GHz range with little distortion, and minimal power consumption. Timing calibration is not attractive, therefore design techniques are presented which do not require timing calibration. The design of power efficient sub-ADCs is addressed with a theoretical analysis of a successive approximation converter and a pipeline converter. It turns out that t

  11. Energy Savings Assessment for Digital-to-Analog Converter Boxes

    Energy Technology Data Exchange (ETDEWEB)

    Cheung, Hoi Ying Iris; Meier, Alan; Brown, Richard

    2011-01-18

    The Digital Television (DTV) Converter Box Coupon Program was administered by the U.S. government to subsidize purchases of digital-to-analog converter boxes, with up to two $40 coupons for each eligible household. In order to qualify as Coupon Eligible Converter Boxes (CECBs), these devices had to meet a number of minimum performance specifications, including energy efficiency standards. The Energy Star Program also established voluntary energy efficiency specifications that are more stringent than the CECB requirements. In this study, we measured the power and energy consumptions for a sample of 12 CECBs (including 6 Energy Star labeled models) in-use in homes and estimated aggregate energy savings produced by the energy efficiency policies. Based on the 35 million coupons redeemed through the end of the program, our analysis indicates that between 2500 and 3700 GWh per year are saved as a result of the energy efficiency policies implemented on digital-to-analog converter boxes. The energy savings generated are equivalent to the annual electricity use of 280,000 average US homes.

  12. Optimizing analog-to-digital converters for sampling extracellular potentials.

    Science.gov (United States)

    Artan, N Sertac; Xu, Xiaoxiang; Shi, Wei; Chao, H Jonathan

    2012-01-01

    In neural implants, an analog-to-digital converter (ADC) provides the delicate interface between the analog signals generated by neurological processes and the digital signal processor that is tasked to interpret these signals for instance for epileptic seizure detection or limb control. In this paper, we propose a low-power ADC architecture for neural implants that process extracellular potentials. The proposed architecture uses the spike detector that is readily available on most of these implants in a closed-loop with an ADC. The spike detector determines whether the current input signal is part of a spike or it is part of noise to adaptively determine the instantaneous sampling rate of the ADC. The proposed architecture can reduce the power consumption of a traditional ADC by 62% when sampling extracellular potentials without any significant impact on spike detection accuracy.

  13. VHDL Implementation of Sigma-Delta Analog To Digital Converter

    Science.gov (United States)

    Chavan, R. N.; Chougule, D. G.

    2010-11-01

    Sigma-Delta modulation techniques provide a range of opportunities in a signal processing system for both increasing performance and data path optimization along the silicon area axis in the design space. One of the most challenging tasks in Analog to Digital Converter (ADC) design is to adapt the circuitry to ever new CMOS process technology. For digital circuits the number of gates per square mm app. doubles per chip generation. Integration of analog parts in newer deep submicron technologies is much more tough and additionally complicated because the usable voltage ranges are decreasing with every new integration step. This paper shows an approach which only uses 2 resistors and 1 capacitor which are located outside a pure digital chip. So all integration advantages of pure digital chips are preserved, there is no design effort for a new chip generation and the ADC also can be used for FPGAs. Resolutions of up to 16 bit are achievable. Sample rates in the 1 MHz region are feasible so that the approach is also useful for ADCs for xDSL technologies.

  14. Error Models of the Analog to Digital Converters

    Science.gov (United States)

    Michaeli, Linus; Šaliga, Ján

    2014-04-01

    Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

  15. Error Models of the Analog to Digital Converters

    Directory of Open Access Journals (Sweden)

    Michaeli Linus

    2014-04-01

    Full Text Available Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

  16. Optical-spectrum-encoded analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    LIAO Xiao-jun; YANG Ya-pei

    2007-01-01

    A novel optical-spectrum-encoded (OSE) analog-to-digital converter (ADC) is proposed in this letter. To simply exemplify the conversion idea, a 5-bit device structure consisted of Fabry-Perot interferometers (FPI) is analyzed and numerically simulated. The dependence of peak-transmission wavelength on modulation voltage in an electro-optical FPI and the dependence of transmitted power on incident light wavelength in an FPI are discussed and utilized to implement OSEADC.A linearly tunable mode-locked laser, as a voltage-wavelength transformer and a sampler, and chirped grating FPIs, as an encoder array, can be used to obtain much greater sampling rate and bit-resolution.

  17. High fidelity, radiation tolerant analog-to-digital converters

    Science.gov (United States)

    Wang, Charles Chang-I (Inventor); Linscott, Ivan Richard (Inventor); Inan, Umran S. (Inventor)

    2012-01-01

    Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming meters), it maintains this performance in harsh radiation environments. Specifically, the stated performance is sustained through a highest tested 2 megarad(Si) total dose, and the ADC displays no latchup up to a highest tested linear energy transfer of 63 million electron Volts square centimeters per milligram at elevated temperature (131 degrees C.) and supply (2.7 Volts, versus 2.5 Volts nominal).

  18. Serial pixel analog-to-digital converter (ADC)

    Science.gov (United States)

    Larson, Eric D.

    2010-02-01

    This method reduces the data path from the counter to the pixel register of the analog-to-digital converter (ADC) from as many as 10 bits to a single bit. The reduction in data path width is accomplished by using a coded serial data stream similar to a pseudo random number (PRN) generator. The resulting encoded pixel data is then decoded into a standard hexadecimal format before storage. The high-speed serial pixel ADC concept is based on the single-slope integrating pixel ADC architecture. Previous work has described a massively parallel pixel readout of a similar architecture. The serial ADC connection is similar to the state-of-the art method with the exception that the pixel ADC register is a shift register and the data path is a single bit. A state-of-the-art individual-pixel ADC uses a single-slope charge integration converter architecture with integral registers and "one-hot" counters. This implies that parallel data bits are routed among the counter and the individual on-chip pixel ADC registers. The data path bit-width to the pixel is therefore equivalent to the pixel ADC bit resolution.

  19. Photonic analog-to-digital converter via asynchronous oversampling

    Science.gov (United States)

    Carver, Spencer; Reeves, Erin; Siahmakoun, Azad; Granieri, Sergio

    2012-06-01

    This paper presents a hybrid opto-electronic asynchronous delta-sigma modulator, implemented in the form of a fiber-optic Analog-to-Digital converter (ADC). This architecture was chosen for its independence of an external clock and ease of demodulation through a single low-pass filter stage. The fiber-optic prototype consists of an input laser (wavelength λ1) which is modulated with an input RF signal, a high-speed comparator circuit working as bi-stable quantizer, and a fiber-optic loop that includes a SOA and a band-pass filter that act as a leaky integrator. The fiber-optic loop acts as a fiber-ring resonator (FRR), and defines the resonance wavelength λ2 of the system. The gain within this loop is modified through cross-gain modulation (XGM) by the input wavelength λ1, and thus achieves the desired modulation effect. The proposed architecture has been constructed and characterized at a sampling rate of 15.4 MS/s processing input analog signals in the range of dc-3 MHz with a signal-to-noise ratio of 36 dB and an effective number of bits of 5.7.

  20. Lower Bounds on the Performance of Analog to Digital Converters

    CERN Document Server

    Osqui, Mitra; Roozbehani, Mardavij

    2012-01-01

    This paper deals with the task of finding certified lower bounds for the performance of Analog to Digital Converters (ADCs). A general ADC is modeled as a causal, discrete-time dynamical system with outputs taking values in a finite set. We define the performance of an ADC as the worst-case average intensity of the filtered input matching error, defined as the difference between the input and output of the ADC. The passband of the shaping filter used to filter the error signal determines the frequency region of interest for minimizing the error. The problem of finding a lower bound for the performance of an ADC is formulated as a dynamic game problem in which the input signal to the ADC plays against the output of the ADC. Furthermore, the performance measure must be optimized in the presence of quantized disturbances (output of the ADC) that can exceed the control variable (input of the ADC) in magnitude. We characterize the optimal solution in terms of a Bellman-type inequality. A numerical approach is pres...

  1. Mismatch-Shaping Serial Digital-to-Analog Converter

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper; Moon, Un-Ku; Temes, Gabor C.

    1999-01-01

    A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal a...

  2. Automatic Synthesis of CMOS Algorithmic Analog To-Digital Converter.

    Science.gov (United States)

    Jusuf, Gani

    The steady decrease in technological feature size is allowing increasing levels of integration in analog/digital interface functions. These functions consist of analog as well as digital circuits. While the turn around time for an all digital IC chip is very short due to the maturity of digital IC computer-aided design (CAD) tools over the last ten years, most analog circuits have to be designed manually due to the lack of analog IC CAD tools. As a result, analog circuit design becomes the bottleneck in the design of mixed signal processing chips. One common analog function in a mixed signal processing chip is an analog-to-digital conversion (ADC) function. This function recurs frequently but with varying performance requirements. The objective of this research is to study the design methodology of a compilation program capable of synthesizing ADC's with a broad range of sampling rates and resolution, and silicon area and performance comparable with the manual approach. The automatic compilation of the ADC function is a difficult problem mainly because ADC techniques span such a wide spectrum of performance, with radically different implementations being optimum for different ranges of conversion range, resolution, and power dissipation. We will show that a proper choice of the ADC architectures and the incorporation of many analog circuit design techniques will simplify the synthesis procedure tremendously. Moreover, in order to speed up the device sizing, hierarchical optimization procedure and behavioral simulation are implemented into the ADC module generation steps. As a result of this study, a new improved algorithmic ADC without the need of high precision comparators has been developed. This type of ADC lends itself to automatic generation due to its modularity, simplicity, small area consumption, moderate speed, low power dissipation, and single parameter trim capability that can be added at high resolution. Furthermore, a performance-driven CMOS ADC module

  3. A Low-Power, Variable-Resolution Analog-to-Digital Converter

    OpenAIRE

    Aust, Carrie Ellen

    2000-01-01

    Analog-to-digital converters (ADCs) are used to convert analog signals to the digital domain in digital communications systems. An ADC used in wireless communications should meet the necessary requirements for the worst-case channel condition. However, the worst-case scenario rarely occurs. As a consequence, a high-resolution and subsequently high power ADC designed for the worst case is not required for most operating conditions. A solution to reduce the power dissipation of ADCs in wire...

  4. Design and Research on Sigma-Delta Digital-to-Analog Converters for Audio Power Amplifiers

    OpenAIRE

    Puidokas, Vytenis

    2011-01-01

    The dissertation investigates the issues of analyzing a digital Sigma-Delta digital-to-analog converter (DAC) for audio power amplifiers. The main objects of research include a digital Sigma-Delta audio power DAC, improvement of its structure and an experimental research. The primary purpose of the dissertation is to suggest methods for improvement the structure of digital Sigma-Delta audio power DAC interpolator and the converter analysis. Disertacijoje nagrinėjami Sigma-Delta skaitmenini...

  5. Pipeline analog-to-digital converters for wide-band wireless communications

    OpenAIRE

    Sumanen, Lauri

    2002-01-01

    During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates...

  6. [Principles of design of neural-network analog-to-digital converters of bioelectric signals].

    Science.gov (United States)

    Loktiukhin, V N; Chelebaev, S V

    2007-01-01

    A design principle and a procedure for synthesis of neural-network analog-to-digital converters of bioelectric signals are suggested. An example of implementation of an FPGA-based neural-network converter for classification of bioparameters is presented.

  7. 1 GS/s, Low Power Flash, Analog to Digital Converter in 90nm CMOS Technology

    OpenAIRE

    Hassan Raza Naqvi, Syed

    2007-01-01

    The analog to digital converters is the key components in modern electronic systems. As the digital signal processing industry grows the ADC design becomes more and more challenging for researchers. In these days an ADC becomes a part of the system on chip instead of standalone circuit for data converters. This increases the requirements on ADC design concerning for example speed, power, area, resolution, noise etc. New techniques and methods are going to develop day by day to achieve high pe...

  8. Design of Pipelined Analog-to-Digital Converter with SI Technique in 65 nm CMOS Technology

    OpenAIRE

    2011-01-01

    Analog-to-digital converter (ADC) plays an important role in mixed signal processingsystems. It serves as an interface between analog and digital signal processingsystems. In the last two decades, circuits implemented in current-modetechnique have drawn lots of interest for sensory systems and integrated circuits.Current-mode circuits have a few vital advantages such as low voltage operation,high speed and wide dynamic ranges. These circuits have wide applications in lowvoltage, high speed-mi...

  9. Predictive analog-to-digital converter for Fourier-transform spectrometers.

    Science.gov (United States)

    Deschênes, Jean-Daniel; Potvin, Simon; Ash, Jean-Simon; Genest, Jérôme

    2010-09-10

    This paper proposes the use of predictive analog-to-digital converters (ADC) to handle dynamic range issues in Fourier-transform spectrometers. Several predictive approaches are proposed, and one is implemented experimentally to show that the technique works. A system was implemented with 16 bit (13 bits effective) ADCs and digital-to-analog converters (DACs) operated at 8 bits to provide a comparison basis. Measurements of a blackbody at 900 °C performed using the setup show a 13 bit effective performance, limited by the input noise of the data acquisition card.

  10. Low-Voltage Analog-to-Digital Converters and Mixed-Signal Interfaces

    OpenAIRE

    Harikumar, Prakash

    2016-01-01

    Analog-to-digital converters (ADCs) are crucial blocks which form the interface between the physical world and the digital domain. ADCs are indispensable in numerous applications such as wireless sensor networks (WSNs), wireless/wireline communication receivers and data acquisition systems. To achieve long-term, autonomous operation for WSNs, the nodes are powered by harvesting energy from ambient sources such as solar energy, vibrational energy etc. Since the signal frequencies in these dist...

  11. Analog-To-Digital Converter For Sum-Of-Squares Measurements

    Science.gov (United States)

    Osborn, Stephen H.; Davies, Bryan L.; Sullender, Craig C.

    1993-01-01

    Analog-to-digital converter (ADC) circuit designed as part of larger circuit intended to measure root-mean-square current on 20-kHz powerline. Provides digital output of 11 bits of data plus 1-bit overflow signal at sampling rate of 4 MHz. Output processed by multiplying-and-accumulating circuitry to obtain sum of squares and digitized current samples accumulated during preset number of consecutive sampling periods. Used to digitize current samples from ADC directly as alternative or auxiliary output. Notable features include low power and fast conversion.

  12. Charge integration successive approximation analog-to-digital converter for focal plane applications using a single amplifier

    Science.gov (United States)

    Zhou, Zhimin (Inventor); Pain, Bedabrata (Inventor)

    1999-01-01

    An analog-to-digital converter for on-chip focal-plane image sensor applications. The analog-to-digital converter utilizes a single charge integrating amplifier in a charge balancing architecture to implement successive approximation analog-to-digital conversion. This design requires minimal chip area and has high speed and low power dissipation for operation in the 2-10 bit range. The invention is particularly well suited to CMOS on-chip applications requiring many analog-to-digital converters, such as column-parallel focal-plane architectures.

  13. Post-Correction of Analog-to-Digital Converters

    OpenAIRE

    Lundin, Henrik; Skoglund, Mikael; Händel, Peter

    2003-01-01

    A dynamic post-correction method for ADCs is presented. The method utilizes bit-masking, and a tool for analyzing the effects thereof is proposed. This tool is used to calculate optimal bit allocations, in order to minimize the THD of the corrected ADC. An example based on experimental ADC data is presented. Abstract submitted to the “Northern Lights Workshop on Sensors, Signals & Systems”. January 27, 2003.Konferensen blev inställdQC 20111101

  14. A new structure of substage in pipelined analog-to-digital converters

    Institute of Scientific and Technical Information of China (English)

    JIA Hua-yu; CHEN Gui-can; ZHANG Hong

    2009-01-01

    The article presents a new (1+1)-bit/stage structure for pipelined analog-to-digital converters (ADC). When the input analog signal of the structure exceeds the converting range of the whole ADC, the signal can still be converted precisely and the output residue voltage of the structure will be in the converting range of the ADC. The structure is used in a 12-bit 40 MS/s pipelined ADC to test its function. The testing results show that the structure has right function and can correct the transition error induced by offset of comparators' decision levels. The ADC implemented in Semiconductor Manufactory International Corporation (SMIC) 0.18 μm CMOS process consumes 210 mW and occupies a chip area of 3.2×3.7 mm2.

  15. A RESEARCH ON HIGH -PERFORMANCE ANALOG-TO-DIGITAL CONVERTERS IN WIRELESS COMMUNICATION SYSTEMSIN

    OpenAIRE

    伊藤, 朋彦; ITO,Tomohiko

    2014-01-01

    To realize next-generation high-throughput wireless communication systems, it is essential to develop analog-to-digital converters (ADC) with high conversion speed, high resolution, low power, and low operational supply voltage. In this work, the design methodologies and the new circuit architectures for these high-performance ADCs are researched.First, the methods to optimize these performances for ADCs were confirmed. In a pipeline ADC which is promising to realize the high-throughput syste...

  16. Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps

    Energy Technology Data Exchange (ETDEWEB)

    Doerry, Armin Walter [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Dubbert, Dale F. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States); Tise, Bertice L. [Sandia National Lab. (SNL-NM), Albuquerque, NM (United States)

    2014-07-01

    Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the relationship of INL to GMTI performance.

  17. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  18. Multisensor transducer based on a parallel fiber optic digital-to-analog converter

    Directory of Open Access Journals (Sweden)

    Grechishnikov Vladimir

    2017-01-01

    Full Text Available Considered possibility of creating a multisensory information converter (MSPI based on new fiber-optic functional element-digital-to-analog (DAC fiber optic converter. The use of DAC fiber-optic provides jamming immunity combined with low weight and cost of indicators .Because of that MSPI scheme was developed based on parallel DAC fiber-optic (Russian Federation Patent 157416. We came up with an equation for parallel DAC fiber-optic. An eleborate general mathematical model of the proposed converter. Developed a method for reducing conversion errors by placing the DAC transfer function between i and i + 1 ADC quantization levels. By using this model it allows you to obtain reliable information about the technical capabilities of a converter without the need for costly experiments.

  19. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J M

    2010-01-01

    The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

  20. SEM analysis of ionizing radiation effects in an analog to digital converter /AD571/

    Science.gov (United States)

    Gauthier, M. K.; Perret, J.; Evans, K. C.

    1981-01-01

    The considered investigation is concerned with the study of the total-dose degradation mechanisms in an IIL analog to digital (A/D) converter. The A/D converter is a 10 digit device having nine separate functional units on the chip which encompass several hundred transistors and circuit elements. It was the objective of the described research to find the radiation sensitive elements by a systematic search of the devices on the LSI chip. The employed technique using a scanning electron microscope to determine the functional blocks of an integrated circuit which are sensitive to ionizing radiation and then progressively zeroing in on the soft components within those blocks, proved extremely successful on the AD571. Four functional blocks were found to be sensitive to radiation, including the Voltage Reference, DAC, IIL Clock, and IIL SAR.

  1. Cryogenic analog-to-digital converters using spread spectrum technology for coherent receivers

    Science.gov (United States)

    Shiao, Yu-Shao Jerry; Chiueh, Tzihong; Hu, Robert

    2012-09-01

    We propose analog-to-digital converters (ADCs) using spread spectrum technology in cryogenic receivers or at warm room temperature for coherent receiver backend systems. As receiver signals are processed and stored digitally, ADCs play a critical role in backend read-out systems. To minimize signal distortion, the down-converted signals should be digitized without further transportation. However, digitizing the signals in or near receivers may cause radio frequency interference. We suggest that spread spectrum technology can reduce the interference significantly. Moreover, cryogenic ADCs at regulated temperature in receiver dewars may also increase the bandwidth usage and simplify the backend digital signal process with fewer temperature-dependant components. While industrial semiconductor technology continuously reduces transistor power consumption, low power high speed cryogenic ADCs may become a better solution for coherent receivers. To examine the performance of cooled ADCs, first, we design 4 bit 65 nm and 40 nm CMOS ADCs specifically at 10 K temperature, which commonly is the second stage temperature in dewars. While the development of 65 nm and 40 nm CMOS ADCs are still on-going, we estimate the ENOB is 2.4 at 10 GSPS, corresponding to the correlation efficiency, 0.87. The power consumption is less than 20 mW.

  2. High-performance Analog-to-Digital Converters and Line Drivers

    OpenAIRE

    Nieminen, Tero

    2016-01-01

    Nowadays, a high-speed medium-accuracy analog-to-digital converter (ADC) is required in numerous applications, such as a synthetic aperture radar (SAR) system, wireless local area network (WLAN) receiver, or DVD and Blu-Ray readout. As one of the two main parts, this dissertation presents the design and implementation of wideband high-speed medium-accuracy pipeline ADC as a part of a receiver of a SAR system, implemented in a deep-submicron CMOS process. Technology scaling of modern narrow li...

  3. Experimental demonstration of arbitrary waveform generation by a 4-bit photonic digital-to-analog converter

    Science.gov (United States)

    Gao, Bindong; Zhang, Fangzheng; Pan, Shilong

    2017-01-01

    Arbitrary waveform generation by a serial photonic digital-to-analog converter (PDAC) is demonstrated in this paper. To construct the PDAC, an intensity weighted, time and wavelength interleaved optical pulse train is first generated by phase modulation and fiber dispersion. Then, on-off keying modulation of the optical pulses is implemented according to the input serial digital bits. After proper dispersion compensation, a combined optical pulse is obtained with its total power proportional to the weighted sum of the input digital bits, and digital-to-analog conversion is achieved after optical-to-electronic conversion. By properly designing the input bits and using a low pass filter for signal smoothing, arbitrary waveforms can be generated. Performance of the PDAC is experimentally investigated by establishing a 2.5 GSa/s 4-bit PDAC. The established PDAC is found to have a good linear transfer function and the effective number of bits (ENOB) reaches as high as 3.49. Based on the constructed PDAC, generation of multiple waveforms including triangular, parabolic, square and sawtooth pulses are implemented with the generated waveforms very close to the ideal waveforms.

  4. Active-Pixel Image Sensor With Analog-To-Digital Converters

    Science.gov (United States)

    Fossum, Eric R.; Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.

    1995-01-01

    Proposed single-chip integrated-circuit image sensor contains 128 x 128 array of active pixel sensors at 50-micrometer pitch. Output terminals of all pixels in each given column connected to analog-to-digital (A/D) converter located at bottom of column. Pixels scanned in semiparallel fashion, one row at time; during time allocated to scanning row, outputs of all active pixel sensors in row fed to respective A/D converters. Design of chip based on complementary metal oxide semiconductor (CMOS) technology, and individual circuit elements fabricated according to 2-micrometer CMOS design rules. Active pixel sensors designed to operate at video rate of 30 frames/second, even at low light levels. A/D scheme based on first-order Sigma-Delta modulation.

  5. Increasing the dynamic range of a transient recorder by using two analog-to-digital converters.

    Science.gov (United States)

    Beavis, R C

    1996-01-01

    This article describes an algorithm for recording transient voltages with enhanced dynamic range by using two 8-bit analog-to-digital converters (ADCs). The method requires each transient to be recorded in both ADCs, with different input voltage gains. The transients then are compared and combined to produce a single signal that has less digitization noise and greater dynamic range than signals recorded by either ADC alone and with no decrease in the sampling rate of the ADCs. The selection of operating parameters is considered and guidelines are established for the performance of this type of transient recorder. The system described here was built as a data acquisition device for a time-of-flight mass spectrometer; however, the algorithm could be applied to other types of ADC-based applications to extend their dynamic range.

  6. Design of 6-Bit Flash Analog to Digital Converter Using Variable Switching Voltage CMOS Comparator

    Directory of Open Access Journals (Sweden)

    Gulrej Ahmed

    2014-04-01

    Full Text Available This paper presents the design of 6-bit flash analog to digital Converter (ADC using the new variable switching voltage (VSV comparator. In general, Flash ADCs attain the highest conversion speed at the cost of high power consumption. By using the new VSV comparator, the designed 6-bit Flash ADC exhibits significant improvement in terms of power and speed of previously reported Flash ADCs. The simulation result shows that the converter consumes peak power 2.1 mW from a 1.2 V supply and achieves the speed of 1 GHz in a 65nm standard CMOS process. The measurement of maximum differential and integral nonlinearities (DNL and INL of the Flash ADC are 0.3 LSB and 0.6 LSB respectively.

  7. Multichannel analog-to-digital converters based on current mirrors for the optical systems

    Science.gov (United States)

    Krasilenko, Vladimir G.; Nikolskyy, A. I.; Nikolska, M. A.; Lobodzinska, R. F.

    2011-12-01

    The paper considers results of designing and modeling analogue-digital converters (ADC) based on current mirrors for the optical systems and neural networks with parallel inputs-outputs. Such ADC, named us multichannel analog-todigital converters based on current mirrors (M ADC CM). Compared with usual converters, for example, reading, a bitby- bit equilibration, and so forth, have a number of advantages: high speed and reliability, simplicity, small power consumption, the big degree of integration in linear and matrix structures. The considered aspects of designing of M_ADC CM in binary codes. Base digit cells (ABC) of such M_ADC CM, series-pipelined are connected in structures, consist from 20-30 CMOS the transistors, one photodiode, have low (1,5-3,5) supply voltage, work in current modes with the maximum values of currents (10-40)μA. Therefore such new principles of realization high-speed low-discharge M_ADC CM have allowed, as have shown modeling experiments, to reach time of transformation less than 20-30 nS at 5-6 bits of a binary code and the general power 1-5 mW. The quantity easily cascadable ABC depends on wordlength ADC, and makes n, and provides quantity of levels of quantization equal N=2n. Such simple enough on structure M ADC CM, having low power consumption CMOS-technologies has made 40 MHz, and can be increased 10 times) and accuracy (Δquantization 156,25nA for I max10μA) characteristics is show. The range can be transformed optical signals, taking into account sensitivity of modern photodetectors makes 20-200 μW in such ADC. M_ADC CM open new prospects for realization linear and matrix (with picture operands) micro photoelectronic structures which are necessary for neural networks, digital optoelectronic processors, neurofuzzy controllers, and so forth.

  8. A low-power cryogenic analog to digital converter in standard CMOS technology

    Science.gov (United States)

    Zhao, Hongliang; Liu, Xinghui

    2013-05-01

    This paper presents a cryogenic successive approximation register (SAR) based analog to digital converter (ADC) in standard 0.35 μm complementary metal oxide semiconductor (CMOS) technology that functions from 300 K (room temperature) down to 20 K. It has been designed to operate in low temperature mid- and far-infrared imaging systems. In order to ensure the circuit performance at the extreme temperatures, a dedicated integral-based comparator architecture is employed. SPICE models have been developed for circuit simulation at 20 K. At 20 K, the experimental results exhibit that the ADC achieves 1.6 LSB maximum differential nonlinearity (DNL), 1.7 LSB maximum integral nonlinearity (INL), and 10.4 effective number of bits (ENOB) at 100 kS/s sampling rate with a current consumption of 75 μA from a 3.3 V supply.

  9. A 8 bits Pipeline Analog to Digital Converter Design for High Speed Camera Application

    CERN Document Server

    Prasetyo, Eri; Ginhac, Nurul Huda Dominique; Paindavoine, Michel

    2008-01-01

    - This paper describes a pipeline analog-to-digital converter is implemented for high speed camera. In the pipeline ADC design, prime factor is designing operational amplifier with high gain so ADC have been high speed. The other advantage of pipeline is simple on concept, easy to implement in layout and have flexibility to increase speed. We made design and simulation using Mentor Graphics Software with 0.6 \\mu m CMOS technology with a total power dissipation of 75.47 mW. Circuit techniques used include a precise comparator, operational amplifier and clock management. A switched capacitor is used to sample and multiplying at each stage. Simulation a worst case DNL and INL of 0.75 LSB. The design operates at 5 V dc. The ADC achieves a SNDR of 44.86 dB. keywords: pipeline, switched capacitor, clock management

  10. Note: Increasing dynamic range of digital-to-analog converter using a superconducting quantum interference device

    Energy Technology Data Exchange (ETDEWEB)

    Nakanishi, Masakazu, E-mail: m.nakanishi@aist.go.jp [Metrology Institute of Japan, National Institute of Advanced Industrial Science and Technology, AIST Central-3, 1-1, Umezono, Tsukuba, Ibaraki 305-8563 (Japan)

    2014-10-15

    Responses of a superconducting quantum interference device (SQUID) are periodically dependent on magnetic flux coupling to its superconducting ring and the period is a flux quantum (Φ{sub o} = h/2e, where h and e, respectively, express Planck's constant and elementary charge). Using this periodicity, we had proposed a digital to analog converter using a SQUID (SQUID DAC) of first generation with linear current output, interval of which corresponded to Φ{sub o}. Modification for increasing dynamic range by interpolating within each interval is reported. Linearity of the interpolation was also based on the quantum periodicity. A SQUID DAC with dynamic range of about 1.4 × 10{sup 7} was created as a demonstration.

  11. Optimization of Power Dissipation in Pipelined Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 姚素英; 赵毅强; 张为; 李树荣; 张生才

    2004-01-01

    Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was 1.217 and 1.317.These results can serve as useful guidelines for designers to minimize the ADC's power consumption.

  12. High precision (14 bit), high density (octal) analog to digital converter for spectroscopy applications

    Science.gov (United States)

    Subramaniam, E. T.; Jain, Mamta; Bhowmik, R. K.; Tripon, Michel

    2008-10-01

    Nuclear and particle physics experiments with large number of detectors require signal processing and data collection strategies that call for the ability to collect large amount of data while not sacrificing the precision and accuracy of the data being collected. This paper deals with the development of a high precision pulse peak detection, analog to digital converter (ADC) module with eight independent channels in plug-in daughter card motherboard model, best suited for spectroscopy experiments. This module provides multiple channels without cross-talk and of 14 bit resolution, while maintaining high density (each daughter card has an area of just 4.2″×0.51″) and exhibiting excellent integral nonlinearity (≤±2 mV or ±0.02% full scale reading) and differential nonlinearity (≤±1%). It was designed, developed and tested, in house, and gives added advantages of cost effectiveness and ease of maintenance.

  13. Design of Multi-Valued Quaternary Based Analog-to-Digital Converter

    Directory of Open Access Journals (Sweden)

    A. H.M.Z. Alam

    2009-01-01

    Full Text Available Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

  14. Low-Actuation Voltage MEMS Digital-to-Analog Converter with Parylene Spring Structures

    Directory of Open Access Journals (Sweden)

    Cheng-Wen Ma

    2015-08-01

    Full Text Available We propose an electrostatically-actuated microelectromechanical digital-to-analog converter (M-DAC device with low actuation voltage. The spring structures of the silicon-based M-DAC device were monolithically fabricated using parylene-C. Because the Young’s modulus of parylene-C is considerably lower than that of silicon, the electrostatic microactuators in the proposed device require much lower actuation voltages. The actuation voltage of the proposed M-DAC device is approximately 6 V, which is less than one half of the actuation voltages of a previously reported M-DAC equipped with electrostatic microactuators. The measured total displacement of the proposed three-bit M-DAC is nearly 504 nm, and the motion step is approximately 72 nm. Furthermore, we demonstrated that the M-DAC can be employed as a mirror platform with discrete displacement output for a noncontact surface profiling system.

  15. Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

    Science.gov (United States)

    Turqueti, Marcos; Prestemon, Soren; Albright, Robert

    LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

  16. High Speed High Resolution Current Comparator and its Application to Analog to Digital Converter

    Science.gov (United States)

    Sridhar, Ranjana; Pandey, Neeta; Bhattacharyya, Asok; Bhatia, Veepsa

    2016-06-01

    This paper introduces a high speed high resolution current comparator which includes the current differencing stage and employs non linear feedback in the gain stage. The usefulness of the proposed comparator is demonstrated by implementing a 3-bit current mode flash analog-to-digital converter (ADC). Simulation program with integrated circuit emphasis (SPICE) simulations have been carried out to verify theoretical proposition and performance parameters of both comparator and ADC are obtained using TSMC 0.18 µm CMOS technology parameters. The current comparator shows a resolution of ±5 nA and a delay of 0.86 ns for current difference of ±1 µA. The impact of process variation on proposed comparator propagation delay has been studied through Monte Carlo simulation and it is found that percentage change in propagation delay in best case is 1.3 % only and in worst case is 9 % only. The ADC exhibits an offset, gain error, differential nonlinearity (DNL) and integral nonlinearity (INL) of 0.102 µA, 0.99, -0.34 LSB and 0.0267 LSB, respectively. The impact of process variation on ADC has also been studied at different process corners.

  17. A Review: Compensation of Mismatches in Time Interleaved Analog to Digital Converters

    Directory of Open Access Journals (Sweden)

    Shivlal Mishra

    2014-08-01

    Full Text Available The execution of today's correspondence frameworks is exceedingly subject to the utilized Analog-to-Digital converters (ADCs, and with a specific end goal to give more flexibility and exactness to the developing correspondence innovations, superior-ADCs are needed. In this respect, the time-interleaved operation of an exhibit of ADCs (TI-ADC might be a sensible result. A TI-ADC can build its throughput by utilizing M channel ADCs or sub converters in parallel and examining the data motion in a period-interleaved way. In any case, the execution of a TI-ADC gravely suffers from the bungles around the channel ADCs. In this paper we survey the advancement in the configuration of low-intricacy advanced remedy structures and calculations for time-interleaved ADCs in the course of the most recent five years. We devise a discrete-time model, state the outline issue, and finally infer the calculations and structures. Specifically, we examine proficient calculations to outline time-differing remedy filters and additionally iterative structures using polynomial based filters. Thusly, the remuneration structure may be utilized to repay time-differing recurrence reaction befuddles in time-interleaved ADCs, and in addition to remake uniform examples from nonuniformly tested indicators. We examine the recompense structure, research its execution, and exhibit requisition zones of the structure through various illustrations. At long last, we give a standpoint to future examination questions.

  18. Basic Theoretical Model and Sampling Criteria for Time-Interleaved Photonic Analog-to-Digital Converters

    CERN Document Server

    Su, Feiran; Zou, Weiwen; Chen, Jianping

    2016-01-01

    In this paper, we present a basic model for time-interleaved photonic analog-to-digital converter (TIPADC) and analyze its linear, nonlinear, and noise performance. The basic operation mechanism of TIPADC is illustrated and the linear performance is analyzed in frequency domain. The mathematical expressions and the output of the system are presented in each processing step. We reveal that photonic sampling folds the whole spectrum of input signal in a narrow band, which enables the analog bandwidth of a TIPADC to be much higher than the bandwidth of back-end electronics. The feasible regions of the system is obtained in terms of system frequency response, and a set of sampling criteria determining the basic requirements to the system are summarized for typical applications. The results show that the global minimum feasible bandwidth of back-end electronics is the half of single channel sampling rate when the bandwidth of photonic sampling pulse is comparable to input signal frequency. The amplitude and phase ...

  19. Power Scaling in High Speed Analog-to-Digital Converters using Photonic Time Stretch Technique

    CERN Document Server

    Gupta, Shalabh; Walden, Robert H; Jalali, Bahram

    2009-01-01

    Factors that contribute to the rapid increase in power dissipation as a function of input bandwidth in high speed electronic Analog-to-Digital Converters (ADCs) are discussed. We find that the figure of merit (FOM), defined as the energy required per conversion step, increases linearly with bandwidth for high-speed ADCs with moderate to high resolution, or equivalently, the power dissipation increases quadratically. It is shown that by use of photonic time-stretch technique, it is possible to have ADCs in which this FOM remains constant for up to 10 GHz input RF frequency. Using this technique, it is also possible to overcome the barrier to achieving high resolution caused by clock jitter and speed limitations of electronics in such ADCs. Use of optics is actively being pursued for reducing power dissipation and achieving higher data-rates for board-level and chip-level serial communication links. In the same manner, we expect that optics will also help in reducing power dissipation in high-speed ADCs in addi...

  20. A New Digital to Analog Converter Based on Low-Offset Bandgap Reference

    Directory of Open Access Journals (Sweden)

    Jinpeng Qiu

    2017-01-01

    Full Text Available This paper presents a new 12-bit digital to analog converter (DAC circuit based on a low-offset bandgap reference (BGR circuit with two cascade transistor structure and two self-contained feedback low-offset operational amplifiers to reduce the effects of offset operational amplifier voltage effect on the reference voltage, PMOS current-mirror mismatch, and its channel modulation. A Start-Up circuit with self-bias current architecture and multipoint voltage monitoring is employed to keep the BGR circuit working properly. Finally, a dual-resistor ladder DAC-Core circuit is used to generate an accuracy DAC output signal to the buffer operational amplifier. The proposed circuit was fabricated in CSMC 0.5 μm 5 V 1P4M process. The measured differential nonlinearity (DNL of the output voltages is less than 0.45 LSB and integral nonlinearity (INL less than 1.5 LSB at room temperature, consuming only 3.5 mW from a 5 V supply voltage. The DNL and INL at −55°C and 125°C are presented as well together with the discussion of possibility of improving the DNL and INL accuracy in future design.

  1. Robust symmetrical number system preprocessing for minimizing encoding errors in photonic analog-to-digital converters

    Science.gov (United States)

    Arvizo, Mylene R.; Calusdian, James; Hollinger, Kenneth B.; Pace, Phillip E.

    2011-08-01

    A photonic analog-to-digital converter (ADC) preprocessing architecture based on the robust symmetrical number system (RSNS) is presented. The RSNS preprocessing architecture is a modular scheme in which a modulus number of comparators are used at the output of each Mach-Zehnder modulator channel. The number of comparators with a logic 1 in each channel represents the integer values within each RSNS modulus sequence. When considered together, the integers within each sequence change one at a time at the next code position, resulting in an integer Gray code property. The RSNS ADC has the feature that the maximum nonlinearity is less than a least significant bit (LSB). Although the observed dynamic range (greatest length of combined sequences that contain no ambiguities) of the RSNS ADC is less than the optimum symmetrical number system ADC, the integer Gray code properties make it attractive for error control. A prototype is presented to demonstrate the feasibility of the concept and to show the important RSNS property that the largest nonlinearity is always less than a LSB. Also discussed are practical considerations related to multi-gigahertz implementations.

  2. High voltage, high resolution, digital-to-analog converter for driving deformable mirrors

    Science.gov (United States)

    Kittredge, Jeffrey

    Digital-to-analog converters with a range over 50 volts are required for driving micro-electro mechanical system deformable mirrors used in adaptive optics. An existing tested and deployed DM driver has 1024 channels and resolution of 15mV per Least Significant Bit. DMs used in the search for exoplanets require 3mV per LSB resolution. A technique is presented to employ a secondary high resolution and low voltage DAC which has for it's ground the output of the high voltage DAC. The entire system then has the range of high voltage DAC yet the resolution of the low voltage DAC. A method for providing signal and power to the floating system is given. Rudimentary micro controller firmware and also PC software is presented to achieve complete functionality. The technique uses all off-the-shelf components. Resolution of 1.6mV per LSB, 60V range and 36mW of power per channel is achieved.

  3. Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS Analog to Digital Converter

    Directory of Open Access Journals (Sweden)

    Arun Kumar Sunaniya

    2013-07-01

    Full Text Available This work presents three different approaches which eliminates the resistor ladder completely and hencereduce the power demand drastically of a Analog to Digital Converter. The first approach is SwitchedInverter Scheme (SIS ADC; The test result obtained for it on 45nm technology indicates an offset error of0.014 LSB. The full scale error is of -0.112LSB. The gain error is of 0.07 LSB, actual full scale range of0.49V, worst case DNL & INL each of -0.3V. The power dissipation for the SIS ADC is 207.987 μwatts;Power delay product (PDP is 415.9 fWs, and the area is 1.89μm2. The second and third approaches areclocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in powerdissipation as 57.5% & 71% respectively. Whereas PDP is 229.7 fWs and area is 0.05 μm2 for Clocked SISADC and 107.3 fWs & 1.94 μm2 for Sleep transistor SIS ADC.

  4. Design of Improved Resistor Less 45NM Switched Inverter Scheme (SIS Analog to Digital Converter

    Directory of Open Access Journals (Sweden)

    Arun Kumar Sunaniya

    2013-06-01

    Full Text Available This work presents three different approaches which eliminates the resistor ladder completely and henc e reduce the power demand drastically of a Analog to Digital Converter. The first approach is Switched Inverter Scheme (SIS ADC; The test result obtained for it on 45nm technology indicates an offset erro r of 0.014 LSB. The full scale error is of -0.112LSB. Th e gain error is of 0.07 LSB, actual full scale rang e of 0.49V, worst case DNL & INL each of -0.3V. The powe r dissipation for the SIS ADC is 207.987 μ watts; Power delay product (PDP is 415.9 fWs, and the are a is 1.89μ m2. The second and third approaches are clocked SIS ADC and Sleep transistor SIS ADC. Both of them show significant improvement in power dissipation as 57.5% & 71% respectively. Whereas PD P is 229.7 fWs and area is 0.05 μ m2 for Clocked SIS ADC and 107.3 fWs & 1.94 μ m2 for Sleep transistor S IS ADC.

  5. A Modulated Hybrid Filter Bank for Wide-Band Analog-to-Digital Converters

    Directory of Open Access Journals (Sweden)

    Chunyan Yuan

    2014-04-01

    Full Text Available It is difficult to use a single analog-to-digital conversion (ADC to satisfy the requirements for conversion of an ultra-wideband signal. A parallel architecture for high bandwidth ADC, named cosine modulated hybrid filter bank, is presented to address this problem. First, the proposed architecture shifts the input signal spectrum by means of mixers. The modulated signal is channelized into smaller frequency subband signals using identical lowpass analog filters. Then the subband signals are digitized through identical narrowband ADCs, respectively. Finally, the digitized signals are up-sampled, then filtered and combined to reconstruct the digital representation of the original wide-band input signal. The digital filters are designed to use the eigenfilter method based on total least squares error criterion. Since the sample-and-hold circuits needed are only identical narrowband baseband circuits, the simplicity of the system makes the design easier and cheaper. Several design examples are used to illustrate the performance of the proposed system.

  6. Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

    Science.gov (United States)

    Aytar, Oktay

    2015-09-01

    This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (-0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

  7. Analysis of the resolution-bandwidth-noise trade-off in wavelength-based photonic analog-to-digital converters.

    Science.gov (United States)

    Stigwall, Johan; Galt, Sheila

    2006-06-20

    The performance of wavelength-based photonic analog-to-digital converters (ADCs) is theoretically analyzed in terms of resolution and bandwidth as well as of noise tolerance. The analysis applies to any photonic ADC in which the analog input signal is converted into the wavelength of an optical carrier, but special emphasis is put on the spectrometerlike setup in which the wavelength is mapped to a spatial spot position. The binary output signals are then retrieved by an array of fan-out diffractive optical elements that redirect the beam onto the correct detectors. In particular, the case when the input signal controls the wavelength directly such that it will chirp in frequency during each sampling pulse or interval is studied. This chirping obviously broadens the spot on the diffractive optical element array; the effect of this broadening on noise tolerance and comparator accuracy is analytically analyzed, and accurate numerical calculations of the probability of error are presented.

  8. Analog to Digital Conversion in Physical Measurements

    CERN Document Server

    Kapitaniak, T; Feudel, U; Grebogi, C

    1999-01-01

    There exist measuring devices where an analog input is converted into a digital output. Such converters can have a nonlinear internal dynamics. We show how measurements with such converting devices can be understood using concepts from symbolic dynamics. Our approach is based on a nonlinear one-to-one mapping between the analog input and the digital output of the device. We analyze the Bernoulli shift and the tent map which are realized in specific analog/digital converters. Furthermore, we discuss the sources of errors that are inevitable in physical realizations of such systems and suggest methods for error reduction.

  9. A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

    Institute of Scientific and Technical Information of China (English)

    LI Dan; RONG Men-tian; MAO Jun-fa

    2007-01-01

    A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC).The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge.Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers.The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

  10. Performance requirements for analog-to-digital converters in wideband reconfigurable radios

    Science.gov (United States)

    Naughton, David; Baldwin, Gerard; Farrell, Ronan

    2005-06-01

    With the current trend towards software defined radio, several candidate architectures for the analog receiver front-end have been presented. A common proposal for software defined reconfigurable radio is to develop a wideband ADC and utilise this for capturing a large segment of the spectrum. This would enable the subsequent signal processing operations of channel selection and data extraction to be carried out by a digital processor. This would allow the radio to be reconfigured by simply changing the software. In analysis of these systems, powerful neighbouring signals, or blockers, are considered but it has been conveniently assumed that suitable dynamic range will be available at the ADC. This is an acceptable assumption in narrowband systems where automatic gain control and analogue channel select filters can be used, but is not appropriate for a wideband system. In this paper we present an analysis based on bit-error-rates (BER) which shows the effect of blockers in a wideband architecture on the performance of the communication link and on the dynamic range requirements of the ADC.

  11. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel

    2017-01-01

    This textbook is appropriate for use in graduate-level curricula in analog-to-digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters. It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation. This book presents an overview of the state of the art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, third edition emphasizes novel calibration concepts, the specific requirements of new systems, the consequences of 22-nm technology and the need for a more statistical approach to accuracy. Pedagogical enhancements to this edition include additional, new exercises, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner’s perspective, wherever appropriate. Considerable background information and practical tips, from designing a PCB, to lay-o...

  12. The initial characterization of a revised 10-Gsps analog-to-digital converter board for radio telescopes

    Science.gov (United States)

    Jiango, Homin; Liuo, Howard; Guzzino, Kim

    2016-07-01

    In this study, the design of a 4 bit, 10-gigasamples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was revised, manufactured, and tested. It is used for digitizing radio telescopes. An Adsantec ANST7120-KMA flash ADC chip was used, as in the original design. Associated with the field-programmable gate array platform developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the developed PCBA provides data acquisition systems with a wider bandwidth and simplifies the intermediate frequency section. The current version of the PCBA exhibits an analog bandwidth of up to 10 GHz (3 dB loss), and the chip exhibits an analog bandwidth of up to 18 GHz. This facilitates second and third Nyquist sampling. The following worstcase performance parameters were obtained from the revised PCBA at over 5 GHz: spurious-free dynamic range of 12 dB, signal-to-noise and distortion ratio of 2 dB, and effective number of bits of 0.7. The design bugs in the ADC chip caused the poor performance. The vendor created a new batch run and confirmed that the ADC chips of the new batch will meet the specifications addressed in its data sheet.

  13. 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme

    Directory of Open Access Journals (Sweden)

    Lei Sun

    2014-08-01

    Full Text Available This study presents a successive approximation register analog-to-digital converter with an energy-efficient switching scheme. A split-most significant bit capacitor array is used with a least significant bit-down switching scheme. Compared with the conventional binary-weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal-to-distortion-and-noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure-of-merit is 44.1 fJ/conversion-step.

  14. FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

    DEFF Research Database (Denmark)

    Taeed, Fazel; Salam, Z.; Ayob, S.

    2012-01-01

    for the control surface to be approximated by a piecewise linear. It is shown that, despite the simplicity of SIFLC, its control performance is almost equivalent to that of the conventional FLC. As a proof of concept, the SIFLC is implemented using the Altera EP2C35F672C6N field-programmable gate array (FPGA......-to-digital converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the FPGA. © 2011 IEEE....

  15. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    Science.gov (United States)

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components.

  16. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

    Institute of Scientific and Technical Information of China (English)

    Zhang Zhengping; Wang Yonglu; Huang Xingfa; Shen Xiaofeng; Zhu Can; Zhang Lei; Yu Jinshan; Zhang Ruitao

    2011-01-01

    A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented.The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

  17. Designer-Driven Topology Optimization for Pipelined Analog to Digital Converters

    CERN Document Server

    Chien, Yu-Tsun; Lou, Jea-Hong; Ma, Gin-Kou; Rutenbar, Rob A; Mukherjee, Tamal

    2011-01-01

    This paper suggests a practical "hybrid" synthesis methodology which integrates designer-derived analytical models for system-level description with simulation-based models at the circuit level. We show how to optimize stage-resolution to minimize the power in a pipelined ADC. Exploration (via detailed synthesis) of several ADC configurations is used to show that a 4-3-2... resolution distribution uses the least power for a 13-bit 40 MSPS converter in a 0.25 $\\mu$m CMOS process.

  18. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    Science.gov (United States)

    Weidong, Yang; Jiandong, Zang; Tiehu, Li; Pu, Luo; Jie, Pu; Ruitao, Zhang; Chao, Chen

    2015-10-01

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB & INL less than ±4.3 LSB after the chip is calibrated.

  19. Modeling of quantization noise in linear analog-to-digital converter

    Science.gov (United States)

    Švihlík, Jan; Fliegel, Karel

    2013-09-01

    Quantization noise is present in all the current digital imaging systems, therefore its understanding and modeling is crucial for optimization of image reconstruction techniques. Hence, this paper deals with modeling of the quantization noise. We exploit the undecimated wavelet transform (UWT) for signal representation. We assume that the quantization noise in the spatial domain can be seen as additive, white and uniformly distributed. Hence, the UWT causes the transform of noise distribution due to weighted sum of noise samples and filter coefficients. From the known quantization step we are able to estimate suitable moments of noise uniform probability density function (PDF). These moments then could be directly evaluated in the undecimated wavelet domain using the derived equations. The presented algorithm gives the a priori information about the quantization noise and can be used for the suppression of it.

  20. An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

    Directory of Open Access Journals (Sweden)

    A.R.Ashwatha

    2012-05-01

    Full Text Available This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder.This approach explores the use of a systematically incorporated input offset voltage in a differentialamplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

  1. An approach to design Flash Analog to Digital Converter for High Speed and Low power Applications

    Directory of Open Access Journals (Sweden)

    P.RAJESWARI

    2012-04-01

    Full Text Available This paper proposes the Flash ADC design using Quantized Differential Comparator and fat tree encoder.This approach explores the use of a systematically incorporated input offset voltage in a differential amplifier for quantizing the reference voltages necessary for Flash ADC architectures, therefore eliminating the need for a passive resistor array for the purpose. This approach allows very small voltage comparison and complete elimination of resistor ladder circuit. The thermometer code-to-binary code encoder has become the bottleneck of the ultra-high speed flash ADCs. In this paper, the fat tree thermometer code to-binary code encoder is used for the ultra high speed flash ADCs. The simulation and the implementation results shows that the fat tree encoder performs the commonly used ROM encoder in terms of speed and power for the 6 bit CMOS flash ADC case. The speed is improved by almost a factor of 2 when using the fat tree encoder, which in fact demonstrates the fat tree encoder and it is an effective solution for the bottleneck problem in ultra-high speed ADCs.The design has been carried out for the 0.18um technology using CADENCE tool.

  2. Optimal design of a low-loss 2-bit electrooptic analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    ZHANG Chang-ming; LIAO Yi-tao; LIU Yong-zhi; DAI Ji-zhi

    2005-01-01

    The structure of the optical waveguide of 2-bit electrooptic A/D converter with proton-exchange micro prisms is optimized by the finite-difference beam propagation method (FD-BPM). The electrode parameters of the converter are optimized by conformal mapping. The optimal parameters are a half-wave voltage of Vπ= 4.5 V and a bandwidth of Δf=1.4 GHz.A normalized transmitted power of 69.75% is obtained by FD-BMP and the output waveguide gap is 300 μm.

  3. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J. M

    2013-01-01

    This textbook is appropriate for use in graduate-level curricula in analog to digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters.  It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation.  This book presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, second edition emphasizes novel calibration concepts, the specific requirements of new systems, the consequences of 45-nm technology and the need for a more statistical approach to accuracy.  Pedagogical enhancements to this edition include more than twice the exercises available in the first edition, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner’s perspective, wherever appropriate.  Considerable background information and pr...

  4. Analog approach to mixed analog-digital circuit simulation

    Science.gov (United States)

    Ogrodzki, Jan

    2013-10-01

    Logic simulation of digital circuits is a well explored research area. Most up-to-date CAD tools for digital circuits simulation use an event driven, selective trace algorithm and Hardware Description Languages (HDL), e.g. the VHDL. This techniques enable simulation of mixed circuits, as well, where an analog part is connected to the digital one through D/A and A/D converters. The event-driven mixed simulation applies a unified, digital-circuits dedicated method to both digital and analog subsystems. In recent years HDL techniques have been also applied to mixed domains, as e.g. in the VHDL-AMS. This paper presents an approach dual to the event-driven one, where an analog part together with a digital one and with converters is treated as the analog subsystem and is simulated by means of circuit simulation techniques. In our problem an analog solver used yields some numerical problems caused by nonlinearities of digital elements. Efficient methods for overriding these difficulties have been proposed.

  5. A low-power piecewise linear analog to digital converter for use in particle tracking

    Energy Technology Data Exchange (ETDEWEB)

    Valencic, V.; Deval, P. [MEAD Microelectronics S.A., St. Sulpice (Switzerland)]|[EPFL, Lausanne (Switzerland). Electronics Labs.; Anghinolfi, F. [CERN, Geneva (Switzerland); Bonino, R.; Marra, D. La; Kambara, Hisanori [Univ. of Geneva (Switzerland)

    1995-08-01

    This paper describes a low-power piecewise linear A/D converter. A 5MHz {at} 5V with 25mW power consumption prototype has been implemented in a 1.5{micro}m CMOS process. The die area excluding pads is 5mm{sup 2}. 11-bit absolute accuracy is obtained with a new DC offset plus charge injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments.

  6. A digital calibration technique for an ultra high-speed wide-bandwidth folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology*

    Institute of Scientific and Technical Information of China (English)

    Yu Jinshan; Zhang Ruitao; Zhang Zhengping; Wang Yonglu; Zhu Can; Zhang Lei; Yu Zhou; Han Yong

    2011-01-01

    A digital calibration technique for an ultra high-speed folding and interpolating analog-to-digital converter in 0.18-μm CMOS technology is presented. The similar digital calibration techniques are taken for high 3-bit flash converter and low 5-bit folding and interpolating converter, which are based on well-designed calibration reference, calibration DAC and comparators. The spice simulation and the measured results show the ADC produces 5.9 ENOB with calibration disabled and 7.2 ENOB with calibration enabled for high-frequency wide-bandwidth analog input.

  7. 数字信道化技术中ADC的性能分析%Performance Analysis of Analog-to-Digital Converters in Digital Channelization Techniques

    Institute of Scientific and Technical Information of China (English)

    马丽川; 潘亚汉; 袁方; 刘欣

    2011-01-01

    In the field of satellite communication,digital channelization techniques are used more and more widely.The analog-to-digital converter,one part of the digital channelizer,plays a great important role in the digital channelization techniques.Based on the elementary theory and performance of ADC,the effect on digital modulated signals exerted by the different number of quantization bit are discussed and simulated.%在卫星通信系统中,数字信道化技术的应用越来越广泛,而模数转换器(ADC)作为数字信道化器前端不可缺少的一部分起着至关重要的作用。基于ADC基本原理和性能,仿真分析了在ADC量化位数不同的条件下,ADC对数字已调信号解调性能的影响。

  8. Pixel-level Analog-To-Digital Converters for Hybrid Pixel Detectors with energy sensitivity

    NARCIS (Netherlands)

    San Segundo Bello, David; Nauta, Bram; Visschers, Jan

    2000-01-01

    Single-photon counting hybrid pixel detectors have shown to be a valid alternative to other types of X-ray imaging devices due to their high sensitivity, low noise, linear behavior and wide dynamic range. One important advantage of these devices is the fact that detector and readout electronics are

  9. Design of analog-to-digital converters for energy sensitive hybrid pixel detectors

    NARCIS (Netherlands)

    San Segundo Bello, David; Nauta, Bram; Visschers, Jan

    2001-01-01

    An important feature of hybrid semiconductor pixel detectors is the fact that detector and readout electronics are manufactured separately, allowing the use of industrial state-of-the-art CMOS processes to manufacture the readout electronics. As the feature size of these processes decreases, faster

  10. PIC microcontroller based external fast analog to digital converter to acquire wide-lined solid NMR spectra by BRUKER DRX and Avance-I spectrometers.

    Science.gov (United States)

    Koczor, Bálint; Rohonczy, János

    2015-01-01

    Concerning many former liquid or hybrid liquid/solid NMR consoles, the built in Analog-to-Digital Converters (ADCs) are incapable of digitizing the fids at sampling rates in the MHz range. Regarding both strong anisotropic interactions in the solid state and wide chemical shift dispersion nuclei in solution phase such as (195)Pt, (119)Sn, (207)Pb etc., the spectrum range of interest might be in the MHz range. As determining the informative tensor components of anisotropic NMR interactions requires nonlinear fitting over the whole spectrum including the asymptotic baseline, it is prohibited by low sampling rates of the ADCs. Wide spectrum width is also useful in solution NMR, since windowing of wide chemical shift ranges is avoidable. We built an external analog to digital converter with 10 MHz maximal sampling rate, which can work simultaneously with the built in ADC of the spectrometer. The ADC was tested on both Bruker DRX and Avance-I NMR consoles. In addition to the analog channels it only requires three external digital lines of the NMR console. The ADC sends data to PC via USB. The whole process is controlled by software written in JAVA which is implemented under TopSpin.

  11. Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

    Institute of Scientific and Technical Information of China (English)

    Sheng-Gang Dong; Xiao-Yang Wang; Hua Fan; Jun-Feng Gao; Qiang Li

    2013-01-01

    This paper makes a review of state-of-the-arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330μW.

  12. A Low Power Op Amp for 3-Bit Digital to Analog Converter in 0.18 µm CMOS Process

    Directory of Open Access Journals (Sweden)

    Noor A.B.A. Taib

    2013-03-01

    Full Text Available Digital to (DAC is used to get analog voltage corresponding to input digital data in VLSI circuit design with greater integration levels. However, providing linear current and voltage outputs with the use of strictly CMOS devices presents the need for a low power operational amplifier (op-amp circuit. In this research, the analysis of op-amp circuit for 3-bit DAC is illustrated. In order to reduce the power dissipation, weighted resistor is utilized in the proposed design. To design the op-amp circuit for 3-bit DAC, the design has been implemented in CEDEC 0.18 µm CMOS process. The simulated result shows that, under 8 V as the supply voltage the total power dissipation for the proposed DAC is 43.6 nW. Moreover, 143.17 µm is found as the total chip area of the designed op-amp circuit for 3-bit DAC.

  13. A 1.8 V 1.1 MS/s 96.1 dB-SFDR successive approximation register analog-to-digital converter with calibration

    Institute of Scientific and Technical Information of China (English)

    Chi Yingying; Li Dongmei

    2013-01-01

    A power efficient 96.1 dB-SFDR successive approximation register (SAR) analog-to-digital converter (ADC) with digital calibration aimed at capacitor mismatch is presented.The prototype is fabricated in a 0.18 μm CMOS.The charge redistribution (CR) design and an extra △Σ modulator for capacitance measurement are employed.With a 1.1 MS/s sampling rate,the ADC achieves 70.8 dB SNDR and the power consumption is 2.1 mW.

  14. Modeling and post-correction of pipeline analog-digital converters

    OpenAIRE

    Medawar, Samer

    2010-01-01

    Integral nonlinearity (INL) for pipelined analog-digital converters (ADCs) operating at radio frequency is measured and characterized. A parametric model for the INL of pipelined ADCs is proposed and the corresponding least-squares problem is formulated and solved. The estimated model parameters are used to design a post-correction block in order to compensate the pipeline ADC. The INL is modeled both with respect to the ADC output code k and the frequency stimuli, which is dynamic modeling. ...

  15. Flexible Architecture of Ultra-Low-Power Current-Mode Interleaved Successive Approximation Analog-to-Digital Converter for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Rafał Długosz

    2007-01-01

    Full Text Available A novel 8-bit current mode interleaved successive approximation (SAR analog-digital converter (ADC has been proposed. The proposed converter architecture is very flexible. Using two control DC voltages and one reference current, the converter can be tuned to work with different sampling rates, number of bits of resolution, and power consumption levels. Due to its very low-power consumption and flexibility, the converter is particularly suitable for application in wireless sensor networks. Compared to other solutions presented in the literature, the proposed converter achieves very high figure of merit (FOM value due to numerous low-power circuit innovations utilized in its design. The circuit has been implemented in CMOS 0.18 μm technology. Minimum energy consumption has been found to be in a 25–250 kS/s range (for clock sampling frequency in a 200 kHz--2 MHz range for a single SAR section with the corresponding power dissipation varying from 220 nW to 560 nW for 0.55 V power supply.

  16. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  17. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    Science.gov (United States)

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-11-17

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  18. 光学Sigma-Delta模数转换器的研究进展%Research and development of optical sigma-delta analog to digital converter

    Institute of Scientific and Technical Information of China (English)

    周雯; 王目光; 李博

    2012-01-01

    Optical analog to digital conversion techniques have been the developing trend of analog to digital converter(ADC) with high conversion rate and high bit accuracy in recent years. As a kind of optical ADC, optical Sigma-Delta ADC has distinguished advantages such as high conversion accuracy and simple analog circuitry. Basic principle of optical Sigma-Delta ADC is introduced. The structures of several typical optical Sigma-Delta ADCs are described detailedly.Finally the merits and demerits of optical Sigma-Delta ADCs with different structures are summed up.%采用光学模数转换技术已经成为高转换速率、高比特精度模数转换器(ADC)的发展趋势.光学Sigma-Delta ADC作为一种光学ADC,具有转换精度高和模拟电路简单等显著优点.介绍了光学Sigma-Delta ADC的基本原理,详细阐述了几种典型的光学Sigma-Delta ADC的系统结构,对不同结构的光学Sigma-Delta ADC的优缺点进行了归纳总结.

  19. Input-Dependent Integral Nonlinearity Modeling for Pipelined Analog-Digital Converters

    OpenAIRE

    Samer Medawar; Peter Händel; Niclas Björsell; Magnus Jansson

    2010-01-01

    Integral nonlinearity (INL) for pipelined analog-digital converters (ADCs) operating at RF is measured and characterized. A parametric model for the INL of pipelined ADCs is proposed, and the corresponding least-squares problem is formulated and solved. The INL is modeled both with respect to the converter output code and the frequency stimuli, which is dynamic modeling. The INL model contains a static and a dynamic part. The former comprises two 1-D terms in ADC code that are a sequence of z...

  20. 100 gigasamples per second 12 bits optoelectronic analog-to-digital converter design and implementation based on cellular polyphase-sampling architecture

    Science.gov (United States)

    Villa-Angulo, Carlos

    The next generation digital information systems such as high performance computers, multigigabit/sec communication networks, distributed sensors, three dimensional digital imaging systems etc, will require analog-to-digital converters (ADCs) with high sampling rates exceeding 10 Gigasamples per second (GSPS) and high bit resolution of at least 10 bits. Such performance criteria are difficult to achieve with silicon electronics technology because the switching speeds peak at about 10-20GHz. Also, timing jitters, amplitude fluctuations, phase noise, thermal noise, and harmonic distortion, all contribute to reductions in ADC bit resolution as sampling rate increases. Photonics ADCs are rapidly emerging as the enabling technologies for high-performance digital signal processing systems. For this technology, high optical pulses repetition rate (in the order of GHz) with low time jitter and pulse width in the femtoseconds regime are the major attractive characteristics of optical sources. In this dissertation work, a novel 102.4 GSPS 12-bit optoelectronic analog-to-digital converter architecture that is based on a Cellular Polyphase-Sampling architecture is introduced. First, a 102.4 GHz all-optical clock was designed and implemented using a femtosecond laser source and passive optical components. Second, a novel optoelectronic architecture for optical sampling and parallel demultiplexing of different phases (polyphase) of an input analog signal is presented. The optoelectronic sampling and demultiplexing architecture is composed by 20 optoelectronic subcircuit referred as "OE-Cell"; these have been designed and implemented using optical passive components and InGaAs PIN photodiodes. A unique feature of this approach is that the optically sampled RF signal always remains in the electrical domain and thus eliminates the need for electrical-to-optical and optical-to-electrical conversions. The electrical-in to electrical-out transfer functions of the sampling and

  1. A low-power inverter-based CMOS level-crossing analog-to-digital converter for low-frequency biosignal sensing

    Science.gov (United States)

    Tanaka, Suiki; Niitsu, Kiichi; Nakazato, Kazuo

    2016-03-01

    Low-power analog-to-digital conversion is a key technique for power-limited biomedical applications such as power-limited continuous glucose monitoring. However, a conventional uniform-sampling analog-to-digital converter (ADC) is not suitable for nonuniform biosignals. A level-crossing ADC (LC-ADC) is a promising candidate for low-power biosignal processing because of its event-driven properties. The LC-ADC acquires data by level-crossing sampling. When an input signal crosses the threshold level, the LC-ADC samples the signal. The conventional LC-ADC employs a power-hungry comparator. In this paper, we present a low-power inverter-based LC-ADC. By adjusting the threshold level of the inverter, it can be used as a threshold-fixed window comparator. By using the inverter as an alternative to a comparator, power consumption can be markedly reduced. As a result, the total power consumption is successfully reduced by 90% of that of previous LC-ADC. The inverter-based LC-ADC was found to be very suitable for use in power-limited biomedical devices.

  2. A Low-cost 4 Bit, 10 Giga-samples-per-second Analog-to-digital Converter Printed Circuit Board Assembly for FPGA-based Backends

    Science.gov (United States)

    Jiang, Homin; Yu, Chen-Yu; Kubo, Derek; Chen, Ming-Tang; Guzzino, Kim

    2016-11-01

    In this study, a 4 bit, 10 giga-samples-per-second analog-to-digital converter (ADC) printed circuit board assembly (PCBA) was designed, manufactured, and characterized for digitizing radio telescopes. For this purpose, an Adsantec ANST7120A-KMA flash ADC chip was used. Together with the field-programmable gate array platform, developed by the Collaboration for Astronomy Signal Processing and Electronics Research community, the PCBA enables data acquisition with a wide bandwidth and simplifies the intermediate frequency section. In the current version, the PCBA and the chip exhibit an analog bandwidth of 10 GHz (3 dB loss) and 20 GHz, respectively, which facilitates second, third, and even fourth Nyquist sampling. The following average performance parameters were obtained from the first and second Nyquist zones of the three boards: a spurious-free dynamic range of 31.35/30.45 dB, a signal-to-noise and distortion ratio of 22.95/21.83 dB, and an effective number of bits of 3.65/3.43, respectively.

  3. Multirate Formulation for Mismatch Sensitivity Analysis of Analog-to-Digital Converters That Utilize Parallel ΣΔ-Modulators

    Directory of Open Access Journals (Sweden)

    Per Löwenborg

    2008-02-01

    Full Text Available A general formulation based on multirate filterbank theory for analog-to-digital converters using parallel sigmadelta modulators in conjunction with modulation sequences is presented. The time-interleaved modulators (TIMs, Hadamard modulators (HMs, and frequency-band decomposition modulators (FBDMs can be viewed as special cases of the proposed description. The usefulness of the formulation stems from its ability to analyze a system's sensitivity to aliasing due to channel mismatch and modulation sequence level errors. Both Nyquist-rate and oversampled systems are considered, and it is shown how the matching requirements between channels can be reduced for oversampled systems. The new formulation is useful also for the derivation of new modulation schemes, and an example is given of how it can be used in this context.

  4. Low-Power, Low-Voltage Analog to Digital ΣΔ

    DEFF Research Database (Denmark)

    Wismar, Ulrik Sørensen

    2007-01-01

    implementations of audio band modulators used as CMOS analog to digital converters. The intended application is hearing aids where analog to digital converters are used to convert the preamplied signal from a microphone into a digital signal which is fed into a microprocessor. A hearing aid is battery driven...

  5. Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture

    Directory of Open Access Journals (Sweden)

    C. Villa-Angulo

    2013-01-01

    Full Text Available In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexingarchitecture for optoelectronics analog-to-digital converters (OADCs. The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, anddemultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in toelectrical-out data format is maintained through the sampling, demultiplexing and quantization processes of thearchitecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. Weexperimentally demonstrate a 10.24 giga samples per second (GS/s, 12-bit resolution OADC system comprising theoptically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on theOADC yielded an effective bit resolution (ENOB of 10.3 bits, spurious free dynamic range (SFDR of -32 dB andsignal-to-noise and distortion ratio (SNDR of 63.7 dB.

  6. High-speed analog-to-digital conversion

    CERN Document Server

    Demler, Michael J

    1991-01-01

    This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, ""

  7. ANALOG-TO-DIGITAL CONVERSION OF SIGNALS WITH ANGULAR MANIPULATION FOR SOFTWARE DEFINED RADIO SYSTEMS

    OpenAIRE

    A. Y. Tsvetkov; A. G. Prygunov; N. D. Anikeichik; I. P. Rybalko; N. A. Osipov

    2016-01-01

    The paper deals with the search of ways for speeding up and accuracy increase of conversion of modern analog-to-digital converters. The main shortcomings interfering a solution of this task including the field of optoelectronic analog-to-digital converters are provided. The proposed solution gives the chance to increase high-speed performance of analog-to-digital converters on the basis of holographic interferometry principles without reducing their accuracy of conversion. The optical scheme ...

  8. A digital-to-analog conversion circuit using third-order polynomial interpolation

    Science.gov (United States)

    Dotson, W. P., Jr.; Wilson, J. H.

    1972-01-01

    Zero- and third-order digital-to-analog conversion techniques are described, and the theoretical error performances are compared. The design equations and procedures for constructing a third-order digital-to-analog converter by using analog design elements are presented. Both a zero- and a third-order digital-to-analog converter were built, and the performances are compared with various signal inputs.

  9. Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

    Science.gov (United States)

    Tavousi, Alireza; Mansouri-Birjandi, Mohammad Ali; Saffari, Mehdi

    2016-09-01

    Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring's nonlinear refractive index, and the ring's length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.

  10. Design challenges of EO polymer based leaky waveguide deflector for 40 Gs/s all-optical analog-to-digital converters

    Science.gov (United States)

    Hadjloum, Massinissa; El Gibari, Mohammed; Li, Hongwu; Daryoush, Afshin S.

    2016-08-01

    Design challenges and performance optimization of an all-optical analog-to-digital converter (AOADC) is presented here. The paper addresses both microwave and optical design of a leaky waveguide optical deflector using electro-optic (E-O) polymer. The optical deflector converts magnitude variation of the applied RF voltage into variation of deflection angle out of a leaky waveguide optical beam using the linear E-O effect (Pockels effect) as part of the E-O polymer based optical waveguide. This variation of deflection angle as result of the applied RF signal is then quantized using optical windows followed by an array of high-speed photodetectors. We optimized the leakage coefficient of the leaky waveguide and its physical length to achieve the best trade-off between bandwidth and the deflected optical beam resolution, by improving the phase velocity matching between lightwave and microwave on one hand and using pre-emphasis technique to compensate for the RF signal attenuation on the other hand. In addition, for ease of access from both optical and RF perspective, a via-hole less broad bandwidth transition is designed between coplanar pads and coupled microstrip (CPW-CMS) driving electrodes. With the best reported E-O coefficient of 350 pm/V, the designed E-O deflector should allow an AOADC operating over 44 giga-samples-per-seconds with an estimated effective resolution of 6.5 bits on RF signals with Nyquist bandwidth of 22 GHz. The overall DC power consumption of all components used in this AOADC is of order of 4 W and is dominated by power consumption in the power amplifier to generate a 20 V RF voltage in 50 Ohm system. A higher sampling rate can be achieved at similar bits of resolution by interleaving a number of this elementary AOADC at the expense of a higher power consumption.

  11. Total ionizing dose effects on a radiation-induced BiMOS analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    Wu Xue; Lu Wu; Wang Yiyuan; Xu Jialing; Zhang Leqing; Lu Jian; Yu Xin; Zhang Xingyao; Hu Tianle

    2013-01-01

    The total dose effect of an AD678 with a BiMOS process is studied.We investigate the performance degradation of the device in different bias states and at several dose rates.The results show that an AD678 can endure 3 krad(Si) at low dose rate and 5 krad(Si) at a high dose rate for static bias.The sensitive parameters to the bias states also differ distinctly.We find that the degradation is more serious on static bias.The underlying mechanisms are discussed in detail.

  12. High-Performance Photonic Analog-to-Digital Converter and Low-Noise Mode-Locked Fiber Lasers

    Science.gov (United States)

    2007-11-02

    input signal spanning a time period given by MKT . The sampling times tn, where 0 ≤ n ≤ MK−1, can then be written as: nn nTt ∆+= (1) ∆n is thus... MKT a fa = (5) 22 MKMK a ≤≤− (6) Substitution of (2), (3), (5) into (4) and separation of the overall summation into summations over the...the FFT will be evaluated at frequencies ranging from −1/(2MT) to 1/(2MT) in increments of 1/ MKT . This gives K + 1 total points, but the first and

  13. A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

    Science.gov (United States)

    Xin, Jing; Yiqi, Zhuang; Hualian, Tang; Li, Dai; Yongqian, Du; Li, Zhang; Hongbo, Duan

    2014-02-01

    A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are -0.43 to +0.48 LSB and -1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step.

  14. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    Science.gov (United States)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  15. Design of a Parallel Sampling Encoder for Analog to Information (A2I Converters: Theory, Architecture and CMOS Implementation

    Directory of Open Access Journals (Sweden)

    Andreas G. Andreou

    2013-03-01

    Full Text Available We discuss the architecture and design of parallel sampling front ends for analog to information (A2I converters. As a way of example, we detail the design of a custom 0.5 µm CMOS implementation of a mixed signal parallel sampling encoder architecture. The system consists of configurable parallel analog processing channels, whose output is sampled by traditional analog-to-digital converters (ADCs. The analog front-end modulates the signal of interest with a high-speed digital chipping sequence and integrates the result prior to sampling at a low rate. An FPGA is employed to generate the chipping sequences and process the digitized samples.

  16. An introduction to analog and digital communications

    CERN Document Server

    Haykin, Simon

    2012-01-01

    The second edition of this accessible book provides readers with an introductory treatment of communication theory as applied to the transmission of information-bearing signals. While it covers analog communications, the emphasis is placed on digital technology. It begins by presenting the functional blocks that constitute the transmitter and receiver of a communication system. Readers will next learn about electrical noise and then progress to multiplexing and multiple access techniques.

  17. Frequency to Voltage Converter Analog Front-End Prototype

    Science.gov (United States)

    Mata, Carlos; Raines, Matthew

    2012-01-01

    The frequency to voltage converter analog front end evaluation prototype (F2V AFE) is an evaluation board designed for comparison of different methods of accurately extracting the frequency of a sinusoidal input signal. A configurable input stage is routed to one or several of five separate, configurable filtering circuits, and then to a configurable output stage. Amplifier selection and gain, filter corner frequencies, and comparator hysteresis and voltage reference are all easily configurable through the use of jumpers and potentiometers.

  18. Design and realization of a high-speed 12-bit pipelined analog-digital converter IP block

    OpenAIRE

    Toprak, Zeynep

    2001-01-01

    This thesis presents the design, verification, system integration and the physical realization of a monolithic high-speed analog-digital converter (ADC) with 12-bit accuracy. The architecture of the ADC has been realized as a pipelined structure consisting of four pipeline stages, each of which is capable of processing the incoming analog signal with 4-bit accuracy. A bit-overlapping technique has been employed for digital error correction between the pipeline stages so that the influence of ...

  19. A standardized way to select, evaluate, and test an analog-to-digital converter for ultrawide bandwidth radiofrequency signals based on user's needs, ideal, published,and actual specifications

    Science.gov (United States)

    Chang, Daniel Y.; Rowe, Neil C.

    2012-06-01

    The most important adverse impact on the Electronic Warfare (EW) simulation is that the number of signal sources that can be tested simultaneously is relatively small. When the number of signal sources increases, the analog hardware, complexity and costs grow by the order of N2, since the number of connections among N components is O(N*N) and the signal communication is bi-directional. To solve this problem, digitization of the signal is suggested. In digitizing a radiofrequency signal, an Analog-to-Digital Converter (ADC) is widely used. Most research studies on ADCs are conducted from designer/test engineers' perspective. Some research studies are conducted from market's perspective. This paper presents a generic way to select, evaluate and test ultra high bandwidth COTS ADCs and generate requirements for digitizing continuous time signals from the perspective of user's needs. Based on user's needs, as well as vendor's published, ideal and actual specifications, a decision can be made in selecting a proper ADC for an application. To support our arguments and illustrate the methodology, we evaluate a Tektronix TADC-1000, an 8-bit and 12 gigasamples per second ADC. This project is funded by JEWEL lab, NAWCWD at Point Mugu, CA.

  20. Broadband analog to digital conversion with spatial-spectral holography

    Energy Technology Data Exchange (ETDEWEB)

    Babbitt, W. Randall [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)]. E-mail: babbitt@physics.montana.edu; Neifeld, Mark A. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States); Merkel, Kristian D. [Spectrum Lab, Montana State University, Bozeman, MT 59717-3510 (United States)

    2007-11-15

    A new approach to broadband photonic-assisted analog-to-digital converter (ADC) technology is proposed and analyzed. The core of the device is a spatial spectral holographic (SSH) material, which can directly record the signals of interest in the frequency domain. An SSH-ADC acts as a frequency-domain stretch processor, which leverages the high performance of conventional ADCs by converting high bandwidth input signals to low bandwidth output signals without loss of information. Analysis of a 10 GHz bandwidth SSH-ADC predicts that 10-bit performance can be achieved with currently available materials and components. SSH-ADC technology is scalable to bandwidths over 100 GHz with recently developed SSH materials. While the SSH-ADC is a transient digitizer, the spatial parallelism of SSH materials can be utilized to enable continuous digitization.

  1. ANALOG-TO-DIGITAL CONVERSION OF SIGNALS WITH ANGULAR MANIPULATION FOR SOFTWARE DEFINED RADIO SYSTEMS

    Directory of Open Access Journals (Sweden)

    A. Y. Tsvetkov

    2016-05-01

    Full Text Available The paper deals with the search of ways for speeding up and accuracy increase of conversion of modern analog-to-digital converters. The main shortcomings interfering a solution of this task including the field of optoelectronic analog-to-digital converters are provided. The proposed solution gives the chance to increase high-speed performance of analog-to-digital converters on the basis of holographic interferometry principles without reducing their accuracy of conversion. The optical scheme of interferential and holographic method of analog-to-digital conversion and results of its mathematical modeling are provided. Some recommendations about hardware implementation of this analog data digitizer are formulated. The physical principles and approaches to a choice of the converter structural elements are explained. An example of forming the functional scheme of a decoder for a luminous flux intensity in terms of registration of analog-to-digital converter is reviewed. The practical importance of the provided method consists in possibility of creation of analog-to-digital converters with high-speed performance about 600 MHz and with an accuracy of conversion up to 12 bits.

  2. An analog-to-digital conversion system with a logarithmic characteristic

    Science.gov (United States)

    Bellomo, A.

    1972-01-01

    Detailed analysis of an analog-to-digital conversion system consisting of a linear converter and a logarithmic amplifier containing nonlinear elements. It is shown that the small-signal resolution of such a system is much greater than that of linear systems used under the same conditions. A design for a low-power analog-to-digital converter operating at medium speed with a large input signal variation field is outlined.

  3. Design, development, and fabrication of a electronic analog microminiaturized electronic analog signal to discrete time interval converter

    Science.gov (United States)

    Schoenfeld, A. D.; Schuegraf, K. K.

    1973-01-01

    The microminiaturization of an electronic analog signal to discrete time interval converter is presented. Discrete components and integrated circuits comprising the converter were assembled on a thin-film ceramic substrate containing nichrome resistors with gold interconnections. The finished assembly is enclosed in a flat package measuring 3.30 by 4.57 centimeters. The module can be used whenever conversion of analog to digital signals is required, in particular for the purpose of regulation by means of pulse modulation. In conjunction with a precision voltage reference, the module was applied to control the duty cycle of a switching regulator within a temperature range of -55 C to +125 C, and an input voltage range of 10V to 35V. The output-voltage variation was less than + or - 300 parts per million, i.e., less than + or - 3mV for a 10V output.

  4. Efficiency and hardware comparison of analog control-based and digital control-based 70 W two-stage power factor corrector and DC-DC converters

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2011-01-01

    A comparison of an analog and a digital controller driven 70 W two-stage power factor corrector converter is presented. Both controllers are operated in average current-mode-control for the PFC and peak current control for the DC-DC converter. Digital controller design and converter modeling...... is described. Results show that digital control can compete with the analog one in efficiency, PFC and THD....

  5. A Methodology to Teach Advanced A/D Converters, Combining Digital Signal Processing and Microelectronics Perspectives

    Science.gov (United States)

    Quintans, C.; Colmenar, A.; Castro, M.; Moure, M. J.; Mandado, E.

    2010-01-01

    ADCs (analog-to-digital converters), especially Pipeline and Sigma-Delta converters, are designed using complex architectures in order to increase their sampling rate and/or resolution. Consequently, the learning of ADC devices also encompasses complex concepts such as multistage synchronization, latency, oversampling, modulation, noise shaping,…

  6. A digital silicon photomultiplier with multiple time-to-digital converters

    Energy Technology Data Exchange (ETDEWEB)

    Garutti, Erika [University Hamburg (Germany); Silenzi, Alessandro [DESY, Hamburg (Germany); Xu, Chen [DESY, Hamburg (Germany); University Hamburg (Germany)

    2013-07-01

    A silicon photomultiplier (SiPM) with pixel level signal digitization and column-wise connected time-to-digital converters (TDCs) has been developed for an endoscopic Positron Emission Tomography (PET) detector. A digital SiPM has pixels consist of a single photon avalanche diode (SPAD) and circuit elements to optimize overall dark counts and temporal response. Compared with conventional analog SiPM, digital SiPM's direct signal route from SPAD to TDC improves single photon time resolution. In addition, using multiple TDCs can perform the statistical estimation of the time-of-arrival in multiple photon detection case such as readout of scintillation crystals. Characterization measurements of the prototype digital SiPM and a Monte-Carlo simulation to predict the timing performance of the PET detector are shown.

  7. The Transition from Analog to Digital Mammography: Overall Considerations

    Directory of Open Access Journals (Sweden)

    A. Sardo

    2007-05-01

    Full Text Available In the last decades a continuous growth of the infor-matics process around the world has been observed: paper documents, data, images…, converted into a “digital format” allow an easier and safer manage-ment, making possible its compatibility and access to internet networking. This migration confirms the huge technology progresses made especially in the image capture ways: from photography to graphic arts, from movie to healthcare imaging, where the end user/radiologist requires, at least, a digital clinical image with a quality equivalent to the previous ana-log film image. In women’s breast imaging care mammography is acknowledged as the most effective method to detect a breast cancer at an earlier stage and it is currently the only imaging modality, which has been proven to reduce mortality in women screened from 50 to 69 years. The transition to Digital Mammography represents a challenge to decide when to change the first concern is to get the money availability to purchase a Digital Mammography system and the well-trained human resources (radiologist, technician and physicist for using it. A digital system must satisfy actual needs such as the diagnostic accuracy, dose and regulatory requirements, productivity and archive issues. The new digital modality must be integrated in a fully digital environment (PACS and the presence of CR or DR systems for general radiography could condi-tion the choice of CR or DR Digital Mammography system. The Primary goal of mammography (both analog and digital is to provide to the radiologist clinical images for confident interpretation. Certainly the confidence derives from radiologist’s experience in reading mammograms, but many other factors can increase it, for instance correct patient positioning, excellent and consistent image quality (photographic and artifacts free, easy use and interpretation aid (e.g. lens, CAD use of imaging system. However, the habit in read-ing film-images on view box

  8. All-digital pulse-expansion-based CMOS digital-to-time converter

    Science.gov (United States)

    Chen, Chun-Chi; Chu, Che-Hsun

    2017-02-01

    This paper presents a new all-digital CMOS digital-to-time converter (DTC) based on pulse expansion. Pulse expansion is achieved using an all-digital pulse-mixing scheme that can effectively improve the timing resolution and enable the DTC to be concise. Without requiring the Vernier principle or a costly digital-to-analog converter, the DTC comprises a pulse generator for generating a pulse, a pulse-expanding circuit (PEC) for programming timing generation, and a time subtractor for removing the time width of the pulse. The PEC comprises only a delay chain composed of proposed pulse-expanding units and a multiplexer. For accuracy enhancement, a pulse neutralization technique is presented to eliminate undesirable pulse variation. A 4-bit converter was fabricated in a 0.35-μ m Taiwan Semiconductor Manufacturing Company CMOS process and had a small area of nearly 0.045 mm2. Six chips were tested, all of which exhibited an improved resolution (approximately 16 ps) and low integral nonlinearity (less than ±0.4 least significant bit). The power consumption was 0.2 mW when the sample rate was 1M samples/s and the voltage supply was 3.3 V. The proposed DTC not only has favorable cost and power but also achieves an acceptable resolution without requiring an advanced CMOS process. This study is the first to use pulse expansion in digital-to-time conversion.

  9. High-Performance DA-Converters Application to Digital Transceivers

    CERN Document Server

    Clara, Martin

    2013-01-01

    This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested.  With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.

  10. Digital and analog communication systems

    Science.gov (United States)

    Shanmugam, K. S.

    1979-01-01

    The book presents an introductory treatment of digital and analog communication systems with emphasis on digital systems. Attention is given to the following topics: systems and signal analysis, random signal theory, information and channel capacity, baseband data transmission, analog signal transmission, noise in analog communication systems, digital carrier modulation schemes, error control coding, and the digital transmission of analog signals.

  11. Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system

    Science.gov (United States)

    Jiang, Jia-Jia; Duan, Fa-Jie; Li, Yan-Chao; Hua, Xiang-Ning

    2014-03-01

    Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper.

  12. A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

    Directory of Open Access Journals (Sweden)

    M. Rezvanyvardom

    2015-09-01

    Full Text Available This paper investigates a novel cyclic time-to-digital converter (TDC which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop. The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM. In this converter, the integral nonlinearity (INL and differential nonlinearity (DNL errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

  13. Doubling-resolution analog-to-digital conversion based on PIC18F45K80

    Directory of Open Access Journals (Sweden)

    Yueyang Yuan

    2014-08-01

    Full Text Available Aiming at the analog signal being converted into the digital with a higher precision, a method to improve the analog-to-digital converter (ADC resolution is proposed and described. Based on the microcomputer PIC18F45K80 in which the internal ADC modules are embedded, a circuit is designed for doubling the resolution of ADC. According to the circuit diagram, the mathematical formula for calculating this resolution is derived. The corresponding software and print circuit board assembly is also prepared. With the experiment, a 13 bit ADC is achieved based on the 12 bit ADC module predesigned in the PIC18F45K80.

  14. Converting Taxonomic Descriptions to New Digital Formats

    Directory of Open Access Journals (Sweden)

    Hong Cui

    2008-01-01

    Full Text Available Abstract.--The majority of taxonomic descriptions is currently in print format. The majority of digital descriptions are in formats such as DOC, HTML, or PDF and for human readers. These formats do not convey rich semantics in taxonomic descriptions for computer-aided process. Newer digital formats such as XML and RDF accommodate semantic annotations that allow computers to process the rich semantics on human's behalf, thus open up opportunities for a wide range of innovative usages of taxonomic descriptions, such as searching in more precise and flexible ways, integrating with gnomic and geographic information, generating taxonomic keys automatically, and text data mining and information visualization etc. This paper discusses the challenges in automated conversion of multiple collections of descriptions to XML format and reports an automated system, MARTT. MARTT is a machine-learning system that makes use of training examples to tag new descriptions into XML format. A number of utilities are implemented as solutions to the challenges. The utilities are used to reduce the effort for training example preparation, to facilitate the creation of a comprehensive schema, and to predict system performance on a new collection of descriptions. The system has been tested with several plant and alga taxonomic publications including Flora of China and Flora of North America.

  15. Issues to Consider in Converting to Digital Mammography

    Science.gov (United States)

    Pisano, Etta D.; Zuley, Margarita; Baum, Janet K.; Marques, Helga S.

    2007-01-01

    This paper will outline the reasons that many radiology practices are converting to digital mammography. In addition, we will provide basic information on the issues that must be considered in making the transformation. These include technical matters regarding image display, storage and retrieval, as well as clinical and ergonomic considerations. PMID:17888771

  16. A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems.

    Science.gov (United States)

    Park, Sung-Yun; Cho, Jihyun; Lee, Kyuseok; Yoon, Euisik

    2015-12-01

    We report a pulse width modulation (PWM) buck converter that is able to achieve a power conversion efficiency (PCE) of > 80% in light loads 100 μA) for implantable biomedical systems. In order to achieve a high PCE for the given light loads, the buck converter adaptively reconfigures the size of power PMOS and NMOS transistors and their gate drivers in accordance with load currents, while operating at a fixed frequency of 1 MHz. The buck converter employs the analog-digital hybrid control scheme for coarse/fine adjustment of power transistors. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average of duty cycles for the given load condition from limit cycle oscillations (LCO) induced by coarse adjustment. The fabricated buck converter achieved a peak efficiency of 86.3% at 1.4 mA and > 80% efficiency for a wide range of load conditions from 45 μA to 4.1 mA, while generating 1 V output from 2.5-3.3 V supply. The converter occupies 0.375 mm(2) in 0.18 μm CMOS processes and requires two external components: 1.2 μF capacitor and 6.8 μH inductor.

  17. Sub-picosecond Resolution Time-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Ph D, Vladimir Bratov; Ph D, Vladimir Katzman; MS EE, Jeb Binkley

    2006-03-30

    Time-to-digital converters with sub-picosecond resolutions are needed to satisfy the requirements of time-on-flight measurements of the next generation of high energy and nuclear physics experiments. The converters must be highly integrated, power effective, low cost, and feature plug-and-play capabilities to handle the increasing number of channels (up to hundreds of millions) in future Department of Energy experiments. Current state-off-the-art time-to-digital converter integrated circuits do not have the sufficient degree of integration and flexibility to fulfill all the described requirements. During Phase I, the Advanced Science and Novel Technology Company in cooperation with the nuclear physics division of the Oak Ridge National Laboratory has developed the architecture of a novel time-to-digital converter with multiple channels connected to an external processor through a special interfacing block and synchronized by clock signals generated by an internal phase-locked loop. The critical blocks of the system including signal delay lines and delay-locked loops with proprietary differential delay cells, as well as the required digital code converter and the clock period counter have been designed and simulated using the advanced SiGe120 BiCMOS technological process. The results of investigations demonstrate a possibility to achieve the digitization accuracy within 1ps. ADSANTEC has demonstrated the feasibility of the proposed concept in computer simulations. The proposed system will be a critical component for the next generation of NEP experiments.

  18. Charge to digital converter with constant resolution over the dynamic range

    Energy Technology Data Exchange (ETDEWEB)

    Nascetti, A. [Department of Aerospace and Astronautics Engineering, Sapienza University of Rome, via Eudossiana 16, 00184, Rome (Italy)

    2009-12-15

    A novel pixel-level charge to digital converter circuit suitable for multi-channel charge sensitive amplifiers or pixelated readout ICs for hybrid detectors is presented. The proposed circuit features large dynamic range operation with constant relative resolution over the whole dynamic range. These characteristics have been obtained by introducing the fractional charge packet counting concept. In particular, a solution has been proposed to obtain the analog-to-digital conversion with constant number of significant bits.

  19. Design of High Dynamic Range Digital to Analog Converters for the Calibration of the CALICE Si-W Ecal readout electronics

    CERN Document Server

    Gallin-Martel, L; Hostachy, J Y; Rarbi, F; Rossetto, O

    2009-01-01

    The ILC ECAL front-end chip will integrate many functions of the readout electronics including a DAC dedicated to calibration. We present two versions of DAC with respectively 12 and 14 bits, designed in a CMOS 0.35μm process. Both are based on segmented arrays of switched capacitors controlled by a Dynamic Element Matching (DEM) algorithm. A full differential architecture is used, and the amplifiers can be turned into a standby mode reducing the power dissipation. The 12 bit DAC features an INL lower than 0.3 LSB at 5MHz, and dissipates less than 7mW. The 14 bit DAC is an improved version of the 12 bit design.

  20. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  1. Analog versus digital: extrapolating from electronics to neurobiology.

    Science.gov (United States)

    Sarpeshkar, R

    1998-10-01

    We review the pros and cons of analog and digital computation. We propose that computation that is most efficient in its use of resources is neither analog computation nor digital computation but, rather, a mixture of the two forms. For maximum efficiency, the information and information-processing resources of the hybrid form must be distributed over many wires, with an optimal signal-to-noise ratio per wire. Our results suggest that it is likely that the brain computes in a hybrid fashion and that an underappreciated and important reason for the efficiency of the human brain, which consumes only 12 W, is the hybrid and distributed nature of its architecture.

  2. Pipeline Analog-Digital Converters Dynamic Error Modeling for Calibration : Integral Nonlinearity Modeling, Pipeline ADC Calibration, Wireless Channel K-Factor Estimation

    OpenAIRE

    Medawar, Samer

    2012-01-01

    This thesis deals with the characterization, modeling and calibration of pipeline analog-digital converters (ADC)s. The integral nonlinearity (INL) is characterized, modeled and the model is used to design a post-correction block in order to compensate the imperfections of the ADC. The INL model is divided into: a dynamic term designed by the low code frequency (LCF) component depending on the output code k and the frequency under test m, and a static term known as high code frequency (HCF) c...

  3. New method to implement digital down converter in radar system

    Institute of Scientific and Technical Information of China (English)

    Ma Zhigang; Wen Biyang; Zhou Hao; Bai Liyun

    2005-01-01

    Digital down converter (DDC) is the main part of the next generation high frequency (HF) radar. In order to realize the single chip integrations of digital receiver hardware in the next generation HF Radar, a new design for DDC by using FPGA is presented. Some important and practical applications are given in this paper, and the result can prove the validity. Because we can adjust the parameters freely according to our need, the DDC system can be adapted to the next generation HF radar system.

  4. A Comparative study of Analog and digital Controller On DC/DC Buck-Boost Converter Four Switch for Mobile Device Applications

    Directory of Open Access Journals (Sweden)

    Benlafkih Abdessamad

    2013-01-01

    Full Text Available this paper presents comparative performance between Analog and digital controller on DC/DC buck-boost converter four switch. The design of power electronic converter circuit with the use of closed loop scheme needs modeling and then simulating the converter using the modeled equations. This can easily be done with the help of state equations and MATLAB/SIMULINK as a tool for simulation of those state equations. DC/DC Buckboost converter in this study is operated in buck (step-down and boost (step-up modes.

  5. 12 bit 40 MS/s pipelined analog-to-digital converter with an improved bootstrapped switch%采用改进自举开关的12 bit 40 MS/s流水线ADC

    Institute of Scientific and Technical Information of China (English)

    景鑫; 庄奕琪; 汤华莲; 戴力

    2013-01-01

    设计了一种用于分时长期演进(TD-LTE)系统基带信号处理的12 bit 40 MS/s无校准的流水线模数转换器(ADC).在采样保持前端设计了一种改进的栅压自举开关,有效减少了电路的非线性失真,提高了开关的线性度.设计的ADC采用全2.5 bit/级架构,利用级电路缩减技术满足面积与功耗要求.芯片基于130 nmCMOS(互补金属氧化物半导体)工艺流片验证,电源电压1.2V.实测整个ADC,最大INL(积分非线性)和DNL(微分非线性)误差分别为1.48 LSB(最低有效位)和0.48 LSB.动态特性测试结果表明:在40 MS/s采样频率、-1 dBFS(满度相对电平)、4.3 MHz正弦输入下,设计的模数转换器信噪失真比(SNDR)达到63.55dB,无杂散动态范围(SFDR)达到76.37 dB.整个ADC在40 MS/s全速工作时功耗48 mW,芯片面积(包含Pad)为3.1 mm×1.4 mm.%A 12 bit 40 MS/s calibration-free pipelined analog-to-digital convert (ADC) used in TDLTE(time division long term evolution) baseband was described.A gate-bootstrapping switch's linearity was improved and designed as the input-sampling switches in the front sample-and-hold (S/H) circuit in order to reduce the nonlinearity distortion of the ADC effectively.To achieve low power and small chip size,the pipelined stages were scaled in current and area,and implemented with 2.5 bit/stage architecture.The ADC was fabricated in 130 nm CMOS(complementary metal oxide semiconductor) process with 1.2 V power supply.The results show that the ADC achieves 63.55 dB signal-to-noise and distortion ration (SNDR),76.37 dB spurious free dynamic range (SFDR) under the conditions of 40 MS/s sampling rate and-1 dBFS (dB full scale),4.3 MHz sinusoidal input signal.The measured maximum integral nonlinearities (INL) errors and differential nonlinearities (DNL) errors are 1.48 LSB (least significant bit) and 0.48 LSB at 12 bit level,respectively.The entire ADC consumes 48 mW when operating at 40 MS/s sampling rate and the chip size (including Pad

  6. Efficient Circuit Configuration for Enhancing Resolution of 8-bit flash Analog to Digital Convertor

    Directory of Open Access Journals (Sweden)

    Gururaj Balikatti

    2012-11-01

    Full Text Available The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High speed analog to digital converters (ADCs have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADCs unsuitable for high resolution applications. The focus of this paper is on efficient circuit configuration to enhance resolution of available 8-bit flash ADC, while maintaining number of comparators only 256 for 12 bit conversion. This technique optimizes the number of comparator requirements. In this approach, an 8-bit flash ADC partitions the analog input range into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. The Microcontroller decides within which cell the input sample lies and assigns a 12-bit binary center code 000000000000 to 111111111111 according to the cell value. The exact 12-bit digital code is obtained by successive approximation technique. In this paper the focus will be on all-around efficient circuit for enhancing resolution of 8-bit Flash ADC. It is shown that by adopting this configuration, we can obtain 12-bit digital data just using 256 comparators. Therefore this technique is best suitable when high speed combined with high resolution is required. An experimental prototype of proposed 12-bit ADC was implemented using Philips P89V51RD2BN Microcontroller. Use of Microcontroller has greatly reduced the hardware requirement and cost. An ADC result of 12-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.52LSB and a maximum INL of 0.55LSB.

  7. Analog and digital signal analysis from basics to applications

    CERN Document Server

    Cohen Tenoudji, Frédéric

    2016-01-01

    This book provides comprehensive, graduate-level treatment of analog and digital signal analysis suitable for course use and self-guided learning. This expert text guides the reader from the basics of signal theory through a range of application tools for use in acoustic analysis, geophysics, and data compression. Each concept is introduced and explained step by step, and the necessary mathematical formulae are integrated in an accessible and intuitive way. The first part of the book explores how analog systems and signals form the basics of signal analysis. This section covers Fourier series and integral transforms of analog signals, Laplace and Hilbert transforms, the main analog filter classes, and signal modulations. Part II covers digital signals, demonstrating their key advantages. It presents z and Fourier transforms, digital filtering, inverse filters, deconvolution, and parametric modeling for deterministic signals. Wavelet decomposition and reconstruction of non-stationary signals are also discussed...

  8. 一种新型CMOS数模转换器的设计与仿真%Design and Simulation of New CMOS Digital-analog Converter

    Institute of Scientific and Technical Information of China (English)

    张大为; 姜静; 刘迪

    2011-01-01

    A kind of 8 - bit CMOS digital - analog converter based on inverted R - 2R ladder architecture is designed. The input mode of digital -analog converter adopts parallel - input, and the output mode adopts analog current - output. Voltage reference adopts CMOS bandgap reference source circuit. And the circuit synthesizes techniques such as start - up circuit,temperature compensation and current feedback technology. Further more,the output voltage can get lower temperature coefficient through adjusting the resistance appropriately. Hspice is adopted as the circuit simulation imitate analysis software tool, the result shows that the design comes to the request. With 5 V supply, the settling -time is less than 50 ns,both integral nonlinearity and differential nonlinearity areless than 0. 5 LSB,power is lower than 40 Mw.%设计了一种基于R-2R倒梯形电阻网络结构的8位CMOS数模转换器.数模转换器输入采用并行数字输入结构,输出采用模拟电流输出方式,基准电压源采用CMOS带隙基准电压电路,该电路综合了电路启动、温度补偿和电流反馈等技术,通过适当调节电阻,使输出电压具有较低的温度系数.采用Hspice作为设计电路模拟仿真分析的软件工具,仿真结果表明,在5V工作电压下,建立时间小于50 ns,电路的积分与微分非线性误差均小于5 LSB,功耗小于40 mW,达到了设计要求.

  9. From Analog to Digital Medias in Early Childhood Education

    DEFF Research Database (Denmark)

    Brandt, Erika Zimmer

    2015-01-01

    Research aims: The aim of the study is to explore how the encounters between children and their educators alter when the media changes from analog to digital. Relationship to previous research works Tablets and other handheld, electronic devices has become part of everyday life in kindergartens....... Research shows that there are both potential pedagogical difficulties and possibilities connected to using digital media (ex. Thestrup 2015, Tække and Paulsen 2014) Theoretical and conceptual framework: The study is a single case study of an educational experiment (Flyvbjerg 2006). It is carried out...... Considerations: A changed media environment reveals a kind of social vacuum. Educators find themselves lacking norms for how to interact in this new reality. This lack of knowhow and experience in this specific area of professionalism creates uncertainty and vulnerability in the informants which require micro...

  10. FPGA based sigma –Delta analogue to digital converter design

    Directory of Open Access Journals (Sweden)

    P. A. Uchagaonkar

    2012-03-01

    Full Text Available This paper reports design and development of modified Sigma- Delta ADC realized in FPGA paradigm. The wide gain of this ADC makes it a potential candidate in data converter applications in wide ranging domains such as communication systems, instrumentation, precision measurement devices and manyothers wherein the high resolution precision converter is essential. The proposed architecture encompasses of mixed mode design in which few of the analog and up to 90% digital blocks have been realized on a single platform. The digital building blocks have been tested and implemented in Xilinx ISE with the help of MATLAB system generator tool and instantiated on Spartan 3e FPGA. System performance has been ascertained using the hardware co-simulation and further post verified on the Xilinx analyzer tool.

  11. Photonic Analog-to-Digital Conversion of Time-Continuous Signals using a TDM Switching-Wavelength Sampling Source

    Institute of Scientific and Technical Information of China (English)

    K. L. Lee; M. P. Fok; C. Shu

    2003-01-01

    A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corresponds to 7 effective number of bits.

  12. The GANDALF 128-Channel Time-to-Digital Converter

    CERN Document Server

    Büchele, Maximilian; Herrmann, Florian; Königsmann, Kay; Schill, Christian; Schopferer, Sebastian

    2011-01-01

    The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabr...

  13. Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

    CERN Document Server

    Pickering, J

    2015-01-01

    This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.

  14. Converting To Digital Library in Banking Organizations : Case Study For Library of Central Bank of Libya

    Directory of Open Access Journals (Sweden)

    Asmaa Basher Abou Louefa

    2005-05-01

    Full Text Available A Case study For Library of Central Bank of Libya, it deals the converting to a digital library. It start with an introduction about digital libraries, and technology in libraries, then deal Library of Central Bank of Libya, and it current situation, then states the plan to be converted to digital library.

  15. Analog-Digital Interfaces

    Science.gov (United States)

    Keller, Matthias; Murmann, Boris; Manoli, Yiannos

    This chapter discusses trends in the area of low-power, high-performance A/D conversion. Survey data collected over the past thirteen years are examined to show that the conversion energy of ADCs has halved every two years while the speed-resolution product has doubled approximately only every four years. A closer inspection on the impact of technology scaling and developments in ADC design are then presented to explain the observed trends. Next, opportunities in minimalistic and digitally assisted design are reviewed for the most popular converter architectures. Finally, trends in Delta-Sigma ADCs are analyzed in detail.

  16. Low resource FPGA-based Time to Digital Converter

    CERN Document Server

    Balla, A; Ciambrone, P; Gatta, M; Gonnella, F; Iafolla, L; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2...

  17. The GANDALF 128-channel time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany)

    2013-07-01

    In particle physics experiments, Time-to-Digital Converters (TDC) perform accurate time measurements, thus to allow for charged particle identification and tracking. We have developed within the GANDALF framework a 128-channel TDC, implemented in a Xilinx Virtex-5 FPGA. A time resolution better than 93 ps has been verified for all channels. In contrast to previous FPGA-based TDC, the design makes use of a shifted clock sampling algorithm. In this concept, the input signal is sampled with flip-flops driven by a set of equidistant phase-shifted clocks. The TDC register length depends only on the number of phase-shifted clocks and therefore permits to process a large number of channels in a very resource-efficient way. As not only time measurements but also simultaneous rate measurements are required for many applications, we present a combination of 96 scaler and TDC channels implemented in the same FPGA on the GANDALF 6U-VME64x/VXS carrier board. In addition to the experiment trigger, an internal generated pseudo-random trigger is applied in order to produce two independent data streams. This may allow for online monitoring of the detector device.

  18. Demonstrations of analog-to-digital conversion using a frequency domain stretched processor.

    Science.gov (United States)

    Reibel, Randy Ray; Harrington, Calvin; Dahl, Jason; Ostrander, Charles; Roos, Peter Aaron; Berg, Trenton; Mohan, R Krishna; Neifeld, Mark A; Babbitt, Wm R

    2009-07-06

    The first proof-of-concept demonstrations are presented for a broadband photonic-assisted analog-to-digital converter (ADC) based on spatial spectral holography (SSH). The SSH-ADC acts as a frequency-domain stretch processor converting high bandwidth input signals to low bandwidth output signals, allowing the system to take advantage of high performance, low bandwidth electronic ADCs. Demonstrations with 50 MHz effective bandwidth are shown to highlight basic performance with approximately 5 effective bits of vertical resolution. Signal capture with 1600 MHz effective bandwidth is also shown. Because some SSH materials span over 100 GHz and have large time apertures (approximately 10 micros), this technique holds promise as a candidate for the next generation of ADCs.

  19. All-optical analog-to-digital conversion using optical interconnection for gray code coding

    Science.gov (United States)

    Nishitani, Takashi; Konishi, Tsuyoshi; Itoh, Kazuyoshi

    2006-09-01

    The gray code based all-optical analog-to-digital conversion (ADC) using optical interconnection is described. Recent tremendous growths of optical communications and digital signal processing have encouraged the demand of high-speed and high-resolution ADC. To pursue a high-speed and high-resolution ADC, optical approaches have attracted much attention recently. ADC generally consists of three procedures: sampling, quantization and coding. Whereas the optical sampling techniques have been proposed and realized, the optical quantization and coding techniques have investigated depending on various applications. For the application to the binary detection of a high-speed digital signal, we previously proposed an all-optical ADC which consists of optical quantization using self-frequency shifting in a fiber and optical coding using optical interconnection for general binary code. In addition, since we can easily prepare optical interconnection patterns corresponding to the various codes, this technique can be used in any coding schemes. In this paper, we demonstrate the gray code based all-optical ADC to verify its scalability. Experimental results show that the 8-levels analog signals can be successfully converted into the bitwise allocated 3-bit gray code.

  20. Transitioning from analog to digital communications: An information security perspective

    Science.gov (United States)

    Dean, Richard A.

    1990-01-01

    A summary is given of the government's perspective on evolving digital communications as they affect secure voice users and approaches for operating during a transition period to an all digital world. An integrated architecture and a mobile satellite interface are discussed.

  1. Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, Yi; Chen, Guan-Hong

    2016-04-01

    This paper proposes an all-digital pulse-shrinking time-to-digital converter (TDC) using the offset error cancellation circuitry to widen its dynamic range and to improve its accuracy. Although the TDC based on a pulse-shrinking mechanism can achieve a sub-gate resolution without circuit complexity, it possesses an undesired offset error that results in a nonzero lower bound appeared in its dynamic range and then affects its accuracy. The proposed cancellation circuitry for eliminating the offset error consists of a time adder with a delay line and a time subtractor with an identical delay line. The experimental TDC is implemented on Xilinx field programmable gate arrays and it also functions successfully in improving its dynamic range.

  2. Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range.

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, Yi; Chen, Guan-Hong

    2016-04-01

    This paper proposes an all-digital pulse-shrinking time-to-digital converter (TDC) using the offset error cancellation circuitry to widen its dynamic range and to improve its accuracy. Although the TDC based on a pulse-shrinking mechanism can achieve a sub-gate resolution without circuit complexity, it possesses an undesired offset error that results in a nonzero lower bound appeared in its dynamic range and then affects its accuracy. The proposed cancellation circuitry for eliminating the offset error consists of a time adder with a delay line and a time subtractor with an identical delay line. The experimental TDC is implemented on Xilinx field programmable gate arrays and it also functions successfully in improving its dynamic range.

  3. Optical Analog-to-digital Conversion Scheme Based on Tunable Fabry-Perot Resonator

    Institute of Scientific and Technical Information of China (English)

    LI Zheng

    2007-01-01

    Proposed is an interference type of optical analog-to-digital conversion(ADC). The refractive index of Fabry-Perot cavity changes with different voltages. The Fabry-Perot resonator converts electronic intensity into light wavelength through selecting lights of different wavelengthes. The parameters of the scheme are acquired with the transmission matrix of optical element and the time of steady-state light field. The maximum sampling speedes of 4-bit, 6-bit, 7-bit, 8-bit and 9-bit(ADC) are 1.695×1010 count/s, 4.33×109 count/s, 2.38×109 count/s, 1.24×109 count/s and 5.9×108 count/s, respectively.

  4. 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

    KAUST Repository

    Omran, Hesham

    2014-08-01

    In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

  5. Analog-digital codesign using coarse quantization

    Science.gov (United States)

    Kokkeler, Andre Bernardus Joseph

    With regards to electronic systems, two important trends can be observed. The first trend is generally known as Moore's law: the digital processing capacity per chip is increasing a factor two every 18 months. Another part of the first trend is that the performance increase of integrated linear or analog processing is slow, a factor two every 4.7 years. The second trend is that the rate of data exchange between electronic systems is increasing rapidly. Because of these high data rates especially the design of data converters from analog to digital (ADCs) is demanding. For a specific set of applications, the requirements for the ADC can be relaxed by reducing the resolution of the conversion from analog to digital. Within these specific applications, signal characteristics rather than instantaneous values of the signal are determined. Reducing the resolution to an extreme extend is called 'coarse quantization'. The design of mixed signal systems is guided by a Y-chart design methodology. Analog-Digital Codesign, guided by the Y-chart approach, leads to mixed-signal systems with reduced costs compared to systems designed with the traditional methodology. The Y-chart approach also enables the use of coarse quantization as an additional design parameter to further reduce costs. This is illustrated by two case studies. The first case study concentrates on the design of a digital predistorter for Power Amplifiers (PAs) in telecommunication transmitters. In the second case study, we reconsider the design of a part of a Radio Telescope, used for Radio Astronomy. This part is called the Tied Array Adder and it sums signals from different telescopes. Both case studies show that coarse quantization can lead to mixed-signal systems with lower costs but system parameters will change. The explicit reconsideration of functional specifications, facilitated by the Y-chart approach, is therefore essential for the introduction of coarse quantization.

  6. A high-linearity digital-to-time converter technique: constant-slope charging

    NARCIS (Netherlands)

    Ru, Jiayoon Zhiyu; Palattella, Claudia; Geraedts, Paul; Klumperink, Eric; Nauta, Bram

    2015-01-01

    A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL

  7. Converting Topographic Maps into Digital Form to Aid in Archeological Research in the Peten, Guatemala

    Science.gov (United States)

    Aldrich, Serena R.

    1999-01-01

    The purpose of my project was to convert a topographical map into digital form so that the data can be manipulated and easily accessed in the field. With the data in this particular format, Dr. Sever and his colleagues can highlight the specific features of the landscape that they require for their research of the ancient Mayan civilization. Digital elevation models (DEMs) can also be created from the digitized contour features adding another dimension to their research.

  8. Gluing Lidar Signals Detected in Analog-to-Digital and Photon Counting Modes

    Science.gov (United States)

    Feng, Chang-Zhong; Liu, Bing-Yi; Liu, Jin-Tao; Wu, Song-Hua

    2016-06-01

    Lidar is one of the most effective tools for atmospheric remote sensing. For a ground-based lidar system, the backscattered light usually has large dynamic range. Photon-counting mode has the capability to measure weak signal from high altitude, while Analog-to-Digital mode with better linearity is good at measuring strong signal at low altitude. In some lidar systems, atmospheric return signal is measured in both Analog-to-Digital and Photon Counting modes and combined into an entire profile by using a gluing algorithm. A method for gluing atmospheric return signal is developed and tested. For the Photon Counting signal, the saturation characteristics are analyzed to calculate the coefficients for correction. Then the Analog-to-Digital and Photon Counting signals are glued by a weighted average process. Results show the glued signal is reliable at both low and high altitudes.

  9. 模数转换系统无杂散动态范围的测量技巧%Measurement Techniques for Spurious Free Dynamic Range(SFDR) of Analog to Digital Converter (ADC)

    Institute of Scientific and Technical Information of China (English)

    杨莉军; 朱晓峰; 刘书明

    2013-01-01

    SFDR是评估ADC模数转换系统的重要指标,往往决定了数据采集和信号处理系统的整体性能,但在实际工程中很难得到准确的测量结果。其原因有对概念的理解问题、测试条件问题、算法问题以及测试技巧问题。总结了多年工程实践的经验,从多个方面分析了影响SFDR准确测量的因素,提出了解决的办法和技巧。根据提示,基本可以测量出满意的ADC模数转换系统的SFDR指标。%SFDR is an important index in evaluating the ADC module conversion system, often determines the overall performance of the data acquisition and signal processing system , but it is difficult to get accurate measurement results in the practical engineering. The reasons are for the understanding of the concept of the algorithm, test conditions, and test techniques. Summarizing many years experience of en-gineering practice, are analyzed from the aspects of multiple factors influencing SFDR accurate measurement, which puts forward the solution and skill. According to this article, we can basicly measure the satisfactory SFDR indicator of ADC modulus conversion system.

  10. Time-stretch analog-to-digital conversion with a photonic crystal fiber

    Institute of Scientific and Technical Information of China (English)

    TENG Yun; YU Chong-xiu; YUAN Jin-hui; CHEN Jing-xuan; JIN Cang; XU Qian

    2011-01-01

    All-optical analog-to-digital conversion (ADC) has been extensively researched to break through the inherently limited operating speed of electronic devices. In this paper, we use the photonic crystal fiber (PCF) for time-stretch (TS) analog-todigital (A/D) conversion system through generating low noise, linear chirp distribution and fiat super-continuum (SC).Based on the radio frequency (RF) analog signal modulated to the linearly chirped super-continuum, the large-dispersion photonic crystal fiber is used for time-domain stretching.

  11. A Novel Analog-to-digital conversion Technique using nonlinear duty-cycle modulation

    Directory of Open Access Journals (Sweden)

    Jean Mbihi

    2012-06-01

    Full Text Available A new type of analog-to-digital conversion technique is presented in this paper. The interfacing hardware is a very simple nonlinear circuit with 1-bit modulated output. As a implication, behind the hardware simplicity retained is hidden a dreadful nonlinear duty-cycle modulation ratio. However, the overall nonlinear behavior embeds a sufficiently wide linear range, for a rigorous digital reconstitution of the analog input signal using a standard linear filter. Simulation and experimental results obtained using a well tested prototyping system, show the feasibility and good quality of the proposed conversion technique.

  12. Counting photons at low temperature with a streaming time-to-digital converter

    NARCIS (Netherlands)

    Di Stefano, P. C. F.; Nadeau, P.; Onderwater, C. J. G.; Trudeau, C.; Verdier, M. -A.

    2013-01-01

    We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time struct

  13. A Temperature-to-Digital Converter Based on an Optimized Electrothermal Filter

    NARCIS (Netherlands)

    Kashmiri, S.M.; Xia, S.; Makinwa, K.A.A.

    2009-01-01

    This paper describes the design of a CMOS temperature-to-digital converter (TDC). It operates by measuring the temperature-dependent phase shift of an electrothermal filter (ETF). Compared to previous work, this TDC employs an ETF whose layout has been optimized to minimize the thermal phase spread

  14. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band

    OpenAIRE

    Wali, Naveen; Radhakrishnan, Balamurali

    2013-01-01

    An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the impo...

  15. A 33fJ/Step SAR Capacitance-to-Digital Converter Using a Chain of Inverter-Based Amplifiers

    KAUST Repository

    Omran, Hesham

    2016-11-16

    A 12 - bit energy-efficient capacitive sensor interface circuit that fully relies on capacitance-domain successive approximation (SAR) technique is presented. Analysis shows that for SAR capacitance-to-digital converter (CDC) comparator offset voltage will result in parasitic-dependent conversion errors, which necessitates using an offset cancellation technique. Based on the presented analysis, a SAR CDC that uses a chain of cascode inverter-based amplifiers with near-threshold biasing is proposed to provide robust, energy-efficient, and fast operation. A hybrid coarse-fine capacitive digital-to-analog converter (CapDAC) achieves 11.7 - bit effective resolution, and provides 83% area saving compared to a conventional binary weighted implementation. The prototype fabricated in a 0.18μm CMOS technology is experimentally verified using MEMS capacitive pressure sensor. Experimental results show an energy efficiency figure-of-merit (FoM) of 33 f J/Step which outperforms the state-of-the-art. The CDC output is insensitive to analog references; thus, a very low temperature sensitivity of 2.3 ppm/°C is achieved without the need for calibration.

  16. Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

    CERN Document Server

    Baschirotto, Andrea; Steyaert, Michiel

    2013-01-01

    This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

  17. KM3NeT Neutrino Telescope 1-ns Resolution Time To Digital Converters

    Science.gov (United States)

    Calvo, David; Real, Diego

    2016-04-01

    The KM3NeT collaboration aims the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The main digitization system is composed by 31 Time to Digital Converter channels with 1-ns resolution embedded in a Field Programmable Gate Array. An architecture with low resource occupancy has been chosen allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The 4-oversampling technique with two high frequency clocks working in opposed phases has been used together with an asymmetric FIFO memory. In the present article the architecture and the first results obtained with the Time to Digital Converters are presented.

  18. A digital-analog hybrid system and its application to the automatic flight control system simulation research

    Science.gov (United States)

    1981-01-01

    The characteristics of a digital-analog hybrid system composed of a DJS-8 digital computer and a HMJ-200 analog computer are described as well as its applications to simulation research for an automatic flight control system. A hybrid computational example is included to illustrate the application.

  19. 用于CMOS低中频GPS接收机的模数转换器的设计考虑与实现%Design Considerations and Implementation of an Analog-to-Digital Converter for a CMOS Low-IF GPS Receiver

    Institute of Scientific and Technical Information of China (English)

    莫太山; 叶甜春; 马成炎

    2008-01-01

    首先对用于CMOS低中频GPS接收机的模数转换器(ADC)进行了设计考虑.由ADC引入的信噪比降低与四个因素有关:中频带宽,采样率,ADC的比特数及ADC的最大阈值与噪声均方根比值.在设计考虑的基础上,采用TSMC 0.25tan CMOS单层多晶硅五层金属工艺实现了一个4 bit 16.368 MHz闪烁型模数转换器,并将重点放在了前置放大器和提出的新的比较器的设计和优化上.在时钟采样率16.368 MHz和输入信号频率4.092 MHz的条件下,转换器测试得到的信噪失真比为24.7 dB,无杂散动态范围为32.1 dB,积分非线性为+0.31/-0.46LSB,差分非线性为+0.66/-0.46LSB,功耗为3.5mW.ADC占用芯片面积0.07 mm2.%The design considerations of an analog-to-digital converter (ADC) for a CMOS Low-IF GPS re- ceiver are described first. Signal-to-noise degradation due to ADC is dependent on four factors: the IF bandwidth, the sampling rate, the number of bits of the ADC, and the ratio of the maximum ADC thresh-old to the root-mean-square noise level. Then based on the design considerations, a 4 bit 16. 368 MHz Flash ADC is implemented using TSMC 0. 25/μm CMOS single-poly five-metal process and the special at-tention is spent on the design and optimization of the preamplifier and proposed new comparator. The con-verter achieves a peak signal-to-noise-and-distortion ratio of 24.7 dB, peak spurious-free dynamic range of 32.1 dB, integral nonlinearity of +0. 31/-0. 46LSB, integral nonlinearity of +0.66/-0.46LSB, and a pow-er of 3.5 mW at 16.368 MHz clock and fin=4. 092 MHz. The converter occupies 0.07 mm2 of chip area.

  20. Digitized self-oscillating loop for piezoelectric transformer-based power converters

    DEFF Research Database (Denmark)

    Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe;

    2016-01-01

    A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise...... frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints...

  1. Digital Background Calibration Algorithm for High-Speed and High-Resolution Analog-Digital Converter%高速高精度模数转换器的数字后台校准算法

    Institute of Scientific and Technical Information of China (English)

    熊召新; 蔡敏; 贺小勇

    2013-01-01

    This paper deals with the digital background calibration technique of analog-to-digital converter (ADC) and presents a new algorithm applied to the high-speed and high-resolution 2.5-b/stage pipelined ADC.In this algorithm,signal-dependent dither signals are injected into the 2.5-b/stage flip-over multiplying DAC (MDAC) to measure the nonlinear errors resulting from capacitor mismatch and finite opamp gain in MDAC and feed back the errors to the digital outputs of pipelined ADC for correction.This calibration algorithm is easy to realize and can works at very high speed without interrupting the normal operation of high-resolution ADC.Moreover,it can effectively calibrate all gain errors resulting from capacitor mismatch,finite opamp gain and other sources.Behavior simulation results show that,by using the proposed calibration scheme,the signal-to-noise distortion ratio increases from 63.3 dB to 78.7 dB and the spurious-free dynamic range improves from 63.9 dB to 91.8 dB.%研究了模数转换器(ADC)的数字后台校准技术,提出了一种针对2.5b/级高速高精度流水线ADC的数字后台校准算法.在2.5b/级电容翻转式余量增益电路(MDAC)中注入与输入信号相关的抖动信号,提取MDAC中由于电容失配和放大器增益有限性造成的非线性误差,并在最终的数字输出端对这些误差进行校准.文中提出的数字后台校准算法具有电路实现简单、不中断ADC正常工作、适合高速高精度流水线ADC等优点,能有效地降低电容失配和放大器有限增益等非理想因素对流水线ADC精度的影响.仿真结果表明,经校准后的ADC信号噪声失真比可从63.3 dB提高到78.7 dB,无杂散动态范围由63.9 dB提高到91.8dB.

  2. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

  3. A new program on digitizing analog seismograms

    Science.gov (United States)

    Wang, Maofa; Jiang, Qigang; Liu, Qingjie; Huang, Meng

    2016-08-01

    Historical seismograms contain a great variety of useful information which can be used in the study of earthquakes. It is necessary for researchers to digitize analog records and extract the information just as modern computing analysis requires. Firstly, an algorithm based on color scene filed method is presented in order to digitize analog seismograms. Secondly, an interactive software program using C# has been developed to digitize seismogram traces from raster files quickly and accurately. The program can deal with gray-scale images stored in a suitable file format and it offers two different methods: manual digitization and automatic digitization. The test result of the program shows that the methods presented in this paper can lead to good performance.

  4. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

    2015-01-21

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

  5. Counting photons at low temperature with a streaming time-to-digital converter

    CERN Document Server

    Di Stefano, P C F; Onderwater, C J G; Trudeau, C; Verdier, M -A

    2012-01-01

    We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time structure of a ZnWO4 scintillator are comparable to those obtained with a fast digitizer. Streaming data also provides flexibility in analyzing the data, in terms of coincidence window between the channels, and acquisition window of individual channels. We discuss the effect of changing these parameters, and use them to confirm low-energy features in the spectra of the number of detected photons, such as the 60 keV line from 241Am in the ZnWO4 sample. We lastly use the TDC to study the transmission of the optical cryostat employed in these studies at various temperatures.

  6. A high-resolution time-to-digital converter using a three-level resolution

    Science.gov (United States)

    Dehghani, Asma; Saneei, Mohsen; Mahani, Ali

    2016-08-01

    In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.

  7. A four channel, self-calibrating, high resolution, time to digital converter

    CERN Document Server

    Mota, M

    1998-01-01

    A four channel, self-calibrating, High Resolution Time to Digital Converter (HRTDC) with an RMS error of 35 ps over a dynamic range of 3.2 \\mu s has been developed. Its architecture is based on an arr ay of delay locked loops and an 8-bit coarse time counter driven by an 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read- out FIFO. The HRTDC has been built in a 0.7 \\mu m CMOS process using 23 mm^2 of silicon area.

  8. Digital Operation of Microelectronic Circuits Analogous to Protein Hydrogen Bonding Networks

    Directory of Open Access Journals (Sweden)

    Elitsa Gieva

    2012-12-01

    Full Text Available Two hydrogen bonding networks with water molecules and branching residues extracted from β-lactamase protein are investigated and their proton transfer characteristics are studied by creating analogous electrical circuits consisting of block-elements. The block-elements and their proton transfer are described by polynomials that are coded in Matlab and in Verilog-A for use in the Spectre simulator of Cadence IC design system. DC and digital pulse analyses are performed to demonstrate that some circuit outputs behave as repeaters while other - behave as inverters. The results also showed that the HBN circuits might behave as a D-latch and a demultiplexer.

  9. Signal-to-noise ratio estimation in digital computer simulation of lowpass and bandpass systems with applications to analog and digital communications, volume 3

    Science.gov (United States)

    Tranter, W. H.; Turner, M. D.

    1977-01-01

    Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation.

  10. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Science.gov (United States)

    Zhang, Jie; Zhou, Dongming

    2015-01-01

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns.

  11. Simulation of the High Performance Time to Digital Converter for the ATLAS Muon Spectrometer trigger upgrade

    Science.gov (United States)

    Meng, X. T.; Levin, D. S.; Chapman, J. W.; Zhou, B.

    2016-09-01

    The ATLAS Muon Spectrometer endcap thin-Resistive Plate Chamber trigger project compliments the New Small Wheel endcap Phase-1 upgrade for higher luminosity LHC operation. These new trigger chambers, located in a high rate region of ATLAS, will improve overall trigger acceptance and reduce the fake muon trigger incidence. These chambers must generate a low level muon trigger to be delivered to a remote high level processor within a stringent latency requirement of 43 bunch crossings (1075 ns). To help meet this requirement the High Performance Time to Digital Converter (HPTDC), a multi-channel ASIC designed by CERN Microelectronics group, has been proposed for the digitization of the fast front end detector signals. This paper investigates the HPTDC performance in the context of the overall muon trigger latency, employing detailed behavioral Verilog simulations in which the latency in triggerless mode is measured for a range of configurations and under realistic hit rate conditions. The simulation results show that various HPTDC operational configurations, including leading edge and pair measurement modes can provide high efficiency (>98%) to capture and digitize hits within a time interval satisfying the Phase-1 latency tolerance.

  12. Video signal processing system uses gated current mode switches to perform high speed multiplication and digital-to-analog conversion

    Science.gov (United States)

    Gilliland, M. G.; Rougelot, R. S.; Schumaker, R. A.

    1966-01-01

    Video signal processor uses special-purpose integrated circuits with nonsaturating current mode switching to accept texture and color information from a digital computer in a visual spaceflight simulator and to combine these, for display on color CRT with analog information concerning fading.

  13. Transceiver Design with Low-Precision Analog-to-Digital Conversion : An Information-Theoretic Perspective

    CERN Document Server

    Singh, Jaspreet; Madhow, Upamanyu

    2008-01-01

    Modern communication receiver architectures center around digital signal processing (DSP), with the bulk of the receiver processing being performed on digital signals obtained after analog-to-digital conversion (ADC). In this paper, we explore Shannon-theoretic performance limits when ADC precision is drastically reduced, from typical values of 8-12 bits used in current communication transceivers, to 1-3 bits. The goal is to obtain insight on whether DSP-centric transceiver architectures are feasible as communication bandwidths scale up, recognizing that high-precision ADC at high sampling rates is either unavailable, or too costly or power-hungry. Specifically, we evaluate the communication limits imposed by low-precision ADC for the ideal real discrete-time Additive White Gaussian Noise (AWGN) channel, under an average power constraint on the input. For an ADC with K quantization bins (i.e., a precision of log2 K bits), we show that the Shannon capacity is achievable by a discrete input distribution with at...

  14. The ARAGORN front-end—An FPGA based implementation of a Time-to-Digital Converter

    Science.gov (United States)

    Büchele, M.; Fischer, H.; Herrmann, F.; Schaffer, C.

    2017-02-01

    We present the ARAGORN front-end, a cost-optimized, high-density Time-to-Digital Converter platform. Four Xilinx Artix-7 FPGAs implement 384 channels with an average time resolution of 165 ps on a single module. A fifth FPGA acts as data concentrator and generic board master. The front-end features a SFP+ transceiver for data output and an optional multi-channel optical transceiver slot to interconnect with up to seven boards though a star topology. This novel approach makes it possible to read out up to eight boards yielding 3072 input channels via a single optical fiber at a bandwidth of 6.6 Gb/s.

  15. Design of a delay-locked-loop-based time-to-digital converter

    Science.gov (United States)

    Zhaoxin, Ma; Xuefei, Bai; Lu, Huang

    2013-09-01

    A time-to-digital converter (TDC) based on a reset-free and anti-harmonic delay-locked loop (DLL) circuit for wireless positioning systems is discussed and described. The DLL that generates 32-phase clocks and a cycle period detector is employed to avoid “false locking". Driven by multiphase clocks, an encoder detects pulses and outputs the phase of the clock when the pulse arrives. The proposed TDC was implemented in SMIC 0.18 μm CMOS technology, and its core area occupies 0.7 × 0.55 mm2. The reference frequency ranges from 20 to 150 MHz. An LSB resolution of 521 ps can be achieved by using a reference clock of 60 MHz and the DNL is less than ±0.75 LSB. It dissipates 31.5 mW at 1.8 V supply voltage.

  16. High-Resolution Digital-to-Time Converter Implemented in an FPGA Chip

    Directory of Open Access Journals (Sweden)

    Hai Wang

    2017-01-01

    Full Text Available This paper presents the design and implementation of a new digital-to-time converter (DTC. The obtained resolution is 1.02 ps, and the dynamic range is about 590 ns. The experimental results indicate that the measured differential nonlinearity (DNL and integral nonlinearity (INL are −0.17~+0.13 LSB and −0.35~+0.62 LSB, respectively. This DTC builds coarse and fine Vernier delay lines constructed by programmable delay lines (PDLs to ensure high performance delay. Benefited by the close-loop feedback mechanism of the PDLs’ control module, the presented DTC has excellent voltage and temperature stability. What is more, the proposed DTC can be implemented in a single field programmable gate array (FPGA chip.

  17. CMOS time-to-digital converters for mixed-mode signal processing

    Directory of Open Access Journals (Sweden)

    Fei Yuan

    2014-04-01

    Full Text Available This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs. The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs and pipelined TDCs are studied and their pros and cons are compared. Noise-shaping TDCs that reduce in-band noise below technology limit are investigated. These TDCs include gated ring oscillator TDCs, switched ring oscillator TDCs, relaxation oscillator TDCs, ΔΣ TDCs and MASH TDCs. The performance of sampling and noise-shaping TDCs is compared. The direction of future research on TDCs is explored.

  18. A new approach to improve dynamic characteristics of digitally controlled buck-boost dc-dc converter

    OpenAIRE

    2010-01-01

    This paper presents a new digital control buck-boost dc-dc converter with bias model to improve dynamic characteristics. The buck-boost converter needs to respond appropriately to changing input voltage and load change with wide input voltage. This approach makes adjustment to the bias value by input voltage and output current. As a result, it is revealed that not only the dynamic characteristics but also static characteristics can be improved and it is effective for wide range input voltage.

  19. Design and characterization of a mixed-signal PCB for digital-to-analog conversion in a modular and scalable infrared scene projector

    Science.gov (United States)

    Benedict, Jacob

    Infra-red (IR) sensors have proven instrumental in a wide variety of fields from military to industrial applications. The proliferation of IR sensors has spawned an intense push for technologies that can test and calibrate the multitudes of IR sensors. One such technology, IR scene projection (IRSP), provides an inexpensive and safe method for the testing of IR sensor devices. Previous efforts have been conducted to develop IRSPs based on super-lattice light emitting diodes (SLEDS). A single-color 512x512 SLEDs system has been developed, produced, and tested as documented in Corey Lange's Master's thesis, and a GOMAC paper by Rodney McGee [1][2]. Current efforts are being undergone to develop a two-color 512x512 SLEDs system designated (TCSA). The following thesis discusses the design and implementation of a custom printed circuit board (PCB), known as the FMC 4DAC, that contains both analog and digital signals. Utilizing two 16-bit digital-to-analog converters (DAC) the purpose of the board is to provide four analog current output channels for driving the TCSA system to a maximum frame rate of 1 kHz. In addition, the board supports a scalable TCSA system architecture. Several copies of the board can be run in parallel to achieve a range of analog channels between 4 and 32.

  20. A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

    Directory of Open Access Journals (Sweden)

    Mahdi Rezvanyvardom

    2014-12-01

    Full Text Available Time to digital converter (TDC is a key block for time-gated single photon avalanche diode (SPAD arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented. The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited. The proposed converter features high accuracy, very small average error and high linear range. Also this converter has some advantages such as low circuit complexity, low power consumption and low sensitive to the temperature, power supply and process changes (PVT compared with the time to digital converters that used preceding conversion techniques. The proposed converter uses an indirect time to digital conversion method. Therefore, our converter has the appropriate linearity without extra elements. In order to evaluate the proposed idea, an integrating time to digital converter is designed in 0.18 μm CMOS technology and was simulated by Hspice. Comparison of the theoretical and simulation results confirms the proposed TDC operation; therefore, the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

  1. A 26 ps RMS time-to-digital converter core for Spartan-6 FPGAs

    CERN Document Server

    Bourdeauducq, Sebastien

    2013-01-01

    We have designed, implemented and tested a time-to-digital converter core in a low-cost Spartan-6 FPGA. Our design exploits the finite propagation speed in carry chains to realize a delay line in which the propagation distance of the incoming signal's edges is measured using hundreds of taps. This technique enables the core to reach a precision far better than the minimum switching period of the FPGA flip-flops. To compensate for process, voltage and temperature (PVT) effects, our design uses a combination of two techniques: startup calibration and online calibration. The startup calibration uses a statistical method to estimate the delay between the taps of the delay line and helps eliminate the effect of process variations. The online calibration, which takes place without disruption of the core's operation, uses a ring oscillator whose frequency instability is measured and used to compensate for subsequent voltage and temperature effects on the delay line. Our tests show that our design reaches a precision...

  2. A flexible multi-channel high-resolution time-to-digital converter ASIC

    CERN Document Server

    Mota, M; Debieux, S; Ryzhov, V; Moreira, P; Marchioro, A

    2000-01-01

    A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution ( similar to 25ps - 8OOps binning) and a dynamic range of 102.4mus has been implemented in a 0.25mum CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-dee...

  3. Evolution of Photonic Time Stretch: From Analog to Digital Conversion to Blood Screening

    CERN Document Server

    Jalali, Bahram; Fard, Ali; Kim, Sang Hyup

    2011-01-01

    We show how the ability to slow down, amplify, and capture fast transient events can produce high-throughput real-time instruments ranging from digitizers to imaging flow cytometers for detection of rare diseased cells in blood.

  4. A 96-channel FPGA-based time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold [Chicago U., EFI; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Phillips, Thomas J [Duke U.; Wilson, Peter [Fermilab

    2005-02-01

    We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

  5. High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

    Energy Technology Data Exchange (ETDEWEB)

    Pan, Weibin, E-mail: pwb.thu@gmail.com; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

    2014-02-21

    The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km{sup 2} areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper.

  6. A new realization of time-to-digital converters based on FPGA internal routing resources.

    Science.gov (United States)

    Wang, Hai; Zhang, Min; Yao, Qin

    2013-09-01

    Time-to-digital converters (TDC) implemented in a single field-programmable gate array (FPGA) chip which overcome the difficulties found in other FPGA-based TDCs are proposed in this paper. Emphasis is placed on the construction of two delay lines with a good delay consistency, as well as a minimum delay difference by which the measurement resolution can be improved and measurement error can be reduced. A modified vernier delay line structure is introduced which abandoned special delay elements and directly used FPGA internal routing resources to generate the cell delay. To get a good consistency for the system, manual placement and manual routing are used to standardize the delays. The resolution of the system is 9 ps and the standard deviation is less than 1 least significant bit (LSB) within the whole measurement range. The corrected differential nonlinearity is as low as 0.11 LSB. Experiments showed that the proposed system features high accuracy, low cost, and high stability.

  7. Time-to-digital converter card for multichannel time-resolved single-photon counting applications

    Science.gov (United States)

    Tamborini, Davide; Portaluppi, Davide; Tisa, Simone; Tosi, Alberto

    2015-03-01

    We present a high performance Time-to-Digital Converter (TDC) card that provides 10 ps timing resolution and 20 ps (rms) timing precision with a programmable full-scale-range from 160 ns to 10 μs. Differential Non-Linearity (DNL) is better than 1.3% LSB (rms) and Integral Non-Linearity (INL) is 5 ps rms. Thanks to the low power consumption (400 mW) and the compact size (78 mm x 28 mm x 10 mm), this card is the building block for developing compact multichannel time-resolved instrumentation for Time-Correlated Single-Photon Counting (TCSPC). The TDC-card outputs the time measurement results together with the rates of START and STOP signals and the number of valid TDC conversions. These additional information are needed by many TCSPC-based applications, such as: Fluorescence Lifetime Imaging (FLIM), Time-of-Flight (TOF) ranging measurements, time-resolved Positron Emission Tomography (PET), single-molecule spectroscopy, Fluorescence Correlation Spectroscopy (FCS), Diffuse Optical Tomography (DOT), Optical Time-Domain Reflectometry (OTDR), quantum optics, etc.

  8. Radiation-tolerant delta-sigma time-to-digital converters

    CERN Document Server

    Cao, Ying; Steyaert, Michiel

    2015-01-01

    This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.   · �...

  9. Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

    Science.gov (United States)

    Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

    1993-01-01

    The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

  10. Comparison between analog and digital filters

    Directory of Open Access Journals (Sweden)

    Zoltan Erdei

    2010-12-01

    Full Text Available Digital signal processing(DSP is one of the most powerful technologies and will model science and engineering in the 21st century. Revolutionary changes have already been made in different areas of research such as communications, medical imaging, radar and sonar technology, high fidelity audio signal reproducing etc. Each of these fields developed a different signal processing technology with its own algorithms, mathematics and technology, Digital filters are used in two general directions: to separate mixed signals and to restore signals that were compromised in different modes. The objective of this paper is to compare some basic digital filters versus analog filters such as low-pass, high-pass, band-pass filters. Scientists and engineers comprehend that, in comparison with analog filters, digital filters can process the same signal in real-time with broader flexibility. This understanding is considered important to instill incentive for engineers to become interested in the field of DSP. The analysis of the results will be made using dedicated libraries in MATLAB and Simulink software, such as the Signal Processing Toolbox.

  11. A 45.8fJ/Step, energy-efficient, differential SAR capacitance-to-digital converter for capacitive pressure sensing

    KAUST Repository

    Alhoshany, Abdulaziz

    2016-05-03

    An energy-efficient readout circuit for a capacitive sensor is presented. The capacitive sensor is digitized by a 12-bit energy efficient capacitance-to-digital converter (CDC) that is based on a differential successive-approximation architecture. This CDC meets extremely low power requirements by using an operational transconductance amplifier (OTA) that is based on a current-starved inverter. It uses a charge-redistribution DAC that involves coarse-fine architecture. We split the DAC into a coarse-DAC and a fine-DAC to allow a wide capacitance range in a compact area. It covers a wide range of capacitance of 16.14 pF with a 4.5 fF absolute resolution. An analog comparator is implemented by cross-coupling two 3-input NAND gates to enable power and area efficient operation. The prototype CDC was fabricated using a standard 180 nm CMOS technology. The 12-bit CDC has a measurement time of 42.5 μs, and consumes 3.54 μW and 0.29 μW from analog and digital supplies, respectively. This corresponds to a state-of-the-art figure-of-merit (FoM) of 45.8 fJ/conversion-step. © 2016 Elsevier B.V. All rights reserved.

  12. Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes

    KAUST Repository

    Omran, Hesham

    2015-11-01

    Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications. However, the sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this dissertation, we propose several energy-efficient CDC architectures for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine multislope CDC that employs both current and frequency scaling to achieve significant improvement in energy efficiency. Second, we analyze the limitations of successive approximation (SAR) CDC, and we address these limitations by proposing a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM) of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent energy efficiency for a scalable sample rate. In the second part of this dissertation, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report mismatch measurements for subfemtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors

  13. The characterization and application of a low resource FPGA-based time to digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

    2014-03-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

  14. Step-by-Step Design of an FPGA-Based Digital Compensator for DC/DC Converters Oriented to an Introductory Course

    Science.gov (United States)

    Zumel, P.; Fernandez, C.; Sanz, M.; Lazaro, A.; Barrado, A.

    2011-01-01

    In this paper, a short introductory course to introduce field-programmable gate array (FPGA)-based digital control of dc/dc switching power converters is presented. Digital control based on specific hardware has been at the leading edge of low-medium power dc/dc switching converters in recent years. Besides industry's interest in this topic, from…

  15. DC to DC converters: operation; Hacheurs: fonctionnement

    Energy Technology Data Exchange (ETDEWEB)

    Bernot, F. [Ecole d' Ingenieurs de Tours, 37 (France)

    2002-05-01

    This article deals with pulse width modulation (PWM) and pulse position modulation (PPM) DC to DC converters. A tri-phase PWM converter is made of 6 simple DC/DC converters grouped together into 3 reversible converters of the same type: 1 - single-quadrant voltage lowering converters (hydraulic analogy, study with ideal elements, full scheme with input and output filters); 2 - single-quadrant voltage raising converters (hydraulic analogy, operation); 3 - two quadrants reversible converters (structure construction, quadrants of operation, reversible converter connected to a DC motor); 4 - four-quadrants reversible converters; 5 - other converters structure (current converters and converters with intermediate storage, asymmetrical converters, converters with capacitive storage, insulated converters, resonating converters, status); 6 - conclusion. (J.S.)

  16. Digital and analog gene circuits for biotechnology.

    Science.gov (United States)

    Roquet, Nathaniel; Lu, Timothy K

    2014-05-01

    Biotechnology offers the promise of valuable chemical production via microbial processing of renewable and inexpensive substrates. Thus far, static metabolic engineering strategies have enabled this field to advance industrial applications. However, the industrial scaling of statically engineered microbes inevitably creates inefficiencies due to variable conditions present in large-scale microbial cultures. Synthetic gene circuits that dynamically sense and regulate different molecules can resolve this issue by enabling cells to continuously adapt to variable conditions. These circuits also have the potential to enable next-generation production programs capable of autonomous transitioning between steps in a bioprocess. Here, we review the design and application of two main classes of dynamic gene circuits, digital and analog, for biotechnology. Within the context of these classes, we also discuss the potential benefits of digital-analog interconversion, memory, and multi-signal integration. Though synthetic gene circuits have largely been applied for cellular computation to date, we envision that utilizing them in biotechnology will enhance the efficiency and scope of biochemical production with living cells.

  17. Analog tekst i digital kontekst

    DEFF Research Database (Denmark)

    Nicolaisen, Maria Skou

    2014-01-01

    at have en legitimerende såvel som en strukturerende funktion, hvilket indvirker på læsningen af den pågældende tekst. Den vil proklamere, at traditionelle tekst- og læseformer synes understøttet af digitaliseringen, og diskutere hvordan kvalitativ tekstanalyse stadig har relevans i en digital tidsalder...

  18. Low-frequency analog signal distribution on digital photonic networks by optical delta-sigma modulation

    Science.gov (United States)

    Kanno, Atsushi; Kawanishi, Tetsuya

    2013-12-01

    We propose a delta-sigma modulation scheme for low- and medium-frequency signal transmission in a digital photonic network system. A 10-Gb/s-class optical transceiver with a delta-sigma modulator utilized as a high-speed analog-to-digital converter (ADC) provides a binary optical signal. On the signal reception side, a low-cost and slow-speed photonic receiver directly converts the binary signal into an analog signal at frequencies from several hundreds of kilohertz several tens of megahertz. Further, by using a clock and data recovery circuit at the receiver to reduce jitters, the single-sideband phase noise of the generated signals can be significantly reduced.

  19. Digital-Analog Converter Based on Pulse Width Modulated Force Feedback in Sigma-Delta Accelerometer%Σ△微加速度计中基于脉宽调制的力反馈回路

    Institute of Scientific and Technical Information of China (English)

    陶呈瑶; 邓康发

    2013-01-01

    针对微加速度计接口电路的Sigma-Delta(撞驻)数字反馈系统,提出了一种基于脉宽调制( PWM)的力反馈回路:利用模拟低通滤波器将PWM波解调成模拟输出信号,具有滤波和数模转换功能。首先建立微加速度计撞驻闭环反馈系统的Simulink模型并进行了系统级仿真。之后采用Filter Solutions滤波器设计软件确定三阶低通巴特沃斯滤波器,并采用Pspice仿真软件进行电路级仿真。最后将制作的PCB版电路进行测试:PWM波通过力反馈回路能还原成高保真度的模拟信号,输出信号和输入信号的频率相对误差小于0.36%,等效DAC分辨率为8 bit。试验表明,此方案结构简单、成本低,能以较低电路复杂度实现高精度的模拟信号输出。%Aiming at the Sigma-Delta(Σ△) digital force feedback system in Mcro-accelerometer interface circuit,this paper presents a force feedback loop based on Pulse Width Modulator(PWM). The PWM wave can be translated into output analog singal using low pass filter,indicating that this circuit has a dual function of filter and digital to analog conversion( DAC) . Firstly,Σ△closed loop feedback system was simulated in Simulink model for system level simulation,then Filter Solutions software was used for designing three-order Butterworth low pass filter,and Pspice software was adopted for circuit level simulation. Finally electronic circuit was made by PCB and then tested. Through the force back loop,the wave can be successfully translate to undistorted analog signal,and the maximun relative error is below 0. 36% compared to the input signal,the equivalent DAC resolution is 8 bit. This experiment shows that this method has the advantages of simple structure,low cost,and easy way to produce high precise output analog signal.

  20. An Open-Source Tool Set Enabling Analog-Digital-Software Co-Design

    Directory of Open Access Journals (Sweden)

    Michelle Collins

    2016-02-01

    Full Text Available This paper presents an analog-digital hardware-software co-design environment for simulating and programming reconfigurable systems. The tool simulates, designs, as well as enables experimental measurements after compiling to configurable systems in the same integrated design tool framework. High level software in Scilab/Xcos (open-source programs similar to MATLAB/Simulink that converts the high-level block description by the user to blif format (sci2blif, which acts as an input to the modified VPR tool, including the code v p r 2 s w c s , encoding the specific platform through specific architecture files, resulting in a targetable switch list on the resulting configurable analog–digital system. The resulting tool uses an analog and mixed-signal library of components, enabling users and future researchers access to the basic analog operations/computations that are possible.

  1. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    Directory of Open Access Journals (Sweden)

    Chao Chen

    2014-01-01

    Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

  2. A robust parasitic-insensitive successive approximation capacitance-to-digital converter

    KAUST Repository

    Omran, Hesham

    2014-09-01

    In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/oC. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor. © 2014 IEEE.

  3. Implementation of a high resolution (< 11 ps RMS) Time-to-Digital Converter in a Field Programmable Gate Array

    Energy Technology Data Exchange (ETDEWEB)

    Ugur, Cahit [Helmholtz-Institut Mainz, Johannes Gutenberg-Universitaet Mainz (Germany); Bayer, Eugen [Department for Digital Electronics, University Kassel (Germany); Kurz, Nikolaus; Traxler, Michael [GSI Helmholtz Centre for Heavy Ion Research, Darmstadt (Germany); Michel, Jan [Institute for Nuclear Physics, Goethe University Frankfurt, Frankfurt am Main (Germany)

    2012-07-01

    A high resolution time-to-digital converter (TDC) was implemented in a general purpose field-programmable gate array (FPGA), a re-programmable digital chip. RMS and the time resolution of different channels are calculated for one clock cycle (5 ns) interval and a minimum of 10.3 ps RMS on two channels is achieved, which yields to a time resolution of 7.3 ps (10.3 ps/{radical}(2)) on a single channel. The TDC can be used in time-of-flight, time-over-threshold, drift time measurement applications as well as many other measurements with specific Front-End Electronics (FEE), e.g. charge measurements with charge-to-width (Q2W) FEE. The re-programmable flexibility of FPGAs also allows to have application specific features, e.g. trigger window, zero dead time etc.

  4. A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

    CERN Document Server

    Mester, C; Morira, P

    2008-01-01

    A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.

  5. MENGOLAH DATA VIDEO ANALOG MENJADI VIDEO DIGITAL SEDERHANA

    Directory of Open Access Journals (Sweden)

    Nick

    2010-09-01

    Full Text Available Nowadays, editing technology has entered the digital age. Technology will demonstrate the evidence of processing analog to digital data has become simpler since editing technology has been integrated in the society in all aspects. Understanding the technique of processing analog to digital data is important in producing a video. To utilize this technology, the introduction of equipments is fundamental to understand the features. The next phase is the capturing process that supports the preparation in editing process from scene to scene; therefore, it will become a watchable video.

  6. Analog circuit design structured mixed-mode design, multi-bit sigma-delta converters, short range RF circuits

    CERN Document Server

    van Roermund, Arthur

    2007-01-01

    Preface. Part I: Structured Mixed-Mode Design. Introduction. Structured Oscillator Design; C. Verhoeven, A. van Staveren. Systematic Design of High-frequency gm-C Filters; E. Lauwers, G. Gielen. Structured LNA Design; E.H. Nordholt. High-Level Simulation and Modeling Tools for Mixed-Signal Front-ends of Wireless Systems; P. Wambacq, et al. Structured Simulation-Based Analog Design Synthesis; R.A. Rutenbar. Structured Analog layout Design; K. Lampaert. Part II: Multi-Bit Sigma Delta Converters. Introduction. Architecture Considerations for Multi-Bit SigmaDelta ADCs; T. Brooks. Multirate Sigma-Delta Modulators, an Alternative to Multibit; F. Colodro, A. Torralba. Circuit Design Aspects of Multi-Bit Delta-Sigma Converters; Y. Geerts, et al. High-speed Digital to Analog Converter Issues with Applications to Sigma Delta Modulators; K. Doris, et al. Correction-Free Multi-Bit Sigma-Delta Modulators for ADSL; R. del Rio, et al. Sigma Delta Converters in Wireline Communications; A. Wiesbauer, et al. Part III: Short Ra...

  7. Analog/digital pH meter system I.C.

    Science.gov (United States)

    Vincent, Paul; Park, Jea

    1992-01-01

    The project utilizes design automation software tools to design, simulate, and fabricate a pH meter integrated circuit (IC) system including a successive approximation type seven-bit analog to digital converter circuits using a 1.25 micron N-Well CMOS MOSIS process. The input voltage ranges from 0.5 to 1.0 V derived from a special type pH sensor, and the output is a three-digit decimal number display of pH with one decimal point.

  8. Digitally Controlled Analog Signal Processing

    Science.gov (United States)

    1988-04-01

    Self-Tuned Filters,’ Proc. 26th Mid- west Symp. Ckts Systems, Puebla , Mexico, 1983. V in V C Fig. 6. (Compensated) OTA Integrator. DigWitly ControlDW...Proc. WS Mid- filters obtained by cascading the proposed second-order wat Symp. Circuits Sjdanwk INAOE, Puebla , Mex- block is presently under...REF IN and the instru- ment has warmed up at least 20 minutes at the ambient temperature. FREOUENCY: * Mesursmeet Buale 20 Hz to 40.1 MHz ODiplayed 114

  9. Conversion of the Defense Communications System from Analog to Digital Form.

    Science.gov (United States)

    1974-06-01

    Digital Services ," Proceedings of the IEEE, LX, No. 11 (November 1972), 1352. I p. 1353. 69Allen R. Worley, "The DATRAN System," Proceedings o t he IEE...August 1973, entire issue. Cox, J. E. "Western Union Digital Services ." Proceedings of the IEEE, LX, No. 11 (November 1972), 1350-57. "Crosstalk." Lenkurt

  10. FPGA-based Time to Digital Converter and Data Acquisition system for High Energy Tagger of KLOE-2 experiment

    CERN Document Server

    Iafolla, L; Beretta, M; Ciambrone, P; Gatta, M; Gonnella, F; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.

  11. FPGA-based time to digital converter and data acquisition system for high energy tagger of KLOE-2 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Iafolla, L., E-mail: lorenzo.iafolla@lnf.infn.it [INFN-LNF, Frascati, Rome (Italy); Università di Roma Tor Vergata, Rome (Italy); Balla, A.; Beretta, M.; Ciambrone, P.; Gatta, M.; Gonnella, F. [INFN-LNF, Frascati, Rome (Italy); Mascolo, M.; Messi, R. [Università di Roma Tor Vergata, Rome (Italy); INFN-Sezione Roma 2, Rome (Italy); Moricciani, D. [INFN-Sezione Roma 2, Rome (Italy); Riondino, D. [INFN-LNF, Frascati, Rome (Italy)

    2013-08-01

    In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.

  12. Development of a sub-nanosecond time-to-digital converter based on a field-programmable gate array

    Science.gov (United States)

    Sano, Y.; Tomoto, M.; Horii, Y.; Sasaki, O.; Uchida, T.; Ikeno, M.

    2016-03-01

    The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers.

  13. A hybrid digital-analog long pulse integrator

    Science.gov (United States)

    Strait, E. J.; Broesch, J. D.; Snider, R. T.; Walker, M. L.

    1997-01-01

    A digital-analog integrator has been developed for use with inductive magnetic sensors in long-pulse tokamaks. Continuous compensation of input offsets is accomplished by alternating analog-to-digital convertor samples from the sensor and a dummy load, while a RC network provides passive integration between samples. Typically a sampling rate of 10 kHz is used. In operational tests on the DIII-D tokamak, digital and analog integration of tokamak data show good agreement. The output drift error during a 1200 s integration interval corresponds to a few percent of the anticipated signal for poloidal field probes in International Thermonuclear Experimental Reactor, and bench tests suggest that the error can be reduced further.

  14. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  15. Novel method for converting digital Fresnel hologram to phase-only hologram based on bidirectional error diffusion.

    Science.gov (United States)

    Tsang, P W M; Poon, T-C

    2013-10-01

    We report a novel and fast method for converting a digital, complex Fresnel hologram into a phase-only hologram. Briefly, the pixels in the complex hologram are scanned sequentially in a row by row manner. The odd and even rows are scanned from opposite directions, constituting to a bidirectional error diffusion process. The magnitude of each visited pixel is forced to be a constant value, while preserving the exact phase value. The resulting error is diffused to the neighboring pixels that have not been visited before. The resulting novel phase-only hologram is called the bidirectional error diffusion (BERD) hologram. The reconstructed image from the BERD hologram exhibits high fidelity as compared with those obtained with the original complex hologram.

  16. FPGA implementation of digital down converter using CORDIC algorithm

    Science.gov (United States)

    Agarwal, Ashok; Lakshmi, Boppana

    2013-01-01

    In radio receivers, Digital Down Converters (DDC) are used to translate the signal from Intermediate Frequency level to baseband. It also decimates the oversampled signal to a lower sample rate, eliminating the need of a high end digital signal processors. In this paper we have implemented architecture for DDC employing CORDIC algorithm, which down converts an IF signal of 70MHz (3G) to 200 KHz baseband GSM signal, with an SFDR greater than 100dB. The implemented architecture reduces the hardware resource requirements by 15 percent when compared with other architecture available in the literature due to elimination of explicit multipliers and a quadrature phase shifter for mixing.

  17. Sin/cosine encoder interpolation methods: encoder to digital tracking converters for rate and position loop controllers

    Science.gov (United States)

    Jenkins, Steven T.; Hilkert, J. M.

    2008-04-01

    Pointing and tracking applications usually require relative gimbal angles to be measured for reporting and controlling the line-of-sight angular position. Depending on the application, angular resolution and/or accuracy might jointly or independently determine the angle transducer requirements. In the past decade, encoders have been increasingly taking the place of inductive devices where the measurement of angles over a wide range is required. This is primarily due to the fact that encoders are now achieving very high resolution in smaller sizes than was previously possible. These advances in resolution are primarily due to improved encoder disk and detector technology along with developments in interpolation techniques. Measurement accuracy, on the other hand, is primarily determined by mounting and bearing eccentricity as it is with all angular measurement devices. For very demanding accuracy requirements, some type of calibration of the assembled system may be the only solution, in which case transducer repeatability is paramount. This paper describes a unique encoder-to-digital tracking converter concept for improving interpolation of optical encoders. The new method relies on Fraunhofer diffraction models to correct the non-ideal sin/cos outputs of the encoder detectors. Diffraction model concepts are used in the interpolation filters to predict the phase of non-ideal sin and cosine encoder outputs. The new method also minimizes many of the open loop pre-processing requirements and assumptions that limit interpolation accuracy and rate loop noise performance in ratiometric tracking converter designs.

  18. A flexible 32-channel time-to-digital converter implemented in a Xilinx Zynq-7000 field programmable gate array

    Science.gov (United States)

    Wang, Yonggang; Kuang, Jie; Liu, Chong; Cao, Qiang; Li, Deng

    2017-03-01

    A high performance multi-channel time-to-digital converter (TDC) is implemented in a Xilinx Zynq-7000 field programmable gate array (FPGA). It can be flexibly configured as either 32 TDC channels with 9.9 ps time-interval RMS precision, 16 TDC channels with 6.9 ps RMS precision, or 8 TDC channels with 5.8 ps RMS precision. All TDCs have a 380 M Samples/second measurement throughput and a 2.63 ns measurement dead time. The performance consistency and temperature dependence of TDC channels are also evaluated. Because Zynq-7000 FPGA family integrates a feature-rich dual-core ARM based processing system and 28 nm Xilinx programmable logic in a single device, the realization of high performance TDCs on it will make the platform more widely used in time-measuring related applications.

  19. Weather satellite picture receiving stations, APT digital scan converter

    Science.gov (United States)

    Vermillion, C. H.; Kamowski, J. C.

    1975-01-01

    The automatic picture transmission digital scan converter is used at ground stations to convert signals received from scanning radiometers to data compatible with ground equipment designed to receive signals from vidicons aboard operational meteorological satellites. Information necessary to understand the circuit theory, functional operation, general construction and calibration of the converter is provided. Brief and detailed descriptions of each of the individual circuits are included, accompanied by a schematic diagram contained at the end of each circuit description. Listings of integral parts and testing equipment required as well as an overall wiring diagram are included. This unit will enable the user to readily accept and process weather photographs from the operational meteorological satellites.

  20. A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications.

    Science.gov (United States)

    Cheng, Zeng; Deen, M Jamal; Peng, Hao

    2016-04-01

    In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 mm(2). Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date.

  1. Digital Carrier Modulation and Sampling Issues of Matrix Converters

    DEFF Research Database (Denmark)

    Loh, Poh Chiang; Rong, Runjie; Blaabjerg, Frede

    2009-01-01

    digital carrier modulation schemes for controlling conventional (direct) and indirect matrix converters with minimized semiconductor commutation count and smooth sextant transitions with no erroneous states produced. For guaranteeing the latter two features, correct digital sampling instants and state...... sequence reversal must be chosen appropriately, as demonstrated in the paper for the two different topological options,which, to date, have not yet been discussed in the existing literature. To validate the concepts discussed, experimental testing on the implemented conventional and indirect matrix...

  2. Digital carrier modulation and sampling issues of matrix converters

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Loh, P.C.; Rong, R.J.

    2008-01-01

    digital carrier modulation schemes for controlling conventional and sparse matrix converters with minimized semiconductor commutation count and smooth sextant transitions with no erroneous states produced. For guaranteeing the latter two features, correct digital sampling instants and state sequence...... reversal must be chosen appropriately, as demonstrated in the paper for the two different topological options, which to date, have not yet been discussed in the existing literature. To validate the concepts discussed, experimental testing on the implemented conventional and sparse matrix laboratory...

  3. Epistemic Function and Ontology of Analog and Digital Images

    Directory of Open Access Journals (Sweden)

    Aleksandra Łukaszewicz Alcaraz

    2016-01-01

    Full Text Available The important epistemic function of photographic images is their active role in construction and reconstruction of our beliefs concerning the world and human identity, since we often consider photographs as presenting reality or even the Real itself. Because photography can convince people of how different social and ethnic groups and even they themselves look, documentary projects and the dissemination of photographic practices supported the transition from disciplinary society to the present-day society of control. While both analog and digital images are formed from the same basic materia, the ways in which this matter appears are distinctive. In the case of analog photography, we deal with physical and chemical matter, whereas with digital images we face electronic matter. Because digital photography allows endless modification of the image, we can no longer believe in the truthfulness of digital images.

  4. Digial Technology Qualification Task 2 - Suitability of Digital Alternatives to Analog Sensors and Actuators

    Energy Technology Data Exchange (ETDEWEB)

    Ted Quinn; Jerry Mauck

    2012-09-01

    The next generation reactors in the U.S. are an opportunity for vendors to build new reactor technology with advanced Instrumentation and Control Systems (control rooms, DCS, etc.). The advances made in the development of many current generation operating reactors in other parts of the world are being used in the design and construction of new plants. These new plants are expected to have fully integrated digital control rooms, computerized procedures, integrated surveillance testing with on-line monitoring and a major effort toward improving the O&M and fault survivability of the overall systems. In addition the designs are also incorporating major improvements in the man-machine interface based on lessons learned in nuclear and other industries. The above relates primarily to the scope of supply in instrumentation and control systems addressed by Chapter 7 of the Standard Review Plan (SRP) NUREG-0800 (Reference 9.5), and the associated Balance of Plant (BOP) I&C systems. This does not relate directly to the actuator and motor, breaker, initiation circuitry, valve position, etc. which is the subject of this report and normally outside of the traditional Distributed Control System (DCS), for both safety and non-safety systems. The recommendations presented in this report will be used as input to I&C research programming for the implementation of lessons learned during the early phases of new build both for large light water reactors (LWR) and also small modular reactors (SMR). This report is intended to support current research plans and provide user (vendor, owner-operator) input to the optimization of these research plans.

  5. Anticipatory Functions, Digital-Analog Forms and Biosemiotics

    DEFF Research Database (Denmark)

    Arnellos, Argyris; Bruni, Luis Emilio; El-Hani, Charbel Niño;

    2012-01-01

    our overall approach. We adopt a Peircean approach to Biosemiotics, and a dynamical approach to Digital-Analog relations and to the interplay between different levels of functionality in autonomous systems, taking an integrative approach. We then apply the underlying biosemiotic logic to a particular...

  6. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  7. Hardware-Algorithms Co-Design and Implementation of an Analog-to-Information Converter for Biosignals Based on Compressed Sensing.

    Science.gov (United States)

    Pareschi, Fabio; Albertini, Pierluigi; Frattini, Giovanni; Mangia, Mauro; Rovatti, Riccardo; Setti, Gianluca

    2016-02-01

    We report the design and implementation of an Analog-to-Information Converter (AIC) based on Compressed Sensing (CS). The system is realized in a CMOS 180 nm technology and targets the acquisition of bio-signals with Nyquist frequency up to 100 kHz. To maximize performance and reduce hardware complexity, we co-design hardware together with acquisition and reconstruction algorithms. The resulting AIC outperforms previously proposed solutions mainly thanks to two key features. First, we adopt a novel method to deal with saturations in the computation of CS measurements. This allows no loss in performance even when 60% of measurements saturate. Second, the system is able to adapt itself to the energy distribution of the input by exploiting the so-called rakeness to maximize the amount of information contained in the measurements. With this approach, the 16 measurement channels integrated into a single device are expected to allow the acquisition and the correct reconstruction of most biomedical signals. As a case study, measurements on real electrocardiograms (ECGs) and electromyograms (EMGs) show signals that these can be reconstructed without any noticeable degradation with a compression rate, respectively, of 8 and 10.

  8. Digitally assisted analog beamforming for millimeter-wave communication

    NARCIS (Netherlands)

    Kokkeler, A.B.J.; Smit, G.J.M.

    2015-01-01

    The paper addresses the research question on how digital beamsteering algorithms can be combined with analog beamforming in the context of millimeter-wave communication for next generation (5G) cellular systems. Key is the use of coarse quantisation of the individual antenna signals next to the anal

  9. Comparison of analog and digital transceiver systems for MR imaging.

    Science.gov (United States)

    Hashimoto, Seitaro; Kose, Katsumi; Haishi, Tomoyuki

    2014-01-01

    We critically evaluated analog and digital transceivers for magnetic resonance (MR) imaging systems under identical experimental conditions to identify and compare their advantages and disadvantages. MR imaging experiments were performed using a 4.74-tesla vertical-bore superconducting magnet and a high sensitivity gradient coil probe. We acquired 3-dimensional spin echo images of a kumquat with and without using a gain-stepping scan technique to extend the dynamic range of the receiver systems. The acquired MR images clearly demonstrated nearly identical image quality for both transceiver systems, but DC and ghosting artifacts were obtained for the analog transceiver system. We therefore concluded that digital transceivers have several advantages over the analog transceivers.

  10. The three and a half layers of dynamics : analog, digital, semi-digital, analog

    CERN Document Server

    Singh, T P

    2011-01-01

    Quantum theory is extremely successful in explaining most physical phenomena, and is not contradicted by any experiment. Yet, the theory has many puzzling features : the occurrence of probabilities, the unclear distinction between the microscopic and the macroscopic, the unexplained absence of superpositions in positions of macroscopic objects, the dependence of the theory on an external classical time, and the experimentally verified but peculiar `influence' outside the light-cone in EPR experiments. These puzzles point towards a conflict between quantum theory and our present understanding of spacetime structure, and suggest the existence of a deeper theory. In this essay we make the case that in the underlying theory the matter and spacetime degrees of freedom are non-commuting matrices, and yet the dynamics is analog. A digital quantum-theory like dynamics for matter as well as spacetime emerges in the statistical thermodynamic approximation to this deeper theory. When most of the matter clumps into macro...

  11. A Design of High—precision High—Voltage Fiber—Optic Analog Signal Isolation Converter

    Institute of Scientific and Technical Information of China (English)

    李建伟; 许留伟; 等

    2002-01-01

    This paper introduces a design of high-precision high-voltage fiber-optic analog signal isolation converter based on the technology of Voltage-to-Frequency(V/F) and Frequency-to-Voltage(F/V) conversion.It describes the principle,system configuration and hardware desin.

  12. A design of High-precision High-Voltage Fiber-Optic Analog Signal Isolation Converter

    Institute of Scientific and Technical Information of China (English)

    李建伟; 许留伟; 刘小宁; 杨雷

    2002-01-01

    This paper introduces a design of high-prectison high-voltage fiber-optic analog sig-nal isoaltion converter based on the technology of Voltage-to-Fequency (V/F)and Frequency -to Voltage(F/V) conversion It describes the principle ,system configuration and hardware design

  13. Direct Digital Demultiplexing of Analog TDM Signals for Cable Reduction in Ultrasound Imaging Catheters.

    Science.gov (United States)

    Carpenter, Thomas M; Rashid, M Wasequr; Ghovanloo, Maysam; Cowell, David M J; Freear, Steven; Degertekin, F Levent

    2016-08-01

    In real-time catheter-based 3-D ultrasound imaging applications, gathering data from the transducer arrays is difficult, as there is a restriction on cable count due to the diameter of the catheter. Although area and power hungry multiplexing circuits integrated at the catheter tip are used in some applications, these are unsuitable for use in small sized catheters for applications, such as intracardiac imaging. Furthermore, the length requirement for catheters and limited power available to on-chip cable drivers leads to limited signal strength at the receiver end. In this paper, an alternative approach using analog time-division multiplexing (TDM) is presented, which addresses the cable restrictions of ultrasound catheters. A novel digital demultiplexing technique is also described, which allows for a reduction in the number of analog signal processing stages required. The TDM and digital demultiplexing schemes are demonstrated for an intracardiac imaging system that would operate in the 4- to 11-MHz range. A TDM integrated circuit (IC) with an 8:1 multiplexer is interfaced with a fast analog-to-digital converter (ADC) through a microcoaxial catheter cable bundle, and processed with a field-programmable gate array register-transfer level simulation. Input signals to the TDM IC are recovered with -40-dB crosstalk between the channels on the same microcoax, showing the feasibility of this system for ultrasound imaging applications.

  14. High-Resolution Time-to-Digital Converter in Field Programmable Gate Array

    CERN Document Server

    Aloisio, A; Cicalese, R; Giordano, R; Izzo, V; Loffredo, S; Lomoro, R

    2008-01-01

    Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.

  15. On automatic synthesis of analog/digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.

  16. The application of standardized control and interface circuits to three dc to dc power converters.

    Science.gov (United States)

    Yu, Y.; Biess, J. J.; Schoenfeld, A. D.; Lalli, V. R.

    1973-01-01

    Standardized control and interface circuits were applied to the three most commonly used dc to dc converters: the buck-boost converter, the series-switching buck regulator, and the pulse-modulated parallel inverter. The two-loop ASDTIC regulation control concept was implemented by using a common analog control signal processor and a novel digital control signal processor. This resulted in control circuit standardization and superior static and dynamic performance of the three dc-to-dc converters. Power components stress control, through active peak current limiting and recovery of switching losses, was applied to enhance reliability and converter efficiency.

  17. Building Digital Libraries for Analog People: Ten Common Design Pitfalls and How To Avoid Them.

    Science.gov (United States)

    Johnson, Doug

    2000-01-01

    Reviews design factors to consider when planning library media centers. Highlights include planning teams; planning for more than one kind of learning; considering community as well as school use; planning for existing technology rather than future possibilities; considering ease of supervision; traffic patterns; lighting and sound damping; and…

  18. Synthetic analog and digital circuits for cellular computation and memory

    OpenAIRE

    Purcell, Oliver; Lu, Timothy K.

    2014-01-01

    Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss r...

  19. Digital Control Technologies for Modular DC-DC Converters

    Science.gov (United States)

    Button, Robert M.; Kascak, Peter E.; Lebron-Velilla, Ramon

    2002-01-01

    Recent trends in aerospace Power Management and Distribution (PMAD) systems focus on using commercial off-the-shelf (COTS) components as standard building blocks. This move to more modular designs has been driven by a desire to reduce costs and development times, but is also due to the impressive power density and efficiency numbers achieved by today's commercial DC-DC converters. However, the PMAD designer quickly learns of the hidden "costs" of using COTS converters. The most significant cost is the required addition of external input filters to meet strict electromagnetic interference (MIAMI) requirements for space systems. In fact, the high power density numbers achieved by the commercial manufacturers are greatly due to the lack of necessary input filters included in the COTS module. The NASA Glenn Research Center is currently pursuing a digital control technology that addresses this problem with modular DC-DC converters. This paper presents the digital control technologies that have been developed to greatly reduce the input filter requirements for paralleled, modular DC-DC converters. Initial test result show that the input filter's inductor size was reduced by 75 percent, and the capacitor size was reduced by 94 percent while maintaining the same power quality specifications.

  20. Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

    Energy Technology Data Exchange (ETDEWEB)

    Sano, K., E-mail: sano-kyosuke-cw@ynu.jp [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N. [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Zen, N.; Ohkubo, M. [Research Institute of Instrumentation Frontier, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba 305-8568 (Japan)

    2014-09-15

    Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach.

  1. Noise-shaping gradient descent-based online adaptation algorithms for digital calibration of analog circuits.

    Science.gov (United States)

    Chakrabartty, Shantanu; Shaga, Ravi K; Aono, Kenji

    2013-04-01

    Analog circuits that are calibrated using digital-to-analog converters (DACs) use a digital signal processor-based algorithm for real-time adaptation and programming of system parameters. In this paper, we first show that this conventional framework for adaptation yields suboptimal calibration properties because of artifacts introduced by quantization noise. We then propose a novel online stochastic optimization algorithm called noise-shaping or ΣΔ gradient descent, which can shape the quantization noise out of the frequency regions spanning the parameter adaptation trajectories. As a result, the proposed algorithms demonstrate superior parameter search properties compared to floating-point gradient methods and better convergence properties than conventional quantized gradient-methods. In the second part of this paper, we apply the ΣΔ gradient descent algorithm to two examples of real-time digital calibration: 1) balancing and tracking of bias currents, and 2) frequency calibration of a band-pass Gm-C biquad filter biased in weak inversion. For each of these examples, the circuits have been prototyped in a 0.5-μm complementary metal-oxide-semiconductor process, and we demonstrate that the proposed algorithm is able to find the optimal solution even in the presence of spurious local minima, which are introduced by the nonlinear and non-monotonic response of calibration DACs.

  2. Digital redesign of anti-wind-up controller for cascaded analog system.

    Science.gov (United States)

    Chen, Y S; Tsai, J S H; Shieh, L S; Moussighi, M M

    2003-01-01

    The cascaded conventional anti-wind-up (CAW) design method for integral controller is discussed. Then, the prediction-based digital redesign methodology is utilized to find the new pulse amplitude modulated (PAM) digital controller for effective digital control of the analog plant with input saturation constraint. The desired digital controller is determined from existing or pre-designed CAW analog controller. The proposed method provides a novel methodology for indirect digital design of a continuous-time unity output-feedback system with a cascaded analog controller as in the case of PID controllers for industrial control processes with the presence of actuator saturations. It enables us to implement an existing or pre-designed cascaded CAW analog controller via a digital controller effectively.

  3. Project Birdseye Aerial Photograph Collection: Digital and Analog Materials

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This collection consists of both analog and digital aerial photographs from Arctic areas in and around Baffin Bay, the Labrador Sea, the Arctic Ocean, the Beaufort...

  4. Design of a 12-Bit CMOS Digital-to-Analog Converterwith Current-Steering Architecture%12位CMOS电流舵结构D/A转换器的设计

    Institute of Scientific and Technical Information of China (English)

    贺小勇; 刘三清; 应建华; 郁飞霞

    2001-01-01

    A digital-to-analog converter with current-steering architecture suitable for CMOS process is designed. An 8+4 segmented architecture is presented, and the trade-off between area and performance is considered. The circuit has been simulated and a desirable result is achieved.%设计了一种适用于CMOS工艺的电流舵结构数模转换器,提出8+4分段式的电流舵结构,权衡了面积与性能的关系。文中对所设计的电路进行了仿真,并得到了很好的仿真结果。

  5. Analog Design for Digital Deployment of a Serious Leadership Game

    Science.gov (United States)

    Maxwell, Nicholas; Lang, Tristan; Herman, Jeffrey L.; Phares, Richard

    2012-01-01

    This paper presents the design, development, and user testing of a leadership development simulation. The authors share lessons learned from using a design process for a board game to allow for quick and inexpensive revision cycles during the development of a serious leadership development game. The goal of this leadership simulation is to accelerate the development of leadership capacity in high-potential mid-level managers (GS-15 level) in a federal government agency. Simulation design included a mixed-method needs analysis, using both quantitative and qualitative approaches to determine organizational leadership needs. Eight design iterations were conducted, including three user testing phases. Three re-design iterations followed initial development, enabling game testing as part of comprehensive instructional events. Subsequent design, development and testing processes targeted digital application to a computer- and tablet-based environment. Recommendations include pros and cons of development and learner testing of an initial analog simulation prior to full digital simulation development.

  6. Oversampling data acquisition to improve resolution of digitized signals.

    Science.gov (United States)

    Pagnacco, G; Oggero, E; Morr, D R; Berme, N

    1997-01-01

    The ability to capture analog signals in a digital format suitable for subsequent storage, processing and analysis by a computer has revolutionized many scientific fields, including biomechanics. In the process of going from the analog signal to its digital representation, it is essential to maintain as much of the original signal content as possible. There is always a loss of information associated with the conversion from analog to digital, independently of how it is actually performed. The only possibility to reduce the loss of information is to increase the number of states or the resolution of the digital signal. The method presented here, based on the same theory used in oversampling analog to digital converters, is applicable to digital signals acquired using any converter. In most situations this method provides a feasible and inexpensive technique to significantly improve the amplitude resolution of the analog to digital conversion. This can be of fundamental importance when the information of interest is small in amplitude compared to the overall signal, or when subsequent ill-conditioned operations, like the computation of the derivatives of the signal, are to be performed.

  7. Two-Phase Interleaved Buck Converter with a new Digital Self-Oscillating Modulkator

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents a new Digital Self-Oscillating Modulator (DiSOM) for DC/DC converters. The DiSOM modulator alllows the digital control algorithm to sample the output voltage at a sampling frequency higher than the converter switching frequency. This enables higher control loop bandwidth than...... for traditional digital PWM modulators given a certain switching frequency. A synchronised version of the DiSOM modulator is derived for interleaved converters. A prototype interleaved Buck converter for Point of Load applications has been designed and built to test the performance of DiSOM modulator. The Di......SOM modulator and a digital control algorithm have been implemented in an FPGA. Experimental results show that the converter has a very fast transient response when a loadstep is applied to the output. For a loadstep of 50% of nominal output current the output voltage overshoot is less than 2.5% of the nominal...

  8. Digital control of high-frequency switched-mode power converters

    CERN Document Server

    Corradini, Luca; Mattavelli, Paolo; Zane, Regan

    This book is focused on the fundamental aspects of analysis, modeling and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner Comprehensive treatment of digital control theory for power converters Verilog and VHDL sample codes are provided Enables readers to successfully analyze, model, design, and implement voltage, current, or multi-loop digital feedback loops around switched-mode power converters Practical examples are used throughout the book to illustrate applications of the techniques developed Matlab examples are also

  9. Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

    Science.gov (United States)

    Tamborini, D.; Portaluppi, D.; Villa, F.; Tisa, S.; Tosi, A.

    2014-11-01

    We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

  10. Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

    Energy Technology Data Exchange (ETDEWEB)

    Tamborini, D., E-mail: davide.tamborini@polimi.it; Portaluppi, D.; Villa, F.; Tosi, A. [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Tisa, S. [Micro Photon Devices, via Stradivari 4, 39100 Bolzano (Italy)

    2014-11-15

    We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

  11. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  12. Tremor suppression using functional electrical stimulation: a comparison between digital and analog controllers.

    Science.gov (United States)

    Gillard, D M; Cameron, T; Prochazka, A; Gauthier, M J

    1999-09-01

    In this study, we compared digital and analog versions of a functional electrical stimulator designed to suppress tremor. The device was based on a closed-loop control system designed to attenuate movements in the tremor frequency range, without significantly affecting slower, voluntary movements. Testing of the digital filter was done on three patients with Parkinsonian tremor and the results compared to those of a functional electrical stimulation device based on an analog filter evaluated in a previous study. Additional testing of both the analog and digital filters was done on three subjects with no neurological impairment performing tremor-like movements and slow voluntary movements. We found that the digital controller provided a mean attenuation of 84%, compared to 65% for the analog controller.

  13. The Digital Fields Board for the FIELDS instrument suite on the Solar Probe Plus mission: Analog and digital signal processing

    Science.gov (United States)

    Malaspina, David M.; Ergun, Robert E.; Bolton, Mary; Kien, Mark; Summers, David; Stevens, Ken; Yehle, Alan; Karlsson, Magnus; Hoxie, Vaughn C.; Bale, Stuart D.; Goetz, Keith

    2016-06-01

    The first in situ measurements of electric and magnetic fields in the near-Sun environment (Solar Probe Plus mission. The Digital Fields Board (DFB) is an electronics board within FIELDS that performs analog and digital signal processing, as well as digitization, for signals between DC and 60 kHz from five voltage sensors and four search coil magnetometer channels. These nine input signals are processed on the DFB into 26 analog data streams. A specialized application-specific integrated circuit performs analog to digital conversion on all 26 analog channels simultaneously. The DFB then processes the digital data using a field programmable gate array (FPGA), generating a variety of data products, including digitally filtered continuous waveforms, high-rate burst capture waveforms, power spectra, cross spectra, band-pass filter data, and several ancillary products. While the data products are optimized for encounter-based mission operations, they are also highly configurable, a key design aspect for a mission of exploration. This paper describes the analog and digital signal processing used to ensure that the DFB produces high-quality science data, using minimal resources, in the challenging near-Sun environment.

  14. [Comparative evaluation of six different body regions of the dog using analog and digital radiography].

    Science.gov (United States)

    Meyer-Lindenberg, Andrea; Ebermaier, Christine; Wolvekamp, Pim; Tellhelm, Bernd; Meutstege, Freek J; Lang, Johann; Hartung, Klaus; Fehr, Michael; Nolte, Ingo

    2008-01-01

    In this study the quality of digital and analog radiography in dogs was compared. For this purpose, three conventional radiographs (varying in exposure) and three digital radiographs (varying in MUSI-contrast [MUSI = MUlti Scale Image Contrast], the main post-processing parameter) of six different body regions of the dog were evaluated (thorax, abdomen, skull, femur, hip joints, elbow). The quality of the radiographs was evaluated by eight veterinary specialists familiar with radiographic images using a questionnaire based on details of each body region significant in obtaining a radiographic diagnosis. In the first part of the study the overall quality of the radiographs was evaluated. Within one region, 89.5% (43/48) chose a digital radiograph as the best image. Divided into analog and digital groups, the digital image with the highest MUSI-contrast was most often considered the best, while the analog image considered the best varied between the one with the medium and the one with the longest exposure time. In the second part of the study, each image was rated for the visibility of specific, diagnostically important details. After summarisation of the scores for each criterion, divided into analog and digital imaging, the digital images were rated considerably superior to conventional images. The results of image comparison revealed that digital radiographs showed better image detail than radiographs taken with the analog technique in all six areas of the body.

  15. Phase-locked loops. [in analog and digital circuits communication system

    Science.gov (United States)

    Gupta, S. C.

    1975-01-01

    An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

  16. Analog and digital systems of imaging in roentgenodiagnostics.

    Science.gov (United States)

    Oborska-Kumaszyńska, Dominika; Wiśniewska-Kubka, Sylwia

    2010-04-01

    In the recent years, we have been witnessing a very dynamic development of diagnostic methods of imaging. In contemporary radiology, the carrier of the diagnostic information is the image, obtained as a result of an X-ray beam transmitted through the patient's body, with modulation of intensity, and processing of data collected by the detector. Depending on the diagnostic method used, signals can be detected with analog (x-ray film) or digital systems (CR, DR and DDR). Each of these methods of image acquisition, due to its own technological solutions, determines a different quality of imaging (diagnostic data). The introduction of digital image receptors, instead of conventional SF systems, increased the patient dose, as a result of a gradually increasing exposure. This followed from the fact that in digital systems, the increased radiation dose reduces image noise and improves image quality, and that is owing to the data capacity of these systems (impossible in SF systems with a limited data capacity of the image detector). The availability of the multitude of imaging systems, each characterized by disparate qualitative and quantitative parameters, implies the problem of evaluation and enforcement of a proper efficiency from manufacturers of these systems.At the same time, there is a legal problem present in our country, i.e. the lack of laws and regulations regarding standards of the scope of quality control (parameters) and measurement methodology for the systems of digital image acquisition. In the European countries, the scope and standards of control are regulated by the manufacturers and European Guidelines, whereas in the United States, AAPM Reports have been introduced, that specifically describe methods of tests performance, their frequency, as well as target values and limits. This paper is a review of both, the scope of quality control parameters of image detectors in analog and digital systems of imaging, and the measurement methodology. The parameters

  17. A Power Conditioning Stage Based on Analog-Circuit MPPT Control and a Superbuck Converter for Thermoelectric Generators in Spacecraft Power Systems

    Science.gov (United States)

    Sun, Kai; Wu, Hongfei; Cai, Yan; Xing, Yan

    2014-06-01

    A thermoelectric generator (TEG) is a very important kind of power supply for spacecraft, especially for deep-space missions, due to its long lifetime and high reliability. To develop a practical TEG power supply for spacecraft, a power conditioning stage is indispensable, being employed to convert the varying output voltage of the TEG modules to a definite voltage for feeding batteries or loads. To enhance the system reliability, a power conditioning stage based on analog-circuit maximum-power-point tracking (MPPT) control and a superbuck converter is proposed in this paper. The input of this power conditioning stage is connected to the output of the TEG modules, and the output of this stage is connected to the battery and loads. The superbuck converter is employed as the main circuit, featuring low input current ripples and high conversion efficiency. Since for spacecraft power systems reliable operation is the key target for control circuits, a reset-set flip-flop-based analog circuit is used as the basic control circuit to implement MPPT, being much simpler than digital control circuits and offering higher reliability. Experiments have verified the feasibility and effectiveness of the proposed power conditioning stage. The results show the advantages of the proposed stage, such as maximum utilization of TEG power, small input ripples, and good stability.

  18. Digitally Controlled Offline Converter with Galvanic Isolation Based on an 8-bit Microcontroller

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side...

  19. Digital-analog quantum simulation of generalized Dicke models with superconducting circuits

    Science.gov (United States)

    Lamata, Lucas

    2017-01-01

    We propose a digital-analog quantum simulation of generalized Dicke models with superconducting circuits, including Fermi- Bose condensates, biased and pulsed Dicke models, for all regimes of light-matter coupling. We encode these classes of problems in a set of superconducting qubits coupled with a bosonic mode implemented by a transmission line resonator. Via digital-analog techniques, an efficient quantum simulation can be performed in state-of-the-art circuit quantum electrodynamics platforms, by suitable decomposition into analog qubit-bosonic blocks and collective single-qubit pulses through digital steps. Moreover, just a single global analog block would be needed during the whole protocol in most of the cases, superimposed with fast periodic pulses to rotate and detune the qubits. Therefore, a large number of digital steps may be attained with this approach, providing a reduced digital error. Additionally, the number of gates per digital step does not grow with the number of qubits, rendering the simulation efficient. This strategy paves the way for the scalable digital-analog quantum simulation of many-body dynamics involving bosonic modes and spin degrees of freedom with superconducting circuits. PMID:28256559

  20. Asymmetric bilayer graphene nanoribbon MOSFETs for analog and digital electronics

    Science.gov (United States)

    Dinarvand, A.; Ahmadi, V.; Darvish, Gh.

    2016-05-01

    In this paper, a new structure was proposed for bilayer graphene nanoribbon field-effect transistor (BGNFET) mainly to enhance the electrical characteristics in analog and digital applications. The proposed device uses two metallic gates on the top and bottom of a bilayer graphene nanoribbon, which is surrounded by SiO2 and connected to heavily doped source/drain contacts. Electrical properties of the proposed device were explored using fully self-consistent solution of Poisson and Schrödinger equations based on the nonequilibrium Green's function (NEGF) formalism. Significant improvements in the electrical behavior was seen in the simulation results for gates asymmetrically biased. The comparison with graphene nanoribbon FET showed that the proposed structure benefited from higher intrinsic voltage gain and cut-off frequency and improved switching characteristics such as delay and Ion/Ioff ratio.

  1. Switching Arithmetic for DC to DC Converters Using Delta Sigma Modulator Based Control Circuit

    Directory of Open Access Journals (Sweden)

    K.Diwakar

    2016-02-01

    Full Text Available In the proposed arithmetic unit for dc to dc converters using delta sigma modulator, a new technique is proposed for addition and multiplication of sampled analog signals. The output is in digital form to drive the converters. The conventional method has input signal limitation whereas in the proposed method the inputs can vary to full-scale. The addition of two discrete signals is done by sampling the two signals at a period called update period and feeding each signal to the input of signal dependant delta sigma modulator for half of the update period and combining the outputs for the update period. The extension of three discrete data addition can be carried out by using the same technique. For the multiplication of two discrete signals different method is adopted. One analog signal is fed to the input of first delta-sigma modulator (DSM1 after sampling. The sampled output of the second analog signal is negated or not negated depending on the bit state at the output of DSM1 and is fed to the input of second DSM(DSM2. The resulting bit stream at the output of DSM2 is the digital representation of the product of the sampled data of the two analog signals. In order to multiply three discrete data, the sampled output of third data is negated or not negated depending on the bit state at the output of DSM2 and is fed to the input of third DSM(DSM3. The resulting bit stream at the output of DSM3 is the digital representation of the product of the sampled data of the three analog signals. Using the proposed adder and multiplier circuits any expressions can be evaluated such that the average value of the digital output of the arithmetic unit over the update period gives the value of expressions during that period. The digital output of the arithmetic unit is used to drive the dc-dc converters.

  2. The Setup Phase of Project Open Book: A Report to the Commission on Preservation and Access on the Status of an Effort To Convert Microfilm to Digital Imagery.

    Science.gov (United States)

    Conway, Paul; Weaver, Shari

    Digital image quality, indexing structures, and production workflow were the three central issues examined during the second phase--the set-up phase--of Project Open Book, a major effort by Yale University Library to explore the usefulness of digital technologies for preserving and improving access to deteriorating documents. This report outlines…

  3. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger.\

  4. A 70-MS/s 110-mW 8-b CMOS folding and interpolating A/D converter

    NARCIS (Netherlands)

    Nauta, Bram; Venes, Ardie G.W.

    1995-01-01

    A CMOS analog to digital converter based on the folding and interpolating technique is presented. This technique is successfully applied in bipolar A/D converters and now also becomes available in CMOS technology. The analog bandwidth of the A/D converter is increased by using a transresistance ampl

  5. Multi-Channel Optical Digitizer for Earth Sciences Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The main objective was to design and manufacture a multi-channel high resolution analog-digital converter for digitizing a CCD image signal. The tasks included...

  6. An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

    Institute of Scientific and Technical Information of China (English)

    Zhu Xiaoshi; Chen Chixiao; Xu Jialiang; Ye Fan; Ren Junyan

    2013-01-01

    A sampling switch with an embedded digital-to-skew converter (DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430 μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

  7. Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux

    Energy Technology Data Exchange (ETDEWEB)

    Nogrette, F.; Chang, R.; Bouton, Q.; Westbrook, C. I.; Clément, D. [Laboratoire Charles Fabry, Institut d’Optique Graduate School, CNRS, Univ. Paris-Saclay, 91127 Palaiseau cedex (France); Heurteau, D.; Sellem, R. [Fédération de Recherche LUMAT (DTPI), CNRS, Univ. Paris-Sud, Institut d’Optique Graduate School, Univ. Paris-Saclay, F-91405 Orsay (France)

    2015-11-15

    We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 10{sup 6} s{sup −1} and three-dimensional reconstruction of the coordinates up to 3.2 × 10{sup 6} particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 10{sup 5} particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

  8. Characterization of a detector chain using a FPGA-based Time-to-Digital Converter to reconstruct the three-dimensional coordinates of single particles at high flux

    CERN Document Server

    Nogrette, F; Chang, R; Bouton, Q; Westbrook, C I; Sellem, R; Clément, D

    2015-01-01

    We report on the development of a novel FPGA-based Time-to-Digital Converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of Micro-Channel Plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1x10^6 per second and three-dimensional reconstruction of the coordinates up to 2.5x10^6 particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) um. In addition we analyze a method to measure the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work directly apply to the detection of other kinds of particles.

  9. Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux.

    Science.gov (United States)

    Nogrette, F; Heurteau, D; Chang, R; Bouton, Q; Westbrook, C I; Sellem, R; Clément, D

    2015-11-01

    We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 10(6) s(-1) and three-dimensional reconstruction of the coordinates up to 3.2 × 10(6) particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 10(5) particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

  10. The mixed analog/digital shaper of the LHCb preshower

    CERN Document Server

    Lecoq, J; Cornat, R; Perret, P; Trouilleau, C

    2001-01-01

    The LHCb preshower signals show so many fluctuations at low energy that a classical shaping is not usable at all. Thanks to the fact that the fraction of the collected energy during a whole LHC beam crossing time is 85%, we studied the special solution we presented at Snowmass 1999 workshop. This solution consists of 2 interleaved fast integrators, one being in integrate mode when the other is digitally reset. Two track-and-hold systems and an analog multiplexer are used to give at the output 85% of the signal plus 15% of the previous one. These 15% are digitally computed from the previous sample, and subtracted. A completely new design of this solution had to be made. This new design is described, including new methods to decrease the supply voltage and the noise, as well as to increase the quality of the reset and the linearity. An output stage, consisting of an AB class push-pull using only NPN transistors is also described. Laboratory and beam test results are given. (5 refs).

  11. Low-power low-voltage analogue-to-digital converter design for mobile video and wireless applications.

    OpenAIRE

    Adeniran, O. A.

    2006-01-01

    With the rapid embracing and deployment of Wideband Code Division Multiple Access (WCDMA)-based Third Generation (3G) mobile networks 1 in Europe and East Asia and with the ratification of the Digital Video Broadcast - Handheld (DVB-H) - terrestrial television for battery-powered mobile devices standard in Europe 2, minimization of hand-set power consumption is becoming a key requirement Higher baseband bandwidth is necessary for these enhanced wireless and mobile broadcast services, which tr...

  12. A complete theoretical description of the first-order delta-sigma modulation for analog-to-NRZ binary conversion

    Science.gov (United States)

    Siahmakoun, A.; Reeves, E.; Costanzo-Caso, P.

    2015-03-01

    A novel photonic analog-to-digital converter (ADC) based on asynchronous delta-sigma modulation (ADSM) has been investigated. The architecture utilizes an optical leaky integrator, optoelectronic bistable quantizer, and positive corrective feedback for a non-interferometric optical implementation of ADSM. The principles of the proposed 1st -order ADSM are mathematically modeled and simulated.

  13. Quantization Effects on Period Doubling Route to Chaos in a ZAD-Controlled Buck Converter

    Directory of Open Access Journals (Sweden)

    John Alexander Taborda

    2012-01-01

    cycles. On the other hand many studies have been devoted to analyze the ZAD-controlled buck power converter, but these past studies did not include hardware considerations. In this paper, analog-to-digital conversion process is explicitly introduced in the modeling stage. As the feedback gain is varied, the dynamic behavior depending on the analog-to-digital converter resolution is numerically analyzed. Particularly, it is observed that including the quantizer in the model carries out several changes in the transitions to chaos, which include interruption of band-merging process by cascades of periodic inclusions, disappearing of band transitions, and multiple coexisting of periodic orbits. Many of these phenomena have not been reported as a consequence of the quantization effects.

  14. Digitally Controlled Point of Load Converter with Very Fast Transient Response

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only...... three clock cycles from the time the A/D converter result is read by the control algorithm to the time the duty cycle command is updated. A typical POL converter has been built and the experimental results show that the transient response of the converter is very fast. The output voltage overshoot...

  15. Simplified design of data converters

    CERN Document Server

    Lenk, John

    1997-01-01

    Simplified Design of Data Converters shows how to design and experiment with data converters, both analog-to-digital and digital to analog. The design approach here is the same one used in all of John Lenk's best-selling books on simplified and practical design. Throughout the book, design problems start with guidelines for selecting all components on a trial-value basis, assuming a specific design goal and set of conditions. Then, using the guideline values in experimental circuits, the desired results are produced by varying the experimental component values, if needed.If you are a w

  16. Design of a reliable PUF circuit based on R-2R ladder digital-to-analog convertor

    Science.gov (United States)

    Pengjun, Wang; Xuelong, Zhang; Yuejun, Zhang; Jianrui, Li

    2015-07-01

    A novel physical unclonable functions (PUF) circuit is proposed, which relies on non-linear characteristic of analog voltage generated by R-2R ladder DAC. After amplifying the deviation signal, the robustness of the DAC-PUF circuit has increased significantly. The DAC-PUF circuit is designed in TSMC 65 nm CMOS technology and the layout occupies 86.06 × 63.56 μm2. Monte Carlo simulation results show that the reliability of the DAC-PUF circuit is above 98% over a comprehensive range of environmental variation, such as temperature and supply voltage. Project supported by the National Natural Science Foundation of China (Nos. 61474068, 61404076, 61274132), the Zhejiang Provincial Natural Science Foundation of China (No. LQ14F040001), and the K. C. Wong Magna Fund in Ningbo University, China.

  17. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-07-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented.CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, theswitching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation resultsshow that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supplyvoltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method canreduce about 78% in power consumption.

  18. Archive of Digitized Analog Boomer Seismic Reflection Data Collected from Lake Pontchartrain, Louisiana, to Mobile Bay, Alabama, During Cruises Onboard the R/V ERDA-1, June and August 1992

    Science.gov (United States)

    Sanford, Jordan M.; Harrison, Arnell S.; Wiese, Dana S.; Flocks, James G.

    2008-01-01

    . The acoustic energy is reflected at density boundaries (such as the seafloor or sediment layers beneath the seafloor), detected by the hydrophone receiver, and the amplitude of the reflected energy is recorded by an Edward P. Curley Lab (EPC) thermal plotter. This process is repeated at timed intervals (for example, 0.5 s) and recorded for specific intervals of time (for example, 100 ms). The timed intervals are also referred to as the shot interval or fire rate. On analog records, the recorded interval is referred to as the sweep, which is the amount of time the recorder stylus takes to sweep from the top of the record to the bottom of the record, thereby recording the amplitude of the reflected energy of one shot. In this way, consecutive recorded shots produce a two-dimensional (2-D) vertical image of the shallow geologic structure beneath the ship track. Many of the geophysical data collected by the USGS prior to the late 1990s were recorded in analog format and stored as paper copies. Scientists onboard made hand-written annotations onto these records to note latitude and longitude, time, line number, course heading, and geographic points of reference. Each paper roll typically contained numerous survey lines and could reach more than 90 ft in length. All rolls are stored at the USGS FISC-St. Petersburg, FL. To preserve the integrity of these records and improve accessibility, analog holdings were converted to digital files.

  19. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  20. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  1. Principle of time-to-digital converter and its realization%时间测量系统(TDC)的原理及实现

    Institute of Scientific and Technical Information of China (English)

    何超; 陈建政

    2012-01-01

    Vehicle and track interaction is important factors of the evaluation of operation quality of vehicles and line status. It is necessary to develop a continuous measurement of wheel rail force measuring wheelset device. In the measurement of performance parameters of high speed EMU temperature changes and electromagnetic field often bring error to the traditional simulation test system. Then, adoption of the CMOS technique consisting of TDC time to digital converter. By the TDC conversion principle knowable, TDC can work in strong electromagnetic field and it is digital output. The discussion focuses on TDC measurement principle. Not only that, but also discussed the engineering measurement of strain measurement hardware implementation and temperature drift, zero offset adjustment.%车辆与轨道间的作用力是评价车辆运行品质和线路状态的重要因素。研制能够连续精确测量轮轨力的测力轮对装置是非常必要的。由于在对高速动车组轮轨力性能参数的测量中,其温度变化、强电磁场往往会给传统模拟测试系统带来误差。于是,采用了以CMOS技术组成的TDC时间数字测量系统。由TDC的转换原理可知,TDC可在强电磁场下工作,并为数字输出。本文重点讨论了TDC测量原理。不仅如此,也讨论了在工程测量中应变测量的硬件实现和温度偏移、零点偏移的调整。

  2. Digital and Analog Electronics for an autonomous, deep-sea, Gamma Ray Burst Neutrino prototype detector

    Science.gov (United States)

    Manolopoulos, K.; Belias, A.; Markou, C.; Rapidis, P.; Kappos, E.

    2016-04-01

    GRBNeT is a Gamma Ray Burst Neutrino Telescope made of autonomously operated arrays of deep-sea light detectors, anchored to the sea-bed without any cabled connection to the shore. This paper presents the digital and analog electronics that we have designed and developed for the GRBNeT prototype. We describe the requirements for these electronics and present their design and functionality. We present low-power analog electronics for the PMTs utilized in the GRBNeT prototype and the FPGA based digital system for data selection and storage. We conclude with preliminary performance measurements of the electronics systems for the GRBNeT prototype.

  3. Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

    Science.gov (United States)

    Won, Jun Yeon; Kwon, Sun Il; Yoon, Hyun Suk; Ko, Guen Bae; Son, Jeong-Whan; Lee, Jae Sung

    2016-02-01

    This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS.

  4. High resolution time-to-digital converter (TDC) implemented in field programmable gate array (FPGA) with compensated process voltage and temperature (PVT) variations

    Energy Technology Data Exchange (ETDEWEB)

    Herve, C., E-mail: herve@esrf.fr [European Synchrotron Radiation Facility, BP220, F-38043 Grenoble Cedex (France); Cerrai, J.; Le Caeer, T. [European Synchrotron Radiation Facility, BP220, F-38043 Grenoble Cedex (France)

    2012-08-01

    The paper presents and compares FPGA implementations of Time-to-Digital Converters (TDC) developed in the framework of the XNAP project, an international collaboration building Avalanche Photo Diode based area X-ray detectors. We are revisiting and presenting updated results achieved with recent components of two different TDC architectures previously described in the literature. Particularly care is given to optimize the Differential Non-Linearity (DNL) in order to obtain meaningful resolution figures that can be applied to the final applications. In the first implementation, based on a tapped delay line interpolator, the achieved resolution is in the 40-100 ps range. The hardware compensation for process voltage and temperature (PVT) variations, a weak point of FPGA designs, has been fully addressed by developing specific circuitry. Our hardware design allows closing a feedback loop for controlling the FPGA core voltage. PVT variations are therefore compensated by hardware in real time. The second implementation, based on a multiple-phase clock interpolator, the resolution is close to 175 ps. Interpolator DNL better than {+-}0.4 and {+-}0.2 LSB could be achieved. The relative advantages of both architectures are discussed within the scope of the foreseen applications.

  5. A High-Resolution S-band Down-Converting Digital Phase Detector for SASE FEL Use

    CERN Document Server

    Grelick, A E

    2004-01-01

    Each of the rf phase detectors in the Advanced Photon Source linac consists of a module that down converts from S-band to 20 MHz followed by an analog I/Q detector. Phase is calculated from one digitized sample per pulse each of I and Q. The resulting data has excellent long-term stability but is noisy enough so that a number of samples must be averaged to get a usable reading. The more recent requirement to support a SASE FEL has presented the need to accurately resolve the relative phase of a single pulse. Replacing analog detection with digital sampling and replacing internal intermediate frequency reference oscillators with a lower noise external oscillator were used to control the two largest components of noise. The implementation of a central, ultralow noise reference oscillator and a distribution system capable of maintaining the low phase noise is described, together with the results obtained to date. The principal remaining technical issue is determining the processing power required as a function o...

  6. A digitally controlled PWM/PSM dual-mode DC/DC converter

    Institute of Scientific and Technical Information of China (English)

    Zhen Shaowei; Zhang Bo; Luo Ping; Hou Sijian; Ye Jingxin; Ma Xiao

    2011-01-01

    A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator (DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies,which is much more flexible than its analog rivals.The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm2.Experimental results show that the conversion efficiency is high,being 90% at 200 mA and 67% at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability.

  7. Analysis on multiple-component synchronization of ultra-fast time-interleaved analog-to-digital conversion systems and its novel parameterized hardware solution.

    Science.gov (United States)

    Huang, Wuhuang; Wang, Houjun; Tian, Shulin; Ye, Peng; Zeng, Hao; Qiu, Duyu

    2014-10-01

    Parallelism-based technique of time-interleaved analog-to-digital conversion (TIADC) has become an effective solution for the higher sampling rate acquisition system to acquire non-repetitive waveforms. With the increase of sampling frequency, the indeterminacy of combining sequence of sampled data among multiple components has become a highlighted barrier for the reset operation of high-speed acquisition systems, and this is especially obvious for the ultra-fast TIADC systems. In this paper, we clarify the root of the problem in multiple-component synchronization (MCS) caused by such reset operation. Also we propose a novel and reliable hardware solution to precisely condition each reset signal, including three key circuit design parameters, i.e., the best time interval, required edge uncertainty, and the minimum delay precision. Besides, the designing scheme and debugging procedures are presented in detail in a generalized platform of this system type. Finally, in order to demonstrate the feasibility, parametric materialization and testing verification are gradually accomplished in a 20 Giga Samples Per Second (GSPS) TIADC system composed of four 5 GSPS ADC components. The results show that the proposed method is feasible and effective for ensuring the combined determinacy of multiple groups of sampled data and solving the MCS problem. In comparison with other existing solutions, it adopts some simple logic components more easily and flexibly, and this is significant for the development of congeneric systems or instruments featuring the MCS.

  8. Analysis of parallel optical sampling rate and ADC requirements in digital coherent receivers

    DEFF Research Database (Denmark)

    Lorences Riesgo, Abel; Galili, Michael; Peucheret, Christophe

    2012-01-01

    We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator.......We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator....

  9. Design and Implementation of Digital Current Mode Controller for DC-DC Converters

    DEFF Research Database (Denmark)

    Taeed, Fazel

    a bandwidth of 1/10 of the switching frequency. In the current state-of-the-art, the best reported digital PCMC has crossover frequency of 1/15 of the switching frequency. In this PhD study a novel digital PCMC with negligible delay in the inner current loop has been proposed. The proposed solution has...... a bandwidth of 1/10 of the switching frequency; which is an improvement of 50% compared to the best reported digital solution, also the achieved crossover frequency is nearly equal to analog controller crossover frequency. Furthermore, the proposed solution offers an adaptive compensation slope; therefore...

  10. Design of Digital Synthesis Filters for Hybrid Filter Bank A/D Converters Using Semidefinite Programming

    Directory of Open Access Journals (Sweden)

    Wei Wang

    2014-05-01

    Full Text Available Hybrid filter bank (HFB analog-to-digital systems permit wideband, high frequency conversion. This paper presents mixed norm optimal design of digital synthesis filters of a HFB. The mixed norm is a convex combination of the 2-norm and the Chebyshev norm with a weighting parameter. Robust HFB design method based on worst-case ellipsoidal uncertainty in analog filters errors is also proposed. Both the problems can be solved using semidefinite programming. The proposed mixed norm method allows designers to select the best suitable filters among a family of synthesis filters for specific applications, and the robust design method is more insensitive to analog filters errors than the nominal minimax design

  11. Compensation Tuning of Analog and Digital Controllers for First Order Plus Time Delay Plants

    Directory of Open Access Journals (Sweden)

    Miluše VÍTEČKOVÁ

    2011-06-01

    Full Text Available The article is devoted to the simple compensation tuning of analog and digital PI and PID controllers for the first order plus time delay plants. The described method makes controller tuning possible so that the control process is non-oscillatory without an overshoot for all input variables. The use is shown in the example.

  12. Digitally-controlled PC-interfaced Boost Converter for Educational Purposes

    DEFF Research Database (Denmark)

    Ljusev, Petar; Andersen, Michael A. E.

    2004-01-01

    This paper describes implementation of a simple digital PID control algorithm for a boost converter using a cheap fixed-point 8-bit microcontroller. Serial communication to a PC server program is established for easier downloading of compensator parameters and current and voltage waveform...

  13. Analog electronics for radiation detection

    CERN Document Server

    2016-01-01

    Analog Electronics for Radiation Detection showcases the latest advances in readout electronics for particle, or radiation, detectors. Featuring chapters written by international experts in their respective fields, this authoritative text: Defines the main design parameters of front-end circuitry developed in microelectronics technologies Explains the basis for the use of complementary metal oxide semiconductor (CMOS) image sensors for the detection of charged particles and other non-consumer applications Delivers an in-depth review of analog-to-digital converters (ADCs), evaluating the pros and cons of ADCs integrated at the pixel, column, and per-chip levels Describes incremental sigma delta ADCs, time-to-digital converter (TDC) architectures, and digital pulse-processing techniques complementary to analog processing Examines the fundamental parameters and front-end types associated with silicon photomultipliers used for single visible-light photon detection Discusses pixel sensors ...

  14. Parametric Analog Signal Amplification Applied to Nanoscale CMOS Technologies

    CERN Document Server

    Oliveira, João P

    2012-01-01

    This book is dedicated to the analysis of parametric amplification with special emphasis on the MOS discrete-time implementation. This implementation is demonstrated by the presentation of several circuits where the MOS parametric amplifier cell is used: small gain amplifier, comparator with embedded pre-amplification, discrete-time mixer/IIR-Filter, and analog-to-digital converter (ADC).  Experimental results are shown to validate the overall design technique. Provides the complete theoretical analysis, supported by electrical simulations, of the parametric amplification technique in both continuous time and discrete time domains; Describes the design flow of an ADC fully based on discrete-time parametric amplification in CMOS technology; Presents a high speed time-interleaved pipeline ADC, based on parametric MOS amplification techniques described, complementing theory discussed with experimental results.

  15. Digital control of grid connected converters for distributed power generation

    Energy Technology Data Exchange (ETDEWEB)

    Skjellnes, Tore

    2008-07-01

    Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of small scale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid. A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the voltage in response to the output current to create an outward appearance of a source impedance. This is called a virtual impedance. This thesis presents a controller for a voltage controlled three phase pulse width modulated converter. This controller enables operation in standalone mode, in parallel with other converters in a micro grid, and in parallel with a strong main grid. A time varying virtual impedance is presented which mainly attenuates reactive currents. A method of investigating the overall impedance including the virtual impedance is presented. New net standards have been introduced, requiring the converter to operate even during severe dips in the grid voltage. Experiments are presented verifying the operation of the controller during voltage dips. (Author). 37 refs., 65 figs., 10 tabs

  16. Lunar Analog

    Science.gov (United States)

    Cromwell, Ronita L.

    2009-01-01

    In this viewgraph presentation, a ground-based lunar analog is developed for the return of manned space flight to the Moon. The contents include: 1) Digital Astronaut; 2) Bed Design; 3) Lunar Analog Feasibility Study; 4) Preliminary Data; 5) Pre-pilot Study; 6) Selection of Stockings; 7) Lunar Analog Pilot Study; 8) Bed Design for Lunar Analog Pilot.

  17. An Auto ranging Data Converter Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    Jithin Krishnan

    2013-06-01

    Full Text Available A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA - i.e. an all-digital analog to digital (A/D converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range detection unit with 7 bits and a sign bit for polarity detection. The analog part of the modulator is done utilizing the LVDS transceiver in the FPGA making it a real digital one. The digital section of sigma delta ADC containing the decimation filter banks is done in a cascaded filter structure form including a CIC decimation filter, droop compensation and half-band filters. The top level module was coded using VHDL and the simulation was carried out with ModelSim and MATLAB.

  18. A Nonlinear Digital Control Solution for a DC/DC Power Converter

    Science.gov (United States)

    Zhu, Minshao

    2002-01-01

    A digital Nonlinear Proportional-Integral-Derivative (NPID) control algorithm was proposed to control a 1-kW, PWM, DC/DC, switching power converter. The NPID methodology is introduced and a practical hardware control solution is obtained. The design of the controller was completed using Matlab (trademark) Simulink, while the hardware-in-the-loop testing was performed using both the dSPACE (trademark) rapid prototyping system, and a stand-alone Texas Instruments (trademark) Digital Signal Processor (DSP)-based system. The final Nonlinear digital control algorithm was implemented and tested using the ED408043-1 Westinghouse DC-DC switching power converter. The NPID test results are discussed and compared to the results of a standard Proportional-Integral (PI) controller.

  19. Analog Fixed Maximum Power Point Control for a PWM Step-downConverter for Water Pumping Installations

    DEFF Research Database (Denmark)

    Beltran, H.; Perez, E.; Chen, Zhe

    2009-01-01

    This paper describes a Fixed Maximum Power Point analog control used in a step-down Pulse Width Modulated power converter. The DC/DC converter drives a DC motor used in small water pumping installations, without any electric storage device. The power supply is provided by PV panels working around...

  20. Comparison of State-of-the-Art Digital Control and Analogue Control for High Bandwidth Point of Load Converters

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Schneider, Henrik; Andersen, Michael Andreas E.

    2008-01-01

    The purpose of this paper is to present a comparison of state-of-the-art digital and analogue control for a Buck converter with synchronous rectification. The digital control scheme is based on a digital self-oscillating modulator that allows the sampling frequency to be higher than the switching...... frequency of the converter. Voltage mode control is used in both the analogue and digital control schemes. The experimental results show that it is possible to design a digitally controlled Buck converter that has the same performance as can be achieved using commercially available analogue control ICs....... The performance of the analogue system can however be increased by using a separate operational amplifier as error amplifier. Thus analogue control is still the best option if high control bandwidth and fast transient response to load steps are important design parameters....

  1. Improvements to a Major Digital Archive of Seismic Waveforms from Nuclear Explosions

    Science.gov (United States)

    2010-03-23

    T0=3.5 sec), galvanometer phototube amplifier, three-channel KOD-I amplifier system, analog- to-digital converter and a tape recorder (Shishkevish...vertical-component SKM-3 seismograph KPCh: Low-gain seismograph channel obtained by connecting a galvanometer to the seismome- ter damping coil and used

  2. A novel analog/digital reconfigurable automatic gain control with a novel DC offset cancellation circuit*

    Institute of Scientific and Technical Information of China (English)

    He Xiaofeng; Mo Taishan; Ma Chengyan; Ye Tianchun

    2011-01-01

    An analog/digital reconfigurable automatic gain control (AGC) circuit with a novel DC offset cancellation circuit for a direct-conversion receiver is presented. The AGC is analog/digital reconfigurable in order to be compatible with different baseband chips. What's more, a novel DC offset cancellation (DCOC) circuit with an HPCF (high pass cutoff frequency) less than 10 kHz is proposed. The AGC is fabricated by a 0.18 μm CMOS process. Under analog control mode, the AGC achieves a 70 dB dynamic range with a 3 dB-bandwidth larger than 60 MHz. Under digital control mode, through a 5-bit digital control word, the AGC shows a 64 dB gain control range by 2 dB each step with a gain error of less than 0.3 dB. The DC offset cancellation circuits can suppress the output DC offset voltage to be less than 1.5 mV, while the offset voltage of 40 mV is introduced into the input. The overall power consumption is less than 3.5 mA, and the die area is 800 × 300μm2.

  3. Integrated electrofluidic circuits: pressure sensing with analog and digital operation functionalities for microfluidics.

    Science.gov (United States)

    Wu, Chueh-Yu; Lu, Jau-Ching; Liu, Man-Chi; Tung, Yi-Chung

    2012-10-21

    Microfluidic technology plays an essential role in various lab on a chip devices due to its desired advantages. An automated microfluidic system integrated with actuators and sensors can further achieve better controllability. A number of microfluidic actuation schemes have been well developed. In contrast, most of the existing sensing methods still heavily rely on optical observations and external transducers, which have drawbacks including: costly instrumentation, professional operation, tedious interfacing, and difficulties of scaling up and further signal processing. This paper reports the concept of electrofluidic circuits - electrical circuits which are constructed using ionic liquid (IL)-filled fluidic channels. The developed electrofluidic circuits can be fabricated using a well-developed multi-layer soft lithography (MSL) process with polydimethylsiloxane (PDMS) microfluidic channels. Electrofluidic circuits allow seamless integration of pressure sensors with analog and digital operation functions into microfluidic systems and provide electrical readouts for further signal processing. In the experiments, the analog operation device is constructed based on electrofluidic Wheatstone bridge circuits with electrical outputs of the addition and subtraction results of the applied pressures. The digital operation (AND, OR, and XOR) devices are constructed using the electrofluidic pressure controlled switches, and output electrical signals of digital operations of the applied pressures. The experimental results demonstrate the designed functions for analog and digital operations of applied pressures are successfully achieved using the developed electrofluidic circuits, making them promising to develop integrated microfluidic systems with capabilities of precise pressure monitoring and further feedback control for advanced lab on a chip applications.

  4. Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Bruun, Erik; Dietrich, Casper

    1996-01-01

    In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier....../sign detector. Measurements on a CMOS test chip are presented and validates the techniques. Further, we propose to use an analog extension, based on a simple capacitive storage, for enhancing weight resolution during learning. It is shown that the implementation of Hebbian learning and back-propagation learning...

  5. IS THERE ROOM FOR DURABLE ANALOG INFORMATION STORAGE IN A DIGITAL WORLD

    Energy Technology Data Exchange (ETDEWEB)

    R. A. STUTZ; L. HERETH

    2000-09-20

    Information technology has completely changed our concept of record keeping--the advent of digital records was a momentous discovery, as significant as the invention of the printing press. Digital records allowed huge amounts of information to be stored in a very small space and to be examined quickly. However, digital documents are much more vulnerable to the passage of time than printed documents, because the media on which they are stored are easily affected by physical phenomena, such as magnetic fields, oxidation, material decay, and by various environmental factors that may erase the information. Even more important, digital information becomes obsolete, because even if future generations maybe able to read it, they may not necessarily be able to interpret it. Over the centuries analog documents have been written on solid materials such as stone, clay and metal plates using tools to inscribe the characters. These archival methods have preserved records for centuries, and even millennia, but suffer from low information density. Modem methods facilitate writing pages on smooth material surfaces at high information densities. This writing can generate from about 25 to 100,000 times the area information density of microfilm and work with either analog or digital storage methods. Information of all types is becoming more dependent on digital records. These records are often created and stored on computer systems by scanning in documents or creating them directly on the system. Often analog information (human viewable information) is forced into binary form (ones and zeros). The necessity for the accurate and accessible storage of these documents is increasing for a number of reasons, including legal and environment issues. This paper will discuss information storage life, methods of information storage, media life considerations, and life cycle costs associated with several methods of storage.

  6. Advances in analog and RF IC design for wireless communication systems

    CERN Document Server

    Manganaro, Gabriele

    2013-01-01

    Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters

  7. [Trial digitalization of analog-data obtained from the AutoAnalyzer].

    Science.gov (United States)

    Omori, S

    2000-10-01

    The AutoAnalzer(Basic Model) manufactured on Technicon corporation was a very useful instrument for clinical laboratory automation, but it was necessary to convert the data obtained from the instrument to digital values used the chart reader. This was very troublesome and there was apprehension that there would be errors in A-D conversion. We tried converting data obtained from the AutoAnalzer to a digital value by on-line connection of the instruments with minicomputers(LINC-8 and FACOM-R). The output of the recorder was converted to voltage(0 to 100 V) using a potentiometer, quantitated(0 to 1.000) by the A-D converter attached to LINC-8, and processed by the minicomputer. The control-box was an experimental device mainly designed for the convenience of users. The functions of the control-box were designated analytical items, No. of A-D converters, start and stop of the AutoAnalzer operation to the minicomputer. Employing the control-box, a technician operated this system freely, without direct computer operation. We established a generally satisfactory system for clinical laboratory automation using the minicomputer.

  8. A novel trajectory prediction control for proximate time-optimal digital control DC—DC converters

    Science.gov (United States)

    Qing, Wang; Ning, Chen; Shen, Xu; Weifeng, Sun; Longxing, Shi

    2014-09-01

    The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC—DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC—DC with the proposed prediction is about 8 μs when the load current changes from 0.6 to 0.1 A.

  9. XML Docbook to Mediawiki Converter

    Directory of Open Access Journals (Sweden)

    Maria Chiara Pievatolo

    2013-05-01

    Full Text Available A Perl script, based on the work of Stefano Selleri, to migrate XML-Docbook 4.X documents to Wiki markup. I added some lines to meet my need to convert my Kant translations from Docbook to MediaWiki. A sample of the output can be...

  10. Digital and Analog Electronics for an autonomous, deep-sea, Gamma Ray Burst Neutrino prototype detector

    Directory of Open Access Journals (Sweden)

    Manolopoulos K.

    2016-01-01

    Full Text Available GRBNeT is a Gamma Ray Burst Neutrino Telescope made of autonomously operated arrays of deep-sea light detectors, anchored to the sea-bed without any cabled connection to the shore. This paper presents the digital and analog electronics that we have designed and developed for the GRBNeT prototype. We describe the requirements for these electronics and present their design and functionality. We present low-power analog electronics for the PMTs utilized in the GRBNeT prototype and the FPGA based digital system for data selection and storage. We conclude with preliminary performance measurements of the electronics systems for the GRBNeT prototype.

  11. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  12. Fault detection in digital and analog circuits using an i(DD) temporal analysis technique

    Science.gov (United States)

    Beasley, J.; Magallanes, D.; Vridhagiri, A.; Ramamurthy, Hema; Deyong, Mark

    1993-01-01

    An i(sub DD) temporal analysis technique which is used to detect defects (faults) and fabrication variations in both digital and analog IC's by pulsing the power supply rails and analyzing the temporal data obtained from the resulting transient rail currents is presented. A simple bias voltage is required for all the inputs, to excite the defects. Data from hardware tests supporting this technique are presented.

  13. High-dynamic-range hybrid analog-digital control broadband optical spectral processor using micromirror and acousto-optic devices.

    Science.gov (United States)

    Riza, Nabeel A; Reza, Syed Azer

    2008-06-01

    For the first time, to the best of our knowledge, the design and demonstration of a programmable spectral filtering processor is presented that simultaneously engages the power of an analog-mode optical device such as an acousto-optic tunable filter and a digital-mode optical device such as the digital micromirror device. The demonstrated processor allows a high 50 dB attenuation dynamic range across the chosen 1530-1565 nm (~C band). The hybrid analog-digital spectral control mechanism enables the processor to operate with greater versatility when compared to analog- or digital-only processor designs. Such a processor can be useful both as a test instrument in biomedical applications and as an equalizer in fiber communication networks.

  14. Binary/BCD-to-ASCII data converter

    Science.gov (United States)

    Miller, A. J.

    1977-01-01

    Converter inputs multiple precision binary words, converts data to multiple precision binary-coded decimal, and routes data back to computer. Converter base can be readily changed without need for new gate structure for each base changeover.

  15. Modelling and Simulation of Digital Compensation Technique for dc-dc Converter by Pole Placement

    Science.gov (United States)

    Shenbagalakshmi, R.; Sree Renga Raja, T.

    2015-09-01

    A thorough and effective analysis of the dc-dc converters is carried out in order to achieve the system stability and to improve the dynamic performance. A small signal modelling based on state space averaging technique for dc-dc converters is carried out. A digital state feedback gain matrix is derived by pole placement technique in order to achieve the stability of a completely controllable system. A prediction observer for the dc-dc converters is designed and a dynamic compensation (observer plus control law) is provided using separation principle. The output is very much improved with zero output voltage ripples, zero peak overshoot, and much lesser settling time in the range of ms and with higher overall efficiency (>90 %).

  16. Simple Digital Control of a Two-Stage PFC Converter Using DSPIC30F Microprocessor

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2010-01-01

    The use of dsPIC digital signal controllers (DSC) in Switch Mode Power Supply (SMPS) applications opens new perspectives for cheap and flexible digital control solutions. This paper presents the digital control of a two stage power factor corrector (PFC) converter. The PFC circuit is designed and...

  17. Biomass compounds converted to gasoline

    Energy Technology Data Exchange (ETDEWEB)

    1979-10-08

    It is claimed that corn, castor, and jojoba oils as well as Hevea latex can be converted in high yields to gasoline by passage over zeolite catalysts at 450 degrees to 500 degrees centigrade. Gasoline yields are 60% from corn oil (essentially tristearin), compared with 50% yields from methanol. Latex depolymerizes before conversion. Fat and oil molecules adopt conformations that enable them to enter zeolite interstices, resulting in high yields of C6 to C9 aromatics.

  18. Simplified dc to dc converter

    Science.gov (United States)

    Gruber, R. P. (Inventor)

    1984-01-01

    A dc to dc converter which can start with a shorted output and which regulates output voltage and current is described. Voltage controlled switches directed current through the primary of a transformer the secondary of which includes virtual reactance. The switching frequency of the switches is appropriately varied to increase the voltage drop across the virtual reactance in the secondary winding to which there is connected a low impedance load. A starting circuit suitable for voltage switching devices is provided.

  19. Data management and digital delivery of analog data

    Science.gov (United States)

    Miller, W.A.; Longhenry, R.; Smith, T.

    2008-01-01

    The U.S. Geological Survey's (USGS) data archive at the Earth Resources Observation and Science (EROS) Center is a comprehensive and impartial record of the Earth's changing land surface. USGS/EROS has been archiving and preserving land remote sensing data for over 35 years. This remote sensing archive continues to grow as aircraft and satellites acquire more imagery. As a world leader in preserving data, USGS/EROS has a reputation as a technological innovator in solving challenges and ensuring that access to these collections is available. Other agencies also call on the USGS to consider their collections for long-term archive support. To improve access to the USGS film archive, each frame on every roll of film is being digitized by automated high performance digital camera systems. The system robotically captures a digital image from each film frame for the creation of browse and medium resolution image files. Single frame metadata records are also created to improve access that otherwise involves interpreting flight indexes. USGS/EROS is responsible for over 8.6 million frames of aerial photographs and 27.7 million satellite images.

  20. Challenges and implementation aspects of switched-mode power supplies with digital control for automotive applications

    Science.gov (United States)

    Quenzer-Hohmuth, Samuel; Rosahl, Thoralf; Ritzmann, Steffen; Wicht, Bernhard

    2016-09-01

    Switched-mode power supplies (SMPS) convert an input DC-voltage into a higher or lower output voltage. In automotive, analog control is mostly used in order to keep the required output voltages constant and resistant to disturbances. The design of robust analog control for SMPS faces parameter variations of integrated and external passive components. Using digital control, parameter variations can be eliminated and the required area for the integrated circuit can be reduced at the same time. Digital control design bears challenges like the prevention of limit cycle oscillations and controller-wind-up. This paper reviews how to prevent these effects. Digital control loops introduce new sources for dead times in the control loop, for example the latency of the analog-to-digital-converter (ADC). Dead times have negative influence on the stability of the control loop, because they lead to phase delays. Consequently, low latency is one of the key requirements for analog-to-digital-converters in digitally controlled SMPS. Exploiting the example of a 500 kHz-buck converter with a crossover frequency of 70 kHz, this paper shows that the 5 µs-latency of a ΔΣ-analog-to-digital-converter leads to a reduction in phase margin of 126°. The latency is less critical for boost converters because of their inherent lower crossover frequencies. Finally, the paper shows a comparison between analog and digital control of SMPS with regard to chip area and test costs.

  1. Analog and digital transport of RF channels over converged 5G wireless-optical networks

    Science.gov (United States)

    Binh, Le Nguyen

    2016-02-01

    Under the exponential increase demand by the emerging 5G wireless access networking and thus data-center based Internet, novel and economical transport of RF channels to and from wireless access systems. This paper presents the transport technologies of RF channels over the analog and digital domain so as to meet the demands of the transport capacity reaching multi-Tbps, in the followings: (i) The convergence of 5G broadband wireless and optical networks and its demands on capacity delivery and network structures; (ii) Analog optical technologies for delivery of both the information and RF carriers to and from multiple-input multiple-output (MIMO) antenna sites so as to control the beam steering of MIMO antenna in the mmW at either 28.6 GHz and 56.8 GHz RF carrier and delivery of channels of aggregate capacity reaching several Tbps; (ii) Transceiver employing advanced digital modulation formats and digital signal processing (DSP) so as to provide 100G and beyond transmission rate to meet the ultra-high capacity demands with flexible spectral grids, hence pay-on-demand services. The interplay between DSP-based and analog transport techniques is examined; (iii) Transport technologies for 5G cloud access networks and associate modulation and digital processing techniques for capacity efficiency; and (iv) Finally the integrated optic technologies with novel lasers, comb generators and simultaneous dual function photonic devices for both demultiplexing/multiplexing and modulation are proposed, hence a system on chip structure can be structured. Quantum dot lasers and matrixes of micro ring resonators are integrated on the same Si-on-Silica substrate are proposed and described.

  2. Digital Implementation of Two Inductor Boost Converter Fed DC Drive

    Directory of Open Access Journals (Sweden)

    G. Kishor

    2011-01-01

    Full Text Available The study deals w ith simulation and implementation of two inductor boost converter fed DC drive. The two inductor boost converter fed DC drive is simulated and implemented. The circuit has advantages like higher output voltage and improved power factor. The laboratory model is implemented and the experimental results are obtained. The experimental results were compared w ith the simulation results.

  3. Design of Monolithic Integrator for Strain-to-Frequency Converter

    Directory of Open Access Journals (Sweden)

    Tuan Mohd. Khairi Tuan Mat

    2012-01-01

    Full Text Available Strain-to-Frequency converter (SFC is a one of the analog conditioner tools that converts any strain signal to the frequency signal. The basic concept of SFC is by detecting any changing of strains, then converting the strain to the voltage signal and converting the voltage signal to the frequency signal. This tool consists of 3 main  components which are strain gauge, differential integrator and comparator. This paper presents the designing and analysis of monolithic integrator that to be used in the Strain-toFrequency converter. The primary goal is to design and simulate the performance of monolithic integrator for SFC using GATEWAY Silvaco Electronic Design Automation (S EDA tools and EXPERT software. The performances of SFC using the designed monolithic integrator are also investigated.

  4. Systems and methods for self-synchronized digital sampling

    Science.gov (United States)

    Samson, Jr., John R. (Inventor)

    2008-01-01

    Systems and methods for self-synchronized data sampling are provided. In one embodiment, a system for capturing synchronous data samples is provided. The system includes an analog to digital converter adapted to capture signals from one or more sensors and convert the signals into a stream of digital data samples at a sampling frequency determined by a sampling control signal; and a synchronizer coupled to the analog to digital converter and adapted to receive a rotational frequency signal from a rotating machine, wherein the synchronizer is further adapted to generate the sampling control signal, and wherein the sampling control signal is based on the rotational frequency signal.

  5. Bidirectional dc-to-dc Power Converter

    Science.gov (United States)

    Griesbach, C. R.

    1986-01-01

    Solid-state, series-resonant converter uses high-voltage thyristors. Converter used either to convert high-voltage, low-current dc power to lowvoltage, high current power or reverse. Taking advantage of newly-available high-voltage thyristors to provide better reliability and efficiency than traditional converters that use vacuum tubes as power switches. New converter essentially maintenance free and provides greatly increased mean time between failures. Attractive in industrial applications whether or not bidirectional capability is required.

  6. Documentary Realism, Sampling Theory and Peircean Semiotics: electronic audiovisual signs (analog or digital as indexes of reality

    Directory of Open Access Journals (Sweden)

    Hélio Godoy

    2007-07-01

    Full Text Available This paper addresses Documentary Realism, focusing on thephysical phenomena of transduction that take place in analog and digital audiovisual systems, herein analyzed in the light of the Sampling Theory, within the framework of Shannon and Weaver’s Information Theory. Transduction is a process by which one type of energy is transformed into another, or by which information is transcodified. Within the scope of Documentary Realism, it cannotbe claimed that electronic audiovisual signs, because of their technical digital features lead to a rupture with reality. Rather, the digital documentary, based on electronic digital cinematography, is still an index of reality.

  7. A mixed analog/digital chaotic neuro-computer system for quadratic assignment problems.

    Science.gov (United States)

    Horio, Yoshihiko; Ikeguchi, Tohru; Aihara, Kazuyuki

    2005-01-01

    We construct a mixed analog/digital chaotic neuro-computer prototype system for quadratic assignment problems (QAPs). The QAP is one of the difficult NP-hard problems, and includes several real-world applications. Chaotic neural networks have been used to solve combinatorial optimization problems through chaotic search dynamics, which efficiently searches optimal or near optimal solutions. However, preliminary experiments have shown that, although it obtained good feasible solutions, the Hopfield-type chaotic neuro-computer hardware system could not obtain the optimal solution of the QAP. Therefore, in the present study, we improve the system performance by adopting a solution construction method, which constructs a feasible solution using the analog internal state values of the chaotic neurons at each iteration. In order to include the construction method into our hardware, we install a multi-channel analog-to-digital conversion system to observe the internal states of the chaotic neurons. We show experimentally that a great improvement in the system performance over the original Hopfield-type chaotic neuro-computer is obtained. That is, we obtain the optimal solution for the size-10 QAP in less than 1000 iterations. In addition, we propose a guideline for parameter tuning of the chaotic neuro-computer system according to the observation of the internal states of several chaotic neurons in the network.

  8. A NEW APPROACH TO DESIGN LOW POWER CMOS FLASH A/D CONVERTER

    Directory of Open Access Journals (Sweden)

    Sudakar S. Chauhan

    2011-06-01

    Full Text Available In the present paper, a 4-bit flash analog to digital converter for low power SoC application is presented. CMOS inverter has been used as a comparator and by adjusting the ratio of channel width and length, the switching threshold of the CMOS inverter is varied to detect the input analog signal. The simulation results show that this proposed 4-bit flash ADC consumes about 12.4 mW at 200M sample/s with 3.3V supply voltage in TSMC 0.35 μm process. Compared with the traditional flash ADC, this proposed method can reduce about 78% in power consumption.

  9. An Analog Analogue of a Digital Quantum Computation

    CERN Document Server

    Farhi, E; Farhi, Edward; Gutmann, Sam

    1998-01-01

    We solve a problem, which while not fitting into the usual paradigm, can be viewed as a quantum computation. Suppose we are given a quantum system described by an N dimensional Hilbert space with a Hamiltonian of the form $E |w >$ is an unknown (normalized) state. We show how to discover $| w >$ by adding a Hamiltonian (independent of $| w >$) and evolving for a time proportional to $N^{1/2}/E$. We show that this time is optimally short. This process is an analog analogue to Grover's algorithm, a computation on a conventional (!) quantum computer which locates a marked item from an unsorted list of N items in a number of steps proportional to $N^{1/2}$.

  10. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; The ATLAS collaboration; Akerstedt, H; Biot, A; Bohm, C; Carrio, F; Drake, G; Hildebrand, K; Muschter, S; Oreglia, M; Paramonov, A

    2013-01-01

    A potential upgrade for the front-end electronics and signal digitization and data acquisition system of the ATLAS hadron calorimeter for the high luminosity Large Hadron Collider (HL-LHC) is described. A Demonstrator is being built to readout a slice of the TileCal detector. The on-detector electronics includes up to 48 Analog Front-end Boards for PMT analog signal processing, 4 Main Boards for data digitization and slow controls, 4 Daughter Boards with high speed optical links to interface the on-detector and off-detector electronics. Two super readout driver boards are used for off-detector data acquisition and fulfilling digital trigger. The ATLAS Tile Calorimeter on-detector electronics is housed in the drawers at the back of each of the 256 detector wedges. Each drawer services up to 48 photomultiplier tubes. The new readout system is designed to replace the present system as it will reach component lifetime and radiation tolerance limits making it incompatible with continued use into the HL-LHC era. Wi...

  11. Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

    Institute of Scientific and Technical Information of China (English)

    Shuangfeng Han; ChihLin I; Zhikun Xu; Qi Sun; Haibin Li

    2015-01-01

    A large⁃scale antenna system (LSAS) with digital beamforming is expected to significantly increase energy efficiency (EE) and spectral efficiency (SE) in a wireless communication system. However, there are many challenging issues related to calibration, en⁃ergy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digital⁃analog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configu⁃ration in an N × M beamforming structure, where N is the number of transceivers, M is the number of active antennas per trans⁃ceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EE⁃SE curve, and show that the log⁃scale EE scales linearly with SE along a slope of ⁃lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal (N, M) combination for optimizing EE. The results of numerical simulations are provided, and these re⁃sults support our analysis.

  12. A dc to dc converter

    Science.gov (United States)

    Willis, A. E.; Gould, J. M.; Matheney, J. L.; Garrett, H. (Inventor)

    1984-01-01

    The object of the invention is to provide an improved converter for converting one direct current voltage to another. A plurality of phased square wave voltages are provided from a ring counter through amplifiers to a like plurality of output transformers. Each of these transformers has two windings, and S(1) winding and an S(2) winding. The S(1) windings are connected in series, then the S(2) windings are connected in series, and finally, the two sets of windings are connected in series. One of six SCRs is connected between each two series connected windings to a positive output terminal and one of diodes is connected between each set of two windings of a zero output terminal. By virtue of this configuration, a quite high average direct current voltage is obtained, which varies between full voltage and two-thirds full voltage rather than from full voltage to zero. Further, its variation, ripple frequency, is reduced to one-sixth of that present in a single phase system. Application to raising battery voltage for an ion propulsion system is mentioned.

  13. Digital controller design: Analysis of the annular suspension pointing system. [analog controllers with feedback

    Science.gov (United States)

    Kuo, B. C.

    1978-01-01

    The analog controllers of the annular suspension pointing system are designed for control of the chi, phi sub 1, and phi sub 2 bandwidth dynamics through decoupling and pole placement. Since it is virtually impossible to find an equivalent bandwidth of the overall system and establish a general eigenvalue requirement for the system, the subsystem dynamics are decoupled through state feedback and the poles are placed simultaneously to realize the desired bandwidths for the three system components. Decoupling and pole placement are also used to design the closed-loop digital system through approximation.

  14. Digitala spelmekaniker : för att skapa en analog brädspels prototyp

    OpenAIRE

    Rudvi, Emil

    2013-01-01

    Analog games misses a lot of quick games in terms of game time and play time in the FPS genre. This genre often takes more time to play in an analog game. Could the game play become quicker by examining the different game mechanics in order to give the players a smoother game play by a reduction of downtime. Game mechanics that could be found in a digital FPS game such as Doom III, were converted to a prototype. These digital gameplay mechanics were converted so that an analog game could be p...

  15. Digital Implementation of Method for Discontinuous Current Mode Compensation Of High-Performance Line-Commutated Converters

    CERN Document Server

    Maestri, S; Uicich, G; Gomez Costa, J; Petrocelli, R; CERN. Geneva. TE Department

    2010-01-01

    Many high-performance power converters at CERN are implemented with thyristors, mostly in CCM (Continuous Conduction Mode) due to their better dynamic response. In DCM (Discontinuous Conduction Mode), the converter reduces its small-signal gain, producing a degraded time response which can lead to instability. Several of these converters use digital regulation, allowing the implementation of complex non- linear control techniques. Therefore, a strategy to control the converters in DCM (Discontinuous Conduction Mode) can be implemented, bearing in mind that their standard operation (sampling time, measured signals, acquisition system) can not be drastically changed. This report presents the implementation of a new method to control line-commutated converters in discontinuous conduction mode (DCM). The method is based on the modfication of the thyristor's ring angle _ using a linear approximation, yielding nearly the same dynamic performance as in continuous conduction mode. The _ring angle is corrected by addi...

  16. How to deal with substrate bounce in analog circuits in epi-type CMOS technology

    NARCIS (Netherlands)

    Nauta, Bram; Hoogzaad, Gian; Donnay, S.; Gielen, G.

    2003-01-01

    Substrate noise is one of the key problems in mixed analog/digital ICs. Although measures are known to reduce substrate noise, the noise will never be completely eliminated since this requires larger chip area or exotic packages and thus higher cost. Analog circuits on digital ICs simply have to be

  17. Digital versus analog complete-arch impressions for single-unit premolar implant crowns : Operating time and patient preference

    NARCIS (Netherlands)

    Schepke, Ulf; Meijer, Henny J. A.; Kerdijk, Wouter; Cune, Marco S.

    2015-01-01

    Statement of problem. Digital impression-making techniques are supposedly more patient friendly and less time-consuming than analog techniques, but evidence is lacking to substantiate this assumption. Purpose. The purpose of this in vivo within-subject comparison study was to examine patient percept

  18. Realization of Digital Differentiator Using Generalized Integrator for Power Converters

    DEFF Research Database (Denmark)

    Xin, Zhen; Wang, Xiongfei; Loh, Poh Chiang

    2015-01-01

    , yields unacceptable noise amplification even though it produces the phase of an ideal differentiator perfectly. For an even more accurate performance, this letter proposes a new digital differentiator based on Generalized Integrator (GI). It will specifically be shown that differentiation characteristic...

  19. Beyond digital interference cancellation

    NARCIS (Netherlands)

    Venkateswaran, V.

    2010-01-01

    One of the major drawbacks towards the realization of MIMO and multi-sensor wireless communication systems is that multiple antennas at the receiver each have their own separate radio frequency (RF) front ends and analog to digital converter (ADC) units, leading to increased circuit size and power c

  20. Smooth-Transition Simple Digital PWM Modulator for Four-Switch Buck-Boost Converters

    Science.gov (United States)

    Rodriguez, Alberto; Rodriguez, Miguel; Vazquez, Aitor; Maija, Pablo F.; Sebastian, Javier

    2014-08-01

    Four Switch non-inverting Buck-Boost (4SBB) converters are extensively used in non-isolated applications where voltage step-up and step-down are required. In order to achieve high efficiency operation it is preferred to control the 4SBB as a Buck or Boost converter, depending on the input/output voltage ratio. However, when input and output voltages are close this approach requires near- unity conversion ratios, which are difficult to achieve in practice. Several alternative operating modes have been proposed in the literature to overcome this issue. In particular, operating the 4SBB as a Buck and Boost at the same time (Buck+Boost mode) has proven to be adequate to achieve near-unity conversion ratios.This paper proposes a simple, hardware-efficient digital pulse width modulator for a 4SBB that enables operation in Buck, Boost and Buck+Boost modes, thus allowing near-unity conversion ratios, while achieving smooth transitions between the different modes. The proposed modulator is simulated with Simulink and experimentally demonstrated using a 500W 4SBB converter with 24V input voltage and 12V-36V output voltage range.

  1. Thermal heat-balance mode flow-to-frequency converter

    Science.gov (United States)

    Pawlowski, Eligiusz

    2016-11-01

    This paper presents new type of thermal flow converter with the pulse frequency output. The integrating properties of the temperature sensor have been used, which allowed for realization of pulse frequency modulator with thermal feedback loop, stabilizing temperature of sensor placed in the flowing medium. The system assures balancing of heat amount supplied in impulses to the sensor and heat given up by the sensor in a continuous way to the flowing medium. Therefore the frequency of output impulses is proportional to the heat transfer coefficient from sensor to environment. According to the King's law, the frequency of those impulses is a function of medium flow velocity around the sensor. The special feature of presented solution is total integration of thermal sensor with the measurement signal conditioning system. Sensor and conditioning system are not the separate elements of the measurement circuit, but constitute a whole in form of thermal heat-balance mode flow-to-frequency converter. The advantage of such system is easiness of converting the frequency signal to the digital form, without using any additional analogue-to-digital converters. The frequency signal from the converter may be directly connected to the microprocessor input, which with use of standard built-in counters may convert the frequency into numerical value of high precision. Moreover, the frequency signal has higher resistance to interference than the voltage signal and may be transmitted to remote locations without the information loss.

  2. An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor

    Directory of Open Access Journals (Sweden)

    Yi-Xin Guo

    2015-12-01

    Full Text Available Inductive proximity sensors (IPSs are widely used in position detection given their unique advantages. To address the problem of temperature drift, this paper presents an analog-digital mixed measurement method based on the two-dimensional look-up table. The inductance and resistance components can be separated by processing the measurement data, thus reducing temperature drift and generating quantitative outputs. This study establishes and implements a two-dimensional look-up table that reduces the online computational complexity through structural modeling and by conducting an IPS operating principle analysis. This table is effectively compressed by considering the distribution characteristics of the sample data, thus simplifying the processing circuit. Moreover, power consumption is reduced. A real-time, built-in self-test (BIST function is also designed and achieved by analyzing abnormal sample data. Experiment results show that the proposed method obtains the advantages of both analog and digital measurements, which are stable, reliable, and taken in real time, without the use of floating-point arithmetic and process-control-based components. The quantitative output of displacement measurement accelerates and stabilizes the system control and detection process. The method is particularly suitable for meeting the high-performance requirements of the aviation and aerospace fields.

  3. Analog and Digital Circuit Design in 65 nm CMOS: End of the Road?

    CERN Document Server

    Gielen, Georges; Christie, Phillip; Draxelmayr, Dieter; Janssens, Edmond; Maex, Karen; Vucurevich, Ted

    2011-01-01

    This special session adresses the problems that designers face when implementing analog and digital circuits in nanometer technologies. An introductory embedded tutorial will give an overview of the design problems at hand : the leakage power and process variability and their implications for digital circuits and memories, and the reducing supply voltages, the design productivity and signal integrity problems for embedded analog blocks. Next, a panel of experts from both industrial semiconductor houses and design companies, EDA vendors and research institutes will present and discuss with the audience their opinions on whether the design road ends at marker "65nm" or not.

  4. Digital coherent receiver employing photonic downconversion for phase modulated radio-over-fibre links

    DEFF Research Database (Denmark)

    Zibar, Darko; Caballero Jambrina, Antonio; Guerrero Gonzalez, Neil

    2009-01-01

    A digital coherent receiver employing photonic downconversion is presented and experimentally demonstrated for phase-modulated radio-over-fibre optical links. The receiver is capable of operating at frequencies exceeding the bandwidth of electrical analog-to-digital converter by using photonic...... downconversion to translate the high-frequency input RF signal to the operating frequency range of the analog-to-digital converter. First, using linear digital demodulation scheme we measure SFDR of the link at microwave frequency of 5 GHz. Thereafter, successful signal demodulation of 50 Mbit/s binary phase...... shift keying (BPSK) modulated data signal at 5 GHz RF carrier frequency is experimentally demonstrated by using an analog-to-digital converter with only 1 GHz bandwidth. We successfully demonstrate signal demodulation, using the proposed digital coherent receiver with photonic downconversion, after 40...

  5. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...... Code Division Multiple Access). The ADC is realized with a pipeline ADC architecture for WCDMA and a Sigma-Delta architecture for GSM. In order to have an optimized area and power consumption, the basic building blocks (opamps) of the converters are shared between the two converter architectures...

  6. 23rd workshop on Advances in Analog Circuit Design

    CERN Document Server

    Baschirotto, Andrea; Makinwa, Kofi

    2015-01-01

    This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

  7. Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

    CERN Document Server

    Tang, F; Anderson, K; Bohm, C; Hildebrand, K; Muschter, S; Oreglia, M

    2015-01-01

    The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and de...

  8. Digital Solution to Mining Image Monitor System

    Institute of Scientific and Technical Information of China (English)

    刘越男; 孙继平; 苏辉; 那景芳

    2001-01-01

    The thesis describes an advanced digital solution to mining digital image monitor system, which makes up the shortage of the traditional mining analog image monitor. It illustrates the system components and how to choose the encoder bandwidth of the system. The problem of image multicast and its solution in LAN are also discussed.

  9. A Design Methodology for Power-efficient Continuous-time Sigma-Delta A/D Converters

    DEFF Research Database (Denmark)

    Nielsen, Jannik Hammel; Bruun, Erik

    2003-01-01

    In this paper we present a design methodology for optimizing the power consumption of continuous-time (CT) ΣΔ A/D converters. A method for performance prediction for ΣΔ A/D converters is presented. Estimation of analog and digital power consumption is derived and employed to predict the most power...

  10. Optical Injection Locking of Vertical Cavity Surface-Emitting Lasers: Digital and Analog Applications

    Science.gov (United States)

    Parekh, Devang

    With the rise of mobile (cellphones, tablets, notebooks, etc.) and broadband wireline communications (Fiber to the Home), there are increasing demands being placed on transmitters for moving data from device to device and around the world. Digital and analog fiber-optic communications have been the key technology to meet this challenge, ushering in ubiquitous Internet and cable TV over the past 20 years. At the physical layer, high-volume low-cost manufacturing of semiconductor optoelectronic devices has played an integral role in allowing for deployment of high-speed communication links. In particular, vertical cavity surface emitting lasers (VCSEL) have revolutionized short reach communications and are poised to enter more markets due to their low cost, small size, and performance. However, VCSELs have disadvantages such as limited modulation performance and large frequency chirp which limits fiber transmission speed and distance, key parameters for many fiber-optic communication systems. Optical injection locking is one method to overcome these limitations without re-engineering the VCSEL at the device level. By locking the frequency and phase of the VCSEL by the direct injection of light from another laser oscillator, improved device performance is achieved in a post-fabrication method. In this dissertation, optical injection locking of VCSELs is investigated from an applications perspective. Optical injection locking of VCSELs can be used as a pathway to reduce complexity, cost, and size of both digital and analog fiber-optic communications. On the digital front, reduction of frequency chirp via bit pattern inversion for large-signal modulation is experimentally demonstrated showing up to 10 times reduction in frequency chirp and over 90 times increase in fiber transmission distance. Based on these results, a new reflection-based interferometric model for optical injection locking was established to explain this phenomenon. On the analog side, the resonance

  11. Grid converter for LED based intelligent light sources

    DEFF Research Database (Denmark)

    Török, Lajos

    1010 microcontroller. Peak current control was implemented for the forward converter, using analog comparator module of the digital-signal controller. The waveforms, eciency and power factor results were compared to the performance of an identical two stage 70 W power supply controlled with an analog...... of the PI controller. All four control loops were implemented in a 16 bitfixed point dsPIC33FJ32GS406 microcontroller driving at the same time 8 PWM channels. Finally a brief analysis was done on the eect of the grid disturbances, especially voltage sags on the digital controller. Dierent grid codes...... control is not so clear but with falling prices of microcontrollers and increasing demands on the performance of power converters introducing digital control seems to be a reasonable option for the future development of power converters. Advanced control structures can be implemented to improve...

  12. Namibian Analogs To Titan Dunes

    Science.gov (United States)

    Wall, Stephen D.; Lopes, R.; Kirk, R.; Stofan, E.; Farr, T.; Van der Ploeg, P.; Lorenz, R.; Radebaugh, J.

    2009-09-01

    Titan's equatorial dunes, observed in Cassini SAR, have been described as longitudinal, similar to longitudinal dunes in the Namib sand sea in southern Africa. Their "Y” junctions and the way they divert around topography are used as evidence of equatorial wind flow direction. In two instances of such diversion they exhibit overlying or crosshatched patterns in two distinct directions that have been interpreted as a transition to transverse dunes. Here we describe field observations of the Namibian dunes and these comparisons, we present images of the dunes from terrestrial SAR missions, and we discuss implications to both the Titan dunes and the wind regime that created them. Selected portions of the Namibian dunes resemble Titan's dunes in peak-to-peak distance and length. They are morphologically similar to Titan, and specific superficial analogs are common, but they also differ. For example, when Titan dunes encounter topography they either terminate abruptly, "climb” the upslope, or divert around; only the latter behavior is seen in remote sensing images of Namibia. Namib linear dunes do transition to transverse as they divert, but at considerably smaller wavelength, while at Titan the wavelengths are of the same scale. Crosshatching of similar-wavelength dunes does occur in Namibia, but not near obstacles. Many additional aeolian features that are seen at Namibia such as star dunes, serpentine ridges and scours have not been detected on Titan, although they might be below the Cassini SAR's 300-m resolution. These similarities and differences allow us to explore mechanisms of Titan dune formation, in some cases giving us clues as to what larger scale evidence to look for in SAR images. Viewed at similar resolution, they provide interesting comparisons with the Titan dunes, both in likeness and differences. A part of this work was carried out at JPL under contract with NASA.

  13. Image Resolution in the Digital Era: Notion and Clinical Implications

    Directory of Open Access Journals (Sweden)

    Vahid Rakhshan

    2014-12-01

    Full Text Available Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs.

  14. Image Resolution in the Digital Era: Notion and Clinical Implications

    Science.gov (United States)

    Rakhshan, Vahid

    2014-01-01

    Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs. PMID:25469352

  15. Image Resolution in the Digital Era: Notion and Clinical Implications

    Directory of Open Access Journals (Sweden)

    Vahid Rakhshan

    2014-05-01

    Full Text Available Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs.

  16. Opportunistic beam training with hybrid analog/digital codebooks for mmWave systems

    KAUST Repository

    Eltayeb, Mohammed E.

    2016-02-25

    © 2015 IEEE. Millimeter wave (mmWave) communication is one solution to provide more spectrum than available at lower carrier frequencies. To provide sufficient link budget, mmWave systems will use beamforming with large antenna arrays at both the transmitter and receiver. Training these large arrays using conventional approaches taken at lower carrier frequencies, however, results in high overhead. In this paper, we propose a beam training algorithm that efficiently designs the beamforming vectors with low training overhead. Exploiting mmWave channel reciprocity, the proposed algorithm relaxes the need for an explicit feedback channel, and opportunistically terminates the training process when a desired quality of service is achieved. To construct the training beamforming vectors, a new multi-resolution codebook is developed for hybrid analog/digital architectures. Simulation results show that the proposed algorithm achieves a comparable rate to that obtained by exhaustive search solutions while requiring lower training overhead when compared to prior work.

  17. Preliminary design and implementation of the baseline digital baseband architecture for advanced deep space transponders

    Science.gov (United States)

    Nguyen, T. M.; Yeh, H.-G.

    1993-01-01

    The baseline design and implementation of the digital baseband architecture for advanced deep space transponders is investigated and identified. Trade studies on the selection of the number of bits for the analog-to-digital converter (ADC) and optimum sampling schemes are presented. In addition, the proposed optimum sampling scheme is analyzed in detail. Descriptions of possible implementations for the digital baseband (or digital front end) and digital phase-locked loop (DPLL) for carrier tracking are also described.

  18. A 16 channel high resolution (Digital Converter in a Field Programmable Gate Array

    Science.gov (United States)

    Ugur, C.; Bayer, E.; Kurz, N.; Traxler, M.

    2012-02-01

    A 16-channel Time-to-Digital Converter (TDC) was implemented in a general purpose Field-Programmable Gate Array (FPGA). The fine time calculations are achieved by using the dedicated carry-chain lines. The coarse counter defines the coarse time stamp. In order to overcome the negative effects of temperature and power supply dependency bin-by-bin calibration is applied. The time interval measurements are done using 2 channels. The time resolution of channels are calculated for 1 clock cycle and a minimum of 10.3 ps RMS on two channels, yielding 7.3 ps RMS (10.3 ps/√2) on a single channel is achieved.

  19. A physical analogy to fuzzy clustering

    DEFF Research Database (Denmark)

    Jantzen, Jan

    2004-01-01

    This tutorial paper provides an interpretation of the membership assignment in the fuzzy clustering algorithm fuzzy c-means. The membership of a data point to several clusters is shown to be analogous to the gravitational forces between bodies of mass. This provides an alternative way to explain...... the algorithm to students. The analogy suggests a possible extension of the fuzzy membership assignment equation....

  20. The SIRIUS Mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

    CERN Document Server

    Cros, A; Moutaye, E; Ravera, L; Barret, D; Caïs, P; Clédassou, R; Bodin, P; Seyler, JY; Bonzo, A; Feroci, M; Labanti, C; Evangelista, Y; Favre, Y

    2014-01-01

    We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 {\\mu}W per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

  1. The quantum vector digital voltmeter of INMETRO

    Science.gov (United States)

    Kuerten Ihlenfeld, Waldemar G.; Landim, Regis P.

    2016-07-01

    The paper describes the quantum vector digital voltmeter developed at INMETRO, which is based on a programmable Josephson voltage synthesizer. The system employs digital regulation for phase-alignment and frequency synchronization of signals, is fully automated and allows calibration of ac sources and analog-to-digital converters with uncertainties bearing some parts of 10-07 up to frequencies of around 500 Hz.

  2. 一种基于FPGA的直接数字射频上变频方案%A method for digital direct RF up-converter with FPGA

    Institute of Scientific and Technical Information of China (English)

    梁尧; 徐迪宇; 胥小武

    2014-01-01

    Common method for up-converter implementation with analog device is of high complexity, poor inflexibility and large power consumption. With the development of semiconductor devices, software radio requires the Radio Frequency(RF) or Intermediate Frequency(IF) signals processing next to base band as close as possible. Therefore, a method for digital direct RF up-converter with poly-phase filters based on Field Programmable Gate Array(FPGA) is proposed. Its feasibility is verified through software and hardware simulations.%传统模拟器件实现射频(RF)上变频方法存在硬件复杂度高,灵活性差,功耗大等缺点。随着半导体器件的发展,软件无线电要求将上变频中射频或中频的信号处理尽量往基带数字信号处理靠拢。本文利用多相滤波器原理,提出一种基于现场可编程门阵列(FPGA)的直接数字 RF上变频架构和实施方案,并且通过软硬件仿真验证了该方案的可行性。

  3. The LIGO Suspended Optic Digital Control System

    CERN Document Server

    Heefner, J W

    2001-01-01

    The original LIGO suspension control system [1] used analog circuitry to implement the closed loop damping required for local control of each the suspended optics. Recent developments in analog to digital converters (ADC), digital to analog converters (DAC), increased processor speed and performance, and the use of reflective memory have made a digital alternative possible. Such a control system would provide additional performance and flexibility that will be required for operation of the interferometers. This paper will describe the real-time digital servo control systems that have been designed, developed and implemented for the LIGO suspended optics. In addition, the paper will describe how the suspension controls have been integrated into the overall LIGO control and data acquisition systems [2].

  4. Digitally Controlled Converter with Dynamic Change of Control Law and Power Throughput

    DEFF Research Database (Denmark)

    Nesgaard, Carsten; Andersen, Michael Andreas E.; Nielsen, Nils

    2003-01-01

    the substitution of analog controllers with their digital counterparts are considered. The outline of the paper is divided into two segments – the first being an experimental analysis of the timing behavior by means of code optimization – the second being an examination of the dynamics of incorporating two control......With the continuous development of faster and cheaper microprocessors the field of applications for digital control is constantly expanding. Based on this trend the paper at hand describes the analysis and implementation of multiple control laws within the same controller. Also, implemented within...

  5. Novel Design for High Speed and Resolution Delta-sigma A/D Converter

    Institute of Scientific and Technical Information of China (English)

    TANG Sheng-xue; HE Yi-gang; GUO Jie-rong; LI Hong-min

    2007-01-01

    The delta-sigma converter is one of the high speed and resolution analog-to-digital modulators. Its implementation needs the low oversampling technique and the multi-bit D/A converter. The noise induced by the multi-bit D/A converter becomes one of the key factors deteriorating the signal-to-noise rate of the delta-sigma A/D converter. A novel structure with signal unity transfunction, dynamic element matching(DEM) and noise-shaping is discussed. The method is investigated to design converter based on the proposed structure. The behavior simulation indicates that the structure and the design method are feasible.

  6. Computational approaches to analogical reasoning current trends

    CERN Document Server

    Richard, Gilles

    2014-01-01

    Analogical reasoning is known as a powerful mode for drawing plausible conclusions and solving problems. It has been the topic of a huge number of works by philosophers, anthropologists, linguists, psychologists, and computer scientists. As such, it has been early studied in artificial intelligence, with a particular renewal of interest in the last decade. The present volume provides a structured view of current research trends on computational approaches to analogical reasoning. It starts with an overview of the field, with an extensive bibliography. The 14 collected contributions cover a large scope of issues. First, the use of analogical proportions and analogies is explained and discussed in various natural language processing problems, as well as in automated deduction. Then, different formal frameworks for handling analogies are presented, dealing with case-based reasoning, heuristic-driven theory projection, commonsense reasoning about incomplete rule bases, logical proportions induced by similarity an...

  7. Simple digital PWM and PSM controlled DC-DC boost converter for luminance-regulated WLED driver

    Institute of Scientific and Technical Information of China (English)

    LIU Xin; GUO Shu-xu; CHANG Yu-chun; ZHU Shun-dong; WANG Shuai

    2009-01-01

    This article presents a control strategy based on simple digital pulse-width modulation (DPWM) and pulse-skip modulation (PSM) for a DC-DC boost converter, to drive a luminance-regulated white light emitting diodes (WLEDs). The presented control strategy not only retains most of the advantages and flexibilities of traditional digital PWM, but also reduces complexity and cost. Based on analyzing the principle of the presented control strategy, the white light emitting diode (WLED) driver is designed and simulated using the 0.6 (m CMOS process. Simulation results of the boost converter show that the power efficiency is above 76% for a full load, with a peak efficiency of 88% when supply voltage varies from 2.7 V to 5.5 V. The control strategy overcomes low efficiency for PWM mode with light load.

  8. Analisis Migrasi Radio Trunking Analog ke Radio Trunking Digital di Indonesia

    Directory of Open Access Journals (Sweden)

    Riza Azmi

    2013-09-01

    Full Text Available Dalam Tabel Alokasi Spektrum Frekuensi di Indonesia pada catatan kaki INS9 dan INS13 disebutkan bahwa alokasi pada pita-pita frekuensi yang digunakan untuk teknologi trunking direncanakan dimigrasi ke sistem komunikasi trunking digital pada waktu yang akan ditentukan oleh pemerintah. Terkait dengan hal itu, studi ini bertujuan untuk mengkaji bagaimana kelayakan migrasi dari sistem trunking analog ke sistem trunking digital dan hal-hal yang terkait dengannya. Dengan menggunakan analisis biaya dan manfaat (Cost-Benefit Analysis studi ini melihat bahwa migrasi hanya dapat dilakukan jika umur masing-masing lisensi dari operator telah berakhir, atau dengan kata lain pemerintah dapat mendorong transisi ke digital dengan menerbitkan lisensi baru yaitu lisensi trunking digital.

  9. Pixel-Level Digital-to-Analog Conversion Scheme for Compact Data Drivers of Active Matrix Organic Light-Emitting Diodes with Low-Temperature Polycrystalline Silicon Thin-Film Transistors

    Science.gov (United States)

    Tae-Wook Kim,; Byong-Deok Choi,

    2010-03-01

    This paper shows that a part of a digital-to-analog conversion (DAC) function can be included in a pixel circuit to save the circuit area of an integrated data driver fabricated with low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs). Because the pixel-level DAC can be constructed by two TFTs and one small capacitor, the pixel circuit does not become markedly complex. The design of an 8-bit DAC, which combines a 6-bit resistor-string-based DAC and a 2-bit pixel-level DAC for a 4-in. diagonal VGA format active matrix organic light-emitting diode (AMOLED), is shown in detail. In addition, analysis results are presented, revealing that the 8-bit DAC scheme including a 2-bit pixel-level DAC with 1:3 demultiplexing can be applied to very high video formats, such as XGA, for a 3 to 4-in. diagonal AMOLED. Even for a 9- to 12-in. diagonal AMOLED, the proposed scheme can still be applied to the XGA format, even though no demultiplexing is allowed. The total height of the proposed 8-bit DAC is approximately 960 μm, which is almost one-half of that of the previous 6-bit resistor-string-based DAC.

  10. Transfer Between Analogies: How Solving One Analogy Problem Helps to Solve Another

    OpenAIRE

    Keane, Mark T.

    1995-01-01

    This paper deals with transfer between analogies; with what people acquire from one analogy problem-solving episode that can be re-applied to a subsequent analogy, problem-solving episode. This issue must be resolved if we are to understand the nature of expertise and the appropriate use of analogy in education. There are two main explanations of what subjects acquire from an analogy problem-solving episode. The schema-induction hypothesis maintains that subjects acquire an abs...

  11. An 8-bit Data Driving Scheme Based on Two-Step Digital-to-Analog Conversion for Integrated Data Drivers of Active-Matrix Organic Light-Emitting Diodes

    Science.gov (United States)

    Kim, Tae-Wook; Choi, Byong-Deok

    2012-03-01

    The two-step digital-to-analog conversion (DAC) scheme has been reported to be very area-efficient for thin-film transistor-liquid crystal display (TFT-LCD) data driver ICs, but it is not as well suited as it is for polycrystalline silicon (poly-Si) TFT integrated circuits. The charge redistribution in the two-step DAC process requires an operational amplifier in principle, which is most challenging for poly-Si TFT circuits. The proposed two-step DAC for active-matrix organic light-emitting diodes (AMOLEDs) makes the operational amplifier unnecessary by appropriately exploiting the preexisting capacitors in the pixel to compensate for the characteristic variations of TFTs. Moreover, the second-step DAC occurs at the same time as threshold voltage compensation, and it does not require additional time. By thoroughly analyzing area efficiency depending on the resolution decomposition between the first- and second-step DACs, we found that 5-bit coarse plus 3-bit fine DACs are best in terms of circuit area. When we designed a layout of the proposed 8-bit DAC on the basis of the 4 µm design rules, the DAC circuit area is no more than 72×637 µm2, which, to the best of our knowledge, is the most compact to date.

  12. 10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Markovic, B.; Tamborini, D.; Villa, F.; Tisa, S.; Tosi, A.; Zappa, F. [Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci 32, 20133 Milano (Italy)

    2012-07-15

    We present a compact high performance time-to-digital converter (TDC) module that provides 10 ps timing resolution, 160 ns dynamic range and a differential non-linearity better than 1.5% LSB{sub rms}. The TDC can be operated either as a general-purpose time-interval measurement device, when receiving external START and STOP pulses, or in photon-timing mode, when employing the on-chip SPAD (single photon avalanche diode) detector for detecting photons and time-tagging them. The instrument precision is 15 ps{sub rms} (i.e., 36 ps{sub FWHM}) and in photon timing mode it is still better than 70 ps{sub FWHM}. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via an user-friendly software interface. The module proves to be the best candidate for a wide variety of applications such as: fluorescence lifetime imaging, time-of-flight ranging measurements, time-resolved positron emission tomography, single-molecule spectroscopy, fluorescence correlation spectroscopy, diffuse optical tomography, optical time-domain reflectometry, quantum optics, etc.

  13. Pixel-Level Digital-to-Analog Conversion Scheme with Compensation of Thin-Film-Transistor Variations for Compact Integrated Data Drivers of Active Matrix Organic Light Emitting Diodes

    Science.gov (United States)

    Kim, Tae-Wook; Park, Sang-Gyu; Choi, Byong-Deok

    2011-03-01

    The previous pixel-level digital-to-analog-conversion (DAC) scheme that implements a part of a DAC in a pixel circuit turned out to be very efficient for reducing the peripheral area of an integrated data driver fabricated with low-temperature polycrystalline silicon thin-film transistors (LTPS TFTs). However, how the pixel-level DAC can be compatible with the existing pixel circuits including compensation schemes of TFT variations and IR drops on supply rails, which is of primary importance for active matrix organic light emitting diodes (AMOLEDs) is an issue in this scheme, because LTPS TFTs suffer from random variations in their characteristics. In this paper, we show that the pixel-level DAC scheme can be successfully used with the previous compensation schemes by giving two examples of voltage- and current-programming pixels. The previous pixel-level DAC schemes require additional two TFTs and one capacitor, but for these newly proposed pixel circuits, the overhead is no more than two TFTs by utilizing the already existing capacitor. In addition, through a detailed analysis, it has been shown that the pixel-level DAC can be expanded to a 4-bit resolution, or be applied together with 1:2 demultiplexing driving for 6- to 8-in. diagonal XGA AMOLED display panels.

  14. "Forback" Dc-To-Dc Converters

    Science.gov (United States)

    Lukemire, Alan T.

    1992-01-01

    Dc-to-dc power-converter circuits called "forback" resemble circuits of standard configurations called "forward", "flyback", and "Cuk". Circuit employs minor modifications to existing topologies, combines advantages, while eliminating disadvantages, of older circuits.

  15. 一种模/数混合型FIR噪声滤波器设计%Design of Analog and Digital Mixed FIR Noise Filter

    Institute of Scientific and Technical Information of China (English)

    易鸿

    2011-01-01

    In combination with the method of analog circuit, a hybrid FIR noise filtering technology is proposed to solve the problem of noise amplification existing in the existing digital FIR noise filtering technology. This method converts the dig-ital control phase error in phase-locked loop to simulation domain charge by the aid of a charge pump. One or several clock cy-cle delay of the modulator output is realized through a registers chain. Some taps are choosen to control the corresponding fre-quency dividers or phase selectors respectively to quantify the generated instantaneous phase error through phase discrimina-tors in every branch and synthetize the analog domain error charge in a multi-input charge pump. The noise amplification prob-lem of the existing digital FIR filtering technology is solved by providing a constant DC gain. The novel filter has the following characteristics: the work of time domain can be dispersed; the analog mismatch isn't sensitive) it is helpful for linearity im-provement, so the cost of additional hardware is lower.%针对现有数字FIR噪声滤除技术的噪声放大问题,结合模拟电路的方法,提出一种新的混合型FIR噪声滤波技术.该方法采用电荷泵将锁相环中数字控制的相位误差转换为模拟域电荷,调制器的输出经过一个寄存器链实现一个或数个时钟周期的延时,从中选出若干抽头分别去控制对应的分频器或相位选择器,从而量化所产生的经过各支路鉴相器的瞬时相位误差,在一个多输入电荷泵中合成为模拟域误差电荷,通过提供恒定单位直流增益,解决现有数字FIR噪声滤除技术的噪声放大问题.这种新型的滤波器具有如下特点:离散时间域工作,模拟失配不敏感,有助于提高线性度,额外硬件开销小.

  16. Quantum secure direct communication of digital and analog signals using continuum coherent states

    Science.gov (United States)

    Guerra, Antônio Geovan de Araújo Holanda; Rios, Francisco Franklin Sousa; Ramos, Rubens Viana

    2016-11-01

    In this work, we present optical schemes for secure direct quantum communication of digital and analog signals using continuum coherent states and frequency-dependent phase modulation. The main advantages of the proposed schemes are that they do not use entangled states and they can be implemented with today technology. The theory of quantum interference of continuum coherent state is described, and the optical setups for secure direct communication are presented and their securities are discussed.

  17. Quantum secure direct communication of digital and analog signals using continuum coherent states

    Science.gov (United States)

    Guerra, Antônio Geovan de Araújo Holanda; Rios, Francisco Franklin Sousa; Ramos, Rubens Viana

    2016-08-01

    In this work, we present optical schemes for secure direct quantum communication of digital and analog signals using continuum coherent states and frequency-dependent phase modulation. The main advantages of the proposed schemes are that they do not use entangled states and they can be implemented with today technology. The theory of quantum interference of continuum coherent state is described, and the optical setups for secure direct communication are presented and their securities are discussed.

  18. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  19. Greenland Snow Pit and Core Stratigraphy (Analog and Digital Formats)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This data set is comprised of scientific field study notebooks from geologist Carl S. Benson describing his traverses of Greenland from 1952 to 1955. The notebooks...

  20. An Implantable Mixed Analog/Digital Neural Stimulator Circuit

    DEFF Research Database (Denmark)

    Gudnason, Gunnar; Bruun, Erik; Haugland, Morten

    1999-01-01

    This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation. The chip performs all the signal processing required in an implanted neural stimulator. The power and signal transmission to the stimulator is carried out via an inductive link. From the signals...

  1. Hardware Index to Permutation Converter

    Science.gov (United States)

    2012-05-01

    latency to be n−1. Note that, after the first codeword emerges, a codeword emerges at each clock period. C. Results A Verilog program was written to...by the Verilog code executes significantly faster on the SRC-6 than the C code on the microprocessor. For example, for 10-element permutations, the... Verilog code, each permutation was represented by a single word. Here, each word has nlog2(n) bits, which is 36 for n = 9, for example. Although a

  2. Neural recording front-end IC using action potential detection and analog buffer with digital delay for data compression.

    Science.gov (United States)

    Liu, Lei; Yao, Lei; Zou, Xiaodan; Goh, Wang Ling; Je, Minkyu

    2013-01-01

    This paper presents a neural recording analog front-end IC intended for simultaneous neural recording with action potential (AP) detection for data compression in wireless multichannel neural implants. The proposed neural recording front-end IC detects the neural spikes and sends only the preserved AP information for wireless transmission in order to reduce the overall power consumption of the neural implant. The IC consists of a low-noise neural amplifier, an AP detection circuit and an analog buffer with digital delay. The neural amplifier makes use of a current-reuse technique to maximize the transconductance efficiency for attaining a good noise efficiency factor. The AP detection circuit uses an adaptive threshold voltage to generate an enable signal for the subsequent functional blocks. The analog buffer with digital delay is employed using a finite impulse response (FIR) filter which preserves the AP waveform before the enable signal as well as provides low-pass filtering. The neural recording front-end IC has been designed using standard CMOS 0.18-µm technology occupying a core area of 220 µm by 820 µm.

  3. Digitally-assisted analog and RF CMOS circuit design for software-defined radio

    CERN Document Server

    Okada, Kenichi

    2011-01-01

    This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

  4. eeDAP: an evaluation environment for digital and analog pathology

    Science.gov (United States)

    Gallas, Brandon D.; Cheng, Wei-Chung; Gavrielides, Marios A.; Ivansky, Adam; Keay, Tyler; Wunderlich, Adam; Hipp, Jason; Hewitt, Stephen M.

    2014-03-01

    Purpose: The purpose of this work is to present a platform for designing and executing studies that compare pathologists interpreting histopathology of whole slide images (WSI) on a computer display to pathologists interpreting glass slides on an optical microscope. Methods: Here we present eeDAP, an evaluation environment for digital and analog pathology. The key element in eeDAP is the registration of theWSI to the glass slide. Registration is accomplished through computer control of the microscope stage and a camera mounted on the microscope that acquires images of the real time microscope view. Registration allows for the evaluation of the same regions of interest (ROIs) in both domains. This can reduce or eliminate disagreements that arise from pathologists interpreting different areas and focuses the comparison on image quality. Results: We reduced the pathologist interpretation area from an entire glass slide (≈10-30 mm)2 to small ROIs google.com (project: eeDAP) as Matlab source or as a precompiled stand-alone license-free application.

  5. Maintainability of Digital Systems: Technical Basis and Human Factors Review Guidance

    Science.gov (United States)

    2000-03-01

    installed, it may be necessary to install additional signal converters to translate the analog signals into digital format and then translate the digital...affecting troubleshooting (Teague and Allen, 1997). One conclusion drawn from this research is that humans are not optimal troubleshooters ( Henneman

  6. A linear temperature-to-frequency converter

    DEFF Research Database (Denmark)

    Løvborg, Leif

    1965-01-01

    The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized, and that th......The possibility of converting temperature into a frequency signal by means of a thermistor which is part of the frequency-determining network of an RC oscillator is investigated. It is shown that a temperature - frequency characteristic which has a point of inflection may be realized......, and that the maximum value of the temperature-frequency coefficient beta in this point is-1/3 alpha, where a is the temperature coefficient of the thermistor at the corresponding temperature. Curves showing the range in which the converter is expected to be linear to within plusmn0.1 degC are given. A laboratory...

  7. Advances in Analog Circuit Design 2015

    CERN Document Server

    Baschirotto, Andrea; Harpe, Pieter

    2016-01-01

    This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

  8. Analog and hybrid computing

    CERN Document Server

    Hyndman, D E

    2013-01-01

    Analog and Hybrid Computing focuses on the operations of analog and hybrid computers. The book first outlines the history of computing devices that influenced the creation of analog and digital computers. The types of problems to be solved on computers, computing systems, and digital computers are discussed. The text looks at the theory and operation of electronic analog computers, including linear and non-linear computing units and use of analog computers as operational amplifiers. The monograph examines the preparation of problems to be deciphered on computers. Flow diagrams, methods of ampl

  9. A Wideband 2x13-bit All-Digital I/Q RF-DAC

    NARCIS (Netherlands)

    Alavi, S.M.; Staszewski, R.B.; De Vreede, L.C.N.; Long, J.R.

    2014-01-01

    This paper presents a wideband 2 13-bit in-phase/quadrature-phase (I/Q) RF digital-to-analog converter-based all-digital modulator realized in 65-nm CMOS. The isolation between I and Q paths is guaranteed employing 25% duty-cycle differential quadrature clocks. With a 1.3-V supply and an on-chip pow

  10. A Digitally Calibrated 12 bits 25 MS/s Pipelined ADC with a 3 input multiplexer for CALICE Integrated Readout

    CERN Document Server

    Rarbi, F; Gallin-Martell, L; Hostachy, J Y

    2009-01-01

    The necessity of full integrated electronics readout for the next ILC ECAL presents many challenges for low power mixed signal design. The analog to digital converter is a critical stage for the system going from the very front-end stages to digital memories. We present here a high speed converter configuration designed to multiplex 3 analog channels through one analog to digital converter. It is a first step for a multiplexed 64 channel design. A CMOS 0.35μm process is used. The dynamic range is 2V over a 3.3V power supply, and the total power dissipation at 25 MHz is approximately 40mW. An analog power management is included to allow a fast switching into a standby mode that reduces the DC power dissipation by a ratio of three orders of magnitude (1/1000).

  11. High Speed Digitizer for Remote Sensing Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in a...

  12. On the comparison of analog and digital SiPM readout in terms of expected timing performance

    Energy Technology Data Exchange (ETDEWEB)

    Gundacker, S., E-mail: stefan.gundacker@cern.ch; Auffray, E.; Jarron, P.; Meyer, T.; Lecoq, P.

    2015-07-01

    In time of flight positron emission tomography (TOF-PET) and in particular for the EndoTOFPET-US Project (Frisch, 2013 [1]), and other applications for high energy physics, the multi-digital silicon photomultiplier (MD-SiPM) was recently proposed (Mandai and Charbon, 2012 [2]), in which the time of every single photoelectron is being recorded. If such a photodetector is coupled to a scintillator, the largest and most accurate timing information can be extracted from the cascade of the scintillation photons, and the most probable time of positron emission determined. The readout concept of the MD-SiPM is very different from that of the analog SiPM, where the individual photoelectrons are merely summed up and the output signal fed into the readout electronics. We have developed a comprehensive Monte Carlo (MC) simulation tool that describes the timing properties of the photodetector and electronics, the scintillation properties of the crystal and the light transfer within the crystal. In previous studies we have compared MC simulations with coincidence time resolution (CTR) measurements and found good agreement within less than 10% for crystals of different lengths (from 3 mm to 20 mm) coupled to SiPMs from Hamamatsu. In this work we will use the developed MC tool to directly compare the highest possible time resolution for both the analog and digital readout of SiPMs with different scintillator lengths. The presented studies reveal that the analog readout of SiPMs with microcell signal pile-up and leading edge discrimination can lead to nearly the same time resolution as compared to the maximum likelihood time estimation applied to MD-SiPMs. Consequently there is no real preference for either a digital or analog SiPM for the sake of achieving highest time resolution. However, the best CTR in the analog SiPM is observed for a rather small range of optimal threshold values, whereas the MD-SiPM provides stable CTR after roughly 20 registered photoelectron timestamps in

  13. Digital Simulation of Closed Loop Zvs-Zcs Bidirectional Dc-Dc Converter for Fuel Cell and Battery Application

    Directory of Open Access Journals (Sweden)

    V. V. Subrahmanya Kumar Bhajana

    2010-08-01

    Full Text Available A closed loop ZVS-ZCS bidirectional dc-dc converter is modeled and appropriate digital simulations are provided. With the ZVS-ZCS concept, the MATLAB simulation results of application to a fuel cell and battery application have been obtained whenever the input voltage exceeds the given 24V, at that time the load voltage will change from 180V to 230V. But due to this usage the load is disturbed and there is instability in the model. Using closed loop the output voltage is stabilized.

  14. Converting Student Support Services to Online Delivery.

    Science.gov (United States)

    Brigham, David E.

    2001-01-01

    Uses a systems framework to analyze the creation of student support services for distance education at Regents College: electronic advising, electronic peer network, online course database, online bookstore, virtual library, and alumni services website. Addresses the issues involved in converting distance education programs from print-based and…

  15. Fast Constant Weight Codeword to Index Converter

    Science.gov (United States)

    2011-08-01

    is achievable; a 64-out- of-128 bit converter uses only 9% of the available ALMs. The large values of n required special Verilog programming. For...n r ) in a MATLAB program and wrote it to a header file that was included in the Verilog code. III. COMPLEX DISJOINT DECOMPOSITION SOLUTION It can

  16. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

    @@ China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.

  17. China to Gradually Make Capital Account Convertible

    Institute of Scientific and Technical Information of China (English)

    2006-01-01

      China is pushing forward its currency Renminbi (RMB)'s capital account convertibility gradually and in a stable manner, said an official with the State Administration of Foreign Exchange (SAFE), ruling out both an adventurous leap and conservative cautiousness, according to a report of Xinhua on April 12.……

  18. The development and demonstration of hybrid programmable attitude control electronics. [with adaptable analog/digital design approach

    Science.gov (United States)

    Smith, L. S.; Kopf, E. H., Jr.

    1974-01-01

    HYPACE provides an adaptable, analog/digital design approach that permits preflight and in-flight accommodation of mission changes, component performance variations, spacecraft changes, etc., through programing. This enabled broad multimission flexibility of application in a cost-effective manner. The HYPACE design, which was demonstrated in breadboard form on a single-axis gas-bearing spacecraft simulation, uses a single control channel to perform the attitude control functions sequentially, thus significantly reducing the number of component parts over hard-wired designs. The success of this effort resulted in the concept being selected for the Mariner/Jupiter/Saturn 1977 spacecraft application.

  19. A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

    Institute of Scientific and Technical Information of China (English)

    Xie Renzhong; Jiang Chen; Li Weinan; Huang Yumei; Hong Zhiliang

    2011-01-01

    A dual-mode analog baseband with digital-assisted DC-offsset calibration(DCOC)for WCDMA/GSM receiver is presented.A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DCoffset component only.This method has no bandwidth sacrifice.After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm.The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz.Total baseband gain can be programmed from 6 to 54 dB.The chip is manufactured with 0.13 μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm2.

  20. DigitSeis: A New Digitization Software and its Application to the Harvard-Adam Dziewoński Observatory Collection

    Science.gov (United States)

    Bogiatzis, P.; Altoé, I. L.; Karamitrou, A.; Ishii, M.; Ishii, H.

    2015-12-01

    DigitSeis is a new open-source, interactive digitization software written in MATLAB that converts digital, raster images of analog seismograms to readily usable, discretized time series using image processing algorithms. DigitSeis automatically identifies and corrects for various geometrical distortions of seismogram images that are acquired through the original recording, storage, and scanning procedures. With human supervision, the software further identifies and classifies important features such as time marks and notes, corrects time-mark offsets from the main trace, and digitizes the combined trace with an analysis to obtain as accurate timing as possible. Although a large effort has been made to minimize the human input, DigitSeis provides interactive tools for challenging situations such as trace crossings and stains in the paper. The effectiveness of the software is demonstrated with the digitization of seismograms that are over half a century old from the Harvard-Adam Dziewoński observatory that is still in operation as a part of the Global Seismographic Network (station code HRV and network code IU). The spectral analysis of the digitized time series shows no spurious features that may be related to the occurrence of minute and hour marks. They also display signals associated with significant earthquakes, and a comparison of the spectrograms with modern recordings reveals similarities in the background noise.

  1. Development of a High-Speed Digitizer to Time Resolve Nanosecond Fluorescence Pulses

    Directory of Open Access Journals (Sweden)

    E. Moreno-García

    2012-04-01

    Full Text Available The development of a high-speed digitizer system to measure time-domain voltage pulses in nanoseconds range is presented in this work. The digitizer design includes a high performance digital signal processor, a high-bandwidth analog-to-digital converter of flash-type, a set of delay lines, and a computer to achieve the time-domain measurements. A program running on the processor applies a time-equivalent sampling technique to acquire the input pulse. The processor communicates with the computer via a serial port RS-232 to receive commands and to transmit data. A control program written in LabVIEW 7.1 starts an acquisition routine in the processor. The program reads data from processor point by point in each occurrence of the signal, and plots each point to recover the time-resolved input pulse after n occurrences. The developed prototype is applied to measure fluorescence pulses from a homemade spectrometer. For this application, the LabVIEW program was improved to control the spectrometer, and to register and plot time-resolved fluorescence pulses produced by a substance. The developed digitizer has 750 MHz of analog input bandwidth, and it is able to resolve 2 ns rise-time pulses with 150 ps of resolution and a temporal error of 2.6 percent.

  2. Digital Fuzzy logic and PI control of phase-shifted full-bridge current-doubler converter

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2011-01-01

    Simple digital fuzzy logic voltage control of a phaseshifted full-bridge (PSFB) converter is proposed in this article. A comparison of the fuzzy controller and the classical PI voltage controller is presented and their effects on the converter dynamics are analyzed. Simulation model of the conver...... of the converter was built in Matlab/Simulink using PLECS. A 600W PSFB convert was designed and built and the control strategies were implemented in a 16 bit fixed point dsPIC microcontroller. The advantages and disadvantages of using Fuzzy logic control are highlighted....

  3. An integrated device with high performance multi-function generators and time-to-digital convertors

    Science.gov (United States)

    Qin, X.; Shi, Z.; Xie, Y.; Wang, L.; Rong, X.; Jia, W.; Zhang, W.; Du, J.

    2017-01-01

    A highly integrated, high performance, and re-configurable device, which is designed for the Nitrogen-Vacancy (N-V) center based quantum applications, is reported. The digital compartment of the device is fully implemented in a Field-Programmable-Gate-Array (FPGA). The digital compartment is designed to manage the multi-function digital waveform generation and the time-to-digital convertors. The device provides two arbitrary-waveform-generator channels which operate at a 1 Gsps sampling rate with a maximum bandwidth of 500 MHz. There are twelve pulse channels integrated in the device with a 50 ps time resolution in both duration and delay. The pulse channels operate with the 3.3 V transistor-transistor logic. The FPGA-based time-to-digital convertor provides a 23-ps time measurement precision. A data accumulation module, which can record the input count rate and the distributions of the time measurement, is also available. A digital-to-analog convertor board is implemented as the analog compartment, which converts the digital waveforms to analog signals with 500 MHz lowpass filters. All the input and output channels of the device are equipped with 50 Ω SubMiniature version A termination. The hardware design is modularized thus it can be easily upgraded with compatible components. The device is suitable to be applied in the quantum technologies based on the N-V centers, as well as in other quantum solid state systems, such as quantum dots, phosphorus doped in silicon, and defect spins in silicon carbide.

  4. Local digital control of power electronic converters in a dc microgrid based on a-priori derivation of switching surfaces

    Science.gov (United States)

    Banerjee, Bibaswan

    In power electronic basedmicrogrids, the computational requirements needed to implement an optimized online control strategy can be prohibitive. The work presented in this dissertation proposes a generalized method of derivation of geometric manifolds in a dc microgrid that is based on the a-priori computation of the optimal reactions and trajectories for classes of events in a dc microgrid. The proposed states are the stored energies in all the energy storage elements of the dc microgrid and power flowing into them. It is anticipated that calculating a large enough set of dissimilar transient scenarios will also span many scenarios not specifically used to develop the surface. These geometric manifolds will then be used as reference surfaces in any type of controller, such as a sliding mode hysteretic controller. The presence of switched power converters in microgrids involve different control actions for different system events. The control of the switch states of the converters is essential for steady state and transient operations. A digital memory look-up based controller that uses a hysteretic sliding mode control strategy is an effective technique to generate the proper switch states for the converters. An example dcmicrogrid with three dc-dc boost converters and resistive loads is considered for this work. The geometric manifolds are successfully generated for transient events, such as step changes in the loads and the sources. The surfaces corresponding to a specific case of step change in the loads are then used as reference surfaces in an EEPROM for experimentally validating the control strategy. The required switch states corresponding to this specific transient scenario are programmed in the EEPROM as a memory table. This controls the switching of the dc-dc boost converters and drives the system states to the reference manifold. In this work, it is shown that this strategy effectively controls the system for a transient condition such as step changes

  5. Discrete iterative-map mo deling and dynamical analysis of digital voltage-mo de controlled buck converter with dual-edge mo dulation%基于双缘调制的数字电压型控制Buck变换器离散迭代映射建模与动力学分析∗

    Institute of Scientific and Technical Information of China (English)

    刘啸天; 周国华; 李振华; 陈兴

    2015-01-01

    The operation principle of digital voltage-mode controlled buck converter with dual-edge modulation is analyzed in this paper. Based on the state equation of buck converter and six possible evolutions in one switching cycle, the discrete iterative-map model of digital voltage-mode controlled buck converter with dual-edge modulation is established. Ignoring the quantization error of analog-digital converter and on the basis of its discrete iterative-map model, the nonlinear dynamical behavior of digital voltage-mode controlled buck converter with dual-edge modulation is investigated in detail. Taking the input voltage and the load resistance as bifurcation parameters, the output voltage bifurcation diagram and the inductor current bifurcation diagram are plotted. Through analyzing the bifurcation diagrams, it is indicated that there are two kinds of similar but different Hopf bifurcation phenomena. By use of Poincar´e section, time-domain simulation waveforms and phase portraits, two different Hopf bifurcations and low-frequency oscillation phenomena are compared and studied. Observing the inductor current and capacitor voltage waveforms respectively, it is obviously found that their oscillation frequencies and amplitudes are different, the shapes of two Poincar´e sections and phase portraits are also different. In order to verify the correctness of the simulation and theoretical analysis, the eigenvalues of Jacobian matrix of the discrete iterative map model are introduced and solved in two kinds of stable evolutions. Through analyzing variation of eigenvalues of Jacobi matrix with input voltage, the existence and difference of two kinds of Hopf bifurcation phenomena are proved theoretically. Moreover, it is observed in this paper that the odd period-doubling bifurcation phenomenon exists in digital voltage-mode controlled buck converter with dual-edge modulation for the first time, where the operation state of the buck converter turns from period-one into period

  6. Optical Flow in a Smart Sensor Based on Hybrid Analog-Digital Architecture

    Directory of Open Access Journals (Sweden)

    Pablo Guzmán

    2010-03-01

    Full Text Available The purpose of this study is to develop a motion sensor (delivering optical flow estimations using a platform that includes the sensor itself, focal plane processing resources, and co-processing resources on a general purpose embedded processor. All this is implemented on a single device as a SoC (System-on-a-Chip. Optical flow is the 2-D projection into the camera plane of the 3-D motion information presented at the world scenario. This motion representation is widespread well-known and applied in the science community to solve a wide variety of problems. Most applications based on motion estimation require work in real-time; hence, this restriction must be taken into account. In this paper, we show an efficient approach to estimate the motion velocity vectors with an architecture based on a focal plane processor combined on-chip with a 32 bits NIOS II processor. Our approach relies on the simplification of the original optical flow model and its efficient implementation in a platform that combines an analog (focal-plane and digital (NIOS II processor. The system is fully functional and is organized in different stages where the early processing (focal plane stage is mainly focus to pre-process the input image stream to reduce the computational cost in the post-processing (NIOS II stage. We present the employed co-design techniques and analyze this novel architecture. We evaluate the system’s performance and accuracy with respect to the different proposed approaches described in the literature. We also discuss the advantages of the proposed approach as well as the degree of efficiency which can be obtained from the focal plane processing capabilities of the system. The final outcome is a low cost smart sensor for optical flow computation with real-time performance and reduced power consumption that can be used for very diverse application domains.

  7. Optical flow in a smart sensor based on hybrid analog-digital architecture.

    Science.gov (United States)

    Guzmán, Pablo; Díaz, Javier; Agís, Rodrigo; Ros, Eduardo

    2010-01-01

    The purpose of this study is to develop a motion sensor (delivering optical flow estimations) using a platform that includes the sensor itself, focal plane processing resources, and co-processing resources on a general purpose embedded processor. All this is implemented on a single device as a SoC (System-on-a-Chip). Optical flow is the 2-D projection into the camera plane of the 3-D motion information presented at the world scenario. This motion representation is widespread well-known and applied in the science community to solve a wide variety of problems. Most applications based on motion estimation require work in real-time; hence, this restriction must be taken into account. In this paper, we show an efficient approach to estimate the motion velocity vectors with an architecture based on a focal plane processor combined on-chip with a 32 bits NIOS II processor. Our approach relies on the simplification of the original optical flow model and its efficient implementation in a platform that combines an analog (focal-plane) and digital (NIOS II) processor. The system is fully functional and is organized in different stages where the early processing (focal plane) stage is mainly focus to pre-process the input image stream to reduce the computational cost in the post-processing (NIOS II) stage. We present the employed co-design techniques and analyze this novel architecture. We evaluate the system's performance and accuracy with respect to the different proposed approaches described in the literature. We also discuss the advantages of the proposed approach as well as the degree of efficiency which can be obtained from the focal plane processing capabilities of the system. The final outcome is a low cost smart sensor for optical flow computation with real-time performance and reduced power consumption that can be used for very diverse application domains.

  8. Converting Student Support Services to Online Delivery

    OpenAIRE

    David E. Brigham

    2001-01-01

    This case study describes how Regents College (soon to be Excelsior College), an accredited, private, distance education institution with administrative offices in Albany, New York addressed the structural, management, and resource issues that came into play when converting distance education programs from print-based and telephone delivery to online delivery. The study uses a systems framework to describe and analyze the circumstances and issues surrounding the creation of six student suppor...

  9. An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

    Directory of Open Access Journals (Sweden)

    Yuan Cao

    2014-12-01

    Full Text Available In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO based analog-to-digital converter (ADC to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is preserved. Moreover, by combining the gamma correction with the analog-to-digital conversion, the silicon area and overall power consumption can be greatly reduced. The proposed gamma correction scheme is validated by the reported simulation results and the experimental results measured for our designed test structure, which is fabricated with 0.35 μm standard complementary-metal-oxide-semiconductor (CMOS process.

  10. Data Converters Performance at Extreme Temperatures

    Science.gov (United States)

    Rejeshuni, Rarnesham; Kumar, Nikil; Mao, James; Keymeulen, Didier; Zebulum, Ricardo S.; Stoica, Adrian

    2006-01-01

    Space missions often require radiation and extreme-temperature hardened electronics to survive the harsh environments beyond earth's atmosphere. Traditional approaches to preserve electronics incorporate shielding, insulation and redundancy at the expense of power and weight. However, a novel way of bypassing these problems is the concept of evolutionary hardware. A reconfgurable device, consisting of several switches interconnected with analog/digital parts, is controlled by an evolutionary processor (EP). When the EP detects degradation in the circuit it sends signals to reconfgure the switches, thus forming a new circuit with the desired output. This concept has been developed since the mid-90s, but one problem remains - the EP cannot degrade substantially. For this reason, extensive testing at extreme temperatures (-180' to 120(deg)C) has been done on devices found on FPGA boards (taking the role of the EP) such as the Analog to Digital and the Digital to Analog Converter. Analysis of the results has shown that FPGA boards implementing EP with some compensation may be a practical solution to evolving circuits. This paper describes results on the tests of data converters at extreme temperatures.

  11. Progress on the development of a detector mounted analog and digital readout system for the ATLAS TRT

    CERN Document Server

    Baxter, C; Dressnandt, N; Gay, C; Lundberg, B; Munar, A; Mayers, G; Newcomer, M; Van Berg, R; Williams, H H

    2004-01-01

    The 430,000 element ATLAS Transition Radiation straw tube Tracker (TRT) is divided into a central barrel tracker consisting of 104,000 axially mounted straws and two radially arranged end caps on either side of the barrel with 160,000 straws each. To achieve a track position resolution of 140 mu m, the front end electronics must operate at a low (2fC) threshold with a time marking capability of ~1ns. Two ASICs, the ASDBLR and DTMROC provide the complete pipelined readout chain. Custom designed FBGA packages for the ASICs provide a small enough outline to be detector mounted and the extensive use of low level differential signals make mounting the analog packages on printed circuit boards directly opposite the 40 MHz digital chips feasible. The readout electronics for the barrel occupies a potentially important part of the active tracker volume and an aggressive effort has been made to make it as compact as possible. Utilizing a single board for both analog and digital ASICS a 0.1 cm /sup 3/ per channel volume...

  12. Construction Of 3phase Sine Waves Using Digital Technique

    Directory of Open Access Journals (Sweden)

    S.Madhavi

    2012-11-01

    Full Text Available All the real world parameters such as temperature, pressure etc., are analog in nature, In order to control these physical parameters using computers, which are digital in nature, high speed signal processing board is used. This mainly consists of devices such as analog to digital converter, digital to analog converters and timer which perform the interfacing function between analog and digital are known as data converters. By using Digital methods accuracy and precision of the equipment will be very high compared to analog method of sine wave generation. It provides highly stable and accurate Voltages, Currents and frequency of the 3 phase signals because it is having feedback mechanism. This work consists of DAC 8822[7], 8254 [6] Programmable Timer. This timer is programmed to generate an interrupt of 56µs time period which is fed to IRQ10 pin of PC 104 bus based single board computer [3]. A Device driver is written in Linux which is inserted into the Kernel. Then the processor communicates with 16- bit high speed DAC[7]which outputs the sine samples of 50Hz frequency.

  13. Compact self-contained electrical-to-optical converter/transmitter

    Energy Technology Data Exchange (ETDEWEB)

    Seligmann, D.A.; Moss, W.C.; Valk, T.C.; Conder, A.D.

    1992-12-31

    An electrical-to-optical converter/transmitter is disclosed. A first optical receiver and a second optical receiver are provided for receiving a calibrate command and a power switching signal, respectively, from a remote processor. A third receiver is provided for receiving an analog electrical signal from a transducer. A calibrator generates a reference signal in response to the calibrate command. A combiner mixes the electrical signal with the reference signal to form a calibrated signal. A converter converts the calibrated signal to an optical signal. A transmitter transmits the optical signal to the remote processor. A primary battery supplies power to the calibrator, the combiner, the converter, and the transmitter. An optically-activated switch supplies power to the calibrator, the combiner, the converter, and the transmitter in response to the power switching signal. An auxiliary battery supplies power continuously to the switch means.

  14. Emissions Tests Of Two Dc-To-Dc Converters

    Science.gov (United States)

    Mclyman, W. T.

    1992-01-01

    Report describes tests to characterize unwanted electric and magnetic fields, at frequencies up to few megahertz, radiated by two dc-to-dc converters, one 20-kHz square-wave converter; the other, a 33-kHz sine-wave converter. Part of effort to develop "quiet" power converter for use aboard spacecraft. Converter required to interfere minimally with delicate instruments measuring electric and magnetic fields.

  15. Quantum Electric Circuits Analogous to Ballistic Conductors

    OpenAIRE

    2007-01-01

    The conductance steps in a constricted two-dimensional electron gas and the minimum conductivity in graphene are related to a new uncertainty relation between electric charge and conductance in a quantized electric circuit that mimics the electric transport in mesoscopic systems. This uncertainty relation makes specific use of the discreteness of electric charge. Quantum electric circuits analogous to both constricted two-dimensional electron gas and graphene are introduced. In the latter cas...

  16. HOW TO USE ANALOGIES FOR BREAKTHROUGH INNOVATIONS

    OpenAIRE

    CORNELIUS HERSTATT; KATHARINA KALOGERAKIS

    2005-01-01

    Analogies can trigger breakthrough ideas in new product development. Numerous examples demonstrate that substantial innovations often result from transferring problem solutions from one industry or domain to another. For instance, the designers of the new running show generation of Nike, "Nike SHOX", use the same suspension concept like the technologies applied for formula 1 racing cars, or the biological Lotus-effect leading to the evelopment of various self-cleaning surfaces. Academic resea...

  17. How to use analogies for breakthrough innovations

    OpenAIRE

    Schild, Katharina; Herstatt, Cornelius; Lüthje, Christian

    2004-01-01

    Analogies can trigger breakthrough ideas in new product development. Numerous examples demonstrate that substantial innovations often result from transferring problem solutions from one industry or domain to another. For instance, the designers of the new running shoe generation of Nike, “Nike SHOX”, use the same suspension concept like the technologies applied for Formula 1 racing cars, or the biological Lotus-effect led to the development of various self-cleaning surfaces. Academic resea...

  18. Toward direct light-to-digital conversion using a pulse-driven hybrid MOS-PN photodetector.

    Science.gov (United States)

    Sallin, Denis; Koukab, Adil; Kayal, Maher

    2015-02-15

    In this Letter, a direct light-to-digital converter based on an MOS-PN photodetector driven by pulsed voltage is presented. The objective is to avoid any analog-to-digital or time-to-digital conversion and, thereby, to pave the way for a new generation of fully digital imaging sensors with reduced complexity, area, and power consumption. Moreover, the pulsed voltage operation allows for a significant reduction of the dark level. The concept is validated by a theoretical study and TCAD simulations. A first prototype fabricated in 0.18 μm CMOS technology is presented. The experimental results under various light conditions show that the pulsed voltage improves the light sensitivity by several orders of magnitude.

  19. Traditional to Digital Books

    Institute of Scientific and Technical Information of China (English)

    JING XIAOLEI

    2010-01-01

    @@ A book fair wouldn't be a book fair without books.And while the number of book fairs in China has increased in recent years,the Guangzhou Book Fair has been helping to redefine the very nature of books by promoting digital works and reading technology.This year,the fair again set up an exclusive digital reading experience exhibition hall to showcase the host province's latest achievements in the field.

  20. Digital media labs in libraries

    CERN Document Server

    Goodman, Amanda L

    2014-01-01

    Families share stories with each other and veterans reconnect with their comrades, while teens edit music videos and then upload them to the web: all this and more can happen in the digital media lab (DML), a gathering of equipment with which people create digital content or convert content that is in analog formats. Enabling community members to create digital content was identified by The Edge Initiative, a national coalition of leading library and local government organizations, as a library technology benchmark. Surveying academic and public libraries in a variety of settings and sharing a

  1. Delta-Sigma Modulated Photodetection Method to Reduce Laser Power Project

    Data.gov (United States)

    National Aeronautics and Space Administration — This delta-sigma technique may be thought of as a form of analog-to-digital converter (ADC). The proposed network offers a means of processing electronic signals...

  2. Converting VSAM in COBOL to embedded SQL

    Energy Technology Data Exchange (ETDEWEB)

    Huang, Hai; Wang, Yamin; Tsai, Wei-Tek [Univ. of Minnesota, Minneapolis, MN (United States)

    1996-12-31

    VSAM databases we widely used on IBM mainframe systems. As new technology, such as relational database and client-server computing, becomes popular, there is a need to reengineer the VSAM databases to relational databases. This paper addresses the issues on converting COBOL programs that access VSAM database to COBOL programs that access relational databases with embedded SQL. It proposed a semi-automatic approach to the conversion of VSAM data sets to SQL tables and VSAM operations in COBOL program to embedded SQL queries. The proposed approach has been experimented on several industrial COBOL programs and a tool implementing the approach is under development.

  3. Coordinated Control of Wave Energy Converters Subject to Motion Constraints

    OpenAIRE

    2016-01-01

    In this paper, a generic coordinated control method for wave energy converters is proposed, and the constraints on motion amplitudes and the hydrodynamic interaction between converters are considered. The objective of the control problem is to maximize the energy converted from ocean waves, and this is achieved by coordinating the power take-off (PTO) damping of each wave energy converter in the frequency domain in each sea state. In a case study, a wave energy farm consisting of four convert...

  4. Converting Student Support Services to Online Delivery

    Directory of Open Access Journals (Sweden)

    David E. Brigham

    2001-01-01

    Full Text Available This case study describes how Regents College (soon to be Excelsior College, an accredited, private, distance education institution with administrative offices in Albany, New York addressed the structural, management, and resource issues that came into play when converting distance education programs from print-based and telephone delivery to online delivery. The study uses a systems framework to describe and analyze the circumstances and issues surrounding the creation of six student support services: electronic advising, an electronic peer network, an online database of distance courses, an online bookstore, a virtual library, and an alumni services website.

  5. Digital Libraries and the Problem of Purpose [and] On DigiPaper and the Dissemination of Electronic Documents [and] DFAS: The Distributed Finding Aid Search System [and] Best Practices for Digital Archiving: An Information Life Cycle Approach [and] Mapping and Converting Essential Federal Geographic Data Committee (FGDC) Metadata into MARC21 and Dublin Core: Towards an Alternative to the FGDC Clearinghouse [and] Evaluating Website Modifications at the National Library of Medicine through Search Log analysis.

    Science.gov (United States)

    Levy, David M.; Huttenlocher, Dan; Moll, Angela; Smith, MacKenzie; Hodge, Gail M.; Chandler, Adam; Foley, Dan; Hafez, Alaaeldin M.; Redalen, Aaron; Miller, Naomi

    2000-01-01

    Includes six articles focusing on the purpose of digital public libraries; encoding electronic documents through compression techniques; a distributed finding aid server; digital archiving practices in the framework of information life cycle management; converting metadata into MARC format and Dublin Core formats; and evaluating Web sites through…

  6. 47 CFR 74.796 - Modification of digital transmission systems and analog transmission systems for digital operation.

    Science.gov (United States)

    2010-10-01

    ...) Subtract the value determined in the previous step from the authorized effective radiated power (“ERP”) of... ERP must be expressed in decibels above one kilowatt: ERP(dBk) = 10 log ERP(kW); (4) Convert the ERP calculated in the previous step to units of kilowatts; and (5) The ERP value determined through the...

  7. A Robust Method to Improve Stability in Matrix Converters

    DEFF Research Database (Denmark)

    Liu, F.; Klumpner, Christian; Blaabjerg, Frede

    2004-01-01

    of instability. The matrix converter stability can be improved by decoupling its input current with the input voltage. A modulation strategy is presented that satisfies the idea. The difference of the strategy compared with the traditional one only concerns on the definition of the reference angle for the input...... current vector. A matrix converter model that takes the switching behavior and effects related with the digital implementations into consideration is developed for evaluation of the strategy. The simulation results show that the proposed strategy can highly improve the matrix converter stability...

  8. CMOS digital pixel sensors: technology and applications

    Science.gov (United States)

    Skorka, Orit; Joseph, Dileepan

    2014-04-01

    CMOS active pixel sensor technology, which is widely used these days for digital imaging, is based on analog pixels. Transition to digital pixel sensors can boost signal-to-noise ratios and enhance image quality, but can increase pixel area to dimensions that are impractical for the high-volume market of consumer electronic devices. There are two main approaches to digital pixel design. The first uses digitization methods that largely rely on photodetector properties and so are unique to imaging. The second is based on adaptation of a classical analog-to-digital converter (ADC) for in-pixel data conversion. Imaging systems for medical, industrial, and security applications are emerging lower-volume markets that can benefit from these in-pixel ADCs. With these applications, larger pixels are typically acceptable, and imaging may be done in invisible spectral bands.

  9. Converting DYNAMO simulations to Powersim Studio simulations

    Energy Technology Data Exchange (ETDEWEB)

    Walker, La Tonya Nicole; Malczynski, Leonard A.

    2014-02-01

    DYNAMO is a computer program for building and running 'continuous' simulation models. It was developed by the Industrial Dynamics Group at the Massachusetts Institute of Technology for simulating dynamic feedback models of business, economic, and social systems. The history of the system dynamics method since 1957 includes many classic models built in DYANMO. It was not until the late 1980s that software was built to take advantage of the rise of personal computers and graphical user interfaces that DYNAMO was supplanted. There is much learning and insight to be gained from examining the DYANMO models and their accompanying research papers. We believe that it is a worthwhile exercise to convert DYNAMO models to more recent software packages. We have made an attempt to make it easier to turn these models into a more current system dynamics software language, Powersim © Studio produced by Powersim AS2 of Bergen, Norway. This guide shows how to convert DYNAMO syntax into Studio syntax.

  10. Forback DC-to-DC converter

    Science.gov (United States)

    Lukemire, Alan T.

    1995-05-01

    A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

  11. Forback DC-to-DC converter

    Science.gov (United States)

    Lukemire, Alan T. (Inventor)

    1993-01-01

    A pulse-width modulated DC-to-DC power converter including a first inductor, i.e. a transformer or an equivalent fixed inductor equal to the inductance of the secondary winding of the transformer, coupled across a source of DC input voltage via a transistor switch which is rendered alternately conductive (ON) and nonconductive (OFF) in accordance with a signal from a feedback control circuit is described. A first capacitor capacitively couples one side of the first inductor to a second inductor which is connected to a second capacitor which is coupled to the other side of the first inductor. A circuit load shunts the second capacitor. A semiconductor diode is additionally coupled from a common circuit connection between the first capacitor and the second inductor to the other side of the first inductor. A current sense transformer generating a current feedback signal for the switch control circuit is directly coupled in series with the other side of the first inductor so that the first capacitor, the second inductor and the current sense transformer are connected in series through the first inductor. The inductance values of the first and second inductors, moreover, are made identical. Such a converter topology results in a simultaneous voltsecond balance in the first inductance and ampere-second balance in the current sense transformer.

  12. Digital Light Processing and MEMS: reflecting the digital display needs of the networked society

    Science.gov (United States)

    Hornbeck, Larry J.

    1996-08-01

    Digital video technology is becoming increasingly important to the networked society. The natural interface to digital video is a digital display, one that accepts electrical bits at its input and converts them into optical bits at the output. The digital-to-analog processing function is performed in the mind of the observer. Texas Instruments has developed such a display with its recent market introduction of the Digital Light ProcessingTM (DLPTM) projection display. DLP technology is based on the Digital Micromirror DeviceTM (DMDTM), a microelectromechanical systems (MEMS) array of semiconductor-based digital light switches. The DMD switching array precisely controls a light source for projection display and digital printing applications. This paper presents an overview of DLP technology along with the architecture, projection operation, manufacture, and reliability of the DMD. Features of DMD technology that distinguish it from conventional MEMS technology are explored. Finally, the paper provides a view of DLP business opportunities.

  13. Dynamic-mismatch mapping for digitally-assisted DACs

    CERN Document Server

    Tang, Yongjian; van Roermund, Arthur

    2013-01-01

    This book describes a novel digital calibration technique called dynamic-mismatch mapping (DMM) to improve the performance of digital to analog converters (DACs).  Compared to other techniques, the DMM technique has the advantage of calibrating all mismatch errors without any noise penalty, which is particularly useful in order to meet the demand for high performance DACs in rapidly developing applications, such as multimedia and communication systems.   ·         Discusses fundamental performance limitations of digital to analog converters and summarizes existing design/calibration techniques; ·         Introduces a novel digital calibration technique, called dynamic-mismatch mapping (DMM) to improve both static and dynamic performance of DACs; ·         Includes two state-of-the-art DAC design examples with in-depth discussion.

  14. Design and evaluation of a low-level RF control system analog/digital receiver for the ILC main Linacs

    Energy Technology Data Exchange (ETDEWEB)

    Mavric, Uros; Vidmar, Matjaz; Chase, Brian; /Fermilab

    2008-06-01

    The proposed RF distribution scheme for the two 15 km long ILC LINACs, uses one klystron to feed 26 superconducting RF cavities operating at 1.3 GHz. For a precise control of the vector sum of the signals coming from the SC cavities, the control system needs a high performance, low cost, reliable and modular multichannel receiver. At Fermilab we developed a 96 channel, 1.3 GHz analog/digital receiver for the ILC LINAC LLRF control system. In the paper we present a balanced design approach to the specifications of each receiver section, the design choices made to fulfill the goals and a description of the prototyped system. The design is tested by measuring standard performance parameters, such as noise figure, linearity and temperature sensitivity. Measurements show that the design meets the specifications and it is comparable to other similar systems developed at other laboratories, in terms of performance.

  15. Design and evaluation of a low-level RF control system analog/digital receiver for the ILC main LINACs

    Energy Technology Data Exchange (ETDEWEB)

    Mavric, Uros [Fermilab, P.O. Box 500, 60510 Batavia, IL (United States)], E-mail: mavric@fnal.gov; Chase, Brian [Fermilab, P.O. Box 500, 60510 Batavia, IL (United States); Vidmar, Matjaz [Faculty of Electrical Engineering in Ljubljana, Trzaska 25, 1000 Ljubljana (Slovenia)

    2008-08-21

    The proposed RF distribution scheme for the two 15 km long ILC LINACs uses one klystron to feed 26 superconducting RF cavities operating at 1.3 GHz. For a precise control of the vector sum of the signals coming from the SC cavities, the control system needs a high-performance, low-cost, reliable and modular multichannel receiver. At Fermilab we developed a 96-channel, 1.3 GHz analog/digital receiver for the ILC LINAC LLRF control system. In this paper we present a balanced design approach to the specifications of each receiver section, the design choices made to fulfill the goals and a description of the prototyped system. The design is tested by measuring standard performance parameters, such as noise figure, linearity and temperature sensitivity. Measurements show that the design meets the specifications and it is comparable to other similar systems developed at other laboratories, in terms of performance.

  16. Mechanical vibration to electrical energy converter

    Science.gov (United States)

    Kellogg, Rick Allen; Brotz, Jay Kristoffer

    2009-03-03

    Electromechanical devices that generate an electrical signal in response to an external source of mechanical vibrations can operate as a sensor of vibrations and as an energy harvester for converting mechanical vibration to electrical energy. The devices incorporate a magnet that is movable through a gap in a ferromagnetic circuit, wherein a coil is wound around a portion of the ferromagnetic circuit. A flexible coupling is used to attach the magnet to a frame for providing alignment of the magnet as it moves or oscillates through the gap in the ferromagnetic circuit. The motion of the magnet can be constrained to occur within a substantially linear range of magnetostatic force that develops due to the motion of the magnet. The devices can have ferromagnetic circuits with multiple arms, an array of magnets having alternating polarity and, encompass micro-electromechanical (MEM) devices.

  17. The exoplanets analogy to the Multiverse

    CERN Document Server

    Kinouchi, Osame

    2015-01-01

    The idea of a Mutiverse is controversial, although it is a natural possible solution to particle physics and cosmological fine-tuning problems (FTPs). Here I explore the analogy between the Multiverse proposal and the proposal that there exist an infinite number of stellar systems with planets in a flat Universe, the Multiplanetverse. Although the measure problem is present in this scenario, the idea of a Multiplanetverse has predictive power, even in the absence of direct evidence for exoplanets that appeared since the 90s. We argue that the fine-tuning of Earth to life (and not only the fine-tuning of life to Earth) could predict with certainty the existence of exoplanets decades or even centuries before that direct evidence. Several other predictions can be made by studying only the Earth and the Sun, without any information about stars. The analogy also shows that theories that defend that the Earth is the unique existing planet and that, at the same time, is fine-tuned to life by pure chance (or pure phy...

  18. CMOS sigma-delta converters practical design guide

    CERN Document Server

    De la Rosa, Jose M

    2013-01-01

    A comprehensive overview of Sigma-Delta Analog-to-Digital Converters (ADCs) and a practical guide to their design in nano-scale CMOS for optimal performance. This book presents a systematic and comprehensive compilation of sigma-delta converter operating principles, the new advances in architectures and circuits, design methodologies and practical considerations - going from system-level specifications to silicon integration, packaging and measurements, with emphasis on nanometer CMOS implementation. The book emphasizes practical design issues - from high-level behavioural modelling i

  19. Radiant energy to electric energy converter

    Science.gov (United States)

    Sher, Arden (Inventor)

    1980-01-01

    Radiant energy is converted into electric energy by irradiating a capacitor including an ionic dielectric. The dielectric is a sintered crystal superionic conductor, e.g., lanthanum trifluoride, lanthanum trichloride, or silver bromide, so that a multiplicity of crystallites exist between electrodes of the capacitor. The radiant energy cyclically irradiates the dielectric so that the dielectric exhibits a cyclic photocapacitive like effect. Adjacent crystallites have abutting surfaces that enable the crystallites to effectively form a multiplicity of series capacitor elements between the electrodes. Each of the capacitor elements has a dipole layer only on or near its surface. The capacitor is initially charged to a voltage just below the dielectric breakdown voltage by connecting it across a DC source causing a current to flow through a charging resistor to the dielectric. The device can be utilized as a radiant energy detector or as a solar energy cell.

  20. Converting environmental documentation to management information

    Energy Technology Data Exchange (ETDEWEB)

    Larsen, M.J.; Frentz, H.J. [Tracor Technology Resources, Inc., Rockville, MD (United States)

    1996-12-01

    The growth of environmental, health, and safety regulations and their reporting requirements has been extraordinary. Penalties for missteps in environmental documentation also grow more serious. Every major piece of environmental legislation requires facilities to collect data and maintain records, in many cases detailed records for long periods of time, on raw materials, processes, emissions, events, personnel, and many other facets of business operations. Unfortunately, for some organizations, the collection of data that satisfies regulatory requirements is an end in itself. Data acquired in this manner may result in little useful information that managers can use to foster their business goals. For organizations of any appreciable size, the volume of environmental data, in manual form, makes analysis difficult to impossible. Too often, data resides in disparate databases, in different locations, and within incompatible information management systems. This paper discusses converting these disparate databases into a useful system.

  1. Processing deficits in monitoring analog and digital displays: Implications for attentional theory and mental-state estimation research

    Science.gov (United States)

    Payne, David G.; Gunther, Virginia A. L.

    1988-01-01

    Subjects performed short term memory tasks, involving both spatial and verbal components, and a visual monitoring task involving either analog or digital display formats. These two tasks (memory vs. monitoring) were performed both singly and in conjunction. Contrary to expectations derived from multiple resource theories of attentional processes, there was no evidence that when the two tasks involved the same cognitive codes (i.e., either both spatial or both verbal/linguistics) there was more of a dual task performance decrement than when the two tasks employed different cognitive codes/processes. These results are discussed in terms of their implications for theories of attentional processes and also for research in mental state estimation.

  2. Design of High-Voltage Switch-Mode Power Amplifier Based on Digital-Controlled Hybrid Multilevel Converter

    Directory of Open Access Journals (Sweden)

    Yanbin Hou

    2016-01-01

    Full Text Available Compared with conventional Class-A, Class-B, and Class-AB amplifiers, Class-D amplifier, also known as switching amplifier, employs pulse width modulation (PWM technology and solid-state switching devices, capable of achieving much higher efficiency. However, PWM-based switching amplifier is usually designed for low-voltage application, offering a maximum output voltage of several hundred Volts. Therefore, a step-up transformer is indispensably adopted in PWM-based Class-D amplifier to produce high-voltage output. In this paper, a switching amplifier without step-up transformer is developed based on digital pulse step modulation (PSM and hybrid multilevel converter. Under the control of input signal, cascaded power converters with separate DC sources operate in PSM switch mode to directly generate high-voltage and high-power output. The relevant topological structure, operating principle, and design scheme are introduced. Finally, a prototype system is built, which can provide power up to 1400 Watts and peak voltage up to ±1700 Volts. And the performance, including efficiency, linearity, and distortion, is evaluated by experimental tests.

  3. Radiation tests on commercial instrumentation amplifiers, analog switches & DAC's

    CERN Document Server

    Agapito, J A; Cardeira, F M; Casas, C; Fernandes, A; Franco, F J; Gomes, P; Gonçalves, I C; Cachero, A H; Lozano-Bahilo, J; Marques, J G; Paz, A; Prata, M J; Ramalho, A J G; Rodríguez-Ruiz, M A; Santos, J P; Vieira, A

    2001-01-01

    A study of several commercial instrumentation amplifiers (INA110, INA111, INA114, INA116, INA118 & INA121) under neutron and vestigial gamma radiation was done. Some parameters (Gain, input offset voltage, input bias currents) were measured on-line and bandwidth, and slew rate were determined before and after radiation. The results of the testing of some voltage references REF102 and ADR290GR and the DG412 analog switch are shown. Finally, different digital-to-analog converters were tested under radiation. (6 refs).

  4. Noise and Spurious Tones Management Techniques for Multi-GHz RF-CMOS Frequency Synthesizers Operating in Large Mixed Analog-Digital SOCs

    Directory of Open Access Journals (Sweden)

    Maxim Adrian

    2006-01-01

    Full Text Available This paper presents circuit techniques and power supply partitioning, filtering, and regulation methods aimed at reducing the phase noise and spurious tones in frequency synthesizers operating in large mixed analog-digital system-on-chip (SOC. The different noise and spur coupling mechanisms are presented together with solutions to minimize their impact on the overall PLL phase noise performance. Challenges specific to deep-submicron CMOS integration of multi-GHz PLLs are revealed, while new architectures that address these issues are presented. Layout techniques that help reducing the parasitic noise and spur coupling between digital and analog blocks are described. Combining system-level and circuit-level low noise design methods, low phase noise frequency synthesizers were achieved which are compatible with the demanding nowadays wireless communication standards.

  5. New drive converter and digital control for the pulsed power supply system of ASDEX Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Käsemann, Claus-Peter, E-mail: c.p.kaesemann@ipp.mpg.de [Max Planck Institute for Plasma Physics, Boltzmannstraße 2, 85748 Garching (Germany); Jacob, Christian; Nguyen, Hong Ha; Stobbe, Ferdinand; Mayer, Alois [Max Planck Institute for Plasma Physics, Boltzmannstraße 2, 85748 Garching (Germany); Sachs, Edgar; Klein, Reiner [Siemens AG, Industrial Automation Systems, Gleiwitzer Straße 555, 90475 Nürnberg (Germany)

    2015-10-15

    Highlights: • IGBT converter system with integrated control. • Proven technology reduces time and budget. • Flexibility to be integrated into a 35 years old installation. • Stable control algorithms for static and dynamic speed control. • Possibilities for active and reactive power management. - Abstract: Safety and reliability are major issues for the ASDEX Upgrade (AUG) pulsed power supply systems. To avoid long downtimes during an experimental campaign, fault-prone components have to be identified and treated early. This becomes even more important due to the AUG participation in the EUROfusion Medium Sized Tokamak (MST) program. Operating equipment which is up to 40 years old adds additional complications. This contribution describes one such example where a 35 year old flywheel generator at AUG was identified as fault-prone and pre-emptively upgraded with a new drive converter with integrated control. Most challenging was to adapt a modern converter, originally designed for wind turbines, toward a drive system for a flywheel-motor-generator system. To identify the layout of the controller and the control parameters, accurate modeling and comprehensive simulations were performed. This effort paid off during commissioning and measuring results verified the calculated design values. Finally, the system shows good performance during AUG plasma experiments.

  6. A Probabilistic Approach to Pronunciation by Analogy

    CERN Document Server

    Kujala, Janne V

    2011-01-01

    The relationship between written and spoken words is convoluted in languages with a deep orthography such as English and therefore it is difficult to devise explicit rules for generating the pronunciations for unseen words. Pronunciation by analogy (PbA) is a data-driven method of constructing pronunciations for novel words from concatenated segments of known words and their pronunciations. PbA performs relatively well with English and outperforms several other proposed methods. However, the best published word accuracy of 65.5% (for the 20,000 word NETtalk corpus) suggests there is much room for improvement in it. Previous PbA algorithms have used several different scoring strategies such as the product of the frequencies of the component pronunciations of the segments, or the number of different segmentations that yield the same pronunciation, and different combinations of these methods, to evaluate the candidate pronunciations. In this article, we instead propose to use a probabilistically justified scorin...

  7. An op-amp gain error-compensated SC cyclic D/A converter converting from least significant bit

    OpenAIRE

    加藤, 卓; 松本, 寛樹

    2011-01-01

    In this paper, we propose a switched-capacitor (SC) cyclic digital-to-analog converter (DAC) which compensate for the gain error and the offset voltage of operational amplifier (op-amp). The DAC convert from least significant bit (LSB). Even when the gain of op-amp is poor, compensated circuit can keep up a resolution. Circuit operation is evaluated on SIMetrix. An error analysis presented that shows an accuracy greater than 8-bits, where amplifier gain is 60 dB.

  8. Power quality improvement by using multi-pulse AC-DC converters for DC drives: Modeling, simulation and its digital implementation

    Directory of Open Access Journals (Sweden)

    Mohd Tariq

    2014-12-01

    Full Text Available The paper presents the modeling, simulation and digital implementation of power quality improvement of DC drives by using multi pulse AC–DC converter. As it is a well-known fact that power quality determines the fitness of electrical power to consumer devices, hence an effort has been made to improve power quality in this work. Simulation and digital implementation with the help of MATLAB/Simulink has been done and results obtained are discussed in detail to verify the theoretical results. The multipulse converter was connected with DC drives and was run at no load condition to find out the transient and steady state performances. FFT analysis has been performed and Total Harmonic Distortion (THD results obtained at different pulses are shown here.

  9. A low-resolution, GSa/s streaming digitizer for a correlation-based trigger system

    CERN Document Server

    Nishimura, Kurtis; Cao, Zhe; Cooney, Michael; Gorham, Peter; Macchiarulo, Luca; Ritter, Lisa; Romero-Wolf, Andres; Varner, Gary

    2012-01-01

    Searches for radio signatures of ultra-high energy neutrinos and cosmic rays could benefit from improved efficiency by using real-time beamforming or correlation triggering. For missions with power limitations, such as the ANITA-3 Antarctic balloon experiment, full speed high resolution digitization of incoming signals is not practical. To this end, the University of Hawaii has developed the Realtime Independent Three-bit Converter (RITC), a 3-channel, 3-bit, streaming analog-to-digital converter implemented in the IBM-8RF 0.13 um process. RITC is primarily designed to digitize broadband radio signals produced by the Askaryan effect, and thus targets an analog bandwidth of >1 GHz, with a sample-and-hold architecture capable of storing up to 2.6 gigasamples-per-second. An array of flash analog-to-digital converters perform 3-bit conversion of sets of stored samples while acquisition continues elsewhere in the sampling array. A serial interface is provided to access an array of on chip digital-to-analog convert...

  10. High performance printed N and P-type OTFTs enabling digital and analog complementary circuits on flexible plastic substrate

    Science.gov (United States)

    Jacob, S.; Abdinia, S.; Benwadih, M.; Bablet, J.; Chartier, I.; Gwoziecki, R.; Cantatore, E.; van Roermund, A. H. M.; Maddiona, L.; Tramontana, F.; Maiellaro, G.; Mariucci, L.; Rapisarda, M.; Palmisano, G.; Coppard, R.

    2013-06-01

    This paper presents a printed organic complementary technology on flexible plastic substrate with high performance N and P-type Organic Thin Film Transistors (OTFTs), based on small-molecule organic semiconductors in solution. Challenges related to the integration of both OTFT types in a common complementary flow are addressed, showing the importance of surface treatments. Stability on single devices and on an elementary complementary digital circuit (ring oscillator) is studied, demonstrating that a robust and reliable flow with high electrical performances can be established for printed organic devices. These devices are used to manufacture several analog and digital building blocks. The design is carried out using a model specifically developed for this technology, and taking into account the parametric variability. High-frequency measurements of printed envelope detectors show improved speed performance, resulting from the high mobility of the OTFTs. In addition, a compact dynamic flip-flop and a low-offset comparator are demonstrated, thanks to availability of both n-type and p-type OTFTs in the technology. Measurement results are in good agreement with the simulations. The circuits presented establish a complete library of building blocks for the realization of a printed RFID tag.

  11. Analog circuit design

    CERN Document Server

    Dobkin, Bob

    2012-01-01

    Analog circuit and system design today is more essential than ever before. With the growth of digital systems, wireless communications, complex industrial and automotive systems, designers are being challenged to develop sophisticated analog solutions. This comprehensive source book of circuit design solutions aids engineers with elegant and practical design techniques that focus on common analog challenges. The book's in-depth application examples provide insight into circuit design and application solutions that you can apply in today's demanding designs. <

  12. A nanoscale linear-to-linear motion converter of graphene.

    Science.gov (United States)

    Dai, Chunchun; Guo, Zhengrong; Zhang, Hongwei; Chang, Tienchong

    2016-08-14

    Motion conversion plays an irreplaceable role in a variety of machinery. Although many macroscopic motion converters have been widely used, it remains a challenge to convert motion at the nanoscale. Here we propose a nanoscale linear-to-linear motion converter, made of a flake-substrate system of graphene, which can convert the out-of-plane motion of the substrate into the in-plane motion of the flake. The curvature gradient induced van der Waals potential gradient between the flake and the substrate provides the driving force to achieve motion conversion. The proposed motion converter may have general implications for the design of nanomachinery and nanosensors.

  13. Image processing to optimize wave energy converters

    Science.gov (United States)

    Bailey, Kyle Marc-Anthony

    The world is turning to renewable energies as a means of ensuring the planet's future and well-being. There have been a few attempts in the past to utilize wave power as a means of generating electricity through the use of Wave Energy Converters (WEC), but only recently are they becoming a focal point in the renewable energy field. Over the past few years there has been a global drive to advance the efficiency of WEC. Placing a mechanical device either onshore or offshore that captures the energy within ocean surface waves to drive a mechanical device is how wave power is produced. This paper seeks to provide a novel and innovative way to estimate ocean wave frequency through the use of image processing. This will be achieved by applying a complex modulated lapped orthogonal transform filter bank to satellite images of ocean waves. The complex modulated lapped orthogonal transform filterbank provides an equal subband decomposition of the Nyquist bounded discrete time Fourier Transform spectrum. The maximum energy of the 2D complex modulated lapped transform subband is used to determine the horizontal and vertical frequency, which subsequently can be used to determine the wave frequency in the direction of the WEC by a simple trigonometric scaling. The robustness of the proposed method is provided by the applications to simulated and real satellite images where the frequency is known.

  14. A parallel unbalanced digitization architecture to reduce the dynamic range of multiple signals

    Science.gov (United States)

    Vallérian, Mathieu; HuÅ£u, Florin; Villemaud, Guillaume; Miscopein, Benoît; Risset, Tanguy

    2016-05-01

    Technologies employed in urban sensor networks are permanently evolving, and thus the gateways employed to collect data in such kind of networks have to be very flexible in order to be compliant with the new communication standards. A convenient way to do that is to digitize all the received signals in one shot and then to digitally perform the signal processing, as it is done in software-defined radio (SDR). All signals can be emitted with very different features (bandwidth, modulation type, and power level) in order to respond to the various propagation conditions. Their difference in terms of power levels is a problem when digitizing them together, as no current commercial analog-to-digital converter (ADC) can provide a fine enough resolution to digitize this high dynamic range between the weakest possible signal in the presence of a stronger signal. This paper presents an RF front end receiver architecture capable of handling this problem by using two ADCs of lower resolutions. The architecture is validated through a set of simulations using Keysight's ADS software. The main validation criterion is the bit error rate comparison with a classical receiver.

  15. Editoração científica: as duas faces - analógica e digital Scientific publishing: the two faces - analogic and digital

    Directory of Open Access Journals (Sweden)

    Carlos Teixeira Brandt

    2004-12-01

    Full Text Available A Associação Brasileira de Editores Científicos (ABEC promoveu, em setembro de 2004, o III Workshop de Editores Científicos em Recife. O enfoque principal foi sobre a forma de divulgação do conhecimento científico: analógico ou digital. Contudo, foram também discutidas as formas de financiamento da produção e divulgação desse conhecimento. A importância maior na produção do conhecimento esteve associada aos institutos de pesquisa, as universidades e as sociedades científicas. Tem sido observada uma tendência ao aumento no gerenciamento eletrônico da editoração e a informatização da divulgação; sobretudo pelo menor custo e maior facilidade; se os recursos humanos das ciências da informação estiverem disponíveis, todavia, a convivência da formatação analógica e digital é esperada por bastante tempo. Foi apresentada a idéia de um sítio eletrônico dos editores, com certificação digital, para que os autores da produção do conhecimento pudessem, com mais facilidade enviar os seus manuscritos. A seleção pelo corpo editorial das revistas desses manuscritos e a participação do corpo editorial na orientação da elaboração dos mesmos foi enfatizada. Essa atitude poderia aumentar a publicação do conhecimento produzido, particularmente daquele advindo dos programas de pós-graduação das universidades. Durante todo o evento ficou evidente a essencialidade da produção do conhecimento como elemento básico de evolução da própria sociedade humana.The Brazilian Association for the Scientific Editors (ABEC promoted in September, 2004, the III Workshop for the Scientific Editors in Recife, Pernambuco - Brazil. The main focus was in the way that the scientific knowledge needs to be spread out : analogical or digital. However, the financial support for the production and the divulgation of this knowledge was also discussed. In the production it was agreed that it is made in the research institutes; universities

  16. The Politics of Mass Digitization

    DEFF Research Database (Denmark)

    Thylstrup, Nanna Bonde

    Mass-digitization of cultural-heritage archives has become increasingly pervasive. From Google Books to Europeana, bounded material is converted into ephemeral data on an unprecedented scale, promising to provide mankind with readily accessible and enduring reservoirs of knowledge. Interrogating...... this phenomenon, this dissertation asks how mass digitization affects the politics of cultural heritage. Its central argument is that mass digitization of cultural heritage is neither a neutral technical process, nor a transposition of the politics of analog cultural heritage to the digital realm on a 1:1 scale....... Rather, it should be understood as distinct subpolitical processes that bring together a multiplicity of interests and actors hitherto foreign to the field of cultural heritage archives. Mass digitization is thus upheaving the disciplinary enclosures of cultural heritage and gives rise to new territorial...

  17. A Mixed Analog-Digital Radiation Hard Technology for High Energy Physics Electronics: DMILL~(Durci~Mixte~sur~Isolant~Logico-Lineaire)

    CERN Multimedia

    Lugiez, F; Leray, J; Rouger, M; Fourches, N T; Musseau, O; Potheau, R

    2002-01-01

    %RD29 %title\\\\ \\\\Physics experiments under preparation with the future LHC require a fast, low noise, very rad-hard (>10 Mrad and >10$^{14}$ neutron/cm$^{2}$), mixed analog-digital microelectronics VLSI technology.\\\\ \\\\The DMILL microelectronics technology (RD29) was developed between 1990 and 1995 by a Consortium gathering the CEA and the firm Thomson-TCS, with the collaboration of IN2P3. The goal of the DMILL program, which is now completed, was to provide the High Energy Physics community, space industry, nuclear industry, and other applications, with an industrial very rad-hard mixed analog-digital microelectronics technology.\\\\ \\\\DMILL integrates mixed analog-digital very rad-hard (>10 Mrad and >10$^{14}$ neutron/cm$^{2}$) vertical bipolar, 0.8 $\\mu$m CMOS and 1.2 $\\mu$m PJFET transistors. Its SOI substrate and its dielectric trenches strongly reduce SEU sensitivity and completely eliminate any possibility of latch-up. Its four transistors are optimized to obtain low-noise features. DMILL also integrates...

  18. A FAST FOREGROUND DIGITAL CALIBRATION TECHNIQUE FOR PIPELINED ADC

    Institute of Scientific and Technical Information of China (English)

    Wang Yu; Yang Haigang; Cheng Xin; Liu Fei; Yin Tao

    2012-01-01

    Digital calibration techniques are widely developed to cancel the non-idealities of the pipelined Analog-to-Digital Converters (ADCs).This letter presents a fast foreground digital calibration technique based on the analysis of error sources which influence the resolution of pipelined ADCs.This method estimates the gain error of the ADC prototype quickly and calibrates the ADC simultaneously in the operation time.Finally,a 10 bit,100 Ms/s pipelined ADC is implemented and calibrated.The simulation results show that the digital calibration technique has its efficiency with fewem operation cycles.

  19. Choosing to convert to critical access hospital status.

    Science.gov (United States)

    Dalton, Kathleen; Slifkin, Rebecca; Poley, Stephanie; Fruhbeis, Melissa

    2003-01-01

    The authors profile facilities converting to critical access hospitals (CAHs) from 1998-2000, comparing characteristics of their communities, operations, and finances to those of other small rural providers. Counties where CAHs are located are more sparsely populated, but do not have substantially different sociodemographic profiles than other rural counties. Converting hospitals' acute daily census averaged well below the statutory limit of 15, but over one-half reduced unused bed capacity to meet CAH size limitations. The average case-mix adjusted Medicare cost per case was 16-percent higher for CAH converters than for other small hospitals and their financial ratios were substantially worse, although many other operating characteristics were similar.

  20. Broad-Bandwidth FPGA-Based Digital Polyphase Spectrometer

    Science.gov (United States)

    Jamot, Robert F.; Monroe, Ryan M.

    2012-01-01

    With present concern for ecological sustainability ever increasing, it is desirable to model the composition of Earth s upper atmosphere accurately with regards to certain helpful and harmful chemicals, such as greenhouse gases and ozone. The microwave limb sounder (MLS) is an instrument designed to map the global day-to-day concentrations of key atmospheric constituents continuously. One important component in MLS is the spectrometer, which processes the raw data provided by the receivers into frequency-domain information that cannot only be transmitted more efficiently, but also processed directly once received. The present-generation spectrometer is fully analog. The goal is to include a fully digital spectrometer in the next-generation sensor. In a digital spectrometer, incoming analog data must be converted into a digital format, processed through a Fourier transform, and finally accumulated to reduce the impact of input noise. While the final design will be placed on an application specific integrated circuit (ASIC), the building of these chips is prohibitively expensive. To that end, this design was constructed on a field-programmable gate array (FPGA). A family of state-of-the-art digital Fourier transform spectrometers has been developed, with a combination of high bandwidth and fine resolution. Analog signals consisting of radiation emitted by constituents in planetary atmospheres or galactic sources are downconverted and subsequently digitized by a pair of interleaved analog-to-digital converters (ADCs). This 6-Gsps (gigasample per second) digital representation of the analog signal is then processed through an FPGA-based streaming fast Fourier transform (FFT). Digital spectrometers have many advantages over previously used analog spectrometers, especially in terms of accuracy and resolution, both of which are particularly important for the type of scientific questions to be addressed with next-generation radiometers.

  1. High-Precision Hysteresis Sensing of the Quartz Crystal Inductance-to-Frequency Converter

    Science.gov (United States)

    Matko, Vojko; Milanović, Miro

    2016-01-01

    A new method for the automated measurement of the hysteresis of the temperature-compensated inductance-to-frequency converter with a single quartz crystal is proposed. The new idea behind this method is a converter with two programmable analog switches enabling the automated measurement of the converter hysteresis, as well as the temperature compensation of the quartz crystal and any other circuit element. Also used is the programmable timing control device that allows the selection of different oscillating frequencies. In the proposed programmable method two different inductances connected in series to the quartz crystal are switched in a short time sequence, compensating the crystal’s natural temperature characteristics (in the temperature range between 0 and 50 °C). The procedure allows for the measurement of the converter hysteresis at various values of capacitance connected in parallel with the quartz crystal for the converter sensitivity setting at selected inductance. It, furthermore, enables the measurement of hysteresis at various values of inductance at selected parallel capacitance (sensitivity) connected to the quartz crystal. The article shows that the proposed hysteresis measurement of the converter, which converts the inductance in the range between 95 and 100 μH to a frequency in the range between 1 and 200 kHz, has only 7 × 10−13 frequency instability (during the temperature change between 0 and 50 °C) with a maximum 1 × 10−11 hysteresis frequency difference. PMID:27367688

  2. High-Precision Hysteresis Sensing of the Quartz Crystal Inductance-to-Frequency Converter.

    Science.gov (United States)

    Matko, Vojko; Milanović, Miro

    2016-06-28

    A new method for the automated measurement of the hysteresis of the temperature-compensated inductance-to-frequency converter with a single quartz crystal is proposed. The new idea behind this method is a converter with two programmable analog switches enabling the automated measurement of the converter hysteresis, as well as the temperature compensation of the quartz crystal and any other circuit element. Also used is the programmable timing control device that allows the selection of different oscillating frequencies. In the proposed programmable method two different inductances connected in series to the quartz crystal are switched in a short time sequence, compensating the crystal's natural temperature characteristics (in the temperature range between 0 and 50 °C). The procedure allows for the measurement of the converter hysteresis at various values of capacitance connected in parallel with the quartz crystal for the converter sensitivity setting at selected inductance. It, furthermore, enables the measurement of hysteresis at various values of inductance at selected parallel capacitance (sensitivity) connected to the quartz crystal. The article shows that the proposed hysteresis measurement of the converter, which converts the inductance in the range between 95 and 100 μH to a frequency in the range between 1 and 200 kHz, has only 7 × 10(-13) frequency instability (during the temperature change between 0 and 50 °C) with a maximum 1 × 10(-11) hysteresis frequency difference.

  3. Effective number of samples and pseudo-random nonlinear distortions in digital OFDM coded signal

    CERN Document Server

    Rudziński, Adam

    2013-01-01

    This paper concerns theoretical modeling of degradation of signal with OFDM coding caused by pseudo-random nonlinear distortions introduced by an analog-to-digital or digital-to-analog converter. A new quantity, effective number of samples, is defined and used for derivation of accurate expressions for autocorrelation function and the total power of the distortions. The derivation is based on probabilistic model of the signal and its transition probability. It is shown, that for digital (discrete and quantized) signals the effective number of samples replaces the total number of samples and is the proper quantity defining their properties.

  4. Digital I&C systems in nuclear power plants. Risk-screening of environmental stressors and a comparison of hardware unavailability with an existing analog system

    Energy Technology Data Exchange (ETDEWEB)

    Hassan, M.; Vesely, W.E.

    1998-01-01

    In this report, we present a screening study to identify environmental stressors for digital instrumentation and control (I&C) systems in a nuclear power plant (NPP) which can be potentially risk-significant, and compare the hardware unavailability of such a system with that of its existing analog counterpart. The stressors evaluated are temperature, humidity, vibration, radiation, electro-magnetic interference (EMI), and smoke. The results of risk-screening for an example plant, subject to some bounding assumptions and based on relative changes in plant risk (core damage frequency impacts of the stressors), indicate that humidity, EMI from lightning, and smoke can be potentially risk-significant. Risk from other sources of EMI could not be evaluated for a lack of data. Risk from temperature appears to be insignificant as that from the assumed levels of vibrations. A comparison of the hardware unavailability of the existing analog Safety Injection Actuation System (SIAS) in the example plant with that of an assumed digital upgrade of the system indicates that system unavailability may be more sensitive to the level of redundancy in elements of the digital system than to the environmental and operational variations involved. The findings of this study can be used to focus activities relating to the regulatory basis for digital I&C upgrades in NPPs, including identification of dominant stressors, data-gathering, equipment qualification, and requirements to limit the effects of environmental stressors. 30 refs., 8 figs., 26 tabs.

  5. 基于数模混合的混沌映射实现∗%Chaotic map implementation based on digital-analog hybrid metho d

    Institute of Scientific and Technical Information of China (English)

    党小宇; 李洪涛; 袁泽世; 胡文

    2015-01-01

    混沌随机序列发生器在数字实现时面临有限字长效应,无法严格保证伪随机序列的非周期性。构建了一类包含最少模拟器件的新数模混合系统,分析比较了此类系统的非线性动力学行为。利用现场可编程逻辑门阵列和RC电路实现了混沌映射,构造了稳定的高速随机序列发生器,可产生100 Gbit/s以上速率的随机数。研究表明,数模混合系统的混沌性对元件参数变化不敏感,数模实现验证了新系统的存在性和物理上的可实现性。系统易于集成在数字加密、保密通信和雷达波形产生等应用系统中。%Random number generator plays an important role in many domains, including secret communication, radar wave-form generation, etc. However, the existing methods for generating random numbers cannot meet the actual demand for speed. Even worse, the use of analog device will restrict the speed of generator and robustness of system. As a result, researchers start to turn their eyes to digital implementation which is stabler and more efficient than the analog counterpart. Unfortunately, digital methods still have the disadvantages of dynamical degradation because of word length limitation effect. Though some remedies, such as increasing computing precision, cascading multiple chaotic sys-tems, pseudo-randomly perturbing the chaotic system, the switching multiple chaotic systems and error compensation method are proposed, but the limitations are still inevitable. In recent researches, continuous-time chaotic oscillators are used with digital devices to realize random number generator, and a new approach is proposed to solve the dynamical degradation of digital chaotic system by coupling the given digital chaotic map with an analog chaotic system, where the analog chaotic system is applied to anti-control the given digital chaotic map. However, this method also requires a whole continuous-time system realized with analog devices

  6. The Application on Analog-digital Mixed ADC Design for 60 GHz Microwave Wireless Communication System%一种应用于60GHz毫米波无线传输系统的数模混合ADC设计

    Institute of Scientific and Technical Information of China (English)

    冯晓东; 马骏

    2011-01-01

    A novel analog-digital mixed signal processing ADC architecture is proposed for 60 GHz high speed wireless communication system. An analog-digtial mixed equalizer is designed in this architeture to minimize the precision requirement of ADC in frequency selective fading channel. This architecure can reduce the precision requirement of 2 btis with no performance loss in receiver at the price of one extra DAC module. Simulation results show that the analog-digital mixed ADC design have the advantages in the performace of BER and convergence speed. Furthermore, this ADC architecture is optimized by converting the most significant bit to analog domain. This method can reduce the precision requirement of the extra DAC to (2 ~ 3 ) bits. That will further reduce the complexity and power consumption in ADC design.%以60 GHz毫米波高速无线传输系统为背景,对无线信号历经的频率选择性衰落信道进行了深入分析,并对接收机结构进行研究.提出一种利用数模信号混合处理的低复杂度ADC结构.该结构利用数模混合均衡器来降低频率选择性衰落信道中接收机ADC的精度要求.通过引入一个高精度、高采样率的DAC为代价,在不改变接收机性能的情况下将ADC的采样精度降低2个比特.该ADC均衡器在误码率、收敛速度等性能上相比同精度的全数字均衡器有很大提高.进一步,对该结构进行优化.通过把补偿信号的高比特位的值转换到模拟域,将引入的DAC精度降低到2~3个比特,从而进一步降低了该结构的设计复杂度和功耗.

  7. Introduction to digital communication systems

    CERN Document Server

    Wesolowski, Krzysztof

    2009-01-01

    Combining theoretical knowledge and practical applications, this advanced-level textbook covers the most important aspects of contemporary digital communication systems. Introduction to Digital Communication Systems focuses on the rules of functioning digital communication system blocks, starting with the performance limits set by the information theory. Drawing on information relating to turbo codes and LDPC codes, the text presents the basic methods of error correction and detection, followed by baseband transmission methods, and single- and multi-carrier digital modulations. The basi

  8. Adaptive Digital Calibration of Amplifier Finite Gain Effects and C-ratio Matching Errors for MASH Modulators

    Institute of Scientific and Technical Information of China (English)

    Feng Hui(冯晖); Lin Zhenghui

    2004-01-01

    Cascaded sigma-delta (MASH) modulators for higher order oversampled analog-to-digital conversion rely on precise matching of contributions from different quantizers to cancel lower order quantization noise from intermediate delta-sigma stages. This paper studies the effect of analog imperfections in the implementation, such as finite gain of the amplifiers and capacitor ratio mismatch, and presents an adaptive algorithm and implementation architectures for digital correction of such analog imperfections. Behavioral simulations on 1-1-1 oversampled converters demonstrate over 10dB improvements in signal-to-noise and over 20 dB improvements in dynamic range performance.

  9. Switching power converters medium and high power

    CERN Document Server

    Neacsu, Dorin O

    2013-01-01

    An examination of all of the multidisciplinary aspects of medium- and high-power converter systems, including basic power electronics, digital control and hardware, sensors, analog preprocessing of signals, protection devices and fault management, and pulse-width-modulation (PWM) algorithms, Switching Power Converters: Medium and High Power, Second Edition discusses the actual use of industrial technology and its related subassemblies and components, covering facets of implementation otherwise overlooked by theoretical textbooks. The updated Second Edition contains many new figures, as well as

  10. Enhancing analog seismic data resolution using the A/D converter: Examples of Sicilia Channel and Marmara Sea data set

    Science.gov (United States)

    Alp, H.

    2015-12-01

    We present here two data set composed of about 20 multichannel seismic data profiles, for a total of 1102 km of data acquired in the Sicilia Channel in Italy and Marmara Sea in Turkey. The data set of Multichannel seismic reflection profiles and well information acquired for commercial purpose by oil companies in the 1970's and 1980's. All profiles in Sicilia Channel, which are available on .pdf files were downloaded from VIDEPI website. Other profiles in Marmara Sea were taken from Turkish Petroleum Corporation. The first step was to convert the graphic files SEG-Y format files, using SeisTrans® software. Due to the great inhomogeneity of the various seismic lines, which have been recorded from different companies with different acquisition parameters, it has been necessary a great job of homogenization and noise reduction through the use of adequate band-pass filters. Then, for each reconstructed seismic line, SEG-Y header editing was necessary in order to assign the CDP (common-depth-points) and the SP (shot points) to the corresponding geographic coordinates. The SEG-Y files so created were uploaded and archived into a project using the Kingdom Suite® seismic package. To perform the calibration of seismic data with the stratigraphic wells, the classic problem is to identify on seismic profiles the reflections corresponding to the lithological variations identified in the wells. This is because the vertical scale of the seismic data is expressed in time, while that of the wells is expressed in meters. The main unknown is then the sound velocity within the different lithologies. In order to better correlate real data reflections with the corresponding stratigraphic discontinuities, synthetic seismogram have been created from the reflectivity series obtained through acoustic impedance calculations. They represent an example of forward modeling to match as closely as possible the real seismic data.

  11. An iconic, analogical approach to grammaticalization

    NARCIS (Netherlands)

    Fischer, O.; Conradie, C.J.; Johl, R.; Beukes, M.; Fischer, O.; Ljungberg, C.

    2010-01-01

    This paper addresses a number of problems connected with the ‘apparatus’ used in grammaticalization theory. It will be argued that we get a better grip on what happens in processes of grammaticalization (and its ‘opposite’, lexicalization) if the process is viewed in terms of analogical processes, w

  12. All-Digital ADC Design in 65 nm CMOS Technology

    OpenAIRE

    Pathapati, Srinivasa Rao

    2014-01-01

    The design of analog and complex mixed-signal circuits in a deep submicron CMOS process technology is a big challenge. This makes it desirable to shift data converter design towards the digital domain. The advantage of using a fully digital ADC design rather than a traditional analog ADC design is that the circuit is defined by an HDL description and automatically synthesized by tools. It offers low power consumption, low silicon area and a fully optimized gate-level circuit that reduces the ...

  13. Analog circuit design a tutorial guide to applications and solutions

    CERN Document Server

    Williams, Jim

    2011-01-01

    * Covers the fundamentals of linear/analog circuit and system design to guide engineers with their design challenges. * Based on the Application Notes of Linear Technology, the foremost designer of high performance analog products, readers will gain practical insights into design techniques and practice. * Broad range of topics, including power management tutorials, switching regulator design, linear regulator design, data conversion, signal conditioning, and high frequency/RF design. * Contributors include the leading lights in analog design, Robert Dobkin, Jim Willia

  14. Analog preprocessing in a SNS 2 micrometers low-noise CMOS folding ADC

    Science.gov (United States)

    Carr, Richard D.

    1994-12-01

    Significant research in high performance analog-to-digital converters (ADC's) has been directed at retaining part of the high-speed flash ADC architecture, while reducing the total number of comparators in the circuit. The symmetrical number system (SNS) can be used to preprocess the analog input signal, reducing the number of comparators and thus reducing the chip area and power consumption of the ADC. This thesis examines a Very Large Scale Integrated (VLSI) design for a folding circuit for a SNS analog preprocessing architecture in a 9-bit folding ADC with a total of 23 comparators. The analog folding circuit layout uses the Orbit 2 micrometers CMOS N-well double-metal, double-poly low-noise analog process. The effects of Spice level 2 parameter tolerances during fabrication on the operation of the folding circuit are investigated numerically. The frequency response of the circuit is also quantified. An Application Specific Integrated Circuit (ASIC) is designed.

  15. Short term wave forecasting, using digital filters, for improved control of Wave Energy Converters

    DEFF Research Database (Denmark)

    Tedd, James; Frigaard, Peter

    2007-01-01

    experimentally. Results are shown form measurements taken on the Wave Dragon prototype device, a floating overtopping device situated in Northern Denmark. In this case the method is able to accurately predict the surface elevation at the device 11.2 seconds before the measurement is made. This is sufficient......This paper presents a Digital Filter method for real time prediction of waves incident upon a Wave Energy device. The method transforms waves measured at a point ahead of the device, to expected waves incident on the device. The relationship between these incident waves and power capture is derived...

  16. A contribution to the design of fast code converters for position encoders

    Science.gov (United States)

    Denic, Dragan B.; Dincic, Milan R.; Miljkovic, Goran S.; Peric, Zoran H.

    2016-10-01

    Pseudorandom binary sequences (PRBS) are very useful in many areas of applications. Absolute position encoders based on PRBS have many advantages. However, the pseudorandom code is not directly applicable to the digital electronic systems, hence a converter from pseudorandom to natural binary code is needed. Recently, a fast pseudorandom/natural code converter based on Galois PRBS generator (much faster than previously used converter based on Fibonacci PRBS generator) was proposed. One of the main parts of the Galois code converter is an initial logic. The problem of the design of the initial logic has been solved only for some single values of resolution, but it is still not solved for any value of resolution, which significantly limits the applicability of the fast Galois code converter. This paper solves this problem presenting the solution for the design of the initial logic of the fast Galois pseudorandom/natural code converters used in the pseudorandom position encoders, in general manner, that is for any value of the resolution, allowing for a wide applicability of the fast Galois pseudorandom position encoders. Rigorous mathematical derivation of the formula for the designing of the initial logic is presented. Simulation of the proposed converter is performed in NI MultiSim software. The proposed solution, although developed for pseudorandom position encoders, can be used in many other fields where PRBS are used.

  17. Evaluation and optimization of the bandwidth of static converters: application to multi-cell converters; Evaluation et optimisation de la bande passante des convertisseurs statiques

    Energy Technology Data Exchange (ETDEWEB)

    Aime, M.

    2003-11-15

    Thanks to the technological progress achieved in the field of power electronics, the use of static converters has spread to new applications. In particular, some applications such as active filtering or the supply of special AC machines require power converters having good dynamic performances. The subject of this thesis is to evaluate systematically the dynamic performances of multi-cell converters, and then to optimize these performances. This document is organized in four chapters. The first one summarizes the main multilevel converter structures, and some control strategies dedicated to these structures. The second chapter presents the evaluation criteria chosen to quantify the dynamic performances of static converters. These criteria are then used to compare the performances obtained with two different PWM strategies. An optimized strategy which results from a trade-off between the two former strategies is then introduced. The third chapter shows a new control strategy of multi-cell voltage source converters. This new strategy enables to control the peak current at a fixed switching frequency. The operation of this controller is explained, and the results obtained by digital simulations are presented and discussed. The fourth chapter deals with the experimental achievement of the peak current control. In particular, the implementation of the control algorithm within a FPGA is demonstrated. Finally, the conclusion of this thesis presents some orientations for further developments, in order to improve the current control strategy and to widen its field of applications. (author)

  18. Design of a MGy radiation tolerant resolver-to-digital convertor IC for remotely operated maintenance in harsh environments

    Energy Technology Data Exchange (ETDEWEB)

    Leroux, Paul, E-mail: paul.leroux@kuleuven.be [KU Leuven, Dept. of Electrical Engineering (ESAT), AdvISe, Kleinhoefstraat 4, 2440 Geel (Belgium); Van Koeckhoven, Wesley; Verbeeck, Jens [KU Leuven, Dept. of Electrical Engineering (ESAT), AdvISe, Kleinhoefstraat 4, 2440 Geel (Belgium); Van Uffelen, Marco; Esqué, Salvador; Ranz, Roberto; Damiani, Carlo [Fusion for Energy, Torres Diagonal Litoral B3, Josep Pla 2, 08019 Barcelona (Spain); Hamilton, David [ITER Organization, Route de Vinon sur Verdon, 13115 Saint Paul-lez-Durance (France)

    2014-10-15

    During future ITER maintenance operations, sensors and their embarked electronics will be exposed to a hostile and radioactive environment. This paper presents the design of a MGy radiation tolerant 16 bit resolver-to-digital converter (RDC) in 130 nm CMOS technology. The RDC features a Type II digital tracking loop, able to track resolvers with speeds up to 300 rps, and excitation frequencies up to 4 kHz. The RDC uses two integrated ΔΣ-analog-to-digital converters (ADCs) to digitize the resolver outputs. The 16 bit, 10 kHz ADCs utilize a correlated double sampling technique to remove radiation induced offset and 1/f-noise. The front-end features a static angular resolution of 16 bits (4.2 arcsec{sub rms}) and a resolution of 10 bits (6 arcmin{sub rms}) at a rotor speed of 100 rps. The circuit has a simulated radiation tolerance exceeding 1 MGy. It has the ability to operate under temperatures up to 125 °C, and to allow multiplexing with signals from other conventional sensors for compact, robust read-out architectures.

  19. Analog of landau Levels to Electric Dipole

    CERN Document Server

    Ribeiro, L R; Nascimento, J R; Furtado, Claudio

    2006-01-01

    In this article we discuss the analogy between the dynamics of a neutral particle with an electric dipole, in the presence of configuration of magnetic field, with Landau level quantization for charged particle. We analyze this quantization based on the He-Mckelar-Wilkens interaction developed of similar way that Ericsson and Sj\\"oqvist[Phys Rev. A {\\bf 65} 013607 (2001)] was analyzed the Landau-Aharonov-Casher effect. The energy level and eingenfuctions and eigenvalues are obtained.

  20. Using Analogies to Prevent Misconceptions about Chemical Equilibrium

    Science.gov (United States)

    Sahin Pekmez, Esin

    2010-01-01

    The main purpose of this study was to find the effectiveness of using analogies to prevent misconceptions about chemical equilibrium. Nineteen analogies, which were based on dynamic aspects of chemical equilibrium and application of Le Chatelier's principle, were developed. The participations of this study consisted of 11th grade students (n: 151)…