WorldWideScience

Sample records for analog to digital converters

  1. Digital to Analog Converter Description

    OpenAIRE

    Tuijl, van, B.A.J.

    2003-01-01

    A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2, 40-n) are used may be changed in different samples. The current sources (40-1, 40-2, 40-n) may be replaced by one bit switched capacitor converters or by inverters connected to one end of a set o...

  2. Optical analog-to-digital converter

    Science.gov (United States)

    Vawter, G. Allen; Raring, James; Skogen, Erik J.

    2009-07-21

    An optical analog-to-digital converter (ADC) is disclosed which converts an input optical analog signal to an output optical digital signal at a sampling rate defined by a sampling optical signal. Each bit of the digital representation is separately determined using an optical waveguide interferometer and an optical thresholding element. The interferometer uses the optical analog signal and the sampling optical signal to generate a sinusoidally-varying output signal using cross-phase-modulation (XPM) or a photocurrent generated from the optical analog signal. The sinusoidally-varying output signal is then digitized by the thresholding element, which includes a saturable absorber or at least one semiconductor optical amplifier, to form the optical digital signal which can be output either in parallel or serially.

  3. Digital to Analog Converter Description

    NARCIS (Netherlands)

    Tuijl, van Adrianus J.M.

    2003-01-01

    A circuit for analogue to digital or digital to analogue conversion comprising at least 2n matched current sources (40-1, 40-2, 40-n), where n is the resolution required of the conversion. Preferably more than 2n current sources (40-1, 40-2, 40-n) are used. The order in which the sources (40-1, 40-2

  4. Analog-digital converters for industrial applications including an introduction to digital-analog converters

    CERN Document Server

    Ohnhäuser, Frank

    2015-01-01

    This book offers students and those new to the topic of analog-to-digital converters (ADCs) a broad introduction, before going into details of the state-of-the-art design techniques for SAR and DS converters, including the latest research topics, which are valuable for IC design engineers as well as users of ADCs in applications. The book then addresses important topics, such as correct connectivity of ADCs in an application, the verification, characterization and testing of ADCs that ensure high-quality end products. Analog-to-digital converters are the central element in any data processing system and regulation loops such as modems or electrical motor drives. They significantly affect the performance and resolution of a system or end product. System development engineers need to be familiar with the performance parameters of the converters and understand the advantages and disadvantages of the various architectures. Integrated circuit development engineers have to overcome the problem of achieving high per...

  5. Superconducting sigma-delta analog-to-digital converter

    International Nuclear Information System (INIS)

    This patent describes a superconducting sigma-delta analog-to-digital converter for converting an analog input signal to a digital output signal. It comprises a superconducting inductor to which the analog input signal is applied to produce an inductor current; a Josephson junction connected in series with the superconducting inductor and through which the inductor current flows; a pulse generator adding sampling current pulses to the inductor current to produce a total current flowing through the Josephson junction; and output means generating from the voltage pulses the digital output signal

  6. High-speed and high-resolution analog-to-digital and digital-to-analog converters

    NARCIS (Netherlands)

    van de Plassche, R.J.

    1989-01-01

    Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog filte

  7. Reference-Free CMOS Pipeline Analog-to-Digital Converters

    CERN Document Server

    Figueiredo, Michael; Evans, Guiomar

    2013-01-01

    This book shows that digitally assisted analog-to-digital converters are not the only way to cope with poor analog performance caused by technology scaling. It describes various analog design techniques that enhance the area and power efficiency without employing any type of digital calibration circuitry. These techniques consist of self-biasing for PVT enhancement, inverter-based design for improved speed/power ratio, gain-of-two obtained by voltage sum instead of charge redistribution, and current-mode reference shifting instead of voltage reference shifting. Together, these techniques allow enhancing the area and power efficiency of the main building blocks of a multiplying digital-to-analog converter (MDAC) based stage, namely, the flash quantizer, the amplifier, and the switched capacitor network of the MDAC. Complementing the theoretical analyses of the various techniques, a power efficient operational transconductance amplifier is implemented and experimentally characterized. Furthermore, a medium-low ...

  8. Time-interleaved analog-to-digital converters

    NARCIS (Netherlands)

    Louwsma, Simon Minze

    2009-01-01

    This thesis describes the feasibility of an analog-to-digital converter (ADC) with a sample-rate of 1-2 GS/s, a resolution of 8-10 bits, and a state-of-the-art power efficiency of less than 1 pJ/conversion step. The time-interleaved architecture exploits parallelism to increase the sample-rate while

  9. High-speed and high-resolution analog-to-digital and digital-to-analog converters

    OpenAIRE

    van de Plassche, R.J.

    1992-01-01

    Analog-to-digital and digital-to-analog converters are important building blocks connecting the analog world of transducers with the digital world of computing, signal processing and data acquisition systems. In chapter two the converter as part of a system is described. Requirements of analog filtering of input signals before they are applied to an A/D converter are defined. In the case of a D/A converter the amount of filtering of the repetitive signal bands around multiples of the sampling...

  10. Design of Low Power Successive Approximation Analog to Digital Converter

    OpenAIRE

    Mr. Jitendra A. Waghmare; Prof. P.M. Ghutke

    2014-01-01

    In Biomedical applications such as pacemaker it becomes mandatory to design the circuits with low power and low voltage to enhance the system by means of long sustainability and less power consumption with maintenance free operation, especially in the circuits like Analog to Digital Converters (ADCs). So here is the selection of right architecture is very crucial. Day by day more and more applications are built on the basis of power consumption so SAR ADC will be useful for me...

  11. Energy Savings Assessment for Digital-to-Analog Converter Boxes

    Energy Technology Data Exchange (ETDEWEB)

    Cheung, Hoi Ying Iris; Meier, Alan; Brown, Richard

    2011-01-18

    The Digital Television (DTV) Converter Box Coupon Program was administered by the U.S. government to subsidize purchases of digital-to-analog converter boxes, with up to two $40 coupons for each eligible household. In order to qualify as Coupon Eligible Converter Boxes (CECBs), these devices had to meet a number of minimum performance specifications, including energy efficiency standards. The Energy Star Program also established voluntary energy efficiency specifications that are more stringent than the CECB requirements. In this study, we measured the power and energy consumptions for a sample of 12 CECBs (including 6 Energy Star labeled models) in-use in homes and estimated aggregate energy savings produced by the energy efficiency policies. Based on the 35 million coupons redeemed through the end of the program, our analysis indicates that between 2500 and 3700 GWh per year are saved as a result of the energy efficiency policies implemented on digital-to-analog converter boxes. The energy savings generated are equivalent to the annual electricity use of 280,000 average US homes.

  12. Penggunaan ADC (Analog to Digital Converter) 0804 Pada Perancangan Sensor Intensitas Cahaya

    OpenAIRE

    Mouammar, Angga

    2010-01-01

    ADC (Analog to Digital Converter) adalah sebuah rangkaian elektronika yang dapat mengubah besaran analog menjadi besaran digital. Pada setiap sensor yang berbasis mikrokontroler (sebagai pusat pengolah data) diperlukan adanya rangkaian ADC (Analog to Digital Converter) untuk mengubah sinyal yang diterima oleh sensor untuk menjadi besaran digital supaya sinyal tersebut bisa diterjemahkan atau dibaca mikrokontroler. Sensor- sensor disini dapat berupa sensor suhu, sensor level,...

  13. Error Models of the Analog to Digital Converters

    Science.gov (United States)

    Michaeli, Linus; Šaliga, Ján

    2014-04-01

    Error models of the Analog to Digital Converters describe metrological properties of the signal conversion from analog to digital domain in a concise form using few dominant error parameters. Knowledge of the error models allows the end user to provide fast testing in the crucial points of the full input signal range and to use identified error models for post correction in the digital domain. The imperfections of the internal ADC structure determine the error characteristics represented by the nonlinearities as a function of the output code. Progress in the microelectronics and missing information about circuital details together with the lack of knowledge about interfering effects caused by ADC installation prefers another modeling approach based on the input-output behavioral characterization by the input-output error box. Internal links in the ADC structure cause that the input-output error function could be described in a concise form by suitable function. Modeled functional parameters allow determining the integral error parameters of ADC. Paper is a survey of error models starting from the structural models for the most common architectures and their linkage with the behavioral models represented by the simple look up table or the functional description of nonlinear errors for the output codes.

  14. Optical-spectrum-encoded analog-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    LIAO Xiao-jun; YANG Ya-pei

    2007-01-01

    A novel optical-spectrum-encoded (OSE) analog-to-digital converter (ADC) is proposed in this letter. To simply exemplify the conversion idea, a 5-bit device structure consisted of Fabry-Perot interferometers (FPI) is analyzed and numerically simulated. The dependence of peak-transmission wavelength on modulation voltage in an electro-optical FPI and the dependence of transmitted power on incident light wavelength in an FPI are discussed and utilized to implement OSEADC.A linearly tunable mode-locked laser, as a voltage-wavelength transformer and a sampler, and chirped grating FPIs, as an encoder array, can be used to obtain much greater sampling rate and bit-resolution.

  15. On Time-Interleaved Analog-to-Digital Converters for Digital Transceivers

    OpenAIRE

    Soudan, Michael; Farrell, Ronan; Barrandon, Ludovic

    2009-01-01

    This paper presents a transceiver model that comprises two time-interleaved analog-to-digital (A/D) converter systems to sample the inphase and quadrature signals in a digital receiver. Random data is used as the information signal and quadrature modulation is employed as the modulation scheme. A polyphase filter bank is derived as a representation of the time-interleaved A/D converter system, thereby modelling its converter mismatch. Furthermore, filter bank theory is used to design re...

  16. An optimized analog to digital converter for WLAN analog front end

    International Nuclear Information System (INIS)

    A 10 bit 80 MSPS analog to digital converter optimized for WLAN analog front end is presented. In contrast to conventional 1.5 bit pipeline architecture, four optimized multi-bit multiply digital to analog converter stages are implemented. An on-chip low-noise reference buffer is proposed for SoC integration purposes, and a wide-bandwidth wide swing sample and hold amplifier is also presented for achieving a good dynamic range. The converter was fabricated in 0.18 μm 1P6M CMOS technology, and the core area occupies approximately 0.85 mm2. Measured results show that with an 11 MHz input signal, it provides a 9.4 bit effective number of bits and a 72 dBc spurious frequency dynamic range when sampled at 80 MHz. (semiconductor integrated circuits)

  17. High fidelity, radiation tolerant analog-to-digital converters

    Science.gov (United States)

    Wang, Charles Chang-I (Inventor); Linscott, Ivan Richard (Inventor); Inan, Umran S. (Inventor)

    2012-01-01

    Techniques for an analog-to-digital converter (ADC) using pipeline architecture includes a linearization technique for a spurious-free dynamic range (SFDR) over 80 deciBels. In some embodiments, sampling rates exceed a megahertz. According to a second approach, a switched-capacitor circuit is configured for correct operation in a high radiation environment. In one embodiment, the combination yields high fidelity ADC (>88 deciBel SFDR) while sampling at 5 megahertz sampling rates and consuming <60 milliWatts. Furthermore, even though it is manufactured in a commercial 0.25-.mu.m CMOS technology (1 .mu.m=12.sup.-6 meters), it maintains this performance in harsh radiation environments. Specifically, the stated performance is sustained through a highest tested 2 megarad(Si) total dose, and the ADC displays no latchup up to a highest tested linear energy transfer of 63 million electron Volts square centimeters per milligram at elevated temperature (131 degrees C.) and supply (2.7 Volts, versus 2.5 Volts nominal).

  18. Kalman filtering applied to the calibration of a high- resolution analog-to-digital converter

    International Nuclear Information System (INIS)

    The paper proposes the application of the Kalman filter in dc calibrations of analog-to- digital converters with a Zener or a Josephson dc voltage reference standard. Repeated measurements over the entire full-scale range of an analog-to-digital converter with posterior Kalman filtering allow optimal estimation of its deviations in respect to a dc reference to be obtained, yielding improved assessment of converter's linearity

  19. Mismatch-Shaping Serial Digital-to-Analog Converter

    DEFF Research Database (Denmark)

    Steensgaard-Madsen, Jesper; Moon, Un-Ku; Temes, Gabor C.

    1999-01-01

    A simple but accurate pseudo-passive mismatch-shaping D/A converter is described. A digital state machine is used to control the switching sequence of a symmetric two-capacitor network that performs the D/A conversion. The error caused by capacitor mismatch is uncorrelated with the input signal a...

  20. Impact of Time-interleaved Analog-to-Digital Converter Mismatch on Digital Receivers

    OpenAIRE

    Soudan, Michael; Farrell, Ronan

    2008-01-01

    This paper presents the impact that gain, offset and timing mismatch in time-interleaved analog-to-digital converter (TIADC) have on digital receiver systems. An analysis of the mismatch errors shows the dependency of the different errors from the spectrum of the input signal. A discrete-time TIADC model is derived allowing to simulate the mismatch effects of the individual ADCs. Finally, simulations results present the performance degradation that can be expected by the usage of non-id...

  1. Precision BiCMOS successive approximation analog-to-digital converter with low power consumption

    International Nuclear Information System (INIS)

    An IP block of a successive approximation analog-to-digital converter (ADC) with low power consumption has been developed as a part of an application-specific integrated circuit (ASIC) for an intellectual flow meter. The advantages of the application of the modified “top-down” design method to the design of the chip have been demonstrated. The results of the simulation, verification, and test of the analog-to-digital converter are presented

  2. Pipeline analog-to-digital converters for wide-band wireless communications

    OpenAIRE

    Sumanen, Lauri

    2002-01-01

    During the last decade, the development of the analog electronics has been dictated by the enormous growth of the wireless communications. Typical for the new communication standards has been an evolution towards higher data rates, which allows more services to be provided. Simultaneously, the boundary between analog and digital signal processing is moving closer to the antenna, thus aiming for a software defined radio. For analog-to-digital converters (ADCs) of radio receivers this indicates...

  3. A Cyclic Analog to Digital Converter for CMOS image sensors

    OpenAIRE

    Levski Dimitrov, Deyan

    2014-01-01

    The constant strive for improvement of digital video capturing speeds together with power efficiency increase, has lead to tremendous research activities in the image sensor readout field during the past decade. The improvement of lithography and solid-state technologies provide the possibility of manufacturing higher resolution image sensors. A double resolution size-up, leads to a quadruple readout speed requirement, if the same capturing frame rate is to be maintained. The speed requiremen...

  4. Basic Theoretical Model and Sampling Criteria for Time-Interleaved Photonic Analog-to-Digital Converters

    OpenAIRE

    Su, Feiran; Wu, Guiling; Zou, Weiwen; Chen, Jianping

    2016-01-01

    In this paper, we present a basic model for time-interleaved photonic analog-to-digital converter (TIPADC) and analyze its linear, nonlinear, and noise performance. The basic operation mechanism of TIPADC is illustrated and the linear performance is analyzed in frequency domain. The mathematical expressions and the output of the system are presented in each processing step. We reveal that photonic sampling folds the whole spectrum of input signal in a narrow band, which enables the analog ban...

  5. 8-bit serial-parallel analog-to-digital converter for fast transient recorder

    International Nuclear Information System (INIS)

    An 8-bit serial-parallel analog-to-digital converter with a sampling frequency 5 MHz is described. The most important circuits of the device are described and parameters are given. The converter is a central part of a transient recorder type TR-1 designed for recording pulse waveforms in measurements of the kinetics of chemical reactions which are radiation-induced using an electron linear accelerator. 9 refs., 9 figs. (author)

  6. Digital-to-analog converters of the X-ray spectrometers of the Kosmos-1106 satellite

    International Nuclear Information System (INIS)

    The principle of operation and peculiarities of the structure of digital-to-analog converterr used in spectrometers of the ''Kosmos-1106'' satellite for hard X-rays are considered. The converters are used as units for matching the information double code and analog telemetric system of the satellite. The error of output analog levels of the converters is of the value not larger than 1/2 of the lowest significant order. That allows to use a computer for the scientific information processing. The results of tests of type 1841E2 micro-circuits are given, the latter were used in the circuit of the converters and operated in the regime different from the nominal one

  7. Demonstration of a 3-bit optical digital-to-analog converter based on silicon microring resonators.

    Science.gov (United States)

    Yang, Lin; Ding, Jianfeng; Chen, Qiaoshan; Zhou, Ping; Zhang, Fanfan; Zhang, Lei

    2014-10-01

    We propose an N-bit optical digital-to-analog converter based on silicon microring resonators (MRRs), which can transform an N-bit electrical digital signal to an optical analog signal. A 3-bit optical digital-to-analog convertor is fabricated as proof of concept through a CMOS-compatible process on a silicon-on-insulator platform. The silicon MRRs are modulated through the electric-field-induced carrier injection in forward biased PN junctions embedded in the ring waveguides. The electro-optical 3-dB bandwidths of the silicon MRRs are approximately 800 MHz. The device works well at a speed of 500  MSample/s under driving voltage swings of 0.75 V. PMID:25360972

  8. A column-based two-stage analog-to-digital converter for uncooled microbolometer arrays

    Science.gov (United States)

    Toprak, Alperen; Tepegoz, Murat; Akin, Tayfun

    2009-05-01

    This paper presents a column-based, two-stage, 12-bit analog-to-digital converter structure designed for uncooled microbolometer arrays. On-chip analog-to-digital converters prevent the degradation of sensitive analog output by external noise sources as well as providing a more integrated functionality. Despite these advantages, the area and power constraints limit the usage of high performance converters. This paper presents a new structure that provides a balance between area, power, and performance. The structure is composed of two stages: a tracking ADC stage running at each column during integration and a successive approximation ADC stage which is shared by a number of columns depending on the array size and operation frequency. The tracking ADC operates during the integration time, while the second ADC starts after the integration is completed. The converter includes self-calibration to lower the effect of process variations and digital correction mechanisms to eliminate the need for low-offset comparators. The simulations and theoretical calculations based on the simulation results show that the total power dissipation of the proposed structure will be approximately 73.7 mW and 88.4 mW on a 320x240 array operating at 60 Hz and 384x288 array operating at 50 Hz, respectively.

  9. Radiation effects of a 12-bit bipolar digital-to-analog converter under different dose rates

    International Nuclear Information System (INIS)

    Total-dose effects and room-temperature annealing behavior of bipolar digital-to-analog converter (DAC) irradiated by 60Co γ-rays were investigated. The results show that the response of the DAC is different between low- and high-dose-rate irradiation. It was found that the integrated circuits exhibit ELDRS and time dependence effect as well. Based on the space charge model, possible mechanism for this response is discussed. (authors)

  10. A CMOS time to digital converter with analog memory for high energy physics particle detectors

    International Nuclear Information System (INIS)

    A data driven TDC (Time to Digital Converter) has been designed and fabricated in HP's 1.2 μm nwell CMOS process. The circuit was designed to work with the straw tube electronics of the Superconducting Supercollider (SSC), where the authors wish to measure the arrival time of electrons at a sense wire. The TCCAMU (Time to Charge Converter with an Analog Memory Unit) measures the time between an edge of the system clock and the leading edge of an asynchronous signal, and then gives a digital output representing that time measurement. Analog data sparsification occurs before the digitization with the help of an analog Level 1/Level 2 storage system; Level 1 to Level 2 data transfers are virtual, in the sense that one swaps capacitor addresses instead of moving charge. Two separate fabrication runs resulted in chips that have ∼ 108 ps/LSB resolution for any particular storage location. The measurement range is 8-24 ns, but adding digital logic to count the reference clock will extend the range to ∼ 1 second

  11. Time-to-digital converters

    CERN Document Server

    Henzler, Stephan

    2010-01-01

    This text covers the fundamentals of time-to-digital converters on analog and digital conversion principles. It includes a theoretical investigation into quantization, linearity, noise and variability, and it details a range of advanced TDC architectures.

  12. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J M

    2010-01-01

    The design of an analog-to-digital converter or digital-to-analog converter is one of the most fascinating tasks in micro-electronics. In a converter the analog world with all its intricacies meets the realm of the formal digital abstraction. Both disciplines must be understood for an optimum conversion solution. In a converter also system challenges meet technology opportunities. Modern systems rely on analog-to-digital converters as an essential part of the complex chain to access the physical world. And processors need the ultimate performance of digital-to-analog converters to present the results of their complex algorithms. The same progress in CMOS technology that enables these VLSI digital systems creates new challenges for analog-to-digital converters: lower signal swings, less power and variability issues. Last but not least, the analog-to-digital converter must follow the cost reduction trend. These changing boundary conditions require micro-electronics engineers to consider their design choices for...

  13. A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter

    Institute of Scientific and Technical Information of China (English)

    Li Xueqing; Fan Hua; Wei Qi; Xu Zhen; Liu Jianan; Yang Huazhong

    2013-01-01

    A 14-bit 250-MS/s current-steering digital-to-analog converter (DAC) was fabricated in a 0.13 μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range (SFDR) is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ).Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

  14. Specifications of analog-to-digital converter for uncooled infrared readout circuits

    Science.gov (United States)

    Robert, Patrick; Durand, Alain; Gravot, Vincent; Pochic, David; Tissot, Jean-Luc

    2011-10-01

    This paper presents how to specify an ADC to digitalize the analog video of the uncooled infrared readout circuit. In a first part the main features will be discussed to select the right resolution, SNR, THD and ENOB of the converter. In a second part the characteristics more specifically sensitive for an ADC integrated in the readout circuit will be presented: architecture, power consumption, electrical dynamic range, crosstalk issues. Indeed, the increasing demand for integrated functions in uncooled readout circuits leads to on-chip ADC design as interface between the internal analog core and the digital processing electronic. In addition this IP could be seen as an inescapable link to integrate also NUC, BPR or all other processing functions on-chip. However specifying an on-chip ADC dedicated to focal plane array raises many questions about its architecture and its performance requirements. We show two architectural approaches are needed to cover the different sensor features in term of array size and frame speed. Finally we will conclude with a trade-off between external or internal approach taking into account the application of the camera, the cost and the ADC state of art.

  15. Microprocessor control of a fast analog-to-digital converter for an underwater fiber optic data link

    OpenAIRE

    Schlechte, Gene L.

    1988-01-01

    This thesis reports on the design and evaluation of a microprocessor-controlled, high-speed analog-to-digital converter. The processor supervises and manages the digital conversion, split-phase encoding (Manchester) and framing of the input signal. This converter is designed to be applied in an underwater package which will serially transmit sensor data over a fiber optic link to a shore station. This intelligent sensor will provide for ease of future system enhancements. An example would be ...

  16. Optimization of Power Dissipation in Pipelined Analog-to-Digital Converter

    Institute of Scientific and Technical Information of China (English)

    徐江涛; 姚素英; 赵毅强; 张为; 李树荣; 张生才

    2004-01-01

    Power optimization for pipelined analog-to-digital converter(ADC) was studied. Operational principle of pipelined ADC was discussed and noise voltage caused by two important thermal noise sources, sampling switch and amplifier,was quantitatively analyzed. Method used to minimize power and the values under simple model were presented. Power can be saved by making the sampling and feedback capacitors scale down in the pipeline.And the size of capacitors was limited by thermal noise in high resolution ADC.The equivalent circuits of the two important thermal noise sources were established.Thermal noise was optimally distributed among the pipeline stages,and the relationship between scaling factor and closed loop gain was obtained for minimum power dissipation.Typical closed loop gain was 2 or 4 in pipeline ADC, and the corresponding scaling factor was 1.217 and 1.317.These results can serve as useful guidelines for designers to minimize the ADC's power consumption.

  17. Effects of Analog-to-Digital Converter Nonlinearities on Radar Range-Doppler Maps.

    Energy Technology Data Exchange (ETDEWEB)

    Doerry, Armin Walter; Dubbert, Dale F.; Tise, Bertice L.

    2014-07-01

    Radar operation, particularly Ground Moving Target Indicator (GMTI) radar modes, are very sensitive to anomalous effects of system nonlinearities. These throw off harmonic spurs that are sometimes detected as false alarms. One significant source of nonlinear behavior is the Analog to Digital Converter (ADC). One measure of its undesired nonlinearity is its Integral Nonlinearity (INL) specification. We examine in this report the rela tionship of INL to GMTI performance. - 4 - Acknowledgements This report is the result of a n unfunded Research and Development effort . Sandia National Laboratories is a multi - program laboratory managed and operated by Sandia Corporation, a wholly owned subsidia ry of Lockheed Martin Corporation, for the U.S. Department of Energy's National Nuclear Security Administration under contract DE - AC04 - 94AL85000.

  18. A behavioral simulator for switched-capacitor sigma-delta modulator analog-to-digital converter

    International Nuclear Information System (INIS)

    In this paper, a PC-based simulator for state of the art oversampled switched-capacitor sigma-delta analog-to-digital converters is presented. The proposed simulator employs behavioral model of switched-capacitor integrator and non-linear quantizer to stimulate the system. The behavioral simulation of the integrator is also verified with SPICE. The simulator is fully integrated and standalone. It integrates an input netlist file interpreter, a behavioral simulator, a generic part library and a powerful post-processor to evaluate the SNR, SDR And TSNR. Both passive and active sensitivities can be investigated by the proposed simulator. The simulator is coded in C++, and is very fast

  19. High precision (14 bit), high density (octal) analog to digital converter for spectroscopy applications

    Science.gov (United States)

    Subramaniam, E. T.; Jain, Mamta; Bhowmik, R. K.; Tripon, Michel

    2008-10-01

    Nuclear and particle physics experiments with large number of detectors require signal processing and data collection strategies that call for the ability to collect large amount of data while not sacrificing the precision and accuracy of the data being collected. This paper deals with the development of a high precision pulse peak detection, analog to digital converter (ADC) module with eight independent channels in plug-in daughter card motherboard model, best suited for spectroscopy experiments. This module provides multiple channels without cross-talk and of 14 bit resolution, while maintaining high density (each daughter card has an area of just 4.2″×0.51″) and exhibiting excellent integral nonlinearity (≤±2 mV or ±0.02% full scale reading) and differential nonlinearity (≤±1%). It was designed, developed and tested, in house, and gives added advantages of cost effectiveness and ease of maintenance.

  20. Design of Multi-Valued Quaternary Based Analog-to-Digital Converter

    Directory of Open Access Journals (Sweden)

    A. H.M.Z. Alam

    2009-01-01

    Full Text Available Problem statement: The design of multi-valued quaternary based Analog-to-Digital Converter (ADC circuit was presented. The ADC generates multi-valued logic outputs rather than the conventional binary output system to overall reduction in circuit complexity and size. Approach: Design was implemented using pipeline ADC architecture and was simulated using model parameters based on standard 0.13 µm CMOS process. Results: Performance analysis of the design showed desirable performance parameters in terms of response, low power consumption, and a sampling rate of 10 MHz at a supply voltage of 1.3V was achieved. Conclusion/Recommendations: The ADC design was suitable for the needs of mixed-signal integrated circuit design and can be implemented as a conversion circuit for systems based on multiple-valued logic design.

  1. Correction of differential nonlinearities in analog-to-digital converters used for digital γ-ray spectroscopy

    International Nuclear Information System (INIS)

    Many experiments in nuclear structure and nuclear astrophysics demand for a spectroscopy setup with a high dynamic energy range while maintaining decent count rates. In such experiments conducted at the Cologne HORUS γ-ray spectrometer which is equipped with a fully digitized data acquisition system severe peak broadening and double peak structures in the energy spectra have been observed. These spectral distortions originate from the differential nonlinearity (DNL) of the Analog-to-digital converters used for digitizing the preamplifier signals. A correction method for this DNL using standard calibration sources and artificial pulser signals will be presented as well as an offline correction algorithm. The algorithm is capable of removing double peak structures and increasing the energy resolution for broadened peaks while achieving a better linearity in energy calibration compared to the uncorrected data.

  2. Deep Cryogenic Low Power 24 Bits Analog to Digital Converter with Active Reverse Cryostat

    Science.gov (United States)

    Turqueti, Marcos; Prestemon, Soren; Albright, Robert

    LBNL is developing an innovative data acquisition module for superconductive magnets where the front-end electronics and digitizer resides inside the cryostat. This electronic package allows conventional electronic technologies such as enhanced metal-oxide-semiconductor to work inside cryostats at temperatures as low as 4.2 K. This is achieved by careful management of heat inside the module that keeps the electronic envelop at approximately 85 K. This approach avoids all the difficulties that arise from changes in carrier mobility that occur in semiconductors at deep cryogenic temperatures. There are several advantages in utilizing this system. A significant reduction in electrical noise from signals captured inside the cryostat occurs due to the low temperature that the electronics is immersed in, reducing the thermal noise. The shorter distance that signals are transmitted before digitalization reduces pickup and cross-talk between channels. This improved performance in signal-to-noise rate by itself is a significant advantage. Another important advantage is the simplification of the feedthrough interface on the cryostat head. Data coming out of the cryostat is digital and serial, dramatically reducing the number of lines going through the cryostat feedthrough interface. It is important to notice that all lines coming out of the cryostat are digital and low voltage, reducing the possibility of electric breakdown inside the cryostat. This paper will explain in details the architecture and inner workings of this data acquisition system. It will also provide the performance of the analog to digital converter when the system is immersed in liquid helium, and in liquid nitrogen. Parameters such as power dissipation, integral non-linearity, effective number of bits, signal-to-noise and distortion, will be presented for both temperatures.

  3. A Review: Compensation of Mismatches in Time Interleaved Analog to Digital Converters

    Directory of Open Access Journals (Sweden)

    Shivlal Mishra

    2014-08-01

    Full Text Available The execution of today's correspondence frameworks is exceedingly subject to the utilized Analog-to-Digital converters (ADCs, and with a specific end goal to give more flexibility and exactness to the developing correspondence innovations, superior-ADCs are needed. In this respect, the time-interleaved operation of an exhibit of ADCs (TI-ADC might be a sensible result. A TI-ADC can build its throughput by utilizing M channel ADCs or sub converters in parallel and examining the data motion in a period-interleaved way. In any case, the execution of a TI-ADC gravely suffers from the bungles around the channel ADCs. In this paper we survey the advancement in the configuration of low-intricacy advanced remedy structures and calculations for time-interleaved ADCs in the course of the most recent five years. We devise a discrete-time model, state the outline issue, and finally infer the calculations and structures. Specifically, we examine proficient calculations to outline time-differing remedy filters and additionally iterative structures using polynomial based filters. Thusly, the remuneration structure may be utilized to repay time-differing recurrence reaction befuddles in time-interleaved ADCs, and in addition to remake uniform examples from nonuniformly tested indicators. We examine the recompense structure, research its execution, and exhibit requisition zones of the structure through various illustrations. At long last, we give a standpoint to future examination questions.

  4. Basic Theoretical Model and Sampling Criteria for Time-Interleaved Photonic Analog-to-Digital Converters

    CERN Document Server

    Su, Feiran; Zou, Weiwen; Chen, Jianping

    2016-01-01

    In this paper, we present a basic model for time-interleaved photonic analog-to-digital converter (TIPADC) and analyze its linear, nonlinear, and noise performance. The basic operation mechanism of TIPADC is illustrated and the linear performance is analyzed in frequency domain. The mathematical expressions and the output of the system are presented in each processing step. We reveal that photonic sampling folds the whole spectrum of input signal in a narrow band, which enables the analog bandwidth of a TIPADC to be much higher than the bandwidth of back-end electronics. The feasible regions of the system is obtained in terms of system frequency response, and a set of sampling criteria determining the basic requirements to the system are summarized for typical applications. The results show that the global minimum feasible bandwidth of back-end electronics is the half of single channel sampling rate when the bandwidth of photonic sampling pulse is comparable to input signal frequency. The amplitude and phase ...

  5. A Novel Method for Testing Digital to Analog Converter in Static Range

    Directory of Open Access Journals (Sweden)

    K. Hariharan

    2010-01-01

    Full Text Available Problem statement: Linearity testing methods for DAC usually involves usage of non-linear analog components, which are indeed prone to various errors. Few other testing methodologies involve complex circuitry for measuring exactitude of DAC. Practically, it is difficult to build those as Built In Self Test (BIST due to complexity of calculation, which demands more usage of ALU (or core of processing unit. This research aims to optimize and simplify the design of DAC testing scheme, while minimizing the computational overhead. Henceforth, the testing technique can be brought on to BIST level circuitry. Approach: A slope generator (more commonly known as integrator produces a Ramp type of output voltage when it is fed with a DC voltage, slope of ramp depends upon the magnitude of DC-voltage. These varying slopes, when converted into a useful number, can provide some information, regarding voltage level of input. Results: In this research, we replace the DC input of the Slope generator by analog output of DAC, which is under test. As the output of DAC varies according to the Digital code input, various slopes can be generated. These slopes are converted here into useful numbers called tick counts, by measuring the time taken by Ramp type output to cross a defined threshold voltage interval. The proposed method makes use of an integrator to produce a ramp signal of high precision and conditioned slope. The actual slope produced by the output of the DAC is compared with the expected slope by counting the number of clock ticks. Conclusion: This system of using Time Tick based BIST eludes the usage of high precision non-linear devices like ADCs to test DACs. Also this system reduces exigency of separate ALU for computing error."

  6. Analog to Digital Conversion in Physical Measurements

    OpenAIRE

    Kapitaniak, T.; Zyczkowski, K.; Feudel, U.; Grebogi, C.

    1999-01-01

    There exist measuring devices where an analog input is converted into a digital output. Such converters can have a nonlinear internal dynamics. We show how measurements with such converting devices can be understood using concepts from symbolic dynamics. Our approach is based on a nonlinear one-to-one mapping between the analog input and the digital output of the device. We analyze the Bernoulli shift and the tent map which are realized in specific analog/digital converters. Furthermore, we d...

  7. FPGA implementation of a single-input fuzzy logic controller for boost converter with the absence of an external analog-to-digital converter

    DEFF Research Database (Denmark)

    Taeed, Fazel; Salam, Z.; Ayob, S.

    2012-01-01

    In this paper, the single-input fuzzy logic controller (FLC) (SIFLC) for boost converter output-voltage regulation is proposed. The SIFLC utilizes the signed distance method that reduces the multidimensional rule table to 1-D with only one input variable, i.e., distance d. The simplification allows...... analog-to-digital converter (ADC). Instead, a simple analog-to-digital conversion scheme is implemented using the FPGA itself. Due to the simplicity of the SIFLC algorithm and the absence of an external ADC, the overall implementation requires only 408 logic elements and five input-output pins of the...

  8. Digital-to-analog converters for the Kosmos-1106 satellite scintillation spectrometers with controlled coefficient of preliminary interconversion

    International Nuclear Information System (INIS)

    The principle of operation and specific features of digital-analog converters for scintillation spectrometers the of ''Kosmos-1106'' satellite with the controlled coefficient of preliminary interconvepsion are consideped. As a result of change in the coefficient of preliminary itnterconversion a minimum error at the measurements of fluxes of cosmic rays is provided within 28 to 20

  9. LDRD final report: photonic analog-to-digital converter (ADC) technology; TOPICAL

    International Nuclear Information System (INIS)

    We report on an LDRD seed program of novel technology development (started by an FY98 Engineering Tech-base project) that will enable extremely high-fidelity analog-to-digital converters for a variety of national security missions. High speed (l0+ GS/s ), high precision (l0+ bits) ADC technology requires extremely short aperture times ((approx)1ps ) with very low jitter requirements (sub 10fs ). These fundamental requirements, along with other technological barriers, are difficult to realize with electronics: However, we outline here, a way to achieve these timing apertures using a novel multi-wavelength optoelectronic short-pulse optical source. Our approach uses an optoelectronic feedback scheme with high optical Q to produce an optical pulse train with ultra-low jitter ( sub 5fs) and high amplitude stability ( and lt;10(sup 10)). This approach requires low power and can be integrated into an optoelectronic integrated circuit to minimize the size. Under this seed program we have demonstrated that the optical feedback mechanism can be used to generate a high Q resonator. This has reduced the technical risk for further development, making it an attractive candidate for outside funding

  10. Proposal for a digital converter of analog magnetic signals

    OpenAIRE

    Ertler, Christian; Fabian, Jaroslav

    2006-01-01

    A device which converts analog magnetic signals directly into digital information is proposed. The device concept is based on the monostable-bistable transition logic element, which consists of two resonant tunneling diodes (load and driver) connected in series and employs the monostable to bistable working point transition of the circuit. Using a magnetic resonant tunneling diode as the driver allows to control the resulting working point of the bistable region by an external magnetic field ...

  11. Time-to-digital converter based on analog time expansion for 3D time-of-flight cameras

    Science.gov (United States)

    Tanveer, Muhammad; Nissinen, Ilkka; Nissinen, Jan; Kostamovaara, Juha; Borg, Johan; Johansson, Jonny

    2014-03-01

    This paper presents an architecture and achievable performance for a time-to-digital converter, for 3D time-of-flight cameras. This design is partitioned in two levels. In the first level, an analog time expansion, where the time interval to be measured is stretched by a factor k, is achieved by charging a capacitor with current I, followed by discharging the capacitor with a current I/k. In the second level, the final time to digital conversion is performed by a global gated ring oscillator based time-to-digital converter. The performance can be increased by exploiting its properties of intrinsic scrambling of quantization noise and mismatch error, and first order noise shaping. The stretched time interval is measured by counting full clock cycles and storing the states of nine phases of the gated ring oscillator. The frequency of the gated ring oscillator is approximately 131 MHz, and an appropriate stretch factor k, can give a resolution of ≍ 57 ps. The combined low nonlinearity of the time stretcher and the gated ring oscillator-based time-to-digital converter can achieve a distance resolution of a few centimeters with low power consumption and small area occupation. The carefully optimized circuit configuration achieved by using an edge aligner, the time amplification property and the gated ring oscillator-based time-to-digital converter may lead to a compact, low power single photon configuration for 3D time-of-flight cameras, aimed for a measurement range of 10 meters.

  12. Mixed Linear/Square-Root Encoded Single Slope Ramp Provides a Fast, Low Noise Analog to Digital Converter with Very High Linearity for Focal Plane Arrays

    Science.gov (United States)

    Wrigley, Christopher James (Inventor); Hancock, Bruce R. (Inventor); Newton, Kenneth W. (Inventor); Cunningham, Thomas J. (Inventor)

    2014-01-01

    An analog-to-digital converter (ADC) converts pixel voltages from a CMOS image into a digital output. A voltage ramp generator generates a voltage ramp that has a linear first portion and a non-linear second portion. A digital output generator generates a digital output based on the voltage ramp, the pixel voltages, and comparator output from an array of comparators that compare the voltage ramp to the pixel voltages. A return lookup table linearizes the digital output values.

  13. Design of A 5-Bit Fully Parallel Analog to Digital Converter Using Common Gate Differrential Mos Pair-Based Comparator

    Science.gov (United States)

    Aytar, Oktay

    2015-09-01

    This paper presents a novel comparator structure based on the common gate differential MOS pair. The proposed comparator has been applied to fully parallel analog to digital converter (A/D converter). Furthermore, this article presents 5 bit fully parallel A/D Converter design using the cadence IC5141 design platform and NCSU(North Carolina State University) design kit with 0.18 μm CMOS technology library. The proposed fully parallel A/D converter consist of resistor array block, comparator block, 1-n decoder block and programmable logic array. The 1-n decoder block includes latch block and thermometer code circuit that is implemented using transmission gate based multiplexer circuit. Thus, sampling frequency and analog bandwidth are increased. The INL and DNL of the proposed fully parallel A/D converter are (0/ + 0.63) LSB and (-0.26/ + 0.31) LSB at a sampling frequency of 5 GS/s with an input signal of 50 MHz, respectively. The proposed fully parallel A/D Converter consumes 340 mW from 1.8 V supply.

  14. A photonic analog-to-digital converter using phase modulation and self-coherent detection with spatial oversampling.

    Science.gov (United States)

    Golani, Ori; Mauri, Luca; Pasinato, Fabiano; Cattaneo, Cristian; Consonnni, Guido; Balsamo, Stefano; Marom, Dan M

    2014-05-19

    We propose a new type of photonic analog-to-digital converter (ADC), designed for high-resolution (>7 bit) and high sampling rates (scalable to tens of GS/s). It is based on encoding the input analog voltage signal onto the phase of an optical pulse stream originating from a mode-locked laser, and uses spatial oversampling as a means to improve the conversion resolution. This paper describes the concept of spatial oversampling and draws its similarities to the commonly used temporal oversampling. The design and fabrication of a LiNbO(3)/silica hybrid photonic integrated circuit for implementing the spatial oversampling is shown, and its abilities are demonstrated experimentally by digitizing gigahertz signals (frequencies up to 18GHz) at an undersampled rate of 2.56GS/s with a conversion resolution of up to 7.6 effective bits. Oversampling factors of 1-4 are demonstrated. PMID:24921345

  15. Photonic preprocessor for analog-to-digital-converter using a cavity-less pulse source.

    Science.gov (United States)

    Wiberg, Andreas O J; Liu, Lan; Tong, Zhi; Myslivets, Evgeny; Ataie, Vahid; Kuo, Bill P-P; Alic, Nikola; Radic, Stojan

    2012-12-10

    A photonic preprocessor for analog to digital conversion is demonstrated and characterized using a cavity-less optical pulse source. The pulse source generates high fidelity pulses at 2 GHz repetition rate with temporal width of 3 ps. Chirped pulses are formed by cascaded amplitude and phase modulators, and subsequently compressed in dispersion compensating fiber. Sampling operation is performed with a dual-output Mach-Zehnder modulator, where the complimentary output enables a reduction of noise by 3 dB. Phase noise characterization shows that the phase noise of the generated pulses is fully dictated by the RF source. The high quality of the pulse source used in a sampling preprocessor experiment was verified by measuring 8 effective number of bits at 10 GHz and 7.0 effective number of bits at 40 GHz. PMID:23262883

  16. A 13-Bits wilkinson analog-digital converter for NIM acquisition system

    International Nuclear Information System (INIS)

    A new 13-bits Wilkinson analog-digital converter is described. The aim of this work is to describe the circuits of sample and hold, memory condensator loading and releasing PROM based control memory logic, zero level detection and correction. The converter is designed for the digital measurement of the peak amplitudes of pulses with statistical or periodical time distribution. The analog-digital converter may be used in spectrometric systems, multi-channel analysers or any similar PC based system

  17. A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

    Institute of Scientific and Technical Information of China (English)

    LI Dan; RONG Men-tian; MAO Jun-fa

    2007-01-01

    A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC).The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge.Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers.The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

  18. A micromirror module using a MEMS digital-to-analog converter and its application for optical surface profiling

    International Nuclear Information System (INIS)

    In this work, we develop a microelectromechanical digital-to-analog converter mirror module (M-DACMM) and demonstrate its application for non-contact optical surface profiling systems. The proposed device generates nano-scale step motions that are proportional to input digital signals. A fabrication process, which is capable of releasing a large-area movable mirror without etching holes, is proposed to realize the M-DACMM monolithically. The transient responses of the mirror module are also measured and discussed. The switching time between two input binary states is less than 80 ms. The measured full-scale displacement is 1050 nm, and the motion step is 72 nm. The M-DACMM is also successfully installed on a surface profiling system as a reference mirror module. The surface-profiling results measured by the system are also presented

  19. Proton-induced single event upset characterisation of a 1 giga-sample per second analog to digital converter

    International Nuclear Information System (INIS)

    The SPT7760 is an analog to digital converter that is used in satellite for digital processing. In this paper we describe the characterization and analysis of proton-induced single event upsets (SEU) for the SPT7760 operating at sample rates from 125 Msps (Mega-samples per second) to 1 Gsps. The SEU cross-section has been measured as a function of sample rate for various input levels. The data collected is clearly non-linear for all cases. The data shows that this device has a relative low cross-section for proton-induced SEUs and remains functional at a proton dose of 580 krad (Si). (A.C.)

  20. 23 µW 8.9-effective number of bit 1.1 MS/s successive approximation register analog-to-digital converter with an energy-efficient digital-to-analog converter switching scheme

    Directory of Open Access Journals (Sweden)

    Lei Sun

    2014-08-01

    Full Text Available This study presents a successive approximation register analog-to-digital converter with an energy-efficient switching scheme. A split-most significant bit capacitor array is used with a least significant bit-down switching scheme. Compared with the conventional binary-weighted capacitor array, it reduces the area and average switching energy by 50 and 87% under the same unit capacitor. Moreover, capacitor matching requirement is relaxed by 75%. A prototype design was fabricated in a 0.13 µm complementary metal oxide semiconductor process. It consumes 23.2 µW under 1 V analog supply and 0.5 V digital supply. Measured results show a peak signal-to-distortion-and-noise ratio of 55.2 dB and an effective resolution bandwidth up to 1.1 MHz when it operates at 1.1 MS/s. Its figure-of-merit is 44.1 fJ/conversion-step.

  1. Design of a general purpose (RS-232C) analog-to-digital data converter

    International Nuclear Information System (INIS)

    The purpose of this project is to design a general purpose hardware that interfaces analog devices with any desirable computer supporting the RS-232 interface. The hardware incorporates bidirectional data transmission at 1,200 bps, 2,400 bps, 4800 bps, 9,600 bps, 19,200 pbs and 38400 bps. The communication / processing software has been written in C language that incorporates the idea of the potability of the software from one environment to the other. (author)

  2. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits

    Directory of Open Access Journals (Sweden)

    Xinjie eGuo

    2015-12-01

    Full Text Available The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC with up to 8 bits of precision. Major shortcomings affecting the ADC’s precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2-x/Pt memristors and CMOS integrated circuit components.

  3. Modeling and Experimental Demonstration of a Hopfield Network Analog-to-Digital Converter with Hybrid CMOS/Memristor Circuits.

    Science.gov (United States)

    Guo, Xinjie; Merrikh-Bayat, Farnood; Gao, Ligang; Hoskins, Brian D; Alibart, Fabien; Linares-Barranco, Bernabe; Theogarajan, Luke; Teuscher, Christof; Strukov, Dmitri B

    2015-01-01

    The purpose of this work was to demonstrate the feasibility of building recurrent artificial neural networks with hybrid complementary metal oxide semiconductor (CMOS)/memristor circuits. To do so, we modeled a Hopfield network implementing an analog-to-digital converter (ADC) with up to 8 bits of precision. Major shortcomings affecting the ADC's precision, such as the non-ideal behavior of CMOS circuitry and the specific limitations of memristors, were investigated and an effective solution was proposed, capitalizing on the in-field programmability of memristors. The theoretical work was validated experimentally by demonstrating the successful operation of a 4-bit ADC circuit implemented with discrete Pt/TiO2- x /Pt memristors and CMOS integrated circuit components. PMID:26732664

  4. Progress in voltage and current mode on-chip analog-to-digital converters for CMOS image sensors

    Science.gov (United States)

    Panicacci, Roger; Pain, Bedabrata; Zhou, Zhimin; Nakamura, Junichi; Fossum, Eric R.

    1996-03-01

    Two 8 bit successive approximation analog-to-digital converter (ADC) designs and a 12 bit current mode incremental sigma delta ((Sigma) -(Delta) ) ADC have been designed, fabricated, and tested. The successive approximation test chip designs are compatible with active pixel sensor (APS) column parallel architectures with a 20.4 micrometers pitch in a 1.2 micrometers n-well CMOS process and a 40 micrometers pitch in a 2 micrometers n-well CMOS process. The successive approximation designs consume as little as 49 (mu) W at a 500 KHz conversion rate meeting the low power requirements inherent in column parallel architectures. The current mode incremental (Sigma) -(Delta) ADC test chip is designed to be multiplexed among 8 columns in a semi-column parallel current mode APS architecture. The higher accuracy ADC consumes 800 (mu) W at a 5 KHz conversion rate.

  5. An ultra high-speed 8-bit timing interleave folding & interpolating analog-to-digital converter with digital foreground calibration technology

    Institute of Scientific and Technical Information of China (English)

    Zhang Zhengping; Wang Yonglu; Huang Xingfa; Shen Xiaofeng; Zhu Can; Zhang Lei; Yu Jinshan; Zhang Ruitao

    2011-01-01

    A 2-Gsample/s 8-b analog-to-digital converter in 0.35μm BiCMOS process technology is presented.The ADC uses the unique folding and interpolating algorithm and dual-channel timing interleave multiplexing technology to achieve a sampling rate of 2 GSPS.Digital calibration technology is used for the offset and gain corrections of the S/H circuit,the offset correction of preamplifier,and the gain and clock phase corrections between channels.As a result of testing,the ADC achieves 7.32 ENOB at an analog input of 484 MHz and 7.1 ENOB at Nyquist input after the chip is self-corrected.

  6. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    International Nuclear Information System (INIS)

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB and INL less than ±4.3 LSB after the chip is calibrated. (paper)

  7. A 16 b 2 GHz digital-to-analog converter in 0.18 μm CMOS with digital calibration technology

    Science.gov (United States)

    Weidong, Yang; Jiandong, Zang; Tiehu, Li; Pu, Luo; Jie, Pu; Ruitao, Zhang; Chao, Chen

    2015-10-01

    This paper presents a 16-bit 2 GSPS digital-to-analog converter (DAC) in 0.18 μm CMOS technology. This DAC is implemented using time division multiplex access system architecture in the digital domain. The input data is received with a two-channel LVDS interface. The DLL technology is introduced to meet the timing requirements between phases of the LVDS data and the data sampling clock. A FIFO is designed to absorb the phase difference between the data clock and DAC system clock. A delay controller is integrated to adjust the phase relationship between the high speed digital clock and analog clock, obtaining a sampling rate of 2 GSPS. The current source mismatch at higher bits is calibrated in the digital domain. Test results show that the DAC achieves 74.02 dBC SFDR at analog output of 36 MHz, and DNL less than ±2.1 LSB & INL less than ±4.3 LSB after the chip is calibrated.

  8. A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC) for CMOS Image Sensors

    OpenAIRE

    Tao Lyu; Suying Yao; Kaiming Nie; Jiangtao Xu

    2014-01-01

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the s...

  9. Design and Simulation of Seido Buffer for Analog to Digital Converter (ADC) on Multichannel Analyzer (MCA) Application

    International Nuclear Information System (INIS)

    Most of our electronic equipment has buffer, thus this make buffer as one of importance in electronic gadget. This paper introduced Single Ended Input Differential Output (SEIDO) buffer to predict the bias at approximately 2.5 V. For this purpose, the input range between -1 mV to 4 V was implemented. The software used to cascade SEIDO buffer is called LTspice IV; an open source software developed by Linear Technology Incorporation. The component involve in this development was Operational Amplifier (OP AMP) AD826 from Analog Devices Incorporation, capacitor and resistor. Kirchhoffs Current Law and Kirchhoffs Voltage Law was applied to calculated voltage gain and biasing voltage. All design has been verified by LTspice IV. The result produced from simulation was between -0.3 V to 6.3 V with bias roughly at 2.5 V. These results prove that it was capable to drive Analog Digital Converter (ADC) that can subsequently apply for Multichannel Analyzer (MCA). (author)

  10. Analog-to-digital conversion

    CERN Document Server

    Pelgrom, Marcel J. M

    2013-01-01

    This textbook is appropriate for use in graduate-level curricula in analog to digital conversion, as well as for practicing engineers in need of a state-of-the-art reference on data converters.  It discusses various analog-to-digital conversion principles, including sampling, quantization, reference generation, nyquist architectures and sigma-delta modulation.  This book presents an overview of the state-of-the-art in this field and focuses on issues of optimizing accuracy and speed, while reducing the power level. This new, second edition emphasizes novel calibration concepts, the specific requirements of new systems, the consequences of 45-nm technology and the need for a more statistical approach to accuracy.  Pedagogical enhancements to this edition include more than twice the exercises available in the first edition, solved examples to introduce all key, new concepts and warnings, remarks and hints, from a practitioner’s perspective, wherever appropriate.  Considerable background information and pr...

  11. Digital to position converter

    International Nuclear Information System (INIS)

    This report deals with a digitally controllable servosystem for the regulation of a mechanical movement. The system has been applied, as prototyupe, to the phase rotator in the driver of the klystron of station 13 (NIKHEF K), and to the reducer at the output of this klystron. Control and supply takes place from a Camac-module, Borer type 1084A. (author). 6 figs

  12. A low-power piecewise linear analog to digital converter for use in particle tracking

    International Nuclear Information System (INIS)

    This paper describes a low-power piecewise linear A/D converter. A 5MHz at sign 5V with 25mW power consumption prototype has been implemented in a 1.5microm CMOS process. The die area excluding pads is 5mm2. 11-bit absolute accuracy is obtained with a new DC offset plus charge injection compensation technique used in the comparators scheme. This ADC with large dynamic range and high resolution is developed for the readout of a tracker and/or preshower in the future LHC experiments

  13. Optical domain analog to digital conversion methods and apparatus

    Science.gov (United States)

    Vawter, Gregory A

    2014-05-13

    Methods and apparatus for optical analog to digital conversion are disclosed. An optical signal is converted by mapping the optical analog signal onto a wavelength modulated optical beam, passing the mapped beam through interferometers to generate analog bit representation signals, and converting the analog bit representation signals into an optical digital signal. A photodiode receives an optical analog signal, a wavelength modulated laser coupled to the photodiode maps the optical analog signal to a wavelength modulated optical beam, interferometers produce an analog bit representation signal from the mapped wavelength modulated optical beam, and sample and threshold circuits corresponding to the interferometers produce a digital bit signal from the analog bit representation signal.

  14. Low-power 12-bit superconducting analog-to-digital converter for cryogenic focal plane array readouts

    Science.gov (United States)

    Rylov, Sergey V.; Robertazzi, R. P.

    1996-06-01

    Superconducting Analog-to-Digital Converters (ADCs) are attractive for use on cryogenic focal plane arrays because of their ultra-low power consumption and their ability to operate at cryogenic temperatures. We have developed a 12 bit ADC based on Nb thin film superconducting integrated circuit technology which dissipates less than 0.44 mW while in operation at 4.2 K. Extensions of this deign to lower junction critical currents would allow the production of an ADC which dissipates less than 0.1 mW when fully biased. The ADC had at least 9.75 effective bits of resolution for 20 kHz input signals, limited by the harmonic distortions of the signal source. We estimate that the ultimate resolution of this ADC can be greater than 20 bits at 10 MHz bandwidth with our current 2.5 micron fabrication process. Potential applications for this device include focal plane array read out electronics for low temperature (4.2 K and below) imaging arrays, such as those being used on the SIRTF mission being planned by NASA. Other applications include high precision instrumentation for metrology uses.

  15. Design and operation of voltage quadrupler cell for rapid-single-flux-quantum digital-to-analog converters

    International Nuclear Information System (INIS)

    We propose a voltage quadrupler cell for the voltage multiplier in a RSFQ-DAC. It is composed of an input JTL and an output two-SQUID-stack. By operating the two-SQUID-stack in the second mode, fourfold voltage is obtained. A voltage quadrupler cell is fabricated using the ISTEC standard Nb process. The fourfold operation is confirmed in experiment. A conventional voltage multiplier cell in a rapid-single-flux-quantum (RSFQ) digital-to-analog converter is composed of an output dc-superconducting quantum interference device (dc-SQUID) magnetically coupled to an input Josephson transmission line. The authors previously demonstrated the operation of a voltage doubler cell that doubled the input voltage by introducing the second-mode operation. In this paper, we propose another type of a voltage multiplier cell, a voltage quadrupler, where the output dc-SQUID is replaced with two dc-SQUIDs sharing one coupling inductor. The proposed cell quadruples the input voltage when each SQUID is operated in the second-mode. A single voltage quadrupler has been designed and fabricated using the ISTEC standard process (STP2). Although operation margins for the bias current and the input SFQ repetition frequency are smaller than the values expected from simulation, its fundamental operation has been confirmed in experiment.

  16. Precision timing measurement of phototube pulses using a flash analog-to-digital converter

    OpenAIRE

    Bennett, J. V.(Carnegie Mellon University, Pittsburgh, Pennsylvania 15213, USA); Kornicer, M.(University of Hawaii, Honolulu, HI, 96822, USA); Shepherd, M. R.; Ito, M. M.

    2010-01-01

    We present the timing characteristics of the flash ADC readout of the GlueX forward calorimeter, which depends on precise measurement of arrival time of pulses from FEU 84-3 photomultiplier tubes to suppress backgrounds. The tests presented were performed using two different 250 MHz prototype flash ADC devices, one with eight-bit and one with twelve-bit sampling depth. All measured time resolutions were better than 1 ns, independent of signal size, which is the design goal for the GlueX forwa...

  17. Precision timing measurement of phototube pulses using a flash analog-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Bennett, J.V.; Kornicer, M. [Indiana University, Bloomington, IN 47405 (United States); Shepherd, M.R., E-mail: mashephe@indiana.ed [Indiana University, Bloomington, IN 47405 (United States); Ito, M.M. [Thomas Jefferson National Accelerator Facility, Newport News, VA 23606 (United States)

    2010-10-01

    We present the timing characteristics of the flash ADC readout of the GlueX forward calorimeter, which depends on precise measurement of arrival time of pulses from FEU 84-3 photomultiplier tubes to suppress backgrounds. The tests presented were performed using two different 250 MHz prototype flash ADC devices, one with eight-bit and one with 12-bit sampling depth. All measured time resolutions were better than 1 ns, independent of signal size, which is the design goal for the GlueX forward calorimeter. For pulses with an amplitude of 100 mV the timing resolution is 0.57{+-}0.18 ns, while for 500 mV pulses it is 0.24{+-}0.08 ns.

  18. Precision timing measurement of phototube pulses using a flash analog-to-digital converter

    International Nuclear Information System (INIS)

    We present the timing characteristics of the flash ADC readout of the GlueX forward calorimeter, which depends on precise measurement of arrival time of pulses from FEU 84-3 photomultiplier tubes to suppress backgrounds. The tests presented were performed using two different 250 MHz prototype flash ADC devices, one with eight-bit and one with 12-bit sampling depth. All measured time resolutions were better than 1 ns, independent of signal size, which is the design goal for the GlueX forward calorimeter. For pulses with an amplitude of 100 mV the timing resolution is 0.57±0.18 ns, while for 500 mV pulses it is 0.24±0.08 ns.

  19. Precision timing measurement of phototube pulses using a flash analog-to-digital converter

    CERN Document Server

    Bennett, J V; Shepherd, M R; Ito, M M

    2010-01-01

    We present the timing characteristics of the flash ADC readout of the GlueX forward calorimeter, which depends on precise measurement of arrival time of pulses from FEU 84-3 photomultiplier tubes to suppress backgrounds. The tests presented were performed using two different 250 MHz prototype flash ADC devices, one with eight-bit and one with twelve-bit sampling depth. All measured time resolutions were better than 1 ns, independent of signal size, which is the design goal for the GlueX forward calorimeter. For pulses with an amplitude of 100 mV the timing resolution is 0.57 +- 0.18 ns, while for 500 mV pulses it is 0.24 +- 0.08 ns.

  20. Precision timing measurement of phototube pulses using a flash analog-to-digital converter

    Science.gov (United States)

    Bennett, J. V.; Kornicer, M.; Shepherd, M. R.; Ito, M. M.

    2010-10-01

    We present the timing characteristics of the flash ADC readout of the GlueX forward calorimeter, which depends on precise measurement of arrival time of pulses from FEU 84-3 photomultiplier tubes to suppress backgrounds. The tests presented were performed using two different 250 MHz prototype flash ADC devices, one with eight-bit and one with 12-bit sampling depth. All measured time resolutions were better than 1 ns, independent of signal size, which is the design goal for the GlueX forward calorimeter. For pulses with an amplitude of 100 mV the timing resolution is 0.57±0.18 ns, while for 500 mV pulses it is 0.24±0.08 ns.

  1. Comparison of performance of analog-to-digital converters (ADC) for pulse height analyzers

    International Nuclear Information System (INIS)

    In the recent ADCs for pulse height analyzers (PHA), Wilkinson type is a leading one, and those with 50 to 200 MHz clock frequency and 8K channel are mostly on the market. The comparison of the performance of ADCs was conducted under the condition of using these multi-channel PHAs as γ-ray spectrometers. The following three ADCs were compared: ADC incorporated in CANBERRA 8100 MCA, and CANBERRA 8060 ADCs used as the ADCs for 1st and 2nd GAMA systems. In this case, the conversion gains of these ADCs were set at 4K because the memory of 8100 MCA was 4K, and the GAMA systems were also mostly operated at 4K. In this paper, report is made on the measurements of dead time, the change of γ peaks immediately after the power was turned on, the temperature dependence of ADCs the long term stability of ADCs, derivative non-linearity, and integration non-linearity. The dead time of the ADC of 8100 CMA was shorter in the range up to 1000 channels. The temperature dependence was -0.017%/deg C in 8100 MCA, and -0.061 and -0.072%/deg C in GAMA. The long term stability was -0.02%/14 hr in 8100 MCA, and -0.027%/14 hr in 8060 of 1st GAMA. The derivative non-linearity was 0.45% in 8100 MCA, 0.67% in 8060 of 1st GAMA, and the integration non-linearity was 0.075% for 8100 MCA, and 0.085 - 0.1% in 8060 ADCs. Also, the change of γ peaks immediately after the power was turned on for 8100 ADC was better than that of 8060 ADC. (Wakatsuki, Y.)

  2. A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

    Science.gov (United States)

    Iguchi, Kyosuke; Matsuoka, Ayako

    2014-07-01

    One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2-13.3 of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nTrms at 0.1-10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket.

  3. A digital-type fluxgate magnetometer using a sigma-delta digital-to-analog converter for a sounding rocket experiment

    International Nuclear Information System (INIS)

    One of the design challenges for future magnetospheric satellite missions is optimizing the mass, size, and power consumption of the instruments to meet the mission requirements. We have developed a digital-type fluxgate (DFG) magnetometer that is anticipated to have significantly less mass and volume than the conventional analog-type. Hitherto, the lack of a space-grade digital-to-analog converter (DAC) with good accuracy has prevented the development of a high-performance DFG. To solve this problem, we developed a high-resolution DAC using parts whose performance was equivalent to existing space-grade parts. The developed DAC consists of a 1-bit second-order sigma-delta modulator and a fourth-order analog low-pass filter. We tested the performance of the DAC experimentally and found that it had better than 17-bits resolution in 80% of the measurement range, and the linearity error was 2−13.3 of the measurement range. We built a DFG flight model (in which this DAC was embedded) for a sounding rocket experiment as an interim step in the development of a future satellite mission. The noise of this DFG was 0.79 nTrms at 0.1–10 Hz, which corresponds to a roughly 17-bit resolution. The results show that the sigma-delta DAC and the DFG had a performance that is consistent with our optimized design, and the noise was as expected from the noise simulation. Finally, we have confirmed that the DFG worked successfully during the flight of the sounding rocket. (paper)

  4. Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters:State-of-the-Art and a Design Example

    Institute of Scientific and Technical Information of China (English)

    Sheng-Gang Dong; Xiao-Yang Wang; Hua Fan; Jun-Feng Gao; Qiang Li

    2013-01-01

    This paper makes a review of state-of-the-arts designs of successive-approximation register analog-to-digital converters (SAR ADCs). Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert (DAC) and comparator to settle. The 10 bit ADC is simulated in 0.13μm CMOS process technology. The signal-to-noise and distortion ratio (SNDR) is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330μW.

  5. Connect high speed analog-digital converter with EPICS based on LabVIEW

    International Nuclear Information System (INIS)

    This paper introduce a method to connect high speed analog-digital converter (ADC212/100) with EPICS on Windows platform using LabVIEW. We use labVIEW to communicate with the converter, then use interface sub-VIs between LabVIEW and EPICS to access the EPICS IOC by Channel Access (CA). For the easy use graph programming language of LabVIEW, this method could shorten the develop period and reduce manpower cost. (authors)

  6. Design of a low-power flash analog-to-digital converter chip for temperature sensors in 0.18 µm CMOS process

    Directory of Open Access Journals (Sweden)

    Al Al

    2015-01-01

    Full Text Available Current paper proposes a simple design of a 6-bit flash analog-to-digital converter (ADC by process in 0.18 μm CMOS. ADC is expected to be used within a temperature sensor which provides analog data output having a range of 360 mV to 560 mV. The complete system consisting of three main blocks, which are the threshold inverter quantization (TIQ-comparator, the encoder and the parallel input serial output (PISO register. The TIQ-comparator functions as quantization of the analog data to the thermometer code. The encoder converts this thermometer code to 6-bit binary code and the PISO register transforms the parallel data into a data series. The design aims to get a flash ADC on low power dissipation, small size and compatible with the temperature sensors. The method is proposed to set each of the transistor channel length to find out the threshold voltage difference of the inverter on the TIQ comparator. A portion design encoder and PISO registers circuit selected a simple circuit with the best performance from previous studies and adjusted to this system. The design has an input range of 285 to 600 mV and 6-bit resolution output. The chip area of the designed ADC is 844.48 x 764.77 µm2 and the power dissipation is 0.162 µW with 1.6 V supply voltage.

  7. A 12-Bit High-Speed Column-Parallel Two-Step Single-Slope Analog-to-Digital Converter (ADC for CMOS Image Sensors

    Directory of Open Access Journals (Sweden)

    Tao Lyu

    2014-11-01

    Full Text Available A 12-bit high-speed column-parallel two-step single-slope (SS analog-to-digital converter (ADC for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC’s linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors.

  8. A 12-bit high-speed column-parallel two-step single-slope analog-to-digital converter (ADC) for CMOS image sensors.

    Science.gov (United States)

    Lyu, Tao; Yao, Suying; Nie, Kaiming; Xu, Jiangtao

    2014-01-01

    A 12-bit high-speed column-parallel two-step single-slope (SS) analog-to-digital converter (ADC) for CMOS image sensors is proposed. The proposed ADC employs a single ramp voltage and multiple reference voltages, and the conversion is divided into coarse phase and fine phase to improve the conversion rate. An error calibration scheme is proposed to correct errors caused by offsets among the reference voltages. The digital-to-analog converter (DAC) used for the ramp generator is based on the split-capacitor array with an attenuation capacitor. Analysis of the DAC's linearity performance versus capacitor mismatch and parasitic capacitance is presented. A prototype 1024 × 32 Time Delay Integration (TDI) CMOS image sensor with the proposed ADC architecture has been fabricated in a standard 0.18 μm CMOS process. The proposed ADC has average power consumption of 128 μW and a conventional rate 6 times higher than the conventional SS ADC. A high-quality image, captured at the line rate of 15.5 k lines/s, shows that the proposed ADC is suitable for high-speed CMOS image sensors. PMID:25407903

  9. Apple interface for experimental instrumentation and control-Pulse counter, timer, digital-to-analog converter, step motor and relays

    International Nuclear Information System (INIS)

    An interface plate for Apple II type microcomputer developed aiming to automatize measuring systems in which a TTL pulse counter, output of analogic voltage (with resolution of 12 bits), out put of step-motor control, relay drive, and timer for real time control, are necessary to carry-out the parallel tasks, is described. An application of this plate to a thermoluminescence reader is also presented. (M.C.K.)

  10. A Photonic Analog to Digital Convert Technology with Time Stretched Preprocessor%一种基于时间展宽的光模数转换技术

    Institute of Scientific and Technical Information of China (English)

    张晓兴; 谭中伟; 李博; 盛晓娟

    2011-01-01

    基于时间展宽的光模数转换技术通过在采样量化之前对模拟信号进行时域上的展宽,可大大提高模数转换器(ADC)的性能。介绍了这种技术的基本原理,分析了基于此技术的并行ADC采样结构的性能,并对该结构与传统并行采样结构进行了比较,结果证明,该技术具有高采样率、大有效输入带宽以及高分辨率等优势。%A photonic time stretched analog to digital conversion has been proposed. With this technology, the analogue signal is stretched in time domain prior to sampling and quantization. It can improve the performance of analog to digital converter (ADC) significantly. The principle of it is summarized, the characteristics of the parallel ADC sampling structure based on this technology are analyzed, and compared with those of traditional parallel sampling structure. The results show that the technolog~r has some advantages such as high sampling rate, large effective input bandwidth, and high resolution.

  11. Estimation of channel mismatches in time-interleaved analog-to-digital converters based on fractional delay and sine curve fitting.

    Science.gov (United States)

    Guo, Lianping; Tian, Shulin; Jiang, Jun

    2015-03-01

    This paper proposes an algorithm to estimate the channel mismatches in time-interleaved analog-to-digital converter (TIADC) based on fractional delay (FD) and sine curve fitting. Choose one channel as the reference channel and apply FD to the output samples of reference channel to obtain the ideal samples of non-reference channels with no mismatches. Based on least square method, the sine curves are adopted to fit the ideal and the actual samples of non-reference channels, and then the mismatch parameters can be estimated by comparing the ideal sine curves and the actual ones. The principle of this algorithm is simple and easily understood. Moreover, its implementation needs no extra circuits, lowering the hardware cost. Simulation results show that the estimation accuracy of this algorithm can be controlled within 2%. Finally, the practicability of this algorithm is verified by the measurement results of channel mismatch errors of a two-channel TIADC prototype. PMID:25832264

  12. Design of A high performance low-power consumption discrete time Second order Sigma-Delta modulator used for Analog to Digital Converter

    Directory of Open Access Journals (Sweden)

    Radwene LAAJIMI

    2012-12-01

    Full Text Available This paper presents the design and simulations results of a switched-capacitor discrete time Second order Sigma-Delta modulator used for a resolution of 14 bits Sigma-Delta analog to digital converter. The use of operational amplifier is necessary for low power consumption, it is designed to provide large bandwidth and moderate DC gain. With 0.35µm CMOS technology, the ΣΔ modulator achieves 86 dB dynamic range, and 85 dB signal to noise ratio (SNR over an 80 KHz signal bandwidth with an oversampling ratio (OSR of 88, while dissipating 9.8mW at ±1.5V supply voltage.

  13. Ramp Slope Built-in-Self-Calibration Scheme for Single-Slope Column Analog-to-Digital Converter Complementary Metal-Oxide-Semiconductor Image Sensor

    Science.gov (United States)

    Ham, Seogheon; Jung, Wunki; Lee, Dongmyung; Lee, Yonghee; Han, Gunhee

    2006-02-01

    The conversion gain of a single-slope analog-to-digital converter (ADC) suffers from the process and frequency variations. This ADC gain variation eventually limits the performance of image signal processing (ISP) in a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS). This paper proposes a ramp slope built-in-self-calibration (BISC) scheme for a CIS. The CIS with the proposed BISC was fabricated with a 0.35-μm CMOS process. The measurement results show that the proposed architecture effectively calibrates the ramp slope against the process and the clock frequency variation. The silicon area overhead is less than 0.7% of the full chip area.

  14. Post-Correction of Pipelined Analog-Digital Converters Based on Input Dependent Integral Nonlinearity Modeling

    OpenAIRE

    Samer Medawar; Peter H\\xe4ndel; Niclas Bj\\xf6rsell; Magnus Jansson

    2010-01-01

    The integral nonlinearity (INL) is used for the postcorrection of analog-digital converters (ADCs). An input-frequency-dependent INL model is developed for the postcorrection. The model consists of a static term that is dependent on the ADC output code and a dynamic term that has an additional dependence on the input frequency. The concept of ADC digital output postcorrection by INL is first introduced. The INL model is subtracted from the digital output for postcorrection. The static compens...

  15. Implementation of a 10.24 GS/s 12-bit Optoelectronics Analog-to- Digital Converter Based on a Polyphase Demultiplexing Architecture

    Directory of Open Access Journals (Sweden)

    C. Villa-Angulo

    2013-01-01

    Full Text Available In this paper we present the practical implementation of a high-speed polyphase sampling and demultiplexingarchitecture for optoelectronics analog-to-digital converters (OADCs. The architecture consists of a one-stage divideby-eight decimator circuit where optically-triggered samplers are cascaded to sample an analog input signal, anddemultiplex different phases of the sampled signal to yield low data rate for electronic quantization. Electrical-in toelectrical-out data format is maintained through the sampling, demultiplexing and quantization processes of thearchitecture thereby avoiding the need for electrical-to-optical and optical-to-electrical signal conversions. Weexperimentally demonstrate a 10.24 giga samples per second (GS/s, 12-bit resolution OADC system comprising theoptically-triggered sampling circuits integrated with commercial electronic quantizers. Measurements performed on theOADC yielded an effective bit resolution (ENOB of 10.3 bits, spurious free dynamic range (SFDR of -32 dB andsignal-to-noise and distortion ratio (SNDR of 63.7 dB.

  16. On a possibility of construction of the fast micropower analog-to-digital converter on the base of using charge-coupled devices

    International Nuclear Information System (INIS)

    A possibility of construction of the fast micropower analog-to-digital converter (ADC) on the base of using the charge-coupled devices (CCD) has been considered, and its comparison with the bit coding ADC has been carried out. The results of the analysis of the ADC of both types revealed the 4-5 times gain over occupied area and supply power for the ADC on the base of CCD as compared to the bit coding ADC. Particular amphasis is placed upon the accuracy of conversion in the ADC on the base of CCD. The spread of the charge detector gain has been shown to influence upon the accuracy of conversion. This undesirable effect appears due to the large CCD gate area spread. Possible ways of avoiding the effects of area spread on the conversion accuracy have been indicated. As a result of the study made is a conclusion on the possibility of designing the 8-bit ADC (without analogous units) on the base of 1x1 mm crystal with a response of about several MHz at energy power unit of about hundreds of milliwatts

  17. Low Temperature Testing of a Radiation Hardened CMOS 8-Bit Flash Analog-to-Digital (A/D) Converter

    Science.gov (United States)

    Gerber, Scott S.; Hammond, Ahmad; Elbuluk, Malik E.; Patterson, Richard L.; Overton, Eric; Ghaffarian, Reza; Ramesham, Rajeshuni; Agarwal, Shri G.

    2001-01-01

    Power processing electronic systems, data acquiring probes, and signal conditioning circuits are required to operate reliably under harsh environments in many of NASA:s missions. The environment of the space mission as well as the operational requirements of some of the electronic systems, such as infrared-based satellite or telescopic observation stations where cryogenics are involved, dictate the utilization of electronics that can operate efficiently and reliably at low temperatures. In this work, radiation-hard CMOS 8-bit flash A/D converters were characterized in terms of voltage conversion and offset in the temperature range of +25 to -190 C. Static and dynamic supply currents, ladder resistance, and gain and offset errors were also obtained in the temperature range of +125 to -190 C. The effect of thermal cycling on these properties for a total of ten cycles between +80 and - 150 C was also determined. The experimental procedure along with the data obtained are reported and discussed in this paper.

  18. High-speed analog-to-digital conversion

    CERN Document Server

    Demler, Michael J

    1991-01-01

    This book covers the theory and applications of high-speed analog-to-digital conversion. An analog-to-digital converter takes real-world inputs (such as visual images, temperature readings, and rates of speed) and transforms them into digital form for processing by computer. This book discusses the design and uses of such circuits, with particular emphasis on improving the speed of the conversion process and the accuracy of its output--how well the output is a corresponding digital representation of the output*b1input signal. As computers become increasingly interfaced to the outside world, ""

  19. Ultra-energy-efficient analog-to-digital converters based on single-electron transistor/CMOS hybrid technology for biomedical applications

    International Nuclear Information System (INIS)

    Ultra-energy-efficient analog-to-digital converters (ADCs) based on single-electron transistor (SET)/complementary metal-oxide-semiconductor (CMOS) hybrid technology are proposed as a solution to sense and process biomedical signals. Our results show the energy efficiency of 0.82 pJ/state, which is lower than that in previously reported energy-efficient ADCs. The performance and dissipated power of proposed ADCs are estimated and compared with those of CMOS ADCs by using Lee's SPICE model including non-ideal effects of the experimental data. While the proposed ADC shows an operating power lower by two orders of magnitude than that of the CMOS flash-type ADC, the number of required transistors is about 10% of that in the CMOS flash-type ADC. The peak-to-valley current ratio in Coulomb oscillation of SETs used in the circuit implementation has the range of 1.15–1.5, which is consistent with the experimental result of top-down approached Si-based SETs at T = 77–100 K. From the perspective of the immunity to the gate capacitance Ccg mismatch and the background charge Q0 noise, it is shown that the criteria of SET/CMOS hybrid ADCs are ΔCcg ≤ 0.02 × Ccg (with Ccg = 0.24 aF) and ΔQ0 ≤ 0.23q, respectively

  20. Successive approximation-like 4-bit full-optical analog-to-digital converter based on Kerr-like nonlinear photonic crystal ring resonators

    Science.gov (United States)

    Tavousi, Alireza; Mansouri-Birjandi, Mohammad Ali; Saffari, Mehdi

    2016-09-01

    Implementing of photonic sampling and quantizing analog-to-digital converters (ADCs) enable us to extract a single binary word from optical signals without need for extra electronic assisting parts. This would enormously increase the sampling and quantizing time as well as decreasing the consumed power. To this end, based on the concept of successive approximation method, a 4-bit full-optical ADC that operates using the intensity-dependent Kerr-like nonlinearity in a two dimensional photonic crystal (2DPhC) platform is proposed. The Silicon (Si) nanocrystal is chosen because of the suitable nonlinear material characteristic. An optical limiter is used for the clamping and quantization of each successive levels that represent the ADC bits. In the proposal, an energy efficient optical ADC circuit is implemented by controlling the system parameters such as ring-to-waveguide coupling coefficients, the ring's nonlinear refractive index, and the ring's length. The performance of the ADC structure is verified by the simulation using finite difference time domain (FDTD) method.

  1. Design challenges of EO polymer based leaky waveguide deflector for 40 Gs/s all-optical analog-to-digital converters

    Science.gov (United States)

    Hadjloum, Massinissa; El Gibari, Mohammed; Li, Hongwu; Daryoush, Afshin S.

    2016-08-01

    Design challenges and performance optimization of an all-optical analog-to-digital converter (AOADC) is presented here. The paper addresses both microwave and optical design of a leaky waveguide optical deflector using electro-optic (E-O) polymer. The optical deflector converts magnitude variation of the applied RF voltage into variation of deflection angle out of a leaky waveguide optical beam using the linear E-O effect (Pockels effect) as part of the E-O polymer based optical waveguide. This variation of deflection angle as result of the applied RF signal is then quantized using optical windows followed by an array of high-speed photodetectors. We optimized the leakage coefficient of the leaky waveguide and its physical length to achieve the best trade-off between bandwidth and the deflected optical beam resolution, by improving the phase velocity matching between lightwave and microwave on one hand and using pre-emphasis technique to compensate for the RF signal attenuation on the other hand. In addition, for ease of access from both optical and RF perspective, a via-hole less broad bandwidth transition is designed between coplanar pads and coupled microstrip (CPW-CMS) driving electrodes. With the best reported E-O coefficient of 350 pm/V, the designed E-O deflector should allow an AOADC operating over 44 giga-samples-per-seconds with an estimated effective resolution of 6.5 bits on RF signals with Nyquist bandwidth of 22 GHz. The overall DC power consumption of all components used in this AOADC is of order of 4 W and is dominated by power consumption in the power amplifier to generate a 20 V RF voltage in 50 Ohm system. A higher sampling rate can be achieved at similar bits of resolution by interleaving a number of this elementary AOADC at the expense of a higher power consumption.

  2. a 9-BIT, Pipelined Gallium Arsenide Analog-Digital Converter

    Science.gov (United States)

    Breevoort, Cornelius Marius

    1992-01-01

    Excellent Short Take-Off and Landing (STOL) performance is achieved by Upper Surface Blowing (USB) aircraft as a result of mounting high by-pass turbofan engines over the forward part of the wing. High lift levels are generated by directing the engine exhaust over the wing upper surface to entrain additional airflow and by using the Coanda effect to turn the exhaust flow downward over a large radius "Coanda" flap. Commercial application of USB technology could reduce airport congestion and community noise if future configurations can be designed with economically acceptable cruise drag levels. An experimental investigation of the high speed aerodynamics of USB aircraft configurations has been conducted to accurately define the magnitude and causes of the powered configuration cruise drag. A highly instrumented wind tunnel model of a realistic USB configuration has been used which permitted parametric variations in the number and spanwise location of the nacelles and accurately modeled the engine power effects with turbofan propulsion simulators. The measured force data provides an accurate definition of the cruise drag penalty associated with each configuration and the constructed pressure contour plots provide detailed insight into their causes. It was found that the high speed aerodynamics of USB configurations is a complex interaction of jet induced and wing transonic flowfields. The presence of the nacelles on the wing upper surface created a severe drag penalty which increased with freestream Mach number, power setting and angle of attack. The more widely spaced two nacelle configurations exhibited improved flowfields at moderate Mach numbers but suffered from drag levels comparable to the baseline configuration for high speed cruise conditions. At high Mach numbers and power settings, all of the tested configurations displayed strong shocks and separated zones in the wing/nacelle junction regions. Detailed discussions of the causes of the cruise drag penalty

  3. Square-root pulse amplitude-to-digital converter

    International Nuclear Information System (INIS)

    A device for converting pulse amplitudes from gas-discharged detectors of ionizing radiations to digits is described. Minimum of losses of energy resolution, expenditure of operating memory volume, spectrum set and processing times are provided with use a linear atomic numbers scale and constancy of peak widths of x-ray spectrum. The converter is placed on two separate circuit boards of an analogous amplitude-time converter (ATC) and digital control unit. The signal amplitude in ATC is compared with periodical reference voltage of a parabolic form generated with two analogous integrators. For 256 channels a maximum dead system time is 25.6 μs, mean time-13 μs, amplitude range-0.1-6v, pulse duration - 0.3-300 μs. The converter described is used for a long time under laboratory and field corditiosns in a portable x-ray spectrometer

  4. Xampling: Analog to Digital at Sub-Nyquist Rates

    OpenAIRE

    Mishali, Moshe; Eldar, Yonina C.; Dounaevsky, Oleg; Shoshan, Eli

    2009-01-01

    We present a sub-Nyquist analog-to-digital converter of wideband inputs. Our circuit realizes the recently proposed modulated wideband converter, which is a flexible platform for sampling signals according to their actual bandwidth occupation. The theoretical work enables, for example, a sub-Nyquist wideband receiver, which has no prior information on the transmitter carrier positions. Our design supports input signals with 2 GHz Nyquist rate and 120 MHz spectrum occupancy, with arbitrary tra...

  5. A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

    International Nuclear Information System (INIS)

    A power-efficient 12-bit 40-MS/s pipeline analog-to-digital converter (ADC) implemented in a 0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two opamp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode (RFC) amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC's performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range (SFDR) of 75.7 dB and a signal-to-noise-plus-distortion ratio (SNDR) of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.43 to +0.48 LSB and −1.62 to +1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure-of-merit (FOM) of 0.63 pJ per conversion-step. (semiconductor integrated circuits)

  6. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    International Nuclear Information System (INIS)

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015

  7. Design of a 10-bit segmented current-steering digital-to-analog converter in CMOS 65 nm technology for the bias of new generation readout chips in high radiation environment

    Science.gov (United States)

    De Robertis, G.; Loddo, F.; Mattiazzo, S.; Pacher, L.; Pantano, D.; Tamma, C.

    2016-01-01

    A new pixel front end chip for HL-LHC experiments in CMOS 65nm technology is under development by the CERN RD53 collaboration together with the Chipix65 INFN project. This work describes the design of a 10-bit segmented current-steering Digital-to-Analog Converter (DAC) to provide a programmable bias current to the analog blocks of the circuit. The main requirements are monotonicity, good linearity, limited area consumption and radiation hardness up to 10 MGy. The DAC was prototyped and electrically tested, while irradiation tests will be performed in Autumn 2015.

  8. An introduction to analog and digital communications

    CERN Document Server

    Haykin, Simon

    2012-01-01

    The second edition of this accessible book provides readers with an introductory treatment of communication theory as applied to the transmission of information-bearing signals. While it covers analog communications, the emphasis is placed on digital technology. It begins by presenting the functional blocks that constitute the transmitter and receiver of a communication system. Readers will next learn about electrical noise and then progress to multiplexing and multiple access techniques.

  9. The SAMPIC Waveform and Time to Digital Converter

    OpenAIRE

    Delagnes, E.; Breton, D.; H. Grabas; Maalmi, J.; Rusquart, P.; Saimpert, M.

    2014-01-01

    Sce Electronique International audience SAMPIC is a Waveform and Time to DigitalConverter (WTDC) multichannel chip. Each of its 16 channelsassociates a DLL-based TDC providing a raw time with an ultrafastanalog memory allowing fine timing extraction as well asother parameters of the pulse. Each channel also integrates adiscriminator that can trigger itself independently or participateto a more complex trigger. After triggering, analog data isdigitized by an on-chip ADC and only that cor...

  10. Analog to digital control system replacement projects

    International Nuclear Information System (INIS)

    Problem Statement: Numerous Control Systems within Operating Nuclear Units are nearing or at the end of their useful life. These systems are typically Analog in design, installed and commissioned during original construction dates. Problems associated with these aging system which are plaging Nuclear Operators are Obsolescence, Inadequate Spares, Complexity in Troubleshooting large hardwired systems, Eroding Experience and Device Failures leading to safety and economic impacts. There are a number of factors to consider when attempting to justify a complete system replacement versus a component by component replacement. This presentation will look at some of these systems which have been chosen for replacement and discuss the rationale used to drive this digital upgrade decision. Specific project related concerns due to the digital technology such as Software Qualification shall be addressed. Also specific to hybrid main control rooms is the Human Factors requirements when replacing analog controllers and meters with Touch Screen based HMI. One aspect of the Nuclear Power Plants which traditionally differs from other industry is the requirement for Full Scope Simulator for training purposes. This presention will identify the importance of the full scope simulator and the role it plays in digital system replacements. Other topics to be discussed in proposed presentation include: - Probablistic Risk Assessment; - Stakeholder Involvement; - New Technology Benefits; - New Technology 'Traps'; - Security; - Phased Acceptance Testing. The proposed presentation shall be in a PowerPoint format

  11. Design and realization of a high-speed 12-bit pipelined analog-digital converter IP block

    OpenAIRE

    Toprak, Zeynep

    2001-01-01

    This thesis presents the design, verification, system integration and the physical realization of a monolithic high-speed analog-digital converter (ADC) with 12-bit accuracy. The architecture of the ADC has been realized as a pipelined structure consisting of four pipeline stages, each of which is capable of processing the incoming analog signal with 4-bit accuracy. A bit-overlapping technique has been employed for digital error correction between the pipeline stages so that the influence of ...

  12. A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

    OpenAIRE

    M. Rezvanyvardom; E. Farshidi

    2015-01-01

    This paper investigates a novel cyclic time-to-digital converter (TDC) which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop). The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT) variations. The other advantages of the propo...

  13. 高速光学模数转换器的研究现状及进展%Research status and progress of high-speed optical analog-to-digital converters

    Institute of Scientific and Technical Information of China (English)

    范修宏; 颜璟; 徐磊; 张尚剑; 刘永

    2012-01-01

    高速高精度模数转换器(Analog-to-digital Converters,ADC)是现代数字信息处理系统中的关键组成部分,现有的电子模数转换器存在运行速率严重受限的难题,因此引入光学方法实现高速高精度模数转换成为研究的热点。本文重点针对高速光学模数转换器的研究现状及进展进行了探讨,并对光学辅助、光采样电量化、电采样光量化以及全光采样量化目前4种最主要的光学模数转换器的原理、结构和最新的研究进展进行了详细的介绍。%High speed and high resolution Analog-to-Digital Converter is a key part in the information processing system,the current electronic ADCs have difficulties for achieving high speed operation,so it becomes a hot research topic to introduce optic method into ADC area for high speed operation.In this paper,the current research situation and development of the high-speed optical ADC are discussed,we introduce the system structures and working principles,as well as latest research progress.In particular,we present the four main types of analog-to-digital converters in detail,i.e.photonic assisted ADC,photonic sampled and quantized ADC,photonic quantized and electronically sampled ADC,photonic sampled and quantized ADC.

  14. Focal plane analog-to-digital conversion development

    Science.gov (United States)

    Mandl, William J.

    1995-05-01

    An on focal plane analog to digital conversion approach has been implemented for infrared sensor application. This development uses a patented oversampling methodology named MOSAD (Multiplexed OverSample Analog to Digital) in the design of simple circuits that can be placed at individual pixel sites. The construction of an analog to digital converter pixel is allowed with this technology. Most of the crosstalk and broadband noise associated with analog multiplexing and readout is avoided. Two demonstration designs were developed and built with Orbit, 1.2 micron CMOS Foresight process. For cost reasons, both designs were placed on the small die, 4.8 X 4.8 mm, and packaged in a 84 pin grid array carrier. These designs consist of a scanning array, 1 X 64 on 60 micron centers and two column portion of a 64 X 64 staring array on 60 micron centers. The detector buffer design will support HgCdTe high background applications. Support for the demonstration was received from Army, Night Vision Laboratory under their two color detector SBIR development program.

  15. Spectroscopy analogue-to-digital converters

    International Nuclear Information System (INIS)

    A review of world trends in the branch of electronic constructions for spectroscopy analogue-to-digital converters (ADC) applied in different fields of nuclear physics and techniques has been done. Data sheets and graphical comparison of main parameters for ADC that have appeared in world literature are also added. Recent methods applied for conversion of voltage pulse amplitude with linear coding scale have been described. Future trends up to year 1990 anticipating the increase of spectroscopy ADC resolution up to 15 bits and the shortening of ADC conversion time down to 1 μs have been presented. The dynamic development of very fast converters with low accuracy has been predicted. Present ADC are capable of sampling pulses from nuclear detectors with repetition rate up to 100 MHz. Examples of different correction methods for deleting ADC measurement errors show that both hardware and software tools may be used. On the ground of these methods one can use for spectroscopy ADC design commercially available integrated circuits with large scale integration. Then good metrology parameters, simplicity of realization and small overall dimensions may be obtained. These correction methods make a compromise between speed and precision of ADC operation possible. 81 refs., 22 figs., 3 tabs. (author)

  16. Efficiency and hardware comparison of analog control-based and digital control-based 70 W two-stage power factor corrector and DC-DC converters

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2011-01-01

    A comparison of an analog and a digital controller driven 70 W two-stage power factor corrector converter is presented. Both controllers are operated in average current-mode-control for the PFC and peak current control for the DC-DC converter. Digital controller design and converter modeling is...

  17. The Transition from Analog to Digital Mammography: Overall Considerations

    Directory of Open Access Journals (Sweden)

    A. Sardo

    2007-05-01

    Full Text Available In the last decades a continuous growth of the infor-matics process around the world has been observed: paper documents, data, images…, converted into a “digital format” allow an easier and safer manage-ment, making possible its compatibility and access to internet networking. This migration confirms the huge technology progresses made especially in the image capture ways: from photography to graphic arts, from movie to healthcare imaging, where the end user/radiologist requires, at least, a digital clinical image with a quality equivalent to the previous ana-log film image. In women’s breast imaging care mammography is acknowledged as the most effective method to detect a breast cancer at an earlier stage and it is currently the only imaging modality, which has been proven to reduce mortality in women screened from 50 to 69 years. The transition to Digital Mammography represents a challenge to decide when to change the first concern is to get the money availability to purchase a Digital Mammography system and the well-trained human resources (radiologist, technician and physicist for using it. A digital system must satisfy actual needs such as the diagnostic accuracy, dose and regulatory requirements, productivity and archive issues. The new digital modality must be integrated in a fully digital environment (PACS and the presence of CR or DR systems for general radiography could condi-tion the choice of CR or DR Digital Mammography system. The Primary goal of mammography (both analog and digital is to provide to the radiologist clinical images for confident interpretation. Certainly the confidence derives from radiologist’s experience in reading mammograms, but many other factors can increase it, for instance correct patient positioning, excellent and consistent image quality (photographic and artifacts free, easy use and interpretation aid (e.g. lens, CAD use of imaging system. However, the habit in read-ing film-images on view box

  18. A Column-Parallel Hybrid Analog-to-Digital Converter Using Successive-Approximation-Register and Single-Slope Architectures with Error Correction for Complementary Metal Oxide Silicon Image Sensors

    Science.gov (United States)

    Li, Tsung-Ling; Sakai, Shin; Kawada, Shun; Goda, Yasuyuki; Wakashima, Shunichi; Kuroda, Rihito; Sugawa, Shigetoshi

    2013-04-01

    In this paper, a column-parallel hybrid analog-to-digital converter (ADC) architecture taking the advantages of both successive-approximation-register (SAR) and single-slope (SS) architectures has been developed for CMOS image sensors. The proposed architecture achieves high conversion speed and low power consumption without requiring a high clock frequency and a large number of capacitors. Moreover, an error correction methodology has been presented to calibrate capacitance mismatches in a SAR capacitor array for linearity improvement. An 11-bit hybrid prototype ADC has been implemented in a 0.18-µm 1-poly 5-metal standard CMOS process. The conversion time is 1.225 µs with a maximum operation clock frequency of 40 MHz and it consumes 48 µW. With the proposed error correction, the measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.40/-0.44 least significant bit (LSB) and +1.21/-1.12 LSB, respectively.

  19. A digital silicon photomultiplier with multiple time-to-digital converters

    International Nuclear Information System (INIS)

    A silicon photomultiplier (SiPM) with pixel level signal digitization and column-wise connected time-to-digital converters (TDCs) has been developed for an endoscopic Positron Emission Tomography (PET) detector. A digital SiPM has pixels consist of a single photon avalanche diode (SPAD) and circuit elements to optimize overall dark counts and temporal response. Compared with conventional analog SiPM, digital SiPM's direct signal route from SPAD to TDC improves single photon time resolution. In addition, using multiple TDCs can perform the statistical estimation of the time-of-arrival in multiple photon detection case such as readout of scintillation crystals. Characterization measurements of the prototype digital SiPM and a Monte-Carlo simulation to predict the timing performance of the PET detector are shown.

  20. A Methodology to Teach Advanced A/D Converters, Combining Digital Signal Processing and Microelectronics Perspectives

    Science.gov (United States)

    Quintans, C.; Colmenar, A.; Castro, M.; Moure, M. J.; Mandado, E.

    2010-01-01

    ADCs (analog-to-digital converters), especially Pipeline and Sigma-Delta converters, are designed using complex architectures in order to increase their sampling rate and/or resolution. Consequently, the learning of ADC devices also encompasses complex concepts such as multistage synchronization, latency, oversampling, modulation, noise shaping,…

  1. Digital and analog communication systems

    Science.gov (United States)

    Shanmugam, K. S.

    1979-01-01

    The book presents an introductory treatment of digital and analog communication systems with emphasis on digital systems. Attention is given to the following topics: systems and signal analysis, random signal theory, information and channel capacity, baseband data transmission, analog signal transmission, noise in analog communication systems, digital carrier modulation schemes, error control coding, and the digital transmission of analog signals.

  2. High-Performance DA-Converters Application to Digital Transceivers

    CERN Document Server

    Clara, Martin

    2013-01-01

    This book deals with modeling and implementation of high performance, current-steering D/A-converters for digital transceivers in nanometer CMOS technology. In the first part, the fundamental performance limitations of current-steering DACs are discussed. Based on simplified models, closed-form expressions for a number of basic non-ideal effects are derived and tested.  With the knowledge of basic performance limits, the converter and system architecture can be optimized in an early design phase, trading off circuit complexity, silicon area and power dissipation for static and dynamic performance. The second part describes four different current-steering DAC designs in standard 130 nm CMOS. The converters have a resolution in the range of 12-14 bits for an analog bandwidth between 2.2 MHz and 50 MHz and sampling rates from 100 MHz to 350 MHz. Dynamic-Element-Matching (DEM) and advanced dynamic current calibration techniques are employed to minimize the required silicon area.

  3. Synchronization sampling method based on delta-sigma analog-digital converter for underwater towed array system.

    Science.gov (United States)

    Jiang, Jia-Jia; Duan, Fa-Jie; Li, Yan-Chao; Hua, Xiang-Ning

    2014-03-01

    Synchronization sampling is very important in underwater towed array system where every acquisition node (AN) samples analog signals by its own analog-digital converter (ADC). In this paper, a simple and effective synchronization sampling method is proposed to ensure synchronized operation among different ANs of the underwater towed array system. We first present a master-slave synchronization sampling model, and then design a high accuracy phase-locked loop to synchronize all delta-sigma ADCs to a reference clock. However, when the master-slave synchronization sampling model is used, both the time-delay (TD) of messages traveling along the wired transmission medium and the jitter of the clocks will bring out synchronization sampling error (SSE). Therefore, a simple method is proposed to estimate and compensate the TD of the messages transmission, and then another effective method is presented to overcome the SSE caused by the jitter of the clocks. An experimental system with three ANs is set up, and the related experimental results verify the validity of the synchronization sampling method proposed in this paper. PMID:24689606

  4. A DSP-based, analog-to-digital convertor for nuclear radiation spectroscopy

    International Nuclear Information System (INIS)

    A new, digital signal processor (DSP)-based system is under development for analyzing and processing pulses produced by radiation detectors. A DSP-based system will be capable of advanced features for all types of radiation spectroscopy systems (e.g., pulse validation, pulse shape analysis, dynamic threshold determination, and noise reduction) with fewer and simpler electronics for increased reliability, reduced electronic noise, and less expense. A prototype system has been built, and performance parameters are being evaluated. The analysis of a pulse from radiation detectors is currently performed by converting the peak of the detector pulse from analog form to digital form with a peak detection analog-to-digital converter (ADC). To accomplish this, the pulse from the detector is first amplified and shaped. The peak of the pulse is captured and subsequently converted to digital form

  5. A Novel Cyclic Time to Digital Converter Based on Triple-Slope Interpolation and Time Amplification

    Directory of Open Access Journals (Sweden)

    M. Rezvanyvardom

    2015-09-01

    Full Text Available This paper investigates a novel cyclic time-to-digital converter (TDC which employs triple-slope analog interpolation and time amplification techniques for digitizing the time interval between the rising edges of two input signals(Start and Stop. The proposed converter will be a 9-bit cyclic time-to-digital converter that does not use delay lines in its structure. Therefore, it has a low sensitivity to temperature, power supply and process (PVT variations. The other advantages of the proposed converter are low circuit complexity, and high accuracy compared with the time-to-digital converters that have previously been proposed. Also, this converter improves the time resolution and the dynamic range. In the same resolution, linear range and dynamic range, the proposed cyclic TDC reduces the number of circuit elements compared with the converters that have a similar circuit structure. Thus, the converter reduces the chip area, the power consumption and the figure of merit (FoM. In this converter, the integral nonlinearity (INL and differential nonlinearity (DNL errors are reduced. In order to evaluate the idea, the proposed time-to-digital converter is designed in TSMC 45 nm CMOS technology and simulated. Comparison of the theoretical and simulation results confirms the benefits of the proposed TDC.

  6. Converting Taxonomic Descriptions to New Digital Formats

    Directory of Open Access Journals (Sweden)

    Hong Cui

    2008-01-01

    Full Text Available Abstract.--The majority of taxonomic descriptions is currently in print format. The majority of digital descriptions are in formats such as DOC, HTML, or PDF and for human readers. These formats do not convey rich semantics in taxonomic descriptions for computer-aided process. Newer digital formats such as XML and RDF accommodate semantic annotations that allow computers to process the rich semantics on human's behalf, thus open up opportunities for a wide range of innovative usages of taxonomic descriptions, such as searching in more precise and flexible ways, integrating with gnomic and geographic information, generating taxonomic keys automatically, and text data mining and information visualization etc. This paper discusses the challenges in automated conversion of multiple collections of descriptions to XML format and reports an automated system, MARTT. MARTT is a machine-learning system that makes use of training examples to tag new descriptions into XML format. A number of utilities are implemented as solutions to the challenges. The utilities are used to reduce the effort for training example preparation, to facilitate the creation of a comprehensive schema, and to predict system performance on a new collection of descriptions. The system has been tested with several plant and alga taxonomic publications including Flora of China and Flora of North America.

  7. A PWM Buck Converter With Load-Adaptive Power Transistor Scaling Scheme Using Analog-Digital Hybrid Control for High Energy Efficiency in Implantable Biomedical Systems.

    Science.gov (United States)

    Park, Sung-Yun; Cho, Jihyun; Lee, Kyuseok; Yoon, Euisik

    2015-12-01

    We report a pulse width modulation (PWM) buck converter that is able to achieve a power conversion efficiency (PCE) of > 80% in light loads 100 μA) for implantable biomedical systems. In order to achieve a high PCE for the given light loads, the buck converter adaptively reconfigures the size of power PMOS and NMOS transistors and their gate drivers in accordance with load currents, while operating at a fixed frequency of 1 MHz. The buck converter employs the analog-digital hybrid control scheme for coarse/fine adjustment of power transistors. The coarse digital control generates an approximate duty cycle necessary for driving a given load and selects an appropriate width of power transistors to minimize redundant power dissipation. The fine analog control provides the final tuning of the duty cycle to compensate for the error from the coarse digital control. The mode switching between the analog and digital controls is accomplished by a mode arbiter which estimates the average of duty cycles for the given load condition from limit cycle oscillations (LCO) induced by coarse adjustment. The fabricated buck converter achieved a peak efficiency of 86.3% at 1.4 mA and > 80% efficiency for a wide range of load conditions from 45 μA to 4.1 mA, while generating 1 V output from 2.5-3.3 V supply. The converter occupies 0.375 mm(2) in 0.18 μm CMOS processes and requires two external components: 1.2 μF capacitor and 6.8 μH inductor. PMID:26742139

  8. Methods of reducing errors in amplitude-to-digital converters

    International Nuclear Information System (INIS)

    Most pulse analysers use the Wilkinson principle of amplitude-to-digital conversion because of its inherent simplicity. This paper analyses the various causes of inaccuracy in such converters and describes means of overcoming them. The paper then describes the principles of a new converter which uses largely semiconductor devices. The new converter possesses a high degree of channel-width uniformity and channel-position stability over a large dynamic range of pulse amplitudes. Methods of measuring converters to a high precision are also discussed. (author)

  9. Low-Power, Low-Voltage Analog to Digital ΣΔ

    DEFF Research Database (Denmark)

    Wismar, Ulrik Sørensen

    2007-01-01

    implementations of audio band modulators used as CMOS analog to digital converters. The intended application is hearing aids where analog to digital converters are used to convert the preamplied signal from a microphone into a digital signal which is fed into a microprocessor. A hearing aid is battery driven, and...... since long operation time is required, low supply voltage and low power consumption are of paramount importance. Consequently, various topologies have been compared to nd the most power ecient audio frequency modulator topology. Chapter 4 of this thesis compares power consumption of two of the most...... prevalent topologies, the single-loop modulator with integration in discrete time and the single-loop modulator with integration in continuous time. Both modulator topologies are with feedback, and all intermediate signals are in the voltage mode. Chapter 5 treats a modulator without feedback. Another...

  10. Sub-picosecond Resolution Time-to-Digital Converter

    Energy Technology Data Exchange (ETDEWEB)

    Ph D, Vladimir Bratov; Ph D, Vladimir Katzman; MS EE, Jeb Binkley

    2006-03-30

    Time-to-digital converters with sub-picosecond resolutions are needed to satisfy the requirements of time-on-flight measurements of the next generation of high energy and nuclear physics experiments. The converters must be highly integrated, power effective, low cost, and feature plug-and-play capabilities to handle the increasing number of channels (up to hundreds of millions) in future Department of Energy experiments. Current state-off-the-art time-to-digital converter integrated circuits do not have the sufficient degree of integration and flexibility to fulfill all the described requirements. During Phase I, the Advanced Science and Novel Technology Company in cooperation with the nuclear physics division of the Oak Ridge National Laboratory has developed the architecture of a novel time-to-digital converter with multiple channels connected to an external processor through a special interfacing block and synchronized by clock signals generated by an internal phase-locked loop. The critical blocks of the system including signal delay lines and delay-locked loops with proprietary differential delay cells, as well as the required digital code converter and the clock period counter have been designed and simulated using the advanced SiGe120 BiCMOS technological process. The results of investigations demonstrate a possibility to achieve the digitization accuracy within 1ps. ADSANTEC has demonstrated the feasibility of the proposed concept in computer simulations. The proposed system will be a critical component for the next generation of NEP experiments.

  11. Analog circuit design scalable analog circuit design, high speed D/A converters, RF power amplifiers

    CERN Document Server

    Huijsing, Johan

    2007-01-01

    Preface. Part I: Scalable Analog Circuit Design. Introduction. Scalable High-Speed Analog Circuit Design; M. Vertregt, P. Scholtens. Scalable High Resolution Mixed Mode Circuit Design; R.J. Brewer. Scalable 'High Voltages' Integrated Circuit Design for XDSL Type of Applications; D. Rossi. Scalability of Wire-Line Analog Front-Ends; K. Bult. Reusable IP Analog Circuit Design; J. Hauptmann, A. Wiesbauer, H. Weinberger. Process Migration Tools for Analog and Digital Circuits; K. Francken, G. Gielen. Part II: High-Speed D/A Converters. Introduction. Introduction to High-Speed Digital-to-Analog Con

  12. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    International Nuclear Information System (INIS)

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ''KLauS' developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track and hold circuit

  13. Low power Analog Digital Converter for a silicon photomultiplier readout ASIC

    Science.gov (United States)

    Briggl, K.; Chen, H.; Shen, W.; Schultz-Coulon, H. C.

    2015-04-01

    We present an ADC designed in the UMC 0.18um CMOS technology. It will be used in the SiPM analog front-end ``KLauS" developed for the analog hadronic calorimeter at ILD. Key parameter in this application is an extremely low power consumption of the front-end electronics. For quantization of the energy depositions, a 10-bit ADC resolution is required. For calibration purposes, a 12-bit quantization is used. A successive approximation register split capacitor array structure is chosen to minimize the DC power consumption. A peak sensing block is used to minimize the required sampling rate. We present design details and simulation results of the ADC, as well as the peak sensing track & hold circuit.

  14. Programmable bivariate-analysis unit based on high-speed analog-digital converter

    International Nuclear Information System (INIS)

    A unit is described that consists of logic circuits for event sampling and converts input parameters (tin or time) to code and generates a logic signal whose presence is determined by memory contents. The unit has two channels that operate in a range of up to ∼ 100 pC. The unit can be used as a time-to-number converter if a current generator is connected to the input of each channel. The unit employs a K500RU415 RAM chip and two K1107PV3B 6-bit time-conversion ADCs with ECL outputs. The unit has a resolving time of ∼ 110 nsec and a recovery time of ∼ 350 nsec. The unit is CAMAC-compatible and is contained in a module of size 1M

  15. A Binary-Weighted Photonic Digital-to-Analogue Converter

    OpenAIRE

    Abdollahi, SR; Al-Raweshidy, HS; Owens, TJ

    2016-01-01

    In fifth-generation (5G) mobile networks the available bandwidth and the range of carrier frequencies will be significantly larger than in current mobile networks. To cope with the consequent increase in traffic 5G networks will be Digital Radio over Fibre (DRoF) networks for deploying cloud radio access networks (CRAN). As conventional electronic data converters in DRoF networks suffer from jitter at very high giga sampling rates while photonic data converters have better perform...

  16. A Multiphase Interpolator for the Time-To-Digital Converters

    CERN Document Server

    Rusanov, I R

    2000-01-01

    An interpolation algorithm for time-to-digital converter based on he direct transformation method is described in the work. The new measuring algorithm is designed for application in the TDC for readout of information from the drift chamber. The new multiphase digital interpolators permit to achieve the high time resolution of T_e/8, where T_e is a period of clock generator.

  17. A high-linearity digital-to-time converter technique: constant-slope charging

    OpenAIRE

    Ru, Jiayoon Zhiyu; Palattella, Claudia; Geraedts, Paul; Klumperink, Eric; Nauta, Bram

    2015-01-01

    A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL) compared to the popular variable-slope method. The proposed DTC chip realized in 65 nm CMOS consists of a voltage-controlled variable-delay element (DTC-core) driven by a 10 bit digital-to-analog...

  18. A Comparative study of Analog and digital Controller On DC/DC Buck-Boost Converter Four Switch for Mobile Device Applications

    Directory of Open Access Journals (Sweden)

    Benlafkih Abdessamad

    2013-01-01

    Full Text Available this paper presents comparative performance between Analog and digital controller on DC/DC buck-boost converter four switch. The design of power electronic converter circuit with the use of closed loop scheme needs modeling and then simulating the converter using the modeled equations. This can easily be done with the help of state equations and MATLAB/SIMULINK as a tool for simulation of those state equations. DC/DC Buckboost converter in this study is operated in buck (step-down and boost (step-up modes.

  19. A Comparative study of Analog and digital Controller On DC/DC Buck-Boost Converter Four Switch for Mobile Device Applications

    OpenAIRE

    Benlafkih Abdessamad; Krit Salah-Ddine; Chafik Elidrissi Mohamed

    2013-01-01

    this paper presents comparative performance between Analog and digital controller on DC/DC buck-boost converter four switch. The design of power electronic converter circuit with the use of closed loop scheme needs modeling and then simulating the converter using the modeled equations. This can easily be done with the help of state equations and MATLAB/SIMULINK as a tool for simulation of those state equations. DC/DC Buckboost converter in this study is operated in buck (step-down) and boost ...

  20. Current to frequency converter for digitization of millisecond beam signals

    International Nuclear Information System (INIS)

    Beam-intensity monitoring in the Fermilab Neutrino Area requires sensitive and fast processing for beam signals (with four or five decade amplitude variations for a typical detector) which are digitized with a current-to-frequency converter (IFC). The converter digitizes the input charge at a 1 pC/Hz rate with a processing limit at 10 MHz for a 10 nC charge input or a 10 ;mu;A current input. For a 1 ms beam pulse, the IFC can generate a 1 to 10,000 count output. The digitizer is two to three decades more sensitive than the fastest commercial V to F converters and the upper frequency limit is two or three decades higher than the present laboratory built IFC's. The resolution over the 0 to 50 C temperature range and the linearity from 1 Hz to 1 MHz is held to ;plus or minus;1% with a linearity deviation of +5% at 10 MHz. 3 refs

  1. The Transition from Analog to Digital Mammography: Overall Considerations

    OpenAIRE

    A. Sardo

    2007-01-01

    In the last decades a continuous growth of the infor-matics process around the world has been observed: paper documents, data, images…, converted into a “digital format” allow an easier and safer manage-ment, making possible its compatibility and access to internet networking. This migration confirms the huge technology progresses made especially in the image capture ways: from photography to graphic arts, from movie to healthcare imaging, where the end user/radiologist requires, at least, a ...

  2. TPC Readout Electronics with Time-to-Digital Converters

    CERN Document Server

    Kaukher, Alexander

    2009-01-01

    Development of readout electronics for Time Projection Chamber for a Linear Collider is ongoing under stringent requirements on high channel density, lowest possible power consumption and small material budget. In the studied TPC readout electronics time and charge of TPC signals are measured with the help of Time-to-Digit Converters. Optimization of performance of this electronics is considered and a methodology of signal simulation is presented.

  3. New system for digital to analog transformation and reconstruction of 12-lead ECGs.

    Directory of Open Access Journals (Sweden)

    Roshni Kothadia

    Full Text Available INTRODUCTION: We describe initial validation of a new system for digital to analog conversion (DAC and reconstruction of 12-lead ECGs. The system utilizes an open and optimized software format with a commensurately optimized DAC hardware configuration to accurately reproduce, from digital files, the original analog electrocardiographic signals of previously instrumented patients. By doing so, the system also ultimately allows for transmission of data collected on one manufacturer's 12-lead ECG hardware/software into that of any other. MATERIALS AND METHODS: To initially validate the system, we compared original and post-DAC re-digitized 12-lead ECG data files (∼5-minutes long in two types of validation studies in 10 patients. The first type quantitatively compared the total waveform voltage differences between the original and re-digitized data while the second type qualitatively compared the automated electrocardiographic diagnostic statements generated by the original versus re-digitized data. RESULTS: The grand-averaged difference in root mean squared voltage between the original and re-digitized data was 20.8 µV per channel when re-digitization involved the same manufacturer's analog to digital converter (ADC as the original digitization, and 28.4 µV per channel when it involved a different manufacturer's ADC. Automated diagnostic statements generated by the original versus reconstructed data did not differ when using the diagnostic algorithm from the same manufacturer on whose device the original data were collected, and differed only slightly for just 1 of 10 patients when using a third-party diagnostic algorithm throughout. CONCLUSION: Original analog 12-lead ECG signals can be reconstructed from digital data files with accuracy sufficient for clinical use. Such reconstructions can readily enable automated second opinions for difficult-to-interpret 12-lead ECGs, either locally or remotely through the use of dedicated or cloud

  4. Analog-to-Digital Conversion to Accommodate the Dynamics of Live Music in Hearing Instruments

    Science.gov (United States)

    Bahlmann, Frauke; Fulton, Bernadette

    2012-01-01

    Hearing instrument design focuses on the amplification of speech to reduce the negative effects of hearing loss. Many amateur and professional musicians, along with music enthusiasts, also require their hearing instruments to perform well when listening to the frequent, high amplitude peaks of live music. One limitation, in most current digital hearing instruments with 16-bit analog-to-digital (A/D) converters, is that the compressor before the A/D conversion is limited to 95 dB (SPL) or less at the input. This is more than adequate for the dynamic range of speech; however, this does not accommodate the amplitude peaks present in live music. The hearing instrument input compression system can be adjusted to accommodate for the amplitudes present in music that would otherwise be compressed before the A/D converter in the hearing instrument. The methodology behind this technological approach will be presented along with measurements to demonstrate its effectiveness. PMID:23258618

  5. Analog and digital signal analysis from basics to applications

    CERN Document Server

    Cohen Tenoudji, Frédéric

    2016-01-01

    This book provides comprehensive, graduate-level treatment of analog and digital signal analysis suitable for course use and self-guided learning. This expert text guides the reader from the basics of signal theory through a range of application tools for use in acoustic analysis, geophysics, and data compression. Each concept is introduced and explained step by step, and the necessary mathematical formulae are integrated in an accessible and intuitive way. The first part of the book explores how analog systems and signals form the basics of signal analysis. This section covers Fourier series and integral transforms of analog signals, Laplace and Hilbert transforms, the main analog filter classes, and signal modulations. Part II covers digital signals, demonstrating their key advantages. It presents z and Fourier transforms, digital filtering, inverse filters, deconvolution, and parametric modeling for deterministic signals. Wavelet decomposition and reconstruction of non-stationary signals are also discussed...

  6. Efficient Circuit Configuration for Enhancing Resolution of 8-bit flash Analog to Digital Convertor

    Directory of Open Access Journals (Sweden)

    Gururaj Balikatti

    2012-11-01

    Full Text Available The need constantly exists for converters with higher resolution, faster conversion speeds and lower power dissipation. High speed analog to digital converters (ADCs have been based on flash architecture, because all comparators sample the analog input voltage simultaneously, this ADC is thus inherently fast. Unfortunately flash ADC requires 2N - 1 comparators to convert N bit digital code from an analog sample. This makes flash ADCs unsuitable for high resolution applications. The focus of this paper is on efficient circuit configuration to enhance resolution of available 8-bit flash ADC, while maintaining number of comparators only 256 for 12 bit conversion. This technique optimizes the number of comparator requirements. In this approach, an 8-bit flash ADC partitions the analog input range into 256 quantization cells, separated by 255 boundary points. An 8-bit binary code 00000000 to 11111111 is assigned to each cell. The Microcontroller decides within which cell the input sample lies and assigns a 12-bit binary center code 000000000000 to 111111111111 according to the cell value. The exact 12-bit digital code is obtained by successive approximation technique. In this paper the focus will be on all-around efficient circuit for enhancing resolution of 8-bit Flash ADC. It is shown that by adopting this configuration, we can obtain 12-bit digital data just using 256 comparators. Therefore this technique is best suitable when high speed combined with high resolution is required. An experimental prototype of proposed 12-bit ADC was implemented using Philips P89V51RD2BN Microcontroller. Use of Microcontroller has greatly reduced the hardware requirement and cost. An ADC result of 12-bit prototype is presented. The results show that the ADC exhibits a maximum DNL of 0.52LSB and a maximum INL of 0.55LSB.

  7. From Analog to Digital Medias in Early Childhood Education

    DEFF Research Database (Denmark)

    Brandt, Erika Zimmer

    2015-01-01

    in a mixed-methods design based on field observation and interviews (Frederiksen, Gundelach and Skovgaard Nielsen 2014) Paradigm, methodology and methods Special sensitivity is directed towards how the dialog between children and educators develops, when they use tablets in educational practice. Ethical......Research aims: The aim of the study is to explore how the encounters between children and their educators alter when the media changes from analog to digital. Relationship to previous research works Tablets and other handheld, electronic devices has become part of everyday life in kindergartens....... Research shows that there are both potential pedagogical difficulties and possibilities connected to using digital media (ex. Thestrup 2015, Tække and Paulsen 2014) Theoretical and conceptual framework: The study is a single case study of an educational experiment (Flyvbjerg 2006). It is carried out...

  8. Low resource FPGA-based Time to Digital Converter

    OpenAIRE

    Balla, A.; Beretta, M.; Ciambrone, P.; Gatta, M.; Gonnella, F.; Iafolla, L.; M. Mascolo; Messi, R.; Moricciani, D.; Riondino, D.

    2012-01-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is no...

  9. Frequency to digital converter for IUAC Linac control system

    International Nuclear Information System (INIS)

    A frequency to digital converter CAMAC module has been designed and developed for LINAC control systems. This module is used to see the frequency difference of master clock and the resonator frequency digitally without using the oscilloscope. Later on this can be used for automatic tuning and locking of the cavities using piezoelectric actuator based tunner control. This module has eight independent channels to fulfill the need of all the eight cavities of the cryostat. A Schmitt trigger along with level converaccepts almost any form of pulse train, with 30 Vp-p. The time period is measured by counters clocked from a high resolution clock (10 MHz +/- 250 ps). The counter values are cross checked at both the input levels. Frequency is obtained from the computed time period by a special divisor core implemented inside the FPGA. The major task was the implementation of eight individual divisor cores and routing inside one Spartan 3s500E FPGA chip

  10. Implementation of Power Efficient Flash Analogue-to-Digital Converter

    Directory of Open Access Journals (Sweden)

    Taninki Sai Lakshmi

    2014-01-01

    Full Text Available An efficient low power high speed 5-bit 5-GS/s flash analogue-to-digital converter (ADC is proposed in this paper. The designing of a thermometer code to binary code is one of the exacting issues of low power flash ADC. The embodiment consists of two main blocks, a comparator and a digital encoder. To reduce the metastability and the effect of bubble errors, the thermometer code is converted into the gray code and there after translated to binary code through encoder. The proposed encoder is thus implemented by using differential cascade voltage switch logic (DCVSL to maintain high speed and low power dissipation. The proposed 5-bit flash ADC is designed using Cadence 180 nm CMOS technology with a supply rail voltage typically ±0.85 V. The simulation results include a total power dissipation of 46.69 mW, integral nonlinearity (INL value of −0.30 LSB and differential nonlinearity (DNL value of −0.24 LSB, of the flash ADC.

  11. Simplified 2-bit photonic digital-to-analog conversion unit based on polarization multiplexing

    Science.gov (United States)

    Zhang, Fangzheng; Gao, Bindong; Ge, Xiaozhong; Pan, Shilong

    2016-03-01

    A 2-bit photonic digital-to-analog conversion unit is proposed and demonstrated based on polarization multiplexing. The proposed 2-bit digital-to-analog converter (DAC) unit is realized by optical intensity weighting and summing, and its complexity is greatly reduced compared with the traditional 2-bit photonic DACs. Performance of the proposed 2-bit DAC unit is experimentally investigated. The established 2-bit DAC unit achieves a good linear transfer function, and the effective number of bits is calculated to be 1.3. Based on the proposed 2-bit DAC unit, two DAC structures with higher (>2) bit resolutions are proposed and discussed, and the system complexity is expected to be reduced by half by using the proposed technique.

  12. Focal plane array readout integrated circuit with per-pixel analog-to-digital and digital-to-analog conversion

    Science.gov (United States)

    Kleinfelder, Stuart; Hottes, Alison; Pease, R. Fabian W.

    2000-07-01

    A pixel array readout integrated circuit (ROIC) containing per-pixel analog-to-digital conversion (ADC) and digital-to- analog conversion (DAC) for infrared detectors is presented with design and test result details. Fabricated in a standard 0.35 micron, 3.3 volt CMOS technology. the prototype consists of a linear array of 64 pixels, containing over 100 transistors per 30 by 30 micron pixel. The 8-bit per-pixel ADC is a Nyquist-rate single-slope design consisting of a three stage comparator and an 8 bit memory. This fully pixel- parallel ADC architecture operates in full-frame 'snapshot' mode and can reach over 1,000 frames per second. Each pixel also contains cascoded current source, globally biased to subtract an identical, fixed amount of current from each pixel in order to remove a common background signal by 'charge skimming.' It operates over more than 3 decades of current cancellation (approximately 10 pA to > 10 nA). As well, each pixel contains a 4 to 6+ bit current-mode DAC, intended to trim-out pixel-to-pixel variations in background current. It consists of 16 unit-cells of switched cascoded current sources per pixel, organized as two separately biased weights and controlled by a 16-bit per-pixel memory. The DAC operates over more than 4 decades of current cancellation (< 10 pA to approximately equals 100 nA) per least significant bit (LSB).

  13. FPGA based sigma –Delta analogue to digital converter design

    Directory of Open Access Journals (Sweden)

    P. A. Uchagaonkar

    2012-03-01

    Full Text Available This paper reports design and development of modified Sigma- Delta ADC realized in FPGA paradigm. The wide gain of this ADC makes it a potential candidate in data converter applications in wide ranging domains such as communication systems, instrumentation, precision measurement devices and manyothers wherein the high resolution precision converter is essential. The proposed architecture encompasses of mixed mode design in which few of the analog and up to 90% digital blocks have been realized on a single platform. The digital building blocks have been tested and implemented in Xilinx ISE with the help of MATLAB system generator tool and instantiated on Spartan 3e FPGA. System performance has been ascertained using the hardware co-simulation and further post verified on the Xilinx analyzer tool.

  14. Photonic Analog-to-Digital Conversion of Time-Continuous Signals using a TDM Switching-Wavelength Sampling Source

    Institute of Scientific and Technical Information of China (English)

    K.; L.; Lee; M.; P.; Fok; C.; Shu

    2003-01-01

    A 20 Gsample/s photonic analog-to-digital converter is constructed using a 4-switching-wavelength repetitive sampling pulse source. The signal-to-noise and distortion ratio (SINAD) is measured to be 44.5 dB and corresponds to 7 effective number of bits.

  15. Configurable analog-digital conversion using the neural engineering framework

    OpenAIRE

    Christian G Mayr; Partzsch, Johannes; Noack, Marko; Schüffny, Rene

    2014-01-01

    Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and...

  16. The GANDALF 128-Channel Time-to-Digital Converter

    Science.gov (United States)

    Büchele, M.; Fischer, H.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

    The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabric is a particular challenge of this design. We present measurement results for the time resolution and the nonlinearity of the TDC readout system.

  17. The GANDALF 128-Channel Time-to-Digital Converter

    CERN Document Server

    Büchele, Maximilian; Herrmann, Florian; Königsmann, Kay; Schill, Christian; Schopferer, Sebastian

    2011-01-01

    The GANDALF 6U-VME64x/VXS module has been designed to cope with a variety of readout tasks in high energy and nuclear physics experiments, in particular the COMPASS experiment at CERN. The exchangeable mezzanine cards allow for an employment of the system in very different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition or fast trigger generation. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In this concept each input signal is continuously sampled by 16 flip-flops using equidistant phase-shifted clocks. Compared to previous FPGA designs, usually based on delay lines and comprising few TDC channels with resolutions in the order of 10 ps, our design permits the implementation of a large number of TDC channels with a resolution of 64 ps in a single FPGA. Predictable placement of logic components and uniform routing inside the FPGA fabr...

  18. Analogue to Digital and Digital to Analogue Converters (ADCs and DACs): A Review Update

    CERN Document Server

    Pickering, J

    2015-01-01

    This is a review paper updated from that presented for CAS 2004. Essentially, since then, commercial components have continued to extend their performance boundaries but the basic building blocks and the techniques for choosing the best device and implementing it in a design have not changed. Analogue to digital and digital to analogue converters are crucial components in the continued drive to replace analogue circuitry with more controllable and less costly digital processing. This paper discusses the technologies available to perform in the likely measurement and control applications that arise within accelerators. It covers much of the terminology and 'specmanship' together with an application-oriented analysis of the realisable performance of the various types. Finally, some hints and warnings on system integration problems are given.

  19. Converting To Digital Library in Banking Organizations : Case Study For Library of Central Bank of Libya

    OpenAIRE

    Asmaa Basher Abou Louefa

    2005-01-01

    A Case study For Library of Central Bank of Libya, it deals the converting to a digital library. It start with an introduction about digital libraries, and technology in libraries, then deal Library of Central Bank of Libya, and it current situation, then states the plan to be converted to digital library.

  20. Converting To Digital Library in Banking Organizations : Case Study For Library of Central Bank of Libya

    Directory of Open Access Journals (Sweden)

    Asmaa Basher Abou Louefa

    2005-05-01

    Full Text Available A Case study For Library of Central Bank of Libya, it deals the converting to a digital library. It start with an introduction about digital libraries, and technology in libraries, then deal Library of Central Bank of Libya, and it current situation, then states the plan to be converted to digital library.

  1. Proton-induced single event upset characterisation of a 1 giga-sample per second analog to digital converter; Caracterisation de la sensibilite aux upsets induits par les protons d'un convertisseur analogique numerique de 1 giga-echantillons par seconde

    Energy Technology Data Exchange (ETDEWEB)

    Reed, R.A. [NASA/GSFC Greenbelt, MD (United States); Marshall, P.W. [NASA/GSFC Greenbelt, Consultant, MD (United States); Carts, M.A. [Naval Research Lab., Washington (United States)

    1999-07-01

    The SPT7760 is an analog to digital converter that is used in satellite for digital processing. In this paper we describe the characterization and analysis of proton-induced single event upsets (SEU) for the SPT7760 operating at sample rates from 125 Msps (Mega-samples per second) to 1 Gsps. The SEU cross-section has been measured as a function of sample rate for various input levels. The data collected is clearly non-linear for all cases. The data shows that this device has a relative low cross-section for proton-induced SEUs and remains functional at a proton dose of 580 krad (Si). (A.C.)

  2. Capacitive digital-to-analogue converters with least significant bit down in differential successive approximation register ADCs

    Directory of Open Access Journals (Sweden)

    Lei Sun

    2014-01-01

    Full Text Available This Letter proposes a least significant bit-down switching scheme in the capacitive digital-to-analogue converters (CDACs of successive approximation register analog-to-digital converter (ADC. Under the same unit capacitor, the chip area and the switching energy are halved without increasing the complexity of logic circuits. Compared with conventional CDAC, when it is applied to one of the most efficient switching schemes, V(cm-based structure, it achieves 93% less switching energy and 75% less chip area with the same differential non linearity (DNL/integral non linearity (INL performance.

  3. The GANDALF 128-channel time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Baumann, Tobias; Buechele, Maximilian; Fischer, Horst; Gorzellik, Matthias; Grussenmeyer, Tobias; Herrmann, Florian; Joerg, Philipp; Kremser, Paul; Kunz, Tobias; Michalski, Christoph; Schopferer, Sebastian; Szameitat, Tobias [Physikalisches Institut, Freiburg Univ. (Germany)

    2013-07-01

    In particle physics experiments, Time-to-Digital Converters (TDC) perform accurate time measurements, thus to allow for charged particle identification and tracking. We have developed within the GANDALF framework a 128-channel TDC, implemented in a Xilinx Virtex-5 FPGA. A time resolution better than 93 ps has been verified for all channels. In contrast to previous FPGA-based TDC, the design makes use of a shifted clock sampling algorithm. In this concept, the input signal is sampled with flip-flops driven by a set of equidistant phase-shifted clocks. The TDC register length depends only on the number of phase-shifted clocks and therefore permits to process a large number of channels in a very resource-efficient way. As not only time measurements but also simultaneous rate measurements are required for many applications, we present a combination of 96 scaler and TDC channels implemented in the same FPGA on the GANDALF 6U-VME64x/VXS carrier board. In addition to the experiment trigger, an internal generated pseudo-random trigger is applied in order to produce two independent data streams. This may allow for online monitoring of the detector device.

  4. Low resource FPGA-based Time to Digital Converter

    CERN Document Server

    Balla, A; Ciambrone, P; Gatta, M; Gonnella, F; Iafolla, L; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2...

  5. Digital generating converters with heightened sensibility for controlling systems

    OpenAIRE

    Ivanov V.V.; Shakurskiy V. K.; Nagaev D. A.

    2008-01-01

    The authors propose to implement known generating analog converters in a digital form. Realization of heightened sensibility effect of self-oscillating systems in digital producers allows to increase their sensibility and acquire new kinds of transformations. The paper presents results of computer simulation.

  6. Analog versus digital: How human perception adapts to new film aesthetics

    OpenAIRE

    Loertscher, Miriam Laura; Weibel, David; FLUECKIGER, Barbara; Spiegel, Simon; Mennel, Pierre; Mast, Fred; Groner, Rudolf; Iseli, Christian

    2015-01-01

    The digital revolution changed film production in many ways. But so far, nobody has com- pared complete narrative films captured with analog and digital cinematography empir- ically. In two cinema experiments (356 participants in experiment 1, 137 participants in experiment 2), we tested whether digital and analog recording methods are perceived dif- ferently. Eye tracking analysis of 67 participants was carried out to compare the perception of typical film scenes. The two capturing technolog...

  7. Transitioning from analog to digital communications: An information security perspective

    Science.gov (United States)

    Dean, Richard A.

    1990-01-01

    A summary is given of the government's perspective on evolving digital communications as they affect secure voice users and approaches for operating during a transition period to an all digital world. An integrated architecture and a mobile satellite interface are discussed.

  8. Note: All-digital pulse-shrinking time-to-digital converter with improved dynamic range

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, Yi; Chen, Guan-Hong

    2016-04-01

    This paper proposes an all-digital pulse-shrinking time-to-digital converter (TDC) using the offset error cancellation circuitry to widen its dynamic range and to improve its accuracy. Although the TDC based on a pulse-shrinking mechanism can achieve a sub-gate resolution without circuit complexity, it possesses an undesired offset error that results in a nonzero lower bound appeared in its dynamic range and then affects its accuracy. The proposed cancellation circuitry for eliminating the offset error consists of a time adder with a delay line and a time subtractor with an identical delay line. The experimental TDC is implemented on Xilinx field programmable gate arrays and it also functions successfully in improving its dynamic range.

  9. Analog and digital signal processing

    Science.gov (United States)

    Baher, H.

    The techniques of signal processing in both the analog and digital domains are addressed in a fashion suitable for undergraduate courses in modern electrical engineering. The topics considered include: spectral analysis of continuous and discrete signals, analysis of continuous and discrete systems and networks using transform methods, design of analog and digital filters, digitization of analog signals, power spectrum estimation of stochastic signals, FFT algorithms, finite word-length effects in digital signal processes, linear estimation, and adaptive filtering.

  10. Optical Analog-to-digital Conversion Scheme Based on Tunable Fabry-Perot Resonator

    Institute of Scientific and Technical Information of China (English)

    LI Zheng

    2007-01-01

    Proposed is an interference type of optical analog-to-digital conversion(ADC). The refractive index of Fabry-Perot cavity changes with different voltages. The Fabry-Perot resonator converts electronic intensity into light wavelength through selecting lights of different wavelengthes. The parameters of the scheme are acquired with the transmission matrix of optical element and the time of steady-state light field. The maximum sampling speedes of 4-bit, 6-bit, 7-bit, 8-bit and 9-bit(ADC) are 1.695×1010 count/s, 4.33×109 count/s, 2.38×109 count/s, 1.24×109 count/s and 5.9×108 count/s, respectively.

  11. New System for Digital to Analog Transformation and Reconstruction of 12-Lead ECGs

    OpenAIRE

    Roshni Kothadia; Kulecz, Walter B; Kofman, Igor S.; Black, Adam J.; Grier, James W.; Schlegel, Todd T

    2013-01-01

    INTRODUCTION: We describe initial validation of a new system for digital to analog conversion (DAC) and reconstruction of 12-lead ECGs. The system utilizes an open and optimized software format with a commensurately optimized DAC hardware configuration to accurately reproduce, from digital files, the original analog electrocardiographic signals of previously instrumented patients. By doing so, the system also ultimately allows for transmission of data collected on one manufacturer's 12-lead E...

  12. Conversion of a servomanipulator from analog to digital control

    International Nuclear Information System (INIS)

    Oak Ridge National Laboratory (ORNL) has developed expertise in computer control of force-reflecting master/slave servomanipulators as a result of research for the Consolidated Fuel Reprocessing Program. These computer control capabilities have been applied to a commercially available servomanipulator, the TeleOperator Systems SM-229. All of the servo drive and control circuitry has been replaced with commercially available digital controls and amplifiers, and a customer software - package has been developed at ORNL. This conversion to digital computer control resulted in significant improvements in force-reflection characteristics, ease of operation, diagnostic capabilities, indexing features, and potential increased reliability. The system will be used at the Tokamak Fusion Test Reactor at the Princeton Plasma Physics Laboratory (PPPL) for maintenance demonstrations

  13. The Sea As Sculptress—From Analog to Digital

    OpenAIRE

    Wallen, Ruth

    2009-01-01

    In this paper I consider the potential of digital technology to raise ecological awareness and motivate change, focusing on my artwork, The Sea As Sculptress, a macrophotographic record of the marine life growing on sculptures I placed in the San Francisco Bay. Originally presented thirty years ago as a performative lecture with slide dissolves, I recently redesigned and updated the project as an extensive web site. Here, I present the initial context and intention of the project and then out...

  14. 7.9 pJ/Step Energy-Efficient Multi-Slope 13-bit Capacitance-to-Digital Converter

    KAUST Repository

    Omran, Hesham

    2014-08-01

    In this brief, an energy-efficient capacitance-to-digital converter (CDC) is presented. The proposed CDC uses digitally controlled coarse-fine multi-slope integration to digitize a wide range of capacitance in short conversion time. Both integration current and frequency are scaled, which leads to significant improvement in the energy efficiency of both analog and digital circuitry. Mathematical analysis for circuit nonidealities, noise, and improvement in energy efficiency is provided. A prototype fabricated in a 0.35-μm CMOS process occupies 0.09 mm2 and consumes a total of 153 μA from 3.3 V supply while achieving 13-bit resolution. The operation of the prototype is experimentally verified using MEMS capacitive pressure sensor. Compared to recently published work, the prototype achieves an excellent energy efficiency of 7.9 pJ/Step. © 2004-2012 IEEE.

  15. A digital to time converter with fully digital calibration scheme for ultra-low power ADPLL in 40 nm CMOS

    OpenAIRE

    Wang, Bindi; Liu, Yao-Hong; Harpe, Pieter; Staszewski, Robert Bogdan; et al.

    2015-01-01

    In this paper, a digital-to-time converter (DTC) assisting a time-to-digital converter (TDC) as a fractional phase error detector in an ultra-low power ADPLL is proposed and demonstrated in 40nm CMOS. A phase prediction algorithm via the assistance of the DTC reduces the required TDC range, thus saving substantial power. Additionally, a fully digital calibration algorithm is presented and proved to validate the whole ADPLL system and improve the DTC linearity. At 1 V supply voltage, the measu...

  16. A high-linearity digital-to-time converter technique: constant-slope charging

    NARCIS (Netherlands)

    Ru, Jiayoon Zhiyu; Palattella, Claudia; Geraedts, Paul; Klumperink, Eric; Nauta, Bram

    2015-01-01

    A digital-to-time converter (DTC) controls time delay by a digital code, which is useful, for example, in a sampling oscilloscope, fractional-N PLL, or time-interleaved ADC. This paper proposes constant-slope charging as a method to realize a DTC with intrinsically better integral non-linearity (INL

  17. Gluing Lidar Signals Detected in Analog-to-Digital and Photon Counting Modes

    Science.gov (United States)

    Feng, Chang-Zhong; Liu, Bing-Yi; Liu, Jin-Tao; Wu, Song-Hua

    2016-06-01

    Lidar is one of the most effective tools for atmospheric remote sensing. For a ground-based lidar system, the backscattered light usually has large dynamic range. Photon-counting mode has the capability to measure weak signal from high altitude, while Analog-to-Digital mode with better linearity is good at measuring strong signal at low altitude. In some lidar systems, atmospheric return signal is measured in both Analog-to-Digital and Photon Counting modes and combined into an entire profile by using a gluing algorithm. A method for gluing atmospheric return signal is developed and tested. For the Photon Counting signal, the saturation characteristics are analyzed to calculate the coefficients for correction. Then the Analog-to-Digital and Photon Counting signals are glued by a weighted average process. Results show the glued signal is reliable at both low and high altitudes.

  18. Renewal of HOR Nuclear Instrumentation. From Analog to Digital System

    International Nuclear Information System (INIS)

    This paper describes the renewal of the nuclear instrumentation of the research reactor named HOR in Delft. This research reactor was built around 1960. Because of ageing effects, the nuclear instrumentation was completely replaced in 1980, together with the construction of a new control room outside the containment. In 2010, after 30 years of successful operation, it became a real challenge to repair the nuclear channels because of obsolete components. Of course, this problem was identified earlier, and a project was started in 2008 to select and replace the electronics of the nuclear channels. For this purpose a European tender was started to select a manufacturer for the new electronics in accordance with the requirements. The boundary conditions to be fulfilled by the manufacturer were: a) The functionality of the instrumentation and the interface to the plant should remain the same, and b) The proposed type of equipment should have been installed and commissioned successfully at other research reactors of comparable type earlier. Only the electronics should be replaced, detectors and cabling are reused. We selected a digital system based on two microcontrollers, each one checking the other one. It turned out to be a flexible system. It was easily adapted to our needs, showing adequate provisions for guaranteeing data integrity. In the summer maintenance period of 2010 the instrumentation was successfully installed and commissioned. This paper will describe the steps taken and the tests performed. (author)

  19. A Novel Analog-to-digital conversion Technique using nonlinear duty-cycle modulation

    Directory of Open Access Journals (Sweden)

    Jean Mbihi

    2012-06-01

    Full Text Available A new type of analog-to-digital conversion technique is presented in this paper. The interfacing hardware is a very simple nonlinear circuit with 1-bit modulated output. As a implication, behind the hardware simplicity retained is hidden a dreadful nonlinear duty-cycle modulation ratio. However, the overall nonlinear behavior embeds a sufficiently wide linear range, for a rigorous digital reconstitution of the analog input signal using a standard linear filter. Simulation and experimental results obtained using a well tested prototyping system, show the feasibility and good quality of the proposed conversion technique.

  20. Comparison of three approaches on DSP based digital controlled 2-wheeler forward converter

    OpenAIRE

    Lau, CK; Pong, MH

    1994-01-01

    This paper presents the design of digital controls of PWM DC-DC converters on a digital signal processor (DSP) based platform. Three digital control approaches are being investigated: discretisation of analog control, digital proportional-integral-derivative (PID) control, and deadbeat control. Simulation results of the three types of control are shown. Experimental results of a 25W 2-wheeler forward converter prototype are presented to verify the design.

  1. Reconfigurable Analog to Digital Converters for Low Power Wireless Applications

    OpenAIRE

    Gustafsson, E. Martin I.

    2008-01-01

    The commercialization of Marconi’s radio transmission and reception, along with the development of integrated circuits in the 1960’s have facilitated many new consumer products for wireless communication, where the mobile phones or handsets are one. These handsets started out as a portable phone, mounted in cars, and have with time added additional services as Short Message Service, and have today become a media center with global positioning, and high-speed internet connection. This has been...

  2. A new forward-scatter visibility sensor based on a universal frequency-to-digital converter

    OpenAIRE

    BARRALES GUADARRAMA, RAYMUNDO; Mocholí Salcedo, Antonio; Rodríguez Rodríguez, M.E.; Barrales Guadarrame, Víctor Rogelio; Vázquez Cerón, Ernesto Rodrigo

    2013-01-01

    Traffic delays attributable to weather conditions may cause an increase in fuel consumption and then an increase in CO2 emissions to the environment. Visibility reduction in roads due to dense fog is a main cause of traffic accidents and possible environmental pollution, hence the importance of deploying fog warning systems. In this article, we present a forward-scatter visibility sensor that uses a quasi-digital photodetector and a universal frequency-to-digital converter instead of a conven...

  3. A sensitive method to measure the integral nonlinearity of a digital-to-time converter based on phase modulation

    NARCIS (Netherlands)

    Palattella, Claudia; Klumperink, Eric A.M.; Ru, Jiayun (Zhiyu); Nauta, Bram

    2015-01-01

    A digital-to-time converter (DTC) produces a time delay based on a digital code. Similar to data converters, linearity is a key metric for a DTC and it can be characterized by its integral nonlinearity (INL). However, measuring the INL of a subpicosecond-resolution DTC is problematic, even when usin

  4. Simplified architecture for photonic analog-to-digital conversion, utilizing an array of optical modulators

    Science.gov (United States)

    Gevorgyan, Hayk; Khilo, Anatol

    2016-03-01

    In this work a novel photonic sampled and electronically quantized analog-to-digital converter (ADC) system is introduced. High overall sampling rate and relaxed analog bandwidth requirements for photodetectors and electronic quantizers are attained by multichannel architecture. The proposed scheme, with a dedicated electro-optic modulator for each of the channels, is much simpler and has a perspective to outreach the performance of a similar time- wavelength demultiplexed photonic ADC. Absolute optical power isolation between the channels completely eliminates the issue of channel crosstalk, resulting in increased power efficiency of the system. Owing to small number of wavelength demultiplexers less wavelength alignment is required, which reduces the complexity of both photonic and electronic subsystems. Due to the significance of having compact, on-chip photonic ADCs, the analysis of integration of proposed system on a silicon platform is performed. The availability of high performance devices in various Si platforms, such as low loss Si waveguides, microring resonator filters, modulators, photodetectors, necessary for building the system, proves that the photonic ADC is well suited for integration on a silicon chip. For integrated version of proposed architecture Si microring resonator modulators are suitable. They are compact, and can have shorter total length of diode phase shifters as compared to Mach-Zehnder modulators, used in time-wavelength demultiplexed photonic ADCs. To achieve large modulation depth and lower nonlinear distortions, the choice of optimum optical bandwidth of microring modulator is analyzed. Finally, the nonlinearity analysis of ring modulators is performed and the influence of nonlinearities on the ADC performance is discussed.

  5. High-speed multiple-channel analog to digital data-acquisition module for microprocessor systems

    International Nuclear Information System (INIS)

    Intelligent data acquisition and instrumentation systems established by the incorporation of microprocessor technology require high-speed analog to digital conversion of multiple-channel input signals. Sophisticated data systems or subsystems are enabled by the microprocessor software flexibility to establish adaptive input data procedures. These adaptive procedures are enhanced by versatile interface circuitry which is software controlled

  6. KM3NeT Neutrino Telescope 1-ns Resolution Time To Digital Converters

    OpenAIRE

    Calvo David; Real Diego

    2016-01-01

    The KM3NeT collaboration aims the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The main digitization system is composed by 31 Time to Digital Converter channels with 1-ns resolution embedded in a Field Programmable Gate Array. An architecture with low resource occupancy has been chosen allowing the implementation of other instrumentation, comm...

  7. Configurable Analog-Digital Conversion Using the Neural EngineeringFramework

    OpenAIRE

    Christian G Mayr; Johannes ePartzsch; Marko eNoack; Rene eSchüffny

    2014-01-01

    Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e. to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and ...

  8. Design of a Time-to-Digital Converter for an All-Digital Phase Locked Loop for the 2-GHz Band

    OpenAIRE

    Wali, Naveen; Radhakrishnan, Balamurali

    2013-01-01

    An all-digital phase locked loop for WiGig systems was implemented. The developedall-digital phase locked loop has a targeted frequency range of 2.1-GHz to2.5-GHz. The all-digital phase locked loop replaces the traditional charge pumpbased analog phase locked loop. The digital nature of the all-digital phase lockedloop system makes it superior to the analog counterpart.There are four main partswhich constitutes the all-digital phase locked loop. The time-to-digital converteris one of the impo...

  9. Counting photons at low temperature with a streaming time-to-digital converter

    NARCIS (Netherlands)

    Di Stefano, P. C. F.; Nadeau, P.; Onderwater, C. J. G.; Trudeau, C.; Verdier, M. -A.

    2013-01-01

    We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time struct

  10. Time-to-digital converter with generalized measurer of 32 inputs

    International Nuclear Information System (INIS)

    A time-to-digital converter (TDC) intended for signal recording from drift chambers at low loads of the detecting plane is described. TDC principle of operation is based on direct time-to-digit conversion at maximum clock time frequency of 100 MHz. Compression of input data (32 inputs represent two-dimensional matrix 4x8) and following coding of the positional code into a binary one (5 digits) are applied to reduce instrumental costs and TDC disposition in the CAMAC module

  11. The Time-to-Digital Converter with Selection of Time Intervals

    CERN Document Server

    Atanasov, I H

    2000-01-01

    The realisation of the time-to-digital converter with selection of time intervals is described. The method of the selection is based on the use of proframmable delay generator AD9500. The time of the selection of time intervals is 50 ns.

  12. Nyquist AD Converters, Sensor Interfaces, and Robustness Advances in Analog Circuit Design, 2012

    CERN Document Server

    Baschirotto, Andrea; Steyaert, Michiel

    2013-01-01

    This book is based on the presentations during the 21st workshop on Advances in Analog Circuit Design.  Expert designers provide readers with information about a variety of topics at the frontier of analog circuit design, including Nyquist analog-to-digital converters, capacitive sensor interfaces, reliability, variability, and connectivity.  This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.  Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; Presents material in a tutorial-based format; Includes coverage of Nyquist A/D converters, capacitive sensor interfaces, reliability, variability, and connectivity.

  13. KM3NeT Neutrino Telescope 1-ns Resolution Time To Digital Converters

    Directory of Open Access Journals (Sweden)

    Calvo David

    2016-01-01

    Full Text Available The KM3NeT collaboration aims the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The main digitization system is composed by 31 Time to Digital Converter channels with 1-ns resolution embedded in a Field Programmable Gate Array. An architecture with low resource occupancy has been chosen allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The 4-oversampling technique with two high frequency clocks working in opposed phases has been used together with an asymmetric FIFO memory. In the present article the architecture and the first results obtained with the Time to Digital Converters are presented.

  14. KM3NeT Neutrino Telescope 1-ns Resolution Time To Digital Converters

    Science.gov (United States)

    Calvo, David; Real, Diego

    2016-04-01

    The KM3NeT collaboration aims the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean sea consisting of thousands of glass spheres, each of them containing 31 photomultiplier of small photocathode area. The main digitization system is composed by 31 Time to Digital Converter channels with 1-ns resolution embedded in a Field Programmable Gate Array. An architecture with low resource occupancy has been chosen allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The 4-oversampling technique with two high frequency clocks working in opposed phases has been used together with an asymmetric FIFO memory. In the present article the architecture and the first results obtained with the Time to Digital Converters are presented.

  15. Engineering information on an Analog Signal to Discrete Time Interval Converter (ASDT-IC)

    Science.gov (United States)

    Schwarz, F. C.

    1974-01-01

    An electronic control system for nondissipative dc power converters is presented which improves (1) the routinely attainable static output voltage accuracy to the order of + or - 1% for ambient temperatures from -55 to 100 C and (2) the dynamic stability by utilizing approximately one tenth of the feedback gain needed otherwise. Performance is due to a functional philosophy of deterministic pulse modulation based on pulse area control and to an autocompensated signal processing principle. The system can be implemented with commercially available unselected components.

  16. Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers

    Science.gov (United States)

    Bengtsson, Lars E.

    2012-04-01

    This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation.

  17. Implementation of high-resolution time-to-digital converter in 8-bit microcontrollers.

    Science.gov (United States)

    Bengtsson, Lars E

    2012-04-01

    This paper will demonstrate how a time-to-digital converter (TDC) with sub-nanosecond resolution can be implemented into an 8-bit microcontroller using so called "direct" methods. This means that a TDC is created using only five bidirectional digital input-output-pins of a microcontroller and a few passive components (two resistors, a capacitor, and a diode). We will demonstrate how a TDC for the range 1-10 μs is implemented with 0.17 ns resolution. This work will also show how to linearize the output by combining look-up tables and interpolation. PMID:22559576

  18. A new digital control DC-DC converter with peak current -injected control

    OpenAIRE

    Kurokawa, Fujio; Sukita, Shohei; Shibata, Yuichiro; Yokoyama, Tomoki; Sasaki, Masahiro; Mimura, Yasuhiro

    2008-01-01

    This paper presents a new digital control circuit which is able to detect the peak switch current of the high frequency switching dc-dc converter. In this proposed digital control circuit, the peak current-injected control is realized using the combination of the simple dual pulse width modulation analog-to-digital signal converter and the programmed delay circuit. In 100kHz digitally controlled dc-dc converter, it is seen in simulation that the proposed method has no overshoot of the output ...

  19. High resolution heterodyne interferometer based on time-to-digital converter.

    Science.gov (United States)

    Wang, Fei; Long, Zhangcai; Zhang, Bin; Zhao, Meirong

    2012-04-01

    A new heterodyne interferometer is presented, which adopts time-to-digital converter (TDC) measuring the time intervals of zero crossings of heterodyne signal for phase demodulation. Thanks to the 0.1 ns time resolution of TDC and linear phase demodulation, it can achieve high resolution and avoids nonlinear measuring distortion in other indirect high precise phase demodulation methods, such as pulse width modulation (PWM) and in-phase∕quadrature (I∕Q) method. PMID:22559581

  20. CMOS time-to-digital converters for mixed-mode signal processing

    OpenAIRE

    Fei Yuan

    2014-01-01

    This study provides an in-depth review of the principles, architectures and design techniques of CMOS time-to-digital converters (TDCs). The classification of TDCs is introduced. It is followed by the examination of the parameters quantifying the performance of TDCs. Sampling TDCs including direct-counter TDCs, tapped delay-line TDCs, pulse-shrinking delay-line TDCs, cyclic pulse-shrinking TDCs, direct-counter TDCs with interpolation, vernier TDCs, flash TDCs, successive approximation TDCs an...

  1. Digitized self-oscillating loop for piezoelectric transformer-based power converters

    DEFF Research Database (Denmark)

    Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe;

    2016-01-01

    A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise...... frequency control and ensures an optimum operation of the piezoelectric transformer in terms of voltage gain and efficiency. In this work, additional time delay is implemented digitally for the first time through 16 bit digital-to-analog converter to the self-oscillating loop. Delay control setpoints...

  2. Analog controllers using digital stochastic logic

    OpenAIRE

    Quero Reboul, José Manuel; S. L. Toral; García Ortega, Juan de la Cruz; García Franquelo, Leopoldo

    1999-01-01

    Stochastic logic is based on digital processing of a random pulse stream, where the information is codified as the probability of a high level in a finite sequence. The probability of the pulse stream codifies a continuous time variable. Subsequently, this pulse stream can be digitally processed to perform analog operations. In this paper we propose a stochastic approach to the digital implementation of complex controllers. This is approach allows for the realization of the controllers, and A...

  3. Analog-to-digital conversion using custom CMOS analog memory for the EOS time projection chamber

    International Nuclear Information System (INIS)

    This paper reports on an expert system for generating control rod patterns that has been developed. The knowledge is transformed into IF-THEN rules. The inference engine uses the Rete pattern matching algorithm to match facts, and rule premises and conflict resolution strategies to make the system function intelligently. A forward-chaining mechanism is adopted in the inference engine. The system is implemented in the Common Lisp programming language. The three-dimensional core simulation model performs the core status and burnup calculations. The system is successfully demonstrated by generating control rod programming for the 2894-MW (thermal) Kuosheng nuclear power plant in Taiwan. The computing time is tremendously reduced compared to programs using mathematical methods

  4. Transistorized analogue-to-digital converter for pulse-height analysis

    International Nuclear Information System (INIS)

    An analogue-to-digital converter has been built employing a Miller run-down for the linear conversion of a pulse amplitude into time. The input is required in the form of current pulses from a suitable amplifier and delivered through a series gate to the low-impedance input of the converter. The converter proper consists of a current amplifier for charging the storage capacitor of a Miller time-base, with both the amplifier and the Miller time-base forming an integral part of the converter circuit. Voltage feedback from the output stabilizes the amplitude to which the capacitor is charged by incoming pulses. As each pulse passes its peak, the overall feedback loop opens because the storage capacitor is charged through a diode, the latter being cut off during the ''run down'' part of the cycle. However, the Miller part of the converter remains active and causes the storage capacitor to discharge linearily. With the completion of the run-down the overall feedback loop closes again, returning the Miller capacitor to exactly the same quiescent voltage from which its charge had started previously. Thus, the influence of slow DC drifts within the overall feedback loop on the conversion factor is practically eliminated. A crystal oscillator assures the stability of the timing-clock pulses. Phasing problems are eliminated by delaying the start of the discharge until the arrival of a clock pulse. A description of the circuit and performance data is given in the paper.

  5. Modern approaches to the design of analog-digit integrated circuits based on multilevel simulation methods

    International Nuclear Information System (INIS)

    Modern methods for the design of analog and analog-digit integrated circuits have been analyzed. “Top-down” and “bottom-up” design methods are compared. The advantages of the “top-down” method in the rate of the development and verification of integrated circuits have been demonstrated

  6. Configurable analog-digital conversion using the neural engineering framework.

    Science.gov (United States)

    Mayr, Christian G; Partzsch, Johannes; Noack, Marko; Schüffny, Rene

    2014-01-01

    Efficient Analog-Digital Converters (ADC) are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e., to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF). It carries out a large fraction of the overall ADC process in the digital domain, i.e., it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic. PMID:25100933

  7. Approaches and analysis for on-focal-plane analog-to-digital conversion

    Science.gov (United States)

    Pain, Bedabrata; Fossum, Eric R.

    1994-06-01

    This paper presents approaches for on-focal-plane analog-to-digital conversion (ADC). Common approaches and architectures for ADC and their utility for on-focal-plane integration are discussed. Candidate approaches are analyzed with respect to required amplifier gain, bandwidth, capacitance matching, noise and offsets as a function of ADC resolution. A column-parallel ADC architecture appears to be an effective compromise of chip area, power, circuit speed and ADC resolution. The discussion is valid for both infrared focal-plane arrays and visible image sensors.

  8. Note: All-digital CMOS MOS-capacitor-based pulse-shrinking mechanism suitable for time-to-digital converters

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Lin, You-Ting; Liu, Keng-Chih

    2015-12-01

    This paper presents an all-digital CMOS pulse-shrinking mechanism suitable for time-to-digital converters (TDCs). A simple MOS capacitor is used as a pulse-shrinking cell to perform time attenuation for time resolving. Compared with a previous pulse-shrinking mechanism, the proposed mechanism provides an appreciably improved temporal resolution with high linearity. Furthermore, the use of a binary-weighted pulse-shrinking unit with scaled MOS capacitors is proposed for achieving a programmable resolution. A TDC involving the proposed mechanism was fabricated using a TSMC (Taiwan Semiconductor Manufacturing Company) 0.18-μm CMOS process, and it has a small area of nearly 0.02 mm2 and an integral nonlinearity error of ±0.8 LSB for a resolution of 24 ps.

  9. Digital Operation of Microelectronic Circuits Analogous to Protein Hydrogen Bonding Networks

    Directory of Open Access Journals (Sweden)

    Elitsa Gieva

    2012-12-01

    Full Text Available Two hydrogen bonding networks with water molecules and branching residues extracted from β-lactamase protein are investigated and their proton transfer characteristics are studied by creating analogous electrical circuits consisting of block-elements. The block-elements and their proton transfer are described by polynomials that are coded in Matlab and in Verilog-A for use in the Spectre simulator of Cadence IC design system. DC and digital pulse analyses are performed to demonstrate that some circuit outputs behave as repeaters while other - behave as inverters. The results also showed that the HBN circuits might behave as a D-latch and a demultiplexer.

  10. A low cost multi-hit time to digital converter system for drift chamber applications

    International Nuclear Information System (INIS)

    The time to digital converter (TDC) described here is of the common stop type; 16 channels are housed in a single CAMAC module. Minimum time bin width is 7 ns, full scale range is selectable to 6, 7 or 8 bits. Multiple hit capacity is >= 32 hits per wire. Time measurement is performed by one random access memory chip (RAM) per wire and a clocked scaler which is in common for 16 wires. Conversion time is 100 to 500 μs depending on the number of recognized hits and on the full range selected. Converted data are stored in a first-in - last-out memory for convenient computer read out. For operation, the module needs an external clock. (orig.)

  11. Counting photons at low temperature with a streaming time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Di Stefano, P.C.F., E-mail: distefan@queensu.ca [Department of Physics, Engineering Physics and Astronomy, Queen' s University, Kingston, ON, Canada K7L 3N6 (Canada); Nadeau, P. [Department of Physics, Engineering Physics and Astronomy, Queen' s University, Kingston, ON, Canada K7L 3N6 (Canada); Onderwater, C.J.G. [Kernfysisch Versneller Instituut, University of Groningen, NL-9747AA Groningen (Netherlands); Trudeau, C.; Verdier, M.-A. [Department of Physics, Engineering Physics and Astronomy, Queen' s University, Kingston, ON, Canada K7L 3N6 (Canada)

    2013-02-01

    We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time structure of a ZnWO{sub 4} scintillator are comparable to those obtained with a fast digitizer. Streaming data also provides flexibility in analyzing the data, in terms of coincidence window between the channels, and acquisition window of individual channels. We discuss the effect of changing these parameters, and use them to confirm low-energy features in the spectra of the number of detected photons, such as the 60 keV line from {sup 241}Am in the ZnWO{sub 4} sample. We lastly use the TDC to study the transmission of the optical cryostat employed in these studies at various temperatures.

  12. Counting photons at low temperature with a streaming time-to-digital converter

    CERN Document Server

    Di Stefano, P C F; Onderwater, C J G; Trudeau, C; Verdier, M -A

    2012-01-01

    We present some aspects of photon counting to study scintillators at low temperatures. A time-to-digital converter (TDC) had been configured to acquire several-minute-long streams of data, simplifying the multiple photon counting coincidence technique. Results in terms of light yield and time structure of a ZnWO4 scintillator are comparable to those obtained with a fast digitizer. Streaming data also provides flexibility in analyzing the data, in terms of coincidence window between the channels, and acquisition window of individual channels. We discuss the effect of changing these parameters, and use them to confirm low-energy features in the spectra of the number of detected photons, such as the 60 keV line from 241Am in the ZnWO4 sample. We lastly use the TDC to study the transmission of the optical cryostat employed in these studies at various temperatures.

  13. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    International Nuclear Information System (INIS)

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage

  14. A new delay line loops shrinking time-to-digital converter in low-cost FPGA

    Energy Technology Data Exchange (ETDEWEB)

    Zhang, Jie, E-mail: zhangjie071063@163.com [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China); University of Chinese Academy of Sciences, Beijing, China, 100049 (China); Zhou, Dongming [State Key Laboratory of Geodesy and Earth’s Dynamics, Institute of Geodesy and Geophysics, CAS, Wuhan, China, 430077 (China)

    2015-01-21

    The article provides the design and test results of a new time-to-digital converter (TDC) based on delay line loops shrinking method and implemented in a low-cost field programmable gate array (FPGA) device. A technique that achieves high resolution with low cost and flexibility is presented. The technique is based on two delay line loops which are used to directly shrink the measured time interval in the designed TDC, and the resolution is dependent on the difference between the entire delay times of the two delay line loops. In order to realize high resolution and eliminate temperature influence, the two delay line loops consist of the same delay cells with the same number. A delay-locked loop (DLL) is used to stabilize the resolution against process variations and ambient conditions. Meanwhile, one method is used to accurately evaluate the resolution of the implemented TDC. The converter has been implemented in a general-propose FPGA device (Actel SmartFusion A2F200M3). A single shot resolution of the implemented converter is 63.3 ps and the measurement standard deviation is about 61.7 ps within the measurement range of 5 ns. - Highlights: • We provide a new FPGA-integrated time-to-digital converter based on delay line loops method which used two delay line loops to directly shrink time intervals with only rising edges. • The two delay line loops consist of the same delay cells with the same number and symmetrical structure. • The resolution is dependent on the difference between the entire delays of the two delay line loops. • We use delay-locked loop to stabilize the resolution against temperature and supply voltage.

  15. A high-resolution time-to-digital converter using a three-level resolution

    Science.gov (United States)

    Dehghani, Asma; Saneei, Mohsen; Mahani, Ali

    2016-08-01

    In this article, a three-level resolution Vernier delay line time-to-digital converter (TDC) was proposed. The proposed TDC core was based on the pseudo-differential digital architecture that made it insensitive to nMOS and pMOS transistor mismatches. It also employed a Vernier delay line (VDL) in conjunction with an asynchronous read-out circuitry. The time interval resolution was equal to the difference of delay between buffers of upper and lower chains. Then, via the extra chain included in the lower delay line, resolution was controlled and power consumption was reduced. This method led to high resolution and low power consumption. The measurement results of TDC showed a resolution of 4.5 ps, 12-bit output dynamic range, and integral nonlinearity of 1.5 least significant bits. This TDC achieved the consumption of 68.43 µW from 1.1-V supply.

  16. Multi-hit time-to-digital converter VLSI for high-energy physics experiments

    CERN Document Server

    Arai, Y

    2001-01-01

    A multi-hit time-to-digital converter VLSI has been developed using a CMOS 0.3 mu m gate-array technology. The chip is designed for use in a high-energy physics experiment ATLAS. Precise timing signals are generated from 16 taps of an asymmetric ring oscillator oscillating at 80 MHz and controlled by a PLL circuit. A prototype chip has been developed, and a time resolution of 300 ps RMS was obtained. Many macro cells are developed to achieve such high resolution still using commercial gate-array technology. (4 refs).

  17. A multichannel time-to-digital converter ASIC with better than 3 ps RMS time resolution

    International Nuclear Information System (INIS)

    The development of a new multichannel, fine-time resolution time-to-digital converter (TDC) ASIC is currently under development at CERN. A prototype TDC has been designed, fabricated and successfully verified with demonstrated time resolutions of better than 3 ps-rms. Least-significant-bit (LSB) sizes as small as 5 ps with a differential-non-linearity (DNL) of better than ±0.9 LSB and integral-non-linearity (INL) of better than ±1.3 LSB respectively have been achieved. The contribution describes the implemented architecture and presents measurement results of a prototype ASIC implemented in a commercial 130 nm technology

  18. A four channel, self-calibrating, high resolution, time to digital converter

    CERN Document Server

    Mota, M

    1998-01-01

    A four channel, self-calibrating, High Resolution Time to Digital Converter (HRTDC) with an RMS error of 35 ps over a dynamic range of 3.2 \\mu s has been developed. Its architecture is based on an arr ay of delay locked loops and an 8-bit coarse time counter driven by an 80 MHz reference clock. Time measurements are buffered in two time registers per channel followed by a common 32 words deep read- out FIFO. The HRTDC has been built in a 0.7 \\mu m CMOS process using 23 mm^2 of silicon area.

  19. Signal-to-noise ratio estimation in digital computer simulation of lowpass and bandpass systems with applications to analog and digital communications, volume 3

    Science.gov (United States)

    Tranter, W. H.; Turner, M. D.

    1977-01-01

    Techniques are developed to estimate power gain, delay, signal-to-noise ratio, and mean square error in digital computer simulations of lowpass and bandpass systems. The techniques are applied to analog and digital communications. The signal-to-noise ratio estimates are shown to be maximum likelihood estimates in additive white Gaussian noise. The methods are seen to be especially useful for digital communication systems where the mapping from the signal-to-noise ratio to the error probability can be obtained. Simulation results show the techniques developed to be accurate and quite versatile in evaluating the performance of many systems through digital computer simulation.

  20. Frequency domain near-infrared multiwavelength imager design using high-speed, direct analog-to-digital conversion

    Science.gov (United States)

    Zimmermann, Bernhard B.; Fang, Qianqian; Boas, David A.; Carp, Stefan A.

    2016-01-01

    Frequency domain near-infrared spectroscopy (FD-NIRS) has proven to be a reliable method for quantification of tissue absolute optical properties. We present a full-sampling direct analog-to-digital conversion FD-NIR imager. While we developed this instrument with a focus on high-speed optical breast tomographic imaging, the proposed design is suitable for a wide-range of biophotonic applications where fast, accurate quantification of absolute optical properties is needed. Simultaneous dual wavelength operation at 685 and 830 nm is achieved by concurrent 67.5 and 75 MHz frequency modulation of each laser source, respectively, followed by digitization using a high-speed (180 MS/s) 16-bit A/D converter and hybrid FPGA-assisted demodulation. The instrument supports 25 source locations and features 20 concurrently operating detectors. The noise floor of the instrument was measured at Titration experiments consisting of 200 different absorption and scattering values were conducted to demonstrate accurate optical property quantification over the entire range of physiologically expected values.

  1. A 96-Channel FPGA-based Time-to-Digital Converter

    CERN Document Server

    Bogdan, M; Heintz, M; Paramonov, A A; Sanders, H; Chappa, S; De Maat, R; Klein, R; Miao, T; Wilson, P; Phillips, T J; Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold; Chappa, Steve; Maat, Robert De; Klein, Rod; Miao, Ting; Wilson, Peter; Phillips, Thomas J.

    2005-01-01

    We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) in the CDF Experiment at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA's. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 $\\mu$s allow deadtime-less operation in the first-leve...

  2. Design rules for superconducting analog-digital transducers

    International Nuclear Information System (INIS)

    This Thesis is a contribution for dimensioning aspects of circuits designs in superconductor electronics. Mainly superconductor comparators inclusive Josephson comparators as well as QOJS-Comparators are investigated. Both types were investigated in terms of speed and sensitivity. The influence of the thermal noise on the decision process of the comparators represent in so called gray zone, which is analysed in this thesis. Thereby, different relations between design parameters were derived. A circuit model of the Josephson comparator was verified by experiments. Concepts of superconductor analog-to-digital converters, which are based on above called comparators, were investigated in detail. From the comparator design rules, new rules for AD-converters were derived. Because of the reduced switching energy, the signal to noise ratio (SNR) of the circuits is affected and therefore the reliability of the decision-process is affected. For special applications with very demanding requirements in terms of the speed and accuracy superconductor analog-to-digital converters offer an excellent performance. This thesis provides relations between different design paramenters and shows resulting trade-offs, This method is transparent and easy to transfer to other circuit topologies. As a main result, a highly predictive tool for dimensioning of superconducting ADC's is proved.

  3. A 98-channel FPGA-based time-to-digital converter (TDC)

    Energy Technology Data Exchange (ETDEWEB)

    Bieling, John [Physikalische Institut der Universitaet Bonn (Germany); Collaboration: BGO-OD-Collaboration

    2013-07-01

    A new 98-channel FPGA-based time-to-digital converter (TDC) has been developed for the BGO-OD experiment located at the ELSA accelerator facility in Bonn. Its main feature is the ability to handle an input rate of 200 MHz on all channels in parallel for up to 1.25 μs. It uses a Spartan6 from Xilinx and has as resolution (bin-size) of 100 ps (240 ps using a Spartan3). To achieve this, the TDC serializes the recorded hits only after the trigger event and uses a second memory page to continuously record hits. Furthermore, it uses the carry-chain-sampling method to reach its sampling resolution. The poster illustrates the ideas and technical methods invoked.

  4. Program-controlled generator of delayed pulses for nanosecond time-to-digital converter control

    International Nuclear Information System (INIS)

    The structure of a delayed pulse generator designed for testing microchannel markers, amplification assemblies, time-to-digital converters, being a part of charged particle time-of-flight spectrometers, is described. The generator is included into a complex of automated test means of spectrometers and it is aimed at interfacing with the ELEKTRONIKA-60 microcomputer channel. The generator circuit is made on the basis of transistor matrices of series 198. The compensation circuit of the accumulation condensator charge permits to stabilize the initial zero potential, that besides high stability of thresholds of discriminating elements 521SA4, permits to obtain accuracy of time interval representation with near 2 ns ± 0.3%

  5. Digital multiplexing of analog data in a microprocessor controlled data acquisition system

    Science.gov (United States)

    Cliff, R. A.

    1980-01-01

    The purpose of the paper is to explore the ramifications of doing the multiplexing function in the digital domain and of using the microprocessor to replace the hardwired control logic which resides in the typical analog to digital converter. Two types of conversion (one working in parallel inputs, and one in sequential order) strategies are discussed where the microprocessor is in full control of the conversion. One advantage of using a digital multiplexor is that, contrary to an analog multiplexor, it does not degrade the fidelity of the conversion process.

  6. The All-digital Approach to LHC Power Converter Current Control

    CERN Document Server

    Dinius, A H; Pett, John G; Brazier, J C L

    2001-01-01

    The design of the LHC machine imposes severe demands upon the control of current in the 1700 magnet circuits. This has required the use of novel methods for the control of individual power converters and of the magnet current control system as a whole. This paper will review the chosen hardware and software methods and architectures. The digital regulation techniques used to achieve the overall targets for short-term stability (<3ppm) and reproducibility (<10ppm) of the 24 principal LHC circuits will be discussed. While the proposed system architecture will follow the canonical three-layer design, so successfully exploited in LEP, the software will be far from traditional. This software must be more reliable and maintainable than ever before, and will need to integrate with advanced object-oriented applications via commercial middleware. These challenges will be faced by applying object-oriented techniques throughout the system and by harnessing the power of XML for system definition.

  7. A 128-channel Time-to-Digital Converter (TDC) inside a Virtex-5 FPGA on the GANDALF module

    Science.gov (United States)

    Büchele, M.; Fischer, H.; Gorzellik, M.; Herrmann, F.; Königsmann, K.; Schill, C.; Schopferer, S.

    2012-03-01

    The GANDALF 6U-VME64x/VXS module has been developed for the digitization and real time analysis of detector signals. To perform different applications such as analog-to-digital or time-to-digital conversions, coincidence matrix formation, fast pattern recognition and trigger generation, this module comes with exchangeable analog and digital mezzanine cards. Based on this platform, we present a 128-channel TDC which is implemented in a single Xilinx Virtex-5 FPGA using a shifted clock sampling method. In contrast to common TDC concepts, the input signal is sampled by 16 equidistant phase-shifted clocks. A particular challenge of the design is the minimum skew routing of the input signals to the sampling flip-flops. We present measurement results for the differential nonlinearity and the time resolution of the TDC readout system.

  8. Design and implementation of double oscillator time-to-digital converter using SFQ logic circuits

    International Nuclear Information System (INIS)

    We have designed, fabricated and tested a time-to-digital converter (TDC) using SFQ logic circuits. The proposed TDC consists of two sets of ring oscillators and binary counters, and a coincidence detector (CD), which detects the coincidence of the arrival of two SFQ pulses from two ring oscillators. The advantage of the proposed TDC is its simple circuit structure with wide measurement range. The time resolution of the proposed TDC is limited by the resolution of the CD, which is about 10 ps because it is made by an NDRO cell in this study. The circuits are implemented using NEC 2.5 kA/cm2 Nb standard process and the CONNECT cell library. We have demonstrated the measurement of the propagation delay of a Josephson transmission line by the TDC with the time resolution of about 10 ps

  9. A New Fully Differential CMOS Capacitance to Digital Converter for Lab-on-Chip Applications.

    Science.gov (United States)

    Nabovati, Ghazal; Ghafar-Zadeh, Ebrahim; Mirzaei, Maryam; Ayala-Charca, Giancarlo; Awwad, Falah; Sawan, Mohamad

    2015-06-01

    In this paper, we present a new differential CMOS capacitive sensor for Lab-on-Chip applications. The proposed integrated sensor features a DC-input ΣΔ capacitance to digital converter (CDC) and two reference and sensing microelectrodes integrated on the top most metal layer in 0.35 μm CMOS process. Herein, we describe a readout circuitry with a programmable clocking strategy using a Charge Based Capacitance Measurement technique. The simulation and experimental results demonstrate a high capacitive dynamic range of 100 fF-110 fF, the sensitivity of 350 mV/fF and the minimum detectable capacitance variation of as low as 10 aF. We also demonstrate and discuss the use of this device for environmental applications through various chemical solvents. PMID:25134090

  10. A fast time domain digital simulation technique for power converters - Application to a buck converter with feedforward compensation

    Science.gov (United States)

    Kelkar, S. S.; Lee, F. C.

    1984-01-01

    Small signal analysis was performed earlier to demonstrate the marked improvement of dynamic properties and stability margins of a switching regulator employing a novel feedforward input filter compensation scheme. A large signal nonlinear recurrent time domain model is presented for the converter to analyse the transient response due to a step input change with and without the presence of the proposed feedforward loop. The results are verified with experimental data.

  11. Changing from analog to digital images: Does it affect the accuracy of alignment measurements of the lower extremity?

    OpenAIRE

    Lohman, Martina; Tallroth, Kaj; Kettunen, Jyrki A.; Remes, Ville

    2011-01-01

    Background and purpose Medical imaging has changed from analog films to digital media. We examined and compared the accuracy of orthopedic measurements using different media. Methods Before knee arthroplasty, full-length standing radiographs of 52 legs were obtained. The mechanical axis (MA), tibio-femoral angle (TFA), and femur angle (FA) were measured and analyzed twice, by 2 radiologists, using (1) true-size films, (2) short films, (3) a digital high-resolution workstation, and (4) a web-b...

  12. EFFICIENT DC GO/NO-GO TEST OF AN N-STAGE PIPELINED ANALOG-TODIGITAL CONVERTER

    Directory of Open Access Journals (Sweden)

    S. M. Hamed

    2013-03-01

    Full Text Available Nowadays, Analog to Digital Converters (ADCs play an important role in many applications. Pipelined Analog-to-Digital Converters (PADCs are extremely useful in high-speed applications. Testing PADC circuitsbecame essential. In this paper, a low-cost test is developed for a one stage PADC. It is shown that only three DC test values are capable to detect all catastrophic faults in the stage by observing only the digital outputs of the stage under test and its succeeding stage. In addition, the test of an N-stage PADC is investigated in this paper using extra hardware to facilitate the test. Only eleven DC test inputs are capable to detect all faults in the N stages as well as the extra hardware circuitry. The test was verified using the Eldo simulator provided by Mentor Graphics Corp. on 90nm CMOS model provided by MOSIS.

  13. An integrated CMOS time-to-digital converter for coincidence detection in a liquid xenon PET prototype

    OpenAIRE

    Bourrion, O.; Gallin-Martel, L.

    2005-01-01

    A Time to Digital Converter was designed (CMOS 0.35 μm) to perform coincidence detection in a Liquid Xenon PET prototype. This circuit proved to be able to operate at 150 K, while showing a resolution better than 250 ps. The circuit enables a low readout dead time (

  14. Analog-to-digital conversion with a SQUID: Conditions for a countable pulse train

    International Nuclear Information System (INIS)

    A superconducting loop containing a Josephson junction develops voltage pulses when it admits and expels magnetic flux quanta, and thus may be used as an A/D converter. We here develop and discuss several conditions which must be satisfied for the generation by the SQUID of an unambiguously countable pulse train, from which the analog signal can be faithfully reconstructed. These conditions can be satisfied over a broad range of realizable values of inductance and resistance. The capacitance, however, must be carefully controlled. The results of simulations are also presented, illustrating the various ways in which the pulse trains are affected

  15. The characterization and application of a low resource FPGA-based time to digital converter

    Science.gov (United States)

    Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco; Iafolla, Lorenzo; Mascolo, Matteo; Messi, Roberto; Moricciani, Dario; Riondino, Domenico

    2014-03-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of "off-the-shelf" TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured.

  16. Comparison between analog and digital filters

    Directory of Open Access Journals (Sweden)

    Zoltan Erdei

    2010-12-01

    Full Text Available Digital signal processing(DSP is one of the most powerful technologies and will model science and engineering in the 21st century. Revolutionary changes have already been made in different areas of research such as communications, medical imaging, radar and sonar technology, high fidelity audio signal reproducing etc. Each of these fields developed a different signal processing technology with its own algorithms, mathematics and technology, Digital filters are used in two general directions: to separate mixed signals and to restore signals that were compromised in different modes. The objective of this paper is to compare some basic digital filters versus analog filters such as low-pass, high-pass, band-pass filters. Scientists and engineers comprehend that, in comparison with analog filters, digital filters can process the same signal in real-time with broader flexibility. This understanding is considered important to instill incentive for engineers to become interested in the field of DSP. The analysis of the results will be made using dedicated libraries in MATLAB and Simulink software, such as the Signal Processing Toolbox.

  17. A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

    OpenAIRE

    Mahdi Rezvanyvardom; Tayebeh Ghanavati Nejad; Ebrahim Farshidi

    2014-01-01

    Time to digital converter (TDC) is a key block for time-gated single photon avalanche diode (SPAD) arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented. The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited. The proposed co...

  18. A 5-bit time to digital converter using time to voltage conversion and integrating techniques for agricultural products analysis by Raman spectroscopy

    Directory of Open Access Journals (Sweden)

    Mahdi Rezvanyvardom

    2014-12-01

    Full Text Available Time to digital converter (TDC is a key block for time-gated single photon avalanche diode (SPAD arrays for Raman spectroscopy that applicable in the agricultural products and food analysis. In this paper a new dual slope time to digital converter that employs the time to voltage conversion and integrating techniques for digitizing the time interval input signals is presented. The reference clock frequency of the TDC is 100 MHz and the input range is theoretically unlimited. The proposed converter features high accuracy, very small average error and high linear range. Also this converter has some advantages such as low circuit complexity, low power consumption and low sensitive to the temperature, power supply and process changes (PVT compared with the time to digital converters that used preceding conversion techniques. The proposed converter uses an indirect time to digital conversion method. Therefore, our converter has the appropriate linearity without extra elements. In order to evaluate the proposed idea, an integrating time to digital converter is designed in 0.18 μm CMOS technology and was simulated by Hspice. Comparison of the theoretical and simulation results confirms the proposed TDC operation; therefore, the proposed converter is very convenient for applications which have average speed and low variations in the signal amplitude such as biomedical signals.

  19. Design of a Low-Light-Level Image Sensor with On-Chip Sigma-Delta Analog-to- Digital Conversion

    Science.gov (United States)

    Mendis, Sunetra K.; Pain, Bedabrata; Nixon, Robert H.; Fossum, Eric R.

    1993-01-01

    The design and projected performance of a low-light-level active-pixel-sensor (APS) chip with semi-parallel analog-to-digital (A/D) conversion is presented. The individual elements have been fabricated and tested using MOSIS* 2 micrometer CMOS technology, although the integrated system has not yet been fabricated. The imager consists of a 128 x 128 array of active pixels at a 50 micrometer pitch. Each column of pixels shares a 10-bit A/D converter based on first-order oversampled sigma-delta (Sigma-Delta) modulation. The 10-bit outputs of each converter are multiplexed and read out through a single set of outputs. A semi-parallel architecture is chosen to achieve 30 frames/second operation even at low light levels. The sensor is designed for less than 12 e^- rms noise performance.

  20. Properties of matrix-assisted laser desorption. Measurements with a time-to-digital converter.

    Science.gov (United States)

    Ens, W; Mao, Y; Mayer, F; Standing, K G

    1991-03-01

    Some properties of matrix-assisted laser desorption have been studied using single-ion-counting methods and a time-to-digital converter. The methods allow examination of the process for irradiances near the reported threshold for observation with a transient recorder. All measurements were made using bovine insulin as a test compound. We present direct evidence that an irradiance threshold near 10(6) W cm-2 exists for ion production, and that the process is a collective effect, either involving a large number of molecular ions (approximately 10(4) in a successful event or none at all. Above the threshold, the yield is found to scale with a high power (4th to 6th) of the irradiance. Measurements of initial velocity distributions indicate an axial velocity spread corresponding to approximately 50 eV and a radial velocity spread corresponding to approximately 2.4 eV. Thus the ejection or extraction mechanism appears to be strongly asymmetric. PMID:1804409

  1. A 26 ps RMS time-to-digital converter core for Spartan-6 FPGAs

    CERN Document Server

    Bourdeauducq, Sebastien

    2013-01-01

    We have designed, implemented and tested a time-to-digital converter core in a low-cost Spartan-6 FPGA. Our design exploits the finite propagation speed in carry chains to realize a delay line in which the propagation distance of the incoming signal's edges is measured using hundreds of taps. This technique enables the core to reach a precision far better than the minimum switching period of the FPGA flip-flops. To compensate for process, voltage and temperature (PVT) effects, our design uses a combination of two techniques: startup calibration and online calibration. The startup calibration uses a statistical method to estimate the delay between the taps of the delay line and helps eliminate the effect of process variations. The online calibration, which takes place without disruption of the core's operation, uses a ring oscillator whose frequency instability is measured and used to compensate for subsequent voltage and temperature effects on the delay line. Our tests show that our design reaches a precision...

  2. A flexible multi-channel high-resolution time-to-digital converter ASIC

    CERN Document Server

    Mota, M; Debieux, S; Ryzhov, V; Moreira, P; Marchioro, A

    2000-01-01

    A data driven multi-channel Time-to-Digital Converter (TDC) circuit with programmable resolution ( similar to 25ps - 8OOps binning) and a dynamic range of 102.4mus has been implemented in a 0.25mum CMOS technology. An on-chip PLL is used for clock multiplication up to 320MHz from an external 40MHz reference. A 32 element Delay Locked Loop (DLL) performs time interpolation down to 97.5ps. Finally, finer time interpolation is obtained using four samples of the DLL separated by 24.5ps generated by an adjustable on-chip RC delay line. In the lower resolution modes of operation, 32 TDC channels are available. In the highest resolution mode eight channels are available, since four low-resolution channels are used to perform a single fine time interpolation. The TDC is capable of measuring both leading and trailing edges of the input signal. Measurements are initially stored as time stamps in individual four-location deep asynchronous channel buffers. After proper encoding, measurements are written into four 256-dee...

  3. High resolution time to digital converter for the KM3NeT neutrino telescope

    Science.gov (United States)

    Calvo, D.; Real, D.

    2015-01-01

    The KM3NeT collaboration aims at the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean Sea consisting of thousands of glass spheres, each of them containing 31 photomultipliers of small photocathode area. The readout and data acquisition system of KM3NeT has to collect, treat and send to shore, the enormous amount of data produced by the photomultipliers. For this purpose, 31 high-resolution time-interval measuring channels based on time to digital converter are implemented on the field-programmable gate arrays. Architectures with low resources occupancy are desirable allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The required resolution to measure both, time of flight and time-stamp must be 1 ns. A 4-Oversampling technique with two high frequency clocks and an asymmetric FIFO memory is used to achieve this resolution. The proposed firmware has been developed in Xilinx Kintex-7.

  4. 1 ns time to digital converters for the KM3NeT data readout system

    Energy Technology Data Exchange (ETDEWEB)

    Calvo, David [IFIC, Instituto de Física Corpuscular, CSIC- Universidad de Valencia, C/Catedrático José Beltrán, 2, 46980 Paterna (Spain); Collaboration: KM3NeT Collaboration

    2014-11-18

    The KM3NeT collaboration aims at the construction of a multi-km3 high-energy neutrino telescope in the Mediterranean Sea consisting of thousands of glass spheres (nodes), each of them containing 31 photomultiplier (PMT) of small photocathode area. The readout and data acquisition system of KM3NeT has to collect, treat and send to shore, in an economic way, the enormous amount of data produced by the photomultipliers. For this purpose, 31 high-resolution time-interval measuring channels are implemented on the Field-Programmable Gate Arrays (FPGA) based on Time to Digital Converter (TDC). TDC are very common devices in particles physics experiments. Architectures with low resources occupancy are desirable allowing the implementation of other instrumentation, communication and synchronization systems on the same device. The required resolution to measure both, time of flight and timestamp must be 1 ns. A 4-Oversampling technique with two high frequency clocks is used to achieve this resolution. The proposed TDC firmware is developed using very few resources in Xilinx Kintex-7.

  5. A 96-channel FPGA-based time-to-digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Bogdan, Mircea; Frisch, Henry; Heintz, Mary; Paramonov, Alexander; Sanders, Harold [Chicago U., EFI; Chappa, Steve; DeMaat, Robert; Klein, Rod; Miao, Ting; Phillips, Thomas J [Duke U.; Wilson, Peter [Fermilab

    2005-02-01

    We describe an FPGA-based, 96-channel, time-to-digital converter (TDC) intended for use with the Central Outer Tracker (COT) [1] in the CDF Experiment [2] at the Fermilab Tevatron. The COT system is digitized and read out by 315 TDC cards, each serving 96 wires of the chamber. The TDC is physically configured as a 9U VME card. The functionality is almost entirely programmed in firmware in two Altera Stratix FPGA’s. The special capabilities of this device are the availability of 840 MHz LVDS inputs, multiple phase-locked clock modules, and abundant memory. The TDC system operates with an input resolution of 1.2 ns, a minimum input pulse width of 4.8 ns and a minimum separation of 4.8 ns between pulses. Each input can accept up to 7 hits per collision. The time-to-digital conversion is done by first sampling each of the 96 inputs in 1.2-ns bins and filling a circular memory; the memory addresses of logical transitions (edges) in the input data are then translated into the time of arrival and width of the COT pulses. Memory pipelines with a depth of 5.5 μs allow deadtime-less operation in the first-level trigger; the data are multiple-buffered to diminish deadtime in the second-level trigger. The complete process of edge-detection and filling of buffers for readout takes 12 μs. The TDC VME interface allows a 64-bit Chain Block Transfer of multiple boards in a crate with transfer-rates up to 47 Mbytes/sec. The TDC also contains a separately-programmed data path that produces prompt trigger data every Tevatron crossing. The trigger bits are clocked onto the P3 VME backplane connector with a 22-ns clock for transmission to the trigger. The full TDC design and multi-card test results are described. The physical simplicity ensures low-maintenance; the functionality being in firmware allows reprogramming for other applications.

  6. High resolution distributed time-to-digital converter (TDC) in a White Rabbit network

    Energy Technology Data Exchange (ETDEWEB)

    Pan, Weibin, E-mail: pwb.thu@gmail.com; Gong, Guanghua; Du, Qiang; Li, Hongming; Li, Jianmin

    2014-02-21

    The Large High Altitude Air Shower Observatory (LHAASO) project consists of a complex detector array with over 6000 detector nodes spreading over 1.2 km{sup 2} areas. The arrival times of shower particles are captured by time-to-digital converters (TDCs) in the detectors' frontend electronics, the arrival direction of the high energy cosmic ray are then to be reconstructed from the space-time information of all detector nodes. To guarantee the angular resolution of 0.5°, a time synchronization of 500 ps (RMS) accuracy and 100 ps precision must be achieved among all TDC nodes. A technology enhancing Gigabit Ethernet, called the White Rabbit (WR), has shown the capability of delivering sub-nanosecond accuracy and picoseconds precision of synchronization over the standard data packet transfer. In this paper we demonstrate a distributed TDC prototype system combining the FPGA based TDC and the WR technology. With the time synchronization and data transfer services from a compact WR node, separate FPGA-TDC nodes can be combined to provide uniform time measurement information for correlated events. The design detail and test performance will be described in the paper.

  7. Radiation-tolerant delta-sigma time-to-digital converters

    CERN Document Server

    Cao, Ying; Steyaert, Michiel

    2015-01-01

    This book focuses on the design of a Mega-Gray (a standard unit of total ionizing radiation) radiation-tolerant ps-resolution time-to-digital converter (TDC) for a light detection and ranging (LIDAR) system used in a gamma-radiation environment. Several radiation-hardened-by-design (RHBD) techniques are demonstrated throughout the design of the TDC and other circuit techniques to improve the TDC's resolution in a harsh environment are also investigated. Readers can learn from scratch how to design a radiation-tolerant IC. Information regarding radiation effects, radiation-hardened design techniques and  measurements are organized in such a way that readers can easily gain a thorough understanding of the topic. Readers will also learn the design theory behind the newly proposed delta-sigma TDC. Readers can quickly acquire knowledge about the design of radiation-hardened bandgap voltage references and low-jitter relaxation oscillators, which are introduced in the content from a designer's perspective.   · �...

  8. Fully digital pixel readout architecture with a current-mode A/D converter

    Science.gov (United States)

    Eshraghian, Kamran; Lachowicz, Stefan W.

    2001-11-01

    Camera-on-a-CMOS chip will be an inevitable component of future intelligent vision systems. However, up till now, the dominant format of data in imaging devices is still analog. The analog photocurrent or sampled voltage is transferred to the ADC via a column or a column/row bus. Moreover, in the active pixel configuration the area occupied by circuitry reduces significantly the fill factor, so that there are heavy constraints imposed on the size of the circuits used. In this paper a concept of back illuminated focal plane is presented. The system consists of two chips bonded face to face using Indium bumps. The top chip, which is the seeing chip, is thinned and the light signal is applied to the bottom surface. The bottom chip is the processing chip and it contains a distributed array of analog-to digital converters. As the seeing chip is fully dedicated to photosensors the fill factor can be increased from 25-40% possible on a single plane to over 95% with two planes. The analog-to-digital converters are algorithmic current-mode converters, where one-bit cell is implemented in the processing area facing one-pixel. Eight such cells are cascaded to form an 8-bit converter. As a result, a fully digital pixel readout is obtained.

  9. Benefit of Analog, Programmable and Digital Hearing Aids

    OpenAIRE

    Jamileh Fatahi; Mansoureh Adel Ghahraman; Azadeh Ebrahimi; Faranak Ehsani; Samaneh Pourhadi

    2006-01-01

    Background and Aims: As the hearing aid technology progressively promotes toward replacing analog hearing aids with digital and programmable ones, comparison of the patient satisfaction of those kinds of hearing aids by means of a valuable tool seems so necessary. So, the aim of this study was to compare self-reported benefit of analog, digitally controlled programmable and digital hearing aids for reducing disability caused by hearing impairment in mild to severe sensorineural hearing impair...

  10. A new multiwire proportional chamber with fast single strip readout and individual analog to digital conversion

    International Nuclear Information System (INIS)

    A new precision MWPC with an active length of 400 mm has been built for the Munich Q3D spectrograph. The readout method uses the individual amplitude signals of narrow cathode strips (3 mm width, 0.5 mm spacing). Each of these signals is converted into a digital word by an individual fast ADC. A newly developed hard wired logic calculates the position of the particle event by the center of gravity method with a dead time of about 108 μs. The position resolution in test measurements simulating particle events was better than 0.1 mm. (orig.)

  11. Energy-Efficient Capacitance-to-Digital Converters for Low-Energy Sensor Nodes

    KAUST Repository

    Omran, Hesham

    2015-11-01

    Energy efficiency is a key requirement for wireless sensor nodes, biomedical implants, and wearable devices. The energy consumption of the sensor node needs to be minimized to avoid battery replacement, or even better, to enable the device to survive on energy harvested from the ambient. Capacitive sensors do not consume static power; thus, they are attractive from an energy efficiency perspective. In addition, they can be employed in a wide range of sensing applications. However, the sensor readout circuit–i.e., the capacitance-to-digital converter (CDC)–can be the dominant source of energy consumption in the system. Thus, the development of energy-efficient CDCs is crucial to minimizing the energy consumption of capacitive sensor nodes. In the first part of this dissertation, we propose several energy-efficient CDC architectures for low-energy sensor nodes. First, we propose a digitally-controlled coarsefine multislope CDC that employs both current and frequency scaling to achieve significant improvement in energy efficiency. Second, we analyze the limitations of successive approximation (SAR) CDC, and we address these limitations by proposing a robust parasitic-insensitive opamp-based SAR CDC. Third, we propose an inverter-based SAR CDC that achieves an energy efficiency figure-of-merit (FoM) of 31fJ/Step, which is the best energy efficiency FoM reported to date. Fourth, we propose a differential SAR CDC with quasi-dynamic operation to maintain excellent energy efficiency for a scalable sample rate. In the second part of this dissertation, we study the matching properties of small integrated capacitors, which are an integral component of energy-efficient CDCs. Despite conventional wisdom, we experimentally illustrate that the mismatch of small capacitors can be directly measured, and we report mismatch measurements for subfemtofarad integrated capacitors. We also correct the common misconception that lateral capacitors match better than vertical capacitors

  12. The characterization and application of a low resource FPGA-based time to digital converter

    International Nuclear Information System (INIS)

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented

  13. The characterization and application of a low resource FPGA-based time to digital converter

    Energy Technology Data Exchange (ETDEWEB)

    Balla, Alessandro; Mario Beretta, Matteo; Ciambrone, Paolo; Gatta, Maurizio; Gonnella, Francesco [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); Iafolla, Lorenzo, E-mail: lorenzo.iafolla@lnf.infn.it [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy); University of Rome “Tor Vergata” – Electronic Engineering Department (Italy); Mascolo, Matteo; Messi, Roberto [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); University of Rome “Tor Vergata” – Physics Department (Italy); Moricciani, Dario [Roma-2 Department of INFN, via della Ricerca Scientifica, 1, 00133 Rome (Italy); Riondino, Domenico [National Laboratories of Frascati (LNF) of INFN, via E. Fermi 40, 00044 Frascati (RM) (Italy)

    2014-03-01

    Time to Digital Converters (TDCs) are very common devices in particles physics experiments. A lot of “off-the-shelf” TDCs can be employed but the necessity of a custom DAta acQuisition (DAQ) system makes the TDCs implemented on the Field-Programmable Gate Arrays (FPGAs) desirable. Most of the architectures developed so far are based on the tapped delay lines with precision down to 10 ps, obtained with high FPGA resources usage and non-linearity issues to be managed. Often such precision is not necessary; in this case TDC architectures with low resources occupancy are preferable allowing the implementation of data processing systems and of other utilities on the same device. In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a 32 channel TDC with a precision of 255 ps and low non-linearity effects along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. The TDC is based on a low resources occupancy technique: the 4×Oversampling technique which, in this work, is pushed to its best resolution and its performances were exhaustively measured. - Highlights: • We need to measure the Time of Flight of the detected particles to reconstruct physics events. • We looked for an embedded solution based on an FPGA to implement a TDC with its DAQ system. • The solution is based on the 4xOversampling technique which employs very effectively the FPGA. • The 4×Oversampling technique was characterized and the results and comparisons with the state of the art are presented.

  14. CMOS time-to-digital converter based on a pulse-mixing scheme.

    Science.gov (United States)

    Chen, Chun-Chi; Hwang, Chorng-Sii; Liu, Keng-Chih; Chen, Guan-Hong

    2014-11-01

    This paper proposes a new pulse-mixing scheme utilizing both pulse-shrinking and pulse-stretching mechanisms to improve the performance of time-to-digital converters (TDCs). The temporal resolution of the conventional pulse-shrinking mechanism is determined by the size ratio between homogeneous and inhomogeneous elements. The proposed scheme which features double-stage operation derives its resolution according to the time difference between pulse-shrinking and pulse-stretching amounts. Thus, it can achieve greater immunity against temperature and ambient variations than that of the single-stage scheme. The circuit area also can be reduced by the proposed pulse-mixing scheme. In addition, this study proposes an improved cyclic delay line to eliminate the undesirable shift in the temporal resolution successfully. Therefore, the effective resolution can be controlled completely by the pulse-mixing unit to improve accuracy. The proposed TDC composed of only one cyclic delay line and one counter is fabricated in a TSMC CMOS 0.35-μm DPQM process. The chip core occupies an extremely small area of 0.02 mm(2), which is the best among the related works. The experimental result shows that an effective resolution of around 53 ps within ±13% variation over a 0-100 °C temperature range is achieved. The power consumption is 90 μW at a sample rate of 1000 samples/s. In addition to the reduced area, the proposed TDC circuit achieves its resolution with less thermal-sensitivity and better fluctuations caused by process variations. PMID:25430128

  15. Step-by-Step Design of an FPGA-Based Digital Compensator for DC/DC Converters Oriented to an Introductory Course

    Science.gov (United States)

    Zumel, P.; Fernandez, C.; Sanz, M.; Lazaro, A.; Barrado, A.

    2011-01-01

    In this paper, a short introductory course to introduce field-programmable gate array (FPGA)-based digital control of dc/dc switching power converters is presented. Digital control based on specific hardware has been at the leading edge of low-medium power dc/dc switching converters in recent years. Besides industry's interest in this topic, from…

  16. A low-cost scalable solution for digitizing analog X-rays with applications to rural healthcare.

    Science.gov (United States)

    Javvadi Appanacharya, Kalyan Tej; Tatinati, Anil Kumar; Kunderu, Hari Krishna; Syed, Khalid Mohammad; Channappayya, Sumohana S; Acharyya, Amit; Tripathi, Sourav

    2013-01-01

    In this paper, we present a low-cost scalable solution for digitizing analog X-ray images with the goal of improving diagnostics in rural and remote areas, in addition to having potential applications in disaster healthcare. Our solution attempts to capitalize on the rapid gains made in cellular communication and mobile technologies. The proposed mobile application lets the user digitally acquire the analog X-ray image and apply enhancement operations to it. A novel nonlinear technique for X-ray image enhancement has been proposed and implemented in the application. Additionally, several standard enhancement techniques have also been implemented. A proof-of-concept of the proposed solution is demonstrated with an Android application running on a smartphone. Results from real-world data collected at a semi-urban hospital in India are presented. The Android application has been made available online at the fifth authors' homepage. PMID:24111479

  17. Modeling from Local to Subsystem Level Effects in Analog and Digital Circuits Due to Space Induced Single Event Transients

    Science.gov (United States)

    Perez, Reinaldo J.

    2011-01-01

    Single Event Transients in analog and digital electronics from space generated high energetic nuclear particles can disrupt either temporarily and sometimes permanently the functionality and performance of electronics in space vehicles. This work first provides some insights into the modeling of SET in electronic circuits that can be used in SPICE-like simulators. The work is then directed to present methodologies, one of which was developed by this author, for the assessment of SET at different levels of integration in electronics, from the circuit level to the subsystem level.

  18. DIGITAL UP CONVERTER FOR WIMAX SYSTEM

    Directory of Open Access Journals (Sweden)

    CHARANJIT SINGH

    2010-09-01

    Full Text Available In the recent times, mobile communication needs not only a high data rate transmission but also a relatively fast mobility. The mobile WiMAX based on orthogonal frequency division multiple access (OFDMA can addresses both of these requirements. To implement the mobile WiMAX (IEEE 802.16e system, one must address a number of key issues in signal processing related to physical layer implementation. Within wireless base station system design, one continues to seek ways to add value and performance while increasing differentiation. In thispaper solution is proposed mainly for the front end, in term of design of Digital Up Converter (DUC which will obey the spectral consideration of WiMAX system (IEEE 802.16. Efficient design of DUC can contribute in the overall efficient system implementation. The DUC is designed for high-speed and high-bandwidth digitalsignal processing applications along with the capability of flexible digital filtering.

  19. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    OpenAIRE

    Chao Chen; Shengwei Meng; Zhenghuan Xia; Guangyou Fang; Hejun Yin

    2014-01-01

    We describe the architecture of a time-to-digital converter (TDC), specially intended to measure the delay resolution of a programmable delay line (PDL). The configuration, which consists of a ring oscillator, a frequency divider (FD), and a period measurement circuit (PMC), is implemented in a field programmable gate array (FPGA) device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT) generates periodic oscillatory pulses. The FD amplifies the oscillatory peri...

  20. Benefit of Analog, Programmable and Digital Hearing Aids

    Directory of Open Access Journals (Sweden)

    Jamileh Fatahi

    2006-12-01

    Full Text Available Background and Aims: As the hearing aid technology progressively promotes toward replacing analog hearing aids with digital and programmable ones, comparison of the patient satisfaction of those kinds of hearing aids by means of a valuable tool seems so necessary. So, the aim of this study was to compare self-reported benefit of analog, digitally controlled programmable and digital hearing aids for reducing disability caused by hearing impairment in mild to severe sensorineural hearing impaired persons. Materials and Methods: This cross-sectional study was performed on 90 persons with mild to severe sensorineural hearing loss dividing into three groups: 43 subjects were fitted with digital, 15 with programmable, 32 with analog hearing aids. After pure tone audiometry, Abbreviated profile of hearing aid benefit (APHAB was completed before and one month after using hearing aids to determine the benefit of them. Results: Global APHAB mean scores for digital, programmable and analog hearing aids were 49.05, 33.19 and 39.53, respectively. Ease of Communication subscale mean scores were 53.46 for digitals, 37.66 for programmables and 39.09 for analogs. Background noise subscale mean scores for digital programmable and analog hearing aids were 46.36, 25.53 and 35.31, respectively. Global and also both subscale mean scores showed significant difference between digital hearing aids and programmable and analog ones. There was no significant difference between reverberation subscale mean scores of three groups. Conclusion: It seems digital hearing aids may be more beneficial to reduce disability caused by hearing loss than analog and programmable hearing aids are.

  1. Analog tekst i digital kontekst

    DEFF Research Database (Denmark)

    Nicolaisen, Maria Skou

    2014-01-01

    have en legitimerende såvel som en strukturerende funktion, hvilket indvirker på læsningen af den pågældende tekst. Den vil proklamere, at traditionelle tekst- og læseformer synes understøttet af digitaliseringen, og diskutere hvordan kvalitativ tekstanalyse stadig har relevans i en digital tidsalder...

  2. Comparing Analog and Digital Hearing Aids in Reducing Hearing Disability

    OpenAIRE

    Ghassem Mohammad Khani; Mohammad Hassan Khalesi; Soghrat Faghih Zadeh; Bahieh Kohansal; Zahra Jafari

    2004-01-01

    Objective: Comparing analog and digital hearing aids reducing disability caused by hearing deficiency among moderate to severe sensorineural hearing-impaired persons. Method and Material: This descriptive-analytic study was carried out on two groups of subjects participated in this study in some audiology clinics of hearing aid since May 2002 to October 2003. Twenty subjects wore analog hearing aids and twenty one subjects wore digital hearing aids. In this study , no subject had previous mid...

  3. Analog and digital simulation of the radiocardiogram

    International Nuclear Information System (INIS)

    A mathematical model of the radiocardiogram has been developed to deal with the pulsatile component of the tracing. It is applicable to the bedside radiocardiogram, radionuclide angiocardiographic studies with the scintillation camera, or description of other tracer studies in the central circulation. The model consists of four heart chambers, each ejecting a fixed fraction of its contained tracer with each systole, and a lung delay function. Discrete-variable calculation of end-systolic and end-diastolic tracer content of the heart chambers and lung allowed development of simple, rapid programs for simulation by small digital computers. By this means, curve fitting and estimation of ejection fractions, end-diastolic volumes and mean lung delay may eventually be automated. A better understanding of the problems of extracting diagnostically useful information from such a multiparameter fit should result from study of these simulations. Families of characteristic curves were generated for several disorders where pattern recognition as well as parameter estimation is important. A small, light-weight, portable electronic analog simulator has been developed to permit the same simulation and trial-and-error parameter estimation at the bedside. It puts a real-time tracing onto the chart recorder used for actual radiocardiograms. Its design features are described. Some ideas unifying analog and digital modeling are expressed in differential equations. They provide a framework for future simulation of the radiocardiogram in the irregularly beating heart and an algorithm for potential extraction of detailed chamber-volume curves from the non-equilibrium portion of the radiocardiogram. (author)

  4. A robust parasitic-insensitive successive approximation capacitance-to-digital converter

    KAUST Repository

    Omran, Hesham

    2014-09-01

    In this paper, we present a capacitive sensor digital interface circuit using true capacitance-domain successive approximation that is independent of supply voltage. Robust operation is achieved by using a charge amplifier stage and multiple comparison technique. The interface circuit is insensitive to parasitic capacitances, offset voltages, and charge injection, and is not prone to noise coupling. The proposed design achieves very low temperature sensitivity of 25ppm/oC. A coarse-fine programmable capacitance array allows digitizing a wide capacitance range of 16pF with 12.5-bit quantization limited resolution in a compact area of 0.07mm2. The fabricated prototype is experimentally verified using on-chip sensor and off-chip MEMS capacitive pressure sensor. © 2014 IEEE.

  5. An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

    Directory of Open Access Journals (Sweden)

    Chao Chen

    2014-01-01

    Full Text Available We describe the architecture of a time-to-digital converter (TDC, specially intended to measure the delay resolution of a programmable delay line (PDL. The configuration, which consists of a ring oscillator, a frequency divider (FD, and a period measurement circuit (PMC, is implemented in a field programmable gate array (FPGA device. The ring oscillator realized in loop containing a PDL and a look-up table (LUT generates periodic oscillatory pulses. The FD amplifies the oscillatory period from nanosecond range to microsecond range. The time-to-digital conversion is based on counting the number of clock cycles between two consecutive pulses of the FD by the PMC. Experiments have been conducted to verify the performance of the TDC. The achieved relative errors for four PDLs are within 0.50%–1.21% and the TDC has an equivalent resolution of about 0.4 ps.

  6. Regulatory requirements for replacement of analog systems with digital upgrades

    International Nuclear Information System (INIS)

    This paper reviews briefly the regulatory guidelines which must be met in order to replace analog systems in nuclear power plants with digital systems. There is a move to do such replacements for a number of reasons: analog systems are aging, and showing considerable drift; few vendors manufacture analog systems today; support and parts are hard to get; digital systems provide flexibility. There is a safety concern however about undesirable and unpredictable effects to digital safety equipment due to plant transients, accidents, post-accident condition, and EMI/RF environmental interferences. License holders must comply with the requirements of 10 C.F.R. 50.59, which deals with safety concerns with respect to any changes to operating plants which may have an impact on the safety of the plant. NRC staff is taking the position that all digital upgrades will require an evaluation under this regulation

  7. A multi-channel 24.4 ps bin size Time-to-Digital Converter for HEP applications

    CERN Document Server

    Mester, C; Morira, P

    2008-01-01

    A multi-channel time-tagging Time-to-Digital Converter (TDC) ASIC with a resolution of 24.4 ps (bin size) has been implemented and fabricated in a 130 nm CMOS technology. An on-chip PLL is used to generate an internal timing reference from an external 40 MHz clock source. The circuit is based on a 32 element Delay Locked Loop (DLL) which performs the time interpolation. The 32 channel architecture of the TDC is suitable for both triggered and non-triggered applications. The prototype contains test structures such as a substrate noise generator. The paper describes the circuit architecture and its principles of operation.

  8. Analog-digital models of stream-aquifer systems

    Science.gov (United States)

    Moulder, E.A.; Jenkins, C.T.

    1969-01-01

    The best features of analog and digital computers were combined to make a management model of a stream-aquifer system. The analog model provides a means for synthesizing, verifying, and summarizing aquifer properties; the digital model permits rapid calculation of the effects of water management practices. Given specific management alternatives, a digital program can be written that will optimize operation plans of stream-aquifer systems. The techniques are demonstrated by application to a study of the Arkansas River valley in southeastern Colorado.

  9. A demonstration of ERTS-1 analog and digital techniques applied to strip mining in Maryland and West Virginia

    Science.gov (United States)

    Anderson, A. T.; Schubert, J.

    1974-01-01

    The largest contour strip mining operations in western Maryland and West Virginia are located within the Georges Creek and the Upper Potomac Basins. These two coal basins lie within the Georges Creek (Wellersburg) syncline. The disturbed strip mine areas were delineated with the surrounding geological and vegetation features using ERTS-1 data in both analog (imagery) and digital form. The two digital systems used were: (1) the ERTS-Analysis system, a point-by-point digital analysis of spectral signatures based on known spectral values, and (2) the LARS Automatic Data Processing System. The digital techniques being developed will later be incorporated into a data base for land use planning. These two systems aided in efforts to determine the extent and state of strip mining in this region. Aircraft data, ground verification information, and geological field studies also aided in the application of ERTS-1 imagery to perform an integrated analysis that assessed the adverse effects of strip mining. The results indicated that ERTS can both monitor and map the extent of strip mining to determine immediately the acreage affected and indicate where future reclamation and revegetation may be necessary.

  10. Verifying analog circuits based on a digital signature

    OpenAIRE

    Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan

    2009-01-01

    Verification of analog circuit specifications is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost parameter verification based on statistical analysis of a digital signature. A CMOS on-chip monitor and sampler circuit generates the digital signature of the CUT. The monitor composes two signals (x(t); y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code fo...

  11. Analog circuit design structured mixed-mode design, multi-bit sigma-delta converters, short range RF circuits

    CERN Document Server

    van Roermund, Arthur

    2007-01-01

    Preface. Part I: Structured Mixed-Mode Design. Introduction. Structured Oscillator Design; C. Verhoeven, A. van Staveren. Systematic Design of High-frequency gm-C Filters; E. Lauwers, G. Gielen. Structured LNA Design; E.H. Nordholt. High-Level Simulation and Modeling Tools for Mixed-Signal Front-ends of Wireless Systems; P. Wambacq, et al. Structured Simulation-Based Analog Design Synthesis; R.A. Rutenbar. Structured Analog layout Design; K. Lampaert. Part II: Multi-Bit Sigma Delta Converters. Introduction. Architecture Considerations for Multi-Bit SigmaDelta ADCs; T. Brooks. Multirate Sigma-Delta Modulators, an Alternative to Multibit; F. Colodro, A. Torralba. Circuit Design Aspects of Multi-Bit Delta-Sigma Converters; Y. Geerts, et al. High-speed Digital to Analog Converter Issues with Applications to Sigma Delta Modulators; K. Doris, et al. Correction-Free Multi-Bit Sigma-Delta Modulators for ADSL; R. del Rio, et al. Sigma Delta Converters in Wireline Communications; A. Wiesbauer, et al. Part III: Short Ra...

  12. Comparison of digital selenium radiography with an analog screen-film system in the diagnostic process of pneumoconiosis according to ILO classification

    International Nuclear Information System (INIS)

    Purpose: The aim of the study was to determine the diagnostic value of digital selenium radiography in patients with pneumoconiosis. For this purpose chest X-rays by digital selenium radiography and analog screen-film system were compared according to the ILO classification of pneumoconiosis. Method: After approval of the study by the local ethic commission and the Federal German Office for Radiation Protection 50 patients were subjected to X-rays by digital selenium radiography (Thoravision; Philips Medical Systems, Hamburg, Germany) and analog screen-film system of the same day within the scope of an industrial medicine preventive checkup. Four investigators rated the chest X-rays according to the ILO classification of pneumoconiosis. Results: The findings demonstrated by chest X-rays according to ILO classification were rated similar by digital selenium radiography and analog screen film systems. Image quality of the digital pictures was rated significantly better. Conclusion: The use of digital selenium radiography in evaluating chest X-rays according to the ILO classification does not result in over- or underestimation of pulmonary pathologies. Hence, in the diagnosis of pneumoconiosis, digital selenium radiography can replace the tested analog screen-film system. (orig.)

  13. A fast time-to-digital converter for position-sensitive radiation detectors with delay line readouts

    International Nuclear Information System (INIS)

    A fast time-to-digital converter (TDC) has been developed for use with position-sensitive radiation detectors having delay line readouts. The device is recommended for detector applications where high position resolution and low distortion are required at high rates. The device has 2 ns time resolution, less than 0.1% differential nonlinearity, and a recovery time of 70 ns. When used with a detector system having a delay line of temporal length τ, the following performance has been achieved: (1) a position digitization of 1 position resolution element per ns of delay line; (2) an average dead time of (3/4 τ + 70) ns; (3) a maximum incident radiation rate of ≅4/τ; and (4) a maximum conversion rate of ≅ 1/(3τ). Discriminator circuits reduce pile-up distortion to negligible levels for rates as high as those listed above. Finally, two converters may be connected together for synchronous operation as required by 2-dimensional (χ-γ) detectors. (orig.)

  14. A multi-channel time-to-digital converter chip for drift chamber readout

    International Nuclear Information System (INIS)

    A complete, multi-channel, timing and amplitude measurement IC for use in drift chamber applications is described. By targeting specific resolutions, i.e., 6-bits of resolution for both time and amplitude, area and power can be minimized while achieving the proper level of measurement accuracy. Time is digitized using an TDC comprised of a delay locked loop, latch and encoder. Amplitude (for dE/dx) is digitized using a dual-range FADC for each channel. Eight bits of dynamic range with six bits of accuracy are achieved with the dual-range. Eight complete channels of timing and amplitude information are multiplexed into one DRAM (Dynamic Random Access Memory) trigger latency buffer. Interesting events are subsequently transferred into an SRAM (Static Random Access Memory) readout buffer before the latency time has expired. The design has been optimized to achieve the requisite resolution using the smallest area and lowest power. The circuit has been implemented in an 0.8 microm triple metal CMOS process. The measured results indicate that the differential non-linearities of the TDC and the FADC are 200 ps and 10 mV, respectively. The integral nonlinearities of the TDC and the FADC are 230 ps and 9 mV, respectively

  15. Converting digital learning content into learning objects

    OpenAIRE

    Schreurs, Jeanne; Moreau, Rachel

    2006-01-01

    Our learning content can be structured as learning objects( LO) and as atomic learning objects (ALO). For both of them a set of metadata has been defined. The metadata follows the international standards on learning content. As a result the interoperability of the learning objects in different learning systems is being guaranteed. We are converting the digital learning content into LO's. A learning object is seen as a composition or a scenario model of a set of blocks. The blocks, presenting ...

  16. Configurable Analog-Digital Conversion Using the Neural EngineeringFramework

    Directory of Open Access Journals (Sweden)

    Christian G Mayr

    2014-07-01

    Full Text Available Efficient Analog-Digital Converters (ADC are one of the mainstays of mixed-signal integrated circuit design. Besides the conventional ADCs used in mainstream ICs, there have been various attempts in the past to utilize neuromorphic networks to accomplish an efficient crossing between analog and digital domains, i.e. to build neurally inspired ADCs. Generally, these have suffered from the same problems as conventional ADCs, that is they require high-precision, handcrafted analog circuits and are thus not technology portable. In this paper, we present an ADC based on the Neural Engineering Framework (NEF. It carries out a large fraction of the overall ADC process in the digital domain, i.e. it is easily portable across technologies. The analog-digital conversion takes full advantage of the high degree of parallelism inherent in neuromorphic networks, making for a very scalable ADC. In addition, it has a number of features not commonly found in conventional ADCs, such as a runtime reconfigurability of the ADC sampling rate, resolution and transfer characteristic.

  17. A Novel Vernier-based Time to Digital Converter for Low-power RFID Sensor Tags

    Directory of Open Access Journals (Sweden)

    Seyed Hossein Shahrokhi

    Full Text Available Power consumption is a key factor in analogue and digital design for portable devices. Radio Frequency Identification (RFID is widely used in industry, military and medical purposes. This technology operates with very low power consumption. Power consump ...

  18. FPGA-based time to digital converter and data acquisition system for high energy tagger of KLOE-2 experiment

    Energy Technology Data Exchange (ETDEWEB)

    Iafolla, L., E-mail: lorenzo.iafolla@lnf.infn.it [INFN-LNF, Frascati, Rome (Italy); Università di Roma Tor Vergata, Rome (Italy); Balla, A.; Beretta, M.; Ciambrone, P.; Gatta, M.; Gonnella, F. [INFN-LNF, Frascati, Rome (Italy); Mascolo, M.; Messi, R. [Università di Roma Tor Vergata, Rome (Italy); INFN-Sezione Roma 2, Rome (Italy); Moricciani, D. [INFN-Sezione Roma 2, Rome (Italy); Riondino, D. [INFN-LNF, Frascati, Rome (Italy)

    2013-08-01

    In order to reconstruct γγ physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.

  19. FPGA-based Time to Digital Converter and Data Acquisition system for High Energy Tagger of KLOE-2 experiment

    CERN Document Server

    Iafolla, L; Beretta, M; Ciambrone, P; Gatta, M; Gonnella, F; Mascolo, M; Messi, R; Moricciani, D; Riondino, D

    2012-01-01

    In order to reconstruct gamma-gamma physics events tagged with High Energy Tagger (HET) in the KLOE-2 (K LOng Experiment 2), we need to measure the Time Of Flight (TOF) of the electrons and positrons from the KLOE-2 Interaction Point (IP) to our tagging stations (11 m apart). The required resolution must be better than the bunch spacing (2.7 ns). We have developed and implemented on a Xilinx Virtex-5 FPGA a Time to Digital Converter (TDC) with 625 ps resolution (LSB) along with an embedded data acquisition system and the interface to the online FARM of KLOE-2. We will describe briefly the architecture of the TDC and of the Data AcQuisition (DAQ) system. Some more details will be provided about the zero-suppression algorithm used to reduce the data throughput.

  20. Development of a sub-nanosecond time-to-digital converter based on a field-programmable gate array

    International Nuclear Information System (INIS)

    The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers

  1. Development of a sub-nanosecond time-to-digital converter based on a field-programmable gate array

    Science.gov (United States)

    Sano, Y.; Tomoto, M.; Horii, Y.; Sasaki, O.; Uchida, T.; Ikeno, M.

    2016-03-01

    The present time-to-digital converter (TDC) chips for the monitored drift tube (MDT) chambers at the ATLAS experiment will be replaced with new ones for the High-Luminosity LHC, expected to begin operation in 2026. The design and the performance of a 24 channel TDC with a variable time binning of down to 0.28 nsec based on a Xilinx Kintex-7 field programmable gate array are reported. The time measurement is provided by a multisampling scheme with quad phase clocks synchronized with an external reference clock. The differential and integral nonlinearities have been measured to be less than half of the time binning. The temperature dependence on the performance is observed to be small. In conclusion the obtained performance of the time measurement is sufficiently high for the use with MDT chambers.

  2. Analog to Digital Conversion Techniques in Array Image Sensors%阵列型图像传感器模数转换技术

    Institute of Scientific and Technical Information of China (English)

    陈楠; 姚立斌

    2014-01-01

    阵列型图像传感器的信号读出方式对整个传感器的性能有较大的影响。在新型的数字化图像传感器中,光电信号的多路传输在数字域实现,实现了信号的无损传输,提高了图像传感器的通道隔离度及抗干扰能力。模拟数字转换器(ADC)是数字化图像传感器的重要组成部分,其性能对整个成像系统的性能有重大影响。以阵列型图像传感器对ADC的要求入手,分析了ADC各性能参数对阵列型图像传感器性能的影响,介绍了数字化图像传感器的各类结构及适用于阵列型图像传感器的不同ADC及其实现方式。CMOS工艺技术的发展使得像素级ADC技术进入实用化阶段,像素级ADC技术可以利用数字积分技术有效提高图像传感器的动态范围,使得光电信号积分及多路传输都在数字域进行,极大地提高了图像传感器的性能。%The photo signal readout plays an important role in array image sensors. The digital image sensor enables photo signal multiplexing and transmission losslessly in digital domain, increasing the channel isolation and making the sensor immune to interference. Analog to digital converter is a major component in digital image sensors and it is critical to the performance of the image sensor. Based on the requirements of the array image sensor to ADCs, the influences of the ADC to the image sensor performance are analyzed. The digital image sensor architectures and different types of ADC implementation are introduced. The development of the CMOS technologies makes the pixel-level ADC applicable, extending the dynamic range of the image sensor and enabling the signal integration in digital domain which improves the image sensor performance greatly.

  3. A high-resolution and one-cycle conversion time-to-digital converter architecture for PET image applications.

    Science.gov (United States)

    Sheng, Duo; Chung, Ching-Che; Huang, Chih-Chung; Jian, Jia-Wei

    2013-01-01

    In this paper, a high-resolution and one-cycle conversion time-to-digital converter (TDC) architecture with cell-based design for positron emission tomography (PET) applications is presented. The proposed TDC employs a cascade-stage structure to achieve high timing resolution and wide sampling range at the same time. Besides, based on the proposed two-level conversion structure, the proposed TDC not only can achieve single cycle latency and high speed of operation, but also have low circuit complexity as compared with conventional approaches. Simulation results show that operation frequency of the proposed TDC can be improved to 200 MHz with 50 ps resolution. In addition, the proposed TDC can be implemented with standard cells, making it easily portable to different processes and very suitable for biomedical chip applications. PMID:24110225

  4. A 75 ps rms time resolution BiCMOS time to digital converter optimized for high rate imaging detectors

    CERN Document Server

    Hervé, C

    2002-01-01

    This paper presents an integrated time to digital converter (TDC) with a bin size adjustable in the range of 125 to 175 ps and a differential nonlinearity of +-0.3%. The TDC has four channels. Its architecture has been optimized for the readout of imaging detectors in use at Synchrotron Radiation facilities. In particular, a built-in logic flags piled-up events. Multi-hit patterns are also supported for other applications. Time measurements are extracted off chip at the maximum throughput of 40 MHz. The dynamic range is 14 bits. It has been fabricated in 0.8 mu m BiCMOS technology. Time critical inputs are PECL compatible whereas other signals are CMOS compatible. A second application specific integrated circuit (ASIC) has been developed which translates NIM electrical levels to PECL ones. Both circuits are used to assemble board level TDCs complying with industry standards like VME, NIM and PCI.

  5. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    International Nuclear Information System (INIS)

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively

  6. A four channel time-to-digital converter ASIC with in-built calibration and SPI interface

    Energy Technology Data Exchange (ETDEWEB)

    Hari Prasad, K.; Sukhwani, Menka [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Saxena, Pooja [Homi Bhabha National Institute, Mumbai 400094 (India); Chandratre, V.B., E-mail: vbc@barc.gov.in [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India); Pithawa, C.K. [Electronics Division, Bhabha Atomic Research Center, Mumbai 400085 (India)

    2014-02-11

    A design of high resolution, wide dynamic range Time-to-Digital Converter (TDC) ASIC, implemented in 0.35 µm commercial CMOS technology is presented. The ASIC features four channel TDC with an in-built calibration and Serial Peripheral Interconnect (SPI) slave interface. The TDC is based on the vernier ring oscillator method in order to achieve both high resolution and wide dynamic range. This TDC ASIC is tested and found to have resolution of 127 ps (LSB), dynamic range of 1.8 µs and precision (σ) of 74 ps. The measured values of differential non-linearity (DNL) and integral non-linearity (INL) are 350 ps and 300 ps respectively.

  7. Digial Technology Qualification Task 2 - Suitability of Digital Alternatives to Analog Sensors and Actuators

    Energy Technology Data Exchange (ETDEWEB)

    Ted Quinn; Jerry Mauck

    2012-09-01

    The next generation reactors in the U.S. are an opportunity for vendors to build new reactor technology with advanced Instrumentation and Control Systems (control rooms, DCS, etc.). The advances made in the development of many current generation operating reactors in other parts of the world are being used in the design and construction of new plants. These new plants are expected to have fully integrated digital control rooms, computerized procedures, integrated surveillance testing with on-line monitoring and a major effort toward improving the O&M and fault survivability of the overall systems. In addition the designs are also incorporating major improvements in the man-machine interface based on lessons learned in nuclear and other industries. The above relates primarily to the scope of supply in instrumentation and control systems addressed by Chapter 7 of the Standard Review Plan (SRP) NUREG-0800 (Reference 9.5), and the associated Balance of Plant (BOP) I&C systems. This does not relate directly to the actuator and motor, breaker, initiation circuitry, valve position, etc. which is the subject of this report and normally outside of the traditional Distributed Control System (DCS), for both safety and non-safety systems. The recommendations presented in this report will be used as input to I&C research programming for the implementation of lessons learned during the early phases of new build both for large light water reactors (LWR) and also small modular reactors (SMR). This report is intended to support current research plans and provide user (vendor, owner-operator) input to the optimization of these research plans.

  8. A Low-Power Gateable Vernier Ring Oscillator Time-to-Digital Converter for Biomedical Imaging Applications.

    Science.gov (United States)

    Cheng, Zeng; Deen, M Jamal; Peng, Hao

    2016-04-01

    In this paper, a high resolution, high precision and ultra-low power consumption time-to-digital converter (TDC) is presented. The proposed TDC is based on the gateable Vernier ring oscillator architecture. Fine resolution is achieved through two ring oscillators arranged in the Vernier configuration. This TDC employs a single-transition end-of-conversion detection circuit and turns off the ring oscillators whenever the conversion is completed to reduce power consumption. The prototype chip is fabricated in a standard 130 nm digital CMOS process and its area is only 0.03 mm(2). Using a 1.2 V supply, the TDC achieves a resolution of 7.3 ps, a single-shot precision of 1.0LSB, and an average power consumption of 1.2 mW. A root-mean-square integral nonlinearity (INL) of 1.2 LSB is obtained with the help of an INL look-up-table calibration. Compared to previously reported ring-oscillator based TDCs, the proposed design achieves the lowest power consumption to date. PMID:26168446

  9. Digitally assisted analog beamforming for millimeter-wave communication

    NARCIS (Netherlands)

    Kokkeler, A.B.J.; Smit, G.J.M.

    2015-01-01

    The paper addresses the research question on how digital beamsteering algorithms can be combined with analog beamforming in the context of millimeter-wave communication for next generation (5G) cellular systems. Key is the use of coarse quantisation of the individual antenna signals next to the anal

  10. Two-Phase Interleaved Buck Converter with a new Digital Self-Oscillating Modulkator

    OpenAIRE

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents a new Digital Self-Oscillating Modulator (DiSOM) for DC/DC converters. The DiSOM modulator alllows the digital control algorithm to sample the output voltage at a sampling frequency higher than the converter switching frequency. This enables higher control loop bandwidth than for traditional digital PWM modulators given a certain switching frequency. A synchronised version of the DiSOM modulator is derived for interleaved converters. A prototype interleaved Buck converter ...

  11. Integrated power electronic converters and digital control

    CERN Document Server

    Emadi, Ali; Nie, Zhong

    2009-01-01

    Non-isolated DC-DC ConvertersBuck ConverterBoost ConverterBuck-Boost ConverterIsolated DC-DC ConvertersFlyback ConverterForward ConverterPush-Pull ConverterFull-Bridge ConverterHalf-Bridge ConverterPower Factor CorrectionConcept of PFCGeneral Classification of PFC CircuitsHigh Switching Frequency Topologies for PFCApplication of PFC in Advanced Motor DrivesIntegrated Switched-Mode Power ConvertersSwitched-Mode Power SuppliesThe Concept of Integrated ConverterDefinition of Integrated Switched-Mode Power Supplies (ISMPS)Boost-Type Integrated TopologiesGeneral Structure of Boost-Type Integrated T

  12. Comparing Analog and Digital Hearing Aids in Reducing Hearing Disability

    Directory of Open Access Journals (Sweden)

    Ghassem Mohammad Khani

    2004-06-01

    Full Text Available Objective: Comparing analog and digital hearing aids reducing disability caused by hearing deficiency among moderate to severe sensorineural hearing-impaired persons. Method and Material: This descriptive-analytic study was carried out on two groups of subjects participated in this study in some audiology clinics of hearing aid since May 2002 to October 2003. Twenty subjects wore analog hearing aids and twenty one subjects wore digital hearing aids. In this study , no subject had previous middle ear or psychological problems. APHAB questionnaire was completed before using hearing aid and 2 months after to determine benefit of hearing aid use. Results: Total score mean of APHAB inventory before and after use of analoge hearing aids were 52.215+6.420 and 32.300+3.443 respectively. Also total score mean of APHAB inventory before and after use of digital hearing aids were 54.9252+9.028 and 26.321+10.916 respectively. There was no significant difference between total mean score of APHAB inventory before and after using analog and digital hearing aids (P=0.058.While there was significant difference between total mean score of APHAB questionnaire before and after use of analog hearing aids (P<0.001 and also before and after use of digital hearing aids (P<0.001. Moreover age, gender , litracy level , occupation , degree of hearing loss and manner of hearing aid usage did not have significant effect on APHAB results. Configuration of loss had siginficant effect on aversiveness subscale before and after use of analog hearing aids (P=0.008. Previous experience and duration of hearing aid usage had significant effect on aversiveness subscale before and after use of digital hearing aids (P=0.043 and (P=0.024, respectively , while all of these three items did not have significant effect on total mean score of APHAB inventory and also total mean scores of three subscales of ease of communication , reverberation and background noise. Conclusion: Comparing to

  13. Strip silicon waveguide for code synchronization in all-optical analog-to-digital conversion based on a lumped time-delay compensation scheme

    Science.gov (United States)

    Sha, Li; Zhi-Guo, Shi; Zhe, Kang; Chong-Xiu, Yu; Jian-Ping, Wang

    2016-04-01

    An all-optical analog-to-digital converter (ADC) based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift (SSFS) module within a wavelength range of 1550 nm–1580 nm. A dispersion coefficient as high as –19800 ps/(km·nm) with ±0.5 ps/(km·nm) variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate (MSSR) is 50.45 GSa/s with full width at half maximum (FWHM) variation less than 2.52 ps, along with the 2-bit effective-number-of-bit and Gray code output. Project supported by the Fundamental Research Funds for the Central Universities, China (Grant No. FRF-TP-15-030A1) and China Postdoctoral Science Foundation (Grant No. 2015M580978).

  14. Use of an anthropomorphic hand phantom to verify the radiation intensity that is needed to modify the analog and digital radiographic quality

    International Nuclear Information System (INIS)

    The radiology is a field of medicine that is in constantly expansion and advancing. This can be noticed with the transition from analog to digital radiology systems, it is important that professionals understand image formation in both systems in order to produce radiographies with diagnostic quality. Therefore, the objective of this work is to present the importance of radiological protection by changing values of technical parameters while the quality of radiographic imaging is sustained. An anthropomorphic hand phantom was built in order to obtain radiographies, as it is necessary to respect the Brazilian regulations (Portaria 453/98) which forbids the use of radiation in patients for testing. Three analog and eight digital radiographies were obtained using fixed kVp and varying mAs. Each image was compared to the others acquired in the same location. Digital radiographies have shown that approximately 28% of change in mAs is necessary to change noise, whereas approximately 33,3% is necessary in the analog system to change density. The conclusion is that computerized systems need less x-ray intensity to modify image features and can reduce the patient radiation doses. However, more testing must be conducted in different radiologic environments to confirm the results obtained in the present study. (author)

  15. Realization of Digital Differentiator Using Generalized Integrator for Power Converters

    DEFF Research Database (Denmark)

    Xin, Zhen; Wang, Xiongfei; Loh, Poh Chiang;

    2015-01-01

    In power converters, the digital implementation of differentiator is challenged by noise amplification and phase error. For example, the backward Euler differentiator loses its effectiveness at high frequency due to an introduced large phase error. The Tustin differentiator, on the other hand...

  16. A multi-path gated ring oscillator based time-to-digital converter in 65 nm CMOS technology

    Institute of Scientific and Technical Information of China (English)

    Jiang Chen; Huang Yumei; Hong Zhiliang

    2013-01-01

    A gated ring oscillator (GRO) based time-to-digital converter (TDC) is presented.To enhance the resolution of the TDC,a multi-path structure for the GRO is used to achieve a higher oscillation frequency and an input stage is also presented to equivalently amplify the input time difference with a gain of 2.The GRO based TDC circuit is fabricated in TSMC 65 nm CMOS technology and the core area is about 0.02 mm2.According to the measurement results,the effective resolution of this circuit is better than 4.22 ps under a 50 MHz clock frequency.With a 1 ns input range,the maximum clock frequency of this circuit is larger than 200 MHz.Under a 1 V power supply,with a 200-800 ps input time difference,the measured power consumption is 1.24 to 1.72 mW at 50 MHz clock frequency and 1.73 to 2.20 mW at 200 MHz clock frequency.

  17. Direct Digital Demultiplexing of Analog TDM Signals for Cable Reduction in Ultrasound Imaging Catheters.

    Science.gov (United States)

    Carpenter, Thomas M; Rashid, M Wasequr; Ghovanloo, Maysam; Cowell, David M J; Freear, Steven; Degertekin, F Levent

    2016-08-01

    In real-time catheter-based 3-D ultrasound imaging applications, gathering data from the transducer arrays is difficult, as there is a restriction on cable count due to the diameter of the catheter. Although area and power hungry multiplexing circuits integrated at the catheter tip are used in some applications, these are unsuitable for use in small sized catheters for applications, such as intracardiac imaging. Furthermore, the length requirement for catheters and limited power available to on-chip cable drivers leads to limited signal strength at the receiver end. In this paper, an alternative approach using analog time-division multiplexing (TDM) is presented, which addresses the cable restrictions of ultrasound catheters. A novel digital demultiplexing technique is also described, which allows for a reduction in the number of analog signal processing stages required. The TDM and digital demultiplexing schemes are demonstrated for an intracardiac imaging system that would operate in the 4- to 11-MHz range. A TDM integrated circuit (IC) with an 8:1 multiplexer is interfaced with a fast analog-to-digital converter (ADC) through a microcoaxial catheter cable bundle, and processed with a field-programmable gate array register-transfer level simulation. Input signals to the TDM IC are recovered with -40-dB crosstalk between the channels on the same microcoax, showing the feasibility of this system for ultrasound imaging applications. PMID:27116738

  18. Digital Voltage Control of DC-DC Boost Converter

    Directory of Open Access Journals (Sweden)

    T. M. Swathy

    2015-05-01

    Full Text Available The need for digital control for faster communication between power stage module & system controllers is increased with requirement of load complexity. The requirements also include stability of power module with the parametric variation. This paper presents a digital control of a dc-dc boost converter under nominal parameter conditions. The system controller has been verified in both frequency response as well as MATLAB-Simulink under nominal & parametric varying condition. The modeling of converter has been illustrated using state-space averaging technique. Direct digital design method is equipped to design the controller in frequency response to yield constant load voltage. The characteristic of load voltage before & after parametric variation is shown.

  19. On automatic synthesis of analog/digital circuits

    Energy Technology Data Exchange (ETDEWEB)

    Beiu, V.

    1998-12-31

    The paper builds on a recent explicit numerical algorithm for Kolmogorov`s superpositions, and will show that in order to synthesize minimum size (i.e., size-optimal) circuits for implementing any Boolean function, the nonlinear activation function of the gates has to be the identity function. Because classical and--or implementations, as well as threshold gate implementations require exponential size, it follows that size-optimal solutions for implementing arbitrary Boolean functions can be obtained using analog (or mixed analog/digital) circuits. Conclusions and several comments are ending the paper.

  20. Low-power 4-bit flash analogue to digital converter for ranging applications

    OpenAIRE

    Torfs, Guy; Li, Zhisheng; Bauwelinck, Johan; Yin, Xin; Plas, G. Van Der; Vandewege, Jan

    2011-01-01

    A 4-bit 700 MS/s flash ADC is presented in 0.18 mu m CMOS. By lowering the kickback noise of the individual comparators it was possible to reduce the power consumption to 4.43 mW. Improved calibration capabilities resulted in an INL and DNL smaller than 0.25 LSB. These low nonlinearities give rise to 3.77 effective number of bits at the Nyquist input frequency and this in turn yields an overall figure of merit of 0.46 pJ per conversion step, the lowest figure of merit reported for ADCs with s...

  1. High-Resolution Time-to-Digital Converter in Field Programmable Gate Array

    CERN Document Server

    Aloisio, A; Cicalese, R; Giordano, R; Izzo, V; Loffredo, S; Lomoro, R

    2008-01-01

    Two high-resolution time-interval measuring systems implemented in a SRAM-based FPGA device are presented. The two methods ought to be used for time interpolation within the system clock cycle. We designed and built a PCB hosting a Virtex-5 Xilinx FPGA. We exploited high stability oscillators to test the two different architectures. In the first method, dedicated carry lines are used to perform fine time measurement, while in the second one a differential tapped delay line is used. In this paper we compare the two architectures and show their performance in terms of stability and resolution.

  2. F1 An Eight Channel Time-to-Digital Converter Chip for High Rate Experiments

    CERN Document Server

    Braun, G; Franz, J; Grünemaier, A; Heinsius, F H; Hennig, L; Königsmann, K C; Niebuhr, M; Schierloh, M; Schmidt, T; Schmitt, H; Urban, H J

    1999-01-01

    A new TDC chip has been developed for the COMPASS experiment at CERN. The resulting ASIC offers an unprecedented degree of flexibility and functionality. Its capability to handle highest hit and trigger input rates as well as its low power consumption makes it an ideal tool for future collider and fixed target experiments. First front-end boards equipped with the F1 chip have been used recently at testbeam experiments at CERN. A functional description and specification for this new TDC chip is presented.

  3. Synthetic analog and digital circuits for cellular computation and memory

    OpenAIRE

    Purcell, Oliver; Lu, Timothy K.

    2014-01-01

    Biological computation is a major area of focus in synthetic biology because it has the potential to enable a wide range of applications. Synthetic biologists have applied engineering concepts to biological systems in order to construct progressively more complex gene circuits capable of processing information in living cells. Here, we review the current state of computational genetic circuits and describe artificial gene circuits that perform digital and analog computation. We then discuss r...

  4. Analog circuit test based on a digital signature

    OpenAIRE

    Gómez Pau, Álvaro; Sanahuja Moliner, Ricard; Balado Suárez, Luz María; Figueras Pàmies, Joan

    2010-01-01

    Production verification of analog circuit specifica- tions is a challenging task requiring expensive test equipment and time consuming procedures. This paper presents a method for low cost on-chip parameter verification based on the analysis of a digital signature. A 65 nm CMOS on-chip monitor is proposed and validated in practice. The monitor composes two signals (x(t), y(t)) and divides the X-Y plane with nonlinear boundaries in order to generate a digital code for ever...

  5. A neurocomputer based on an analog-digital hybrid architecture

    Science.gov (United States)

    Moopenn, A.; Thakoor, A. P.; Duong, T.; Khanna, S. K.

    1987-01-01

    A novel analog-digital hybrid architecture based on the utilization of high density digital random access memories for the storage of the synaptic weights of a neural network, and high speed analog hardware to perform neural computation is described. An electronic neurocomputer based on such an architecture is ideally suited for investigating the dynamics, associative recall properties, and computational capabilities of neural networks and provides significant speed improvement in comparison to conventional software based neural network simulations. As a demonstration of the feasibility of the hybrid architectural concept, a prototype breadboard hybrid neurocomputer system with 32 neurons has been designed and fabricated with off-the-shelf hardware components. The performance of the breadboard system has been tested for variety of applications including associative memory and combinatorial problem solving such as Graph Coloring, and is discussed in this paper.

  6. Optical Packet Routing Performance of an Optical Packet Switch With an Optical Digital/Analog-Conversion-Type Header Processor (Wavelength Label Switch)

    Institute of Scientific and Technical Information of China (English)

    Hiroyuki; Uenohara; Takeshi; Seki; Kohroh; Kobayashi

    2003-01-01

    We demonstrate the routing operation of optical packets by an optical packet switch consisting of an optical digital-to-analog conversion-type header processor, a wavelength converter using an electrically-tunable laser, and an arrayed-waveguide grating router. A packet transfer by two-bit optical header was achieved for the first time.

  7. Optical Packet Routing Performance of an Optical Packet Switch Digital/ Analog-Conversion-Type With an Optical Header Processor (Wavelength Label Switch)

    Institute of Scientific and Technical Information of China (English)

    Hiroyuki Uenohara; Takeshi Seki; Kohroh Kobayashi

    2003-01-01

    We demonstrate the routing operation of optical packets by an optical packet switch consisting of an optical digital-to-analog conversion-type header processor, a wavelength converter using an electrically-tunable laser, and an arrayed-waveguide grating router. A packet transfer by two -bit optical header was achieved for the first time.

  8. Code synchronization based on lumped time-delay compensation scheme with a linearly chirped fiber Bragg grating in all-optical analog-to-digital conversion

    International Nuclear Information System (INIS)

    We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines. (electromagnetism, optics, acoustics, heat transfer, classical mechanics, and fluid dynamics)

  9. Lumped time-delay compensation scheme for coding synchronization in the nonlinear spectral quantization-based all-optical analog-to-digital conversion

    OpenAIRE

    Kang, Zhe; Yuan, Jinhui; Wu, Qiang; WANG, Tao; Li, Sha; Sang, Xinzhu; Yu, Chongxiu; Farrell, Gerald

    2013-01-01

    In this paper, we propose a novel lumped time-delay compensation scheme for the all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. By inserting a segment of negative dispersion fiber between the quantization and the coding module, the time delay of different quantized pulses can be accurately compensated with a simple structure compared to the multiple time-delay lines. The simulation results show that the coding pulses...

  10. 基于0.11μm CMOS工艺的时域SAR模数转换器%Time Domain SAR Analog-to-Digital Conversion Based on 0.11μm CMOS Process

    Institute of Scientific and Technical Information of China (English)

    李莎

    2016-01-01

    In order to avoid the linear degradation caused by multiple delay lines,an approximation register analog-to-digital converter based on the time domain comparator is proposed. By using a single delay line to implement the time domain comparator of the mode converter,the delay line includes the numerical control delay line and the volt⁃age controlled delay line. The proposed analog-to-digital converter has 8 effective bits,with the use of an area of 0.11μm CMOS process to achieve 0.128 mm2. Experimental results show that the power consumption of the time do⁃main SAR ADC is 1.8 μW when the power supply voltage is 0.6 V.%为避免因多种延迟线之间不匹配造成的线性退化,提出了一种基于时域比较器的逐次逼近型SAR(Successive Approximation Register)模数转换器。通过使用单个延迟线来实现该模转换器的时域比较器,此延迟线包括数控延迟线和压控延迟线。提出的模数转换器具有8个有效位,使用面积为0.128 mm2的0.11μm CMOS工艺实现。实验结果表明,当工作电源电压低至0.6 V时,提出的时域SAR模数转换器功耗为1.8μW。

  11. Digitally programmable analog building blocks for the implementation of artificial neural networks.

    Science.gov (United States)

    Almeida, A P; Franca, J E

    1996-01-01

    This paper describes the design, experimental characterization and behavior modeling of a homogeneous set of building blocks necessary to construct in analog hardware feed-forward artificial neural networks. A novel synapse architecture is proposed using a quasi-passive D/A (digital-to-analog) converter followed by a four-quadrant analog-digital multiplier, its main advantages are 1) increased signal input range; 2) improved area/weight resolution ratio; 3) on-chip refreshing of the weight value; and 4) serial loading the weight bits. The neurons are built using MOS (metal-oxide semiconductor) transistors operating in the saturation region and exploiting the inherent quadratic characteristics. Experimental results obtained from a demonstration prototype chip realized in a 1.2 mum double-poly, double-metal CMOS (complimentary MOS) technology show good agreement with the design specifications. A simple application of the proposed building blocks is illustrated based on the mixed-signal simulation of the corresponding behavior models constructed from the experimental characterization data. PMID:18255602

  12. Analog pulse processor

    Science.gov (United States)

    Wessendorf, Kurt O.; Kemper, Dale A.

    2003-06-03

    A very low power analog pulse processing system implemented as an ASIC useful for processing signals from radiation detectors, among other things. The system incorporates the functions of a charge sensitive amplifier, a shaping amplifier, a peak sample and hold circuit, and, optionally, an analog to digital converter and associated drivers.

  13. Digital-Analog Quantum Simulation of Spin Models in Trapped Ions

    Science.gov (United States)

    Arrazola, Iñigo; Pedernales, Julen S.; Lamata, Lucas; Solano, Enrique

    2016-01-01

    We propose a method to simulate spin models in trapped ions using a digital-analog approach, consisting in a suitable gate decomposition in terms of analog blocks and digital steps. In this way, we show that the quantum dynamics of an enhanced variety of spin models could be implemented with substantially less number of gates than a fully digital approach. Typically, analog blocks are built of multipartite dynamics providing the complexity of the simulated model, while the digital steps are local operations bringing versatility to it. Finally, we describe a possible experimental implementation in trapped-ion technologies. PMID:27470970

  14. Project Birdseye Aerial Photograph Collection: Digital and Analog Materials

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This collection consists of both analog and digital aerial photographs from Arctic areas in and around Baffin Bay, the Labrador Sea, the Arctic Ocean, the Beaufort...

  15. Reduction of the jitter of single-flux-quantum time-to-digital converters for time-of-flight mass spectrometry

    Energy Technology Data Exchange (ETDEWEB)

    Sano, K., E-mail: sano-kyosuke-cw@ynu.jp [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Muramatsu, Y.; Yamanashi, Y.; Yoshikawa, N. [Department Electrical and Computer Engineering, Yokohama National University, 79-5 Tokiwadai, Hodogaya, Yokohama 240-8501 (Japan); Zen, N.; Ohkubo, M. [Research Institute of Instrumentation Frontier, National Institute of Advanced Industrial Science and Technology, 1-1-1 Umezono, Tsukuba 305-8568 (Japan)

    2014-09-15

    Highlights: • We proposed single-flux-quantum (SFQ) time-to-digital converters (TDCs) for TOF-MS. • SFQ TDC can measure time intervals between multiple signals with high-resolution. • SFQ TDC can directly convert the time intervals into binary data. • We designed two types of SFQ TDCs to reduce the jitter. • The jitter is reduced to less than 100 ps. - Abstract: We have been developing a high-resolution superconducting time-of-flight mass spectrometry (TOF-MS) system, which utilizes a superconducting strip ion detector (SSID) and a single-flux-quantum (SFQ) time-to-digital converter (TDC). The SFQ TDC can measure time intervals between multiple input signals and directly convert them into binary data. In our previous study, 24-bit SFQ TDC with a 3 × 24-bit First-In First-Out (FIFO) buffer was designed and implemented using the AIST Nb standard process 2 (STP2), whose time resolution and dynamic range are 100 ps and 1.6 ms, respectively. In this study we reduce the jitter of the TDC by using two different approaches: one uses an on-chip clock generator with an on-chip low-pass filter for reducing the noise in the bias current, and the other uses a low-jitter external clock source at room temperature. We confirmed that the jitter is reduced to less than 100 ps in the latter approach.

  16. New capabilities for older aircraft: A study of pilot integration of retro-fit digital avionics to analog-instrumented flight decks

    Science.gov (United States)

    Breuer, Glynn E.

    The purpose of this study was to determine whether applying Gilbert's Behavior Engineering Model to military tactical aviation organizations would foster effective user integration of retro-fit digital avionics in analog-instrumented flight decks. This study examined the relationship between the reported presence of environmental supports and personal repertory supports as defined by Gilbert, and the reported self-efficacy of users of retro-fit digital avionics to analog flight decks, and examined the efficacious behaviors of users as they attain mastery of the equipment and procedures, and user reported best practices and criteria for masterful performance in the use of retro-fit digital avionics and components. This study used a mixed methodology, using quantitative surveys to measure the perceived level of organizational supports that foster mastery of retro-fit digital avionic components, and qualitative interviews to ascertain the efficacious behaviors and best practices of masterful users of these devices. The results of this study indicate that there is some relationship between the reported presence of organizational supports and personal repertory supports and the reported self-mastery and perceived organizational mastery of retro-fit digital avionics applied to the operation of the research aircraft. The primary recommendation is that unit leadership decide exactly the capabilities desired from retro-fit equipment, publish these standards, ensure training in these standards is effective, and evaluate performance based on these standards. Conclusions indicate that sufficient time and resources are available to the individual within the study population, and the organization as a whole, to apply Gilbert's criteria toward the mastery of retro-fit digital avionics applied to the operation of the research aircraft.

  17. Pulse-Height Distribution Analysis for Superconducting Nanostripline Ion Detector with a Fast Pulse-Integration Analog-Todigital Converter

    Science.gov (United States)

    Suzuki, Koji; Ukibe, Masahiro; Shiki, Shigetomo; Miki, Shigehito; Wang, Zhen; Takahashi, Yoshihiro; Yoshikawa, Nobuyuki; Ohkubo, Masataka

    Superconducting nano-stripline structure is promising for realizing an ideal ion detector for mass spectrometry (MS); nano-second time resolution and mass-independent detection efficiency from atoms to proteins. We report the first pulse-height spectra of a superconducting nano-stripline ion detector (SSLD) by a pulse-integration analog-to-digital converter (PIADC). A niobium nitride (NbN)-SSLD had a meander structure of the stripline with a thickness of 10 nm and a linewidth of 800 nm on an MgO substrate. A matrix-assisted laser desorption/ionization (MALDI) time-of-flight (TOF) mass spectrometer or a double-focusing mass spectrometer was used to produce and accelerate biomolecule ions (bovine serum albumin) with a molecular weight (MW) of 66,400 and Ar ions with an atomic weight (AW) of 40. Output pulse height did not depend on the MW or ion species for a wide mass range. Moreover, measured pulse-height distribution indicates that our SSLD system is so fast enough to discriminate the simultaneous ion incidence within 200 ns, which is close to the virtual dead time of time-to-digital converters (TDCs) at the practical usage in TOF MS for macromolecules.

  18. Digitally-controlled PC-interfaced Boost Converter for Educational Purposes

    DEFF Research Database (Denmark)

    Ljusev, Petar; Andersen, Michael A. E.

    2004-01-01

    acquisition. At the end, client program is presented which uses TCP/IP connection for operating the digitally controlled boost converter over Internet. The aim of this cheap and flexible PC-interfaced boost converter bench is predominantly educational, to allow students to synthesize different digital...

  19. Restructuring of a flash A/D converter to improve SEU rad tolerance

    International Nuclear Information System (INIS)

    The purpose of this work is to present how structural changes in the conventional Flash Analog to Digital Converter can secure it for a harsh radiation environment. The method consists in a coupling of two complementary techniques: a robust reconfiguration of the logical structure joined to a design hardening of the individual blocks. This approach preserves the ADC performances. (authors)

  20. Analog-to-Digital Conversion Using Single-Layer Integrate-and-Fire Networks with Inhibitory Connections

    Directory of Open Access Journals (Sweden)

    Shoop Barry L

    2004-01-01

    Full Text Available We discuss a method for increasing the effective sampling rate of binary A/D converters using an architecture that is inspired by biological neural networks. As in biological systems, many relatively simple components can act in concert without a predetermined progression of states or even a timing signal (clock. The charge-fire cycles of individual A/D converters are coordinated using feedback in a manner that suppresses noise in the signal baseband of the power spectrum of output spikes. We have demonstrated that these networks self-organize and that by utilizing the emergent properties of such networks, it is possible to leverage many A/D converters to increase the overall network sampling rate. We present experimental and simulation results for networks of oversampling 1-bit A/D converters arranged in single-layer integrate-and-fire networks with inhibitory connections. In addition, we demonstrate information transmission and preservation through chains of cascaded single-layer networks.

  1. Analog Design for Digital Deployment of a Serious Leadership Game

    Science.gov (United States)

    Maxwell, Nicholas; Lang, Tristan; Herman, Jeffrey L.; Phares, Richard

    2012-01-01

    This paper presents the design, development, and user testing of a leadership development simulation. The authors share lessons learned from using a design process for a board game to allow for quick and inexpensive revision cycles during the development of a serious leadership development game. The goal of this leadership simulation is to accelerate the development of leadership capacity in high-potential mid-level managers (GS-15 level) in a federal government agency. Simulation design included a mixed-method needs analysis, using both quantitative and qualitative approaches to determine organizational leadership needs. Eight design iterations were conducted, including three user testing phases. Three re-design iterations followed initial development, enabling game testing as part of comprehensive instructional events. Subsequent design, development and testing processes targeted digital application to a computer- and tablet-based environment. Recommendations include pros and cons of development and learner testing of an initial analog simulation prior to full digital simulation development.

  2. 4 Channel Digital Down Converter – DDC (EDA-00991)

    CERN Document Server

    BLAS, A; DELONG, J (BNL)

    2012-01-01

    A novel rf beam control architecture has been successfully tested in the LEIR synchrotron. The design is based on a VME 64X carrier board, including a DSP (digital signal processor), into which different daughter cards can be plugged in. The DDC (Digital Down Converter) is one of them. Hardware wise it has the features of a four-channel ADC (analogue-to-digital converter) which outputs drive a powerful FPGA (field programmable logic array); the latter is connected to the DSP on the carrier board via high-speed connectors. Mainly, this unit will acquire rf signals to analyze their phase and amplitude at a specified harmonic of the revolution. The main sampling clock feeding the mezzanine board is at a high harmonic of the particle’s revolution frequency. In the PSB, this frequency is varying along the accelerating cycle and this choice allows analyzing the rf signals from the cavities or from the beam without changing any parameter along the cycle. The sampling clock is tagged at the revolution rate allowing...

  3. Adaptive prediction in digitally controlled buck converter with fast load transient response

    OpenAIRE

    Lee, TLA; Chan, PCH

    2012-01-01

    An adaptive prediction scheme based on linear extrapolation for digitally controlled voltage-mode buck-type switching converter is presented. A major drawback of conventional digitally controlled switching converters is bandwidth limitation due to the additional phase lag in the digital feedback control loop. By predicting the future error voltage, the ADC sampling time delay is compensated in order to achieve a higher bandwidth even with a modest sampling rate. Both simulation and measuremen...

  4. Adaptive High-Bandwidth Digitally Controlled Buck Converter with Improved Line and Load Transient Response

    OpenAIRE

    Lee, ATL; Sin, JKO; Chan, PCH

    2014-01-01

    Digitally controlled switching converter suffers from bandwidth limitation because of the additional phase delay in the digital feedback control loop. In order to overcome the bandwidth limitation without using a high sampling rate, this paper presents an adaptive third-order digital controller for regulating a voltage-mode buck converter with a modest 2x oversampling ratio. The phase lag due to the ADC conversion time delay is virtually compensated by providing an early estimation of the err...

  5. A Pipeline Voltage-To-Time Converter for High Resolution Signal Extraction Off-Chip

    OpenAIRE

    Hogan, John; Farrell, Ronan

    2005-01-01

    In this paper a pipelined voltage to time converter is presented. It is targeted at the extraction, in digital form, of sensitive analog signals from an integrated circuit. The tester is able to measure the period of this signal and derive the original voltage. The input signal is low frequency. This paper provides solutions to the main challenges in implementing this modulator and how it may be integrated with a digital tester.

  6. A Cost-Effective 10-Bit D/A Converter for Digital-Input MOEMS Micromirror Actuation

    Directory of Open Access Journals (Sweden)

    Sergio Saponara

    2010-01-01

    Full Text Available The design of a 10-bit resistor-string digital-to-analog converter (DAC for MOEMS micromirror interfacing is addressed in this paper. The proposed DAC, realized in a 0.18-μm BCD technology, features a folded resistor-string stage with a switch matrix and address decoders plus an output voltage buffer stage. The proposed DAC and buffer circuitry are key elements of an innovative scanning micromirror actuator, characterized by direct digital input, full differential driving, and linear response. With respect to the the state-of-the-art resistor-string converters in similar technologies, the proposed DAC has comparable nonlinearity (INL, DNL performances while it has the advantage of a smaller area occupation, 0.17 mm2, including output buffer, and relatively low-power consumption, 200 μW at 500 kSPS and few μW in idle mode.

  7. Study and achievement of a digital-analog-divider

    International Nuclear Information System (INIS)

    This apparatus is designed to give directly, in digital form, the value of the ratio Vt1/V2 two analog voltages. It consists essentially of an analog-digital coder operating by successive weighing; the comparison voltage is made proportional to the divider V2 in the coder. The input dynamics are such that the voltages Vi and V2 are all in the range -50 mV to -5 V. Each of the circuits has an input impedance of about 10 KΩ. As for the quotient, it is a binary number given in series and parallel form; it is made up of 8 bits, this giving a change of 1/16 to 16 per jump of 1/16 in the zone where the accuracy is highest (V2 ≥ 800 mV). The time required for a division is, at best, 15 μsec. During the time of calculation, the voltages V1 and V2 should not vary by more than 1 per cent and 0.5 per cent respectively. The theory of the system and the investigation of a synoptic diagram, the study of the circuits and the actual construction are presented. (author)

  8. Two-Phase Interleaved Buck Converter with a new Digital Self-Oscillating Modulkator

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents a new Digital Self-Oscillating Modulator (DiSOM) for DC/DC converters. The DiSOM modulator alllows the digital control algorithm to sample the output voltage at a sampling frequency higher than the converter switching frequency. This enables higher control loop bandwidth than...... for traditional digital PWM modulators given a certain switching frequency. A synchronised version of the DiSOM modulator is derived for interleaved converters. A prototype interleaved Buck converter for Point of Load applications has been designed and built to test the performance of DiSOM modulator....... The DiSOM modulator and a digital control algorithm have been implemented in an FPGA. Experimental results show that the converter has a very fast transient response when a loadstep is applied to the output. For a loadstep of 50% of nominal output current the output voltage overshoot is less than 2...

  9. SOI design analog, memory and digital techniques

    CERN Document Server

    Marshall, Andrew

    2007-01-01

    Preface. Acknowledgements. 1. Overview. 2. SOI Materials. 3. Components. 4. SOI Modeling. 5. Layout for SOI. 6. Static SOI Design. 7. Dynamic SOI Design. 8. SOI SRAMs. 9. SOI DRAMs. 10. SOI Analog Design. 11. Global Design Issues. 12. Low Power Design. 13. SOI in Development. Appendix 1: Internet Sites (issue 1.0). Appendix 2: Trade Mark / Technology Information (issue 1.0). Index. About the Authors.

  10. Bridging Converts a Noncytotoxic nor-Paclitaxel Derivative to a Cytotoxic Analog by Constraining it to the T-Taxol Conformation

    OpenAIRE

    Tang, Shoubin; Yang, Chao; Brodie, Peggy; Bane, Susan; Ravindra, Rudravajhala; Sharma, Shubhada; Jiang, Yi; Snyder, James P.; Kingston, David G I

    2006-01-01

    The synthesis of the bridged A-nor-paclitaxel 4 has been achieved from paclitaxel in a key test of the T-Taxol conformational hypothesis. Although the unbridged A-nor-paclitaxel 3 is essentially non-cytotoxic, the bridged analog 4 is strongly cytotoxic. This result provides strong evidence for the T-Taxol conformation as the bioactive tubulin-binding conformation of paclitaxel.

  11. Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

    Energy Technology Data Exchange (ETDEWEB)

    Tamborini, D., E-mail: davide.tamborini@polimi.it; Portaluppi, D.; Villa, F.; Tosi, A. [Politecnico di Milano, Dipartimento di Elettronica, Informazione e Bioingegneria, Piazza Leonardo Da Vinci 32, 20133 Milano (Italy); Tisa, S. [Micro Photon Devices, via Stradivari 4, 39100 Bolzano (Italy)

    2014-11-15

    We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link.

  12. Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs.

    Science.gov (United States)

    Tamborini, D; Portaluppi, D; Villa, F; Tisa, S; Tosi, A

    2014-11-01

    We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link. PMID:25430129

  13. Multichannel low power time-to-digital converter card with 21 ps precision and full scale range up to 10 μs

    International Nuclear Information System (INIS)

    We present a Time-to-Digital Converter (TDC) card with a compact form factor, suitable for multichannel timing instruments or for integration into more complex systems. The TDC Card provides 10 ps timing resolution over the whole measurement range, which is selectable from 160 ns up to 10 μs, reaching 21 ps rms precision, 1.25% LSB rms differential nonlinearity, up to 3 Mconversion/s with 400 mW power consumption. The I/O edge card connector provides timing data readout through either a parallel bus or a 100 MHz serial interface and further measurement information like input signal rate and valid conversion rate (typically useful for time-correlated single-photon counting application) through an independent serial link

  14. The Digital Fields Board for the FIELDS instrument suite on the Solar Probe Plus mission: Analog and digital signal processing

    Science.gov (United States)

    Malaspina, David M.; Ergun, Robert E.; Bolton, Mary; Kien, Mark; Summers, David; Stevens, Ken; Yehle, Alan; Karlsson, Magnus; Hoxie, Vaughn C.; Bale, Stuart D.; Goetz, Keith

    2016-06-01

    The first in situ measurements of electric and magnetic fields in the near-Sun environment (Solar Probe Plus mission. The Digital Fields Board (DFB) is an electronics board within FIELDS that performs analog and digital signal processing, as well as digitization, for signals between DC and 60 kHz from five voltage sensors and four search coil magnetometer channels. These nine input signals are processed on the DFB into 26 analog data streams. A specialized application-specific integrated circuit performs analog to digital conversion on all 26 analog channels simultaneously. The DFB then processes the digital data using a field programmable gate array (FPGA), generating a variety of data products, including digitally filtered continuous waveforms, high-rate burst capture waveforms, power spectra, cross spectra, band-pass filter data, and several ancillary products. While the data products are optimized for encounter-based mission operations, they are also highly configurable, a key design aspect for a mission of exploration. This paper describes the analog and digital signal processing used to ensure that the DFB produces high-quality science data, using minimal resources, in the challenging near-Sun environment.

  15. Digital control of high-frequency switched-mode power converters

    CERN Document Server

    Corradini, Luca; Mattavelli, Paolo; Zane, Regan

    This book is focused on the fundamental aspects of analysis, modeling and design of digital control loops around high-frequency switched-mode power converters in a systematic and rigorous manner Comprehensive treatment of digital control theory for power converters Verilog and VHDL sample codes are provided Enables readers to successfully analyze, model, design, and implement voltage, current, or multi-loop digital feedback loops around switched-mode power converters Practical examples are used throughout the book to illustrate applications of the techniques developed Matlab examples are also

  16. Digitally Controlled Point of Load Converter with Very Fast Transient Response

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    voltage mode control and very fast transient response. The DiSOM modulator is combined with a digital PID compensator algorithm is implemented in a hybrid CPLD/FPGA and is used to control a synchronous Buck converter, which is used in typical Point of Load applications. The computational time is only...... comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of the DiSOM modulator makes it possible to design a digitally controlled DC/DC converter with linear...... three clock cycles from the time the A/D converter result is read by the control algorithm to the time the duty cycle command is updated. A typical POL converter has been built and the experimental results show that the transient response of the converter is very fast. The output voltage overshoot is...

  17. Dynamic characteristics of DC-DC converter with novel digital peak current-injected control

    OpenAIRE

    Kurokawa, Fujio; Sakemi, Junya; Sukita, Shohei; Shibata, Yuichiro; Soejima, Masato; YOKOYAMA, Tomonori; Sasaki, Masahiro; Mimura, Yasuhiro

    2009-01-01

    This paper presents the dynamic characteristics of the proposed digital control current mode de-de converter. In the proposed novel digital control circuit, the peak current-injected control is realized using the combination of the simple dual A-Dsignal converter and the programmed delay circuit. In 100kHz digitally controlled de-de converter, it is seen in simulation that the proposed method has no overshoot of the output voltage and the convergencetime that the output voltage is settled to ...

  18. Phase-locked loops. [in analog and digital circuits communication system

    Science.gov (United States)

    Gupta, S. C.

    1975-01-01

    An attempt to systematically outline the work done in the area of phase-locked loops which are now used in modern communication system design is presented. The analog phase-locked loops are well documented in several books but discrete, analog-digital, and digital phase-locked loop work is scattered. Apart from discussing the various analysis, design, and application aspects of phase-locked loops, a number of references are given in the bibliography.

  19. Analog and digital systems of imaging in roentgenodiagnostics

    International Nuclear Information System (INIS)

    In the recent years, we have been witnessing a very dynamic development of diagnostic methods of imaging. In contemporary radiology, the carrier of the diagnostic information is the image, obtained as a result of an X-ray beam transmitted through the patients body, with modulation of intensity, and processing of data collected by the detector. Depending on the diagnostic method used, signals can be detected with analog (x-ray film) or digital systems (CR, DR and DDR). Each of these methods of image acquisition, due to its own technological solutions, determines a different quality of imaging (diagnostic data). The introduction of digital image receptors, instead of conventional SF systems, increased the patient dose, as a result of a gradually increasing exposure. This followed from the fact that in digital systems, the increased radiation dose reduces image noise and improves image quality, and that is owing to the data capacity of these systems (impossible in SF systems with a limited data capacity of the image detector). The availability of the multitude of imaging systems, each characterized by disparate qualitative and quantitative parameters, implies the problem of evaluation and enforcement of a proper efficiency from manufacturers of these systems. At the same time, there is a legal problem present in our country, i.e. the lack of laws and regulations regarding standards of the scope of quality control (parameters) and measurement methodology for the systems of digital image acquisition. In the European countries, the scope and standards of control are regulated by the manufacturers and European Guidelines, whereas in the United States, AAPM Reports have been introduced, that specifically describe methods of tests performance, their frequency, as well as target values and limits. This paper is a review of both, the scope of quality control parameters of image detectors in analog and digital systems of imaging, and the measurement methodology. The parameters

  20. DSP controlled power converter

    OpenAIRE

    Chan, CH; Pong, MH

    1995-01-01

    A digital controller is designed and implemented by a Digital Signal Processor (DSP) to replace the Pulse Width Modulator (PWM) and error amplifier compensation network in a two wheeler forward converter. The DSP controller is designed in three approaches: a) Discretization of analog controller - the design is based on the transfer function of the error amplifier compensation network. b) Digital PID controller design - the design is based on the general form of the pulse transfer function of ...

  1. A 5 Giga Samples Per Second 8-Bit Analog to Digital Printed Circuit Board for Radio Astronomy

    Science.gov (United States)

    Jiang, Homin; Liu, Howard; Guzzino, Kim; Kubo, Derek; Li, Chao-Te; Chang, Ray; Chen, Ming-Tang

    2014-08-01

    We have designed, manufactured, and characterized an 8-bit 5 Giga samples per second (Gsps) ADC printed circuit board assembly (PCBA). An e2v EV8AQ160 ADC chip was used in the design and the board is plug compatible with the field programmable gate array (FPGA) board developed by the Collaboration for Astronomy Signal Processing and Electronics Research (CASPER) community. Astronomical interference fringes were demonstrated across a single baseline pair of antennas using two ADC boards on the Yuan Tseh Lee Array for Microwave Background Anisotropy (AMiBA) telescope. Several radio interferometers are using this board for bandwidth expansion, such as Submillimeter Array; also, several experimental telescopes are building new spectrometers using the same board. The ADC boards were attached directly to the Reconfigurable Open Architecture Computing Hardware (ROACH-2) FPGA board for processing of the digital output signals. This ADC board provides the capability of digitizing radio frequency signals from DC to 2 GHz (3 dB bandwidth), and to an extended bandwidth of 2.5 GHz (5 dB) with derated performance. The following worst-case performance parameters were obtained over 2 GHz: spur free dynamic range (SFDR) of 44 dB, signal-to-noise and distortion (SINAD) of 35 dB, and effective number of bits (ENOB) of 5.5.

  2. Some important aspects of the amplitude, charge and shape analog signals digitization in nuclear physics experiment

    International Nuclear Information System (INIS)

    One of the fundamental reasons of the special requirements concerning analog-to-digital converters (ADC's) used in nuclear experimental physics, especially in nuclear spectroscopy, in comparison to the conventional ADC's is a fact that they are utilized for continuous distribution measurements which are the nuclear radiation spectra. The ADC's used for distribution registration in form of amplitude or charge histogram spectra should have the differential linearity of two orders of magnitude better than that for conventional ADC's. Moreover, the problem of achievement the acceptable differential linearity (as well as stability) in nuclear spectroscopy is much more complicated because high resolution and high speed of the converters are also required. The first requirement comes out from application of semiconductor detectors, the second one comes from the statistical character of the nuclear processes, as well as, a necessity of collection of huge amount of nuclear data - often in a short time. In this report the influence of the specific needs of the nuclear experiments on the conversion methods selection and construction principles of the pulse ADC's is analyzed. Focus is taken on these ADC's which are used mainly to digital amplitude and charge detector signals measurements in nuclear spectroscopy. Based on the chosen examples of different types of ADC's it is shown how to obtain the required metrological parameters by using enlarged converter's structures and proper choice of the electronics components. In addition, a problem of the detector signals shape measurements in particle physics using the high speed flash ADC's is also discussed. (author). 196 refs, 99 figs, 7 tabs

  3. Analog-to-Digital Conversion Using Single-Layer Integrate-and-Fire Networks with Inhibitory Connections

    OpenAIRE

    Watson, Brian C.; Shoop, Barry L.; Eugene K. Ressler; Pankaj K. Das

    2004-01-01

    We discuss a method for increasing the effective sampling rate of binary A/D converters using an architecture that is inspired by biological neural networks. As in biological systems, many relatively simple components can act in concert without a predetermined progression of states or even a timing signal (clock). The charge-fire cycles of individual A/D converters are coordinated using feedback in a manner that suppresses noise in the signal baseband of the power spectrum of output spikes. W...

  4. Analog-to-Digital Conversion Using Single-Layer Integrate-and-Fire Networks with Inhibitory Connections

    OpenAIRE

    Shoop Barry L; Ressler Eugene K; Watson Brian C; Das Pankaj K

    2004-01-01

    We discuss a method for increasing the effective sampling rate of binary A/D converters using an architecture that is inspired by biological neural networks. As in biological systems, many relatively simple components can act in concert without a predetermined progression of states or even a timing signal (clock). The charge-fire cycles of individual A/D converters are coordinated using feedback in a manner that suppresses noise in the signal baseband of the power spectrum of output spikes. ...

  5. Asymmetric bilayer graphene nanoribbon MOSFETs for analog and digital electronics

    Science.gov (United States)

    Dinarvand, A.; Ahmadi, V.; Darvish, Gh.

    2016-05-01

    In this paper, a new structure was proposed for bilayer graphene nanoribbon field-effect transistor (BGNFET) mainly to enhance the electrical characteristics in analog and digital applications. The proposed device uses two metallic gates on the top and bottom of a bilayer graphene nanoribbon, which is surrounded by SiO2 and connected to heavily doped source/drain contacts. Electrical properties of the proposed device were explored using fully self-consistent solution of Poisson and Schrödinger equations based on the nonequilibrium Green's function (NEGF) formalism. Significant improvements in the electrical behavior was seen in the simulation results for gates asymmetrically biased. The comparison with graphene nanoribbon FET showed that the proposed structure benefited from higher intrinsic voltage gain and cut-off frequency and improved switching characteristics such as delay and Ion/Ioff ratio.

  6. Joint Source Channel Coding with Side Information Using Hybrid Digital Analog Codes

    CERN Document Server

    Wilson, Makesh Pravin; Caire, Giuseppe

    2008-01-01

    We study the joint source channel coding problem of transmitting an analog source over a Gaussian channel in two cases - (i) the presence of interference known only to the transmitter and (ii) in the presence of side information known only to the receiver. We introduce hybrid digital analog forms of the Costa and Wyner-Ziv coding schemes. Our schemes are based on random coding arguments and are different from the nested lattice schemes by Kochman and Zamir that use dithered quantization. We also discuss superimposed digital and analog schemes for the above problems which show that there are infinitely many schemes for achieving the optimal distortion for these problems. This provides an extension of the schemes by Bross et al to the interference/side information case. We then discuss applications of the hybrid digital analog schemes for transmitting under a channel signal-to-noise ratio mismatch and for broadcasting a Gaussian source with bandwidth compression.

  7. Digitally Controlled Offline Converter with Galvanic Isolation Based on an 8-bit Microcontroller

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents an offline AC/DC converter with digital control and galvanic isolation that can be implemented using cheap commercially available components. An ATMEL ATTiny26 8-bit microcontroller is used to control the converter. The microcontroller is placed on the secondary side of the...

  8. Simple Digital Control of a Two-Stage PFC Converter Using DSPIC30F Microprocessor

    DEFF Research Database (Denmark)

    Török, Lajos; Munk-Nielsen, Stig

    2010-01-01

    built for 70W rated output power. Average current mode control for boost converter and current programmed control for forward converter are implemented on a dsPIC30F1010. Pulse Width Modulation (PWM) technique is used to drive the switching MOSFETs. Results show that digital solutions with ds...

  9. Full characterization of self-phase-modulation based low-noise, cavity-less pulse source for photonic-assisted analog-to-digital conversion.

    Science.gov (United States)

    Liu, Lan; Tong, Zhi; Wiberg, Andreas O J; Myslivets, Evgeny; Alic, Nikola; Radic, Stojan

    2012-12-10

    A high quality cavity-less pulse source, realized as a combination of linear pulse compression and self-phase-modulation (SPM) based regeneration is demonstrated and strictly characterized for the first time. The regenerated pulses, with 3.6 GHz repetition rate, are optimized through rigorous relative intensity-noise (RIN) measurement. Temporal intensity and chirp characterizations demonstrate that the pulses exhibit characteristic of low RIN, and are chirp- and pedestal-free. The cavity-less pulse source is further tested in a photonic-assisted analog-to-digital (ADC) configuration as the sampling source. A record result of more than 8 effective quantization bits at 202 MHz is demonstrated. PMID:23262840

  10. Converting Radiology Operations in a Six-Hospital Healthcare System from Film-Based to Digital: Another Leadership Role for the Diagnostic Medical Physicist

    International Nuclear Information System (INIS)

    As medical facilities across the United States continue to convert their radiology operations from film-based to digital environments, partially accomplished and failed endeavors are frequent because of the lack of competent and knowledgeable leadership. The diagnostic medical physicist is, without a doubt, in a privileged position to take such a leadership role, not only because of her/his understanding of the basics principles of new imaging modalities, but also because of her/his inherent participation in workflow design and educational/training activities. A well-structured approach by the physicist will certainly lead the project to a successful completion, opening, in turn, new opportunities for the medical physicist to become an active participant in the decision-making process for an institution

  11. Root-mean-square pulse-amplitude-to-number converters

    International Nuclear Information System (INIS)

    The amplitude dispersion of pulses from gas-discharge and other detectors of ionizing radiation is determined by the sum of the analog additive noise and is proportional to the amplitude of the Poisson component. Losses of energy resolution or overexpenditure of channels are reduced by conversion of pulse amplitude to code by comparison of the peak value with a periodic parabolic voltage. The described converter has a scale that is linear with respect to atomic number and provides a constancy peak width that is acceptable for a digital spectrum filter with constant parameters. With 256 channels, the dead time is less than or equal to 25.6 microseconds and the error of the root-mean-square scale is less than 0.1% of the instantaneous value. The described converter has undergone prolonged testing under laboratory and field conditions in conjunction with an AMA-8 portable x-ray spectrometer and has shown sufficiently high metrological characteristics

  12. An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

    Institute of Scientific and Technical Information of China (English)

    Zhu Xiaoshi; Chen Chixiao; Xu Jialiang; Ye Fan; Ren Junyan

    2013-01-01

    A sampling switch with an embedded digital-to-skew converter (DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430 μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

  13. An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

    International Nuclear Information System (INIS)

    A sampling switch with an embedded digital-to-skew converter (DSC) is presented. The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage. A similar bridged capacitors' charge sharing structure is used to minimize the area. The circuit is fabricated in a 0.18 μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s. The power consumption is 430 μW at maximum. The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs (TI-ADCs) with the proposed DSC switch's demonstration. This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs. (semiconductor integrated circuits)

  14. Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux

    Energy Technology Data Exchange (ETDEWEB)

    Nogrette, F.; Chang, R.; Bouton, Q.; Westbrook, C. I.; Clément, D. [Laboratoire Charles Fabry, Institut d’Optique Graduate School, CNRS, Univ. Paris-Saclay, 91127 Palaiseau cedex (France); Heurteau, D.; Sellem, R. [Fédération de Recherche LUMAT (DTPI), CNRS, Univ. Paris-Sud, Institut d’Optique Graduate School, Univ. Paris-Saclay, F-91405 Orsay (France)

    2015-11-15

    We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 10{sup 6} s{sup −1} and three-dimensional reconstruction of the coordinates up to 3.2 × 10{sup 6} particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 10{sup 5} particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

  15. Characterization of a detector chain using a FPGA-based time-to-digital converter to reconstruct the three-dimensional coordinates of single particles at high flux

    Science.gov (United States)

    Nogrette, F.; Heurteau, D.; Chang, R.; Bouton, Q.; Westbrook, C. I.; Sellem, R.; Clément, D.

    2015-11-01

    We report on the development of a novel FPGA-based time-to-digital converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of micro-channel plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1 × 106 s-1 and three-dimensional reconstruction of the coordinates up to 3.2 × 106 particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) μm at a flux of 3 × 105 particles per second. In addition, we analyze a method to estimate the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work apply to the detection of other kinds of particles.

  16. Characterization of a detector chain using a FPGA-based Time-to-Digital Converter to reconstruct the three-dimensional coordinates of single particles at high flux

    CERN Document Server

    Nogrette, F; Chang, R; Bouton, Q; Westbrook, C I; Sellem, R; Clément, D

    2015-01-01

    We report on the development of a novel FPGA-based Time-to-Digital Converter and its implementation in a detection chain that records the coordinates of single particles along three dimensions. The detector is composed of Micro-Channel Plates mounted on top of a cross delay line and connected to fast electronics. We demonstrate continuous recording of the timing signals from the cross delay line at rates up to 4.1x10^6 per second and three-dimensional reconstruction of the coordinates up to 2.5x10^6 particles per second. From the imaging of a calibrated structure we measure the in-plane resolution of the detector to be 140(20) um. In addition we analyze a method to measure the resolution without placing any structure under vacuum, a significant practical improvement. While we use UV photons here, the results of this work directly apply to the detection of other kinds of particles.

  17. PHASE CONVERTER OF COMPOSING DISPLACEMENT

    OpenAIRE

    SMIRNOV YU.S.; Lysov, A. N.; E.V. Yurasova; SAFRONOV V.V.; VSTAVSKAYA E.V.

    2016-01-01

    Minimax strategy of mechatronic converters efficiency improving relative to error decrease with velocity increase at the same time provides common dataware level rise. The analysis of usage possibilities of different type position transducers (PT) gives the advantages of resolvers. The subsequent processing of their output signals is performed by “Resolver-to-Digit” Converter (RDC) which provides displacement digital equivalent and digital or analog signals specifying its velocity and acceler...

  18. Multi-Channel Optical Digitizer for Earth Sciences Project

    Data.gov (United States)

    National Aeronautics and Space Administration — The main objective was to design and manufacture a multi-channel high resolution analog-digital converter for digitizing a CCD image signal. The tasks included...

  19. Quality assessment of the digitalization process of analog x-ray images

    International Nuclear Information System (INIS)

    Computer-assisted diagnosis enabled doctors for a second point-of-view on the test results. This improves the diseases' early detection and significantly reduces the chance of errors. These methods very nicely complemented the possibilities of digital medical imaging apparatus, but in analog images their applicability and results entirely depend on the quality of analog images digitalisation. Today many standards and remarks for good practices discuss the digital apparatus image quality but the digitalisation process of analog medical images is not a part of them. Medical imaging apparatus have become digital, but within an entirely digital medical environment is necessary for their ability to blend with the old analog medical imaging carriers. The life of patients doesn't start with the beginning of digital era and for the aim of tracking diseases it is necessary to use the new digital images as well as older analog ones. For the generation of 40-50 years a large archive of images is piled up, which should be accounted of in the diagnosis process. This article is the author's study of the digitalized image quality problem. It offers a new approach to the x-ray image digitalisation - getting the HDR-image by optical sensor. After the HDR-image generation method offers to be used a digital signal processing to improve the quality of the final 16 bit gray scale medical image. The new method for medical image enhancement is proposed - it improves the image contrast, it increases or preserves the dynamic range and it doesn't lead to the loss of small low contrast structures in the image. Key words: Quality of Digital X-Rays Images

  20. Resolution upgrade toward 6-bit optical quantization using power-to-wavelength conversion for photonic analog-to-digital conversion.

    Science.gov (United States)

    Takahashi, Koji; Matsui, Hideki; Nagashima, Tomotaka; Konishi, Tsuyoshi

    2013-11-15

    We demonstrate a resolution upgrade toward 6 bit optical quantization using a power-to-wavelength conversion without an increment of system parallelism. Expansion of a full-scale input range is employed in conjunction with reduction of a quantization step size with keeping a sampling-rate transparency characteristic over several 100 sGS/s. The effective number of bits is estimated to 5.74 bit, and the integral nonlinearity error and differential nonlinearity error are estimated to less than 1 least significant bit. PMID:24322152

  1. Design of Monolithic Integrator for Strain-to-Frequency Converter

    OpenAIRE

    Tuan Mohd. Khairi Tuan Mat; Chew Sue Ping; Akram Abdul Azid

    2012-01-01

    Strain-to-Frequency converter (SFC) is a one of the analog conditioner tools that converts any strain signal to the frequency signal. The basic concept of SFC is by detecting any changing of strains, then converting the strain to the voltage signal and converting the voltage signal to the frequency signal. This tool consists of 3 main  components which are strain gauge, differential integrator and comparator. This paper presents the designing and analysis of monolithic integrator that to be u...

  2. Archive of Digitized Analog Boomer Seismic Reflection Data Collected from Lake Pontchartrain, Louisiana, to Mobile Bay, Alabama, During Cruises Onboard the R/V ERDA-1, June and August 1992

    Science.gov (United States)

    Sanford, Jordan M.; Harrison, Arnell S.; Wiese, Dana S.; Flocks, James G.

    2008-01-01

    . The acoustic energy is reflected at density boundaries (such as the seafloor or sediment layers beneath the seafloor), detected by the hydrophone receiver, and the amplitude of the reflected energy is recorded by an Edward P. Curley Lab (EPC) thermal plotter. This process is repeated at timed intervals (for example, 0.5 s) and recorded for specific intervals of time (for example, 100 ms). The timed intervals are also referred to as the shot interval or fire rate. On analog records, the recorded interval is referred to as the sweep, which is the amount of time the recorder stylus takes to sweep from the top of the record to the bottom of the record, thereby recording the amplitude of the reflected energy of one shot. In this way, consecutive recorded shots produce a two-dimensional (2-D) vertical image of the shallow geologic structure beneath the ship track. Many of the geophysical data collected by the USGS prior to the late 1990s were recorded in analog format and stored as paper copies. Scientists onboard made hand-written annotations onto these records to note latitude and longitude, time, line number, course heading, and geographic points of reference. Each paper roll typically contained numerous survey lines and could reach more than 90 ft in length. All rolls are stored at the USGS FISC-St. Petersburg, FL. To preserve the integrity of these records and improve accessibility, analog holdings were converted to digital files.

  3. Analog and Digital Simulations of Maxwellian Plasmas for Astrophysics

    International Nuclear Information System (INIS)

    Many astrophysical and laboratory plasmas possess Maxwell-Boltzmann (MB) electron energy distributions (EEDs). Interpreting or predicting the properties of these plasmas requires accurate knowledge of atomic processes such as radiative lifetimes, electron impact excitation and de-excitation, electron impact ionization, radiative recombination, dielectronic recombination, and charge transfer for thousands of levels or more. Plasma models cannot include all of the needed levels and atomic data. Hence approximations need to be made to make the models tractable. Here we report on an 'analog' technique we have developed for simulating a Maxwellian EED using an electron beam ion trap and review some recent results using this method. A subset of the atomic data needed for modeling Maxwellian plasmas relates to calculating the ionization balance. Accurate fractional abundance calculations for the different ionization stages of the various elements in the plasma are needed to reliably interpret or predict the properties of the gas. However, much of the atomic data needed for these calculations have not been generated using modern theoretical methods and are often highly suspect. Here we will also review our recent updating of the recommended atomic data for 'digital' computer simulations of MB plasmas in collisional ionization equilibrium (CIE), describe the changes relative to previously recommended CIE calculations, and discuss what further recombination and ionization data are needed to improve this latest set of recommended CIE calculations.

  4. Phase-locked loops for wireless communications digital, analog and optical implementations

    CERN Document Server

    Stephens, Donald R

    2007-01-01

    Preface. The Early History of Phase-Locked Loops. Analog Phase-Locked Loops. Root Locus and Frequency Analysis. Acquisition and Tracking. Digital Transforms. Charge Pumps, Counters, and Delay-Locked Loops. Digital Transformation of analog Phase-Locked Loops. Stability and Frequency Response of Digital Loops. All-Digital Phase-Locked Loops. Digital PLL Responses and Acquisition. Synchronizers for Digital Communications. Optical Phase-Locked Loops. Phase Noise Analysis. Appendix A: Laplace Transforms. Appendix B: Z Transforms. Index.

  5. Comparison of State-of-the-Art Digital Control and Analogue Control for High Bandwidth Point of Load Converters

    DEFF Research Database (Denmark)

    Jakobsen, Lars Tønnes; Schneider, Henrik; Andersen, Michael Andreas E.

    frequency of the converter. Voltage mode control is used in both the analogue and digital control schemes. The experimental results show that it is possible to design a digitally controlled Buck converter that has the same performance as can be achieved using commercially available analogue control ICs. The...

  6. Development of reconfigurable analog and digital circuits for plasma diagnostics measurement systems

    International Nuclear Information System (INIS)

    In long pulse discharge tokamak, a large number of diagnostic channels are being used to understand the complex behavior of plasma. Different diagnostics demand different types of analog and digital processing for plasma parameters measurement. This leads to variable requirements of signal processing for diagnostic measurement. For such types of requirements, we have developed hardware with reconfigurable electronic devices, which provide flexible solution for rapid development of measurement system. Here the analog processing is achieved by Field Programmable Analog Array (FPAA) integrated circuit while reconfigurable digital devices (CPLD/FPGA) achieve digital processing. FPAA's provide an ideal integrated platform for implementing low to medium complexity analog signal processing. With dynamic reconfigurability, the functionality of the FPAA can be reconfigured in-system by the designer or on the fly by a microprocessor. This feature is quite useful to manipulate the tuning or the construction of any part of the analog circuit without interrupting operation of the FPAA, thus maintaining system integrity. The hardware operation control logic circuits are configured in the reconfigurable digital devices (CPLD/FPGA) to control proper hardware functioning. These reconfigurable devices provide the design flexibility and save the component space on the board. It also provides the flexibility for various setting through software. The circuit controlling commands are either issued by computer/processor or generated by circuit itself. (author)

  7. Principle of time-to-digital converter and its realization%时间测量系统(TDC)的原理及实现

    Institute of Scientific and Technical Information of China (English)

    何超; 陈建政

    2012-01-01

    Vehicle and track interaction is important factors of the evaluation of operation quality of vehicles and line status. It is necessary to develop a continuous measurement of wheel rail force measuring wheelset device. In the measurement of performance parameters of high speed EMU temperature changes and electromagnetic field often bring error to the traditional simulation test system. Then, adoption of the CMOS technique consisting of TDC time to digital converter. By the TDC conversion principle knowable, TDC can work in strong electromagnetic field and it is digital output. The discussion focuses on TDC measurement principle. Not only that, but also discussed the engineering measurement of strain measurement hardware implementation and temperature drift, zero offset adjustment.%车辆与轨道间的作用力是评价车辆运行品质和线路状态的重要因素。研制能够连续精确测量轮轨力的测力轮对装置是非常必要的。由于在对高速动车组轮轨力性能参数的测量中,其温度变化、强电磁场往往会给传统模拟测试系统带来误差。于是,采用了以CMOS技术组成的TDC时间数字测量系统。由TDC的转换原理可知,TDC可在强电磁场下工作,并为数字输出。本文重点讨论了TDC测量原理。不仅如此,也讨论了在工程测量中应变测量的硬件实现和温度偏移、零点偏移的调整。

  8. Potential Upgrade of the CMS Tracker Analog Readout Optical Links using Bandwidth Efficient Digital Modulation

    CERN Document Server

    Dris, Stefanos; Gill, K; Grabit, R; Ricci, D; Troska, J; Vasey, F

    2007-01-01

    The potential application of advanced digital communication schemes in a future upgrade of the CMS Tracker readout optical links is currently being investigated at CERN. We show experimentally that multi-Gbit/s data rates are possible over the current 40 MSamples/s analog optical links by employing techniques similar to those used in ADSL. The concept involves using one or more digitally-modulated sinusoidal carriers in order to make efficient use of the available bandwidth.

  9. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Ridgetop Group will design a high-speed, low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital beam forming...

  10. High-Speed, Low-Power ADC for Digital Beam Forming (DBF) Systems Project

    Data.gov (United States)

    National Aeronautics and Space Administration — In Phase 1, Ridgetop Group designed a high-speed, yet low-power silicon germanium (SiGe)-based, analog-to-digital converter (ADC) to be a key element for digital...

  11. Digitally Controlled Converter with Dynamic Change of Control Law and Power Throughput

    DEFF Research Database (Denmark)

    Nesgaard, Carsten; Andersen, Michael Andreas E.; Nielsen, Nils

    2003-01-01

    substitution of analog controllers with their digital counterparts are considered. The outline of the paper is divided into two segments – the first being an experimental analysis of the timing behavior by means of code optimization – the second being an examination of the dynamics of incorporating two control......With the continuous development of faster and cheaper microprocessors the field of applications for digital control is constantly expanding. Based on this trend the paper at hand describes the analysis and implementation of multiple control laws within the same controller. Also, implemented within...... the control algorithm is a thermal monitoring scheme used for assessment of safe converter power throughput. An added benefit of this thermal monitoring is the possibility of software implemented analytic redundancy, which improves system fault resilience. Finally, reliability issues concerning the...

  12. Educating for a digital future – Walking three roads simultaneously: one analog and two digital

    OpenAIRE

    Lahtinen, Markus; Weaver, Benjamin

    2015-01-01

    In this paper we introduce the digitization challenge for higher education. Furthermore, three parallel ‘roads’ are proposed to consider in designing higher education content to address the digitization challenge. Program designers and educators will benefit by giving consideration to: (1) non-digital teaching activities that promote digital literacy, (2) digital opportunities to enhance traditional classroom practices, and (3) digitizing the university, referring to the opportunity to move h...

  13. Dual-Phase Tapped-Delay-Line Time-to-Digital Converter With On-the-Fly Calibration Implemented in 40 nm FPGA.

    Science.gov (United States)

    Won, Jun Yeon; Kwon, Sun Il; Yoon, Hyun Suk; Ko, Guen Bae; Son, Jeong-Whan; Lee, Jae Sung

    2016-02-01

    This paper describes two novel time-to-digital converter (TDC) architectures. The first is a dual-phase tapped-delay-line (TDL) TDC architecture that allows us to minimize the clock skew problem that causes the highly nonlinear characteristics of the TDC. The second is a pipelined on-the-fly calibration architecture that continuously compensates the nonlinearity and calibrates the fine times using the most up-to-date bin widths without additional dead time. The two architectures were combined and implemented in a single Virtex-6 device (ML605, Xilinx) for time interval measurement. The standard uncertainty for the time intervals from 0 to 20 ns was less than 12.83 ps-RMS (root mean square). The resolution (i.e., the least significant bit, LSB) of the TDC was approximately 10 ps at room temperature. The differential nonlinearity (DNL) values were [-1.0, 1.91] and [-1.0, 1.88] LSB and the integral nonlinearity (INL) values were [-2.20, 2.60] and [-1.63, 3.93] LSB for the two different TDLs that constitute one TDC channel. During temperature drift from 10 to 50(°)C, the TDC with on-the-fly calibration maintained the standard uncertainty of 11.03 ps-RMS. PMID:25775497

  14. Digitally Controlled Point of Load Converter with Very Fast Transient Response

    OpenAIRE

    Jakobsen, Lars Tønnes; Andersen, Michael Andreas E.

    2007-01-01

    This paper presents a new Digital Self-Oscillating Modulator (DiSOM) that allows the duty cycle to be changed instantly. The DiSOM modulator is shown to have variable switching that is a function of the duty cycle. Compared to a more traditional digital PWM modulator based on a counter and comparator the DiSOM modulator allows the sampling frequency of the output voltage control loop to be higher than the switching frequency of the power converter, typically a DC/DC converter. The features of...

  15. Implementation of FPGA based Digital Controller for Controlling Chaos in DC/DC converters

    Directory of Open Access Journals (Sweden)

    RANJAN Vanaja

    2010-05-01

    Full Text Available This paper analyzes the subharmonics andchaos generated in closed loop pulse width modulatedDC/DC buck converter and suggests the implementationof Digital controller based on time delayed selfcontrolling feedback concept for stabilizing the chaosgenerated in such converter. FPGA based digitalcontroller is designed and implemented for controllingthe chaotic oscillations of nonlinear switching converters.An experimental FPGA prototype and an applicationspecific IC that employ new controller architecture arebuilt around 11.3 V, 5.5 W, 2.5 KHz buck converter stageand successful operation of digital controller is verified.The experimental results prove the inherent capability ofthe proposed controller in maintaining the desired outputvoltage and keep the system chaos free by making thesystem insensitive to parameter variations.

  16. A high precision time-to-digital converter based on multi-phase clock implemented within Field-Programmable-Gate-Array

    International Nuclear Information System (INIS)

    In this paper, the design of a coarse-fine interpolation Time-to-Digital Converter (TDC) is implemented in an ALTERA's Cyclone FPGA. The carry-select chain performs as the tapped delay line. The Logic Array Block (LAB) having a propagation delay of 165 ps in the chain is synthesized as delay cell. Coarse counters triggered by the global clock count the more significant bits of the time data. This clock is also fed through the delay line, and LABs create the copies. The replicas are latched by the tested event signal, and the less significant bits are encoded from the latched binary bits. Single-shot resolution of the TDC can be 60 ps. The worst Differential Nonlinearity (DNL) is about 0.2 Least Significant Bit (LSB, 165 ps in this TDC module), and the Integral Nonlinearity (INL) is 0.6 LSB. In comparison with other architectures using the synchronous global clock to sample the taps, this architecture consumed less electric power and logic cells, and is more stable. (authors)

  17. Multi-Channel, High Resolution Time-to-Digital Converter%多通道高精度时间-数字转换器的研制

    Institute of Scientific and Technical Information of China (English)

    李清江; 徐欣; 孙兆林; 李楠; 李耀立; 周振

    2010-01-01

    介绍了一种基于USB2.0接口的多通道高精度时间-数字转换器(time-to-digital converter, TDC)的设计与实现.完成了NIM-LVPECL电平转换电路、高速串并转换电路、基于FPGA的数据处理及相关逻辑控制等单元电路的设计,最后给出了TDC的测试性能指标.结果表明,TDC的最小时间分辨率为403 ps,测量时间范围为0~420 us,测量"死时间"<13 ns.TDC可广泛应用于高精度的时间间隔测量领域,特别是作为飞行时间质谱仪(time-of-flight mass spectrometer, TOF-MS)的数据采集卡.

  18. A digitally controlled PWM/PSM dual-mode DC/DC converter

    Institute of Scientific and Technical Information of China (English)

    Zhen Shaowei; Zhang Bo; Luo Ping; Hou Sijian; Ye Jingxin; Ma Xiao

    2011-01-01

    A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed.Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM).The converter works in PSM at DCM and in 2 MHz PWM at CCM.Switching loss is reduced at a light load by skipping cycles.Thus high conversion efficiency is realized in a wide load current.The implementations of PWM control blocks,such as the ADC,the digital pulse width modulator (DPWM) and the loop compensator,and PSM control blocks are described in detail.The parameters of the loop compensator can be programmed for different external component values and switching frequencies,which is much more flexible than its analog rivals.The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm2.Experimental results show that the conversion efficiency is high,being 90% at 200 mA and 67% at 20 mA.Meanwhile,the measured load step response shows that the proposed dual-mode converter has good stability.

  19. A digitally controlled PWM/PSM dual-mode DC/DC converter

    International Nuclear Information System (INIS)

    A digitally controlled pulse width modulation/pulse skip modulation (PWM/PSM) dual-mode buck DC/DC converter is proposed. Its operation mode can be automatically chosen as continuous conduction mode (CCM) or discontinuous conduction mode (DCM). The converter works in PSM at DCM and in 2 MHz PWM at CCM. Switching loss is reduced at a light load by skipping cycles. Thus high conversion efficiency is realized in a wide load current. The implementations of PWM control blocks, such as the ADC, the digital pulse width modulator (DPWM) and the loop compensator, and PSM control blocks are described in detail. The parameters of the loop compensator can be programmed for different external component values and switching frequencies, which is much more flexible than its analog rivals. The chip is manufactured in 0.13 μm CMOS technology and the chip area is 1.21 mm2. Experimental results show that the conversion efficiency is high, being 90% at 200 mA and 67% at 20 mA. Meanwhile, the measured load step response shows that the proposed dual-mode converter has good stability. (semiconductor integrated circuits)

  20. Digitized self-oscillating loop for piezoelectric transformer-based power converters

    DEFF Research Database (Denmark)

    Ekhtiari, Marzieh; Andersen, Thomas; Zhang, Zhe; Andersen, Michael A. E.

    A new method is implemented in designing of self-oscillating loop for driving piezoelectric transformers. The implemented method is based on combining both analog and digital control systems. Digitized delay, or digitized phase shift through the self-oscillating loop results in a very precise fre...... updates at a rate of 417 kHz. This allows the control loop to dynamically follow frequency changes of the transformer in each resonant cycle. The operation principle behind self-oscillating is discussed in this paper. Moreover, experimental results are reported....

  1. Analysis of parallel optical sampling rate and ADC requirements in digital coherent receivers

    DEFF Research Database (Denmark)

    Lorences Riesgo, Abel; Galili, Michael; Peucheret, Christophe

    2012-01-01

    We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator.......We comprehensively assess analog-to-digital converter requirements in coherent digital receiver schemes with parallel optical sampling. We determine the electronic requirements in accordance with the properties of the free running local oscillator....

  2. Digital Control of Converters for Distributed Power Generations

    OpenAIRE

    Skjellnes, Tore

    2008-01-01

    Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of smallscale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid.A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the vol...

  3. Performance Effects of Display Incogruity in a Digital and Analog Clock Reading Task

    Science.gov (United States)

    Comstock, J. Raymond, Jr.; Derks, Peter L.

    2004-01-01

    In an era of increasing automation, it is important to design displays and input devices that minimize human error. In this context, information concerning the human response to the detection of incongruous information is important. Such incongruous information can be operationalized as unexpected (perhaps erroneous) information on which a decision by the human or operation by an automated system is based. In the aviation environment, decision making when faced with inadequate, incomplete, or incongruous information may occur in a failure scenario. An additional challenge facing the human operator in automated environments is maintaining alertness or vigilance. The vigilance issue is of particular concern as a factor that may interact with performance when faced with inadequate, incomplete, or incongruous information. From the literature on eye-scan behavior we know that the time spent looking at a particular display or indicator is a function of the type of information one is trying to discern from the display. For example, quick glances are all it takes for confirming that an indicator is in a normal position or range, whereas a continuous look of several seconds may be required for confirmation that a complex control input is having the desired effect. Important to consider is that while an extended look takes place, visual input from other sources may be missed. Much like an extended look, the interpretation of incongruous information may require extra time. The present experiment was designed to explore the performance consequences of a decision making task when incongruous information was presented. For this experiment a display incongruity was created on a subset of trials of a clock reading laboratory task. Display incongruity was made possible through presentation of 'impossible' times (e.g. 1:65 or 11:90). Subjects made 'same' 'different' decisions and keyboard responses to pairings of Analog-Analog (AA), Digital-Digital (DD), and Analog- Digital (AD

  4. 2 GHz self-aligning tandem A/D converter for SAR

    DEFF Research Database (Denmark)

    Søbjærg, Sten Schmidl; Christensen, Erik Lintz

    2001-01-01

    A new generation of the Danish synthetic aperture radar system (EMISAR) is under development targeting a bandwidth of 800 MHz and a corresponding range resolution of around 25 cm. Two alternative approaches to achieve the wide bandwidth are considered. One is to use analog I/Q demodulation before...... digitizing, and the other is to digitize the signal before digital I/Q demodulation. In both cases the digitizing may be performed by a digital front end (DFE) with two parallel analog-to-digital-converters (ADCs) sampling at 1 GHz in phase or in anti-phase respectively, provided the analog bandwidth of the...

  5. Design of Digital Controlled Forward Converter%数字控制正激变换器设计实现

    Institute of Scientific and Technical Information of China (English)

    张樨; 刘喆; 李杰

    2012-01-01

    According to some problems as adjustment difficulty of output voltage value in conventional forward converter, realization of analog feedback system on experience and unintelligent power control circuit,this paper puts forward to a forward converter circuit controlled by digital signal processor. This circuit can quick adjust control parameters according to the feedback signal, improve stability of output voltage and the anti-interference ability of the power. System tested under different load shows that this converter has advantages of parameter adjustment intelligent, strong antinterference ability.%针对常规正激变换器输出电压数值调整困难,模拟反馈系统实现倚重经验,电源控制电路不够智能化的问题,提出一种由数字信号处理器控制的正激变化电路。该电路能够根据反馈信号快速调整控制参数,提高了输出电压稳定性,提高了电源的抗干扰能力。通过在不同负载下进行试验,证明该变换器具有参数调整智能化程度高、抗干扰能力强的特点。

  6. High Speed Digitizer for Remote Sensing Project

    Data.gov (United States)

    National Aeronautics and Space Administration — Alphacore, Inc. proposes to design and characterize a 24Gsps (giga-samples per-second), 6-bit, low-power, and low-cost analog-to-digital converter (ADC) for use in...

  7. Analog electronics for radiation detection

    CERN Document Server

    2016-01-01

    Analog Electronics for Radiation Detection showcases the latest advances in readout electronics for particle, or radiation, detectors. Featuring chapters written by international experts in their respective fields, this authoritative text: Defines the main design parameters of front-end circuitry developed in microelectronics technologies Explains the basis for the use of complementary metal oxide semiconductor (CMOS) image sensors for the detection of charged particles and other non-consumer applications Delivers an in-depth review of analog-to-digital converters (ADCs), evaluating the pros and cons of ADCs integrated at the pixel, column, and per-chip levels Describes incremental sigma delta ADCs, time-to-digital converter (TDC) architectures, and digital pulse-processing techniques complementary to analog processing Examines the fundamental parameters and front-end types associated with silicon photomultipliers used for single visible-light photon detection Discusses pixel sensors ...

  8. A Survey of the Effectiveness of a Signal In a Wireless Analog and Digital System

    OpenAIRE

    Lundholm, Rickard; Bashir, Zaid; Kurowski, Sven

    2015-01-01

    The aim of this paper is to study the different parts of a wireless system in order to better understand the signal properties and what key factors changes the signal during its transmission. Two transmitters were created, an FM transmitter that transmits analog data and an Arudino board programed to convert data to bits before its transmission. The acquired signals were then compared to the original signal noting how differently the data had changed. To understand the antennas contribution t...

  9. Digital control of grid connected converters for distributed power generation

    Energy Technology Data Exchange (ETDEWEB)

    Skjellnes, Tore

    2008-07-01

    Pulse width modulated converters are becoming increasingly popular as their cost decreases and power rating increases. The new trend of small scale power producers, often using renewable energy sources, has created new demands for delivery of energy to the grid. A major advantage of the pulse width modulated converter is the ability to control the output voltage at any point in the voltage period. This enables rapid response to load changes and non-linear loads. In addition it can shape the voltage in response to the output current to create an outward appearance of a source impedance. This is called a virtual impedance. This thesis presents a controller for a voltage controlled three phase pulse width modulated converter. This controller enables operation in standalone mode, in parallel with other converters in a micro grid, and in parallel with a strong main grid. A time varying virtual impedance is presented which mainly attenuates reactive currents. A method of investigating the overall impedance including the virtual impedance is presented. New net standards have been introduced, requiring the converter to operate even during severe dips in the grid voltage. Experiments are presented verifying the operation of the controller during voltage dips. (Author). 37 refs., 65 figs., 10 tabs

  10. Image Resolution in the Digital Era: Notion and Clinical Implications

    OpenAIRE

    Vahid Rakhshan

    2014-01-01

    Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs.

  11. High-speed charge-to-time converter ASIC for the Super-Kamiokande detector

    CERN Document Server

    Nishino, H; Hayato, Y; Nakayama, S; Okumura, K; Shiozawa, M; Takeda, A; Ishikawa, K; Minegishi, A; Arai, Y; 10.1016/j.nima.2009.09.026

    2009-01-01

    A new application-specific integrated circuit (ASIC), the high-speed charge-to-time converter (QTC) IWATSU CLC101, provides three channels, each consisting of preamplifier, discriminator, low-pass filter, and charge integration circuitry, optimized for the waveform of a photomultiplier tube (PMT). This ASIC detects PMT signals using individual built-in discriminators and drives output timing signals whose width represents the integrated charge of the PMT signal. Combined with external input circuits composed of passive elements, the QTC provides full analog signal processing for the detector's PMTs, ready for further processing by time-to-digital converters (TDCs). High-rate (>1MHz) signal processing is achieved by short-charge-conversion-time and baseline-restoration circuits. Wide-range charge measurements are enabled by offering three gain ranges while maintaining a short cycle time. QTC chip test results show good analog performance, with efficient detection for a single photoelectron signal, four orders ...

  12. Multichannel analog temperature sensing system

    International Nuclear Information System (INIS)

    A multichannel system that protects the numerous and costly water-cooled magnet coils on the translation section of the FRX-C/T magnetic fusion experiment is described. The system comprises a thermistor for each coil, a constant current circuit for each thermistor, and a multichannel analog-to-digital converter interfaced to the computer

  13. Multichannel analog temperature sensing system

    Science.gov (United States)

    Gribble, R.

    1985-08-01

    A multichannel system that protects the numerous and costly water-cooled magnet coils on the translation section of the FRX-C/T magnetic fusion experiment is described. The system comprises a thermistor for each coil, a constant current circuit for each thermistor, and a multichannel analog-to-digital converter interfaced to the computer.

  14. Analog Signal Correlating Using an Analog-Based Signal Conditioning Front End

    Science.gov (United States)

    Prokop, Norman; Krasowski, Michael

    2013-01-01

    This innovation is capable of correlating two analog signals by using an analog-based signal conditioning front end to hard-limit the analog signals through adaptive thresholding into a binary bit stream, then performing the correlation using a Hamming "similarity" calculator function embedded in a one-bit digital correlator (OBDC). By converting the analog signal into a bit stream, the calculation of the correlation function is simplified, and less hardware resources are needed. This binary representation allows the hardware to move from a DSP where instructions are performed serially, into digital logic where calculations can be performed in parallel, greatly speeding up calculations.

  15. An Auto ranging Data Converter Implementation in FPGA

    Directory of Open Access Journals (Sweden)

    Jithin Krishnan

    2013-06-01

    Full Text Available A novel project is being presented here for implementation an auto ranging analog to digital converter for biomedical applications completely inside an FPGA - i.e. an all-digital analog to digital (A/D converter system. The only analog part is the auto ranging circuitry and an RC Integrator outside FPGA. The system outputs 24 bits and features a sigma delta ADC of 16 bits resolution, a range detection unit with 7 bits and a sign bit for polarity detection. The analog part of the modulator is done utilizing the LVDS transceiver in the FPGA making it a real digital one. The digital section of sigma delta ADC containing the decimation filter banks is done in a cascaded filter structure form including a CIC decimation filter, droop compensation and half-band filters. The top level module was coded using VHDL and the simulation was carried out with ModelSim and MATLAB.

  16. Modeling and Analysis of an All-digital Magnetic Encoder-to-digital Converters for Servo Motors%全数字伺服电机轴角转换单元建模与分析

    Institute of Scientific and Technical Information of China (English)

    刘亚静; 范瑜; 吕刚

    2013-01-01

    基于跟踪法的磁编码器轴角转换单元具有抗干扰能力强,同时能得到角度和速度信号等优点;而专用集成电路具有并行性、灵活性和实时性高等优点.当采用专用集成电路(application specific integrated circuits,ASIC)设计全数字、纯硬件的轴角数字转换单元时,面临着系统和算法的结构选择、内部参数界确定以及字长选取等问题.该文利用数字坐标旋转机(coordinate rotational digital computer,CORDIC)算法来替代传统跟踪测角中的乘法器和数控振荡器,通过对XY通道和Z通道进行标定以及误差分析,将其等效为一个减法操作符,实现角度求差功能.在此基础上,分析内部的误差传播路径,并从稳定性和动态性能角度确定传播路径的界,从而建立全数字轴角转换单元的模型,最后利用FPGA分别实现了A/D位数为10位、12位和14位时的轴角转换单元.实验结果验证了该文所建模型的正确性及有效性.%Magnetic encoder-to-digital converters (MEDC) based on a tracking method had the merits of noise-rejection capability, simultaneous extraction of the angular position and speed and so on. Application specific integrated circuits (ASIC) had the advantages of parallelism, flexibility and real-time. There were some problems such as choice of system architecture and algorithm structure, determination of parameters-region, and optimization of word-length etc, while implementing all-digital and full-hardware MEDC on ASIC. The coordinate rotational digital computer (CORDIC) algorithm was proposed instead of numeric controlled oscillator (NCO) and multiplier in the conventional tracking method, and then an equivalent subtraction operator was derived through error analysis and calibration of the XY and Z channels. On the basis of foregoing, an error propagations model was deduced and the intersection set of stability and dynamic parameters-region was determined, so the MEDC was modeled

  17. Digital engineering from base to application

    International Nuclear Information System (INIS)

    This book consists of 18 chapters, which deal with introduction of analog and digital, number system, logical function, simplify of logic function, digital logic gate, basic circuit, multiplex and de multiplex, adder-subtractor, encoder and decoder, comparator circuit and check circuit, flip-flop, counter, shift register, monostable multivibrator, DA converter, interface and memory and micro processor. The end has exercises and answers and an index.

  18. Analog Fixed Maximum Power Point Control for a PWM Step-downConverter for Water Pumping Installations

    DEFF Research Database (Denmark)

    Beltran, H.; Perez, E.; Chen, Zhe;

    2009-01-01

    This paper describes a Fixed Maximum Power Point analog control used in a step-down Pulse Width Modulated power converter. The DC/DC converter drives a DC motor used in small water pumping installations, without any electric storage device. The power supply is provided by PV panels working around...

  19. IS THERE ROOM FOR DURABLE ANALOG INFORMATION STORAGE IN A DIGITAL WORLD

    Energy Technology Data Exchange (ETDEWEB)

    R. A. STUTZ; L. HERETH

    2000-09-20

    Information technology has completely changed our concept of record keeping--the advent of digital records was a momentous discovery, as significant as the invention of the printing press. Digital records allowed huge amounts of information to be stored in a very small space and to be examined quickly. However, digital documents are much more vulnerable to the passage of time than printed documents, because the media on which they are stored are easily affected by physical phenomena, such as magnetic fields, oxidation, material decay, and by various environmental factors that may erase the information. Even more important, digital information becomes obsolete, because even if future generations maybe able to read it, they may not necessarily be able to interpret it. Over the centuries analog documents have been written on solid materials such as stone, clay and metal plates using tools to inscribe the characters. These archival methods have preserved records for centuries, and even millennia, but suffer from low information density. Modem methods facilitate writing pages on smooth material surfaces at high information densities. This writing can generate from about 25 to 100,000 times the area information density of microfilm and work with either analog or digital storage methods. Information of all types is becoming more dependent on digital records. These records are often created and stored on computer systems by scanning in documents or creating them directly on the system. Often analog information (human viewable information) is forced into binary form (ones and zeros). The necessity for the accurate and accessible storage of these documents is increasing for a number of reasons, including legal and environment issues. This paper will discuss information storage life, methods of information storage, media life considerations, and life cycle costs associated with several methods of storage.

  20. High resolution spectrum estimation for digital tracking array

    OpenAIRE

    Yeo, Kwang Hui

    2009-01-01

    To design a high resolution spectrum estimation module as part of a digital tracking array system, the theory and mathematical formulations of several high resolution spectrum estimation methods are presented. In the implementation of a spectrum estimation system, the received signal is first down-converted to baseband frequency using single channel or in-phase (I) and quad phase (Q) channel down-converter before it is digitized using an analog-to-digital (ADC) converter. Three distinct fre...

  1. Analog Beamforming and Digital Beamforming on Receive for Range Ambiguity Suppression in Spaceborne SAR

    OpenAIRE

    Pingping Huang; Wei Xu

    2015-01-01

    For future spaceborne synthetic aperture radar (SAR) missions, digital beamforming (DBF) on receive in elevation to form a sharp high receive beam will be adopted to improve the signal to noise ratio (SNR) level and suppress range ambiguities. However, in some special cases, range ambiguities may be received by grating lobes with the high receive beam gain, and range ambiguities would not be well suppressed and even may be increased. In this paper, a new receiving approach based on analog bea...

  2. Digital and Analog Electronics for an autonomous, deep-sea, Gamma Ray Burst Neutrino prototype detector

    Directory of Open Access Journals (Sweden)

    Manolopoulos K.

    2016-01-01

    Full Text Available GRBNeT is a Gamma Ray Burst Neutrino Telescope made of autonomously operated arrays of deep-sea light detectors, anchored to the sea-bed without any cabled connection to the shore. This paper presents the digital and analog electronics that we have designed and developed for the GRBNeT prototype. We describe the requirements for these electronics and present their design and functionality. We present low-power analog electronics for the PMTs utilized in the GRBNeT prototype and the FPGA based digital system for data selection and storage. We conclude with preliminary performance measurements of the electronics systems for the GRBNeT prototype.

  3. The design, fabrication, and test of a new VLSI hybrid analog-digital neural processing element

    Science.gov (United States)

    Deyong, Mark R.; Findley, Randall L.; Fields, Chris

    1992-01-01

    A hybrid analog-digital neural processing element with the time-dependent behavior of biological neurons has been developed. The hybrid processing element is designed for VLSI implementation and offers the best attributes of both analog and digital computation. Custom VLSI layout reduces the layout area of the processing element, which in turn increases the expected network density. The hybrid processing element operates at the nanosecond time scale, which enables it to produce real-time solutions to complex spatiotemporal problems found in high-speed signal processing applications. VLSI prototype chips have been designed, fabricated, and tested with encouraging results. Systems utilizing the time-dependent behavior of the hybrid processing element have been simulated and are currently in the fabrication process. Future applications are also discussed.

  4. Evaluation environment for digital and analog pathology: a platform for validation studies

    OpenAIRE

    Gallas, Brandon D.; Gavrielides, Marios A; Conway, Catherine M; Ivansky, Adam; Keay, Tyler C.; Cheng, Wei-Chung; Hipp, Jason; Hewitt, Stephen M

    2014-01-01

    Abstract. We present a platform for designing and executing studies that compare pathologists interpreting histopathology of whole slide images (WSIs) on a computer display to pathologists interpreting glass slides on an optical microscope. eeDAP is an evaluation environment for digital and analog pathology. The key element in eeDAP is the registration of the WSI to the glass slide. Registration is accomplished through computer control of the microscope stage and a camera mounted on the micro...

  5. An Analog Gamma Correction Scheme for High Dynamic Range CMOS Logarithmic Image Sensors

    OpenAIRE

    Yuan Cao; Xiaofang Pan; Xiaojin Zhao; Huisi Wu

    2014-01-01

    In this paper, a novel analog gamma correction scheme with a logarithmic image sensor dedicated to minimize the quantization noise of the high dynamic applications is presented. The proposed implementation exploits a non-linear voltage-controlled-oscillator (VCO) based analog-to-digital converter (ADC) to perform the gamma correction during the analog-to-digital conversion. As a result, the quantization noise does not increase while the same high dynamic range of logarithmic image sensor is p...

  6. EKSPLORASI DESAIN DASAR (NIRMANA MELALUI KOMBINASI MEDIA GRAFIS ANALOG DAN DIGITAL: Suatu Penelitian Kelas/Studio

    Directory of Open Access Journals (Sweden)

    Anita Rahardja

    2013-09-01

    Full Text Available This article is based on a research aiming to contextualize the fundamental principles of art and design to current setting in which analog media are no longer chosen as the ultimate hardware/tools. It is important considering digital hardware becomes more and more prevalent even preferred by students, whereas analog tools are getting harder to obtain, expensive and less ecological friendly. The goal of this research is to produce method analysis and the creation of two-dimensional basic design through digital media (Camera followed by conventional drawing tools, documented and conducted by the lecturers and the students. So far, almost 100% of the studies concerning basic design could only be found in foreign publications, with visual work examples that cannot be used freely in Indonesian local education due to copyright issue. Therefore, a literature study is conducted to examine the formal objects of this research which are the elements and fundamental principles in design, followed by ideation and visualization processes carried by the students in basic design classes through the semester. The visualization itself will integrate analog and digital media to generate the material objects of the research, which is a series of two-dimensional design compositions. These compositions are then analyzed and classified to taxonomic category of fundamental principles of two-dimensional design as an integral part of teaching-learning process (self-evaluation class for future improvement.

  7. Advances in analog and RF IC design for wireless communication systems

    CERN Document Server

    Manganaro, Gabriele

    2013-01-01

    Advances in Analog and RF IC Design for Wireless Communication Systems gives technical introductions to the latest and most significant topics in the area of circuit design of analog/RF ICs for wireless communication systems, emphasizing wireless infrastructure rather than handsets. The book ranges from very high performance circuits for complex wireless infrastructure systems to selected highly integrated systems for handsets and mobile devices. Coverage includes power amplifiers, low-noise amplifiers, modulators, analog-to-digital converters (ADCs) and digital-to-analog converters

  8. An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor

    OpenAIRE

    Yi-Xin Guo; Zhi-Biao Shao; Ting Li

    2015-01-01

    Inductive proximity sensors (IPSs) are widely used in position detection given their unique advantages. To address the problem of temperature drift, this paper presents an analog-digital mixed measurement method based on the two-dimensional look-up table. The inductance and resistance components can be separated by processing the measurement data, thus reducing temperature drift and generating quantitative outputs. This study establishes and implements a two-dimensional look-up table that red...

  9. A novel trajectory prediction control for proximate time-optimal digital control DC—DC converters

    International Nuclear Information System (INIS)

    The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC—DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC—DC with the proposed prediction is about 8 μs when the load current changes from 0.6 to 0.1 A. (semiconductor integrated circuits)

  10. A novel trajectory prediction control for proximate time-optimal digital control DC—DC converters

    Science.gov (United States)

    Qing, Wang; Ning, Chen; Shen, Xu; Weifeng, Sun; Longxing, Shi

    2014-09-01

    The purpose of this paper is to present a novel trajectory prediction method for proximate time-optimal digital control DC—DC converters. The control method provides pre-estimations of the duty ratio in the next several switching cycles, so as to compensate the computational time delay of the control loop and increase the control loop bandwidth, thereby improving the response speed. The experiment results show that the fastest transient response time of the digital DC—DC with the proposed prediction is about 8 μs when the load current changes from 0.6 to 0.1 A.

  11. Digital carrier modulation and sampling issues of matrix converters

    DEFF Research Database (Denmark)

    Blaabjerg, Frede; Loh, P.C.; Rong, R.J.;

    2008-01-01

    because of its inherent auto-sequencing process, and easier implementation using fast on-chip timers embedded in most modern digital signal processors. Motivated by these likely merits, which have previously been proven for dc-ac inverters, an investigation is now pursued here to develop appropriate...

  12. Digital Carrier Modulation and Sampling Issues of Matrix Converters

    DEFF Research Database (Denmark)

    Loh, Poh Chiang; Rong, Runjie; Blaabjerg, Frede;

    2009-01-01

    because of its inherent autosequencing process, and easier implementation using fast on-chip timers embedded in most modern digital signal processors. Motivated by these likely merits, which have previously been proven for dc-ac inverters, an investigation is now pursued here to develop appropriate...

  13. Digital control of dual-load LCLC resonant converters

    OpenAIRE

    Ang, Y.A.; Bingham, Chris; Stone, D. A.; Foster, M.

    2005-01-01

    The paper proposes the analysis, design and realisation of dual-output resonant LCLC converters with independent output regulation, employing a single power stage and combined PWM and frequency control. Asymmetric switching of the power devices is used to facilitate independent control of the outputs to provide +5 V and +3.3 V from a 15 V-20 V input supply over a range of load conditions

  14. Top-down methodology employing hardware description languages (HDLs) for designing digital control in power converters

    OpenAIRE

    Laguna Ruiz, Leonardo; Prieto López, Roberto; Oliver Ramírez, Jesús Angel; Cobos Márquez, José Antonio

    2008-01-01

    This paper presents a research line oriented to develop methodologies that takes advantage of hardware description languages in order to simplify the design of power converters that employ digital control techniques. The methodology focuses on setting the adequate communications among subsystems in order to simplify the change of the levels of abstraction of the subsystem’s models (from the conceptual level to the actual electric + synthesizable code). Changing the level of abstraction in the...

  15. An adaptive digital controller for satellite medium power DC/DC converter

    OpenAIRE

    Skup, Konrad R.; Grudziński, Paweł; Orleański, Orleański

    2011-01-01

    In this paper the work concerning an adaptive digital controller for satellite medium power DC/DC converters is presented. The adaptive techniques and methods developed in Space Research Centre allows an implemented in VHDL controller to modify its parameters according to detected changes in operating conditions. Inductor entering from discontinuous to continuous current mode and vice versa or moving sampling instants due to changes in duty time are good examples of varying operation...

  16. Analog+digital phase and frequency detector for phase locking of diode lasers

    OpenAIRE

    Cacciapuoti, L.; M. De Angelis; Fattori, M.; Lamporesi, G.; Petelski, T.; Prevedelli, M.; Stuhler, J.; Tino, G. M.

    2005-01-01

    We describe a type of phase and frequency detector employing both an analog phase detector and a digital phase and frequency detector. The analog and digital detectors are mutually exclusive so that only one of them is active at any given time, resulting in a phase detector with both the broad capture range of digital circuits and the high speed and low noise of analog mixers. The detector has been used for phase locking the diode lasers generating the sequence of Raman pulses in an atom inte...

  17. Modelling and Simulation of Digital Compensation Technique for dc-dc Converter by Pole Placement

    Science.gov (United States)

    Shenbagalakshmi, R.; Sree Renga Raja, T.

    2015-09-01

    A thorough and effective analysis of the dc-dc converters is carried out in order to achieve the system stability and to improve the dynamic performance. A small signal modelling based on state space averaging technique for dc-dc converters is carried out. A digital state feedback gain matrix is derived by pole placement technique in order to achieve the stability of a completely controllable system. A prediction observer for the dc-dc converters is designed and a dynamic compensation (observer plus control law) is provided using separation principle. The output is very much improved with zero output voltage ripples, zero peak overshoot, and much lesser settling time in the range of ms and with higher overall efficiency (>90 %).

  18. Comparison of the analog and digital pulse-shaping methods in signal processing in nuclear detections

    International Nuclear Information System (INIS)

    The goal of this article is to describe the potential applications of the new improved digital techniques and provide a meaningful figure of merit for the comparison of the analog and digital methods. The experimental operation of a typical digital pulse shaper used in a spectrometer with the 23 Na source and a Ge y-ray detector is discussed. The effect of different imposed dead time on the counted pulses is investigated. It is noticed that nuclear events distribution in all ranges of dead time does not obey Poisson's law and deviation from this distribution depends on the counting rate. For a given dead time, deviation from this distribution increases linearly by increasing imposed dead time. For a fixed dead time, when counting rate increases deviation from Poisson's distribution law increases accordingly, and vice versa. (Author)

  19. Design of Multi-bit Sigma-Delta Modulators for Digital Wireless Communications

    OpenAIRE

    Li, Bingxin

    2003-01-01

    The ever advance of CMOS digital circuit process leads tothe trend of digitizing an analog signal and performing digitalsignal processing as early as possible in a signal processingsystem, which in turn leads to an increasing requirement onanalog- to-digital converter (ADC). A wireless transceiver is asuch kind of signal processing system. Conventionaltransceivers manipulate (filter, amplify and mix) the signalmostly in analog domain. Since analog filters are difficult todesign onchip, the sy...

  20. Thermal margin budgets in the analog/digital core protection and monitoring

    International Nuclear Information System (INIS)

    The core thermal margins of the analog/digital core protection and monitoring systems were assessed for Yonggwang units 3-4 and SMART. The setpoints associated with the analog (OP Δ T /OT Δ T trip function) and the digital systems were determined using the design data of each plant. Following the standard procedure for core thermal margin assessment, the net DNB and LPD overpower margins were estimated and compared for each plant with the analog or digital systems. It was found that the DNB overpower margin is more limiting than the LPD overpower margin for both the protection systems and plants. The limiting DNB overpower margins of the digital core protection system are greater than those of the analog system by 7.5% and 11.1% of rated power for Yonggwang units 3-4 and SMART, respectively

  1. Number-to-voltage converter on commutated condensers

    International Nuclear Information System (INIS)

    A code-voltage converter using precision voltage dividers based on commutated capacitors [1] is described which is distinguished by the absence of precision elements. Each digit includes eight field-effect transistors in two 1KT682 microcircuit assemblies and three microcapacitors with a conventional unstable capacitance 6200 pF +- 50%. The converter has a speed of response that is not inferior to that of converters based on R-2R matrices, while in time stability of the characteristics, low interference level, and low output impedance it is superior to such converters

  2. Documentary Realism, Sampling Theory and Peircean Semiotics: electronic audiovisual signs (analog or digital as indexes of reality

    Directory of Open Access Journals (Sweden)

    Hélio Godoy

    2007-07-01

    Full Text Available This paper addresses Documentary Realism, focusing on thephysical phenomena of transduction that take place in analog and digital audiovisual systems, herein analyzed in the light of the Sampling Theory, within the framework of Shannon and Weaver’s Information Theory. Transduction is a process by which one type of energy is transformed into another, or by which information is transcodified. Within the scope of Documentary Realism, it cannotbe claimed that electronic audiovisual signs, because of their technical digital features lead to a rupture with reality. Rather, the digital documentary, based on electronic digital cinematography, is still an index of reality.

  3. Secure Hybrid Digital-Analog Coding With Side Information at the Receiver

    CERN Document Server

    Bagherikaram, Ghadamali

    2011-01-01

    In this work, the problem of transmitting an i.i.d Gaussian source over an i.i.d Gaussian wiretap channel with an i.i.d Gaussian side information available at the intended receiver is considered. The intended receiver is assumed to have a certain minimum SNR and the eavesdropper is assumed to have a strictly lower SNR, compared to the intended receiver. The objective is to minimize the distortion of source reconstruction at the intended receiver. In this work, it is shown that the source-channel separation coding scheme is optimum in the sense of achieving minimum distortion. Two hybrid digital-analog Wyner-Ziv coding schemes are then proposed which achieve the minimum distortion. These secure joint source-channel coding schemes are based on the Wyner-Ziv coding scheme and wiretap channel coding scheme when the analog source is not explicitly quantized. The proposed secure hybrid digital-analog schemes are analyzed under the main channel SNR mismatch. It is proven that the proposed schemes can give a graceful...

  4. A Time-Delay Suppression Technique for Digital PWM Control Circuit

    OpenAIRE

    Ishizuka, Yoichi

    2010-01-01

    This paper describes a digital PWM controller IC without A/D converters. The analog timing converter (ATC) is proposed for output voltage sensing. In this system, analog circuit are realized with an comparator and an D/A converter.

  5. Noise and resolution with digital filtering for nuclear spectrometry

    International Nuclear Information System (INIS)

    Digital noise filtering looks very promising for semiconductor spectrometry. The resolution and conversion speed of the analog to digital converter (ADC) used at the input of a digital signal processor and analyzer can strongly influence the signal to noise ratio, the peak position and shape. The article leads with the investigation of these effects using computer modelling. (orig.)

  6. Systems and methods for self-synchronized digital sampling

    Science.gov (United States)

    Samson, Jr., John R. (Inventor)

    2008-01-01

    Systems and methods for self-synchronized data sampling are provided. In one embodiment, a system for capturing synchronous data samples is provided. The system includes an analog to digital converter adapted to capture signals from one or more sensors and convert the signals into a stream of digital data samples at a sampling frequency determined by a sampling control signal; and a synchronizer coupled to the analog to digital converter and adapted to receive a rotational frequency signal from a rotating machine, wherein the synchronizer is further adapted to generate the sampling control signal, and wherein the sampling control signal is based on the rotational frequency signal.

  7. Design of Monolithic Integrator for Strain-to-Frequency Converter

    Directory of Open Access Journals (Sweden)

    Tuan Mohd. Khairi Tuan Mat

    2012-01-01

    Full Text Available Strain-to-Frequency converter (SFC is a one of the analog conditioner tools that converts any strain signal to the frequency signal. The basic concept of SFC is by detecting any changing of strains, then converting the strain to the voltage signal and converting the voltage signal to the frequency signal. This tool consists of 3 main  components which are strain gauge, differential integrator and comparator. This paper presents the designing and analysis of monolithic integrator that to be used in the Strain-toFrequency converter. The primary goal is to design and simulate the performance of monolithic integrator for SFC using GATEWAY Silvaco Electronic Design Automation (S EDA tools and EXPERT software. The performances of SFC using the designed monolithic integrator are also investigated.

  8. Energy-Efficient Large-Scale Antenna Systems with Hybrid Digital-Analog Beamforming Structure

    Institute of Scientific and Technical Information of China (English)

    Shuangfeng Han; ChihLin I; Zhikun Xu; Qi Sun; Haibin Li

    2015-01-01

    A large⁃scale antenna system (LSAS) with digital beamforming is expected to significantly increase energy efficiency (EE) and spectral efficiency (SE) in a wireless communication system. However, there are many challenging issues related to calibration, en⁃ergy consumption, and cost in implementing a digital beamforming structure in an LSAS. In a practical LSAS deployment, hybrid digital⁃analog beamforming structures with active antennas can be used. In this paper, we investigate the optimal antenna configu⁃ration in an N × M beamforming structure, where N is the number of transceivers, M is the number of active antennas per trans⁃ceiver, where analog beamforming is introduced for individual transceivers and digital beamforming is introduced across all N transceivers. We analyze the green point, which is the point of maximum EE on the EE⁃SE curve, and show that the log⁃scale EE scales linearly with SE along a slope of ⁃lg2/N. We investigate the effect of M on EE for a given SE value in the case of fixed NM and independent N and M. In both cases, there is a unique optimal M that results in optimal EE. In the case of independent N and M, there is no optimal (N, M) combination for optimizing EE. The results of numerical simulations are provided, and these re⁃sults support our analysis.

  9. Proposal for a fast, zero suppressing circuit for the digitization of analog pulses over long memory times

    International Nuclear Information System (INIS)

    This report describes the design principles of a fast (100 MHz) time and pulse height digitizer that can record up to 15 analog pulses over 10-80 μs memory times. Unlike other triggered circuits prepulse samples are recorded without the help of an analog delay line. The low power requirements of the circuit as well as its fast read-out characteristics make it very attractive for detectors with many digitizing channels. Conventional circuits are described as a reference for the evaluation of this new design. An ECL 10 K implementation of the circuit is presented in the third section. (orig.)

  10. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...

  11. Wideband precision analog telemetry link using digital techniques

    International Nuclear Information System (INIS)

    A highly linear Wideband Analog Fiber Optic Link is described which samples at a 1 MHz rate with 10-bit accuracy and transmits and receives by means of a high speed PDM code. Aliasing and sampling effects are fully suppressed and a nearly Gaussian pulse response is attained with a 2 μsec risetime. Analog signals are recovered with very low distortion and d.c. drift and a S/N ratio of better than 52 db

  12. SOI Fully complementary BI-JFET-MOS technology for analog-digital applications with vertical BJT's

    International Nuclear Information System (INIS)

    A silicon-on-insulator, fully complementary, Bi-JFET-MOS technology has been developed for realizing multi-megarad hardened mixed analog-digital circuits. The six different active components plus resistors and capacitors have been successfully integrated in a 25-mask process using SIMOX substrate and 1 μm thick epitaxial layer. Different constraints such as device compatibility, complexity not higher than BiCMOS technology and breakdown voltages suitable for analog applications have been considered. Several process splits have been realized and all the characteristics presented here have been measured on the same split. P+ gate is used for PMOS transistor to get N and PMOST symmetrical characteristics. Both NPN and PNP vertical bipolar transistors with poly-emitters show fT > 5 GHz. 2-separated gate JFET's need no additional mask. (authors). 9 figs., 1 tab

  13. Performance Comparison of Reflector- and Planar-Antenna based Digital Beam-Forming SAR

    OpenAIRE

    Marwan Younis; Sigurd Huber; Anton Patyuchenko; Federica Bordoni; Gerhard Krieger

    2009-01-01

    The trend in the conception of future spaceborne radar remote sensing is clearly toward the use of digital beamforming techniques. These systems will comprise multiple digital channels, where the analog-to-digital converter is moved closer to the antenna. This dispenses the need for analog beam steering and by this the used of transmit/receive modules for phase and amplitude control. Digital beam-forming will enable Synthetic Aperture Radar (SAR) which overcomes the coverage and resolution li...

  14. Implementation of FPGA based Digital Controller for Controlling Chaos in DC/DC converters

    OpenAIRE

    RANJAN Vanaja; LOGAMANI Premalatha

    2010-01-01

    This paper analyzes the subharmonics andchaos generated in closed loop pulse width modulatedDC/DC buck converter and suggests the implementationof Digital controller based on time delayed selfcontrolling feedback concept for stabilizing the chaosgenerated in such converter. FPGA based digitalcontroller is designed and implemented for controllingthe chaotic oscillations of nonlinear switching converters.An experimental FPGA prototype and an applicationspecific IC that employ new controller arc...

  15. An FPGA-optimized high resolution time-to-digital converter array%针对FPGA优化的高分辨率时间数字转换阵列电路

    Institute of Scientific and Technical Information of China (English)

    杨洋; 阮爱武; 廖永波; 吴文杰

    2011-01-01

    介绍一种针对FPGA优化的时间数字转换阵列电路.利用FPGA片上锁相环对全局时钟进行倍频与移相,通过时钟状态译码的方法解决了FPGA中延迟的不确定性问题,完成时间数字转换的功能.在Altera公司的FPGA上验证表明,本时间数字转换阵列可达1.73 ns的时间分辨率.转换阵列具有占用资源少,可重用性高,可以作为IP核方便地移植到其他设计中.%An FPGA-optimized high resolution time-to-digital converter array is proposed. In this design, we adapt the on-chip PLL as the frequency double circuit and the clock phase shifter. We use the method of clock state decoding to solve the delay uncertainty for FPGA, thereby fulfill the time to digital convert. The circuit has been implemented via FPGA produced by Altera Corp. The result shows that the time resolution is 1.73 ns. It enjoys the advantages of less resource usage, high reusability and easy implantation as IP cores.

  16. A low-delay digital PWM control circuit for DC-DC converters

    OpenAIRE

    Ishizuka, Yoichi; Ueno, Masao; Nishikawa, Ichiro; Ichinose, Akira; Matsuo, Hirofumi

    2007-01-01

    This paper is descried about a proposed scheme of a low-cost digital pulse width modulation (DPWM) control circuit for non-isolated DC-DC converter without A/D converter. Also,real-time PID control technique for DPWM is described. Some experimental results are revealed the proposed circuit and scheme. The purpose of this research is striking a balance between minimizing cost increase by digitalizing of the control circuit of DC-DC converter and speeding up the control circuit.

  17. Approaches to synthetic platelet analogs.

    Science.gov (United States)

    Modery-Pawlowski, Christa L; Tian, Lewis L; Pan, Victor; McCrae, Keith R; Mitragotri, Samir; Sen Gupta, Anirban

    2013-01-01

    Platelet transfusion is routinely used for treating bleeding complications in patients with hematologic or oncologic clotting disorders, chemo/radiotherapy-induced myelosuppression, trauma and surgery. Currently, these transfusions mostly use allogeneic platelet concentrates, while products like lyophilized platelets, cold-stored platelets and infusible platelet membranes are under investigation. These natural platelet-based products pose considerable risks of contamination, resulting in short shelf-life (3-5 days). Recent advances in pathogen reduction technologies have increased shelf-life to ~7 days. Furthermore, natural platelets are short in supply and also cause several biological side effects. Hence, there is significant clinical interest in platelet-mimetic synthetic analogs that can allow long storage-life and minimum side effects. Accordingly, several designs have been studied which decorate synthetic particles with motifs that promote platelet-mimetic adhesion or aggregation. Recent refinement in this design involves combining the adhesion and aggregation functionalities on a single particle platform. Further refinement is being focused on constructing particles that also mimic natural platelet's shape, size and elasticity, to influence margination and wall-interaction. The optimum design of a synthetic platelet analog would require efficient integration of platelet's physico-mechanical properties and biological functionalities. We present a comprehensive review of these approaches and provide our opinion regarding the future directions of this research. PMID:23092864

  18. How to deal with substrate bounce in analog circuits in epi-type CMOS technology

    NARCIS (Netherlands)

    Nauta, Bram; Hoogzaad, Gian; Donnay, S.; Gielen, G.

    2003-01-01

    Substrate noise is one of the key problems in mixed analog/digital ICs. Although measures are known to reduce substrate noise, the noise will never be completely eliminated since this requires larger chip area or exotic packages and thus higher cost. Analog circuits on digital ICs simply have to be

  19. Digital versus analog complete-arch impressions for single-unit premolar implant crowns : Operating time and patient preference

    NARCIS (Netherlands)

    Schepke, Ulf; Meijer, Henny J. A.; Kerdijk, Wouter; Cune, Marco S.

    2015-01-01

    Statement of problem. Digital impression-making techniques are supposedly more patient friendly and less time-consuming than analog techniques, but evidence is lacking to substantiate this assumption. Purpose. The purpose of this in vivo within-subject comparison study was to examine patient percept

  20. Leistungseffiziente Analog-Digital-Umsetzer mit sukzessivem Approximationsregister

    OpenAIRE

    Digel, Johannes

    2015-01-01

    In der Signalverarbeitung und Kommunikation zeichnet sich ein Trend weg vom Analogen hin zum Digitalen ab. Vorteile von digitalen Daten sind, dass ihre physikalische Darstellung losgelöst davon ist, was sie physikalisch repräsentieren, dass zu ihrer Verarbeitung standardisierte Schaltungskomponenten angewendet und spezialisierte Komponenten synthetisiert werden können, sowie dass sie verlustfrei übertragen und gespeichert werden können. Dafür müssen analoge Signale, die beispielsweise von ein...

  1. An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor

    Directory of Open Access Journals (Sweden)

    Yi-Xin Guo

    2015-12-01

    Full Text Available Inductive proximity sensors (IPSs are widely used in position detection given their unique advantages. To address the problem of temperature drift, this paper presents an analog-digital mixed measurement method based on the two-dimensional look-up table. The inductance and resistance components can be separated by processing the measurement data, thus reducing temperature drift and generating quantitative outputs. This study establishes and implements a two-dimensional look-up table that reduces the online computational complexity through structural modeling and by conducting an IPS operating principle analysis. This table is effectively compressed by considering the distribution characteristics of the sample data, thus simplifying the processing circuit. Moreover, power consumption is reduced. A real-time, built-in self-test (BIST function is also designed and achieved by analyzing abnormal sample data. Experiment results show that the proposed method obtains the advantages of both analog and digital measurements, which are stable, reliable, and taken in real time, without the use of floating-point arithmetic and process-control-based components. The quantitative output of displacement measurement accelerates and stabilizes the system control and detection process. The method is particularly suitable for meeting the high-performance requirements of the aviation and aerospace fields.

  2. An Analog-Digital Mixed Measurement Method of Inductive Proximity Sensor.

    Science.gov (United States)

    Guo, Yi-Xin; Shao, Zhi-Biao; Li, Ting

    2015-01-01

    Inductive proximity sensors (IPSs) are widely used in position detection given their unique advantages. To address the problem of temperature drift, this paper presents an analog-digital mixed measurement method based on the two-dimensional look-up table. The inductance and resistance components can be separated by processing the measurement data, thus reducing temperature drift and generating quantitative outputs. This study establishes and implements a two-dimensional look-up table that reduces the online computational complexity through structural modeling and by conducting an IPS operating principle analysis. This table is effectively compressed by considering the distribution characteristics of the sample data, thus simplifying the processing circuit. Moreover, power consumption is reduced. A real-time, built-in self-test (BIST) function is also designed and achieved by analyzing abnormal sample data. Experiment results show that the proposed method obtains the advantages of both analog and digital measurements, which are stable, reliable, and taken in real time, without the use of floating-point arithmetic and process-control-based components. The quantitative output of displacement measurement accelerates and stabilizes the system control and detection process. The method is particularly suitable for meeting the high-performance requirements of the aviation and aerospace fields. PMID:26729118

  3. Systematic selection of analogue redesign method for forward-type digital power converters

    Science.gov (United States)

    Cave-Ayland, Kim; Becerra, Victor M.; Potter, Benjamin; Shirsavar, Seyed

    2014-05-01

    This article proposes a systematic approach to determine the most suitable analogue redesign method to be used for forward-type converters under digital voltage mode control. The focus of the method is to achieve the highest phase margin at the particular switching and crossover frequencies chosen by the designer. It is shown that at high crossover frequencies with respect to switching frequency, controllers designed using backward integration have the largest phase margin; whereas at low crossover frequencies with respect to switching frequency, controllers designed using bilinear integration with pre-warping have the largest phase margins. An algorithm has been developed to determine the frequency of the crossing point where the recommended discretisation method changes. An accurate model of the power stage is used for simulation and experimental results from a Buck converter are collected. The performance of the digital controllers is compared to that of the equivalent analogue controller both in simulation and experiment. Excellent closeness between the simulation and experimental results is presented. This work provides a concrete example to allow academics and engineers to systematically choose a discretisation method.

  4. A method of temperature measurement based on time-to-digital converter technology%基于时间数字转化技术的温度测量

    Institute of Scientific and Technical Information of China (English)

    胡文波; 徐东明; 陈文宣

    2011-01-01

    In order to improve the accuracy of temperature measurement,a kind of Time-to-Digital conversion(TDC) technology is introduced,by which,the temperature can be got from measurement of the time intervals.In other words,the change value of the temperature can be converted into some time intervals when the Resistance-Capacitance(RC) circuit is charged or discharged.Simulation results shows that,the temperature measurement accuracy will be incresed by(0.020±0.004)℃ when TDC is used.Temperature measurement with this technology is of higher accuracy and lower power consumption.%为了提高温度测量的精度,提出一种应用时间数字转化技术(Time-to-Digital Converter,TDC)测量时间间隔从而测得温度的方法。对RC电路充、放电,将温度数值的改变量转化为对时间间隔长度的数值采集,应用TDC进行时间间隔测量以提高其温度测量精确度。仿真实验显示,使用TDC技术能将温度测量精度提高到(0.020±0.004)℃,说明该技术对温度测量具有高精度、低功耗的优势。

  5. Digital Solution to Mining Image Monitor System

    Institute of Scientific and Technical Information of China (English)

    刘越男; 孙继平; 苏辉; 那景芳

    2001-01-01

    The thesis describes an advanced digital solution to mining digital image monitor system, which makes up the shortage of the traditional mining analog image monitor. It illustrates the system components and how to choose the encoder bandwidth of the system. The problem of image multicast and its solution in LAN are also discussed.

  6. 23rd workshop on Advances in Analog Circuit Design

    CERN Document Server

    Baschirotto, Andrea; Makinwa, Kofi

    2015-01-01

    This book is based on the 18 tutorials presented during the 23rd workshop on Advances in Analog Circuit Design.  Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, serving as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development.    • Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing; • Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; • Presents material in a tutorial-based format.

  7. Study of HVDC Controls Through Efficient Dynamic Digital Simulation of Converters

    OpenAIRE

    Padiyar, KR; Sachchidanand,; Kothari, AG; Bhattacharyya, S.; Srivastava, A

    1989-01-01

    This paper describes the converter model for 6/12 pulse operation and presents its applic ations for the study of the performance of converter controls. The simulation is simplified by representing the converter as a time varying equivalent circuit on the DC side which is derived on the basis of graph theory. Elimination of the need to store connection matrices and an efficient way of generating the converter equations are further innovations introduced here. The converter control based o...

  8. Digital coherent receiver employing photonic downconversion for phase modulated radio-over-fibre links

    DEFF Research Database (Denmark)

    Zibar, Darko; Caballero Jambrina, Antonio; Guerrero Gonzalez, Neil; Schaeffer, Christian; Tafur Monroy, Idelfonso

    A digital coherent receiver employing photonic downconversion is presented and experimentally demonstrated for phase-modulated radio-over-fibre optical links. The receiver is capable of operating at frequencies exceeding the bandwidth of electrical analog-to-digital converter by using photonic...... downconversion to translate the high-frequency input RF signal to the operating frequency range of the analog-to-digital converter. First, using linear digital demodulation scheme we measure SFDR of the link at microwave frequency of 5 GHz. Thereafter, successful signal demodulation of 50 Mbit/s binary phase...... shift keying (BPSK) modulated data signal at 5 GHz RF carrier frequency is experimentally demonstrated by using an analog-to-digital converter with only 1 GHz bandwidth. We successfully demonstrate signal demodulation, using the proposed digital coherent receiver with photonic downconversion, after 40...

  9. Mixed Analog/Digital Matrix-Vector Multiplier for Neural Network Synapses

    DEFF Research Database (Denmark)

    Lehmann, Torsten; Bruun, Erik; Dietrich, Casper

    1996-01-01

    In this work we present a hardware efficient matrix-vector multiplier architecture for artificial neural networks with digitally stored synapse strengths. We present a novel technique for manipulating bipolar inputs based on an analog two's complements method and an accurate current rectifier...

  10. The Design of MSK Demodulator Using Time-to-Digital Converter%基于时间数字转换技术的 MS K解调器设计

    Institute of Scientific and Technical Information of China (English)

    韩爽; 万美琳; 李聪; 戴葵; 邹雪城

    2015-01-01

    A new MSK demodulator is designed and realized with Time‐to‐Digital Converter (TDC ) technique in accordance to IEEE 802 .15 .4 standard .It consists of Limiter ,TDC and Data Recovery Circuit .Limiter amplifies the input signal of demodulator to rail‐to‐rail .After that ,TDC measures the frequency of the amplified signal by detecting the zero‐crossing and converts it into binary code .Finally ,the original transmitted data is recovered from the binary code by Data Recovery Circuit .The theoretical model of demodulator is given to analyze the affect factors of system performance .The demodulator is implemented in TSMC 0 .18 μm CMOS technology with the layout area of 0 .1 mm2 .The theoretical and practical simulation results simultaneously show that the proposed demodulator achieves PER of 1% with SNR of 8 .7 dB and power consumption of less than 1 mW ,which meets the requirement of low power and low cost .%采用时间数字转换技术(Time‐to‐Digital Converter ,TDC),设计实现了一种新型符合IEEE 802.15.4标准的MSK解调器.该解调器由限幅放大器、时间数字转换器和数据恢复电路组成,解调器的输入信号被限幅放大器放大至轨到轨,经过T DC过零检测以提取信号的频率信息,并将其转换为二进制码,提供给数据恢复电路处理,恢复出原始发射数据.对解调器进行了理论建模,分析系统性能的影响因素.该解调器基于TSMC 0.18μm CMOS工艺设计,版图面积仅为0.1 mm2.理论模型和实际电路的仿真结果同时表明,提出的解调器在误包率(Packet Error Rate ,PER)低于1%时所需的信噪比仅为8.7 dB ,且功耗小于1 mW ,满足低成本低功耗的设计要求.

  11. Application of real time digital simulation in modeling wind turbines with reduced and full converter schemes

    Energy Technology Data Exchange (ETDEWEB)

    Protsenko, K.; Badrzadeh, B. [Vestas Technology R and D, Aarhus (Denmark); Mayer, P.F. [Vestas Technology R and D, Singapore (Singapore); Luo, Z. [Vestas Americas, Houston, TX (United States)

    2011-07-01

    This paper presents the application of a real-time digital simulation program for wind turbine modeling of a doubly-fed induction generator (type 3) and a fully-converted permanent magnet synchronous generator (type 4). Vestas type 3 and type 4,3 MW turbines are taken as representative for the two turbine types, respectively. The paper begins with an overview of the hardware details used for the simulation studies, outlines the assumptions applied to derive the models, and highlights the limitations imposed by the use of a real time digital simulation program. The implementation of both types of turbine models is then discussed. The validation of both models against electromagnetic time domain simulation results obtained from PSCAD is shown. The validation test performed is the evaluation of low voltage ride through capability of the turbine. Results obtained from the real time digital simulation provide a good match with the PSCAD simulation results, which have in turn been validated against field measurements. This gives confidence in the future application of such real time models, for example in wind power plant protection relay coordination. (orig.)

  12. A physical analogy to fuzzy clustering

    DEFF Research Database (Denmark)

    Jantzen, Jan

    2004-01-01

    This tutorial paper provides an interpretation of the membership assignment in the fuzzy clustering algorithm fuzzy c-means. The membership of a data point to several clusters is shown to be analogous to the gravitational forces between bodies of mass. This provides an alternative way to explain...... the algorithm to students. The analogy suggests a possible extension of the fuzzy membership assignment equation....

  13. The SIRIUS Mixed analog-digital ASIC developed for the LOFT LAD and WFM instruments

    CERN Document Server

    Cros, A; Moutaye, E; Ravera, L; Barret, D; Caïs, P; Clédassou, R; Bodin, P; Seyler, JY; Bonzo, A; Feroci, M; Labanti, C; Evangelista, Y; Favre, Y

    2014-01-01

    We report on the development and characterization of the low-noise, low power, mixed analog-digital SIRIUS ASICs for both the LAD and WFM X-ray instruments of LOFT. The ASICs we developed are reading out large area silicon drift detectors (SDD). Stringent requirements in terms of noise (ENC of 17 e- to achieve an energy resolution on the LAD of 200 eV FWHM at 6 keV) and power consumption (650 {\\mu}W per channel) were basis for the ASICs design. These SIRIUS ASICs are developed to match SDD detectors characteristics: 16 channels ASICs adapted for the LAD (970 microns pitch) and 64 channels for the WFM (145 microns pitch) will be fabricated. The ASICs were developed with the 180nm mixed technology of TSMC.

  14. Multi-scale entropy analysis of VR-based analog-digital system of the operator mental workload

    International Nuclear Information System (INIS)

    In the past, serious accidents of nuclear power plant usually had relation with the negligence, error handling and wrong decisions of operators. Therefore, to understand and be able to measure mental workload levels of operators are significant for safety issues in the nuclear power plant, especially when operators face emergency conditions. Therefore, this study is to determine the physiological indicators to measure the operator in the task of mental workload. This paper was to use electrocardiogram (ECG) measurements, to collect the RR-Interval data; heart rate variability (HRV) to analysis the complexity of the operator. After importing the data to calculate heart rate variability of complexity analysis, it can help us to understand the operator for the analog-digital platform adaptation. The virtual analog-digital nuclear plant control room is built using a 3D game development tool called Unity3D. (author)

  15. Tissue-plastinated vs. celloidin-embedded large serial sections in video, analog and digital photographic on-screen reproduction: a preliminary step to exact virtual 3D modelling, exemplified in the normal midface and cleft-lip and palate

    Science.gov (United States)

    Landes, Constantin A; Weichert, Frank; Geis, Philipp; Wernstedt, Katrin; Wilde, Anja; Fritsch, Helga; Wagner, Mathias

    2005-01-01

    This study analyses tissue-plastinated vs. celloidin-embedded large serial sections, their inherent artefacts and aptitude with common video, analog or digital photographic on-screen reproduction. Subsequent virtual 3D microanatomical reconstruction will increase our knowledge of normal and pathological microanatomy for cleft-lip-palate (clp) reconstructive surgery. Of 18 fetal (six clp, 12 control) specimens, six randomized specimens (two clp) were BiodurE12-plastinated, sawn, burnished 90 µm thick transversely (five) or frontally (one), stained with azureII/methylene blue, and counterstained with basic-fuchsin (TP-AMF). Twelve remaining specimens (four clp) were celloidin-embedded, microtome-sectioned 75 µm thick transversely (ten) or frontally (two), and stained with haematoxylin–eosin (CE-HE). Computed-planimetry gauged artefacts, structure differentiation was compared with light microscopy on video, analog and digital photography. Total artefact was 0.9% (TP-AMF) and 2.1% (CE-HE); TP-AMF showed higher colour contrast, gamut and luminance, and CE-HE more red contrast, saturation and hue (P < 0.4). All (100%) structures of interest were light microscopically discerned, 83% on video, 76% on analog photography and 98% in digital photography. Computed image analysis assessed the greatest colour contrast, gamut, luminance and saturation on video; the most detailed, colour-balanced and sharpest images were obatined with digital photography (P < 0.02). TP-AMF retained spatial oversight, covered the entire area of interest and should be combined in different specimens with CE-HE which enables more refined muscle fibre reproduction. Digital photography is preferred for on-screen analysis. PMID:16050904

  16. Utilization of the voltage frequency converter or digital representation and documentation of transient reactor operation

    International Nuclear Information System (INIS)

    The ease and speed of handling transient data is enhanced by the use of a voltage to frequency converter (VFC). This analogue to digital semiconductor device provides an inexpensive and portable alternative to electro-mechanical recorders and hand entry of data into computer codes. The VFC used at The University of Arizona is a Teledyne Philbrick 4705/01. A zero to positive ten volt input signal provides a zero to one megahertz output signal which is TTL/DTL compatible. VFC is used at the University of Arizona to collect data for super prompt critical TRIGA excursions. The VFC provides a low cost, convenient method of transient data storage and retrieval for experimentation and laboratory demonstration

  17. Image Resolution in the Digital Era: Notion and Clinical Implications

    Directory of Open Access Journals (Sweden)

    Vahid Rakhshan

    2014-05-01

    Full Text Available Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs.

  18. Image Resolution in the Digital Era: Notion and Clinical Implications

    Directory of Open Access Journals (Sweden)

    Vahid Rakhshan

    2014-12-01

    Full Text Available Digital radiographs need additional metadata in order to be accurate when being converted to analog media. Resolution is a major reason of failures in proper printing or digitizing the images. This letter shortly explains the overlooked pitfalls of digital radiography and photography in dental practice, and briefly instructs the reader how to avoid or rectify common problems associated with resolution calibration of digital radiographs.

  19. From Theory to Practice: Sub-Nyquist Sampling of Sparse Wideband Analog Signals

    OpenAIRE

    Mishali, Moshe; Eldar, Yonina C.

    2009-01-01

    Conventional sub-Nyquist sampling methods for analog signals exploit prior information about the spectral support. In this paper, we consider the challenging problem of blind sub-Nyquist sampling of multiband signals, whose unknown frequency support occupies only a small portion of a wide spectrum. Our primary design goals are efficient hardware implementation and low computational load on the supporting digital processing. We propose a system, named the modulated wideband converter, which fi...

  20. Digital to Analog Converter PCM1738 with PCM and DSD%具有PCM和DSD双功能的DAC芯片PCM1738

    Institute of Scientific and Technical Information of China (English)

    钱志远

    2002-01-01

    PCM1738是B-B公司生产的高级数模转换数码音响芯片,利用它可以同时对SACD音频格式的DSD数据流和DVD-Audio用的PCM编码进行数模变换和解码.文中介绍了PCM1738的基本原理、主要性能指标及应用信息,同时对其高级段DAC和电流段DAC的新技术做了描述.

  1. Computational approaches to analogical reasoning current trends

    CERN Document Server

    Richard, Gilles

    2014-01-01

    Analogical reasoning is known as a powerful mode for drawing plausible conclusions and solving problems. It has been the topic of a huge number of works by philosophers, anthropologists, linguists, psychologists, and computer scientists. As such, it has been early studied in artificial intelligence, with a particular renewal of interest in the last decade. The present volume provides a structured view of current research trends on computational approaches to analogical reasoning. It starts with an overview of the field, with an extensive bibliography. The 14 collected contributions cover a large scope of issues. First, the use of analogical proportions and analogies is explained and discussed in various natural language processing problems, as well as in automated deduction. Then, different formal frameworks for handling analogies are presented, dealing with case-based reasoning, heuristic-driven theory projection, commonsense reasoning about incomplete rule bases, logical proportions induced by similarity an...

  2. High-accuracy fit of the poles of spectroscopy amplifiers designed for mixed analog-digital filtering

    International Nuclear Information System (INIS)

    In this paper, a method for the identification of the poles' and zeros' position of an analog amplifier for nuclear spectroscopy used as a prefilter for a subsequent digital filter setup is presented. The proposed technique is based upon a subspace-based system state-space identification (4SID) method, which is well suited to a data set constituted by a noisy measurement of the sampled impulse response of the circuit. The algorithm runs unassisted and does not require skills by the operator. The experiments confirm that by using the so-obtained pole values, the shape of the impulse response of the amplifier can be fit with much better than 1% accuracy. Consequently, the overall filtering (analog + digital) can have finite duration and a top with a flatness much better than 1%

  3. An assessment of reference exposure in analogic and digital mammographic units

    Science.gov (United States)

    Tilly, J. G.; Miguel, C.; Schelin, H. R.; Porto, L. E.; Paschuk, S.; Denyak, V.; Kmiecik, C.

    2014-11-01

    In this study, the incident air kerma (Ki,a), half-value layer (HVL), output and voltage accuracy for 28 mammography services were evaluated. All mammographs had high frequency rectification, a focus-film distance greater than 60 cm, automatic exposure control, a Mo-Mo anode-filter combination, and compression system. Twenty-three evaluations were made of analogic imaging systems and 21 of digital imaging systems, two of which were full field digital mammography units. The Ki,a was measured in the beam radiation with a 6 cm3 ionization chamber, calibrated for a mammography range of energy. A standard American College of Radiology mammographic phantom simulated a skull caudal incidence. The average, minimum, and maximum Ki,a values were 10.13 mGy, 3.92 mGy, and 30.41 mGy, respectively. However, when the analogic and digital systems are analyzed separately in two subsets, the values were 8.13 mGy, 3.92 mGy, and 11.78 mGy for the analogic systems and 12.33 mGy, 5.21 mGy, and 30.41 mGy for the digital systems, respectively. The results show that the Ki,a values found in digital systems were higher than those in analogic systems, highlighting the differences between these acquisition systems. All HVL values, measured in the primary beam at 28 kV were found between 0.33 mm Al and 0.43 mm Al. Although the manufacture time of the equipment was approximately 146 months (~12 years) prior, the variation in output was between 0.071 mGy/mAs and 0.164 mGy/mAs for the entire sample.

  4. Experimental investigation of analog and digital dimming techniques on photometric performance of an indoor Visible Light Communication (VLC) system

    Science.gov (United States)

    Zafar, Fahad; Kalavally, Vineetha; Bakaul, Masuduzzaman; Parthiban, R.

    2015-09-01

    For making commercial implementation of light emitting diode (LED) based visible light communication (VLC) systems feasible, it is necessary to incorporate it with dimming schemes which will provide energy savings, moods and increase the aesthetic value of the places using this technology. There are two general methods which are used to dim LEDs commonly categorized as analog and digital dimming. Incorporating fast data transmission with these techniques is a key challenge in VLC. In this paper, digital and analog dimming for a 10 Mb/s non return to zero on-off keying (NRZ-OOK) based VLC system is experimentally investigated considering both photometric and communicative parameters. A spectrophotometer was used for photometric analysis and a line of sight (LOS) configuration in the presence of ambient light was used for analyzing communication parameters. Based on the experimental results, it was determined that digital dimming scheme is preferable for use in indoor VLC systems requiring high dimming precision and data transmission at lower brightness levels. On the other hand, analog dimming scheme is a cost effective solution for high speed systems where dimming precision is insignificant.

  5. Preliminary results of Digital Pulse Shape Acquisition from Chimera

    Energy Technology Data Exchange (ETDEWEB)

    Alderighi, D.M.; Sechi, G. [INFN Milano and IASF, CNR, Milano (France); Anzalone, A.; Cavallaro, S.; Giustolisi, F.; Laguidara, E.; Lanzalone, G.; Porto, F. [Catania Univ., LNS and Dipartimento di Fisica (France); Bassini, R.; Boiano, C.; Guazzoni, P.; Russo, S.; Sassi, M.; Zetta, L. [Milano Univ., INFN and Dipartimento di Fisica (Italy); Cardella, G.; Defilippo, S.E.; Lanzano, G.; Paganod, A.; Papa, M.; Pirrone, S.; Politi, G. [Catania Univ., INFN and Dipartimento di Fisica (Italy); Geraci, E. [Bologna Univ., INFN and Dipartimento di Fisica (Italy)

    2003-07-01

    A 100 MS/s 14-bit Sampling Analog-to-Digital converter has been used to perform digital pulse-shape acquisition of signals collected from CHIMERA telescopes. The signals from a typical CHIMERA detection cell have been collected using both a standard CHIMERA electronic chain up to the amplifier, and a very simple analog front end, basically reduced to the preamplifier. The preliminary on-beam results are presented. (authors)

  6. Preliminary results of Digital Pulse Shape Acquisition from Chimera

    International Nuclear Information System (INIS)

    A 100 MS/s 14-bit Sampling Analog-to-Digital converter has been used to perform digital pulse-shape acquisition of signals collected from CHIMERA telescopes. The signals from a typical CHIMERA detection cell have been collected using both a standard CHIMERA electronic chain up to the amplifier, and a very simple analog front end, basically reduced to the preamplifier. The preliminary on-beam results are presented. (authors)

  7. A time-to-digital converter used in photon-counting LIDAR%光子计数激光雷达时间-数字转换系统

    Institute of Scientific and Technical Information of China (English)

    侯利冰; 郭颖; 黄庚华; 舒嵘

    2012-01-01

    Timing system was used to measure the time-of-flight(TOF) of laser pulse in light detection and ranging(LIDAR). Performance of a LIDAR system is directly influenced by the properties of the liming system. A time-to-digital converter (TDC) based on FPGA was designed for photon-counting LIDAR. By integrating the delay line interpolation into FPGA, the designed TDC could measure the TOF with fine accuracy and resolution. The performance of the TDC and its application in photon-counting LIDAR were analyzed and studied experimentally. Event-timing of 9 channels was implemented with this TDC, with a resolution of 29 ps and a timing-accuracy of 37 ps. Using a LIDAR system equipped with the TDC, three-dimensional imaging can be realized with time accuracy of 421 ps and 6. 3 cm resolution in space.%时间测量系统在激光雷达中主要用于激光脉冲飞行时间的测量,其性能直接影响着激光雷达的各项指标.基于FPGA设计了一种应用于光子计数激光雷达的时间-数字转换(Time-to-Digital Converter,TDC)系统,利用延迟线内插在FPGA内部实现了高精度的时间测量,通过实验分析,研究了TDC系统的性能及其应用于光子计数激光雷达后的效果.实验结果表明,TDC系统的时间分辨率达到29ps,测时精度37ps,能够实现9通道的高精度事件计时功能,用于光子计数激光雷达后,整个激光雷达系统的测时精度为421ps,达到6.3cm的距离测量精度,能够实现高精度高分辨率的激光三维成像.

  8. Evolution of photography in maxillofacial surgery: from analog to 3D photography – an overview

    OpenAIRE

    Heidrun Schaaf; Christoph Yves Malik; Hans-Peter Howaldt; et al

    2009-01-01

    Heidrun Schaaf, Christoph Yves Malik, Hans-Peter Howaldt, Philipp StreckbeinDepartment of Maxillo-Facial Surgery, University Hospital Giessen and Marburg GmbH, Giessen, GermanyAbstract: In maxillofacial surgery, digital photographic documentation plays a crucial role in clinical routine. This paper gives an overview of the evolution from analog to digital in photography and highlights the integration of digital photography into daily medical routine. The digital workflow is described and we s...

  9. Wide-band multipath A to D converter for Cognitive Radio applications

    OpenAIRE

    Gruget, Alban; Roger, Morgan; Tam Nguyen; Lelandais-Perrault, Caroline; Benabes, Philippe; Loumeau, Patrick

    2010-01-01

    This article presents a digital-enhanced radio frequency receiver for fast wide-band spectrum sensing. It is based on charge sampling and hybrid filter bank techniques. The charge sampling method is employed to design analog bandpass filters. Using a hybrid filter bank for wide-band analog-to-digital conversion improves the speed and resolution of the conversion. We propose to use these techniques in combination of frequencydivision multiplexing with time-division multiplexing to design an in...

  10. A new highly linear MMIC single side-band converter for digital radio links

    OpenAIRE

    Rasa, F.; Pagani, M.; Gabbrielli, B.

    1998-01-01

    This paper describes the design of a very compact Monolithic Single Side-band (SSB) Mixer for Digital Radio Links. The mixer can be used in transmitters as an SSB up-converter over the 5.6-8.5 GHz range, but also in receivers as down-converter combined with Low Noise Preamplifier. All the sub-circuits except only the IF hybrids, are included in a unique small chip whose total size is 3.556 x 3.556 mm2. Very high Linear operation with more than 29dB of Image Rejection and 27dB of Carrier suppr...

  11. Simple digital PWM and PSM controlled DC-DC boost converter for luminance-regulated WLED driver

    Institute of Scientific and Technical Information of China (English)

    LIU Xin; GUO Shu-xu; CHANG Yu-chun; ZHU Shun-dong; WANG Shuai

    2009-01-01

    This article presents a control strategy based on simple digital pulse-width modulation (DPWM) and pulse-skip modulation (PSM) for a DC-DC boost converter, to drive a luminance-regulated white light emitting diodes (WLEDs). The presented control strategy not only retains most of the advantages and flexibilities of traditional digital PWM, but also reduces complexity and cost. Based on analyzing the principle of the presented control strategy, the white light emitting diode (WLED) driver is designed and simulated using the 0.6 (m CMOS process. Simulation results of the boost converter show that the power efficiency is above 76% for a full load, with a peak efficiency of 88% when supply voltage varies from 2.7 V to 5.5 V. The control strategy overcomes low efficiency for PWM mode with light load.

  12. Analog-Digital-Umsetzer für die hochbitratige Datenübertragung

    OpenAIRE

    Lang, Felix

    2014-01-01

    Diese Arbeit befasst sich mit der Theorie, der Entwicklung und der Vermessung von hochbitratigen CMOS-Analog-Digital-Wandlern. Dabei liegt durch die Entwicklung von zwei Parallel-A-D-Wandlern ein besonderer Fokus auf dieser Wandlerstruktur und auf Schaltungskomponenten zur Erweiterung dieser Architektur. Basierend auf dem Projekt 100GET werden zwei Parallelwandler mit nominaler Auflösung von 6 bit und einer Zielwandlerrate von 25 GS/s konzipiert und aufgebaut. Die A-D-Wandler besitzen Echtzei...

  13. An assessment of reference exposure in analogic and digital mammographic units

    International Nuclear Information System (INIS)

    In this study, the incident air kerma (Ki,a), half-value layer (HVL), output and voltage accuracy for 28 mammography services were evaluated. All mammographs had high frequency rectification, a focus-film distance greater than 60 cm, automatic exposure control, a Mo–Mo anode-filter combination, and compression system. Twenty-three evaluations were made of analogic imaging systems and 21 of digital imaging systems, two of which were full field digital mammography units. The Ki,a was measured in the beam radiation with a 6 cm3 ionization chamber, calibrated for a mammography range of energy. A standard American College of Radiology mammographic phantom simulated a skull caudal incidence. The average, minimum, and maximum Ki,a values were 10.13 mGy, 3.92 mGy, and 30.41 mGy, respectively. However, when the analogic and digital systems are analyzed separately in two subsets, the values were 8.13 mGy, 3.92 mGy, and 11.78 mGy for the analogic systems and 12.33 mGy, 5.21 mGy, and 30.41 mGy for the digital systems, respectively. The results show that the Ki,a values found in digital systems were higher than those in analogic systems, highlighting the differences between these acquisition systems. All HVL values, measured in the primary beam at 28 kV were found between 0.33 mm Al and 0.43 mm Al. Although the manufacture time of the equipment was approximately 146 months (∼12 years) prior, the variation in output was between 0.071 mGy/mAs and 0.164 mGy/mAs for the entire sample. - Highlights: • Ki,a, HVL, output and voltage accuracy for 28 mammography services were evaluated. • All HVL values, measured at 28 kV were found between 0.33 mm Al and 0.43 mm Al. • Variation in output was between 0.071 mGy/mAs and 0.164 mGy/mAs for the entire sample. • Ki,a values in digital systems were higher than in analogic systems

  14. Application handbook for analog IC

    International Nuclear Information System (INIS)

    This book consists of ten chapters, which are prolog on analog IC and digital, basic function of OP amp for operation, characteristic on direct current and interchange, Op amp and linear circuit, nonlinear arithmetic circuit, filter circuit, oscillation circuit and V-F converter, D-A converter, A-D converter on introduction eight bit and 12 bit, I C for power supply and switching regulator. Each chapter has the explanations of specific function of the programs, filter circuit, converters. So, this book is a application handbook for analog IC.

  15. 10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements

    International Nuclear Information System (INIS)

    We present a compact high performance time-to-digital converter (TDC) module that provides 10 ps timing resolution, 160 ns dynamic range and a differential non-linearity better than 1.5% LSBrms. The TDC can be operated either as a general-purpose time-interval measurement device, when receiving external START and STOP pulses, or in photon-timing mode, when employing the on-chip SPAD (single photon avalanche diode) detector for detecting photons and time-tagging them. The instrument precision is 15 psrms (i.e., 36 psFWHM) and in photon timing mode it is still better than 70 psFWHM. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via an user-friendly software interface. The module proves to be the best candidate for a wide variety of applications such as: fluorescence lifetime imaging, time-of-flight ranging measurements, time-resolved positron emission tomography, single-molecule spectroscopy, fluorescence correlation spectroscopy, diffuse optical tomography, optical time-domain reflectometry, quantum optics, etc.

  16. 10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements.

    Science.gov (United States)

    Markovic, B; Tamborini, D; Villa, F; Tisa, S; Tosi, A; Zappa, F

    2012-07-01

    We present a compact high performance time-to-digital converter (TDC) module that provides 10 ps timing resolution, 160 ns dynamic range and a differential non-linearity better than 1.5% LSB(rms). The TDC can be operated either as a general-purpose time-interval measurement device, when receiving external START and STOP pulses, or in photon-timing mode, when employing the on-chip SPAD (single photon avalanche diode) detector for detecting photons and time-tagging them. The instrument precision is 15 ps(rms) (i.e., 36 ps(FWHM)) and in photon timing mode it is still better than 70 ps(FWHM). The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via an user-friendly software interface. The module proves to be the best candidate for a wide variety of applications such as: fluorescence lifetime imaging, time-of-flight ranging measurements, time-resolved positron emission tomography, single-molecule spectroscopy, fluorescence correlation spectroscopy, diffuse optical tomography, optical time-domain reflectometry, quantum optics, etc. PMID:22852708

  17. 10 ps resolution, 160 ns full scale range and less than 1.5% differential non-linearity time-to-digital converter module for high performance timing measurements

    Energy Technology Data Exchange (ETDEWEB)

    Markovic, B.; Tamborini, D.; Villa, F.; Tisa, S.; Tosi, A.; Zappa, F. [Politecnico di Milano, Dipartimento di Elettronica e Informazione, Piazza Leonardo da Vinci 32, 20133 Milano (Italy)

    2012-07-15

    We present a compact high performance time-to-digital converter (TDC) module that provides 10 ps timing resolution, 160 ns dynamic range and a differential non-linearity better than 1.5% LSB{sub rms}. The TDC can be operated either as a general-purpose time-interval measurement device, when receiving external START and STOP pulses, or in photon-timing mode, when employing the on-chip SPAD (single photon avalanche diode) detector for detecting photons and time-tagging them. The instrument precision is 15 ps{sub rms} (i.e., 36 ps{sub FWHM}) and in photon timing mode it is still better than 70 ps{sub FWHM}. The USB link to the remote PC allows the easy setting of measurement parameters, the fast download of acquired data, and their visualization and storing via an user-friendly software interface. The module proves to be the best candidate for a wide variety of applications such as: fluorescence lifetime imaging, time-of-flight ranging measurements, time-resolved positron emission tomography, single-molecule spectroscopy, fluorescence correlation spectroscopy, diffuse optical tomography, optical time-domain reflectometry, quantum optics, etc.

  18. Greenland Snow Pit and Core Stratigraphy (Analog and Digital Formats)

    Data.gov (United States)

    National Oceanic and Atmospheric Administration, Department of Commerce — This data set is comprised of scientific field study notebooks from geologist Carl S. Benson describing his traverses of Greenland from 1952 to 1955. The notebooks...

  19. A hybrid analog-digital phase-locked loop for frequency mode non-contact scanning probe microscopy

    Science.gov (United States)

    Mehta, M. M.; Chandrasekhar, V.

    2014-01-01

    Non-contact scanning probe microscopy (SPM) has developed into a powerful technique to image many different properties of samples. The conventional method involves monitoring the amplitude, phase, or frequency of a cantilever oscillating at or near its resonant frequency as it is scanned across the surface of a sample. For high Q factor cantilevers, monitoring the resonant frequency is the preferred method in order to obtain reasonable scan times. This can be done by using a phase-locked-loop (PLL). PLLs can be obtained as commercial integrated circuits, but these do not have the frequency resolution required for SPM. To increase the resolution, all-digital PLLs requiring sophisticated digital signal processors or field programmable gate arrays have also been implemented. We describe here a hybrid analog/digital PLL where most of the components are implemented using discrete analog integrated circuits, but the frequency resolution is provided by a direct digital synthesis chip controlled by a simple peripheral interface controller (PIC) microcontroller. The PLL has excellent frequency resolution and noise, and can be controlled and read by a computer via a universal serial bus connection.

  20. An Implantable Mixed Analog/Digital Neural Stimulator Circuit

    DEFF Research Database (Denmark)

    Gudnason, Gunnar; Bruun, Erik; Haugland, Morten

    This paper describes a chip for a multichannel neural stimulator for functional electrical stimulation. The chip performs all the signal processing required in an implanted neural stimulator. The power and signal transmission to the stimulator is carried out via an inductive link. From the signals...

  1. 基于TDC芯片的LCR参数测量仪%LCR parameter testing instrument based on time-to-digital converter

    Institute of Scientific and Technical Information of China (English)

    李玲; 田书林; 戴志坚

    2012-01-01

    在采用矢量电流电压法测量阻抗时,目前大多采用两种方法来实现阻抗矢量虚实部的分离。一种是通过相敏检波器来实现,另一种是通过高速ADC采样信号,通过比较零点位置获取相位差信息来实现。前一种方法实现复杂且测量速度不易提高,后面的一种测量方法成本太高。本文主要介绍将TDC芯片应用于经典的电流电压法阻抗测量中,用TDC芯片获取被测信号的相位差信息,从而实现复阻抗实部与虚部分离的新方法,在降低成本的同时实现高精度LCR参数测量。%When using Current-Voltage method to measure the impedance,we often have two methods to depart it into real part and imaginary part.One is using phase detector,and the other is by finding and comparing the zerocrossing point of samples of ADC to obtain the phase information between the reference signal and measured signal.The former is complex and hard to get the quick testing speed,and the latter costs too much.So,we put forward a new method to obtain the phase information.In this article,TDC is applied to the classic Current-Voltage method to measure impedance,whose usage is for obtaining accurate phase information to separate the real part and imaginary part of complex impedance.The application of TDC chip in impedance measurement can achieve higher accuracy LCR parameters testing and reduce the cost at the same time.

  2. Neutron measurements on the MK 200N-1 type 2-dimensional delay line position sensitive detector with the new OTDCv1.1 time to digital converter

    International Nuclear Information System (INIS)

    Complete text of publication follows. Neutron tests of the MK 200N-1 two-dimensional delay line type position sensitive detector at the tree-axis spectrometer at the Budapest Research Reactor are described. The active area of this 3He multi-wire detector is 200 x 200 mm2 with 1 mm grid spacing. The new PC connected 4-channel TDC used in the measurement processes every hit and closes out any hazards of the measurements. Parameters as resolution, dead time, linearity and throughput have been measured. Physical measurements as point and line-shape neutron source images as well as powder diffraction patterns have been recorded to validate the tests. High over-all linearity, spatial and time resolution and throughput have been reached. The TDC's high-level and easy-to-handle user interface contains all necessary tools for a comfortable setup and the real time observation of measurements. (author)

  3. The charge pump PLL clock generator designed for the 1.56 ns bin size time-to-digital converter pixel array of the Timepix3 readout ASIC

    CERN Document Server

    Fu, Y et al.

    2014-01-01

    Timepix3 is a newly developed pixel readout chip which is expected to be operated in a wide range of gaseous and silicon detectors. It is made of 256×256 pixels organized in a square pixel-array with 55 µm pitch. Oscillators running at 640 MHz are distributed across the pixel-array and allow for a highly accurate measurement of the arrival time of a hit. This paper concentrates on a low-jitter phase locked loop (PLL) that is located in the chip periphery. This PLL provides a control voltage which regulates the actual frequency of the individual oscillators, allowing for compensation of process, voltage, and temperature variations.

  4. Data Converter for Multistandard Mobile Phones

    DEFF Research Database (Denmark)

    Yurttas, Aziz; Bruun, Erik; Jensen, Rasmus Glarborg

    2004-01-01

    This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideba...... entire ADC consumes about 5.5 mW and occupies an active area of about 0.36 mm(2). A test circuit has been developed and fabricated and measurements show that both the required programmability and the required performance can be obtained using the proposed configurations.......This paper describes an analog to digital converter (ADC) for mobile communication systems using a direct down conversion architecture. The ADC can be programmed to meet the requirements of different communication standards, including GSM (Global System for Mobile communication) and WCDMA (Wideband...

  5. CAMAC octal TDC (Time to Digital Converter)

    International Nuclear Information System (INIS)

    Eight channel CAMAC TDC with 50 pS resolution is designed and developed for GRACE project of NRL. The unit has conversion time of 108 μS with three time scale ranges of 100 nS, 200 nS, 500 nS with 11 bit resolution on each channel. The module approximately has DNL of 10% and INL of 2 counts. The module has individual start, common start, common stop inputs. The unit has in built calibration for start stop and reset function for ease of testing. These functions are available as CAMAC commands. The principle used is start-stop where a capacitor is charged with a high current and discharged with a small current giving time expansion. The duration of discharge time is counted by gating a synchronized clock. (author). 2 refs., 3 figs

  6. Converting Pirates Without Cannibalizing Purchasers: The Impact of Digital Distribution on Physical Sales and Internet Piracy

    OpenAIRE

    Brett Danaher; Samita Dhanasobhon; Michael D. Smith; Rahul Telang

    2010-01-01

    The availability of digital channels for media distribution has raised many important questions for marketers, notably, whether digital distribution channels will cannibalize physical sales and whether legitimate digital distribution channels will dissuade consumers from using (illegitimate) digital piracy channels. We address these two questions using the removal of NBC content from Apple's iTunes store in December 2007, and its restoration in September 2008, as natural shocks to the supply ...

  7. Digitally-assisted analog and RF CMOS circuit design for software-defined radio

    CERN Document Server

    Okada, Kenichi

    2011-01-01

    This book describes the state-of-the-art in RF, analog, and mixed-signal circuit design for Software Defined Radio (SDR). It synthesizes for analog/RF circuit designers the most important general design approaches to take advantage of the most recent CMOS technology, which can integrate millions of transistors, as well as several real examples from the most recent research results.

  8. Fabrication of a resin appliance with alloy components using digital technology without an analog impression.

    Science.gov (United States)

    Al Mortadi, Noor; Jones, Quentin; Eggbeer, Dominic; Lewis, Jeffrey; Williams, Robert J

    2015-11-01

    The aim of this study was to fabricate a resin appliance incorporating "wire" components without the use of an analog impression and dental casts using an intraoral scanner and computer technology to build the appliance. This unique alignment of technology offers an enormous reduction in the number of fabrication steps when compared with more traditional methods of manufacture. The prototype incorporated 2 Adams clasps and a fitted labial bow. The alloy components were built from cobalt-chromium in an initial powdered form using established digital technology methods and then inserted into a build of a resin base plate. This article reports the first known use of computer-aided design and additive manufacture to fabricate a resin and alloy appliance, and constitutes proof of the concept for such manufacturing. The original workflow described could be seen as an example for many other similar appliances, perhaps with active components. The scan data were imported into an appropriate specialized computer-aided design software, which was used in conjunction with a force feedback (haptic) interface. The appliance designs were then exported as stereolithography files and transferred to an additive manufacturing machine for fabrication. The results showed that the applied techniques may provide new manufacturing and design opportunities in orthodontics and highlights the need for intraoral-specific additive manufacture materials to be produced and tested for biocompatibility compliance. In a trial, the retainer was fitted orally and judged acceptable by the clinician according to the typical criteria when placing such appliances in situ. PMID:26522047

  9. eeDAP: an evaluation environment for digital and analog pathology

    Science.gov (United States)

    Gallas, Brandon D.; Cheng, Wei-Chung; Gavrielides, Marios A.; Ivansky, Adam; Keay, Tyler; Wunderlich, Adam; Hipp, Jason; Hewitt, Stephen M.

    2014-03-01

    Purpose: The purpose of this work is to present a platform for designing and executing studies that compare pathologists interpreting histopathology of whole slide images (WSI) on a computer display to pathologists interpreting glass slides on an optical microscope. Methods: Here we present eeDAP, an evaluation environment for digital and analog pathology. The key element in eeDAP is the registration of theWSI to the glass slide. Registration is accomplished through computer control of the microscope stage and a camera mounted on the microscope that acquires images of the real time microscope view. Registration allows for the evaluation of the same regions of interest (ROIs) in both domains. This can reduce or eliminate disagreements that arise from pathologists interpreting different areas and focuses the comparison on image quality. Results: We reduced the pathologist interpretation area from an entire glass slide (≈10-30 mm)2 to small ROIs google.com (project: eeDAP) as Matlab source or as a precompiled stand-alone license-free application.

  10. Evaluation environment for digital and analog pathology: a platform for validation studies.

    Science.gov (United States)

    Gallas, Brandon D; Gavrielides, Marios A; Conway, Catherine M; Ivansky, Adam; Keay, Tyler C; Cheng, Wei-Chung; Hipp, Jason; Hewitt, Stephen M

    2014-10-01

    We present a platform for designing and executing studies that compare pathologists interpreting histopathology of whole slide images (WSIs) on a computer display to pathologists interpreting glass slides on an optical microscope. eeDAP is an evaluation environment for digital and analog pathology. The key element in eeDAP is the registration of the WSI to the glass slide. Registration is accomplished through computer control of the microscope stage and a camera mounted on the microscope that acquires real-time images of the microscope field of view (FOV). Registration allows for the evaluation of the same regions of interest (ROIs) in both domains. This can reduce or eliminate disagreements that arise from pathologists interpreting different areas and focuses on the comparison of image quality. We reduced the pathologist interpretation area from an entire glass slide (10 to [Formula: see text]) to small ROIs ([Formula: see text]). We also made possible the evaluation of individual cells. We summarize eeDAP's software and hardware and provide calculations and corresponding images of the microscope FOV and the ROIs extracted from the WSIs. The eeDAP software can be downloaded from the Google code website (project: eeDAP) as a MATLAB source or as a precompiled stand-alone license-free application. PMID:26158076

  11. Electromagnetic compatibility of new installations of digital/analog and electrical/electronic equipment in nuclear power plants

    International Nuclear Information System (INIS)

    This paper recommends electromagnetic compatibility (EMC) requirements of new digital/analog and electrical/electronic equipment installations in nuclear power plant areas including control rooms, remote shutdown panels, cable spreading rooms, equipment/relay rooms and the turbine deck. A nuclear plant electromagnetic environment (EME) consists of electromagnetic noises from portable two-way radios, arc welders, etc; and high-energy fast transients from generator and transmission / distribution voltages. Trends in current plant modifications suggest that Instrumentation and Control (I and C) systems with analog equipment are being replaced with more efficient computerized/microprocessor-based digital systems. As digital systems are evolving with higher clock frequencies and lower logic level voltages, digital equipment are more vulnerable to electromagnetic/radio frequency interference (EMI/RFI) random noise causing errors in their logic functions. US NRC Regulatory Guide (RG) 1.180, providing guidelines for evaluating EMI/RFI in safety-related I and C systems, endorsed EPRI guidelines TR-102323-RI for EMI emission/susceptibility testing and limiting practices as an acceptable qualification method of digital equipment EMC. Numerous US nuclear utilities have used these EPRI requirements in their equipment specifications. The basis for this paper is derived from these guidelines, military/industry standards, federal regulations and various international publications on EMC. Plant emission levels are selected 8dB below digital equipment susceptibility testing levels and the equipment emissions are conservatively limited to 22dB or more below these levels depending on frequency. Digital equipment is also required to satisfy the EMI limiting practices of EPRI TR-102323-R1 and IEEE 1050-1996. On the other hand, electrical/electronic equipment that operates at higher voltages at power frequency is not as vulnerable to the plant EMI as digital equipment, but could

  12. A 6 device SOI new technology for mixed analog-digital and rad-hard applications

    International Nuclear Information System (INIS)

    DMILL technology is being developed for very rad-hard analog-digital applications, such as space and military circuits or as electronics for the future generation of high energy collider (LHC, CERN, Geneva). Both CMOS and junction (JFET and bipolar) transistors are needed. A new process has been integrated, based on a 1.2μm thick silicon film on insulator (SIMOX plus epitaxy), a complete dielectric isolation and low temperature process. The mean feature is that six different components are fabricated on the same wafer, taking into account the 12 volts supply voltage constraint for some analog applications. The first electrical characteristics are presented in this paper. The optimization capabilities of such a hardened CBi-CJ-CMOS technology are discussed

  13. Converting from ECCE to SICS

    Directory of Open Access Journals (Sweden)

    Nick Astbury

    2009-03-01

    Full Text Available Cataract continues to be the cause of almost half the cases of blindness worldwide and the challenge to meet the needs and develop the required resources is as great as ever.Cataract surgery has evolved from couching, first practised several thousand years ago, through intra- and extracapsular extraction (ECCE, to phacoemulsification. However, whatever the technique, the most important aspect is the outcome for patients. Today, the focus is more and more on excellence, which was one of the central themes of the 8th General Assembly.

  14. BPSK Demodulation Using Digital Signal Processing

    Science.gov (United States)

    Garcia, Thomas R.

    1996-01-01

    A digital communications signal is a sinusoidal waveform that is modified by a binary (digital) information signal. The sinusoidal waveform is called the carrier. The carrier may be modified in amplitude, frequency, phase, or a combination of these. In this project a binary phase shift keyed (BPSK) signal is the communication signal. In a BPSK signal the phase of the carrier is set to one of two states, 180 degrees apart, by a binary (i.e., 1 or 0) information signal. A digital signal is a sampled version of a "real world" time continuous signal. The digital signal is generated by sampling the continuous signal at discrete points in time. The rate at which the signal is sampled is called the sampling rate (f(s)). The device that performs this operation is called an analog-to-digital (A/D) converter or a digitizer. The digital signal is composed of the sequence of individual values of the sampled BPSK signal. Digital signal processing (DSP) is the modification of the digital signal by mathematical operations. A device that performs this processing is called a digital signal processor. After processing, the digital signal may then be converted back to an analog signal using a digital-to-analog (D/A) converter. The goal of this project is to develop a system that will recover the digital information from a BPSK signal using DSP techniques. The project is broken down into the following steps: (1) Development of the algorithms required to demodulate the BPSK signal; (2) Simulation of the system; and (3) Implementation a BPSK receiver using digital signal processing hardware.

  15. Analog and hybrid computing

    CERN Document Server

    Hyndman, D E

    2013-01-01

    Analog and Hybrid Computing focuses on the operations of analog and hybrid computers. The book first outlines the history of computing devices that influenced the creation of analog and digital computers. The types of problems to be solved on computers, computing systems, and digital computers are discussed. The text looks at the theory and operation of electronic analog computers, including linear and non-linear computing units and use of analog computers as operational amplifiers. The monograph examines the preparation of problems to be deciphered on computers. Flow diagrams, methods of ampl

  16. An Economic analogy to Electrodynamics

    OpenAIRE

    Sanjay Dasari; Anindya Kumar Biswas

    2010-01-01

    In this note, we would like to find the laws of electrodynamics in simple economic systems. In this direction, we identify the chief economic variables and parameters, scalar and vector, which are amenable to be put directly into the crouch of the laws of electrodynamics, namely Maxwell's equations. Moreover, we obtain Phillp's curve, recession and Black-Scholes formula, as sample applications.

  17. Advances in Analog Circuit Design 2015

    CERN Document Server

    Baschirotto, Andrea; Harpe, Pieter

    2016-01-01

    This book is based on the 18 tutorials presented during the 24th workshop on Advances in Analog Circuit Design. Expert designers present readers with information about a variety of topics at the frontier of analog circuit design, including low-power and energy-efficient analog electronics, with specific contributions focusing on the design of efficient sensor interfaces and low-power RF systems. This book serves as a valuable reference to the state-of-the-art, for anyone involved in analog circuit research and development. ·         Provides a state-of-the-art reference in analog circuit design, written by experts from industry and academia; ·         Presents material in a tutorial-based format; ·         Includes coverage of high-performance analog-to-digital and digital to analog converters, integrated circuit design in scaled technologies, and time-domain signal processing.

  18. On the comparison of analog and digital SiPM readout in terms of expected timing performance

    Energy Technology Data Exchange (ETDEWEB)

    Gundacker, S., E-mail: stefan.gundacker@cern.ch; Auffray, E.; Jarron, P.; Meyer, T.; Lecoq, P.

    2015-07-01

    In time of flight positron emission tomography (TOF-PET) and in particular for the EndoTOFPET-US Project (Frisch, 2013 [1]), and other applications for high energy physics, the multi-digital silicon photomultiplier (MD-SiPM) was recently proposed (Mandai and Charbon, 2012 [2]), in which the time of every single photoelectron is being recorded. If such a photodetector is coupled to a scintillator, the largest and most accurate timing information can be extracted from the cascade of the scintillation photons, and the most probable time of positron emission determined. The readout concept of the MD-SiPM is very different from that of the analog SiPM, where the individual photoelectrons are merely summed up and the output signal fed into the readout electronics. We have developed a comprehensive Monte Carlo (MC) simulation tool that describes the timing properties of the photodetector and electronics, the scintillation properties of the crystal and the light transfer within the crystal. In previous studies we have compared MC simulations with coincidence time resolution (CTR) measurements and found good agreement within less than 10% for crystals of different lengths (from 3 mm to 20 mm) coupled to SiPMs from Hamamatsu. In this work we will use the developed MC tool to directly compare the highest possible time resolution for both the analog and digital readout of SiPMs with different scintillator lengths. The presented studies reveal that the analog readout of SiPMs with microcell signal pile-up and leading edge discrimination can lead to nearly the same time resolution as compared to the maximum likelihood time estimation applied to MD-SiPMs. Consequently there is no real preference for either a digital or analog SiPM for the sake of achieving highest time resolution. However, the best CTR in the analog SiPM is observed for a rather small range of optimal threshold values, whereas the MD-SiPM provides stable CTR after roughly 20 registered photoelectron timestamps in

  19. A dual-mode analog baseband with digital-assisted DC-offset calibration for WCDMA/GSM receivers

    International Nuclear Information System (INIS)

    A dual-mode analog baseband with digital-assisted DC-offset calibration (DCOC) for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC-offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13 μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm2. (semiconductor integrated circuits)

  20. Integration of analog and digital instrumentation and control systems in hybrid control rooms

    International Nuclear Information System (INIS)

    he IAEA's activities in the area of nuclear power plant operating performance and life cycle management are aimed at increasing Member State capabilities in utilizing good engineering and management practices as developed and transferred by the IAEA. In particular, the IAEA supports the improvement of nuclear power plant performance, plant life management, training, power uprating, operational license renewal, and the modernization of instrumentation and control (I and C) systems of plants. The issue of the integration of analog and digital I and C systems in hybrid control rooms was suggested by the IAEA Technical Working Group on Nuclear Power Plant Control and Instrumentation (TWG-NPPCI) at its meetings in 2003 and 2005. The subject was then approved by the IAEA and included in its work programmes for 2006-2009. The purpose of this report is to help nuclear utilities in planning control room and other human system interface (HSI) changes, making appropriate use of modern technologies. These technologies would aid in managing ageing and obsolescence, and facilitate improvements in plant performance and safety. This report covers a broad spectrum of potential changes to the control room ranging from the replacement of a few obsolete components with newer digital devices to a fully computerized control room. New digital technologies offer significant opportunities to improve access to and presentation of information to the user, e.g. operators, maintenance staff and management. However, this technology should be used prudently. In some cases, modernization is undertaken to resolve ageing and obsolescence or to meet regulatory requirements for license renewal. The integration of new technologies during main control room (MCR) modernizations should be performed cautiously and all affected aspects of plant maintenance, and operation should be carefully considered, paying particular attention to the human factors elements of these aspects. This report describes a