Status report on front end electronics for the EUSO photon detector

Energy Technology Data Exchange (ETDEWEB)

Bosson, G.; Dzahini, D.; Koang, D.H.; Musico, P.; Pallavicini, M.; Pouxe, J.; Pratolongo, F.; Richer, J.P

2002-12-01

In this paper we'll give a status report on the design of the front end electronic system which will be used for the EUSO photon detector. For space, mass and power consumption constraints the system will be implemented developing an ASIC chip using a deep submicron technology. Two complementary approaches will be described: a digital one (DFEE) and an analog one (AFEE). The DFEE is able to count the single photoelectrons coming form the detector, store the numbers in a memory buffer and read them out after a trigger using a serial communication line. The AFEE integrate the anode signals, store them in an analog memory and serially send all the values to a single output after a trigger for digitalisation (external to the chip). Since the approaches are complementary the idea is to put both of them in the final front end chip. An overview of the system is given together to the actual status of the design. Results from simulations are shown: the system is feasible and we think to implement some devices this year to extensively test the proposed solutions.

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Hofsajer, I; Govender, M; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is the portable test-bench for the full certification of the front-end electronics of the ATLAS Tile calorimeter designed for the upgrade phase-II. It is a high throughput electronics system designed to simultaneously read-out all the samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read-out and control the front-end boards. The rest of the functionalities of the system are provided by a HV mezzanine board that to turn on the gain of the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog output of the front-end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

Analog electronics for radiation detection

CERN Document Server

2016-01-01

Analog Electronics for Radiation Detection showcases the latest advances in readout electronics for particle, or radiation, detectors. Featuring chapters written by international experts in their respective fields, this authoritative text: Defines the main design parameters of front-end circuitry developed in microelectronics technologies Explains the basis for the use of complementary metal oxide semiconductor (CMOS) image sensors for the detection of charged particles and other non-consumer applications Delivers an in-depth review of analog-to-digital converters (ADCs), evaluating the pros and cons of ADCs integrated at the pixel, column, and per-chip levels Describes incremental sigma delta ADCs, time-to-digital converter (TDC) architectures, and digital pulse-processing techniques complementary to analog processing Examines the fundamental parameters and front-end types associated with silicon photomultipliers used for single visible-light photon detection Discusses pixel sensors ...

Optimizing read-out of the NECTAr front-end electronics

Energy Technology Data Exchange (ETDEWEB)

Vorobiov, S., E-mail: vorobiov@lpta.in2p3.fr [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); DESY-Zeuthen, Platanenallee 6, 15738 Zeuthen (Germany); Feinstein, F. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Falvard, A. [LUPM, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France); Ribo, M.; Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Tavernet, J.-P.; Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and Universite Paris VII and IN2P3/CNRS, Paris (France)

2012-12-11

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Optimizing read-out of the NECTAr front-end electronics

International Nuclear Information System (INIS)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C.L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-01-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Optimizing read-out of the NECTAr front-end electronics

Science.gov (United States)

Vorobiov, S.; Feinstein, F.; Bolmont, J.; Corona, P.; Delagnes, E.; Falvard, A.; Gascón, D.; Glicenstein, J.-F.; Naumann, C. L.; Nayman, P.; Ribo, M.; Sanuy, A.; Tavernet, J.-P.; Toussenel, F.; Vincent, P.

2012-12-01

We describe the optimization of the read-out specifications of the NECTAr front-end electronics for the Cherenkov Telescope Array (CTA). The NECTAr project aims at building and testing a demonstrator module of a new front-end electronics design, which takes an advantage of the know-how acquired while building the cameras of the CAT, H.E.S.S.-I and H.E.S.S.-II experiments. The goal of the optimization work is to define the specifications of the digitizing electronics of a CTA camera, in particular integration time window, sampling rate, analog bandwidth using physics simulations. We employed for this work real photomultiplier pulses, sampled at 100 ps with a 600 MHz bandwidth oscilloscope. The individual pulses are drawn randomly at the times at which the photo-electrons, originating from atmospheric showers, arrive at the focal planes of imaging atmospheric Cherenkov telescopes. The timing information is extracted from the existing CTA simulations on the GRID and organized in a local database, together with all the relevant physical parameters (energy, primary particle type, zenith angle, distance from the shower axis, pixel offset from the optical axis, night-sky background level, etc.), and detector configurations (telescope types, camera/mirror configurations, etc.). While investigating the parameter space, an optimal pixel charge integration time window, which minimizes relative error in the measured charge, has been determined. This will allow to gain in sensitivity and to lower the energy threshold of CTA telescopes. We present results of our optimizations and first measurements obtained using the NECTAr demonstrator module.

Front-end electronics for the ALICE calorimeters

CERN Document Server

Wang, Ya-Ping; Muller, Hans; Cai, Xu; Zhou, Daicui; Yin, Zhong-Bao; Awes, Terry C.; Wang, Dong

2010-01-01

The ALICE calorimeters PHOS and EMCal are based on Avalanche Photo-Diode (APD) photosensors with Charge Sensitive Preamplifiers (CSP) for readout of the scintillating elements. The amplified signals are read out via 32-channel shaper/digitizer front-end electronics (FEE) with 14-bit effective dynamic range. The electronics is based on second order shapers with dual gain for each channel, getting digitized by ALTRO chips. Each APD channel is equipped with an individual 10-bit APD gain adjustment and 2×2 channel clusters generate a 100 ns shaped analog sums output (Fast OR) for the associated Trigger Region Units (TRU). The Fast OR signals are generated by first order shapers with a dynamic range of 12-bit given by the ADC in the TRU cards. Board controller firmware in the FPGA provides local monitoring and configuration of all parameters via the ALICE DCS system. The signal to noise ratio for MIP at 215 MeV is not, vert, similar7 per channel with a noise level of 30 MeV at room temperature for a dynamic range...

Performance of the front-end signal processing electronics for the drift chambers of the Stanford Large Detector

International Nuclear Information System (INIS)

Honma, A.; Haller, G.M.; Usher, T.; Shypit, R.

1990-10-01

This paper reports on the performance of the front-end analog and digital signal processing electronics for the drift chambers of the Stanford Large Detector (SLD) detector at the Stanford Linear Collider. The electronics mounted on printed circuit boards include up to 64 channels of transimpedance amplification, analog sampling, A/D conversion, and associated control circuitry. Measurements of the time resolution, gain, noise, linearity, crosstalk, and stability of the readout electronics are described and presented. The expected contribution of the electronics to the relevant drift chamber measurement resolutions (i.e., timing and charge division) is given

A CMOS analog front-end chip for amperometric electrochemical sensors

International Nuclear Information System (INIS)

Li Zhichao; Chen Min; Xiao Jingbo; Chen Jie; Liu Yuntao

2015-01-01

This paper reports a complimentary metal–oxide–semiconductor (CMOS) analog front-end chip for amperometric electrochemical sensors. The chip includes a digital configuration circuit, which can communicate with an external microcontroller by employing an I 2 C interface bus, and thus is highly programmable. Digital correlative double samples technique and an incremental sigma–delta analog to digital converter (Σ–Δ ADC) are employed to achieve a new proposed system architecture with double samples. The chip has been fabricated in a standard 0.18-μm CMOS process with high-precision and high-linearity performance occupying an area of 1.3 × 1.9 mm 2 . Sample solutions with various phosphate concentrations have been detected with a step concentration of 0.01 mg/L. (paper)

An ASIC implementation of digital front-end electronics for a high resolution PET scanner

International Nuclear Information System (INIS)

Newport, D.F.; Young, J.W.

1993-01-01

AN Application Specific Integrated Circuit (ASIC) has been designed and fabricated which implements many of the current functions found in the digital front-end electronics for a high resolution Positron Emission Tomography (PET) scanner. The ASIC performs crystal selection, energy qualification, time correction, and event counting functions for block technology high resolution PET scanners. Digitized x and y position, event energy, and time information are used by the ASIC to determine block crystal number, qualify the event based on energy, and correct the event time. In addition, event counting and block dead time calculations are performed for system dead time corrections. A loadable sequencer for controlling the analog front-end electronics is also implemented. The ASIC is implemented in a 37,000 gate, 1.0 micron CMOS gate-array and is capable of handling 4 million events/second while reducing parts count, cost, and power consumption over current board-level designs

Development of a dedicated front-end electronics for straw tube trackers in the bar PANDA experiment

Science.gov (United States)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.; Swientek, K.; Terlecki, P.; Tokarz, J.

2016-08-01

The design and tests of front-end electronics for straw tube trackers in the bar PANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25-67 ns), gain, noise (ENC 800-2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

Pixel front-end development in 65 nm CMOS technology

International Nuclear Information System (INIS)

Havránek, M; Hemperek, T; Kishishita, T; Krüger, H; Wermes, N

2014-01-01

Luminosity upgrade of the LHC (HL-LHC) imposes severe constraints on the detector tracking systems in terms of radiation hardness and capability to cope with higher hit rates. One possible way of keeping track with increasing luminosity is the usage of more advanced technologies. Ultra deep sub-micron CMOS technologies allow a design of complex and high speed electronics with high integration density. In addition, these technologies are inherently radiation hard. We present a prototype of analog pixel front-end integrated circuit designed in 65 nm CMOS technology with applications oriented towards the ATLAS Pixel Detector upgrade. The aspects of ultra deep sub-micron design and performance of the analog pixel front-end circuits will be discussed

Prometeo: A portable test-bench for the upgraded front-end electronics of the ATLAS Tile calorimeter

CERN Document Server

Bullock, D; The ATLAS collaboration; Govender, M; Hofsajer, I; Mellado, B; Moreno, P; Reed, R; Ruan, X; Sandrock, C; Solans, C; Suter, R; Usai, G; Valero, A

2014-01-01

Prometeo is a portable test-bench for full certification of the front-end electronics of the ATLAS Tile calorimeter, designed for the upgrade phase-II. It is a high-throughput electronic system designed to simultaneously read out all the digitized samples from 12 channels at the LHC bunch crossing frequency and assess the quality of the data in real-time. The core of the system is a Xilinx Virtex 7 evaluation board extended with a dual QSFP FMC module to read out and control the on-detector electronics. The rest of the functionalities of the system are provided by a HV mezzanine board that supplied the HV to the photo-multipliers, an LED board that sends light to illuminate them, and a 12 channel ADC board that samples the analog trigger output of the front- end. The system is connected by ethernet to a GUI client from which QA tests are performed on the electronics such as noise measurements and linearity response to an injected charge.

The ALICE TPC front end electronics

CERN Document Server

Musa, L; Bialas, N; Bramm, R; Campagnolo, R; Engster, Claude; Formenti, F; Bonnes, U; Esteve-Bosch, R; Frankenfeld, Ulrich; Glässel, P; Gonzales, C; Gustafsson, Hans Åke; Jiménez, A; Junique, A; Lien, J; Lindenstruth, V; Mota, B; Braun-Munzinger, P; Oeschler, H; Österman, L; Renfordt, R E; Ruschmann, G; Röhrich, D; Schmidt, H R; Stachel, J; Soltveit, A K; Ullaland, K

2004-01-01

In this paper we present the front end electronics for the time projection chamber (TPC) of the ALICE experiment. The system, which consists of about 570000 channels, is based on two basic units: (a) an analogue ASIC (PASA) that incorporates the shaping-amplifier circuits for 16 channels; (b) a mixed-signal ASIC (ALTRO) that integrates 16 channels, each consisting of a 10-bit 25-MSPS ADC, the baseline subtraction, tail cancellation filter, zero suppression and multi-event buffer. The complete readout chain is contained in front end cards (FEC), with 128 channels each, connected to the detector by means of capton cables. A number of FECs (up to 25) are controlled by a readout control unit (RCU), which interfaces the FECs to the data acquisition (DAQ), the trigger, and the detector control system (DCS) . A function of the final electronics (1024 channels) has been characterized in a test that incorporates a prototype of the ALICE TPC as well as many other components of the final set-up. The tests show that the ...

Development of a dedicated front-end electronics for straw tube trackers in the P-bar ANDA experiment

International Nuclear Information System (INIS)

Przyborowski, D.; Fiutowski, T.; Idzik, M.; Swientek, K.; Terlecki, P.; Tokarz, J.; Kajetanowicz, M.; Korcyl, G.; Salabura, P.; Smyrski, J.; Strzempek, P.

2016-01-01

The design and tests of front-end electronics for straw tube trackers in the P-bar ANDA experiment at FAIR are presented. The challenges for the front-end electronics, comprising operation at high counting rate up to 1 MHz per straw tube, are discussed and the proposed architecture comprising a switched gain charge sensitive preamplifier (CSP), a pole-zero cancellation circuit (PZC), a second order variable peaking time shaper, a trimming ion tail cancellation circuit, and a baseline holder (BLH), is described. The front-end provides an analogue output and a discriminator with LVDS differential driver for the Time-of-Arrival (ToA) and Time-over-Threshold (ToT) measurements. A prototype readout ASIC featuring four channels was fabricated in 0.35 μm CMOS technology consuming 15.5 mW (analog part) and 12 mW (LVDS) per channel. The results of measurements of peaking time (25–67 ns), gain, noise (ENC 800–2500 el. for various gains), time walk and jitter are presented as well as the first results obtained with prototype straw tubes connected.

Front-end electronics for the Muon Portal project

Energy Technology Data Exchange (ETDEWEB)

Garozzo, S.; Marano, D.; Bonanno, G.; Grillo, A.; Romeo, G.; Timpanaro, M.C. [INAF, Osservatorio Astrofisico di Catania, Via S. Sofia 78, I-95123 Catania (Italy); Lo Presti, D.; Riggi, F.; Russo, V.; Bonanno, D.; La Rocca, P.; Longhitano, F.; Bongiovanni, D.G. [Università di Catania, Dipartimento di Fisica e Astronomia, and INFN, Sezione di Catania, Via S. Sofia 64, I-95123 Catania (Italy); Fallica, G.; Valvo, G. [ST-Microelectronics, Stradale V Primosole 50, Catania (Italy)

2016-10-11

The Muon Portal Project was born as a joint initiative between Italian research and industrial partners, aimed at the construction of a real-size working detector prototype to inspect the content of traveling containers by means of secondary cosmic-ray muon radiation and recognize potentially dangerous hidden materials. The tomographic image is obtained by reconstructing the incoming and outgoing muon trajectories when crossing the inspected volume, employing two tracker planes located above and below the container under inspection. In this paper, the design and development of the front-end electronics of the Muon Portal detector is presented, with particular emphasis being devoted to the photo-sensor devices detecting the scintillation light and to the read-out circuitry which is in charge of processing and digitizing the analog pulse signals. In addition, the remote control system, mechanical housing, and thermal cooling system of all structural blocks of the Muon Portal tracker are also discussed, demonstrating the effectiveness and functionality of the adopted design.

Front-end electronics for multichannel semiconductor detector systems

CERN Document Server

Grybos, P

2010-01-01

Front-end electronics for multichannel semiconductor detektor systems Volume 08, EuCARD Editorial Series on Accelerator Science and Technology The monograph is devoted to many different aspects related to front-end electronics for semiconductor detector systems, namely: − designing and testing silicon position sensitive detectors for HEP experiments and X-ray imaging applications, − designing and testing of multichannel readout electronics for semiconductor detectors used in X-ray imaging applications, especially for noise minimization, fast signal processing, crosstalk reduction and good matching performance, − optimization of semiconductor detection systems in respect to the effects of radiation damage. The monograph is the result mainly of the author's experience in the above-mentioned areas and it is an attempt of a comprehensive presentation of issues related to the position sensitive detection system working in a single photon counting mode and intended to X-ray imaging applications. The structure...

Fast front-end electronics for semiconductor tracking detectors: Trends and perspectives

Energy Technology Data Exchange (ETDEWEB)

Rivetti, Angelo

2014-11-21

In the past few years, extensive research efforts pursued by both the industry and the academia have lead to major improvements in the performance of Analog to Digital Converters (ADCs) and Time to Digital Converters (TDCs). ADCs achieving 8–10 bit resolution, 50–100 MHz conversion frequency and less than 1 mW power consumption are the today's standard, while TDCs have reached sub-picosecond time resolution. These results have been made possible by architectural upgrades combined with the use of ultra deep submicron CMOS technologies with minimum feature size of 130 nm or smaller. Front-end ASICs in which a prompt digitization is followed by signal conditioning in the digital domain can now be envisaged also within the tight power budget typically available in high density tracking systems. Furthermore, tracking detectors embedding high resolution timing capabilities are gaining interest. In the paper, ADC's and TDC's developments which are of particular relevance for the design front-end electronics for semiconductor trackers are discussed along with the benefits and challenges of exploiting such high performance building blocks in implementing the next generation of ASICs for high granularity particle detectors.

Solid-State Photomultiplier with Integrated Front End Electronics

Science.gov (United States)

Christian, James; Stapels, Christopher; Johnson, Erik; Mukhopadhyay, Sharmistha; Jie Chen, Xiao; Miskimen, Rory

2009-10-01

The instrumentation cost of physics experiments has been reduced per channel, by the use of solid-state detectors, but these cost-effective techniques have not been translated to scintillation-based detectors. When considering photodetectors, the cost per channel is determined by the use of high-voltage, analog-to-digital converters, BNC cables, and any other ancillary devices. The overhead associated with device operation limits the number of channels for the detector system, while potentially limiting the scope of physics that can be explored. The PRIMEX experiment at JLab, which is being designed to measure the radiative widths of the η and η' pseudo-scalar mesons for a more comprehensive understanding of QCD at low energies, is an example where CMOS solid-state photomultipliers (SSPMs) can be implemented. The ubiquitous nature of CMOS allows for on-chip signal processing to provide front-end electronics within the detector package. We present the results of the device development for the PRIMEX calorimeter, discussing the characteristics of SSPMs, the potential cost savings, and experimental results of on-chip signal processing.

Pseudo-differential CMOS analog front-end circuit for wide-bandwidth optical probe current sensor

Science.gov (United States)

Uekura, Takaharu; Oyanagi, Kousuke; Sonehara, Makoto; Sato, Toshiro; Miyaji, Kousuke

2018-04-01

In this paper, we present a pseudo-differential analog front-end (AFE) circuit for a novel optical probe current sensor (OPCS) aimed for high-frequency power electronics. It employs a regulated cascode transimpedance amplifier (RGC-TIA) to achieve a high gain and a large bandwidth without using an extremely high performance operational amplifier. The AFE circuit is designed in a 0.18 µm standard CMOS technology achieving a high transimpedance gain of 120 dB Ω and high cut off frequency of 16 MHz. The measured slew rate is 70 V/µs and the input referred current noise is 1.02 pA/\\sqrt{\\text{Hz}} . The magnetic resolution and bandwidth of OPCS are estimated to be 1.29 mTrms and 16 MHz, respectively; the bandwidth is higher than that of the reported Hall effect current sensor.

Analog Front-End Electronics in Beam Instrumentation

CERN Document Server

Boscolo, A

2005-01-01

The work gives an overview of present and near future technological opportunities for the first analog conditioning and subsequent signal processing of sensor signal. The interactions between beam sensor capability, their signals characteristics and the system requirements are analyzed from different approaches as: full analog continuous, sampled time discrete, full digital time and amplitude discrete. Special attention will be given to the impact of measurement methods and new devices in circuits and instrumentation architecture design, especially from the metrological point of view. A lot of measurement methods and related systems have been developed in order to overcome technological drawbacks and to reach the best cost-performances ratio. By a system revamping, some of these still now show the capability of reaching the actual technological limits in a simpler way in many applications as: ADC, linear and non linear signal processing, ultra high speed logic, etc. These methods could be carried out by the n...

Front-end electronics for accurate energy measurement of double beta decays

International Nuclear Information System (INIS)

Gil, A.; Díaz, J.; Gómez-Cadenas, J.J.; Herrero, V.; Rodriguez, J.; Serra, L.; Toledo, J.; Esteve, R.; Monzó, J.M.; Monrabal, F.; Yahlali, N.

2012-01-01

NEXT, a double beta decay experiment that will operate in Canfranc Underground Laboratory (Spain), aims at measuring the neutrinoless double-β decay of the 136Xe isotope using a TPC filled with enriched Xenon gas at high pressure operated in electroluminescence mode. One technological challenge of the experiment is to achieve resolution better than 1% in the energy measurement using a plane of UV sensitive photomultipliers readout with appropriate custom-made front-end electronics. The front-end is designed to be sensitive to the single photo-electron to detect the weak primary scintillation light produced in the chamber, and also to be able to cope with the electroluminescence signal (several hundred times higher and with a duration of microseconds). For efficient primary scintillation detection and precise energy measurement of the electroluminescent signals the front-end electronics features low noise and adequate amplification. The signal shaping provided allows the digitization of the signals at a frequency as low as 40 MHz.

Front-end electronics for the CMS preshower detector

CERN Document Server

Go, A; Barney, D; Bloch, P; Peisert, Anna; Löfstedt, B; Reynaud, S; Borkar, S; Lalwani, S

2002-01-01

The front-end readout system PACE2 for the CMS preshower detector consists of two chips: Delta is a 32 channel preamplifier and shaper that provides low noise, charge to voltage readout for large capacitive silicon sensors over a large dynamic range (up to 400 MIPs); PACE-AM contains a 32-channel wide, 160-cell deep, analog memory with a 32 to 1 multiplexer for serial readout. These chips are designed in .8 mu m BiCMOS DMILL radiation tolerant technology. The performance in terms of dynamic range, linearity, noise, peaking time and memory uniformity are presented. (4 refs).

Analog front-end cell designed in a commercial 025 mu m process for the ATLAS pixel detector at LHC

CERN Document Server

Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Mandelli, E; Meddeler, G; Peric, I; Richardson, J

2002-01-01

A new analog pixel front-end cell has been developed for the ATLAS detector at the future Large Hadron Collider (LHC) at the European Laboratory for Particle Physics (CERN). This analog cell has been submitted in two commercial 0.25 mu m CMOS processes (in an analog test chip format), using special layout techniques for radiation hardness purposes. It is composed of two cascaded amplifiers followed by a fast discriminator featuring a detection threshold within the range of 1000 to 10000 electrons. The first preamplifier has the principal role of providing a large bandwidth, low input impedance, and fast rise time in order to enhance the time-walk and crosstalk performance, whereas the second fully differential amplifier is aimed at delivering a sufficiently high-voltage gain for optimum comparison. A new do feedback concept renders the cell tolerant of sensor leakage current up to 300 nA and provides monitoring of this current. Two 5-bit digital-to-analog converters tolerant to single- event upset have been i...

Analog front-end for pixel sensors in a 3D CMOS technology for the SuperB Layer0

International Nuclear Information System (INIS)

Manazza, A.; Gaioni, L.; Re, V.

2011-01-01

This work is concerned with the design of two different analog channels for hybrid and monolithic pixels readout in view of applications to the SVT at the SuperB Factory. The circuits have been designed in a 130nm CMOS, vertically integrated technology, which, among others, may provide some advantages in terms of functional density and electrical isolation between the analog and the digital sections of the front-end.

Front-end electronics and readout system for the ILD TPC

CERN Document Server

Hedberg, V; Lundberg, B; Mjörnmark, U; Oskarsson, A; Österman, L; De Lentdecker, G; Yang, Y; Zhang, F

2015-01-01

A high resolution TPC is the main option for a central tracking detector at the future International Linear Collider (ILC). It is planned that the MPGD (Micro Pattern Gas Detector) technology will be used for the readout. A Large Prototype TPC at DESY has been used to test the performance of MPGDs in an electron beam of energies up to 6 GeV. The first step in the technology development was to demonstrate that the MPGDs are able to achieve the necessary performance set by the goals of ILC. For this ’proof of principle’ phase, the ALTRO front-end electronics from the ALICE TPC was used, modified to adapt to MPGD readout. The proof of principle has been verified and at present further improvement of the MPGD technology is going on, using the same readout electronics. The next step is the ’feasibility phase’, which aims at producing front-end electronics comparable in size (few mm2) to the readout pads of the TPC. This development work is based on the succeeding SALTRO16 chip, which combines the analogue ...

A SAR-ADC using unit bridge capacitor and with calibration for the front-end electronics of PET imaging

Energy Technology Data Exchange (ETDEWEB)

Liu, Wei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Wei, Tingcun, E-mail: weitc@nwpu.edu.cn [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Li, Bo; Yang, Lifeng; Xue, Feifei [School of Computer Science and Engineering, Northwestern Polytechnical University, Xi' an 710072, Shaanxi (China); Hu, Yongcai [Institut Pluridisciplinaire Hubert CURIEN, Strasbourg (France)

2016-05-11

This paper presents a 12-bit 1 MS/s successive approximation register-analog to digital converter (SAR-ADC) for the 32-channel front-end electronics of CZT-based PET imaging system. To reduce the capacitance mismatch, instead of the fractional capacitor, the unit capacitor is used as the bridge capacitor in the split-capacitor digital to analog converter (DAC) circuit. In addition, in order to eliminate the periodical DNL errors of −1 LSB which often exists in the SAR-ADC using the charge-redistributed DAC, a calibration algorithm is proposed and verified by the experiments. The proposed 12-bit 1 MS/s SAR-ADC is designed and implemented using a 0.35 μm CMOS technology, it occupies only an active area of 986×956 μm{sup 2}. The measurement results show that, at the power supply of 3.3/5.0 V and the sampling rate of 1 MS/s, the ADC with calibration has a signal-to-noise-and-distortion ratio (SINAD) of 67.98 dB, the power dissipation of 5 mW, and a figure of merit (FOM) of 2.44 pJ/conv.-step. This ADC is with the features of high accuracy, low power and small layout area, it is especially suitable to the one-chip integration of the front-end readout electronics.

Considerations on the design of front-end electronics for silicon calorimetry for the SSC

International Nuclear Information System (INIS)

Wintenberg, A.L.; Bauer, M.L.; Britton, C.L.; Kennedy, E.J.; Todd, R.A.; Berridge, S.C.; Bugg, W.M.

1990-01-01

Some considerations are described for the design of a silicon-based sampling calorimetry detector for the Superconducting Super Collider (SSC). The use of silicon as the detection medium allows fast, accurate, and fine-grained energy measurements - but for optimal performance, the front-end electronics must be matched to the detector characteristics and have the speed required by the high SSC interaction rates. The relation between the signal-to-noise rtio of the calorimeter electronics and the charge collection time, the preamplifier power dissipation, detector capacitance and leakage, charge gain, and signal shaping and sampling was studied. The electrostatic transformer connection was analyzed and found to be unusable for a tightly arranged calorimeter because of stray capacitance effects. The method of deconvolutional sampling was developed as a means for pileup correction following synchronous sampling and analog storage

FRONT-END ASIC FOR A SILICON COMPTON TELESCOPE.

Energy Technology Data Exchange (ETDEWEB)

DE GERONIMO,G.; FRIED, J.; FROST, E.; PHLIPS, B.; VERNON, E.; WULF, E.A.

2007-10-27

We describe a front-end application specific integrated circuit (ASIC) developed for a silicon Compton telescope. Composed of 32 channels, it reads out signals in both polarities from each side of a Silicon strip sensor, 2 mm thick 27 cm long, characterized by a strip capacitance of 30 pF. Each front-end channel provides low-noise charge amplification, shaping with a stabilized baseline, discrimination, and peak detection with an analog memory. The channels can process events simultaneously, and the read out is sparsified. The charge amplifier makes uses a dual-cascode configuration and dual-polarity adaptive reset, The low-hysteresis discriminator and the multi-phase peak detector process signals with a dynamic range in excess of four hundred. An equivalent noise charge (ENC) below 200 electrons was measured at 30 pF, with a slope of about 4.5 electrons/pF at a peaking time of 4 {micro}s. With a total dissipated power of 5 mW the channel covers an energy range up to 3.2 MeV.

Design and construction of the front-end electronics data acquisition for the SLD CRID [Cherenkov Ring Imaging Detector

International Nuclear Information System (INIS)

Hoeflich, J.; McShurley, D.; Marshall, D.; Oxoby, G.; Shapiro, S.; Stiles, P.; Spencer, E.

1990-10-01

We describe the front-end electronics for the Cherenkov Ring Imaging Detector (CRID) of the SLD at the Stanford Linear Accelerator Center. The design philosophy and implementation are discussed with emphasis on the low-noise hybrid amplifiers, signal processing and data acquisition electronics. The system receives signals from a highly efficient single-photo electron detector. These signals are shaped and amplified before being stored in an analog memory and processed by a digitizing system. The data from several ADCs are multiplexed and transmitted via fiber optics to the SLD FASTBUS system. We highlight the technologies used, as well as the space, power dissipation, and environmental constraints imposed on the system. 16 refs., 10 figs

A low power low noise analog front end for portable healthcare system

International Nuclear Information System (INIS)

Wang Yanchao; Ke Keren; Qin Wenhui; Qin Yajie; Yi Ting; Hong Zhiliang

2015-01-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5–100 Hz) and the achieved noise efficient factor is 6.48. (paper)

Front-end Electronics for Unattended Measurement (FEUM). Prototype Test Plan

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C.; Morris, Scott J.; Smith, Leon E.; Keller, Daniel T.

2015-09-16

The IAEA has requested that PNNL perform an initial set of tests on front-end electronics for unattended measurement (FEUM) prototypes. The FEUM prototype test plan details the tests to be performed, the criteria for evaluation, and the procedures used to execute the tests.

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

International Nuclear Information System (INIS)

Chen, Y.T.; La Taille, C. de; Suomijärvi, T.; Cao, Z.; Deligny, O.; Dulucq, F.; Ge, M.M.; Lhenry-Yvon, I.; Martin-Chassard, G.; Nguyen Trung, T.; Wanlin, E.; Xiao, G.; Yin, L.Q.; Yun Ky, B.; Zhang, L.; Zhang, H.Y.; Zhang, S.S.; Zhu, Z.

2015-01-01

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs

Front-end electronics and data acquisition system for imaging atmospheric Cherenkov telescopes

Energy Technology Data Exchange (ETDEWEB)

Chen, Y.T., E-mail: chenytao@ynu.edu.cn [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Yunnan University, 650091 Kunming (China); La Taille, C. de [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Suomijärvi, T. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Cao, Z. [Institute of High Energy Physics, 100049 Beijing (China); Deligny, O. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Dulucq, F. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Ge, M.M. [Yunnan University, 650091 Kunming (China); Lhenry-Yvon, I. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Martin-Chassard, G. [OMEGA (UMS 3605) - IN2P3/CNRS, Ecole Polytechnique, 91128 Palaiseau Cedex (France); Nguyen Trung, T.; Wanlin, E. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Xiao, G.; Yin, L.Q. [Institute of High Energy Physics, 100049 Beijing (China); Yun Ky, B. [Institut de Physique Nucléaire, IN2P3-CNRS, Université Paris-Sud, 91406 Orsay Cedex (France); Zhang, L. [Yunnan University, 650091 Kunming (China); Zhang, H.Y. [Tsinghua University, 100084 Beijing (China); Zhang, S.S.; Zhu, Z. [Institute of High Energy Physics, 100049 Beijing (China)

2015-09-21

In this paper, a front-end electronics based on an application-specific integrated circuit (ASIC) is presented for the future imaging atmospheric Cherenkov telescopes (IACTs). To achieve this purpose, a 16-channel ASIC chip, PARISROC 2 (Photomultiplier ARray Integrated in SiGe ReadOut Chip) is used in the analog signal processing and digitization. The digitized results are sent to the server by a user-defined User Datagram Protocol/Internet Protocol (UDP/IP) hardcore engine through Ethernet that is managed by a FPGA. A prototype electronics fulfilling the requirements of the Wide Field of View Cherenkov Telescope Array (WFCTA) of the Large High Altitude Air Shower Observatory (LHAASO) project has been designed, fabricated and tested to prove the concept of the design. A detailed description of the development with the results of the test measurements are presented. By using a new input structure and a new configuration of the ASIC, the dynamic range of the circuit is extended. A highly precise-time calibrating algorithm is also proposed, verified and optimized for the mass production. The test results suggest that the proposed electronics design fulfills the general specification of the future IACTs.

Front-end data processing the SLD data acquisition system

International Nuclear Information System (INIS)

Nielsen, B.S.

1986-07-01

The data acquisition system for the SLD detector will make extensive use of parallel at the front-end level. Fastbus acquisition modules are being built with powerful processing capabilities for calibration, data reduction and further pre-processing of the large amount of analog data handled by each module. This paper describes the read-out electronics chain and data pre-processing system adapted for most of the detector channels, exemplified by the central drift chamber waveform digitization and processing system

Front-end electronics for H.E.P

International Nuclear Information System (INIS)

Hrisoho, A.

1990-07-01

A simplified description of the front-end electronics used for High Energy Physics Detectors is given. A brief analysis of the speed limitation due to the time necessary for the detector charge transfer is given, which depends as well of the detector behaviour as of the preamplifier configuration. A description of the sample electronic circuits like differentiation, integration, pole zero circuit and preamplifier are given. Noise analysis is carried out to derive the relations for the equivalent noise signal for the measuring device with some description of practical noise measuring. The shaping of the signals to obtain an optimization for the noise is considered and some hints for shaping amplifier design, with a description of the noise weightling function for normal and time variant shaping are given

VME as a front-end electronics system in high energy physics experiments

International Nuclear Information System (INIS)

Ohska, T.K.

1990-01-01

It is only a few years since the VME became a standard system, yet the VME system is already so much more popular than other systems. The VME system was developed for industrial applications and not for the scientific research, and high energy physics field is a tiny market when compared with the industrial market. Considerations made here indicate that the VME system would be a good one for a rear-end system, but would not be a good candidate for front-end electronics in physics experiments. Furthermore, there is a fear that the VXI bus could become popular in this field of instrumentation since the VXI system is backed up by major suppliers of instrumentation in the high energy physics field. VXI would not be an adequate system for front-end electronics, yet advertised to be one. It would be worse to see the VXI system to become a standard system for high energy physics instrumentation than the VME system to be one. The VXI system would do a mediocre job so that people might be misled to think that the VXI system can be used as front-end system. (N.K.)

New RPC front-end electronics for hades

CERN Document Server

Gil, Alejandro; Cabanelas, P; Díaz, J; Garzón, J A; González-Díaz, D; König, W; Lange, J S; Marín, J; Montes, N; Skott, P; Traxler, M

2007-01-01

Time-of-flight (TOF) detectors are mainly used for both particle identification and triggering. Resistive Plate Chamber (RPC) detectors are becoming widely used because of their excellent TOF capabilities and reduced cost. The new ESTRELA* RPC wall, which is being installed in the HADES detector at Darmstadt GSI, will contain 1024 RPC modules, covering an active area of around 7 m2. It has excellent TOF and good charge resolutions. Its Front-End electronics is based on a 8-layer Mother-Board providing impedance matched paths for the output signals of each of the eight 4-channel Daughter-Boards to the TDC.

Development of front-end electronics and TDC LSI for the ATLAS MDT

CERN Document Server

Arai, Y

2000-01-01

Architecture of the front-end electronics for the ATLAS muon precision chamber (MDT) is presented. Especially, test results of a prototype TDC chip are described in detail. The chip was fabricated in a 0.3 mu m CMOS gate-array technology. Measurements of critical elements of the chip such as the PLL, and data buffering circuits demonstrated adequate performance. The effect of gamma-ray irradiation, using a /sup 60/Co source, and neutron irradiation, were also examined. The test results revealed radiation tolerance adequate for the operation of the circuits in the environment of the ATLAS MDT. Mounting of the front-end electronics to the MDT is scheduled to start in the year 2001. (10 refs).

The Majorana Low-noise Low-background Front-end Electronics

Science.gov (United States)

Abgrall, N.; Aguayo, E.; Avignone, F. T.; Barabash, A. S.; Bertrand, F. E.; Boswell, M.; Brudanin, V.; Busch, M.; Byram, D.; Caldwell, A. S.; Chan, Y.-D.; Christofferson, C. D.; Combs, D. C.; Cuesta, C.; Detwiler, J. A.; Doe, P. J.; Efremenko, Yu.; Egorov, V.; Ejiri, H.; Elliott, S. R.; Fast, J. E.; Finnerty, P.; Fraenkle, F. M.; Galindo-Uribarri, A.; Giovanetti, G. K.; Goett, J.; Green, M. P.; Gruszko, J.; Guiseppe, V. E.; Gusev, K.; Hallin, A. L.; Hazama, R.; Hegai, A.; Henning, R.; Hoppe, E. W.; Howard, S.; Howe, M. A.; Keeter, K. J.; Kidd, M. F.; Kochetov, O.; Konovalov, S. I.; Kouzes, R. T.; LaFerriere, B. D.; Leon, J.; Leviner, L. E.; Loach, J. C.; MacMullin, J.; MacMullin, S.; Martin, R. D.; Meijer, S.; Mertens, S.; Nomachi, M.; Orrell, J. L.; O'Shaughnessy, C.; Overman, N. R.; Phillips, D. G.; Poon, A. W. P.; Pushkin, K.; Radford, D. C.; Rager, J.; Rielage, K.; Robertson, R. G. H.; Romero-Romero, E.; Ronquest, M. C.; Schubert, A. G.; Shanks, B.; Shima, T.; Shirchenko, M.; Snavely, K. J.; Snyder, N.; Suriano, A. M.; Thompson, J.; Timkin, V.; Tornow, W.; Trimble, J. E.; Varner, R. L.; Vasilyev, S.; Vetter, K.; Vorren, K.; White, B. R.; Wilkerson, J. F.; Wiseman, C.; Xu, W.; Yakushev, E.; Young, A. R.; Yu, C.-H.; Yumatov, V.

The MAJORANA DEMONSTRATOR will search for the neutrinoless double beta decay (ββ(0ν)) of the isotope 76Ge with a mixed array of enriched and natural germanium detectors. In view of the next generation of tonne-scale germanium-based ββ(0ν)-decay searches, a major goal of the MAJORANA DEMONSTRATOR is to demonstrate a path forward to achieving a background rate at or below 1 cnt/(ROI-t-y) in the 4 keV region of interest (ROI) around the 2039-keV Q-value of the 76Ge ββ(0ν)-decay. Such a requirement on the background level significantly constrains the design of the readout electronics, which is further driven by noise and energy resolution performances. We present here the low-noise low- background front-end electronics developed for the low-capacitance p-type point contact (P-PC) germanium detectors of the MAJORANA DEMONSTRATOR. This resistive-feedback front-end, specifically designed to have low mass, is fabricated on a radioassayed fused-silica substrate where the feedback resistor consists of a sputtered thin film of high purity amorphous germanium and the feedback capacitor is based on the capacitance between gold conductive traces.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Chiri, C.; Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Panareo, M. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy); Pinto, C.; Tassielli, G. [Dipartimento di Matematica e Fisica “Ennio De Giorgi” – Universitá del Salento, Via Arnesano, Lecce (Italy); Istituto Nazionale di Fisica Nucleare Sez. Lecce, Via Arnesano, Lecce (Italy)

2016-07-11

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

A high performance Front End Electronics for drift chamber readout in MEG experiment upgrade

International Nuclear Information System (INIS)

Chiarello, G.; Chiri, C.; Corvaglia, A.; Grancagnolo, F.; Panareo, M.; Pepino, A.; Pinto, C.; Tassielli, G.

2016-01-01

Front End (FE) Electronics plays an essential role in Drift Chambers (DC) for time resolution and, therefore, spatial resolution. The use of cluster timing techniques, by measuring the timing of all the individual ionization clusters after the first one, may enable to reach resolutions even below 100 μm in the measurement of the impact parameter. To this purpose, a Front End Electronics with a wide bandwidth and low noise is mandatory in order to acquire and amplify the drift chamber signals.

A Serializer ASIC at 5 Gbps for Detector Front-end Electronics Readout

CERN Document Server

Gong, D; The ATLAS collaboration; Liu, T; Xiang, A; Ye, J

2010-01-01

High speed and ultra low power serial data transmission over fiber optics plays an essential roll in detector front-end electronics readout for experiments at the LHC. The ATLAS Liquid Argon Calorimeter front-end readout upgrade for the sLHC calls for an optical link system with a data bandwidth of 100 Gbps per each front-end board (FEB), a factor of 62 increase compared with the present optical link system. The transmitter of this optical link will have to withstand the radiation environment where the front-end crates are situated, and stay within the current power dissipation budget limited by the present FEB cooling capacity. To meet these challenges, we developed a 16:1 serializer based on a commercial 0.25 μm silicon-on-sapphire (SOS) CMOS technology. This serializer, designed to work at 5 Gbps, is a key component in an optical link system. Test results of this ASIC will be reported. A system design for the 100 Gbps optical link system will also be presented, with discussions about key components identi...

Analog Circuit Design Low Voltage Low Power; Short Range Wireless Front-Ends; Power Management and DC-DC

CERN Document Server

Roermund, Arthur; Baschirotto, Andrea

2012-01-01

The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design.  Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art information is shared and overviewed. This book is number 20 in this successful series of Analog Circuit Design, providing valuable information and excellent overviews of Low-Voltage Low-Power Data Converters - Chaired by Prof. Anderea Baschirotto, University of Milan-Bicocca Short Range Wireless Front-Ends - Chaired by Prof. Arthur van Roermund, Eindhoven University of Technology Power management and DC-DC - Chaired by Prof. M. Steyaert, Katholieke University Leuven Analog Circuit Design is an essential reference source for analog circuit designers and researchers wishing to keep abreast with the latest development in the field. The tutorial coverage also makes it suitable for use in an advanced design.

A front-end electronic system for large arrays of bolometers

Science.gov (United States)

Arnaboldi, C.; Carniti, P.; Cassina, L.; Gotti, C.; Liu, X.; Maino, M.; Pessina, G.; Rosenfeld, C.; Zhu, B. X.

2018-02-01

CUORE is an array of thermal calorimeters composed of 988 crystals held at about 10 mK, whose absorbed energy is read out with semiconductor thermistors. The composition of the crystal is TeO2, and the aim is the study of the double beta decay of 130Te on very long and stable runs. CUPID-0 is an array of 26 Zn82Se crystals with double thermistor readout to study the double beta decay of 82Se. In the present paper, we present an overview of the entire front-end electronic readout chain, from the preamplifier to the anti-aliasing filter. This overview includes motivations, design strategies, circuit implementation and performance results of the electronic system, including other auxiliary yet important elements like power supplies and the slow control communication system. The stringent requirements of stability on the very long experimental runs that are foreseen during CUORE and CUPID-0 operation, are achieved thanks to novel solutions of the front-end preamplifier and of the detector bias circuit setup.

Novel Front-end Electronics for Time Projection Chamber Detectors

CERN Document Server

García García, Eduardo José

This work has been carried out in the European Organization for Nuclear Research (CERN) and it was supported by the European Union as part of the research and development towards the European detector the (EUDET) project, specifically for the International Linear Collider (ILC). In particle physics there are several different categories of particle detectors. The presented design is focused on a particular kind of tracking detector called Time Projection Chamber (TPC). The TPC provides a three dimensional image of electrically charged particles crossing a gaseous volume. The thesis includes a study of the requirements for future TPC detectors summarizing the parameters that the front-end readout electronics must fulfill. In addition, these requirements are compared with respect to the readouts used in existing TPC detectors. It is concluded that none of the existing front-end readout designs fulfill the stringent requirements. The main requirements for future TPC detectors are high integration, an increased n...

Front-end electronics for the upgraded GMRT

International Nuclear Information System (INIS)

Raut, Anil N; Bhalerao, Vilas; Kumar, A Praveen

2013-01-01

This paper first describes briefly the existing front-end receiver in use at the GMRT observatory and then details the ongoing development of next generation receiver systems for the upgraded GMRT. It covers the design of the new, two stage, room temperature, low noise amplifiers with better noise performance and matching, and improved dynamic range that are being implemented for the 130–260 MHz, 250–500 MHz and 550–900 MHz bands of the upgraded GMRT front-end systems.

Low-voltage analog front-end processor design for ISFET-based sensor and H+ sensing applications

Science.gov (United States)

Chung, Wen-Yaw; Yang, Chung-Huang; Peng, Kang-Chu; Yeh, M. H.

2003-04-01

This paper presents a modular-based low-voltage analog-front-end processor design in a 0.5mm double-poly double-metal CMOS technology for Ion Sensitive Field Effect Transistor (ISFET)-based sensor and H+ sensing applications. To meet the potentiometric response of the ISFET that is proportional to various H+ concentrations, the constant-voltage and constant current (CVCS) testing configuration has been used. Low-voltage design skills such as bulk-driven input pair, folded-cascode amplifier, bootstrap switch control circuits have been designed and integrated for 1.5V supply and nearly rail-to-rail analog to digital signal processing. Core modules consist of an 8-bit two-step analog-digital converter and bulk-driven pre-amplifiers have been developed in this research. The experimental results show that the proposed circuitry has an acceptable linearity to 0.1 pH-H+ sensing conversions with the buffer solution in the range of pH2 to pH12. The processor has a potential usage in battery-operated and portable healthcare devices and environmental monitoring applications.

The hybridized front end electronics of the Central Drift Chamber in the Stanford Linear Collider Detector

International Nuclear Information System (INIS)

Lo, C.C.; Kirsten, F.A.; Nakamura, M.

1987-10-01

In order to accommodate the high packaging density requirements for the front end electronics of the Central Drift Chamber (CDC) in the SLAC Linear Collider Detector (SLD), the CDC front end electronics has been hybridized. The hybrid package contains eight channels of amplifiers together with all the associated circuits for calibration, event recognition and power economy switching functions. A total of 1280 such hybrids are used in the CDC

Installation and testing of the 112 boards for the front-end electronics.

CERN Multimedia

2006-01-01

Installation and testing of the 112 boards for the front-end electronics. 28 boards are interconnected to a TPC type Readout Controller Unit trought the horizontal bus strips. The blue tubes are for the circulating cooling water.

Web-based DAQ systems: connecting the user and electronics front-ends

International Nuclear Information System (INIS)

Lenzi, Thomas

2016-01-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

Web-based DAQ systems: connecting the user and electronics front-ends

Science.gov (United States)

Lenzi, Thomas

2016-12-01

Web technologies are quickly evolving and are gaining in computational power and flexibility, allowing for a paradigm shift in the field of Data Acquisition (DAQ) systems design. Modern web browsers offer the possibility to create intricate user interfaces and are able to process and render complex data. Furthermore, new web standards such as WebSockets allow for fast real-time communication between the server and the user with minimal overhead. Those improvements make it possible to move the control and monitoring operations from the back-end servers directly to the user and to the front-end electronics, thus reducing the complexity of the data acquisition chain. Moreover, web-based DAQ systems offer greater flexibility, accessibility, and maintainability on the user side than traditional applications which often lack portability and ease of use. As proof of concept, we implemented a simplified DAQ system on a mid-range Spartan6 Field Programmable Gate Array (FPGA) development board coupled to a digital front-end readout chip. The system is connected to the Internet and can be accessed from any web browser. It is composed of custom code to control the front-end readout and of a dual soft-core Microblaze processor to communicate with the client.

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2008-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed by a MAPMT and a compact stack of three PCBs which deliver the high voltage, route and readout the output signals. The third board contains a FPGA and MAROC, a 64 channels ASIC which can correct the non uniformity of the MAPMT channels gain thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements.

A low-power high-sensitivity analog front-end for PPG sensor.

Science.gov (United States)

Binghui Lin; Atef, Mohamed; Guoxing Wang

2017-07-01

This paper presents a low-power analog front-end (AFE) photoplethysmography (PPG) sensor fabricated in 0.35 μm CMOS process. The AFE amplifies the weak photocurrent from the photodiode (PD) and converts it to a strong voltage at the output. In order to decrease the power consumption, the circuits are designed in subthreshold region; so the total biasing current of the AFE is 10 μ A. Since the large input DC photocurrent is a big issue for the PPG sensing circuit, we apply a DC photocurrent rejection technique by adding a DC current-cancellation loop to reject the large DC photocurrent up to 10 μA. In addition, a pseudo resistor is used to reduce the high-pass corner frequency below 0.5 Hz and Gm-C filter is adapted to reject the out-of-band noise higher than 16 Hz. For the whole sensor, the amplifier chain can achieve a total gain of 140 dBμ and an input integrated noise current of 68.87 pA rms up to 16 Hz.

Digital front-end electronics for COMPASS Muon-Wall 1 detector

International Nuclear Information System (INIS)

Alekseev, G.D.; Zhuravlev, N.I.; Maggiora, A.

2005-01-01

The digital front-end electronics for the COMPASS Muon-Wall 1 (CERN) detector is described. The digital card has been designed on the basis of the TDC chip F1. One card includes 6 F1 chips (192 channels), bus arbiter, DAC, power supply distribution, hot-link interface. The total number of the digital cards in the system is 44 housed in 5 euro-crates (6U), the total number of readout channels is 8448. The electronics has been designed by the Dzhelepov Laboratory of Nuclear Problems (JINR) and INFN (Torino, Italy) experts

A low power low noise analog front end for portable healthcare system

Science.gov (United States)

Yanchao, Wang; Keren, Ke; Wenhui, Qin; Yajie, Qin; Ting, Yi; Zhiliang, Hong

2015-10-01

The presented analog front end (AFE) used to process human bio-signals consists of chopping instrument amplifier (IA), chopping spikes filter and programmable gain and bandwidth amplifier. The capacitor-coupling input of AFE can reject the DC electrode offset. The power consumption of current-feedback based IA is reduced by adopting capacitor divider in the input and feedback network. Besides, IA's input thermal noise is decreased by utilizing complementary CMOS input pairs which can offer higher transconductance. Fabricated in Global Foundry 0.35 μm CMOS technology, the chip consumes 3.96 μA from 3.3 V supply. The measured input noise is 0.85 μVrms (0.5-100 Hz) and the achieved noise efficient factor is 6.48. Project supported by the Science and Technology Commission of Shanghai Municipality (No. 13511501100), the State Key Laboratory Project of China (No. 11MS002), and the State Key Laboratory of ASIC & System, Fudan University.

Development of a multi-channel front-end electronics module based on ASIC for silicon strip array detectors

International Nuclear Information System (INIS)

Zhao Xingwen; Yan Duo; Su Hong; Qian Yi; Kong Jie; Zhang Xueheng; Li Zhankui; Li Haixia

2014-01-01

The silicon strip array detector is one of external target facility subsystems in the Cooling Storage Ring on the Heavy Ion Research Facility at Lanzhou (HIRFL-CSR). Using the ASICs, the front-end electronics module has been developed for the silicon strip array detectors and can implement measurement of energy of 96 channels. The performance of the front-end electronics module has been tested. The energy linearity of the front-end electronics module is better than 0.3% for the dynamic range of 0.1∼0.7 V. The energy resolution is better than 0.45%. The maximum channel crosstalk is better than 10%. The channel consistency is better than 1.3%. After continuously working for 24 h at room temperature, the maximum drift of the zero-peak is 1.48 mV. (authors)

Front-end Electronics for Unattended Measurement (FEUM). Results of Prototype Evaluation

Energy Technology Data Exchange (ETDEWEB)

Conrad, Ryan C. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Keller, Daniel T. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Morris, Scott J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Smith, Leon E. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States)

2015-07-01

The International Atomic Energy Agency (IAEA) deploys unattended monitoring systems to provide continuous monitoring of nuclear material within safeguarded facilities around the world. As the number of unattended monitoring instruments increases, the IAEA is challenged to become more efficient in the implementation of those systems. In 2010, the IAEA initiated the Front-End Electronics for Unattended Measurement (FEUM) project with the goals of greater flexibility in the interfaces to various sensors and data acquisition systems, and improved capabilities for remotely located sensors (e.g., where sensor and front-end electronics might be separated by tens of meters). In consultation with the IAEA, a technical evaluation of a candidate FEUM device produced by a commercial vendor has been performed. This evaluation assessed the device against the IAEA’s original technical specifications and a broad range of important parameters that include sensor types, cable lengths and types, industrial electromagnetic noise that can degrade signals from remotely located detectors, and high radiation fields. Testing data, interpretation, findings and recommendations are provided.

PMF: The front end electronic of the ALFA detector

Energy Technology Data Exchange (ETDEWEB)

Barrillon, P., E-mail: barrillo@lal.in2p3.f [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Blin, S.; Cheikali, C.; Cuisy, D.; Gaspard, M.; Fournier, D.; Heller, M. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France); Iwanski, W. [Institute of Nuclear Physics PAN, Radzikowskiego 152, 31-342 Cracow (Poland); Lavigne, B.; De la Taille, C.; Puzo, P.; Socha, J-L. [Laboratoire de l' Accelerateur Lineaire, 91898 Orsay (France)

2010-11-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

PMF: the front end electronic of the ALFA detector

CERN Document Server

Barrillon, P; Cheikali, C; Cuisy, D; Gaspard, M; Fournier, D; Heller, M; Iwanski, W; Lavigne, B; de La Taille, C; Puzo, P; Socha, J-L

2010-01-01

The front end electronic (PMF) of the future ATLAS luminometer is described here. It is composed of a MAPMT and a compact stack of three PCBs, which deliver high voltage, route and read out of the output signals. The third board contains an FPGA and MAROC, a 64-channel ASIC, which can correct the non-uniformity of the MAPMT channels gain, thanks to a variable gain preamplifier. Its main role is to shape and discriminate the input signals at 1/3 photo-electron and produce 64 trigger outputs. Laboratory tests performed on prototype and pre-series PMFs have showed performances in good agreement with the requirements and have fulfilled the approval criteria for the final production of all elements.

SPD very front end electronics

International Nuclear Information System (INIS)

Luengo, S.; Gascon, D.; Comerma, A.; Garrido, L.; Riera, J.; Tortella, S.; Vilasis, X.

2006-01-01

The Scintillator Pad Detector (SPD) is part of the LHCb calorimetry system [D. Breton, The front-end electronics for LHCb calorimeters, Tenth International Conference on Calorimetry in Particle Physics, CALOR, Pasadena, 2002] that provides high-energy hadron, electron and photon candidates for the first level trigger. The SPD is designed to distinguish electrons from photons. It consists of a plastic scintillator layer, divided into about 6000 cells of different size to obtain better granularity near the beam [S. Amato, et al., LHCb technical design report, CERN/LHCC/2000-0036, 2000]. Charged particles will produce, and photons will not, ionization in the scintillator. This ionization generates a light pulse that is collected by a WaveLength Shifting (WLS) fiber that is coiled inside the scintillator cell. The light is transmitted through a clear fiber to the readout system that is placed at the periphery of the detector. Due to space constraints, and in order to reduce costs, these 6000 cells are divided in groups using a MAPMT [Z. Ajaltouni, et al., Nucl. Instr. and Meth. A 504 (2003) 9] of 64 channels that provides information to the VFE readout electronics. The SPD signal has rather large statistical fluctuations because of the low number (20-30) of photoelectrons per MIP. Therefore the signal is integrated over the whole bunch crossing length of 25 ns in order to have the maximum value. Since in average about 85% of the SPD signal is within 25 ns, 15% of a sample is subtracted from the following one using an operational amplifier. The SPD VFE readout system that will be presented consists of the following components. A specific ASIC [D. Gascon, et al., Discriminator ASIC for the VFE SPD of the LHCb Calorimeter, LHCB Technical Note, LHCB 2004-xx] integrates the signal, makes the signal-tail subtraction, and compares the level obtained to a programmable threshold (to distinguish electrons from photons). A FPGA programmes the ASIC threshold and the value for

Next generation of optical front-ends for numerical services - 15387

International Nuclear Information System (INIS)

Fullenbaum, M.; Durieux, A.; Dubroca, G.; Fuss, P.

2015-01-01

Visual Inspection and surveillance technology means in environments exhibiting high levels of gamma and neutron radiation are nowadays fulfilled through the use of analog tubes. The images are thus acquired with analog devices whose vast majority relies on 1 and 2/3 inch imaging formats and deliver native analog images. There is a growing demand for real time image processing and distribution through Ethernet services for quicker and seamless process integration throughout many sectors. This will call for the inception of solid state sensor (CCD, CMOS) to generate numerical native images as the first step and building block towards end to end numerical processing (ICT), assuming these sensors can be hardened or protected in the field of the nuclear industry. On the one hand, these sensor sizes will be significantly reduced (by a factor of 2-3) versus those of the tubes, and on the other hand, one will also be presented with the opportunity of increased spatial resolution, stemming from the high pixel count of the solid state technology, for implementation of new or better services or of enhanced pieces of information for decision making purposes. In order to reap the benefits of such sensors, new optical front-ends will have to be designed. Over and beyond the mere aspects of matching the reduced sensor size to the size of the scenes at stake, optical performances of these front-end will also bear an impact on the whole optical chain applications. As an example, detection and tracking needs will be different from a performance standpoint and the overall performances will have to be balanced out in between the optical front-end, the image format, the image processing software capability, processing speed,...just to name a few. In this paper we will review and explain the missing gaps in order to switch to a full numerical optical chain by focusing on the optical front-end and the associated cost trade-offs. Finally, we will conclude by clearly stating the best

Overview of the front end electronics for the Atlas LAR calorimeter

International Nuclear Information System (INIS)

Rescia, S.

1997-11-01

Proposed experiments for the Large Hadron Collider (LHC) set new demands on calorimeter readout electronics. The very high energy and large luminosity of the collider call for a large number of high speed, large dynamic range readout channels which have to be carefully synchronized. The ATLAS liquid argon collaboration, after more than 5 years of R and D developments has now finalized the architecture of its front end and read-out electronics, which have been written down in its Technical Design Report (TDR). An overview is presented

A 1.4-V 48-μW current-mode front-end circuit for analog hearing aids with frequency compensation

International Nuclear Information System (INIS)

Wang Xiaoyu; Yang Haigang; Li Fanyang; Yin Tao; Liu Fei

2012-01-01

A current-mode front-end circuit with low voltage and low power for analog hearing aids is presented. The circuit consists of a current-mode AGC (automatic gain control) and a current-mode adaptive filter. Compared with its conventional voltage-mode counterparts, the proposed front-end circuit has the identified features of frequency compensation based on the state space theory and continuous gain with an exponential characteristic. The frequency compensation which appears only in the DSP unit of the digital hearing aid can upgrade the performance of the analog hearing aid in the field of low-frequency hearing loss. The continuous gain should meet the requirement of any input amplitude level, while its exponential characteristic leads to a large input dynamic range in accordance with the dB SPL (sound pressure level). Furthermore, the front-end circuit also provides a discrete knee point and discrete compression ratio to allow for high calibration flexibility. These features can accommodate users whose ears have different pain thresholds. Taking advantage of the current-mode technique, the MOS transistors work in the subthreshold region so that the quiescent current is small. Moreover, the input current can be compressed to a low voltage signal for processing according to the compression principle from the current-domain to the voltage-domain. Therefore, the objective of low voltage and low power (48 μW at 1.4 V) can be easily achieved in a high threshold-voltage CMOS process of 0.35 μm (V TON + |V TOP |≈ 1.35 V). The THD is below −45 dB. The fabricated chip only occupies the area of 1 × 0.5 mm 2 and 1 × 1 mm 2 .

A dual slope charge sampling analog front-end for a wireless neural recording system.

Science.gov (United States)

Lee, Seung Bae; Lee, Byunghun; Gosselin, Benoit; Ghovanloo, Maysam

2014-01-01

This paper presents a novel dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which amplifies neural signals by taking advantage of the charge sampling concept for analog signal conditioning, such as amplification and filtering. The presented DSCS-AFE achieves amplification, filtering, and sampling in a simultaneous fashion, while consuming very small amount of power. The output of the DSCS-AFE produces a pulse width modulated (PWM) signal that is proportional to the input voltage amplitude. A circular shift register (CSR) utilizes time division multiplexing (TDM) of the PWM pulses to create a pseudo-digital TDM-PWM signal that can feed a wireless transmitter. The 8-channel system-on-a-chip was fabricated in a 0.35-μm CMOS process, occupying 2.4 × 2.1 mm(2) and consuming 255 μW from a 1.8V supply. Measured input-referred noise for the entire system, including the FPGA in order to recover PWM signal is 6.50 μV(rms) in the 288 Hz~10 kHz range. For each channel, sampling rate is 31.25 kHz, and power consumption is 31.8 μW.

A new portable test bench for the ATLAS Tile Calorimeter front-end electronics certification

International Nuclear Information System (INIS)

Alves, J.; Carrio, F.; Moreno, P.; Usai, G.; Valero, A.; Kim, H.Y.; Minashvili, I.; Shalyugin, A.; Reed, R.; Schettino, V.; Souza, J.; Solans, C.

2013-06-01

This paper describes the upgraded portable test bench for the Tile Calorimeter of the ATLAS experiment at CERN. The previous version of the portable test bench was extensively used for certification and qualification of the front-end electronics during the commissioning phase as well as during the short maintenance periods of 2010 and 2011. The new version described here is designed to be an easily upgradable version of the 10-year-old system, able to evaluate the new technologies planned for the ATLAS upgrade as well as provide new functionalities to the present system. It will be used in the consolidation of electronics campaign during the long shutdown of the LHC in 2013-14 and during future maintenance periods. The system, based on a global re-design with state-of-the-art devices, is based on a back-end electronics crate instrumented with commercial and custom modules and a front-end GUI that is executed on an external portable computer and communicates with the controller in the crate through an Ethernet connection. (authors)

Performance of Front-End Readout System for PHENIX RICH

International Nuclear Information System (INIS)

Oyama, K.; Hamagaki, H.; Nishimura, S.; Shigaki, K.; Hayano, R.S.; Hibino, M.; Kametani, S.; Kikuchi, J.; Matsumoto, T.; Sakaguchi, T.; Ebisu, K.; Hara, H.; Tanaka, Y.; Ushiroda, T.; Moscone, C.G.; Wintenberg, A.L.; Young, G.R.

1999-01-01

A front-end electronics system has been developed for the Ring Imaging Cerenkov (RICH) detector of the PHENIX experiment at the Relativistic Heavy Ion Collider (RHIC), Brookhaven National Laboratory (BNL). A high speed custom back-plane with source synchronous bus architecture, a full custom analog ASIC, and board modules with FPGA's and CPLD's were developed for high performance real time data acquisition. The transfer rate of the back-lane has reached 640 MB/s with 128 bits data bus. Total transaction time is estimated to be less than 30 micros per event. The design specifications and test results of the system are presented in this paper

AMIC: an expandable integrated analog front-end for light distribution moments analysis

Energy Technology Data Exchange (ETDEWEB)

Spaggiari, M; Herrero, V; Lerche, C W; Aliaga, R; Monzo, J M; Gadea, R, E-mail: michele.spaggiari@gmail.com [Instituto de Instrumentacion para Imagen Molecular (I3M), Universidad Politecnica de Valencia, Camino de Vera, 46022, Valencia (Spain)

2011-01-15

In this article we introduce AMIC (Analog Moments Integrated Circuit), a novel analog Application Specific Integrated Circuit (ASIC) front-end for Positron Emission Tomography (PET) applications. Its working principle is based on mathematical analysis of light distribution through moments calculation. Each moment provides useful information about light distribution, such as energy, position, depth of interaction, skewness (deformation due to border effect) etc. A current buffer delivers a copy of each input current to several processing blocks. The current preamplifier is designed in order to achieve unconditional stability under high input capacitance, thus allowing the use of both Photo-Multiplier Tubes (PMT) and Silicon Photo-Multipliers (SiPM). Each processing block implements an analog current filtering by multiplying each input current by a programmable 8-bit coefficient. The latter is implemented through a high linear MOS current divider ladder, whose high sensitivity to variations in output voltages requires the integration of an extremely stable fully differential current collector. Output currents are then summed and sent to the output stage, that provides both a buffered output current and a linear rail-to-rail voltage for further digitalization. Since computation is purely additive, the 64 input channels of AMIC do not represent a limitation in the number of the detector's outputs. Current outputs of various AMIC structures can be combined as inputs of a final AMIC, thus providing a fully expandable structure. In this version of AMIC, 8 programmable blocks for moments calculation are integrated, as well as an I2C interface in order to program every coefficient. Extracted layout simulation results demonstrate that the information provided by moment calculation in AMIC helps to improve tridimensional positioning of the detected event. A two-detector test-bench is now being used for AMIC prototype characterization and preliminary results are presented.

Anode front-end electronics for the cathode strip chambers of the CMS Endcap Muon detector

International Nuclear Information System (INIS)

Ferguson, T.; Bondar, N.; Golyash, A.; Sedov, V.; Terentiev, N.; Vorobiev, I.

2005-01-01

The front-end electronics system for the anode signals of the CMS Endcap Muon cathode strip chambers has about 183,000 channels. The purposes of the anode front-end electronics are to acquire precise muon timing information for bunch crossing number identification at the Level-1 muon trigger system and to provide a coarse radial position of the muon track. Each anode channel consists of an input protection network, amplifier, shaper, constant-fraction discriminator, and a programmable delay. The essential parts of the electronics include a 16-channel amplifier-shaper-discriminator ASIC CMP16 and a 16-channel ASIC D16G providing programmable time delay. The ASIC CMP16 was optimized for the large cathode chamber size (up to 3x2.5 m 2 ) and for the large input capacitance (up to 200 pF). The ASIC combines low power consumption (30 mW/channel) with good time resolution (2-3 ns). The delay ASIC D16G makes possible the alignment of signals with an accuracy of 2.2 ns. This paper presents the anode front-end electronics structure and results of the preproduction and the mass production tests, including radiation resistance and reliability tests. The special set of test equipment, techniques, and corresponding software developed and used in the test procedures are also described

Radiation hardness on very front-end for SPD

International Nuclear Information System (INIS)

Cano, Xavier; Graciani, Ricardo; Gascon, David; Garrido, Lluis; Bota, Sebastia; Herms, Atila; Comerma, Albert; Riera, Jordi

2005-01-01

The calorimeter front-end electronics of the LHCb experiment will be located in a region, which is not protected from radiation. Therefore, all the electronics must be qualified to stand some defined radiation levels. The procedure, measurements and results of an irradiation test for every component of the very front-end SPD detector, which is part of the LHCb calorimeter are presented here. All the tested components, except a custom made ASIC, are commercially available

Development of front-end electronics for LumiCal detector in CMOS 130 nm technology

CERN Document Server

Firlej, M; Idzik, M; Moron, J; Swientek, K; Terlecki, P

2015-01-01

front-end electronics for luminosity detector at future Linear Collider are presented. The 8-channel prototype was designed and fabricated in a 130 nm CMOS technology. Each channel comprises a charge sensitive preamplifier with pole-zero cancellation circuit and a CR-RC shaper with 50 ns peaking time. The measurements results confirm full functionality of the prototype and compliance with the requirements imposed by the detector specification. The power consumption of the front-end is in the range 0.6–1.5 mW per channel and the noise ENC around 900 e− at 10 pF input capacitance.

An analog integrated front-end amplifier for neural applications

OpenAIRE

Zhou, Zhijun; Warr, Paul

2017-01-01

The front-end amplifier forms the critical element for signal detection and pre-processing within neural monitoring systems. It determines not only the fidelity of the biosignal, but also impacts power consumption and detector size. In this paper, a combined feedback loop-controlled approach is proposed to neutralize for the input leakage currents generated by low noise amplifiers when in integrated circuit form, alongside signal leakage into the input bias network. Significantly, this loop t...

Tester of the TRT front-end electronics for the ATLAS-experiment

CERN Document Server

Hajduk, Z; Kisielewski, B; Kotarba, A; Malecki, P; Natkaniec, Z; Olszowska, J; Ostrowicz, W; Krupinska, G

2000-01-01

The VME based tester for front-end electronics of the TRT (Transition Radiation Tracker) detector of the ATLAS-LHC experiment at CERN, Geneva, is described. The TRT read-out electronics for 424576 proportional tubes grouped on many thousands of cards requires stringent quality control after assembly and during installation. The tester provides all required data, pulses, timing and power supplies for tested cards. The essential part of the tester is its software that allows for device handling as well as facilitates functional and statistical tests. The prototype, present design as well as the new design for mass production tests are discussed. (17 refs).

Forecasting noise and radiation hardness of CMOS front-end electronics beyond the 100 nm frontier

International Nuclear Information System (INIS)

Re, V.; Gaioni, L.; Manghisoni, M.; Ratti, L.; Traversi, G.

2010-01-01

The progress of industrial microelectronic technologies has already overtaken the 130 nm CMOS generation that is currently the focus of IC designers for new front-end chips in LHC upgrades and other detector applications. In a broader time span, sub-100 nm CMOS processes may become appealing for the design of very compact front-end systems with advanced integrated functionalities. This is especially true in the case of pixel detectors, both for monolithic devices (MAPS) and for hybrid implementations where a high resistivity sensor is connected to a CMOS readout chip. Technologies beyond the 100 nm frontier have peculiar features, such as the evolution of the device gate material to reduce tunneling currents through the thin dielectric. These new physical device parameters may impact on functional properties such as noise and radiation hardness. On the basis of experimental data relevant to commercial devices, this work studies potential advantages and challenges associated to the design of low-noise and rad-hard analog circuits in these aggressively scaled technologies.

Calibration method for direct conversion receiver front-ends

Directory of Open Access Journals (Sweden)

R. Müller

2008-05-01

Full Text Available Technology induced process tolerances in analog circuits cause device characteristics different from specification. For direct conversion receiver front-ends a system level calibration method is presented. The malfunctions of the devices are compensated by tuning dominant circuit parameters. Thereto optimization techniques are applied which use measurement values and special evaluation functions.

End-Users, Front Ends and Librarians.

Science.gov (United States)

Bourne, Donna E.

1989-01-01

The increase in end-user searching, the advantages and limitations of front ends, and the role of the librarian in end-user searching are discussed. It is argued that librarians need to recognize that front ends can be of benefit to themselves and patrons, and to assume the role of advisors and educators for end-users. (37 references) (CLB)

Estimation of radiation effects in the front-end electronics of an ILC electromagnetic calorimeter

International Nuclear Information System (INIS)

Bartsch, V.; Postranecky, M.; Targett-Adams, C.; Warren, M.; Wing, M.

2008-01-01

The front-end electronics of the electromagnetic calorimeter of an International Linear Collider detector are situated in a radiation environment. This requires the effect of the radiation on the performance of the electronics, specifically FPGAs, to be examined. In this paper we study the flux, particle spectra and deposited doses at the front-end electronics of the electromagnetic calorimeter of a detector at the ILC. We also study the occupancy of the electromagnetic calorimeter. These estimates are compared with measurements, e.g. of the radiation damage of FPGAs, done elsewhere. The outcome of the study shows that the radiation doses and the annual flux is low enough to allow today's FPGAs to operate. The Single Event Upset rate, however, lies between 14 min and 12 h depending on the FPGA used and therefore needs to be considered in the design of the data acquisition system of the electromagnetic calorimeter. The occupancy is about 0.002 per bunch train not taking into account the effect of noise which depends on the choice of the detector

Gravitational Reference Sensor Front-End Electronics Simulator for LISA

International Nuclear Information System (INIS)

Meshksar, Neda; Ferraioli, Luigi; Mance, Davor; Zweifel, Peter; Giardini, Domenico; Ten Pierick, Jan

2017-01-01

At the ETH Zurich we are developing a modular simulator that provides a realistic simulation of the Front End Electronics (FEE) for LISA Gravitational Reference Sensor (GRS). It is based on the GRS FEE-simulator already implemented for LISA Pathfinder. It considers, in particular, the non-linearity and the critical details of hardware, such as the non-linear multiplicative noise caused by voltage reference instability, test mass charging and detailed actuation and sensing algorithms. We present the simulation modules, considering the above-mentioned features. Based on the ETH GRS FEE-simulator for LISA Pathfinder we aim to develop a modular simulator that provides a realistic simulation of GRS FEE for LISA. (paper)

Front-end electronics and trigger systems - status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth G; Spieler, Helmuth G

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not provide the required electronic noise at lower power, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

Low noise monolithic CMOS front end electronics

International Nuclear Information System (INIS)

Lutz, G.; Bergmann, H.; Holl, P.; Manfredi, P.F.

1987-01-01

Design considerations for low noise charge measurement and their application in CMOS electronics are described. The amplifier driver combination whose noise performance has been measured in detail as well as the analog multiplexing silicon strip detector readout electronics are designed with low power consumption and can be operated in pulsed mode so as to reduce heat dissipation even further in many applications. (orig.)

Front-end module readout and control electronics for the PHENIX Multiplicity Vertex Detector

International Nuclear Information System (INIS)

Ericson, M.N.; Allen, M.D.; Boissevain, J.

1997-11-01

Front-end module (FEM) readout and control are implemented as modular, high-density, reprogrammable functions in the PHENIX Multiplicity Vertex Detector. FEM control is performed by the heap manager, an FPGA-based circuit in the FEM unit. Each FEM has 256 channels of front-end electronics, readout, and control, all located on an MCM. Data readout, formatting, and control are performed by the heap manager along with 4 interface units that reside outside the MVD detector cylinder. This paper discusses the application of a generic heap manager and the addition of 4 interface module types to meet the specific control and data readout needs of the MVD. Unit functioning, interfaces, timing, data format, and communication rates will be discussed in detail. In addition, subsystem issues regarding mode control, serial architecture and functions, error handling, and FPGA implementation and programming will be presented

Electronic front-end for LHCb electromagnetic and hadronic calorimeters

International Nuclear Information System (INIS)

Beigbeder, Ch.

2000-11-01

The electronic front-end of the LHCb electromagnetic and hadronic calorimeters will be described. It consists of a 9U 32 channel board, each channel including shaper-integrator, 12 bit ADC and look-up tables allowing to code the transverse energy information both for readout and for the Level 0 trigger. The readout information is stored in a fixed latency followed by a derandomizer. The trigger information is processed further on the board by FPGA, performing channel addition and comparison to extract the highest transverse energy local cluster for further processing. The system is fully synchronous and allows to extract candidates for calorimetric trigger at every 40 MHz clock cycle. The operation and characteristics (noise, linearity etc.) of a prototype board will be described. (author)

CODA : Compact front-end analog ASIC for silicon detectors

International Nuclear Information System (INIS)

Chandratre, V.B.; Sardesai, S.V.; Kataria, S.K.

2004-01-01

The paper presents the design of a front-end signal processing ASIC to be used with Silicon detectors having full depletion capacitance up to 40 pf. The ASIC channel consists of a charge amplifier, a shaper amplifier (CR-RC 3 ) and a comparator. There is provision for changing gain and polarity. The circuit has an estimated power dissipation of 16 mw. The ASIC is fabricated in 1.2 um CMOS technology. The 0pf noise is ∼400e. The chip has an area of 3 by 4 mm is packaged in 48 pin CLCC and COB option (Chip on Board). (author)

Design of a wideband CMOS impedance spectroscopy ASIC analog front-end for multichannel biosensor interfaces.

Science.gov (United States)

Valente, Virgilio; Dai Jiang; Demosthenous, Andreas

2015-08-01

This paper presents the preliminary design and simulation of a flexible and programmable analog front-end (AFE) circuit with current and voltage readout capabilities for electric impedance spectroscopy (EIS). The AFE is part of a fully integrated multifrequency EIS platform. The current readout comprises of a transimpedance stage and an automatic gain control (AGC) unit designed to accommodate impedance changes larger than 3 order of magnitude. The AGC is based on a dynamic peak detector that tracks changes in the input current over time and regulates the gain of a programmable gain amplifier in order to optimise the signal-to-noise ratio. The system works up to 1 MHz. The voltage readout consists of a 2 stages of fully differential current-feedback instrumentation amplifier which provide 100 dB of CMRR and a programmable gain up to 20 V/V per stage with a bandwidth in excess of 10MHz.

Highly integrated front-end electronics for spaceborne fluxgate sensors

International Nuclear Information System (INIS)

Magnes, W; Valavanoglou, A; Hagen, C; Jernej, I; Baumjohann, W; Oberst, M; Hauer, H; Neubauer, H; Pierce, D; Means, J; Falkner, P

2008-01-01

Scientific instruments for challenging and cost-optimized space missions have to reduce their resource requirements while keeping the high performance levels of conventional instruments. In this context the development of an instrument front-end ASIC (0.35 µm CMOS from austriamicrosystems) for magnetic field sensors based on the fluxgate principle was undertaken. It is based on the combination of the conventional readout electronics of a fluxgate magnetometer with the control loop of a sigma-delta modulator for a direct digitization of the magnetic field. The analogue part is based on a modified 2–2 cascaded sigma-delta modulator. The digital part includes a primary (128 Hz output) and secondary decimation filter (2, 4, 8,..., 64 Hz output) as well as a serial synchronous interface. The chip area is 20 mm 2 and the total power consumption is 60 mW. It has been demonstrated that the overall functionality and performance of the magnetometer front-end ASIC (MFA) is sufficient for scientific applications in space. Noise performance (SNR of 89 dB with a bandwidth of 30 Hz) and offset stability ( −1 MFA temperature, −1 is acceptable. Only a cross-tone phenomenon must be avoided in future designs even though it is possible to mitigate the effect to a level that is tolerable. The MFA stays within its parameters up to 170 krad of total ionizing dose and it keeps full functionality up to more than 300 krad. The threshold for latch-ups is 14 MeV cm 2 mg −1

Test system for the production of the Atlas Tile Calorimeter front-end electronics

International Nuclear Information System (INIS)

Calvet, David

2004-01-01

The Atlas hadronic Tile Calorimeter front-end electronics is fully included in the so-called 'super-drawers'. The 256 super-drawers needed for the entire calorimeter are assembled and extensively tested in Clermont-Ferrand before being sent to CERN to be inserted in the calorimeter modules. A mobile system has been developed to perform a complete test of the super-drawers during their insertion

Development of ATLAS Liquid Argon Calorimeter Front-end Electronics for the HL-LHC

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00219286; The ATLAS collaboration

2016-01-01

The high-luminosity phase of the Large Hadron Collider will provide 5-7 times greater luminosities than assumed in the original detector design. An improved trigger system requires an upgrade of the readout electronics of the ATLAS Liquid Argon Calorimeter. Concepts for the future readout of the 182,500 calorimeter channels at 40-80 MHz and 16-bit dynamic range and the developments of radiation-tolerant, low-noise, low-power, and high-bandwidth front-end electronic components, including preamplifiers and shapers, 14-bit ADCs, and 10-Gb/s laser diode array drivers, are presented.

An Inductively-Powered Wireless Neural Recording System with a Charge Sampling Analog Front-End.

Science.gov (United States)

Lee, Seung Bae; Lee, Byunghun; Kiani, Mehdi; Mahmoudi, Babak; Gross, Robert; Ghovanloo, Maysam

2016-01-15

An inductively-powered wireless integrated neural recording system (WINeR-7) is presented for wireless and battery less neural recording from freely-behaving animal subjects inside a wirelessly-powered standard homecage. The WINeR-7 system employs a novel wide-swing dual slope charge sampling (DSCS) analog front-end (AFE) architecture, which performs amplification, filtering, sampling, and analog-to-time conversion (ATC) with minimal interference and small amount of power. The output of the DSCS-AFE produces a pseudo-digital pulse width modulated (PWM) signal. A circular shift register (CSR) time division multiplexes (TDM) the PWM pulses to create a TDM-PWM signal, which is fed into an on-chip 915 MHz transmitter (Tx). The AFE and Tx are supplied at 1.8 V and 4.2 V, respectively, by a power management block, which includes a high efficiency active rectifier and automatic resonance tuning (ART), operating at 13.56 MHz. The 8-ch system-on-a-chip (SoC) was fabricated in a 0.35-μm CMOS process, occupying 5.0 × 2.5 mm 2 and consumed 51.4 mW. For each channel, the sampling rate is 21.48 kHz and the power consumption is 19.3 μW. In vivo experiments were conducted on freely behaving rats in an energized homecage by continuously delivering 51.4 mW to the WINeR-7 system in a closed-loop fashion and recording local field potentials (LFP).

Front-end electronics and trigger systems-Status and challenges

International Nuclear Information System (INIS)

Spieler, Helmuth

2007-01-01

The past quarter century has brought about a revolution in front-end electronics for large-scale detector systems. Custom integrated circuits specifically tailored to the requirements of large detector systems have provided unprecedented performance and enabled systems that once were deemed impossible. The evolution of integrated circuit readouts in strip detectors is summarized, the present status described, and challenges posed by the sLHC and ILC are discussed. Performance requirements increase, but key considerations remain as in the past: power dissipation, material, and services. Smaller CMOS feature sizes will not reduce the power required for the desired noise levels, but will improve digital power efficiency. Significant improvements appear to be practical in more efficient power distribution. Enhanced digital electronics have provided powerful trigger processors that greatly improve the trigger efficiency. In data readout systems, they also improve data throughput, while reducing power requirements. Concurrently with new developments in high energy physics, detector systems for cosmology and astrophysics have made great strides. As an example, a large-scale readout for superconducting bolometer arrays is described

FELIX: a high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

NARCIS (Netherlands)

Anderson, J.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Francis, D.; Gorini, B.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Plessl, C.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Zhang, J.

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

Energy Technology Data Exchange (ETDEWEB)

Adinolfi, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Bibby, J.H. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Brisbane, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Gibson, V. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Harnew, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Jones, M. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Libby, J. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom)]. E-mail: j.libby1@physics.ox.ac.uk; Powell, A. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Newby, C. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Rotolo, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Smale, N. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Somerville, L.; Sullivan, P.; Topp-Jorgensen, S. [Sub-department of Particle Physics, University of Oxford, Denys Wilkinson Building, Keble Road, Oxford, OX1 3RH (United Kingdom); Wotton, S. [Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE (United Kingdom); Wyllie, K. [CERN, CH-1211, Geneva 23 (Switzerland)

2007-03-11

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests.

The front-end (Level-0) electronics interface module for the LHCb RICH detectors

International Nuclear Information System (INIS)

Adinolfi, M.; Bibby, J.H.; Brisbane, S.; Gibson, V.; Harnew, N.; Jones, M.; Libby, J.; Powell, A.; Newby, C.; Rotolo, N.; Smale, N.; Somerville, L.; Sullivan, P.; Topp-Jorgensen, S.; Wotton, S.; Wyllie, K.

2007-01-01

The front-end (Level-0) electronics interface module for the LHCb Ring Imaging Cherenkov (RICH) detectors is described. This module integrates the novel hybrid photon detectors (HPDs), which instrument the RICH detectors, to the LHCb trigger, data acquisition (DAQ) and control systems. The system operates at 40 MHz with a first-level trigger rate of 1 MHz. The module design is presented and results are given for both laboratory and beam tests

Review of input stages used in front end electronics for particle detectors

CERN Document Server

Kaplon, J

2015-01-01

In this paper we present noise analysis of the input stages most commonly used in front end electronics for particle detectors. Analysis shows the calculation of the input referenced noise related to the active devices. It identifies the type, parallel or series, of the equivalent noise sources related to the input transistors, which is the important input for the further choice of the signal processing method. Moreover we calculate the input impedance of amplifiers employed in applications where the particle detector is connected to readout electronics by means of transmission line. We present schematics, small signal models,a complete set of equations, and results of the major steps of calculations for all discussed circuits.

Parallel and pipelined front-end for multi-element silicon detectors in scanning electron microscopy

International Nuclear Information System (INIS)

Boulin, C.; Epstein, A.

1992-01-01

This paper discusses a silicon quadrant detector (128 elements) implemented as an electron detector in a Scanning Transmission Electron Microscope. As the electron beam scans over the sample, electrons are counted during each pixel. The authors developed an ASIC for the multichannel counting system. The digital front-end carries out the readout of all elements, in four groups, and uses these data to compute linear combinations to generate up to eight simultaneous images. For the preprocessing the authors implemented a parallel and pipelined system. Dedicated software tools were developed to generate the programs for all the processors. These tools are transparently accessed by the user via a user friendly interface

The control system for the CMS tracker front-end

CERN Document Server

Drouhin, F; Ljuslin, C; Maazouzi, C; Marchiero, A; Marinelli, N; Paillard, C; Siegrist, P; Tsirou, A L; Verdini, P G; Walsham, P; Zghiche, A

2002-01-01

The CMS Tracker uses complex, programmable embedded electronics for the readout of the Silicon sensors, for the control of the working point of the optical transmitters, for the phase adjustment of the 40 MHz LHC clock and for the monitoring of the voltages, currents and temperatures. In order to establish reliable, noise-free communication with the outside world the control chain has been designed to operate over a ribbon of optical fibers. The optical links, the Front End Controller board that carries their support electronics, the Clocking and Control Unit module receiving the signals over the high-speed link and fanning them out to the front- ends have recently become available. A multi-layered software architecture to handle these devices, and the front-ends, in a way transparent to the end-user, interfaced to an Oracle database for the retrieval of the parameters to be downloaded with the intent of building and operating a small-scale prototype of the control system for the CMS Tracker. The paper descri...

BORA: a front end board, with local intelligence, for the RICH detector of the Compass Collaboration

International Nuclear Information System (INIS)

Baum, G.; Birsa, R.; Bradamante, F.; Bressan, A.; Colavita, A.; Crespo, M.; Costa, S.; Dalla Torre, S.; Fauland, P.; Finger, M.; Fratnik, F.; Giorgi, M.; Gobbo, B.; Grasso, A.; Lamanna, M.; Martin, A.; Menon, G.; Panzieri, D.; Schiavon, P.; Tessarotto, F.; Zanetti, A.M.

1999-01-01

In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analog voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analog channel. The digitized analogue values are then written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analog channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC

The Study of Fault Location for Front-End Electronics System

International Nuclear Information System (INIS)

Zhang Fan; Wang Dong; Huang Guangming; Zhou Daicui

2009-01-01

Since some devices on the latest developed 250 ALICE/PHOS Front-end electronics (FEE) system cards had been partly or completely damaged during lead-free soldering. To alleviate the influence on the performance of FEE system and to locate fault related FPGA accurately, we should find a method for locating fault of FEE system based on the deep study of FPGA configuration scheme. It emphasized on the problems such as JTAG configuration of multi-devices, PS configuration based on EPC series configuration devices and auto re-configuration of FPGA. The result of the massive FEE system cards testing and repairing show that that location method can accurately and quickly target the fault point related FPGA on FEE system cards. (authors)

New read-out electronics for ICARUS-T600 liquid Argon TPC. Description, simulation and tests of the new front-end and ADC system arXiv

CERN Document Server

Bagby, L.; Bellini, V.; Bonesini, M.; Braggiotti, A.; Castellani, L.; Centro, S.; Cervi, T.; Cocco, A.G.; Fabris, F.; Falcone, A.; Farnese, C.; Fava, A.; Fichera, F.; Franciotti, D.; Galet, G.; Gibin, D.; Guglielmi, A.; Guida, R.; Ketchum, W.; Marchini, S.; Menegolli, A.; Meng, G.; Menon, G.; Montanari, C.; Nessi, M.; Nicoletto, M.; Pedrotta, R.; Picchi, P.; Pietropaolo, F.; Rampazzo, G.; Rappoldi, A.; Raselli, G.L.; Rossella, M.; Rubbia, C.; Scaramelli, A.; Sergiampietri, F.; Spanu, M.; Torti, M.; Tortorici, F.; Varanini, F.; Ventura, S.; Vignoli, C.; Zani, A.; Zatti, P.G.

The ICARUS T600, a liquid argon time projection chamber (LAr-TPC) detector mainly devoted to neutrino physics, underwent a major overhauling at CERN in 2016-2017, which included also a new design of the read-out electronics, in view of its operation in Fermilab on the Short Baseline Neutrino (SBN) beam from 2019. The new more compact electronics showed capability of handling more efficiently the signals also in the intermediate Induction 2 wire plane with a significant increase of signal to noise (S/N), allowing for charge measurement also in this view. The new front-end and the analog to digital conversion (ADC) system are presented together with the results of the tests on 50 liters liquid argon TPC performed at CERN with cosmic rays.

Parameters-adjustable front-end controller in digital nuclear measurement system

International Nuclear Information System (INIS)

Hao Dejian; Zhang Ruanyu; Yan Yangyang; Wang Peng; Tang Changjian

2013-01-01

Background: One digitizer is used to implement a digital nuclear measurement for the acquisition of nuclear information. Purpose: A principle and method of a parameter-adjustable front-end controller is presented for the sake of reducing the quantitative errors while getting the maximum ENOB (effective number of bits) of ADC (analog-to-digital converter) during waveform digitizing, as well as reducing the losing counts. Methods: First of all, the quantitative relationship among the radiation count rate (n), the amplitude of input signal (V in ), the conversion scale of ADC (±V) and the amplification factor (A) was derived. Secondly, the hardware and software of the front-end controller were designed to fulfill matching the output of different detectors, adjusting the amplification linearly through the control of channel switching, and setting of digital potentiometer by CPLD (Complex Programmable Logic Device). Results: (1) Through the measurement of γ-ray of Am-241 under our digital nuclear measurement set-up with CZT detector, it was validated that the amplitude of output signal of detectors of RC feedback type could be amplified linearly with adjustable amplification by the front-end controller. (2) Through the measurement of X-ray spectrum of Fe-5.5 under our digital nuclear measurement set-up with Si-PIN detector, it was validated that the front-end controller was suitable for the switch resetting type detectors, by which high precision measurement under various count rates could be fulfilled. Conclusion: The principle and method of the parameter-adjustable front-end controller presented in this paper is correct and feasible. (authors)

An integrated multichannel neural recording analog front-end ASIC with area-efficient driven right leg circuit.

Science.gov (United States)

Tao Tang; Wang Ling Goh; Lei Yao; Jia Hao Cheong; Yuan Gao

2017-07-01

This paper describes an integrated multichannel neural recording analog front end (AFE) with a novel area-efficient driven right leg (DRL) circuit to improve the system common mode rejection ratio (CMRR). The proposed AFE consists of an AC-coupled low-noise programmable-gain amplifier, an area-efficient DRL block and a 10-bit SAR ADC. Compared to conventional DRL circuit, the proposed capacitor-less DRL design achieves 90% chip area reduction with enhanced CMRR performance, making it ideal for multichannel biomedical recording applications. The AFE circuit has been designed in a standard 0.18-μm CMOS process. Post-layout simulation results show that the AFE provides two gain settings of 54dB/60dB while consuming 1 μA per channel under a supply voltage of 1 V. The input-referred noise of the AFE integrated from 1 Hz to 10k Hz is only 4 μVrms and the CMRR is 110 dB.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

Science.gov (United States)

Anderson, J.; Bauer, K.; Borga, A.; Boterenbrood, H.; Chen, H.; Chen, K.; Drake, G.; Dönszelmann, M.; Francis, D.; Guest, D.; Gorini, B.; Joos, M.; Lanni, F.; Lehmann Miotto, G.; Levinson, L.; Narevicius, J.; Panduro Vazquez, W.; Roich, A.; Ryu, S.; Schreuder, F.; Schumacher, J.; Vandelli, W.; Vermeulen, J.; Whiteson, D.; Wu, W.; Zhang, J.

2016-12-01

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

CERN Document Server

AUTHOR|(INSPIRE)INSPIRE-00015561; Bauer, Kevin Thomas; Borga, Andrea; Boterenbrood, Henk; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Guest, Daniel; Gorini, Benedetto; Joos, Markus; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Panduro Vazquez, William; Roich, Alexander; Ryu, Soo; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Whiteson, Daniel; Wu, Weihao; Zhang, Jinlong

2016-01-01

The ATLAS Phase-I upgrade (2018) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS Upgrade framework

International Nuclear Information System (INIS)

Anderson, J.; Drake, G.; Ryu, S.; Bauer, K.; Guest, D.; Borga, A.; Boterenbrood, H.; Schreuder, F.; Chen, H.; Chen, K.; Lanni, F.; Dönszelmann, M.; Francis, D.; Gorini, B.; Joos, M.; Miotto, G. Lehmann; Levinson, L.; Narevicius, J.; Roich, A.; Vazquez, W. Panduro

2016-01-01

The ATLAS Phase-I upgrade (2019) requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The Front-End LInk eXchange (FELIX) system provides an infrastructure to achieve this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, interfacing custom radiation tolerant optical links from front-end electronics, via PCIe Gen3 cards, to a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favour of software running on commercial servers. The FELIX system, the design of the PCIe prototype card and the integration test results are presented in this paper.

Testing and development of an OWC MRI compatible PET insert front-end

Energy Technology Data Exchange (ETDEWEB)

Konstantinou, G.; Ali, W.; Chil, R.; Cossu, G.; Ciaramella, E.; Vaquero, J.J.

2016-07-01

We present the design and development of a positron emission tomography (PET) detector module that could be used inside magnetic resonance imager (MRI). Critical factors compromising this combination have been studied and different solutions have been offered. Our design divides the detector module in two sections: one is the insert front-end that is placed inside the MRI and that comprises of a scintillator, a silicon photomultiplier and minimum analog electronics. The analog pulses are sent to the second section, the back-end digitalization and reconstruction module. The analog link is implemented using optical wireless communication (OWC) techniques. In this work we study how such a setting retains all the necessary characteristics for the detection and characterization of gamma scintillation events, providing sufficient communication quality with low consumption and minimizing the need for space. Possible multiplexing schemes for achieving the necessary transmission with less communication channels are also proposed and studied. A series of tests and measurements on different settings demonstrate the viability of this technique. When fully developed, it can provide a cost effective alternative for the industrial production of a flexible and customizable modular PET detector insert that can be applied to pre-existing small animal or human MRI settings, only minimally affecting the size of the MRI bore, without compromising the PET signal quality. (Author)

The Front End Electronics of the Scintillator Pad Detector of LHCb Calorimeter

CERN Document Server

Gascon, David; Bota, S; Comerma, A; Diéguez, A; Garrido, L; Gaspar, A; Graciani, R; Graciani, E; Herms, A; Llorens, M; Luengo, S; Picatoste, E; Riera, J; Rosselló, M; Ruiz, H; Tortella, S; Vilasís, X

2007-01-01

In this paper the Front End electronics of the Scintillator Pad Detector (SPD) is outlined. The SPD is a sub-system of the Calorimeter of the LHCb experiment designed to discriminate between charged and neutral particles for the first level trigger. The system design is presented, describing its different functionalities implemented through three different cards and several ASICs. These functionalities are signal processing and digitization, data transmission, interface with control and timing systems of the experiment, low voltage power supply distribution and monitoring. Special emphasis is placed on installation and commissioning subjects such as cabling, grounding, shielding and power distribution.

Front-end electronics for the readout of CdZnTe sensors

CERN Document Server

Moraes, D; Rudge, A

2006-01-01

The CERN_DxCTA is a front-end ASIC optimized for the readout of CdZn Te sensors. The chip is implemented in 0.25 mum CMOS technology. The circuit consists of 128 channels equipped with a transimpedance amplifier followed by a gain-shaper stage with 20 ns peaking time and two discriminators, allowing two threshold settings. Each discriminator includes a 5-bit trim DAC and is followed by an 18-bit static ripple-counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at counting rates of up to 5 M counts/second. Complete evaluation of the circuit is presented using electronic pulses and Cd ZnTe pixel detectors.

A segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics for a PET scanner

CERN Document Server

Chesi, Enrico Guido; Joram, C; Mathot, S; Séguinot, Jacques; Weilhammer, P; Ciocia, F; De Leo, R; Nappi, E; Vilardi, I; Argentieri, A; Corsi, F; Dragone, A; Pasqua, D

2006-01-01

We describe the design, fabrication and test results of a segmented Hybrid Photon Detector with integrated auto-triggering front-end electronics. Both the photodetector and its VLSI readout electronics are custom designed and have been tailored to the requirements of a recently proposed novel geometrical concept of a Positron Emission Tomograph. Emphasis is put on the PET specific features of the device. The detector has been fabricated in the photocathode facility at CERN.

Detector and Front-end electronics for ALICE and STAR silicon strip layers

CERN Document Server

Arnold, L; Coffin, J P; Guillaume, G; Higueret, S; Jundt, F; Kühn, C E; Lutz, Jean Robert; Suire, C; Tarchini, A; Berst, D; Blondé, J P; Clauss, G; Colledani, C; Deptuch, G; Dulinski, W; Hu, Y; Hébrard, L; Kucewicz, W; Boucham, A; Bouvier, S; Ravel, O; Retière, F

1998-01-01

Detector modules consisting of Silicon Strip Detector (SSD) and Front End Electronics (FEE) assembly have been designed in order to provide the two outer layers of the ALICE Inner Tracker System (ITS) [1] as well as the outer layer of the STAR Silicon Vertex Tracker (SVT) [2]. Several prototypes have beenproduced and tested in the SPS and PS beam at CERN to validate the final design. Double-sided, AC-coupled SSD detectors provided by two different manufacturers and also a pair of single-sided SSD have been asssociated to new low-power CMOS ALICE128C ASIC chips in a new detector module assembly. The same detectors have also been associated to current Viking electronics for reference purpose. These prototype detector modules are described and some first results are presented.

LANSCE-R WIRE-SCANNER ANALOG FRONT-END ELECTRONICS

International Nuclear Information System (INIS)

Gruchalla, Michael E.

2011-01-01

A new AFE is being developed for the new LANSCE-R wire-scanner systems. The new AFE is implemented in a National Instruments Compact RIO (cRIO) module installed a BiRa 4U BiRIO cRIO chassis specifically designed to accommodate the cRIO crate and all the wire-scanner interface, control and motor-drive electronics. A single AFE module provides interface to both X and Y wire sensors using true DC coupled transimpedance amplifiers providing collection of the wire charge signals, real-time wire integrity verification using the normal dataacquisition system, and wire bias of 0V to +/-50V. The AFE system is designed to accommodate comparatively long macropulses (>1ms) with high PRF (>120Hz) without the need to provide timing signals. The basic AFE bandwidth is flat from true DC to 50kHz with a true first-order pole at 50kHz. Numeric integration in the cRIO FPGA provides real-time pulse-to-pulse numeric integration of the AFE signal to compute the total charge collected in each macropulse. This method of charge collection eliminates the need to provide synchronization signals to the wire-scanner AFE while providing the capability to accurately record the charge from long macropulses at high PRF.

Design of a new front-end electronics test-bench for the upgraded ATLAS detector's Tile Calorimeter

International Nuclear Information System (INIS)

Kureba, C O; Govender, M; Hofsajer, I; Ruan, X; Sandrock, C; Spoor, M

2015-01-01

The year 2022 has been scheduled to see an upgrade of the Large Hadron Collider (LHC), in order to increase its instantaneous luminosity. The High Luminosity LHC, also referred to as the upgrade Phase-II, means an inevitable complete re-design of the read-out electronics in the Tile Calorimeter (TileCal) of the A Toroidal LHC Apparatus (ATLAS) detector. Here, the new read-out architecture is expected to have the front-end electronics transmit fully digitized information of the detector to the back-end electronics system. Fully digitized signals will allow more sophisticated reconstruction algorithms which will contribute to the required improved triggers at high pile-up. In Phase II, the current Mobile Drawer Integrity ChecKing (MobiDICK) test-bench will be replaced by the next generation test-bench for the TileCal superdrawers, the new Prometeo (A Portable ReadOut ModulE for Tilecal ElectrOnics). Prometeo is a portable, high-throughput electronic system for full certification of the front-end electronics of the ATLAS TileCal. It is designed to interface to the fast links and perform a series of tests on the data to assess the certification of the electronics. The Prometeo's prototype is being assembled by the University of the Witwatersrand and installed at CERN for further developing, tuning and tests. This article describes the overall design of the new Prometeo, and how it fits into the TileCal electronics upgrade. (paper)

Microwave Photonic Architecture for Direction Finding of LPI Emitters: Front End Analog Circuit Design and Component Characterization

Science.gov (United States)

2016-09-01

into two parts. The design, development, and testing efforts of the front-end microwave photonics circuit design and the system integration with the...miniature microwave - photonic phase-sampling DF technique is investigated in this thesis. This front-end design uses a combination of integrated optical...NAVAL POSTGRADUATE SCHOOL MONTEREY, CALIFORNIA THESIS Approved for public release. Distribution is unlimited. MICROWAVE

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

CERN Document Server

Schreuder, Frans Philip; The ATLAS collaboration

2018-01-01

Starting during the upcoming major LHC shutdown (2019-2021), the ATLAS experiment at CERN will move to the Front-End Link eXchange (FELIX) system as the interface between the data acquisition system and the trigger and detector front-end electronics. FELIX will function as a router between custom serial links and a commodity switch network, which will use industry standard technologies to communicate with data collection and processing components. This presentation will describe the FELIX system design as well as reporting on results of the ongoing development program.

The CBM Experiment at FAIR-New challenges for Front-End Electronics, Data Acquisition and Trigger Systems

International Nuclear Information System (INIS)

Mueller, Walter F J

2006-01-01

The 'Compressed Baryonic Matter' (CBM) experiment at the new 'Facility for Antiproton and Ion Research' (FAIR) in Darmstadt is designed to study the properties of highly compressed baryonic matter produced in nucleus-nucleus collisions in the 10 to 45 A GeV energy range. One of the key observables is hidden (J/ψ) and open (D 0 , D ± ) charm production. To achieve an adequate sensitivity extremely high interaction rates of up to 10 7 events/second are required, resulting in major technological challenges for the detectors, front-end electronics and data processing. The front-end electronics will be self-triggered, autonomously detect particle hits, and output hit parameter together with a precise absolute time-stamp. Several layers of feature extraction and event selection will reduce the primary data flow of about 1 TByte/sec to a level of 1 GByte/sec. This new architecture avoids many limitations of conventional DAQ/Trigger systems and is for example essential for open charm detection, which requires the reconstruction of displaced vertices, in a high-rate heavy ion environment

Front end electronics and first results of the ALICE V0 detector

Energy Technology Data Exchange (ETDEWEB)

Zoccarato, Y., E-mail: y.zoccarato@ipnl.in2p3.f [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Tromeur, W. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Aguilar, S.; Alfaro, R.; Almaraz Avina, E.; Anzo, A.; Belmont, E. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Cheshkov, C.; Cheynis, B.; Combaret, C. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Contreras, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Cuautle, E. [Instituto de Ciencias Nucleares, Universidad Nacional Autonoma de Mexico, Circuito Exterior s/n, Ciudad Universitaria. Delg. Coyoacan, C.P. 04510, Mexico, D.F. (Mexico); Ducroux, L. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Gonzalez Trueba, L.; Grabski, V. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico); Grossiord, J.-Y. [Universite de Lyon, Universite Lyon 1, CNRS/IN2P3, Institut de Physique Nucleaire de Lyon (IPNL), 69622 Villeurbanne (France); Herrera Corral, G. [Centro de Investigacion y de Estudios Avanzados (CINVESTAV), Av. Instituto Politecnico Nacional 2508 Col. San Pedro Zacatenco, C.P. 07360, Mexico, D.F. (Mexico); Martinez, A. [Instituto de Fisica, Universidad Nacional Autonoma de Mexico, Circuito de la Investigacion Cientifica Ciudad Universitaria, C.P. 04510, Mexico, D.F. (Mexico)

2011-01-21

This paper gives a detailed description of the acquisition and trigger electronics especially designed for the V0 detector of ALICE at LHC. A short presentation of the detector itself is given before the description of the Front End Electronics (FEE) system, which is completely embedded within the LHC environment as far as acquisition (DAQ), trigger (CTP), and detector control (DCS) are concerned. It is able to detect on-line coincident events and to achieve charge (with a precision of 0.6 pC) and time measurements (with a precision of 100 ps). It deploys quite a simple architecture. It is however totally programmable and fully non-standard in discriminating events coming from Beam-Beam interaction and Beam-Gas background. Finally, raw data collected from the first LHC colliding beams illustrate the performance of the system.

Hybrid circuit prototypes for the CMS Tracker upgrade front-end electronics

International Nuclear Information System (INIS)

Blanchot, G; Honma, A; Kovacs, M; Braga, D; Raymond, M

2013-01-01

New high-density interconnect hybrid circuits are under development for the CMS tracker modules at the HL-LHC. These hybrids will provide module connectivity between flip-chip front-end ASICs, strip sensors and a service board for the data transmission and powering. Rigid organic-based substrate prototypes and also a flexible hybrid design have been built, containing up to eight front-end flip chip ASICs. A description of the function of the hybrid circuit in the tracker, the first prototype designs, results of some electrical and mechanical properties from the prototypes, and examples of the integration of the hybrids into detector modules are presented

The LHCb front-end electronics and data acquisition system

CERN Document Server

Jost, B

2000-01-01

The LHCb experiment is the most recently approved of the four experiments under construction at CERN's LHC accelerator. It is a special purpose experiment designed to precisely measure the CP violation parameters in the B-B system and to study rare B-decays. Triggering poses special problems since the interesting events containing B-mesons are immersed in a large background of inelastic p-p reactions. We therefore decided to implement a four-level triggering scheme. The LHCb data acquisition (DAQ) system will have to cope with an average trigger rate of 40 kHz, after two levels of hardware triggers, and an average event size of 100 kB. Thus, an event-building network which can sustain an average bandwidth of 4 GB /s is required. A powerful software trigger farm will have to be installed to reduce the rate from 40 kHz to 100 Hz of events written for permanent storage. In this paper we will outline the general architectures of the front-end electronics and of the trigger and DAQ system and the readout protocols...

Detector and front-end electronics of a fissile mass flow monitoring system

International Nuclear Information System (INIS)

Paulus, M.J.; Uckan, T.; Lenarduzzi, R.; Mullens, J.A.; Castleberry, K.N.; McMillan, D.E.; Mihalczo, J.T.

1997-01-01

A detector and front-end electronics unit with secure data transmission has been designed and implemented for a fissile mass flow monitoring system for fissile mass flow of gases and liquids in a pipe. The unit consists of 4 bismuth germanate (BGO) scintillation detectors, pulse-shaping and counting electronics, local temperature sensors, and on-board local area network nodes which locally acquire data and report to the master computer via a secure network link. The signal gain of the pulse-shaping circuitry and energy windows of the pulse-counting circuitry are periodicially self calibrated and self adjusted in situ using a characteristic line in the fissile material pulse height spectrum as a reference point to compensate for drift such as in the detector gain due to PM tube aging. The temperature- dependent signal amplitude variations due to the intrinsic temperature coefficients of the PM tube gain and BGO scintillation efficiency have been characterized and real-time gain corrections introduced. The detector and electronics design, measured intrinsic performance of the detectors and electronics, and the performance of the detector and electronics within the fissile mass flow monitoring system are described

Compact Front-end Prototype for Next Generation RFI-rejecting Polarimetric L-band Radiometer

DEFF Research Database (Denmark)

Jensen, Brian Sveistrup; Søbjærg, Sten Schmidl; Skou, Niels

2009-01-01

Realizing the need for lower noise figure and smaller physical size in todays higly sensitive radiometers, this paper presents a new compact analog front-end (AFE) for use with the existing L-band (1400-1427 MHz) radiometer designed and operated by the Technical University of Denmark. Using subha...

A Real Time Electronics Emulator with Realistic Data Generation for Reception Tests of the CMS ECAL Front-End Boards

CERN Document Server

Romanteau, T; Collard, Caroline; Debraine, A; Decotigny, D; Dobrzynski, L; Karar, A; Regnault, N

2005-01-01

The CMS [1] electromagnetic calorimeter (ECAL) [2] uses 3 132 Front-End boards (FE) performing both trigger and data readout functions. Prior to their integration at CERN, the FE boards have to be validated by dedicated test bench systems. The final one, called "XFEST" (eXtended Front-End System Test) and for which the present developments have been performed, is located at Laboratoire Leprince-Ringuet. In this contribution, a solution is described to efficiently test a large set of complex electronics boards characterized by a large number of input ports and a high throughput data rate. To perform it, an algorithm to simulate the Very Front End signals has been emulated. The project firmwares use VHDL embedded into XILINX Field Programmable Gate Array circuits (FPGA). This contribution describes the solutions developed in order to create a realistic digital input patterns real-time emul ator working at 40 MHz. The implementation of a real time comparison of the FE output streams as well as the test bench wil...

The DIALOG Chip in the Front-End Electronics of the LHCb Muon Detector

CERN Document Server

Cadeddu, S; Lai, A

2004-01-01

We present a custom integrated circuit, named DIALOG, which is a fundamental building block in the front-end architecture of the LHCb Muon detector. DIALOG is realized in IBM 0.25 um technology, using radiation hardening layout techniques. DIALOG integrates important tools for detector time alignment procedures and time alignment monitoring on the front- end system. In particular, it integrates 16 programmable delays, which can be regulated in steps of 1 ns. Many other features, necessary for the Muon trigger operation and for a safe front-end monitoring are integrated: DIALOG generates the information used by the trigger as a combination of its 16 inputs from the Amplifier-Shaper-Discriminator (ASD) chips, it generates the thresholds of the ASD, it monitors the rate of all its input channels. We describe the circuit architecture, its internal blocks and its main modes of operation.

A digital Front-End and Readout MIcrosystem for calorimetry at LHC

CERN Multimedia

2002-01-01

% RD-16 A Digital Front-End and Readout Microsystem for Calorimetry at LHC \\\\ \\\\Front-end signal processing for calorimetric detectors is essential in order to achieve adequate selectivity in the trigger function of an LHC experiment, with data identification and compaction before readout being required in the harsh, high rate environment of a high luminosity hadron machine. Other crucial considerations are the extremely wide dynamic range and bandwidth requirements, as well as the volume of data to be transferred to following stages of the trigger and readout system. These requirements are best met by an early digitalization of the detector information, followed by integrated digital signal processing and buffering functions covering the trigger latencies.\\\\ \\\\The FERMI (Front-End Readout MIcrosystem) is a digital implementation of the front-end and readout electronic chain for calorimeters. It is based on dynamic range compression, high speed A to D converters, a fully programmable pipeline/digital filter c...

System-Level Design of an Integrated Receiver Front End for a Wireless Ultrasound Probe

DEFF Research Database (Denmark)

di Ianni, Tommaso; Hemmsen, Martin Christian; Llimos Muntal, Pere

2016-01-01

In this paper, a system-level design is presented for an integrated receive circuit for a wireless ultrasound probe, which includes analog front ends and beamformation modules. This paper focuses on the investigation of the effects of architectural design choices on the image quality. The point...

FELIX: a High-Throughput Network Approach for Interfacing to Front End Electronics for ATLAS Upgrades

International Nuclear Information System (INIS)

Anderson, J; Drake, G; Ryu, S; Zhang, J; Borga, A; Boterenbrood, H; Schreuder, F; Vermeulen, J; Chen, H; Chen, K; Lanni, F; Francis, D; Gorini, B; Miotto, G Lehmann; Schumacher, J; Vandelli, W; Levinson, L; Narevicius, J; Roich, A; Plessl, C

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified optical link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates up to 10.24 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. A new class of devices will be needed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper FELIX (Front End LInk eXchange) is presented, a PC-based device to route data from and to multiple GBT links via a high-performance general purpose network capable of a total throughput up to O(20 Tbps). FELIX implies architectural changes to the ATLAS data acquisition system, such as the use of industry standard COTS components early in the DAQ chain. Additionally the design and implementation of a FELIX demonstration platform is presented and hardware and software aspects will be discussed. (paper)

The Front-End Electronics for the HADES RPC Wall (ESTRELA-FEE)

International Nuclear Information System (INIS)

Belver, D.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Lange, S.; Marin, J.; Montes, N.; Skott, P.; Traxler, M.; Zapata, M.

2006-01-01

A new front-end electronics (FEE) system for RPC timing measurements has been developed for the ESTRELA project, which is part of the upgrade of the HADES experiment at GSI. The RPCs will cover an area of 8 m 2 with 2048 electronic channels. The chain consists on 2 boards: a 4-channel daughterboard (DB) and a 32-channel motherboard (MB). The DB uses a fast 2 GHz amplifier that feeds a discriminator with a constant threshold and an operational amplifier for a charge measurement by a Time-Over-Threshold (ToT) method for the integrated signal (for a slewing correction). The MB is connected to 8 DB, and provides voltage regulation, DACs for signal thresholds and a trigger logic. The MB delivers the differential output signals to an external HPTDC chip. Results are presented for (a) narrow electronic test pulses and for (b) RPC signals from gamma photons, showing a timing jitter around 15 ps/channel (for pulses above 100 fC) and 30-40 ps/channel, respectively. Tests with coincidently firing channels reveal levels of cross-talk below a 1% for a threshold of 25 fC, with a degradation of the time resolution of 10 ps at most

MUON POLARIZATION EFFECTS IN THE FRONT END OF THE NEUTRINO FACTORY

International Nuclear Information System (INIS)

FERNOW, R.C.; GALLARDO, J.C.; FUKUI, Y.

2000-01-01

The authors summarize the methods used for simulation of polarization effects in the front end of a possible neutrino factory. They first discuss the helicity of muons in the pion decay process. They find that, neglecting acceptance considerations, the average helicity asymptotically approaches a magnitude of 0.185 at large pion momenta. Next they describe the methods used for tracking the spin through the complicated electromagnetic field configurations in the front end of the neutrino factory, including rf phase rotation and ionization cooling channels. Various depolarizing effects in matter are then considered, including multiple Coulomb scattering and elastic scattering from atomic electrons. Finally, they include all these effects in a simulation of a 480 m long, double phase rotation front end scenario

ASIC Wafer Test System for the ATLAS Semiconductor Tracker Front-End Chip

International Nuclear Information System (INIS)

Anghinolfi, F.; Bialas, W.; Busek, N.; Ciocio, A.; Cosgrove, D.; Fadeyev, V.; Flacco, C.; Gilchriese, M.; Grillo, A.A.; Haber, C.; Kaplon, J.; Lacasta, C.; Murray, W.; Niggli, H.; Pritchard, T.; Rosenbaum, F.; Spieler, H.; Stezelberger, T.; Vu, C.; Wilder, M.; Yaver, H.; Zetti, F.

2002-01-01

An ASIC wafer test system has been developed to provide comprehensive production screening of the ATLAS Semiconductor Tracker front-end chip (ABCD3T). The ABCD3T[1] features a 128-channel analog front-end, a digital pipeline, and communication circuitry, clocked at 40 MHz, which is the bunch crossing frequency at the LHC (Large Hadron Collider). The tester measures values and tolerance ranges of all critical IC parameters, including DC parameters, electronic noise, time resolution, clock levels and clock timing. The tester is controlled by an FPGA (ORCA3T) programmed to issue the input commands to the IC and to interpret the output data. This allows the high-speed wafer-level IC testing necessary to meet the production schedule. To characterize signal amplitudes and phase margins, the tester utilizes pin-driver, delay, and DAC chips, which control the amplitudes and delays of signals sent to the IC under test. Output signals from the IC under test go through window comparator chips to measure their levels. A probe card has been designed specifically to reduce pick-up noise that can affect the measurements. The system can operate at frequencies up to 100 MHz to study the speed limits of the digital circuitry before and after radiation damage. Testing requirements and design solutions are presented

Performance evaluation of the analogue front-end and ADC prototypes for the Gotthard-II development

Science.gov (United States)

Zhang, J.; Andrä, M.; Barten, R.; Bergamaschi, A.; Brückner, M.; Dinapoli, R.; Fröjdh, E.; Greiffenberg, D.; Lopez-Cuenca, C.; Mezza, D.; Mozzanica, A.; Ramilli, M.; Redford, S.; Ruat, M.; Ruder, C.; Schmitt, B.; Shi, X.; Thattil, D.; Tinti, G.; Turcato, M.; Vetter, S.

2017-12-01

Gotthard-II is a silicon microstrip detector developed for the European X-ray Free-Electron Laser (XFEL.EU). Its potential scientific applications include X-ray absorption/emission spectroscopy, hard X-ray high resolution single-shot spectrometry (HiREX), energy dispersive experiments at 4.5 MHz frame rate, beam diagnostics, as well as veto signal generation for pixel detectors. Gotthard-II uses a silicon microstrip sensor with a pitch of 50 μm or 25 μm and with 1280 or 2560 channels wire-bonded to readout chips (ROCs). In the ROC, an adaptive gain switching pre-amplifier (PRE), a fully differential Correlated-Double-Sampling (CDS) stage, an Analog-to-Digital Converter (ADC) as well as a Static Random-Access Memory (SRAM) capable of storing all the 2700 images in an XFEL.EU bunch train will be implemented. Several prototypes with different designs of the analogue front-end (PRE and CDS) and ADC test structures have been fabricated in UMC-110 nm CMOS technology and their performance has been evaluated. In this paper, the performance of the analogue front-end and ADC will be summarized.

MMIC front-ends for optical communication systems

DEFF Research Database (Denmark)

Petersen, Anders Kongstad

1993-01-01

Two different types of optical front-end MMIC amplifiers for a 2.5-Gb/s coherent heterodyne optical receiver are presented. A bandwidth of 6-12 GHz has been obtained for a tuned front-end and 3-13 GHz for a distributed front-end. An input noise current density of 5-15 pA/√Hz has been obtained for...

Towards new analog read-out electronics for the HADES drift chamber system

Energy Technology Data Exchange (ETDEWEB)

Wiebusch, Michael [Goethe-Universitaet, Frankfurt (Germany); Collaboration: HADES-Collaboration

2016-07-01

Track reconstruction in HADES is realized with 24 planar, low-mass drift chambers (MDC). About 27000 drift cells provide precise spatial information of track hit points together with energy loss information, serving for particle ID. In order to handle high rates and track densities required at the future SIS100 accelerator at FAIR, an upgrade of the MDC system is necessary, i.e. by receiving additional redundant layers of drift cells in front of the magnet. This involves new front-end electronics, as the original analog read-out ASIC (ASD8) is no longer in stock and cannot be produced due to its legacy silicon process. Employing new FEE would allow to further increase the sensitivity, e.g. providing additional valuable information for the analysis. This contribution presents a market analysis of alternative state-of-the-art technologies for the analog read-out of drift chambers. Test procedures to evaluate the suitability for the HADES MDCs are discussed and preliminary results are shown. Emphasis is put on the benefits and possible implementations of using two separate analog channels for reading out a sense wire, i.e. a fast amplifier with a discriminator for recording the arrival time of the signal pulse and a slow integrating amplifier with a time-over-threshold discriminator to measure the total charge of the pulse.

Actuation stability test of the LISA pathfinder inertial sensor front-end electronics

Science.gov (United States)

Mance, Davor; Gan, Li; Weber, Bill; Weber, Franz; Zweifel, Peter

In order to limit the residual stray forces on the inertial sensor test mass in LISA pathfinder, √ it is required that the fluctuation of the test mass actuation voltage is within 2ppm/ Hz. The actuation voltage stability test on the flight hardware of the inertial sensor front-end electronics (IS FEE) is presented in this paper. This test is completed during the inertial sensor integration at EADS Astrium Friedrichshafen, Germany. The standard measurement method using voltmeter is not sufficient for verification, since the instrument low frequency √ fluctuation is higher than the 2ppm/ Hz requirement. In this test, by using the differential measurement method and the lock-in amplifier, the actuation stability performance is verified and the quality of the IS FEE hardware is confirmed by the test results.

Muon front end for the neutrino factory

CERN Document Server

Rogers, C T; Prior, G; Gilardoni, S; Neuffer, D; Snopok, P; Alekou, A; Pasternak, J

2013-01-01

In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

A software-radio front-end for microwave applications

Directory of Open Access Journals (Sweden)

M. Streifinger

2003-01-01

Full Text Available In modern communication, sensor and signal processing systems digitisation methods are gaining importance. They allow for building software configurable systems and provide better stability and reproducibility. Moreover digital front-ends cover a wider range of applications and have better performance compared with analog ones. The quest for new architectures in radio frequency front-ends is a clear consequence of the ever increasing number of different standards and the resulting task to provide a platform which covers as many standards as possible. At microwave frequencies, in particular at frequencies beyond 10 GHz, no direct sampling receivers are available yet. A look at the roadmap of the development of commercial analog-to-digital-converters (ADC shows clearly, that they can neither be expected in near future. We present a novel architecture, which is capable of direct sampling of band-limited signals at frequencies beyond 10 GHz by means of an over-sampling technique. The wellknown Nyquist criterion states that wide-band digitisation of an RF-signal with a maximum frequency ƒ requires a minimum sampling rate of 2 · ƒ . But for a band-limited signal of bandwidth B the demands for the minimum sampling rate of the ADC relax to the value 2 · B. Employing a noise-forming sigma-delta ADC architecture even with a 1-bit-ADC a signal-to-noise ratio sufficient for many applications can be achieved. The key component of this architecture is the sample-and-hold switch. The required bandwidth of this switch must be well above 2 · ƒ . We designed, fabricated and characterized a preliminary demonstrator for the ISM-band at 2.4 GHz employing silicon Schottky diodes as a switch and SiGe-based MMICs as impedance transformers and comparators. Simulated and measured results will be presented.

Muon front end for the neutrino factory

Directory of Open Access Journals (Sweden)

C. T. Rogers

2013-04-01

Full Text Available In the neutrino factory, muons are produced by firing high-energy protons onto a target to produce pions. The pions decay to muons and pass through a capture channel known as the muon front end, before acceleration to 12.6 GeV. The muon front end comprises a variable frequency rf system for longitudinal capture and an ionization cooling channel. In this paper we detail recent improvements in the design of the muon front end.

Feedback from operational experience in front-end transportation

International Nuclear Information System (INIS)

Mondonel, J.L.; Parison, C.

1998-01-01

Transport forms an integral part of the nuclear fuel cycle, representing the strategic link between each stage of the cycle. In a way there is a transport cycle that parallels the nuclear fuel cycle. This concerns particularly the front-end of the cycle whose steps - mining conversion, enrichment and fuel fabrication - require numerous transports. Back-end shipments involve a handful of countries, but front-end transports involve all five continents, and many exotic countries. All over Europe such transports are routinely performed with an excellent safety track record. Transnucleaire dominates the French nuclear transportation market and carries out both front and back-end transports. For instance in 1996 more than 28,400 front-end packages were transported as well as more than 3,600 back-end packages. However front-end transport is now a business undergoing much change. A nuclear transportation company must now cope with an evolving picture including new technical requirements, new transportation schemes and new business conditions. This paper describes the latest evolutions in terms of front-end transportation and the way this activity is carried out by Transnucleaire, and goes on to discuss future prospects. (authors)

A low-power current-reuse dual-band analog front-end for multi-channel neural signal recording.

Science.gov (United States)

Sepehrian, H; Gosselin, B

2014-01-01

Thoroughly studying the brain activity of freely moving subjects requires miniature data acquisition systems to measure and wirelessly transmit neural signals in real time. In this application, it is mandatory to simultaneously record the bioelectrical activity of a large number of neurons to gain a better knowledge of brain functions. However, due to limitations in transferring the entire raw data to a remote base station, employing dedicated data reduction techniques to extract the relevant part of neural signals is critical to decrease the amount of data to transfer. In this work, we present a new dual-band neural amplifier to separate the neuronal spike signals (SPK) and the local field potential (LFP) simultaneously in the analog domain, immediately after the pre-amplification stage. By separating these two bands right after the pre-amplification stage, it is possible to process LFP and SPK separately. As a result, the required dynamic range of the entire channel, which is determined by the signal-to-noise ratio of the SPK signal of larger bandwidth, can be relaxed. In this design, a new current-reuse low-power low-noise amplifier and a new dual-band filter that separates SPK and LFP while saving capacitors and pseudo resistors. A four-channel dual-band (SPK, LFP) analog front-end capable of simultaneously separating SPK and LFP is implemented in a TSMC 0.18 μm technology. Simulation results present a total power consumption per channel of 3.1 μw for an input referred noise of 3.28 μV and a NEF for 2.07. The cutoff frequency of the LFP band is fc=280 Hz, and fL=725 Hz and fL=11.2 KHz for SPK, with 36 dB gain for LFP band 46 dB gain for SPK band.

Performance of the front-end electronics of the ANTARES neutrino telescope

NARCIS (Netherlands)

Aguilar, J. A.; Al Samarai, I.; Albert, A.; Anghinolfi, M.; Anton, G.; Anvar, S.; Ardid, M.; Jesus, A. C. Assis; Astraatmadja, T.; Aubert, J-J; Auer, R.; Baret, B.; Basa, S.; Bazzotti, M.; Bertin, V.; Biagi, S.; Bigongiari, C.; Bou-Cabo, M.; Bouwhuis, M. C.; Brown, A.; Brunner, J.; Busto, J.; Camarena, F.; Capone, A.; Caponetto, L.; Carloganu, C.; Carminati, G.; Carr, J.; Castorina, E.; Cavasinni, V.; Cecchini, S.; Chaleil, Th; Charvis, [No Value; Chiarusi, T.; Sen, N. Chon; Circella, M.; Costantini, H.; Cottini, N.; Coyle, P.; Curtil, C.; De Bonis, G.; de Botton, N.; Dekeyser, I.; Delagnes, E.; Deschamps, A.; Distefano, C.; Donzaud, C.; Dornic, D.; Drouhin, D.; Druillole, F.; Eberl, T.; Emanuele, U.; Ernenwein, J-P; Escoffier, S.; Falchini, E.; Fehr, F.; Feinstein, F.; Flaminio, V.; Fopma, J.; Fratini, K.; Fritsch, U.; Fuda, J-L; Gay, P.; Giacomelli, G.; Gomez-Gonzalez, J. P.; Graf, K.; Guillard, G.; Halladjian, G.; Hallewell, G.; Hoffmann, C.; van Haren, H.; Heijboer, A. J.; Hello, Y.; Hernandez-Rey, J. J.; Herold, B.; Hoessl, J.; de Jong, M.; Kalantar-Nayestanaki, N.; Kalekin, O.; Kappes, A.; Katz, U.; Kooijman, P.; Kopper, C.; Kouchner, A.; Kretschmer, W.; Lachartre, D.; Lafoux, H.; Lahmann, R.; Lamare, P.; Lambard, G.; Larosa, G.; Laschinsky, H.; Le Provost, H.; Le Van Suu, A.; Lefevre, D.; Legou, T.; Lelaizant, G.; Lim, G.; Lo Presti, D.; Loehner, H.; Loucatos, S.; Lucarelli, F.; Mangano, S.; Marcelin, M.; Margiotta, A.; Martinez-Mora, J. A.; Mazure, A.; Monmarthe, E.; Montaruli, T.; Morganti, M.; Moscoso, L.; Motz, H.; Naumann, C.; Neff, M.; Olivetto, Ch; Ostasch, R.; Palioselitis, D.; Pavala, G. E.; Payre, P.; Petrovic, J.; Piattelli, P.; Picot-Clemente, N.; Picq, C.; Pineau, J-P; Poinsignon, J.; Popa, V.; Pradier, T.; Presani, E.; Racca, C.; Radu, A.; Reed, C.; Rethore, F.; Riccobene, G.; Richardt, C.; Rujoiu, M.; Russo, G. V.; Salesa, F.; Sapienza, P.; Schoeck, F.; Schuller, J. P.; Shanidze, R.; Simeone, F.; Spurio, M.; Steijger, J. J. M.; Stolarczyk, Th.; Tamburini, C.; Tasca, L.; Toscano, S.; Vallage, B.; Van Elewyck, V.; Vannoni, G.; Vecchi, M.; Vernin, P.; Wijnker, G.; de Wolf, E.; Yepes, H.; Zaborov, D.; Zornoza, J. D.; Zuniga, J.

2010-01-01

ANTARES is a high-energy neutrino telescope installed in the Mediterranean Sea at a depth of 2475 m. It consists of a three-dimensional array of optical modules, each containing a large photomultiplier tube. A total of 2700 front-end ASICs named analogue ring samplers (ARS) process the phototube

A Time-Based Front End Readout System for PET & CT

CERN Document Server

Meyer, T C; Anghinolfi, F; Auffray, E; Dosanjh, M; Hillemanns, H; Hoffmann, H -F; Jarron, P; Kaplon, J; Kronberger, M; Lecoq, P; Moraes, D; Trummer, J

2007-01-01

In the framework of the European FP6's BioCare project, we develop a novel, time-based, photo-detector readout technique to increase sensitivity and timing precision for molecular imaging in PET and CT. The project aims to employ Avalanche Photo Diode (APD) arrays with state of the art, high speed, front end amplifiers and discrimination circuits developed for the Large Hadron Collider (LHC) physics program at CERN, suitable to detect and process photons in a combined one-unit PET/CT detection head. In the so-called time-based approach our efforts focus on the system's timing performance with sub-nanosecond time-jitter and -walk, and yet also provide information on photon energy without resorting to analog to digital conversion. The bandwidth of the electronic circuitry is compatible with the scintillator's intrinsic light response (e.g. les40ns in LSO) and hence allows high rate CT operation in single-photon counting mode. Based on commercial LSO crystals and Hamamatsu S8550 APD arrays, we show the system pe...

The front-end data conversion and readout electronics for the CMS ECAL upgrade

CERN Document Server

Mazza, Gianni

2017-01-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with 13 bit resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

International Nuclear Information System (INIS)

Havranek, Miroslav

2014-09-01

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

Development of pixel front-end electronics using advanced deep submicron CMOS technologies

Energy Technology Data Exchange (ETDEWEB)

Havranek, Miroslav

2014-09-15

The content of this thesis is oriented on the R and D of microelectronic integrated circuits for processing the signal from particle sensors and partially on the sensors themselves. This work is motivated by ongoing upgrades of the ATLAS Pixel Detector at CERN laboratory and by exploration of new technologies for the future experiments in particle physics. Evolution of technologies for the fabrication of microelectronic circuits follows Moore's laws. Transistors become smaller and electronic chips reach higher complexity. Apart from this, silicon foundries become more open to smaller customers and often provide non-standard process options. Two new directions in pixel technologies are explored in this thesis: design of pixel electronics using ultra deep submicron (65 nm) CMOS technology and Depleted Monolithic Active Pixel Sensors (DMAPS). An independent project concerning the measurement of pixel capacitance with a dedicated measurement chip is a part of this thesis. Pixel capacitance is one of the key parameters for design of the pixel front-end electronics and thus it is closely related to the content of the thesis. The theoretical background, aspects of chip design, performance of chip prototypes and prospect for design of large pixel chips are comprehensively described in five chapters of the thesis.

45 Gb/s low complexity optical front-end for soft-decision LDPC decoders.

Science.gov (United States)

Sakib, Meer Nazmus; Moayedi, Monireh; Gross, Warren J; Liboiron-Ladouceur, Odile

2012-07-30

In this paper a low complexity and energy efficient 45 Gb/s soft-decision optical front-end to be used with soft-decision low-density parity-check (LDPC) decoders is demonstrated. The results show that the optical front-end exhibits a net coding gain of 7.06 and 9.62 dB for post forward error correction bit error rate of 10(-7) and 10(-12) for long block length LDPC(32768,26803) code. The performance over a hard decision front-end is 1.9 dB for this code. It is shown that the soft-decision circuit can also be used as a 2-bit flash type analog-to-digital converter (ADC), in conjunction with equalization schemes. At bit rate of 15 Gb/s using RS(255,239), LDPC(672,336), (672, 504), (672, 588), and (1440, 1344) used with a 6-tap finite impulse response (FIR) equalizer will result in optical power savings of 3, 5, 7, 9.5 and 10.5 dB, respectively. The 2-bit flash ADC consumes only 2.71 W at 32 GSamples/s. At 45 GSamples/s the power consumption is estimated to be 4.95 W.

Chapter 9: Electronics

International Nuclear Information System (INIS)

Grupen, Claus; Shwartz, Boris A.

2006-01-01

Sophisticated front-end electronics are a key part of practically all modern radiation detector systems. This chapter introduces the basic principles and their implementation. Topics include signal acquisition, electronic noise, pulse shaping (analog and digital), and data readout techniques

Analog data transmission via fiber optics

International Nuclear Information System (INIS)

Cisneros, E.L.; Burgueno, G.F.

1987-01-01

In the SLAC Linear Collider Detector (SLD), as in most high-energy particle detectors, the electromagnetic noise environment is the limiting factor in electronic readout performance. Front-end electronics are particularly susceptible to electromagnetic interference (EMI), and great care has been taken to minimize its effects. The transfer of preprocessed analog signals from the detector environs, to the remote digital processing electronics, by conventional means (via metal conductors), may ultimately limit the performance of the system. Because it is highly impervious to EMI and ground loops, a fiber-optic medium has been chosen for the transmission of these signals. This paper describes several fiber-optic transmission schemes which satisfy the requirements of the SLD analog data transmission

Analog data transmission via fiber optics

International Nuclear Information System (INIS)

Cisneros, E.L.; Burgueno, G.F.

1986-10-01

In the SLAC Linear Collider Detector (SLD), as in most high-energy particle detectors, the electromagnetic noise environment is the limiting factor in electronic readout performance. Front-end electronics are particulary susceptible to electromagnetic interference (EMI), and great care has been taken to minimize its effects. The transfer of preprocessed analog signals from the detector environs, to the remote digital processing electronics, by conventional means (via metal conductors), may ultimately limit the performance of the system. Because it is highly impervious to EMI and ground loops, a fiber-optic medium has been chosen for the transmission of these signals. This paper describes several fiber-optic transmission schemes which satisfy the requirements of the SLD analog data transmission

Design of a New Switching Power Supply for the ATLAS TileCal Front-End Electronics

CERN Document Server

Drake, Gary; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS Hadron Tile Calorimeter. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is in progress, and we present preliminary results from the production checkout.

Redesigned front end for the upgrade at CHESS

International Nuclear Information System (INIS)

Headrick, R.L.; Smolenski, K.W.

1996-01-01

We will report on beamline front-end upgrades for the 24-pole wiggler beamlines at CHESS. A new design for primary x-ray beamstops based on a tapered, water-cooled copper block has been implemented and installed in the CHESS F beamline. The design uses a horizontally tapered open-quote open-quote V close-quote close-quote shape to reduce the power density on the internal surfaces and internal water channels in the block to provide efficient water cooling. Upstream of the beam stops, we have installed a new photoelectron style beam position monitor with separate monitoring of the wiggler and dipole vertical beam positions and with micron-level sensitivity. The monitor close-quote s internal surfaces are designed to absorb the full x-ray power in case of beam missteering, and the uncooled photoelectron collecting plates are not visible to the x-ray beam. A graphite prefilter has been installed to protect the beryllium windows that separate the front end from the x-ray optics downstream. The redesigned front end is required by the upgrade of the Cornell storage ring, now in progress, which will allow stored electron and positron currents of 300 mA by 1996, and 500 mA by 1998. At 500 mA, the wiggler power output will be over 32 kW. copyright 1996 American Institute of Physics

A VLSI front-end circuit for microstrip silicon detectors for medical imaging applications

International Nuclear Information System (INIS)

Beccherle, R.; Cisternino, A.; Guerra, A. Del; Folli, M.; Marchesini, R.; Bisogni, M.G.; Ceccopieri, A.; Rosso, V.; Stefanini, A.; Tripiccione, R.; Kipnis, I.

1999-01-01

An analog CMOS-Integrated Circuit has been developed as Front-End for a double-sided microstrip silicon detector. The IC processes and discriminates signals in the 5-30 keV energy range. Main features are low noise and precise timing information. Low noise is achieved by optimizing the cascoded integrator with the 8 pF detector capacitance and by using an inherently low noise 1.2 μm CMOS technology. Timing information is provided by a double discriminator architecture. The output of the circuit is a digital pulse. The leading edge is determined by a fixed threshold discriminator, while the trailing edge is provided by a zero crossing discriminator. In this paper we first describe the architecture of the Front-End chip. We then present the performance of the chip prototype in terms of noise, minimum discrimination threshold and time resolution

A low-power high dynamic range front-end ASIC for imaging calorimeters

CERN Document Server

Bagliesi, M G; Marrocchesi, P S; Meucci, M; Millucci, V; Morsani, F; Paoletti, R; Pilo, F; Scribano, A; Turini, N; Valle, G D

2002-01-01

High granularity calorimeters with shower imaging capabilities require dedicated front-end electronics. The ICON 4CH and VA4 PMT chip-set is suitable for very high dynamic range systems with strict noise requirements. The ICON 4CH is a 4 channel input, 12 channel output ASIC designed for use in a multi-anode photomultiplier system with very large dynamic range and low-noise requirements. Each of the four input signals to the ASIC is split equally into three branches by a current conveyor. Each of the three branches is scaled differently: 1:1, 1:8 and 1:80. The signal is read out by a 12 channel low noise/low power high dynamic range charge sensitive preamplifier-shaper circuit (VA4-PMT chip), with simultaneous sample- and-hold, multiplexed analog read-out, calibration facilities. Tests performed in our lab with a PMT are reported in terms of linearity, dynamic range and cross-talk of the system. (5 refs).

The front-end data conversion and readout electronics for the CMS ECAL upgrade

Science.gov (United States)

Mazza, G.; Cometti, S.

2018-03-01

The High Luminosity LHC (HL-LHC) will require a significant upgrade of the readout electronics for the CMS Electromagnetic Calorimeter (ECAL). The Very Front-End (VFE) output signal will be sampled at 160 MS/s (i.e. four times the current sampling rate) with a 13 bits resolution. Therefore, a high-speed, high-resolution ADC is required. Moreover, each readout channel will produce 2.08 Gb/s, thus requiring a fast data transmission circuitry. A new readout architecture, based on two 12 bit, 160 MS/s ADCs, lossless data compression algorithms and fast serial links have been developed for the ECAL upgrade. These functions will be integrated in a single ASIC which is currently under design in a commercial CMOS 65 nm technology using radiation damage mitigation techniques.

Adaptive RF front-ends for hand-held applications

CERN Document Server

van Bezooijen, Andre; van Roermund, Arthur

2010-01-01

The RF front-end - antenna combination is a vital part of a mobile phone because its performance is very relevant to the link quality between hand-set and cellular network base-stations. The RF front-end performance suffers from changes in operating environment, like hand-effects, that are often unpredictable. ""Adaptive RF Front-Ends for Hand-Held Applications"" presents an analysis on the impact of fluctuating environmental parameters. In order to overcome undesired behavior two different adaptive control methods are treated that make RF frond-ends more resilient: adaptive impedance control,

Design of a New Switching Power Supply for the ATLAS TileCAL Front-End Electronics

CERN Document Server

Drake, G; The ATLAS collaboration

2012-01-01

We present the design of an upgraded switching power supply for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and improved reliability, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the steps taken to improve the design. We present the results from extensive radiation testing to qualify the design, including SEU sensitivity. We also present our reliability analysis. Production of 2400 new bricks for the detector is currently in progress, and we present preliminary results from the production checkout.

A Full Front End Chain for Drift Chambers

Energy Technology Data Exchange (ETDEWEB)

Chiarello, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Corvaglia, A.; Grancagnolo, F. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Panareo, M. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Pepino, A., E-mail: aurora.pepino@le.infn.it [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Università del Salento, Lecce (Italy); Primiceri, P. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Tassielli, G. [Istituto Nazionale di Fisica Nucleare, Lecce (Italy); Fermilab, Batavia, Illinois (United States); Università Marconi, Roma (Italy)

2014-03-01

We developed a high performance full chain for drift chamber signals processing. The Front End electronics is a multistage amplifier board based on high performance commercial devices. In addition a fast readout algorithm for Cluster Counting and Timing purposes has been implemented on a Xilinx-Virtex 4 core FPGA. The algorithm analyzes and stores data coming from a Helium based drift tube and represents the outcome of balancing between efficiency and high speed performance.

FELIX: A high-throughput network approach for interfacing to front end electronics for ATLAS upgrades

CERN Document Server

Anderson, John Thomas; The ATLAS collaboration; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Francis, David; Gorini, Benedetto; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Narevicius, Julia; Christian Plessl; Roich, Alexander; Schreuder, Frans Philip; Schumacher, Jorn; Vandelli, Wainer; Vermeulen, Jos; Zhang, Jinlong

2015-01-01

The ATLAS experiment at CERN is planning full deployment of a new unified link technology for connecting detector front end electronics on the timescale of the LHC Run 4 (2025). It is estimated that roughly 8000 GBT (GigaBit Transceiver) links, with transfer rates probably up to 9.6 Gbps, will replace existing links used for readout, detector control and distribution of timing and trigger information. In particular the links used for readout are often detector-specific. Already in Run 3 this technology will be deployed in conjunction with new muon detectors, additional muon first-level triggering electronics and new on-detector and off-detector liquid argon calorimeter electronics to be used for first level triggering. A total of roughly 2000 GBT links or GBT-like links (for connecting to off-detector trigger electronics) will be needed. A new class of devices will need to be developed to interface many GBT links to the rest of the trigger, data-acquisition and detector control systems. In this paper we prese...

Front-End ASICs for 3-D Ultrasound : From Beamforming to Digitization

NARCIS (Netherlands)

Chen, C.

2018-01-01

This thesis describes the analysis, design and evaluation of front-end application-specific integrated circuits (ASICs) for 3-D medical ultrasound imaging, with the focus on the receive electronics. They are specifically designed for next-generation miniature 3-D ultrasound devices, such as

Managing Controversies in the Fuzzy Front End

DEFF Research Database (Denmark)

Christiansen, John K.; Gasparin, Marta

2016-01-01

This research investigates the controversies that emerge in the fuzzy front end (FFE) and how they are closed so the innovation process can move on. The fuzzy front has been characterized in the literature as a very critical phase, but controversies in the FFE have not been studied before....... The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...

Front-End Electronics for Verification Measurements: Performance Evaluation and Viability of Advanced Tamper Indicating Measures

International Nuclear Information System (INIS)

Smith, E.; Conrad, R.; Morris, S.; Ramuhalli, P.; Sheen, D.; Schanfein, M.; Ianakiev, K.; Browne, M.; Svoboda, J.

2015-01-01

The International Atomic Energy Agency (IAEA) continues to expand its use of unattended, remotely monitored measurement systems. An increasing number of systems and an expanding family of instruments create challenges in terms of deployment efficiency and the implementation of data authentication measures. A collaboration between Pacific Northwest National Laboratory (PNNL), Idaho National Laboratory (INL), and Los Alamos National Laboratory (LANL) is working to advance the IAEA's capabilities in these areas. The first objective of the project is to perform a comprehensive evaluation of a prototype front-end electronics package, as specified by the IAEA and procured from a commercial vendor. This evaluation begins with an assessment against the IAEA's original technical specifications and expands to consider the strengths and limitations over a broad range of important parameters that include: sensor types, cable types, and the spectrum of industrial electromagnetic noise that can degrade signals from remotely located detectors. A second objective of the collaboration is to explore advanced tamper-indicating (TI) measures that could help to address some of the long-standing data authentication challenges with IAEA's unattended systems. The collaboration has defined high-priority tampering scenarios to consider (e.g., replacement of sensor, intrusion into cable), and drafted preliminary requirements for advanced TI measures. The collaborators are performing independent TI investigations of different candidate approaches: active time-domain reflectometry (PNNL), passive noise analysis (INL), and pulse-by-pulse analysis and correction (LANL). The initial investigations focus on scenarios where new TI measures are retrofitted into existing IAEA UMS deployments; subsequent work will consider the integration of advanced TI methods into new IAEA UMS deployments where the detector is separated from the front-end electronics. In this paper, project progress

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Document Server

Alessio, F; Gaspar, C; Jacobsson, R; Wyllie, K

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well.

A generic firmware core to drive the Front-End GBT-SCAs for the LHCb upgrade

International Nuclear Information System (INIS)

Alessio, F.; Gaspar, C.; Jacobsson, R.; Wyllie, K.; Caplan, C.

2015-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

Front-end receiver electronics for a matrix transducer for 3-D transesophageal echocardiography.

Science.gov (United States)

Yu, Zili; Blaak, Sandra; Chang, Zu-yao; Yao, Jiajian; Bosch, Johan G; Prins, Christian; Lancée, Charles T; de Jong, Nico; Pertijs, Michiel A P; Meijer, Gerard C M

2012-07-01

There is a clear clinical need for creating 3-D images of the heart. One promising technique is the use of transesophageal echocardiography (TEE). To enable 3-D TEE, we are developing a miniature ultrasound probe containing a matrix piezoelectric transducer with more than 2000 elements. Because a gastroscopic tube cannot accommodate the cables needed to connect all transducer elements directly to an imaging system, a major challenge is to locally reduce the number of channels, while maintaining a sufficient signal-to-noise ratio. This can be achieved by using front-end receiver electronics bonded to the transducers to provide appropriate signal conditioning in the tip of the probe. This paper presents the design of such electronics, realizing time-gain compensation (TGC) and micro-beamforming using simple, low-power circuits. Prototypes of TGC amplifiers and micro-beamforming cells have been fabricated in 0.35-μm CMOS technology. These prototype chips have been combined on a printed circuit board (PCB) to form an ultrasound-receiver system capable of reading and combining the signals of three transducer elements. Experimental results show that this design is a suitable candidate for 3-D TEE.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

Energy Technology Data Exchange (ETDEWEB)

Kasinski, K., E-mail: kasinski@agh.edu.pl [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Szczygiel, R. [AGH University of Science and Technology, Department of Measurement and Electronics, Av. Mickiewicza 30, 30-059 Cracow (Poland); Zabolotny, W. [Institute of Electronic Systems, Warsaw University of Technology, ul. Nowowiejska 15/19, 00-665 Warsaw (Poland); Lehnert, J.; Schmidt, C.J. [GSI Helmholtzzentrum für Schwerionenforschung GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany); Müller, W.F.J. [FAIR Facility for Antiproton and Ion Research in Europe GmbH, Planckstrasse 1, 64-291 Darmstadt (Germany)

2016-11-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

A protocol for hit and control synchronous transfer for the front-end electronics at the CBM experiment

International Nuclear Information System (INIS)

Kasinski, K.; Szczygiel, R.; Zabolotny, W.; Lehnert, J.; Schmidt, C.J.; Müller, W.F.J.

2016-01-01

The Silicon Tracking System, Muon Chamber, Transition Radiation Detector and Time-Of-Flight among others are the detector systems of the Compressed Baryonic Matter (CBM) experiment at the FAIR facility. These detector systems will be built with tens of thousands of front-end ASICs exposed to high radiation doses and difficult environmental and interference conditions. A CERN's GBTx-based solution was chosen for combining data from multiple front-end ASICs into an optical link before further concentration and preprocessing in the common Data Processing Board data hub. This paper presents the protocol design addressing the DAQ system requirements, simplifying the ASIC's back-end design and presents its adaptation for the STS and MUCH detector's conditions. A specific link synchronization technique, hit data bandwidth optimization and time synchronization method for the self-triggered front-end chip are presented.

TDC for the front end architecture in the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Riccardi, Alberto; Brinkmann, Kai Thomas; Di Pietro, Valentino [II Physikalisches Institut Justus-Liebig-Universitaet Giessen, Giessen (Germany); Garbolino, Sara; Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

In nuclear detectors the information on the energy of the particle is usually obtained by measuring the amplitude of the signal delivered by the sensor. The low voltage power supply used in modern deep submicron technologies constrains the maximum dynamic range of the ADC. So we can obtain the energy information with time-based techniques, in which the energy is associated with the duration of the signal through the Time over Threshold method. This work is focused on the PANDA Micro Vertex Detector and explores the possibility of applying a time-based readout approach for the microstrip sensors. In PANDA, the strip system must cope with hit rates up to 50 kHz per channel. Therefore, the front-end output must be relatively short. This implies that the clock resolution is not enough to measure the signal duration, so it is necessary to use a Time to Digital Converter. The front-end and the TDC structure are designed in a 0.11μm CMOS process. The TDC chosen is based on an analog clock interpolator because it combines good time resolution with a fairly simple implementation and low power consumption. In the presentation the architectures are described and the challenges associated to its implementation discussed.

Photodetectors and front-end electronics for the LHCb RICH upgrade

Science.gov (United States)

Cassina, L.; LHCb RICH

2017-12-01

The RICH detectors of the LHCb experiment provide identification of hadrons produced in high energy proton-proton collisions in the LHC at CERN over a wide momentum range (2-100 GeV/c). Cherenkov light is collected on photon detector planes sensitive to single photons. The RICH will be upgraded (in 2019) to read out every bunch crossing, at a rate of 40 MHz. The current hybrid photon detectors (HPD) will be replaced with multi-anode photomultiplier tubes (customisations of the Hamamatsu R11265 and the H12699 MaPMTs). These 8×8 pixel devices meet the experimental requirements thanks to their small pixel size, high gain, negligible dark count rate (∼50 Hz/cm2) and moderate cross-talk. The measured performance of several tubes is reported, together with their long-term stability. A new 8-channel front-end chip, named CLARO, has been designed in 0.35 μm CMOS AMS technology for the MaPMT readout. The CLARO chip operates in binary mode and combines low power consumption (∼1 mW/Ch), wide bandwidth (baseline restored in ⩽ 25 ns) and radiation hardness. A 12-bit digital register permits the optimisation of the dynamic range and the threshold level for each channel and provides tools for the on-site calibration. The design choices and the characterization of the electronics are presented.

FELIX: a PCIe based high-throughput approach for interfacing front-end and trigger electronics in the ATLAS upgrade framework

CERN Document Server

Chen, Kai; The ATLAS collaboration

2016-01-01

The ATLAS Phase-I upgrade requires a Trigger and Data Acquisition (TDAQ) system able to trigger and record data from up to three times the nominal LHC instantaneous luminosity. The FELIX system provides this in a scalable, detector agnostic and easily upgradeable way. It is a PC-based gateway, routing between custom radiation tolerant optical links from front-end electronics, via FPGA PCIe Gen3 cards, and a commodity switched Ethernet or InfiniBand network. FELIX enables reducing custom electronics in favor of software on commercial servers. The FELIX system, results of demonstrator, design and testing of prototype are described.

Concepts for a Muon Accelerator Front-End

Energy Technology Data Exchange (ETDEWEB)

Stratakis, Diktys [Fermilab; Berg, Scott [Brookhaven; Neuffer, David [Fermilab

2017-03-16

We present a muon capture front-end scheme for muon based applications. In this Front-End design, a proton bunch strikes a target and creates secondary pions that drift into a capture channel, decaying into muons. A series of rf cavities forms the resulting muon beams into a series of bunches of differerent energies, aligns the bunches to equal central energies, and initiates ionization cooling. We also discuss the design of a chicane system for the removal of unwanted secondary particles from the muon capture region and thus reduce activation of the machine. With the aid of numerical simulations we evaluate the performance of this Front-End scheme as well as study its sensitivity against key parameters such as the type of target, the number of rf cavities and the gas pressure of the channel.

Fast front-end L0 trigger electronics for ALICE FMD-MCP tests and performance

CERN Document Server

Efimov, L G; Kasatkan, V; Klempt, W; Kuts, V; Lenti, V; Platanov, V; Rudge, A; Stolyarov, O I; Tsimbal, F A; Valiev, F F; Villalobos Baillie, O; Vinogradov, L I; Zhigunov, O

1997-01-01

We present design details and new measurements of the performance of fast electronics for the Forward Multiplicity Detector for ALICE. These detectors based on sector type Microchannel Plates (MCP) forming several disks gave the very first trigger decision in the experiment (L0). Fast passive summators integrated with the detectors are used for linear summation of up to eight isochronous signal channels from MCP pads belonging to one sector. Two types of microelectronics design thin film summators were produced. We present test results for these summators, working in the frequency range up to 1 Ghz. New low noise preamplifiers have been built to work with these summators. The new design shows a good performance with the usable frequency range extended up to 1 Ghz. An upgrade of the functional scheme for the L0 ALICE pre-trigger design is also presented.Abstract:List of figures Figure 1: ALICE L0 Trigger Front-End Electronics Functional Scheme. Figure 2: UHF design for a fast passive summator based on direct...

DAQ system for testing RPC front-end electronics of the INO experiment

International Nuclear Information System (INIS)

Hari Prasad, K.; Sukhwani, Menka; Kesarkar, Tushar A.; Kumar, Sandeep; Chandratre, V.B.; Das, D.; Shinde, R.R.; Satyanarayana, B.

2015-01-01

The Resistive Plate Chamber (RPC) is the active detector element in the INO experiment. The in-house developed ANUSPARSH-III ASICs are being used as front-end electronics of the detector. The 2 m X 2 m RPC being used has 64-readout channels on X-side and 64-readout channels on Y-side. In order to test and validate the FE along with the RPC, a 64-channel DAQ system has been designed and developed. The detector parameters to be measured are noise rate, efficiency, hit pattern register and time resolution. The salient features of the DAQ system are: 64-channel LVDS receiver in FPGA, FPGA based parameter calculations and a micro controller for acquiring the processed data from FPGAs and sent through Ethernet and USB interfaces. The DAQ system consists of following parts: Two FPGAs each receiving 32 LVDS channels, FPGA firm-ware, micro controller firm-ware, Ethernet interface, embedded web server hosting data analysis software, USB interface, and Lab-windows based data analysis software. The DAQ system has been tested at TIFR with 1 m X 1 m RPC

Optical Module Front-End for a Neutrino Underwater Telescope PMT interface

CERN Document Server

Lo Presti, D; Caponetto, L

2007-01-01

A proposal for a new system to capture signals in the Optical Module (OM) of an Underwater Neutrino Telescope is described. It concentrates on the problem of power consumption in relation to precision. In particular, a solution for the interface between the photomultiplier (PMT) and the front-end electronics is presented.

A time-based front-end ASIC for the silicon micro strip sensors of the bar PANDA Micro Vertex Detector

Science.gov (United States)

Di Pietro, V.; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Rivetti, A.; Rolo, M. D.; Stockmanns, T.; Zambanini, A.

2016-03-01

The bar PANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA (bar PANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels.

BORA: A front end board, with local intelligence, for the rich detector of the compass collaboration

International Nuclear Information System (INIS)

Baum, G.; Birsa, R.; Bradamante, F.

1999-02-01

In this paper we describe the design of the re-configurable front-end boards (BORA boards) for the 82944 channel RICH-1 (Ring Imaging CHerenkov) of the Compass Collaboration (NA58). The front-end electronics controls the sample-and-hold operation after the arrival of an event trigger, acquires the analogue voltages from the pre-amp VLSI and converts them into 10 bits at a rate of 20 Ms/s per analogue channel. After the analog values are digitized they are written into FIFOs. A subsequent operation compares the readings of each and every channel with corresponding programmable thresholds, and transmits those values larger than the threshold, together with the channel number, through an optical fiber to subsequent processing stages of the acquisition system. The overall operation of the board is controlled and supervised by a fast DSP. The availability of local intelligence allows the board to present innovative features such as: to be part of a computer network that connects several similar boards of the detector with a PC. The presence of the DSP allows testing the operability and linearity of the analogue channels; and creating engineering frames containing local temperatures and voltages and transmitting the results through the network. The operator can reconfigure the hardware and software of the board by downloading programs from the PC. (author)

The Front-End Readout as an Encoder IC for Magneto-Resistive Linear Scale Sensors

Directory of Open Access Journals (Sweden)

Trong-Hieu Tran

2016-09-01

Full Text Available This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs and analog-to-digital converters (ADCs. The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC 0.35-micron complementary metal oxide semiconductor (CMOS technology for verification with a chip size of 6.61 mm2, while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL is −0.79–0.95 LSB while the differential non-linearity (DNL is −0.68–0.72 LSB. The effective number of bits (ENOB of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement

RF front-end world class designs

CERN Document Server

Love, Janine

2009-01-01

All the design and development inspiration and direction a harware engineer needs in one blockbuster book! Janine Love site editor for RF Design Line,columnist, and author has selected the very best RF design material from the Newnes portfolio and has compiled it into this volume. The result is a book covering the gamut of RF front end design from antenna and filter design fundamentals to optimized layout techniques with a strong pragmatic emphasis. In addition to specific design techniques and practices, this book also discusses various approaches to solving RF front end design problems and h

LHCb : A generic firmware core to drive the Front-End GBT-SCAs for the LHCb ugprade

CERN Multimedia

Alessio, Federico; Gaspar, Clara; Jacobsson, Richard; Wyllie, Ken

2014-01-01

The LHCb experiment has proposed an upgrade towards a full 40 MHz readout system in order to run between five and ten times its initial design luminosity. The entire Front-End electronics will be upgraded in order to cope with higher sub-detector occupancy, higher data rate and to work in a complete trigger-less fashion. In this paper, we describe a novel way to transmit slow control information to the Front-End electronics, by profiting from bidirectional optical connections and the GBT and GBT-SCA chipset capabilities. The implementation and preliminary validation tests are shown as well

Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

CERN Document Server

Carrio, F; The ATLAS collaboration; Moreno, P; Reed, R; Sandrock, C; Shalyugin, A; Schettino, V; Solans, C; Souza, J; Usai, G; Valero, A

2013-01-01

The portable test bench (VME based) used for the certification of the Tile calorimeter front-end electronics has been redesigned for the LHC Long Shutdown (2013-2014) improving its portability. The new version is based on a Xilinx Virtex 5 FPGA that implements an embedded system using a hard core PowerPC 440 microprocessor and custom IP cores. The PowerPC microprocessor runs a light Linux version and handles the IP cores written in VHDL that implement the different functionalities (TTC, G-Link, CAN-Bus) Description of the system and performance measurements of the different components will be shown.

The front-end amplifier for the silicon microstrip sensors of the PANDA MVD

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen (Germany); Rivetti, Angelo; Rolo, Manuel [INFN Sezione di Torino (Italy)

2015-07-01

The most common readout systems designed for the nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made from two main building blocks: front-end amplifier and ADC. One of the issues associated with the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the possibility of using time-based architectures offering better performances from that point of view. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work will present the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The key features of the front-end amplifier are illustrated and both schematic level, and post-layout simulations are discussed.

Indico front-end: From spaghetti to lasagna

CERN Multimedia

CERN. Geneva

2017-01-01

We will present how we transitioned from legacy spaghetti UI code to a more coherent, easier to understand and maintain ecosystem of front-end technologies and facilities with a strong emphasis in reusable components. In particular, we will share with you: 1) how we use Sass to maintain our home-baked CSS, 2) how we survive in 2017 without front-end Javascript frameworks, and 3) how we use template macros and WTForms for generating consistent HTML transparently.

LHCb: Test Station for the LHCb Muon Front-End Electronic

CERN Multimedia

Polycarpo, E

2005-01-01

The LHCb Muon Group has developed the CMOS ASIC CARIOCA to readout its Multiwire Proportional Chambers (MWPC) and GEM detectors, using a rad-hard IBM 0.25um process. Each ASIC holds 8 identical current-mode ASDB channels with individual input thresholds. The Muon detector contains around 120000 physical channels, requiring production of 20000 front-end chips, roughly. CARIOCA has been developed to process MWPC cathode and anode signals and two different versions have been implemented to overcome the requirement of MWP and GEM chambers operation. The test station has been devised to accomplish bipolar tests and to measure characteristics of both CARIOCA versions.

A time-based front-end ASIC for the silicon micro strip sensors of the P-bar ANDA Micro Vertex Detector

International Nuclear Information System (INIS)

Pietro, V. Di; Brinkmann, K.-Th.; Riccardi, A.; Ritman, J.; Stockmanns, T.; Zambanini, A.; Rivetti, A.; Rolo, M.D.

2016-01-01

The P-bar ANDA (Antiproton Annihilation at Darmstadt) experiment foresees many detectors for tracking, particle identification and calorimetry. Among them, the innermost is the MVD (Micro Vertex Detector) responsible for a precise tracking and the reconstruction of secondary vertices. This detector will be built from both hybrid pixel (two inner barrels and six forward disks) and double-sided micro strip (two outer barrels and outer rim of the last two disks) silicon sensors. A time-based approach has been chosen for the readout ASIC of the strip sensors. The PASTA ( P-bar ANDA Strip ASIC) chip aims at high resolution time-stamping and charge information through the Time over Threshold (ToT) technique. It benefits from a Time to Digital Converter (TDC) allowing a time bin width down to 50 ps. The analog front-end was designed to serve both n-type and p-type strips and the performed simulations show remarkable performances in terms of linearity and electronic noise. The TDC consists of an analog interpolator, a digital local controller, and a digital global controller as the common back-end for all of the 64 channels

Idea management in support of pharmaceutical front end innovation

DEFF Research Database (Denmark)

Aagaard, Annabeth

2012-01-01

The pharmaceutical industry faces continuing pressures from rising R&D costs and depreciating value of patents, as patent lives is eroded by testing procedures and pressures from public authorities to cut health care costs. These challenges have increased the focus on shortening development times......, which again put pressure on the efficiency of front end innovation (FEI). In the attempt to overcome these various challenges pharmaceutical companies are looking for new models to support FEI. This paper explores in what way idea management can be applied as a tool in facilitation of front end...... innovation in practice. First I show through a literature study, how idea management and front end innovation are related and may support each other. Hereafter I apply an exploratory case study of front end innovation in eight medium to large pharmaceutical companies in examination of how idea management...

Front-end electronics for long straw tube systems

International Nuclear Information System (INIS)

Paulos, J.J.; Blake, S.L.

1990-01-01

This paper addresses several critical issues in the readout of long, small diameter plastic straw tubes for central tracking subsystems. Of particular concern are signal attentuation in long straw tubes and signal reflections which arise from improper termination at the ends of the tube. This work is part of a 12 institution collaboration to design and validate a hybrid central tracking chamber (HCTC) utilizing both straw tube and scintillating fiber components. The HCTC design calls for 4 mm diameter plastic straw tubes spanning the entire central tracking region (6-8 m) with readout electronics at both ends. An electrical isolator may be used at the center of each wire to separate each tube into two electrically isolated regions so as to reduce occupancy by a factor of two. With this scheme, no track is farther than 4 m from the associated readout electronics. The HCTC collaboration includes the participation of researchers at the University of Pennsylvania who have contributed a preamplifier and shaper ship which is used in the simulations presented here. A more complete discussion of the HCTC design can be found in the paper by Dr. Alfred Goshaw

FELIX: The New Approach for Interfacing to Front-end Electronics for the ATLAS Experiment

CERN Document Server

AUTHOR|(SzGeCERN)754725; The ATLAS collaboration; Anderson, John Thomas; Borga, Andrea; Boterenbrood, Hendrik; Chen, Hucheng; Chen, Kai; Drake, Gary; Donszelmann, Mark; Francis, David; Gorini, Benedetto; Guest, Daniel; Lanni, Francesco; Lehmann Miotto, Giovanna; Levinson, Lorne; Roich, Alexander; Schreuder, Frans Philip; Schumacher, J\\"orn; Vandelli, Wainer; Zhang, Jinlong

2016-01-01

From the ATLAS Phase-I upgrade and onward, new or upgraded detectors and trigger systems will be interfaced to the data acquisition, detector control and timing (TTC) systems by the Front-End Link eXchange (FELIX). FELIX is the core of the new ATLAS Trigger/DAQ architecture. Functioning as a router between custom serial links and a commodity network, FELIX is implemented by server PCs with commodity network interfaces and PCIe cards with large FPGAs and many high speed serial fiber transceivers. By separating data transport from data manipulation, the latter can be done by software in commodity servers attached to the network. Replacing traditional point-to-point links between Front-end components and the DAQ system by a switched network, FELIX provides scaling, flexibility uniformity and upgradability and reduces the diversity of custom hardware solutions in favour of software.

Ultra-wideband wireless receiver front-end for high-speed indoor applications

Directory of Open Access Journals (Sweden)

Zhe-Yang Huang

2014-12-01

Full Text Available Low-noise, ultra-wideband (UWB wireless receiver front-end circuits were presented in this study. A two-stage common-source low-noise amplifier with wideband input impedance matching network, an active-balun and a double-balanced down-conversion mixer were adopted in the UWB wireless receiver front-end. The proposed wireless receiver front-end circuits were implemented in 0.18 μm radio-frequency-CMOS process. The maximum down-conversion power gain of the front-end is 25.8 dB; minimum single-sideband noise figure of the front-end is 4.9 dB over complete UWB band ranging from 3.1 to 10.6 GHz. Power consumption including buffers is 39.2 mW.

Programmer's guide to FFE: a fast front-end data-acquisition program

International Nuclear Information System (INIS)

Million, D.L.

1983-05-01

The Large Coil Test Facility project of the Fusion Energy Division has a data acquisition system which includes a large host computer and several small, peripheral front-end computers. The front-end processors handle details of data acquisition under the control of the host and pass data back to the host for storage. Some of the front ends are known as fast front ends and are required to collect a maximum of 64,000 samples each second. This speed and other hardware constraints resulted in a need for a stand-alone, assembly language task which could be downline loaded from the host system into the fast front ends. FFE (Fast Front End) was written to satisfy this need. It was written in the PDP-11 MACRO-11 assembly language for an LSI-11/23 processor. After the host loads the task into the front end, it controls the data acquisition process with a series of commands and parameters. This Programmer's Guide describes the structure and operation of FFE in detail from a programming point of view. A companion User's guide provides more information on the use of the program from the host system

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B0s → J/ψ Φ

International Nuclear Information System (INIS)

Knopf, Jan

2009-01-01

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase Φ s . It can be measured by using the golden decay mode B 0 s → J/ψ Φ. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

Characterisation of the VMM3 Front-end read-out ASIC

CERN Document Server

Bartels, Lara Maria

2018-01-01

This research project was conducted in the RD51 collaboration at CERN, which is involved in the development of micropattern gaseous detector technologies and read-out systems. One example in the broad range of possible applications of such gaseous detectors is the NMX macromolecular diffractometer instrument planned for the European spallation source (ESS) which is currently under construction in Lund, Sweden. For the NMX instrument neutron detectors with high rate capabilities, high stability and excellent spatial resolution are required. A group working in the RD51 collaboration at CERN within the BrightnESS project aims to fulfil those requirements using gas electron multiplier (GEM) detectors with Gadolinium foils as neutron converters [PFE]. In order to match the high rate capability of the detectors, new front-end read-out systems need to be tested and implemented. This project aims to understand and test the capabilities of the VMM3 as the front-end read-out ASIC for GEM detectors.

An array of virtual Frisch-grid CdZnTe detectors and a front-end application-specific integrated circuit for large-area position-sensitive gamma-ray cameras

Energy Technology Data Exchange (ETDEWEB)

Bolotnikov, A. E., E-mail: bolotnik@bnl.gov; Ackley, K.; Camarda, G. S.; Cherches, C.; Cui, Y.; De Geronimo, G.; Fried, J.; Hossain, A.; Mahler, G.; Maritato, M.; Roy, U.; Salwen, C.; Vernon, E.; Yang, G.; James, R. B. [Brookhaven National Laboratory, Upton, New York 11793 (United States); Hodges, D. [University of Texas at El Paso, El Paso, Texas 79968 (United States); Lee, W. [Korea University, Seoul 136-855 (Korea, Republic of); Petryk, M. [SUNY Binghamton, Vestal, New York 13902 (United States)

2015-07-15

We developed a robust and low-cost array of virtual Frisch-grid CdZnTe detectors coupled to a front-end readout application-specific integrated circuit (ASIC) for spectroscopy and imaging of gamma rays. The array operates as a self-reliant detector module. It is comprised of 36 close-packed 6 × 6 × 15 mm{sup 3} detectors grouped into 3 × 3 sub-arrays of 2 × 2 detectors with the common cathodes. The front-end analog ASIC accommodates up to 36 anode and 9 cathode inputs. Several detector modules can be integrated into a single- or multi-layer unit operating as a Compton or a coded-aperture camera. We present the results from testing two fully assembled modules and readout electronics. The further enhancement of the arrays’ performance and reduction of their cost are possible by using position-sensitive virtual Frisch-grid detectors, which allow for accurate corrections of the response of material non-uniformities caused by crystal defects.

Beginning analog electronics through projects

CERN Document Server

Singmin, Andrew

2001-01-01

Analog electronics is the simplest way to start a fun, informative, learning program. Beginning Analog Electronics Through Projects, Second Edition was written with the needs of beginning hobbyists and students in mind. This revision of Andrew Singmin's popular Beginning Electronics Through Projects provides practical exercises, building techniques, and ideas for useful electronics projects. Additionally, it features new material on analog and digital electronics, and new projects for troubleshooting test equipment.Published in the tradition of Beginning Electronics Through Projects an

Align the Front End First.

Science.gov (United States)

Perry, Jim

1995-01-01

Discussion of management styles and front-end analysis focuses on a review of Douglas McGregor's theories. Topics include Theories X, Y, and Z; leadership skills; motivational needs of employees; intrinsic and extrinsic rewards; and faulty implementation of instructional systems design processes. (LRW)

A GEM-TPC prototype with low-Noise highly integrated front-end electronics for linear collider studies

CERN Document Server

Kappler, Steffen; Kaminski, Jochen; Ledermann, Bernhard; Müller, Thomas; Ronan, Michael T; Ropelewski, Leszek; Sauli, Fabio; Settles, Ronald

2004-01-01

Connected to the linear collider project, studies on the readout of time projection chambers (TPCs) based on the gas electron multiplier (GEM) are ongoing. Higher granularity and intrinsically suppressed ion feedback are the major advantages of this technology. After a short discussion of these issues, we present the design of a small and very flexible TPC prototype, whose cylindrical drift volume can be equipped with endcaps of different gas detector types. An endcap with multi-GEM readout is currently set up and successfully operated with a low-noise highly integrated front-end electronics. We discuss results of measurements with this system in high intensity particle beams at CERN, where 99.3 plus or minus 0.2% single-pad-row efficiency could be achieved at an effective gain of 2.5 multiplied by 10**3 only, and spatial resolutions down to 63 plus or minus 3 mum could be demonstrated. Finally, these results are extrapolated to the high magnetic field in a linear collider TPC. 5 Refs.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed; Ghazzai, Hakim; Kadri, Abdullah; Alouini, Mohamed-Slim

2016-01-01

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

Front-End Intelligence for Large-Scale Application-Oriented Internet-of-Things

KAUST Repository

Bader, Ahmed

2016-06-14

The Internet-of-things (IoT) refers to the massive integration of electronic devices, vehicles, buildings, and other objects to collect and exchange data. It is the enabling technology for a plethora of applications touching various aspects of our lives such as healthcare, wearables, surveillance, home automation, smart manufacturing, and intelligent automotive systems. Existing IoT architectures are highly centralized and heavily rely on a back-end core network for all decision-making processes. This may lead to inefficiencies in terms of latency, network traffic management, computational processing, and power consumption. In this paper, we advocate the empowerment of front-end IoT devices to support the back-end network in fulfilling end-user applications requirements mainly by means of improved connectivity and efficient network management. A novel conceptual framework is presented for a new generation of IoT devices that will enable multiple new features for both the IoT administrators as well as end users. Exploiting the recent emergence of software-defined architecture, these smart IoT devices will allow fast, reliable, and intelligent management of diverse IoT-based applications. After highlighting relevant shortcomings of the existing IoT architectures, we outline some key design perspectives to enable front-end intelligence while shedding light on promising future research directions.

FACILITATING RADICAL FRONT-END INNOVATION THROUGH TARGETED HR PRACTICES

DEFF Research Database (Denmark)

Aagaard, Annabeth

2017-01-01

This study examines how radical front end innovation can be actively facilitated through selected and targeted HR practices and bundles of HR practices. The empirical field is an explorative case study of front end innovation and HR practices in the pharmaceutical industry, with an in-depth case ...

The NA62 LAV front-end electronics and the L0 trigger generating firmware

CERN Document Server

Gonnella, Francesco; Corradi, Giovanni; Kozhuharov , Venelin ; Martellotti, Silvia; Moulson, Matthew; Raggi, Mauro; Spadaro, Tommaso

2014-01-01

The aim of the NA62 experiment is to measure the branching ratio of the decay K + ! p + n ̄ n to within about 10%. The large-angle photon vetoes (LAVs) must detect particles with better than 1 ns time resolution and 10% energy resolution over a very large energy range in order to reject the dominant background: photons coming from p + p 0 decays. A low threshold, large dynamic range, time-over-threshold based solution has been developed for the LAV front end electronics (LAV-FEE). Our custom 32 channel 9U board uses a pair of low threshold discriminators for each channel to produce LVDS logic signals. The achieved time resolution obtained in laboratory, coupled to a readout board based on the HPTDC chip developed at CERN, is 100 ps. For LAV-FEE, a FPGA-based level-0 trigger providing slewing-corrected trigger time with similar precision has also been developed.

The front-end chip of the SuperB SVT detector

International Nuclear Information System (INIS)

Giorgi, F.; Comotti, D.; Manghisoni, M.; Re, V.; Traversi, G.; Fabbri, L.; Gabrielli, A.; Pellegrini, G.; Sbarra, C.; Semprini-Cesari, N.; Valentinetti, S.; Villa, M.; Zoccoli, A.; Berra, A.; Lietti, D.; Prest, M.; Bevan, A.; Wilson, F.; Beck, G.; Morris, J.

2013-01-01

The asymmetric e + e − collider SuperB is designed to deliver a high luminosity, greater than 10 36 cm −2 s −1 , with moderate beam currents and a reduced center of mass boost with respect to earlier B-Factories. The innermost detector is the Silicon Vertex Tracker which is made of 5 layers of double sided silicon strip sensors plus a layer 0, that can be equipped with short striplets detectors in a first phase of the experiment. In order to achieve an overall track reconstruction efficiency above 98% it is crucial to optimize both analog and digital readout circuits. The readout architecture being developed for the front-end chips will be able to cope with the very high rates expected in the first layer. The digital readout will be optimized to be fully efficient for hit rates up to 2 MHz/strip, including large margins on the maximum expected background rates, but can potentially accommodate higher rates with a proper tuning of the buffer depth. The readout is based on a triggered architecture where each of the 128 strip channel is provided with a dedicated digital buffer. Each buffer collects the digitized charge information by means of a 4-bit TOT, storing it in conjunction with the related time stamp. The depth of buffers was dimensioned considering the expected trigger latency and hit rate including suitable safety margins. Every buffer is connected to a highly parallelized circuit handling the trigger logic, rejecting expired data in the buffers and channeling the parallel stream of triggered hits to the common output of the chip. The presented architecture has been modeled by HDL language and investigated with a Monte Carlo hit generator emulating the analog front-end behavior. The simulations showed that even applying the highest stressing conditions, about 2 MHz per strip, the efficiency of the digital readout remained above 99.8%

FILTRES: a 128 channels VLSI mixed front-end readout electronic development for microstrip detectors

International Nuclear Information System (INIS)

Anstotz, F.; Hu, Y.; Michel, J.; Sohler, J.L.; Lachartre, D.

1998-01-01

We present a VLSI digital-analog readout electronic chain for silicon microstrip detectors. The characteristics of this circuit have been optimized for the high resolution tracker of the CERN CMS experiment. This chip consists of 128 channels at 50 μm pitch. Each channel is composed by a charge amplifier, a CR-RC shaper, an analog memory, an analog processor, an output FIFO read out serially by a multiplexer. This chip has been processed in the radiation hard technology DMILL. This paper describes the architecture of the circuit and presents test results of the 128 channel full chain chip. (orig.)

A low-power front-end amplifier for the microstrip sensors of the PANDA microvertex detector

Energy Technology Data Exchange (ETDEWEB)

Di Pietro, Valentino; Brinkmann, Kai-Thomas; Riccardi, Alberto [II. Physikalisches Institut, JLU Giessen, Giessen (Germany); Rivetti, Angelo; Rolo, Manuel; Garbolino, Sara [INFN Sezione di Torino, Torino (Italy); Collaboration: PANDA-Collaboration

2014-07-01

The most common readout systems designed for nuclear physics detectors are based on amplitude measurements. The information that needs to be preserved is the charge delivered by a particle hitting the sensor. The electronic chain employed in these cases is made of two main building blocks: front-end amplifier and ADC. An issue in the implementation of such an architecture in scaled CMOS technologies is the dynamic range, because the charge information is extrapolated through the sampling of the peak of the front-end output signal. It is therefore interesting to explore the use of time-based architectures that offer better performances. In fact, in these topologies the linearity between the charge and the signal duration can be maintained even if some building blocks in the chain saturate. The main drawback is the loss in resolution since a duration measurement involves the difference between two time measurements. This work presents the design of a front-end optimized for fast Time-over-Threshold applications. The circuit has been developed for the microstrip detectors of the PANDA experiment. The architecture of the front-end amplifier is presented, and simulations in a 110 nm CMOS technology are discussed.

MMIC tuned front-end for a coherent optical receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A. M.; Ebskamp, F.

1993-01-01

A low-noise transformer tuned optical front-end for a coherent optical receiver is described. The front-end is based on a GaInAs/InP p-i-n photodiode and a full custom designed GaAs monolithic microwave integrated circuit (MMIC). The measured equivalent input noise current density is between 5-16 p...

Design and implementation of the ATLAS TRT front end electronics

Science.gov (United States)

Newcomer, Mitch; Atlas TRT Collaboration

2006-07-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The "on detector" environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ˜1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding.

Design and implementation of the ATLAS TRT front end electronics

International Nuclear Information System (INIS)

Newcomer, Mitch

2006-01-01

The ATLAS TRT subsystem is comprised of 380,000 4 mm straw tube sensors ranging in length from 30 to 80 cm. Polypropelene plastic layers between straws and a xenon-based gas mixture in the straws allow the straws to be used for both tracking and transition radiation detection. Detector-mounted electronics with data sparsification was chosen to minimize the cable plant inside the super-conducting solenoid of the ATLAS inner tracker. The 'on detector' environment required a small footprint, low noise, low power and radiation-tolerant readout capable of triggering at rates up to 20 MHz with an analog signal dynamic range of >300 times the discriminator setting. For tracking, a position resolution better than 150 μm requires leading edge trigger timing with ∼1 ns precision and for transition radiation detection, a charge collection time long enough to integrate the direct and reflected signal from the unterminated straw tube is needed for position-independent energy measurement. These goals have been achieved employing two custom Application-specific integrated circuits (ASICS) and board design techniques that successfully separate analog and digital functionality while providing an integral part of the straw tube shielding

40 CFR 63.487 - Batch front-end process vents-reference control technology.

Science.gov (United States)

2010-07-01

... § 63.487 Batch front-end process vents—reference control technology. (a) Batch front-end process vents... 40 Protection of Environment 9 2010-07-01 2010-07-01 false Batch front-end process vents-reference control technology. 63.487 Section 63.487 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY...

THREE PERSPECTIVES ON MANAGING FRONT END INNOVATION

DEFF Research Database (Denmark)

Jensen, Anna Rose Vagn; Clausen, Christian; Gish, Liv

2018-01-01

as a complementary perspective. The paper combines a literature review with an empirical examination of the application of these multiple perspectives across three cases of front end of innovation (FEI) management in mature product developing companies. While the process models represent the dominant, albeit rather...... to represent an emergent approach in managing FEI where process models, knowledge strategies and objects become integrated elements in more advanced navigational strategies for key players.......This paper presents three complementary perspectives on the management of front end innovation: A process model perspective, a knowledge perspective and a translational perspective. While the first two perspectives are well established in literature, we offer the translation perspective...

REASONING IN THE FUZZY FRONT END OF INNOVATION:

DEFF Research Database (Denmark)

Haase, Louise Møller; Laursen, Linda Nhu

2018-01-01

in the fuzzy front end is the reasoning process: innovation teams are faced with open-ended, ill-defined problems, where they need to make decisions about an unknown future but have only incomplete, ambiguous and contradicting insights available. We study the reasoning of experts, how they frame to make sense...... of all the insights and create a basis for decision-making in relation to a new project. Based on case studies of five innovative products from various industries, we propose a Product DNA model for understanding the reasoning in the fuzzy front end of innovation. The Product DNA Model explains how...... experts reason and what direct their reasoning....

Front-End Electronics in calorimetry: from LHC to ILC

International Nuclear Information System (INIS)

De La Taille, Ch.

2009-09-01

This report summarizes the electronics developments for liquid argon calorimeter read-out at LHC and the development carried out in the framework of the CALICE collaboration for those of the future linear collider (ILC). It also includes chips designed for multi-anode photomultipliers (MaPMT) used in the OPERA experiment or on ATLAS luminometer, which also find applications in medical imaging. Started in the early 90's, the development for ATLAS calorimetry was extremely challenging in terms of readout speed, radiation tolerance and measurement accuracy. The high speed has required a new approach using current-sensitive preamplifiers instead of charge sensitive ones and the redefinition of noise performance in terms of ENI. The preamplifiers developed at Orsay and the monolithic shapers are described in Chapter 1, including considerations of digital filtering, which was a new technique in our field. Chapter 2 is dedicated to the calibration system, designed and built by Orsay, for which the high performance and accuracy necessitated in-depth studies. The 3. chapter closes the studies for ATLAS with a summary of the detector measurements which had to be carried out on the 200 000 channels in order to understand and model the detector and achieve everywhere the accuracy and uniformity at per-cent level. These developments for ATLAS ended in 2004, although parallel work was also carried out for the NA48 and DO calorimeters which are not detailed here. The next generation of collider will require a new generation of calorimeters, much more granular, referred to as 'imaging calorimetry' with embedded read-out electronics. The ASICs developed for this purpose in the framework of the CALICE collaboration are described in Chapter 4. They integrate all the functionalities of amplification, digitization and read-out making them complex 'System-On-Chip' circuits extremely efficient that find many other applications. A family of 3 chips reads out the Si-W electromagnetic

A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System.

Science.gov (United States)

Wu, Chung-Yu; Cheng, Cheng-Hsiang; Chen, Zhi-Xin

2018-06-01

In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-to-digital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-μVrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 μW per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.

Terahertz performance of quasioptical front-ends with a hotelectron bolometer

International Nuclear Information System (INIS)

Semenov, A; Richter, H; Guenther, B; Huebers, H-W; Karamarkovic, J

2006-01-01

We present terahertz performance of quasioptical front-ends consisting of a hotelectron bolometer imbedded in a planar feed antenna and integrated with an immersion lens. The impedance and radiation pattern of the log-spiral and double-slot planar feeds are evaluated using the method of moments; the collimating action of the lens is modelled using the physical optics. The total efficiency of the front-ends is computed taking into account frequency dependent impedance of the bolometer. Measured performance of the front-ends qualifies the simulation technique as a reliable tool for the design of terahertz receivers

A wide dynamic range BF3 neutron monitor with front-end electronics based on a logarithmic amplifier

International Nuclear Information System (INIS)

Ferrarini, M.; Varoli, V.; Favalli, A.; Caresana, M.; Pedersen, B.

2010-01-01

This paper describes a wide dynamic range neutron monitor based on a BF 3 neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10 6 s -1 . It has also proved effective in measuring the PUNITA facility pulse integral fluence.

An Alternative Front End Analysis Strategy for Complex Systems

Science.gov (United States)

2014-12-01

missile ( ABM ) system . Patriot is employed in the field through a battalion echelon organizational structure. The line battery is the basic building...Research Report 1981 An Alternative Front End Analysis Strategy for Complex Systems M. Glenn Cobb U.S. Army Research Institute...NUMBER W5J9CQ11D0003 An Alternative Front End Analysis Strategy for Complex Systems 5b. PROGRAM ELEMENT NUMBER 633007 6

Toward 5G software defined radio receiver front-ends

CERN Document Server

Spiridon, Silvian

2016-01-01

This book introduces a new intuitive design methodology for the optimal design path for next-generation software defined radio front-ends (SDRXs). The methodology described empowers designers to "attack" the multi-standard environment in a parallel way rather than serially, providing a critical tool for any design methodology targeting 5G circuits and systems. Throughout the book the SDRX design follows the key wireless standards of the moment (i.e., GSM, WCDMA, LTE, Bluetooth, WLAN), since a receiver compatible with these standards is the most likely candidate for the first design iteration in a 5G deployment. The author explains the fundamental choice the designer has to make regarding the optimal channel selection: how much of the blockers/interferers will be filtered in the analog domain and how much will remain to be filtered in the digital domain. The system-level analysis the author describes entails the direct sampling architecture is treated as a particular case of mixer-based direct conversion archi...

Continuous-time digital front-ends for multistandard wireless transmission

CERN Document Server

Nuyts, Pieter A J; Dehaene, Wim

2014-01-01

This book describes the design of fully digital multistandard transmitter front-ends which can directly drive one or more switching power amplifiers, thus eliminating all other analog components.  After reviewing different architectures, the authors focus on polar architectures using pulse width modulation (PWM), which are entirely based on unclocked delay lines and other continuous-time digital hardware.  As a result, readers are enabled to shift accuracy concerns from the voltage domain to the time domain, to coincide with submicron CMOS technology scaling.  The authors present different architectural options and compare them, based on their effect on the signal and spectrum quality.  Next, a high-level theoretical analysis of two different PWM-based architectures – baseband PWM and RF PWM – is made.  On the circuit level, traditional digital components and design techniques are revisited from the point of view of continuous-time digital circuits.  Important design criteria are identified and diff...

Signal processing and electronics for nuclear spectrometry. Proceedings of a technical meeting

International Nuclear Information System (INIS)

2009-12-01

The IAEA has responded to Member States needs by implementing programmatic activities that provide interested Member States, particularly those in developing countries, with support to increase, and in some cases establish national and regional capabilities for the proper operation, calibration, maintenance and utilization of instruments in nuclear spectrometry applications. Technological advances in instrumentation, as well as the consequent high rate of obsolescence, make it important for nuclear instrumentation laboratories in Member States to keep their knowledge and skills up to date. This publication reviews the current status, developments and trends in electronics and digital methods for nuclear spectrometry, providing useful information for interested Member States to keep pace with new and evolving technologies. All nuclear spectrometry systems contain electronic circuits and devices, commonly referred to as front-end electronics, which accept and process the electrical signals produced by radiation detectors. This front-end electronics are composed of a chain of signal processing subsystems that filter, amplify, shape, and digitise these electrical signals to finally produce digitally encoded information about the type and nature of the radiation that stimulated the radiation detector. The design objective of front-end electronics is to obtain maximum information about the radiation and with the highest possible accuracy. Historically, the front-end electronics has consisted of all analog components. The performance delivered has increased continually over time through the development and implementation of new and improved analog electronics and electronic designs. The development of digital electronics, programmable logic, and digital signal processing techniques has now enabled most of the analog front-end electronics to be replaced by digital electronics, opening up new opportunities and delivering new benefits not previously achievable. Digital

A 32-channel front-end ASIC for GEM detectors used in beam monitoring applications

Science.gov (United States)

Ciciriello, F.; Altieri, P. R.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Lorusso, L.; Marzocca, C.; Matarrese, G.; Ranieri, A.; Stamerra, A.

2017-11-01

A multichannel, mixed-signal, front-end ASIC for GEM detectors, intended for beam monitoring in hadron therapy applications, has been designed and prototyped in a standard 0.35 μm CMOS technology. The analog channels are based on the classic CSA + shaper processing chain, followed by a peak detector which can work as an analog memory, to simplifiy the analog-to-digital conversion of the peak voltage of the output pulse, proportional to the energy of the detected event. The available hardware resources include an 8-bit A/D converter and a standard-cell digital part, which manages the read-out procedure, in sparse or serial mode. The ASIC is self-triggered and transfers energy and address data to the external DAQ via a fast 100 MHz LVDS link. Preliminary characterization results show that the non-linearity error is limited to 5% for a maximum input charge of about 70 fC, the measured ENC is about 1400e- and the time jitter of the trigger signal generated in response to an injected charge of 60 fC is close to 200 ps.

CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

International Nuclear Information System (INIS)

CHASE, B.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, S.; RESCIA, S.; TAKAI, H.

1999-01-01

The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

CHARACTERIZATION OF THE COHERENT NOISE, ELECTROMAGNETIC COMPATIBILITY AND ELECTROMAGNETIC INTERFERENCE OF THE ATLAS EM CALORIMETER FRONT END BOARD

International Nuclear Information System (INIS)

CHASE, R.L.; CITTERIO, M.; LANNI, F.; MAKOWIECKI, D.; RADEKA, V.; RESCIA, S.; TAKAI, H.; BAN, J.; PARSONS, J.; SIPPACH, W.

2000-01-01

The ATLAS Electromagnetic (EM) calorimeter (EMCAL) Front End Board (FEB) will be located in custom-designed enclosures solidly connected to the feedtroughs. It is a complex mixed signal board which includes the preamplifier, shaper, switched capacitor array analog memory unit (SCA), analog to digital conversion, serialization of the data and related control logic. It will be described in detail elsewhere in these proceedings. The electromagnetic interference (either pick-up from the on board digital activity, from power supply ripple or from external sources) which affects coherently large groups of channels (coherent noise) is of particular concern in calorimetry and it has been studied in detail

An Ultra-Low Voltage Analog Front End for Strain Gauge Sensory System Application in 0.18µm CMOS

Science.gov (United States)

Edward, Alexander; Chan, Pak Kwong

This paper presents analysis and design of a new ultra-low voltage analog front end (AFE) dedicated to strain sensor applications. The AFE, designed in 0.18µm CMOS process, features a chopper-stabilized instrumentation amplifier (IA), a balanced active MOSFET-C 2nd order low pass filter (LPF), a clock generator and a voltage booster which operate at supply voltage (Vdd) of 0.6V. The designed IA achieves 30dB of closed-loop gain, 101dB of common-mode rejection ratio (CMRR) at 50Hz, 80dB of power-supply rejection ratio (PSRR) at 50Hz, thermal noise floor of 53.4 nV/√Hz, current consumption of 14µA, and noise efficiency factor (NEF) of 9.7. The high CMRR and rail-to-rail output swing capability is attributed to a new low voltage realization of the active-bootstrapped technique using a pseudo-differential gain-boosting operational transconductance amplifier (OTA) and proposed current-driven bulk (CDB) biasing technique. An output capacitor-less low-dropout regulator (LDO), with a new fast start-up LPF technique, is used to regulate this 0.6V supply from a 0.8-1.0V energy harvesting power source. It achieves power supply rejection (PSR) of 42dB at frequency of 1MHz. A cascode compensated pseudo differential amplifier is used as the filter's building block for low power design. The filter's single-ended-to-balanced converter is implemented using a new low voltage amplifier with two-stage common-mode cancellation. The overall AFE was simulated to have 65.6dB of signal-to-noise ratio (SNR), total harmonic distortion (THD) of less than 0.9% for a 100Hz sinusoidal maximum input signal, bandwidth of 2kHz, and power consumption of 51.2µW. Spectre RF simulations were performed to validate the design using BSIM3V3 transistor models provided by GLOBALFOUNDRIES 0.18µm CMOS process.

A Programmable Biopotential Aquisition Front-end with a Resistance-free Current-balancing Instrumentation Amplifier

Directory of Open Access Journals (Sweden)

FARAGO, P.

2018-05-01

Full Text Available The development of wearable biomedical equipment benefits from low-power and low-voltage circuit techniques for reduced battery size and battery, or even battery-less, operation. This paper proposes a fully-differential low-power resistance-free programmable instrumentation amplifier for the analog front-end of biopotential monitoring systems. The proposed instrumentation amplifier implements the current balancing technique. Low power consumption is achieved with subthreshold biasing. To reduce chip area and enable integration, passive resistances have been replaced with active equivalents. Accordingly, the instrumentation amplifier gain is expressed as the ratio of two transconductance values. The proposed instrumentation amplifier exhibits two degrees of freedom: one to set the desired range and the other for fine-tuning of the voltage gain. The proposed IA is employed in a programmable biopotential acquisition front-end. The programmable frequency-selective behavior is achieved by having the lower cutoff frequency of a Gm-C Tow-Thomas biquad varied in a constant-C tuning approach. The proposed solutions and the programmability of the operation parameters to the specifications of particular bio-medical signals are validated on a 350nm CMOS process.

Sustainability in the front-end of innovation at design agencies

NARCIS (Netherlands)

Storaker, A.; Wever, R.; Dewulf, K.; Blankenburg, D.

2013-01-01

In the two last decades a considerable amount of research has been conducted on the Front End of Innovation. This is the stage of the product development process where the design brief is formulated. This phase is argued to be crucial to the success of the final product. While the Front End of

Scintillation counter and wire chamber front end modules for high energy physics experiments

International Nuclear Information System (INIS)

Baldin, Boris; DalMonte, Lou

2011-01-01

This document describes two front-end modules developed for the proposed MIPP upgrade (P-960) experiment at Fermilab. The scintillation counter module was developed for the Plastic Ball detector time and charge measurements. The module has eight LEMO 00 input connectors terminated with 50 ohms and accepts negative photomultiplier signals in the range 0.25...1000 pC with the maximum input voltage of 4.0 V. Each input has a passive splitter with integration and differentiation times of ∼20 ns. The integrated portion of the signal is digitized at 26.55 MHz by Analog Devices AD9229 12-bit pipelined 4-channel ADC. The differentiated signal is discriminated for time measurement and sent to one of the four TMC304 inputs. The 4-channel TMC304 chip allows high precision time measurement of rising and falling edges with ∼100 ps resolution and has internal digital pipeline. The ADC data is also pipelined which allows deadtime-less operation with trigger decision times of ∼4 (micro)s. The wire chamber module was developed for MIPP EMCal detector charge measurements. The 32-channel digitizer accepts differential analog signals from four 8-channel integrating wire amplifiers. The connection between wire amplifier and digitizer is provided via 26-wire twist-n-flat cable. The wire amplifier integrates input wire current and has sensitivity of 275 mV/pC and the noise level of ∼0.013 pC. The digitizer uses the same 12-bit AD9229 ADC chip as the scintillator counter module. The wire amplifier has a built-in test pulser with a mask register to provide testing of the individual channels. Both modules are implemented as a 6Ux220 mm VME size board with 48-pin power connector. A custom europack (VME) 21-slot crate is developed for housing these front-end modules.

Rabbit System. Low cost, high reliability front end electronics featuring 16 bit dynamic range

International Nuclear Information System (INIS)

Drake, G.; Droege, T.F.; Nelson, C.A. Jr.; Turner, K.J.; Ohska, T.K.

1985-10-01

A new crate-based front end system has been built which features low cost, compact packaging, command capability, 16 bit dynamic range digitization, and a high degree of redundancy. The crate can contain a variety of instrumentation modules, and is designed to be situated close to the detector. The system is suitable for readout of a large number of channels via parallel multiprocessor data acquisition

The digital ASIC for the digital front end electronics of the SPI astrophysics gamma-ray experiment

International Nuclear Information System (INIS)

Lafond, E.; Mur, M.; Schanne, S.

1998-01-01

The SPI spectrometer is one of the gamma-ray astronomy instruments that will be installed on the ESA INTEGRAL satellite, intended to be launched in 2001 by the European Space Agency. The Digital Front-End Electronics sub-system (DFEE) is in charge of the real time data processing of the various measurements produced by the Germanium (Ge) detectors and the Bismuth Germanate (BGO) anti-coincidence shield. The central processing unit of the DFEE is implemented in a digital ASIC circuit, which provides the real time association of the various time signals, acquires the associated energy measurements, and classifies the various types of physics events. The paper gives the system constraints of the DFEE, the architecture of the ASIC circuit, the technology requirements, and the strategy for test and integration. Emphasis is given to the high level language development and simulation, the automatic circuit synthesis approach, and the performance estimation

The front-end electronics for the 1.8-kchannel SiPM tracking plane in the NEW detector

International Nuclear Information System (INIS)

Rodríguez, J.; Lorca, D.; Monrabal, F.; Toledo, J.; Esteve, R.

2015-01-01

NEW is the first phase of NEXT-100 experiment, an experiment aimed at searching for neutrinoless double-beta decay. NEXT technology combines an excellent energy resolution with tracking capabilities thanks to a combination of optical sensors, PMTs for the energy measurement and SiPMs for topology reconstruction. Those two tools result in one of the highest background rejection potentials in the field. This work describes the tracking plane that will be constructed for the NEW detector which consists of close to 1800 sensors with a 1-cm pitch arranged in twenty-eight 64-SiPM boards. Then it focuses in the development of the electronics needed to read the 1800 channels with a front-end board that includes per-channel differential transimpedance input amplifier, gated integrator, automatic offset voltage compensation and 12-bit ADC. Finally, a description of how the FPGA buffers data, carries out zero suppression and sends data to the DAQ interface using CERN RD-51 SRS's DTCC link specification complements the description of the electronics of the NEW detector tracking plane

The read-out electronics of the AMS prototype RICH detector

International Nuclear Information System (INIS)

Gallin-Martel, L.; Eraud, L.; Pouxe, J.; Aguayo de Hoyos, P.; Marin Munoz, J.; Martinez Botella, G.

2003-01-01

A Ring Imaging Cherenkov (RICH) counter dedicated to the AMS experiment is under development. An integrated circuit has been designed with the Austriamicrosystems 0.6 πm CMOS technology to process the signals of the 16 anode PMTs used in the photon detection. To improve the detector compactness, the read out electronics is placed very close to the PMTs. This lead to the design of a detection cell that comprises: a light guide, a PMT, a high voltage divider, an analog front end chip and an analog to digital converter. The analog front-end chips were extensively and successfully tested in a laboratory environment, 96 of them are now mounted on the RICH prototype. Tests with cosmic rays have started. Ion beam tests are planed in a near future. (authors)

Testing and commissioning of the LHCb Outer Tracker front-end electronic and a study for a background estimation in the decay B{sup 0}{sub s} {yields} J/{psi} {phi}; Tests und Inbetriebnahme der LHCb Outer Tracker Front-end Elektronik und eine Studie zur Abschaetzung des Untergrundes im Zerfall B{sup 0}{sub s} {yields} J/{psi} {phi}

Energy Technology Data Exchange (ETDEWEB)

Knopf, Jan

2009-07-08

The readout electronic of the LHCb outer tracker measures the drift time of a straw tube. The front-end electronic consists of three radiation hard chips. The ASDBLR preamplifier amplifies and discriminates the charge puls produced by the drift chamber. The OTIS-TDC chip measures the drift time every 25 ns on 32 detector channels. The generated data is send via an optical link with 1.6 GBit/s, making use of the GOL chip. The main part of this thesis is dedicated to the testing and commissioning of the outer tracker front-end electronic. Altogether three test systems were developed and operated. The first test system was built to thoroughly check the features of the OTIS-TDC chips on the wafer. The quality of the OTIS board and GOL-Aux board production was checked with another test system. The front-end electronic was also combined and tested to the LHCB readout chain. One of the main goals of the LHCb experiment is the measurement of the CP-violating phase {phi}{sub s}. It can be measured by using the golden decay mode B{sup 0}{sub s} {yields} J/{psi} {phi}. It is vital to have a good knowledge about the background for this decay in order to extract the phase. In this thesis a study was performed to overcome the current limitations due to low Monte-Carlo statistics in this area. (orig.)

Prototype ALICE front-end card

CERN Multimedia

Maximilien Brice

2004-01-01

This circuit board is a prototype 48-channel front end digitizer card for the ALICE time projection chamber (TPC), which takes electrical signals from the wire sensors in the TPC and shapes the data before converting the analogue signal to digital data. A total of 4356 cards will be required to process the data from the ALICE TPC, the largest of this type of detector in the world.

Data acquisition at the front-end of the Mu3e pixel detector

Energy Technology Data Exchange (ETDEWEB)

Perrevoort, Ann-Kathrin [Physikalisches Institut, Universitaet Heidelberg (Germany); Collaboration: Mu3e-Collaboration

2016-07-01

The Mu3e experiment - searching for the lepton-flavour violating decay of the muon into three electrons at an unprecedented sensitivity of one in 10{sup 16} decays - is based on a pixel tracking detector. The sensors are High-Voltage Monolithic Active Pixel Sensors, a technology which allows for very fast and thin detectors, and thus is an ideal fit for Mu3e where the trajectories of low-momentum electrons at high rates are to be measured. The detector will consist of about 275 million pixels and will be operated at up to 10{sup 9} muon stops per second. Therefore, a fast and trigger-less data readout is required. The pixel sensors feature zero-suppressed data output via high-speed serial links. The data is then buffered and sorted by time on a FPGA on the front-end before being processed to the following readout stage. In this talk, the readout of the Mu3e pixel detector at the front-end is introduced. Furthermore, a first firmware implementation of this concept in a beam telescope consisting of the current pixel sensor prototype MuPix7 is presented.

HINS Linac front end focusing system R&D

Energy Technology Data Exchange (ETDEWEB)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; /Fermilab /Argonne

2008-08-01

This report summarizes current status of an R&D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process.

Low-power analog integrated circuits for wireless ECG acquisition systems.

Science.gov (United States)

Tsai, Tsung-Heng; Hong, Jia-Hua; Wang, Liang-Hung; Lee, Shuenn-Yuh

2012-09-01

This paper presents low-power analog ICs for wireless ECG acquisition systems. Considering the power-efficient communication in the body sensor network, the required low-power analog ICs are developed for a healthcare system through miniaturization and system integration. To acquire the ECG signal, a low-power analog front-end system, including an ECG signal acquisition board, an on-chip low-pass filter, and an on-chip successive-approximation analog-to-digital converter for portable ECG detection devices is presented. A quadrature CMOS voltage-controlled oscillator and a 2.4 GHz direct-conversion transmitter with a power amplifier and upconversion mixer are also developed to transmit the ECG signal through wireless communication. In the receiver, a 2.4 GHz fully integrated CMOS RF front end with a low-noise amplifier, differential power splitter, and quadrature mixer based on current-reused folded architecture is proposed. The circuits have been implemented to meet the specifications of the IEEE 802.15.4 2.4 GHz standard. The low-power ICs of the wireless ECG acquisition systems have been fabricated using a 0.18 μm Taiwan Semiconductor Manufacturing Company (TSMC) CMOS standard process. The measured results on the human body reveal that ECG signals can be acquired effectively by the proposed low-power analog front-end ICs.

Front end designs for the 7-GeV advanced photon source

International Nuclear Information System (INIS)

Shu, D.; Barraza, J.; Sanchez, T.; Nielsen, R.W.; Collins, J.T.; Kuzay, T.M.

1992-01-01

The conceptual designs for the insertion device (ID) and bending magnet (BM) front ends have been completed for the 7-GeV Advanced Photon Source (APS) under construction at Argonne National Laboratory. These designs satisfy the generic front end functions. However, the high power and high heat fluxes imposed by the X-ray sources of the 7-GeV APS have presented various design engineering challenges for the front end. Consideration of such challenges and their solutions have led to novel and advanced features including modularized systems, enhanced heat transfer concepts in the fixed mask and the photon shutter designs, a radiation safety philosophy based on multiple photon shutters for a fail-safe operation, a sub-micron resolution beam position monitor for beam monitoring and ring feedback information, and minimal beam filtering concepts to deliver maximized beam power and spectra to the experimenters. The criteria and special features of the front end design are discussed in this paper

Magnet Misalignment Studies for the Front-end of the Neutrino Factory

CERN Document Server

Prior, G; Stratakis, D; Neuffer, D; Snopok, P; Rogers, C

2013-01-01

In the Neutrino Factory front-end the muon beam coming from the interaction of a high-power (4 MW) proton beam on a mercury jet target is transformed through a buncher, a phase rotator and an ionization cooling channel before entering the downstream acceleration system. The muon front-end channel is densely packed with solenoid magnets, normal conducting radio-frequency cavities and absorber windows for the cooling section. The tolerance to the misalignment of the different components has to be determined in order on one hand to set the limits beyond which the performance of the front-end channel would be degraded; on the other hand to optimize the design and assembly of the front-end cells such that the component alignment can be checked and corrected for where crucial for the performance of the channel. In this paper we show the results of some of the simulations of the frontend channel performance where the magnetic field direction has been altered compared to the baseline.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

Science.gov (United States)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ˜ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0.

Control and Interlocking System for Bending Magnet Front-end at Indus-2

International Nuclear Information System (INIS)

Kane, Sanjeev R.; Garg, Chander Kant; Nandedkar, R. V.

2007-01-01

We present control and interlock system developed for Indus-2 bending magnet front-end. The paper describes in detail the control of various signals associated with the front-end and the interlocking scheme implemented for the installed front-end. The number of signals associated with each front-end is ∼ 75. A control system is designed for monitoring temperature, pressure, airflow, water flow and control of vacuum gauges, fast shutter, water cooled shutter, safety shutter, pneumatic gate valves, sputter ion pump power supplies, beam position monitor etc. Two independent signals are generated for critical components that are used for software interlock and hard-wired interlock. The front-end control system is VME based and window 2000/XP workstation as an operator console. The CPU used is Motorola 68000-processor board of the VME bus having OS-9 real time operating system. One VME crate serves a cluster of 2-3 front ends. The communication between the VME and the workstation is linked over RS232 serial communication. The sputter ion power supplies are connected over isolated RS485 network. Critical protection features are implemented so that no single failure can render the system unsafe. This is implemented by providing two independent chains of protection (1) Hard wired in which relay logic is used and (2) Software. A Graphical User Interface (GUI) is developed using Lab view Version 7.0

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

Energy Technology Data Exchange (ETDEWEB)

Blaha, J. [Czech Technical University in Prague, CTU, Praha (Czech Republic); Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France)], E-mail: j.blaha@ipnl.in2p3.fr; Cartiglia, N. [Instituto Nazionale di Fisica Nucleare, INFN, Torino (Italy); Combaret, C. [Czech Technical University in Prague, CTU, Praha (Czech Republic); Fay, J. [Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France); Lustermann, W. [Eidgenossische Technische Hoschschule, ETH, Zuerich (Switzerland); Maurelli, G. [Institut de Physique Nucleaire de Lyon - IN2P3/CNRS and Universite Claude Bernard Lyon 1, Villeurbanne (France); Nardulli, A. [Eidgenossische Technische Hoschschule, ETH, Zuerich (Switzerland); Obertino, M. [Instituto Nazionale di Fisica Nucleare, INFN, Torino (Italy)

2007-10-15

The Very-Front-End cards processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee their functionality and reliability. The characteristics of the VFE cards designed for the calorimeter barrel are presented. The results confirm the high quality of the cards production and show that the specifications are fully reached.

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

International Nuclear Information System (INIS)

Blaha, J.; Cartiglia, N.; Combaret, C.; Fay, J.; Lustermann, W.; Maurelli, G.; Nardulli, A.; Obertino, M.

2007-01-01

The Very-Front-End cards processing signal from photodetectors of the CMS electromagnetic calorimeter, have been put through extensive test program to guarantee their functionality and reliability. The characteristics of the VFE cards designed for the calorimeter barrel are presented. The results confirm the high quality of the cards production and show that the specifications are fully reached

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Science.gov (United States)

Ciciriello, F.; Corsi, F.; De Robertis, G.; Felici, G.; Loddo, F.; Marzocca, C.; Matarrese, G.; Ranieri, A.

2016-07-01

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e- for a detector capacitance of 10 pF.

A new front-end ASIC for GEM detectors with time and charge measurement capabilities

Energy Technology Data Exchange (ETDEWEB)

Ciciriello, F., E-mail: fabio.ciciriello@poliba.it [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Corsi, F. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); De Robertis, G. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Felici, G. [INFN, Laboratori Nazionali di Frascati, Via E. Fermi 40, I-00044 Frascati (Italy); Loddo, F. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Marzocca, C.; Matarrese, G. [DEI-Politecnico di Bari, Via Orabona 4, I-70125 Bari (Italy); INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy); Ranieri, A. [INFN, Sezione di Bari, Via Orabona 4, I-70125 Bari (Italy)

2016-07-11

A 32 channel CMOS front-end ASIC has been designed to read out the GEM detectors intended to be used for beam monitoring in a new proton-therapy facility currently under construction. In order to improve the spatial resolution by exploiting charge centroid algorithms, the analog channels, based on the classic CSA+shaper architecture, are equipped with a peak detector (PD) which works as an analog memory during the read-out phase. The outputs of the PDs are multiplexed towards an integrated 8-bit subranging ADC. An accurate trigger signal marks the arrival of a valid event and is generated by fast-ORing the outputs of 32 voltage discriminators which compare the shaper outputs with a programmable threshold. The digital part of the ASIC manages the read-out of the channels, the A/D conversion and the configuration of the ASIC. A 100 Mbit/s LVDS serial link is used for data communication. The sensitivity of the analog channel is 15 mV/fC and the dynamic range is 80 fC. The simulated ENC is about 650 e{sup −} for a detector capacitance of 10 pF. © 2001 Elsevier Science. All rights reserved.

Measurement of Design Process Front-End – Radical Innovation Approach

DEFF Research Database (Denmark)

Berg, Pekka; Pihlajamaa, Jussi; Hansen, Poul H. Kyvsgård

2014-01-01

The overall structure and the main characteristics of the future product are all decided in the front-end phase, which then strongly affects subsequent new product development activities. Recent studies indicate that these early front-end activities represent the most troublesome phase...... of the innovation process, and at the same time one of the greatest opportunities to improve the overall innovation capability of a company. In this paper dealing with the criteria we concentrate only for the objectives viewpoint and leave the attributes discussion to the future research. Two most crucial questions...... the innovation activities front end contains five assessment viewpoints as follows; input, process, output (including impacts), social environment and structural environment. Based on the results from our first managerial implications in three Finnish manufacturing companies we argue, that the developed model...

Design and Test of a 65nm CMOS Front-End with Zero Dead Time for Next Generation Pixel Detectors

Energy Technology Data Exchange (ETDEWEB)

Gaioni, L. [INFN, Pavia; Braga, D. [Fermilab; Christian, D. [Fermilab; Deptuch, G. [Fermilab; Fahim. F., Fahim. F. [Fermilab; Nodari, B. [Lyon, IPN; Ratti, L. [INFN, Pavia; Re, V. [INFN, Pavia; Zimmerman, T. [Fermilab

2017-09-01

This work is concerned with the experimental characterization of a synchronous analog processor with zero dead time developed in a 65 nm CMOS technology, conceived for pixel detectors at the HL-LHC experiment upgrades. It includes a low noise, fast charge sensitive amplifier with detector leakage compensation circuit, and a compact, single ended comparator able to correctly process hits belonging to two consecutive bunch crossing periods. A 2-bit Flash ADC is exploited for digital conversion immediately after the preamplifier. A description of the circuits integrated in the front-end processor and the initial characterization results are provided

Optimized capture section for a muon accelerator front end

Directory of Open Access Journals (Sweden)

Hisham Kamal Sayed

2014-07-01

Full Text Available In a muon accelerator complex, a target is bombarded by a multi-MW proton beam to produce pions, which decay into the muons which are thereafter bunched, cooled, and accelerated. The front end of the complex captures those pions, then manipulates their phase space, and that of the muons into which they decay, to maximize the number of muons within the acceptance of the downstream systems. The secondary pion beam produced at the target is captured by a high field target solenoid that tapers down to a constant field throughout the rest of the front end. In this study we enhance the useful muon flux by introducing a new design of the longitudinal profile of the solenoid field at, and downstream of, the target. We find that the useful muon flux exiting the front end is larger when the field at the target is higher, the distance over which the field tapers down is shorter, and the field at the end of the taper is higher. We describe how the solenoid field profile impacts the transverse and longitudinal phase space of the beam and thereby leads to these dependencies.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

International Nuclear Information System (INIS)

Belver, D.; Cabanelas, P.; Castro, E.; Diaz, J.; Garzon, J.A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-01-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m 2 with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12 C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

Performances of the Front-End Electronics for the HADES RPC TOF wall on a 12C beam

Science.gov (United States)

Belver, D.; Cabanelas, P.; Castro, E.; Díaz, J.; Garzón, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.; Zapata, M.

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8 m with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a 12C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

A wide dynamic range BF{sub 3} neutron monitor with front-end electronics based on a logarithmic amplifier

Energy Technology Data Exchange (ETDEWEB)

Ferrarini, M., E-mail: michele.ferrarini@polimi.i [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Fondazione CNAO, via Caminadella 16, 20123 Milano (Italy); Varoli, V. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Favalli, A. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Vatican City State, Holy See) (Italy); Caresana, M. [Politecnico di Milano, Dipartimento Energia, via G. Ponzio 34/3, I-20133 Milano (Italy); Pedersen, B. [European Commission, Joint Research Centre, Institute for the Protection and Security of Citizen, TP 800, Via E. Fermi, 21027 Ispra (Italy)

2010-02-01

This paper describes a wide dynamic range neutron monitor based on a BF{sub 3} neutron detector. The detector is used in current mode, and front-end electronics based on a logarithmic amplifier are used in order to have a measurement capability ranging over many orders of magnitude. The system has been calibrated at the Polytechnic of Milan, CESNEF, with an AmBe neutron source, and has been tested in a pulsed field at the PUNITA facility at JRC, Ispra. The detector has achieved a dynamic range of over 6 orders of magnitude, being able to measure single neutron pulses and showing saturation-free response for a reaction rate up to 10{sup 6} s{sup -1}. It has also proved effective in measuring the PUNITA facility pulse integral fluence.

Wide-band low-noise distributed front-end for multi-gigabit CPFSK receivers

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Ebskamp, F; Pedersen, Rune Johan Skullerud

1994-01-01

In this paper a distributed optical front-end amplifier for a coherent optical CPFSK receiver is presented. The measured average input noise current density is 20 pA/√(Hz) in a 3-13 GHz bandwidth. This is the lowest value reported for a distributed optical front-end in this frequency range....... The front-end is tested in a system set-up at a bit rate of 2.5 Gbit/s and a receiver sensitivity of -41.5 dBm is achieved at a 10-9 bit error rate...

Radiological and environmental surveillance in front-end fuel cycle facilities

International Nuclear Information System (INIS)

Khan, A.H.; Sahoo, S.K.; Tripathi, R.M.

2004-01-01

This paper describes the occupational and environmental radiological safety measures associated with the operations of front end nuclear fuel cycle. Radiological monitoring in the facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised

FERMI: a digital Front End and Readout MIcrosystem for high resolution calorimetry

International Nuclear Information System (INIS)

Alexanian, H.; Appelquist, G.; Bailly, P.

1995-01-01

We present a digital solution for the front-end electronics of high resolution calorimeters at future colliders. It is based on analogue signal compression, high speed A/D converters, a fully programmable pipeline and a digital signal processing (DSP) chain with local intelligence and system supervision. This digital solution is aimed at providing maximal front-end processing power by performing waveform analysis using DSP methods. For the system integration of the multichannel device a multi-chip, silicon-on-silicon multi-chip module (MCM) has been adopted. This solution allows a high level of integration of complex analogue and digital functions, with excellent flexibility in mixing technologies for the different functional blocks. This type of multichip integration provides a high degree of reliability and programmability at both the function and the system level, with the additional possibility of customising the microsystem to detector-specific requirements. For enhanced reliability in high radiation environments, fault tolerance strategies, i.e. redundancy, reconfigurability, majority voting and coding for error detection and correction, are integrated into the design. ((orig.))

A THEORETICAL MODEL OF SUPPORTING OPEN SOURCE FRONT END INNOVATION THROUGH IDEA MANAGEMENT

DEFF Research Database (Denmark)

Aagaard, Annabeth

2013-01-01

to overcome these various challenges companies are looking for new models to support FEI. This theoretical paper explores in what way idea management may be applied as a tool in facilitation of front end innovation and how this facilitation may be captured in a conceptual model. First, I show through...... a literature study, how idea management and front end innovation are related and how they may support each other. Secondly, I present a theoretical model of how idea management may be applied in support of the open source front end of new product innovations. Thirdly, I present different venues of further...... exploration of active facilitation of open source front end innovation through idea management....

Integrated X-band FMCW front-end in SiGe BiCMOS

NARCIS (Netherlands)

Suijker, Erwin; de Boer, Lex; Visser, Guido; van Dijk, Raymond; Poschmann, Michael; van Vliet, Frank Edward

2010-01-01

An integrated X-band FMCW front-end is reported. The front-end unites the core functionality of an FMCW transmitter and receiver in a 0.25 μm SiGe BiCMOS process. The chip integrates a PLL for the carrier generation, and single-side band and image-reject mixers for up- and down-conversion of the

Performance of the Low-Jitter High-Gain/Bandwidth Front-End Electronics of the HADES tRPC Wall

Science.gov (United States)

Belver, Daniel; Cabanelas, P.; Castro, E.; Garzon, J. A.; Gil, A.; Gonzalez-Diaz, D.; Koenig, W.; Traxler, M.

2010-10-01

A front-end electronics (FEE) chain for accurate time measurements has been developed for the new Resistive Plate Chamber (RPC)-based Time-of-Flight (TOF) wall of the High Acceptance Di-Electron Spectrometer (HADES). The wall covers an area of around 8 m2, divided in 6 sectors. In total, 1122 4-gap timing RPC cells are read-out by 2244 time and charge sensitive channels. The FEE chain consists of 2 custom-made boards: a 4-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a dual high-speed discriminator. The time and charge information are encoded, respectively, in the leading edge and the width of an LVDS signal. Each MBO houses up to 8 DBOs providing them regulated voltage supply, threshold values via DACs, test signals and, additionally, routing out a signal proportional to the channel multiplicity needed for a 1st level trigger decision. The MBO delivers LVDS signals to a multi-purpose Trigger Readout Board (TRB) for data acquisition. The FEE allows achieving a system resolution around 75 ps fulfilling comfortably the requirements of the HADES upgrade .

Analog and mixed-signal electronics

CERN Document Server

Stephan, Karl

2015-01-01

A practical guide to analog and mixed-signal electronics, with an emphasis on design problems and applications This book provides an in-depth coverage of essential analog and mixed-signal topics such as power amplifiers, active filters, noise and dynamic range, analog-to-digital and digital-to-analog conversion techniques, phase-locked loops, and switching power supplies. Readers will learn the basics of linear systems, types of nonlinearities and their effects, op-amp circuits, the high-gain analog filter-amplifier, and signal generation. The author uses system design examples to motivate

A multitasking, multisinked, multiprocessor data acquisition front end

International Nuclear Information System (INIS)

Fox, R.; Au, R.; Molen, A.V.

1989-01-01

The authors have developed a generalized data acquisition front end system which is based on MC68020 processors running a commercial real time kernel (rhoSOS), and implemented primarily in a high level language (C). This system has been attached to the back end on-line computing system at NSCL via our high performance ETHERNET protocol. Data may be simultaneously sent to any number of back end systems. Fixed fraction sampling along links to back end computing is also supported. A nonprocedural program generator simplifies the development of experiment specific code

An Analog Computer for Electronic Engineering Education

Science.gov (United States)

Fitch, A. L.; Iu, H. H. C.; Lu, D. D. C.

2011-01-01

This paper describes a compact analog computer and proposes its use in electronic engineering teaching laboratories to develop student understanding of applications in analog electronics, electronic components, engineering mathematics, control engineering, safe laboratory and workshop practices, circuit construction, testing, and maintenance. The…

Performances of the Front-End Electronics for the HADES RPC TOF wall on a {sup 12}C beam

Energy Technology Data Exchange (ETDEWEB)

Belver, D. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)], E-mail: danielbf@usc.es; Cabanelas, P.; Castro, E. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Diaz, J. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Garzon, J.A. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain); Gil, A. [Instituto de Fisica Corpuscular, CSIC-Universidad de Valencia, Valencia 46071 (Spain); Gonzalez-Diaz, D.; Koenig, W.; Traxler, M. [Gesellschaft fuer Schwerionenforschung, GSI, 64291 Darmstadt (Germany); Zapata, M. [LabCAF, USC, Universidade de Santiago de Compostela, Dep. de Fisica de Particulas, Santiago de Compostela 15782 (Spain)

2009-05-01

A Front-End Electronics (FEE) chain for timing accurate measurements has been developed for the RPC wall upgrade of the High-Acceptance DiElectron Spectrometer (HADES). The wall will cover an area of around 8m{sup 2} with 1122 RPC cells (2244 electronic channels). The FEE chain consists of two boards: a four-channel DaughterBOard (DBO) and a 32-channel MotherBOard (MBO). The DBO uses a fast 2 GHz amplifier feeding a discriminator. The time and the charge information are encoded in the leading and the trailing edge (by a charge to width method) of an LVDS signal. Each MBO houses up to eight DBOs providing them regulated voltage supply, threshold values via DACs, test signals and collection of their trigger outputs. The MBO delivers LVDS signals to a time-to-digital converter readout board (TRB) based on HPTDC for data acquisition. In this work, we present the performance of the FEE measured using: (a) narrow electronic test pulses and (b) real signals read out in a fully instrumented RPC sextant installed in its final position at the HADES. The detector was exposed to particles coming from reactions of a {sup 12}C beam on Be and Nb targets at 2 GeV/A kinetic energy. Results for the whole electronic chain (DBO+MBO+TRB) show a timing jitter of around 40 ps/channel for pulses above 100 fC and 80 ps/channel for beam data taken with the RPC.

HINS Linac front end focusing system R and D

International Nuclear Information System (INIS)

Apollinari, G.; Carcagno, R.H.; Dimarco, J.; Huang, Y.; Kashikhin, V.V.; Orris, D.F.; Page, T.M.; Rabehl, R.; Sylvester, C.; Tartaglia, M.A.; Terechkine, I.; Fermilab; Argonne

2008-01-01

This report summarizes current status of an R and D program to develop a focusing system for the front end of a superconducting RF linac. Superconducting solenoids will be used as focusing lenses in the low energy accelerating sections of the front end. The development of focusing lenses for the first accelerating section is in the production stage, and lens certification activities are in preparation at FNAL. The report contains information about the focusing lens design and performance, including solenoid, dipole corrector, and power leads, and about cryogenic system design and performance. It also describes the lens magnetic axis position measurement technique and discusses scope of an acceptance/certification process

The OPERA RPCs front end electronics; a novel application of LVDS line receiver as low cost discriminator

International Nuclear Information System (INIS)

Balsamo, E; Bergnoli, A; Bertolin, A; Brugnera, R; Carrara, E; Ciesielski, R; Dal Corso, F; Dusini, S; Garfagnini, A; Kose, U; Longhin, A; Medinaceli, E; Stanco, L

2012-01-01

The OPERA spectrometer is built from two large dipoles instrumented with around 1000 Resistive Plate Chambers (RPCs), covering a surface of about 3350 m 2 , and digitally read out by means of almost 27000 strips. The huge number of channels, the inaccessibility of many parts of the detector and the wide uncertainty about the signal amplitude pushed to study a low cost, high sensitivity discriminator, and a very carefully designed layout for the read out system. Here we will present a novel application of LVDS line receiver as discriminator, showing that it exceeds the requirements of a large RPC based detector and offers the intrinsic advantages of a mature technology in terms of costs, reliability and integration scale. We will also present the layout of the read out system showing as the sensitivity and the noise immunity were preserved in a system where the front end electronics is far away from the detector.

High Dynamic Range RF Front End with Noise Cancellation and Linearization for WiMAX Receivers

Directory of Open Access Journals (Sweden)

J.-M. Wu

2012-06-01

Full Text Available This research deals with verification of the high dynamic range for a heterodyne radio frequency (RF front end. A 2.6 GHz RF front end is designed and implemented in a hybrid microwave integrated circuit (HMIC for worldwide interoperability for microwave access (WiMAX receivers. The heterodyne RF front end consists of a low-noise amplifier (LNA with noise cancellation, an RF bandpass filter (BPF, a downconverter with linearization, and an intermediate frequency (IF BPF. A noise canceling technique used in the low-noise amplifier eliminates a thermal noise and then reduces the noise figure (NF of the RF front end by 0.9 dB. Use of a downconverter with diode linearizer also compensates for gain compression, which increases the input-referred third-order intercept point (IIP3 of the RF front end by 4.3 dB. The proposed method substantially increases the spurious-free dynamic range (DRf of the RF front end by 3.5 dB.

Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

de La Taille, C

2008-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

A mixed analog-digital radiation hard technology for high energy physics electronics DMILL (Durci Mixte sur Isolant Logico-Linéaire)

CERN Document Server

Beuville, E; Borgeaud, P; Fourches, N T; Rouger, M; Blanc, J P; Bruel, M; Delevoye-Orsier, E; Gautier, J; Du Port de Pontcharra, J; Truche, R; Dupont-Nivet, E; Flament, O; Leray, J L; Martin, J L; Montaron, J; Borel, G; Brice, J M; Chatagnon, P; Terrier, C; Aubert, Jean-Jacques; Delpierre, P A; Habrard, M C; Potheau, R; CERN. Geneva. Detector Research and Development Committee

1992-01-01

The high radiation level expected in the inner regions of the high luminosity LHC detectors (gamma and neutron) will require radiation hardened electronics. A consortium between the CEA (Commissariat a l'Energie Atomique) and Thomson TMS (Thomson Composants Militaires et Spatiaux) has been created to push for the development and the industrialization of a nascent technology which looks particularly adapted to the needs of HEP electronics. This technology, currently under development at the LETI(CEA), uses a SIMOX substrate with an epitaxial silicon film. It includes CMOS, JFETs and vertical bipolar transistors with a potential multi-megarad hardness. The CMOS and bipolar transistors constitute a rad-hard BiCMOS which will be useful to design analog and digital high-speed architectures. JFETs, which have intrinsically high hardness behaviour and low noise performances even at low temperature will enable very rad-hard, low noise front end electronics to be designed. Present results, together with the improvemen...

The new version of the LHCb SOL40-SCA core to drive front-end GBT-SCAs for the LHCb upgrade

CERN Document Server

Viana Barbosa, Joao Vitor; Gaspar, Clara

2018-01-01

The LHCb experiment is currently engaged in an upgrade effort that will implement a triggerless 40 MHz readout system. The upgraded Front-End Electronics profit from the GBT chipset functionalities and bidirectional optical fibers for readout, control and synchronization. This paper describes the new version of the firmware core that transmits slow control information from the Control System to thousands of Front-End chips and discusses the implementation that expedites and makes the operation more versatile. The detailed architecture, original interaction with the software control system and integration within the LHCb upgraded architecture are described.

An updated front-end data link design for the Phase-2 upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design of the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS Tile Calorimeter (TileCal) for Phase-II. The new TileCal front-end comprises 1024 “mini-drawers” (MD) installed in 256 calorimeter modules. Each MD serves up to 12 PMT channels, with ADCs and calibration provided by one “main board” (MB) per MD. The DB is connected to the MB through a dense, high-speed FMC connector, and provides bi-directional multi-Gb/s optlcal links to the off-detector electronics for timing, control, and continuous high-speed readout of the ADC channels on the MB. The DB is designed for redundancy and fault-tolerance, and previous versions have already been successfully tested at CERN and elsewhere. The new revision includes Kintex Ultrascale+ FPGAs for improved link timing and radiation tolerance, an expanded role for the rad-tolerant GBTx ASICs, and a simpler design requiring fewer components and optical links.

Design of the Front-End Detector Control System of the ATLAS New Small Wheels

CERN Document Server

Koulouris, Aimilianos; The ATLAS collaboration

2017-01-01

The ATLAS experiment will be upgraded during the next LHC Long Shutdown (LS2). The flagship upgrade is the New Small Wheel (NSW), which consists of 2 disks of Muon Gas detectors. The detector technologies used are Micromegas (MM) and sTGC, providing a total of 16 layers of tracking and trigger. The Slow Control Adapter (SCA) is part of the GigaBit Transceiver (GBT) - “Radiation Hard Optical Link Project” family of chips designed at CERN, EP-ESE department, which will be used at the NSW upgrade. The SCA offers several interfaces to read analog and digital inputs, and configure front-end Readout ASICs, FPGAs, or other chips. This poster gives an overview of the system, data flow, and software developed for communicating with the SCA.

Fast CMOS binary front-end for silicon strip detectors at LHC experiments

CERN Document Server

Kaplon, Jan

2004-01-01

We present the design and the test results of a front-end circuit developed in a 0.25 mu m CMOS technology. The aim of this work is to study the performance of a deep submicron process in applications for fast binary front-end for silicon strip detectors. The channel comprises a fast transimpedance preamplifier working with an active feedback loop, two stages of the amplifier-integrator circuits providing 22 ns peaking time and two-stage differential discriminator. Particular effort has been made to minimize the current and the power consumption of the preamplifier, while keeping the required noise and timing performance. For a detector capacitance of 20 pF noise below 1500 e/sup -/ ENC has been achieved for 300 mu A bias current in the input transistor, which is comparable with levels achieved in the past for a front-end using bipolar input transistor. The total supply current of the front-end is 600 mu A and the power dissipation is 1.5 mW per channel. The offset spread of the comparator is below 3 mV rms.

A tunable RF Front-End with Narrowband Antennas for Mobile Devices

DEFF Research Database (Denmark)

Bahramzy, Pevand; Olesen, Poul; Madsen, Peter

2015-01-01

desensitization due to the Tx signal. The filters and antennas demonstrate tunability across multiple bands. System validation is detailed for LTE band I. Frequency response, as well as linearity measurements of the complete Tx and Rx front-end chains, show that the system requirements are fulfilled.......In conventional full-duplex radio communication systems, the transmitter (Tx) is active at the same time as the receiver (Rx). The isolation between the Tx and the Rx is ensured by duplex filters. However, an increasing number of long-term evolution (LTE) bands crave multiband operation. Therefore......, a new front-end architecture, addressing the increasing number of LTE bands, as well as multiple standards, is presented. In such an architecture, the Tx and Rx chains are separated throughout the front-end. Addition of bands is solved by making the antennas and filters tunable. Banks of duplex filters...

A study on the front-end VME system of BEPC II

International Nuclear Information System (INIS)

Wang Chunhong

2004-01-01

The front-end VME system is not only the heart of the control system, but also a real-time system. This paper describes the component of the front-end VME (Versa Module Eurocard) system including control computer and some related I/O modules. Particularly, the authors present a best solution for the problems about Vx-Works kernel and BSP running on MVME5100. This is a fundamental setup of the BEPC II control system. (author)

A 500μW 5Mbps ULP super-regenerative RF front-end

NARCIS (Netherlands)

Vidojkovic, M.; Rampu, S.; Imamura, K.; Harpe, P.; Dolmans, G.; Groot, H. de

2010-01-01

This paper presents an ultra low power super-regenerative RF front-end for wireless body area network (WBAN) applications. The RF front-end operates in the 2.36-2.4 GHz medical BAN and 2.4-2.485 GHz ISM bands, and consumes 500 μW. It supports OOK modulation at high data rates ranging from 1-5 Mbps.

Functional description of APS beamline front ends

International Nuclear Information System (INIS)

Kuzay, T.

1993-02-01

Traditional synchrotron sources were designed to produce bending magnet radiation and have proven to be an essential scientific tool. Currently, a new generation of synchrotron sources is being built that will be able to accommodate a large number of insertion device (ID) and high quality bending magnet (BM) sources. One example is the 7-GeV Advanced Photon Source (APS) now under construction at Argonne National Laboratory. The research and development effort at the APS is designed to fully develop the potential of this new generation of synchrotron sources. Of the 40 straight sections in the APS storage ring, 34 will be available for IDs. The remaining six sections are reserved for the storage ring hardware and diagnostics. Although the ring incorporates 80 BMs, only 40 of them can be used to extract radiation. The accelerator hardware shadows five of these 40 bending magnets, so the maximum number of BM sources on the lattice is 35. Generally, a photon beamline consists of four functional sections. The first section is the ID or the BM, which provides the radiation source. The second section, which is immediately outside the storage ring but inside a concrete shielding tunnel, is the front end, which is designed to control, define, and/or confine the x-ray beam. In the case of the APS, the front ends are designed to confine the photon beam. The third section, just outside the concrete shielding tunnel and on the experimental floor, is the first optics enclosure, which contains optics to filter and monochromatize the photon beam. The fourth section of a beamline consists of beam transports, additional optics, and experiment stations to do the scientific investigations. This document describes only the front ends of the APS beamlines

Radiological and environmental safety in front-end fuel cycle facilities

International Nuclear Information System (INIS)

Puranik, V.D.

2011-01-01

The front end nuclear fuel cycle comprises of mining and processing of beach mineral sands along the southern coast of Kerala, Tamilnadu and Orissa, mining and processing of uranium ore in Singhbhum-East in Jharkhand and refining and fuel fabrication at Hyderabad. The Health Physics Units (HPUs)/Environmental Survey Laboratories (ESLs) set up at each site from inception of operation to carry out regular in-plant, personnel monitoring and environmental surveillance to ensure safe working conditions, evaluate radiation exposure of workers, ensure compliance with statutory norms, help in keeping the environmental releases well within the limits and advise appropriate control measures. This paper describes the occupational and environmental radiological safety measures associated with the operations of front end of nuclear fuel cycle. Radiological monitoring in these facilities is important to ensure safe working environment, protection of workers against exposure to radiation and comply with regulatory limits of exposure. The radiation exposure of workers in different units of the front end nuclear fuels cycle facilities operated by IREL, UCIL and NFC and environmental monitoring results are summarised in this paper

Design and characterization of integrated front-end transistors in a micro-strip detector technology

International Nuclear Information System (INIS)

Simi, G.; Angelini, C.; Batignani, G.; Bettarini, S.; Bondioli, M.; Boscardin, M.; Bosisio, L.; Dalla Betta, G.-F.; Dittongo, S.; Forti, F.; Giorgi, M.; Gregori, P.; Manghisoni, M.; Morganti, M.; U. Pignatel, G.; Ratti, L.; Re, V.; Rizzo, G.; Speziali, V.; Zorzi, N.

2002-01-01

We present the developments in a research program aimed at the realization of silicon micro-strip detectors with front-end electronics integrated in a high resistivity substrate to be used in high-energy physics, space and medical/industrial imaging applications. We report on the fabrication process developed at IRST (Trento, Italy), the characterization of the basic wafer parameters and measurements of the relevant working characteristics of the integrated transistors and related test structures

Calibration and performance test of the Very-Front-End electronics for the CMS electromagnetic calorimeter

International Nuclear Information System (INIS)

Blaha, J.

2008-05-01

A Very-Front-End (VFE) card is an important part of the on-detector read-out electronics of the CMS (Compact Muon Solenoid) electromagnetic calorimeter that is made of ∼ 76.000 radiation hard scintillating crystals PbWO 4 and operates on the Large Hadron Collider (LHC) at CERN. Almost 16.000 VFE cards that shape, amplify and digitize incoming signals from photodetectors generated by interacting particles. Since any maintenance of any part of the calorimeter is not possible during the 10-year lifetime of the experiment, the extensive screening program was employed throughout the whole manufacture process. As a part of readout electronics quality assurance program, the systems for burn-in and precise calibration of the VFE boards were developed and successfully used at IPN Lyon. In addition to functionality tests, all relevant electrical properties of each card were measured and analyzed in detail to obtain their full characterization and to build a database with all required parameters which will serve for the initial calibration of the whole calorimeter. In order to evaluate the calorimeter performance and also to deliver the most precise calibration constants, several fully equipped super-modules were extensively studied and calibrated during the test beam campaigns at CERN. As an important part of these tests, accurate studies of the electronics noise and relative gains, which are needed for measurement in high energy range, were carried out to optimize amplitude reconstruction procedure and thus improve the precision of the calorimeter energy determination. The heart of the thesis consists of the calibration of all VFE boards, including optimization of the laboratory calibration system and precise analysis of measured values to delivered desired calibration constants. The second half of the thesis is focused on the accurate evaluation and optimization of the read-out electronics in real data taking conditions. The results obtained in the laboratory at IPN Lyon

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

Science.gov (United States)

Prele, D.

2015-08-01

As we have seen for digital camera market and a sensor resolution increasing to "megapixels", all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, "simple" and "efficient" techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described.

Front-end multiplexing—applied to SQUID multiplexing: Athena X-IFU and QUBIC experiments

International Nuclear Information System (INIS)

Prele, D.

2015-01-01

As we have seen for digital camera market and a sensor resolution increasing to 'megapixels', all the scientific and high-tech imagers (whatever the wave length - from radio to X-ray range) tends also to always increases the pixels number. So the constraints on front-end signals transmission increase too. An almost unavoidable solution to simplify integration of large arrays of pixels is front-end multiplexing. Moreover, 'simple' and 'efficient' techniques allow integration of read-out multiplexers in the focal plane itself. For instance, CCD (Charge Coupled Device) technology has boost number of pixels in digital camera. Indeed, this is exactly a planar technology which integrates both the sensors and a front-end multiplexed readout. In this context, front-end multiplexing techniques will be discussed for a better understanding of their advantages and their limits. Finally, the cases of astronomical instruments in the millimeter and in the X-ray ranges using SQUID (Superconducting QUantum Interference Device) will be described

Front-end counting mode electronics for CdZnTe sensor readout

CERN Document Server

Moraes, Danielle; Kaplon, Jan

2004-01-01

The development of a front-end circuit optimized for CdZnTe detector readout, implemented in 0.25 mu m CMOS technology, is reported. The ASIC comprises 17 channels of a charge sensitive amplifier with an active feedback, followed by a gain-shaper stage and a discriminator with a 5 bit fine-tune DAC. The signal from the discriminator is sensed by a 25 ns mono-stable circuit and an 18-bit static ripple- counter. The channel architecture is optimized for the detector characteristics in order to achieve the best energy resolution at a maximum counting rate of 2 million counts/second. The amplifier shows a linear sensitivity of 24 mV/fC with 50 ns peaking time and an equivalent noise charge of about 650 e/sup -/, for a detector capacitance of 10 pF. When connected to a 3*3*7 mm/sup 3/ CdZnTe detector the amplifier gain is about 8 mV/keV with a noise around 3.6 keV.

Resource intensities of the front end of the nuclear fuel cycle

International Nuclear Information System (INIS)

Schneider, E.; Phathanapirom, U.; Eggert, R.; Collins, J.

2013-01-01

This paper presents resource intensities, including direct and embodied energy consumption, land and water use, associated with the processes comprising the front end of the nuclear fuel cycle. These processes include uranium extraction, conversion, enrichment, fuel fabrication and depleted uranium de-conversion. To the extent feasible, these impacts are calculated based on data reported by operating facilities, with preference given to more recent data based on current technologies and regulations. All impacts are normalized per GWh of electricity produced. Uranium extraction is seen to be the most resource intensive front end process. Combined, the energy consumed by all front end processes is equal to less than 1% of the electricity produced by the uranium in a nuclear reactor. Land transformation and water withdrawals are calculated at 8.07 m 2 /GWh(e) and 1.37x10 5 l/GWh(e), respectively. Both are dominated by the requirements of uranium extraction, which accounts for over 70% of land use and nearly 90% of water use

Report on the value engineering workshop on APS beamline front ends

International Nuclear Information System (INIS)

Kuzay, T.

1993-01-01

A formal value engineering evaluation process was developed to address the front end components of the beamlines for the Advanced Photon Source (APS). This process (described in Section 2) involved an information phase, a creative phase, a judgment phase, a development phase, and a recommendation phase. Technical experts from other national laboratories and industry were invited to a two-day Value Engineering Workshop on November 5-6, 1992. The results of this Workshop are described in Section 4. Following the Workshop, various actions by the APS staff led to the redesign of the front end components, which are presented in Sections 5 and 6. The cost benefit analysis is presented in Section 7. It is important of realize that an added benefit of the Workshop was to obtain numerous design evaluations and enhancements of the front end components by experts in the field. As the design work proceeds to Title II completion, the APS staff is including many of these suggestions

Electronic devices for analog signal processing

CERN Document Server

Rybin, Yu K

2012-01-01

Electronic Devices for Analog Signal Processing is intended for engineers and post graduates and considers electronic devices applied to process analog signals in instrument making, automation, measurements, and other branches of technology. They perform various transformations of electrical signals: scaling, integration, logarithming, etc. The need in their deeper study is caused, on the one hand, by the extension of the forms of the input signal and increasing accuracy and performance of such devices, and on the other hand, new devices constantly emerge and are already widely used in practice, but no information about them are written in books on electronics. The basic approach of presenting the material in Electronic Devices for Analog Signal Processing can be formulated as follows: the study with help from self-education. While divided into seven chapters, each chapter contains theoretical material, examples of practical problems, questions and tests. The most difficult questions are marked by a diamon...

Digital front-end module (DFEM) series; Digital front end module (DFEM) series

Energy Technology Data Exchange (ETDEWEB)

NONE

2000-03-01

The digital front-end module (DFEM) is a module in which the processes ranging from the reception of digitally modulated radiofrequencies to the output of digital IF (Intermediate Frequency) signals or data streams are integrated. Beginning with a module for the MCNS (Multimedia Cable Network System) cable modem which was the first module in this business field approved by the Cable Labs, U.S., Toshiba has developed a series of DFEMs for various digital media for satellites, ground waves, and CATV (Cable Television) systems. The series is characterized by (1) the serialization of DFEMs compatible with various digital modulation techniques such as 8 PSK (Phase Shift Keying), OFDM (Orthogonal Frequency Division Multiplexing), and 256 QAM (Quadrature Amplitude Modulation), (2) easy connection with digital circuits thanks to the high shielding effect, and (3) the achievement of smaller size, higher performance, and lower power consumption. (translated by NEDO)

Flexible Frequency Discrimination Subsystems for Reconfigurable Radio Front Ends

Directory of Open Access Journals (Sweden)

Carey-Smith Bruce E

2005-01-01

Full Text Available The required flexibility of the software-defined radio front end may currently be met with better overall performance by employing tunable narrowband circuits rather than pursuing a truly wideband approach. A key component of narrowband transceivers is appropriate filtering to reduce spurious spectral content in the transmitter and limit out-of-band interference in the receiver. In this paper, recent advances in flexible, frequency-selective, circuit components applicable to reconfigurable SDR front ends are reviewed. The paper contains discussion regarding the filtering requirements in the SDR context and the use of intelligent, adaptive control to provide environment-aware frequency discrimination. Wide tuning-range frequency-selective circuit elements are surveyed including bandpass and bandstop filters and narrowband tunable antennas. The suitability of these elements to the mobile wireless SDR environment is discussed.

Managing Controversies in the Fuzzy Front End

DEFF Research Database (Denmark)

Christiansen, John K.; Gasparin, Marta

2016-01-01

. The analysis investigates the microprocesses around the controversies that emerge during the fuzzy front end of four products. Five different types of controversies are identified: profit, production, design, brand and customers/market. Each controversy represents a threat, but also an opportunity to search...... for new solutions in the unpredictable non-linear processes. The study uses an ethnographic approach using qualitative data from interviews, company documents, external communication and marketing material, minutes of meetings, informal conversations and observations. The analysis of four FFE processes...... demonstrates how the fuzzy front requires managers to deal with controversies that emerge from many different places and involve both human and non-human actors. Closing the controversies requires managers to take account of the situation, identify the problem that needs to be addressed, and initiate a search...

Preliminary cleaning tests on candidate materials for APS beamline and front end UHV components

International Nuclear Information System (INIS)

Nielsen, R.; Kuzay, T.M.

1992-01-01

Comparative cleaning tests have been done on four candidate materials for use in APS beamline and front-end vacuum components. These materials are 304 SS, 304L SS, OFHC copper, and Glidcop* (Cu-Al 2 O 3 )- Samples of each material were prepared and cleaned using two different methods. After cleaning, the sample surfaces were analyzed using ESCA (Electron Spectography for Chemical Analysis). Uncleaned samples were used as a reference. The cleaning methods and surface analysis results are further discussed

A 1.2-V CMOS front-end for LTE direct conversion SAW-less receiver

International Nuclear Information System (INIS)

Wang Riyan; Li Zhengping; Zhang Weifeng; Zeng Longyue; Huang Jiwei

2012-01-01

A CMOS RF front-end for the long-term evolution (LTE) direct conversion receiver is presented. With a low noise transconductance amplifier (LNA), current commutating passive mixer and transimpedance operational amplifier (TIA), the RF front-end structure enables high-integration, high linearity and simple frequency planning for LTE multi-band applications. Large variable gain is achieved using current-steering transconductance stages. A current commutating passive mixer with 25% duty-cycle LO improves gain, noise and linearity. A direct coupled current-input filter (DCF) is employed to suppress the out-of-band interferer. Fabricated in a 0.13-μm CMOS process, the RF front-end achieves a 45 dB conversion voltage gain, 2.7 dB NF, −7 dBm IIP3, and +60 dBm IIP2 with calibration from 2.3 to 2.7 GHz. The total RF front end with divider draws 40 mA from a single 1.2-V supply. (semiconductor integrated circuits)

Modern design of a fast front-end computer

Science.gov (United States)

Šoštarić, Z.; Anic̈ić, D.; Sekolec, L.; Su, J.

1994-12-01

Front-end computers (FEC) at Paul Scherrer Institut provide access to accelerator CAMAC-based sensors and actuators by way of a local area network. In the scope of the new generation FEC project, a front-end is regarded as a collection of services. The functionality of one such service is described in terms of Yourdon's environment, behaviour, processor and task models. The computational model (software representation of the environment) of the service is defined separately, using the information model of the Shlaer-Mellor method, and Sather OO language. In parallel with the analysis and later with the design, a suite of test programmes was developed to evaluate the feasibility of different computing platforms for the project and a set of rapid prototypes was produced to resolve different implementation issues. The past and future aspects of the project and its driving forces are presented. Justification of the choice of methodology, platform and requirement, is given. We conclude with a description of the present state, priorities and limitations of our project.

General design of the layout for new undulator-only beamline front ends

International Nuclear Information System (INIS)

Shu Deming; Ramanathan, Mohan; Kuzay, Tuncer M.

2001-01-01

A great majority of the Advanced Photon Source (APS) users have chosen an undulator as the only source for their insertion device beamline. Compared with a wiggler source, the undulator source has a much smaller horizontal divergence, providing us with an opportunity to optimize the beamline front-end design further. In this paper, the particular designs and specifications, as well as the optical and bremsstrahlung ray-tracing analysis of the new APS front ends for undulator-only operation are presented

Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

Directory of Open Access Journals (Sweden)

Jimmy Nsenga

2007-03-01

Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

Comparison of OQPSK and CPM for Communications at 60 GHz with a Nonideal Front End

Directory of Open Access Journals (Sweden)

Nsenga Jimmy

2007-01-01

Full Text Available Short-range digital communications at 60 GHz have recently received a lot of interest because of the huge bandwidth available at those frequencies. The capacity offered to the users could finally reach 2 Gbps, enabling the deployment of new multimedia applications. However, the design of analog components is critical, leading to a possible high nonideality of the front end (FE. The goal of this paper is to compare the suitability of two different air interfaces characterized by a low peak-to-average power ratio (PAPR to support communications at 60 GHz. On one hand, we study the offset-QPSK (OQPSK modulation combined with a channel frequency-domain equalization (FDE. On the other hand, we study the class of continuous phase modulations (CPM combined with a channel time-domain equalizer (TDE. We evaluate their performance in terms of bit error rate (BER considering a typical indoor propagation environment at 60 GHz. For both air interfaces, we analyze the degradation caused by the phase noise (PN coming from the local oscillators; and by the clipping and quantization errors caused by the analog-to-digital converter (ADC; and finally by the nonlinearity in the PA.

A socio-internactive framework for the fuzzy front end

NARCIS (Netherlands)

Smulders, Frido E.; van den Broek, Egon; van der Voort, Mascha C.; Fernandes, A.; Teixeira, A.; Natal Jorge, R.

2007-01-01

This paper aims to illustrate that the dominating rational-analytic perspective on the Fuzzy Front End (FFE) of innovation could benefit by a complementary socio-interactive perspective that addresses the social processes during the FFE. We have developed a still fledgling socio-interactive

A bipolar analog front-end integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1993-11-01

A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDC silicon tracker. The IC was designed and tested at LBL and was fabricated using AT ampersand T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16 nsec time-walk for 1.25 to 10fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a Φ=10 14 protons/cm 2 have been performed on the IC, demonstrating the radiation hardness of the complementary bipolar process

Digital column readout architecture for the ATLAS pixel 025 mum front end IC

CERN Document Server

Mandelli, E; Blanquart, L; Comes, G; Denes, P; Einsweiler, Kevin F; Fischer, P; Marchesini, R; Meddeler, G; Peric, I

2002-01-01

A fast low noise, limited power, radiation-hard front-end chip was developed for reading out the Atlas Pixel Silicon Detector. As in the past prototypes, every chip is used to digitize and read out charge and time information from hits on each one of its 2880 inputs. The basic column readout architecture idea was adopted and modified to allow a safe transition to quarter micron technology. Each pixel cell, organized in a 160 multiplied by 18 matrix, can be independently enabled and configured in order to optimize the analog signal response and to prevent defective pixels from saturating the readout. The digital readout organizes hit data coming from each column, with respect to time, and output them on a low-level serial interface. A considerable effort was made to design state machines free of undefined states, where single-point defects and charge deposited by heavy ions in the silicon could have led to unpredicted forbidden states. 7 Refs.

Practical analog electronics for technicians

CERN Document Server

Kimber, W A

2013-01-01

'Practical Analog Electronics for Technicians' not only provides an accessible introduction to electronics, but also supplies all the problems and practical activities needed to gain hands-on knowledge and experience. This emphasis on practice is surprisingly unusual in electronics texts, and has already gained Will Kimber popularity through the companion volume, 'Practical Digital Electronics for Technicians'. Written to cover the Advanced GNVQ optional unit in electronics, this book is also ideal for BTEC National, A-level electronics and City & Guilds courses. Together with 'Practical Digit

Numerical study of a magnetically insulated front-end channel for a neutrino factory

Directory of Open Access Journals (Sweden)

Diktys Stratakis

2011-01-01

Full Text Available A neutrino factory, which can deliver an intense flux of ∼10^{21} neutrinos per year from a multi-GeV stored muon beam, is seemingly the ideal tool for studying neutrino oscillations and CP violations for leptons. The front end of this facility plays a critical role in determining the number of muons that can be accepted by the downstream accelerators. Delivering peak performance requires transporting the muon beams through long sections of a beam channel containing high-gradient rf cavities and strong focusing solenoids. Here, we propose a novel scheme to improve the performance of the cavities, thereby increasing the number of muons within the acceptance of the accelerator chain. The key element of our new scheme is to apply a tangential magnetic field to the rf surfaces, thus forcing any field-emitted electrons to return to the surface before gaining enough energy to damage the cavity. We incorporate this idea into a new lattice design for a neutrino factory, and detail its performance numerically. Although our proposed front-end channel requires more rf power than conventional pillbox designs, it provides enough beam cooling and muon production to be a feasible option for a neutrino factory.

Design of the new front-end electronics for the readout of the upgraded CMS electromagnetic calorimeter for the HL-LHC

CERN Document Server

Cometti, Simona

2017-01-01

The Compact Muon Solenoid detector was originally designed to operate for about ten years, for LHC instantaneous luminosities up to $1 \\cdot 10^{34}$ cm$^{-2}$ s$^{-1}$ and integrated luminosity of 500 fb$^{-1}$. The High Luminosity LHC will increase the instantaneous luminosity by about a factor of 5 from current levels and CMS will accumulate an integrated luminosity of 3000 fb$^{-1}$ by about 2035. With such high luminosity the electromagnetic calorimeter of CMS will have to cope with a challenging increase in the number of interactions per bunch crossing and in radiation levels. The front-end readout electronics will be completely redesigned, with the goals of providing precision timing, low noise and added flexibility in the trigger system. It will use a faster pre-amplifier, increase the sampling frequency from 40 MS/s to 160 MS/s and implement a trigger system that resides entirely off-detector.

Progress with the SNS front-end systems

International Nuclear Information System (INIS)

Keller, R.; Abraham, W.; Ayers, J.J.; Cheng, D.W.; Cull, P.; DiGennaro, R.; Doolittle, L.; Gough, R.A.; Greer, J.B.; Hoff, M.D.; Leung, K.N.; Lewis, S.; Lionberger, C.; MacGill, R.; Minamihara, Y.; Monroy, M.; Oshatz, D.; Pruyn, J.; Ratti, A.; Reijonen, J.; Schenkel, T.; Staples, J.W.; Syversrud, D.; Thomae, R.; Virostek, S.; Yourd, R.

2001-01-01

The Front-End Systems (FES) of the Spallation Neutron Source (SNS) project have been described in detail elsewhere [1]. They comprise an rf-driven H - ion source, electrostatic LEBT, four-vane RFQ, and an elaborate MEBT. These systems are planned to be delivered to the SNS facility in Oak Ridge in June 2002. This paper discusses the latest design features, the status of development work, component fabrication and procurements, and experimental results with the first commissioned beamline elements

The Contribution of Innovation Strategy Development and Implementation in Active Facilitation of Pharmaceutical Front End Innovation

DEFF Research Database (Denmark)

Aagaard, Annabeth

2012-01-01

Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999,......-oriented longitudinal case study of a Danish pharmaceutical company. The findings and key learnings from the study are presented as propositions of how innovation strategies can be applied to actively facilitate FEI and with measurable results.......Front end innovation (FEI) represents the first building blocks of product development, but is often regarded as a weak link in innovation literature. Various theorists emphasize that a firm’s innovation can benefit substantially by improving the front end of innovation process (Reinertsen, 1999...

Tuned Optical Front-End MMIC Amplifiers for a Coherent Optical Receiver

DEFF Research Database (Denmark)

Petersen, Anders Kongstad; Jagd, A M

1992-01-01

Two low noise tuned optical front-end GaAs MESFET MMIC amplifiers for a coherent optical CPFSK (Continuous Phase Frequency Shift Keying) receiver are presented. The receiver operates at 2.5 Gbit/s at an IF of approx. 9 GHz. The front-ends are based on full-custom designed MMICs and a commercially...... available GaInAs/InP pin photo diode. The procedure for measuring the transimpedance and the equivalent input noise current density is outlined in this paper and demonstrated using one of the MMICs. The MMICs were fabricated using the Plessey F20 process by GEC-Marconi through the ESPRIT programme EUROCHIP...

Commissioning and Operation of the FNAL Front end Injection Line and Ion Sources.

Energy Technology Data Exchange (ETDEWEB)

Karns, Patrick R. [Indiana Univ., Bloomington, IN (United States)

2015-09-01

This thesis documents the efforts made in commissioning and operating the RFQ Injection Line (RIL) as a replacement for the Cockcroft Walton front end. The Low Energy Beam Transport (LEBT) was assembled and tested with multiwire position and emittance monitor measurements. The Radio Frequency Quadrupole (RFQ) commissioning was completed with the same measurements as well as output beam energy measurements that showed it initially accelerated beam only to 700 keV, which was 50 keV lower than the design energy. Working with the manufacturer solutions were found and instituted to continue testing. The Medium Energy Beam Transport (MEBT) was then connected as the RIL was installed as the new front end of Linac. Testing gave way to operation when the new front end was used as the source of all High Energy Physics (HEP) beam for Fermi National Accelerator Laboratory (FNAL). The magnetron ion source that provides the H- beam for the front end required several changes and eventual upgrades to operate well; such as new source operating points for vacuum pressure and cesium admixture, and new materials for critical source components. Further research was conducted on the cathode geometry and nitrogen doping of the hydrogen gas as well as using solid state switches for the extractor system high voltage.

InP DHBT MMICs for millimeter-wave front-ends

DEFF Research Database (Denmark)

Johansen, Tom Keinicke; Hadziabdic, Dzenan; Krozer, Viktor

2009-01-01

In this paper, we show advanced MMIC's using InP DHBT technology. In particular, we demonstrate front-end circuits covering a broad frequency range from Q-band to E-band. Realizations of power amplifiers, quadrature VCOs, and sub-harmonic mixers, are presented and experimental results are discussed....

Single-current-sensor-based active front-end-converter-fed four ...

Indian Academy of Sciences (India)

Joseph Kiran Banda

Keywords. Field-oriented control; vector control of induction motor; active front end converter; power factor correction .... sinusoidal three-phase input currents applied to the stator. ... with necessary feed-forward terms are employed to control.

Control of SiC Based Front-End Rectifier under Unbalanced Supply Voltage

DEFF Research Database (Denmark)

Maheshwari, Ramkrishan; Trintis, Ionut; Gohil, Ghanshyamsinh Vijaysinh

2015-01-01

A voltage source converter is used as a front end converter typically. In this paper, a converter which is realized using SiC MOSFET is considered. Due to SiC MOSFET, a switching frequency more than 50 kHz can be achieved. This can help increasing the current control loop bandwidth, which is not ...... together with a positive-sequence current controller for the front-end rectifier. A gain in the feedforward term can be changed to control the negative-sequence current. Simulation results are presented to verify the theory....

Vacuum tests of a beamline front-end mock-up at the Advanced Photon Source

International Nuclear Information System (INIS)

Liu, C.; Nielsen, R.W.; Kruy, T.L.; Shu, D.; Kuzay, T.M.

1994-01-01

A-mock-up has been constructed to test the functioning and performance of the Advanced Photon Source (APS) front ends. The mock-up consists of all components of the APS insertion-device beamline front end with a differential pumping system. Primary vacuum tests have been performed and compared with finite element vacuum calculations. Pressure distribution measurements using controlled leaks demonstrate a better than four decades of pressure difference between the two ends of the mock-up. The measured pressure profiles are consistent with results of finite element analyses of the system. The safety-control systems are also being tested. A closing time of ∼20 ms for the photon shutter and ∼7 ms for the fast closing valve have been obtained. Experiments on vacuum protection systems indicate that the front end is well protected in case of a vacuum breach

A reconfigurable medically cohesive biomedical front-end with ΣΔ ADC in 0.18µm CMOS.

Science.gov (United States)

Jha, Pankaj; Patra, Pravanjan; Naik, Jairaj; Acharya, Amit; Rajalakshmi, P; Singh, Shiv Govind; Dutta, Ashudeb

2015-08-01

This paper presents a generic programmable analog front-end (AFE) for acquisition and digitization of various biopotential signals. This includes a lead-off detection circuit, an ultra-low current capacitively coupled signal conditioning stage with programmable gain and bandwidth, a new mixed signal automatic gain control (AGC) mechanism and a medically cohesive reconfigurable ΣΔ ADC. The full system is designed in UMC 0.18μm CMOS. The AFE achieves an overall linearity of more 10 bits with 0.47μW power consumption. The ADC provides 2(nd) order noise-shaping while using single integrator and an ENOB of ~11 bits with 5μW power consumption. The system was successfully verified for various ECG signals from PTB database. This system is intended for portable batteryless u-Healthcare devices.

Upgraded readout electronics for the ATLAS LAr Calorimeter at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase [1] in 2018, new digital tower builder boards (sTBB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and identifies sig...

An Updated Front-End Data Link Design for the Phase-2 Upgrade of the ATLAS Tile Calorimeter

CERN Document Server

Silverstein, Samuel; The ATLAS collaboration

2017-01-01

We present a new design for the advanced Link Daughter Board (DB) for the front-end electronics upgrade of the ATLAS hadronic Tile Calorimeter. The DB provides control, configuration and continuous ADC readout for the front-end, as well as bi-directional multi-GB/s optical links to the off-detector readout system. The DB will operate in high luminosity LHC conditions with limited detector access, so the design is fault tolerant with a high level of redundancy to avoid single-point failure modes. The DB is divided longitudinally, with an FPGA serving the ADC channels on its respective side. The new design is based on the new Xilinx Kintex Ultrascale+ FPGA family, which provides improved high-speed link timing performance as well as better signal compatibility with the CERN-developed GBTx link and timing distribution ASICs. Two GBTx ASICs each provide redundant phase-adjusted, LHC synchronous clocks, parallel control buses and remote JTAG configuration access to both FPGAs on the DB.

A front end ASIC for the readout of the PMT in the KM3NeT detector

International Nuclear Information System (INIS)

Gajanana, D; Gromov, V; Timmer, P; Heine, E; Kluit, R

2010-01-01

In this work, we describe the front end ASIC to readout the Photo-Multiplier-Tube of the KM3NeT detector, in detail. Stringent power budgeting, area constraints and lowering cost motivate us to design a custom front-end ASIC for reading the PMT. The ASIC amplifies the PMT signal and discriminates it against a threshold level and delivers the information via low voltage differential signals (LVDS). These LVDS signals carry highly accurate timing information of the photons . The length of the LVDS signals or Time over Threshold (ToT) gives information on the number of detected photons. A one-time programmable read-only memory (PROM) block provides unique identification to the chip. The chip communicates with the data acquisition electronics via an I 2 C bus. The data is transmitted to shore via fiber optics, where processing is done. The ASIC was fabricated in 0.35u CMOS process from AustriaMicroSystems (AMS).

Front-End Types. Automotive Mechanics. Steering & Suspension. Instructor's Guide [and] Student Guide.

Science.gov (United States)

Spignesi, B.

This instructional package, one in a series of individualized instructional units on automotive steering and suspension, consists of a student guide and an instructor guide dealing with automobile front-end types. Covered in the module are three common types of passenger car front suspension systems and their major components as well as two types…

Front-end DAQ strategy and implementation for the KLOE-2 experiment

Science.gov (United States)

Branchini, P.; Budano, A.; Balla, A.; Beretta, M.; Ciambrone, P.; De Lucia, E.; D'Uffizi, A.; Marciniewski, P.

2013-04-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

Front-end DAQ strategy and implementation for the KLOE-2 experiment

International Nuclear Information System (INIS)

Branchini, P; Budano, A; Balla, A; Beretta, M; Ciambrone, P; Lucia, E De; D'Uffizi, A; Marciniewski, P

2013-01-01

A new front-end data acquisition (DAQ) system has been conceived for the data collection of the new detectors which will be installed by the KLOE2 collaboration. This system consists of a general purpose FPGA based DAQ module and a VME board hosting up to 16 optical links. The DAQ module has been built around a Virtex-4 FPGA and it is able to acquire up to 1024 different channels distributed over 16 front-end slave cards. Each module is a general interface board (GIB) which performs also first level data concentration tasks. The GIB has an optical interface, a RS-232, an USB and a Gigabit Ethernet Interface. The optical interface will be used for DAQ purposes while the Gigabit Ethernet interface for monitoring tasks and debug. Two new detectors exploit this strategy to collect data. Optical links are used to deliver data to the VME board which performs data concentration tasks. The return optical link from the board to the GIB is used to initialize the front-end cards. The VME interface of the module implements the VME 2eSST protocol in order to sustain a peak data rate of up to 320 MB/s. At the moment the system is working at the Frascati National Laboratory (LNF).

A 0.18 μm biosensor front-end based on 1/f noise, distortion cancelation and chopper stabilization techniques.

Science.gov (United States)

Balasubramanian, Viswanathan; Ruedi, Pierre-Francois; Temiz, Yuksel; Ferretti, Anna; Guiducci, Carlotta; Enz

2013-10-01

This paper presents a novel sensor front-end circuit that addresses the issues of 1/f noise and distortion in a unique way by using canceling techniques. The proposed front-end is a fully differential transimpedance amplifier (TIA) targeted for current mode electrochemical biosensing applications. In this paper, we discuss the architecture of this canceling based front-end and the optimization methods followed for achieving low noise, low distortion performance at minimum current consumption are presented. To validate the employed canceling based front-end, it has been realized in a 0.18 μm CMOS process and the characterization results are presented. The front-end has also been tested as part of a complete wireless sensing system and the cyclic voltammetry (CV) test results from electrochemical sensors are provided. Overall current consumption in the front-end is 50 μA while operating on a 1.8 V supply.

Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

Energy Technology Data Exchange (ETDEWEB)

Brett Carlsen; Emily Tavrides; Erich Schneider

2010-08-01

Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

Measures of the Environmental Footprint of the Front End of the Nuclear Fuel Cycle

International Nuclear Information System (INIS)

Carlsen, Brett; Tavrides, Emily; Schneider, Erich

2010-01-01

Previous estimates of environmental impacts associated with the front end of the nuclear fuel cycle have focused primarily on energy consumption and CO2 emissions. Results have varied widely. Section 2 of this report provides a summary of historical estimates. This study revises existing empirical correlations and their underlying assumptions to fit to a more complete set of existing data. This study also addresses land transformation, water withdrawals, and occupational and public health impacts associated with the processes of the front end of the once-through nuclear fuel cycle. These processes include uranium mining, milling, refining, conversion, enrichment, and fuel fabrication. Metrics are developed to allow environmental impacts to be summed across the full set of front end processes, including transportation and disposition of the resulting depleted uranium.

Upgraded Readout Electronics for the ATLAS Liquid Argon Calorimeters at the High Luminosity LHC

CERN Document Server

Andeen, T; The ATLAS collaboration

2012-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons or photons, at high background ejection rates. For the first upgrade phase cite{pahse1loi} in 2018, new LAr Trigger Digitizer Boards (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies a digital filtering and id...

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

International Nuclear Information System (INIS)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D.; Hu, Y.

2015-01-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e - to 100000 e - , which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

A Novel Front-End ASIC With Post Digital Filtering and Calibration for CZT-Based PET Detector

Energy Technology Data Exchange (ETDEWEB)

Gao, W.; Yin, J.; Li, C.; Zeng, H.; Gao, D. [Institute of Microelectronics, School of Computer Science and Techonology, Northwestern Polytechnical University, Xi' an (China); Hu, Y. [Institut Pluridiscipline Hubert Curien, CNRS/UDS/IN2P3, Strasbourg (France)

2015-07-01

This paper presents a novel front-end electronics based on a front-end ASIC with post digital filtering and calibration dedicated to CZT detectors for PET imaging. A cascade amplifier based on split-leg topology is selected to realize the charge-sensitive amplifier (CSA) for the sake of low noise performances and the simple scheme of the power supplies. The output of the CSA is connected to a variable-gain amplifier to generate the compatible signals for the A/D conversion. A multi-channel single-slope ADC is designed to sample multiple points for the digital filtering and shaping. The digital signal processing algorithms are implemented by a FPGA. To verify the proposed scheme, a front-end readout prototype ASIC is designed and implemented in 0.35 μm CMOS process. In a single readout channel, a CSA, a VGA, a 10-bit ADC and registers are integrated. Two dummy channels, bias circuits, and time controller are also integrated. The die size is 2.0 mm x 2.1 mm. The input range of the ASIC is from 2000 e{sup -} to 100000 e{sup -}, which is suitable for the detection of the X-and gamma ray from 11.2 keV to 550 keV. The linearity of the output voltage is less than 1 %. The gain of the readout channel is 40.2 V/pC. The static power dissipation is about 10 mW/channel. The above tested results show that the electrical performances of the ASIC can well satisfy PET imaging applications. (authors)

Conceptual design of the TRACE detector readout using a compact, dead time-less analog memory ASIC

OpenAIRE

Aliaga Varea, Ramón José; Herrero Bosch, Vicente; Capra, S.; Pullia, A.; Dueñas, J. A.; Grassi, L.; Triossi, A.; Domingo Pardo, C.; Gadea Gironés, Rafael; González, V.; Hüyük, T.; Sanchís, E.; Gadea, A.; Mengoni, D.

2015-01-01

The new TRacking Array for light Charged particle Ejectiles (TRACE) detector system requires monitorization and sampling of all pulses in a large number of channels with very strict space and power consumption restrictions for the front-end electronics and cabling. Its readout system is to be based on analog memory ASICs with 64 channels each that sample a View the MathML source window of the waveform of any valid pulses at 200 MHz while discarding any other signals and are read out at 50 MHz...

Front end support systems for the Advanced Photon Source

International Nuclear Information System (INIS)

Barraza, J.; Shu, D.; Kuzay, T.M.

1993-01-01

The support system designs for the Advanced Photon Source (APS) front ends are complete and will be installed in 1994. These designs satisfy the positioning and alignment requirements of the front end components installed inside the storage ring tunnel, including the photon beam position monitors, fixed masks, photon and safety shutters, filters, windows, and differential pumps. Other components include beam transport pipes and ion pumps. The designs comprise 3-point kinematic mounts and single axis supports to satisfy various multi-direction positioning requirements from course to ultra-precise. The confined space inside the storage ring tunnel has posed engineering challenges in the design of these devices, considering some components weigh as much as 500 kg. These challenges include designing for mobility during commissioning and initial alignment, mechanical and thermal stability, and precise low profile vertical and horizontal positioning. As a result, novel stages and kinematic mounts have emerged with modular and standard designs. This paper will discuss the diverse group of support systems, including specifications and performance data of the prototypes

Receiver Front-End Circuits for Future Generations of Wireless Communications

NARCIS (Netherlands)

Sanduleanu, M.A.T.; Vidojkovic - Andjelovic, M.; Vidojkovic, V.; Roermund, van A.H.M.; Tasic, A.

2007-01-01

In this paper, new receiver concepts and CMOS circuits for future wireless communications standards are introduced. Tradeoffs between technology, performance and circuit choices of the RF front-end circuits are discussed. In particular, power consumption, noise figure and linearity trade-offs in

Design and Characteristics of a Multichannel Front-End ASIC Using Current-Mode CSA for Small-Animal PET Imaging.

Science.gov (United States)

Ollivier-Henry, N; Wu Gao; Xiaochao Fang; Mbow, N A; Brasse, D; Humbert, B; Hu-Guo, C; Colledani, C; Yann Hu

2011-02-01

This paper presents the design and characteristics of a front-end readout application-specific integrated circuit (ASIC) dedicated to a multichannel-plate photodetector coupled to LYSO scintillating crystals. In our configuration, the crystals are oriented in the axial direction readout on both sides by individual photodetector channels allowing the spatial resolution and the detection efficiency to be independent of each other. Both energy signals and timing triggers from the photodetectors are required to be read out by the front-end ASIC. A current-mode charge-sensitive amplifier is proposed for this application. This paper presents performance characteristics of a 10-channel prototype chip designed and fabricated in a 0.35-μm complementary metal-oxide semiconductor process. The main results of simulations and measurements are presented and discussed. The gain of the chip is 13.1 mV/pC while the peak time of a CR-RC pulse shaper is 280 ns. The signal-to-noise ratio is 39 dB and the rms noise is 300 μV/√(Hz). The nonlinearity is less than 3% and the crosstalk is about 0.2%. The power dissipation is less than 15 mW/channel. This prototype will be extended to a 64-channel circuit with integrated time-to-digital converter and analog-to-digital converter together for a high-sensitive small-animal positron emission tomography imaging system.

A Complete Readout Chain of the ATLAS Tile Calorimeter for the HL-LHC: from FATALIC Front-End Electronics to Signal Reconstruction

CERN Document Server

Senkin, Sergey; The ATLAS collaboration

2017-01-01

We present a front-end readout system, an ASIC called FATALIC, proposed for the high-luminosity phase LHC upgrade of the ATLAS Tile Calorimeter. Based on 130 nm CMOS technology, FATALIC performs the full signal processing, including amplification, shaping and digitisation.

An eight channel low-noise CMOS readout circuit for silicon detectors with on-chip front-end FET

International Nuclear Information System (INIS)

Fiorini, C.; Porro, M.

2006-01-01

We propose a CMOS readout circuit for the processing of signals from multi-channel silicon detectors to be used in X-ray spectroscopy and γ-ray imaging applications. The circuit is composed by eight channels, each one featuring a low-noise preamplifier, a 6th-order semigaussian shaping amplifier with four selectable peaking times, from 1.8 up to 6 μs, a peak stretcher and a discriminator. The circuit is conceived to be used with silicon detectors with a front-end FET integrated on the detector chips itself, like silicon drift detectors with JFET and pixel detectors with DEPMOS. The integrated time constants used for the shaping are implemented by means of an RC-cell, based on the technique of demagnification of the current flowing in a resistor R by means of the use of current mirrors. The eight analog channels of the chip are multiplexed to a single analog output. A suitable digital section provides self-resetting of each channel and trigger output and is able to set independent thresholds on the analog channels by means of a programmable serial register and 3-bit DACs. The circuit has been realized in the 0.35 μm CMOS AMS technology. In this work, the main features of the circuit are presented along with the experimental results of its characterization

A differential low-voltage high gain current-mode integrated RF receiver front-end

Energy Technology Data Exchange (ETDEWEB)

Wang Chunhua; Ma Minglin; Sun Jingru; Du Sichun; Guo Xiaorong; He Haizhen, E-mail: wch1227164@sina.com [School of Information Science and Technology, Hunan University, Changsha 410082 (China)

2011-02-15

A differential low-voltage high gain current-mode integrated RF front end for an 802.11b WLAN is proposed. It contains a differential transconductance low noise amplifier (G{sub m}-LNA) and a differential current-mode down converted mixer. The single terminal of the G{sub m}-LNA contains just one MOS transistor, two capacitors and two inductors. The gate-source shunt capacitors, C{sub x1} and C{sub x2}, can not only reduce the effects of gate-source C{sub gs} on resonance frequency and input-matching impedance, but they also enable the gate inductance L{sub g1,2} to be selected at a very small value. The current-mode mixer is composed of four switched current mirrors. Adjusting the ratio of the drain channel sizes of the switched current mirrors can increase the gain of the mixer and accordingly increase the gain of RF receiver front-end. The RF front-end operates under 1 V supply voltage. The receiver RFIC was fabricated using a chartered 0.18 {mu}m CMOS process. The integrated RF receiver front-end has a measured power conversion gain of 17.48 dB and an input referred third-order intercept point (IIP3) of -7.02 dBm. The total noise figure is 4.5 dB and the power is only 14 mW by post-simulations. (semiconductor integrated circuits)

MDT-ASD, CMOS front-end for ATLAS MDT

CERN Document Server

Posch, C; Oliver, J

2007-01-01

This document serves as the main reference and user`s manual for the read-out chip of the Monitored Drift Tubes in the ATLAS Muon Spectrometer. The eight-channel front-end ASIC is referred to as MDT-ASD. The document contains the requirements and complete specifications, a detailed description of the design with characteristics of all sub-circuits and building blocks, a comprehensive section on functionality and performance test results, and a complete bibliography.

Progress on the development of a detector mounted analog and digital readout system for the ATLAS TRT

CERN Document Server

Baxter, C; Dressnandt, N; Gay, C; Lundberg, B; Munar, A; Mayers, G; Newcomer, M; Van Berg, R; Williams, H H

2004-01-01

The 430,000 element ATLAS Transition Radiation straw tube Tracker (TRT) is divided into a central barrel tracker consisting of 104,000 axially mounted straws and two radially arranged end caps on either side of the barrel with 160,000 straws each. To achieve a track position resolution of 140 mu m, the front end electronics must operate at a low (2fC) threshold with a time marking capability of ~1ns. Two ASICs, the ASDBLR and DTMROC provide the complete pipelined readout chain. Custom designed FBGA packages for the ASICs provide a small enough outline to be detector mounted and the extensive use of low level differential signals make mounting the analog packages on printed circuit boards directly opposite the 40 MHz digital chips feasible. The readout electronics for the barrel occupies a potentially important part of the active tracker volume and an aggressive effort has been made to make it as compact as possible. Utilizing a single board for both analog and digital ASICS a 0.1 cm /sup 3/ per channel volume...

FEREAD: Front End Readout software for the Fermilab PAN-DA data acquisition system

International Nuclear Information System (INIS)

Dorries, T.; Haire, M.; Moore, C.; Pordes, R.; Votava, M.

1989-05-01

The FEREAD system provides a multi-tasking framework for controlling the execution of experiment specific front end readout processes. It supports initializing the front end data acquisition hardware, queueing and processing readout activation signals, cleaning up at the end of data acquisition, and transferring configuration parameters and statistical data between a ''Host'' computer and the readout processes. FEREAD is implemented as part of the PAN-DA software system and is designed to run on any Motorola 68k based processor board. It has been ported to the FASTBUS General Purpose Master (GPM) interface board and the VME MVME133A processor board using the pSOS/Microtec environment. 12 refs., 2 figs

Design of a low-power 433/915-MHz RF front-end with a current-reuse common-gate LNA

International Nuclear Information System (INIS)

Jing Yiou; Lu Huaxiang

2013-01-01

This paper presents a wideband RF front-end with novel current-reuse wide band low noise amplifier (LNA), current-reuse V—I converter, active double balanced mixer and transimpedance amplifier for short range device (SRD) applications. With the proposed current-reuse LNA, the DC consumption of the front-end reduces considerably while maintaining sufficient performance needed by SRD devices. The RF front-end was fabricated in 0.18 μm RFCMOS process and occupies a silicon area of just 0.11 mm 2 . Operating in 433 MHz band, the measurement results show the RF front-end achieves a conversion gain of 29.7 dB, a double side band noise figure of 9.7 dB, an input referenced third intercept point of −24.9 dBm with only 1.44 mA power consumption from 1.8 V supply. Compared to other reported front-ends, it has an advantage in power consumption. (semiconductor integrated circuits)

Development and Demonstration of a Magnesium-Intensive Vehicle Front-End Substructure

Energy Technology Data Exchange (ETDEWEB)

Logan, Stephen D. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Forsmark, Joy H. [United States Automotive Materials Partnership LLC, Southfield, MI (United States); Osborne, Richard [United States Automotive Materials Partnership LLC, Southfield, MI (United States)

2016-07-01

This project is the final phase (designated Phase III) of an extensive, nine-year effort with the objectives of developing a knowledge base and enabling technologies for the design, fabrication and performance evaluation of magnesium-intensive automotive front-end substructures intended to partially or completely replace all-steel comparators, providing a weight savings approaching 50% of the baseline. Benefits of extensive vehicle weight reduction in terms of fuel economy increase, extended vehicle range, vehicle performance and commensurate reductions in greenhouse gas emissions are well known. An exemplary vehicle substructure considered by the project is illustrated in Figure 1, along with the exterior vehicle appearance. This unibody front-end “substructure” is one physical objective of the ultimate design and engineering aspects established at the outset of the larger collective effort.

High Dynamic Range Cognitive Radio Front Ends: Architecture to Evaluation

Science.gov (United States)

Ashok, Arun; Subbiah, Iyappan; Varga, Gabor; Schrey, Moritz; Heinen, Stefan

2016-07-01

Advent of TV white space digitization has released frequencies from 470 MHz to 790 MHz to be utilized opportunistically. The secondary user can utilize these so called TV spaces in the absence of primary users. The most important challenge for this coexistence is mutual interference. While the strong TV stations can completely saturate the receiver of the cognitive radio (CR), the cognitive radio spurious tones can disturb other primary users and white space devices. The aim of this paper is to address the challenges for enabling cognitive radio applications in WLAN and LTE. In this process, architectural considerations for the design of cognitive radio front ends are discussed. With high-IF converters, faster and flexible implementation of CR enabled WLAN and LTE are shown. The effectiveness of the architecture is shown by evaluating the CR front ends for compliance of standards namely 802.11b/g (WLAN) and 3GPP TS 36.101 (LTE).

PACE3 - front-end chip for the CMS Preshower

CERN Multimedia

Aspel, Paul

2003-01-01

This is PACE3 which is the front-end chip for the CMS Preshower. In fact PACE3 is the combination of two ASICs called Delta3 and PACEAM3. Delta3 is on the left and PACEAM3 is on the right. The two ASICs are bonded together and then packaged within a single 196 pin fpBGA package.

Deep sub-micron FD-SOI for front-end application

International Nuclear Information System (INIS)

Ikeda, H.; Arai, Y.; Hara, K.; Hayakawa, H.; Hirose, K.; Ikegami, Y.; Ishino, H.; Kasaba, Y.; Kawasaki, T.; Kohriki, T.; Martin, E.; Miyake, H.; Mochizuki, A.; Tajima, H.; Tajima, O.; Takahashi, T.; Takashima, T.; Terada, S.; Tomita, H.; Tsuboyama, T.

2007-01-01

In order to confirm benefits of a deep sub-micron FD-SOI and to identify possible issues concerning front-end circuits with the FD-SOI, we have submitted a small design to Oki Electric Industry Co., Ltd. via the multi-chip project service of VDEC, the University of Tokyo. The initial test results and future plans for development are presented

Front-end circuit for position sensitive silicon and vacuum tube photomultipliers with gain control and depth of interaction measurement

International Nuclear Information System (INIS)

Herrero, Vicente; Colom, Ricardo; Gadea, Rafael; Lerche, Christoph W.; Cerda, Joaquin; Sebastia, Angel; Benlloch, Jose M.

2007-01-01

Silicon Photomultipliers, though still under development for mass production, may be an alternative to traditional Vacuum Photomultipliers Tubes (VPMT). As a consequence, electronic front-ends initially designed for VPMT will need to be modified. In this simulation, an improved architecture is presented which is able to obtain impact position and depth of interaction of a gamma ray within a continuous scintillation crystal, using either kind of PM. A current sensitive preamplifier stage with individual gain adjustment interfaces the multi-anode PM outputs with a current division resistor network. The preamplifier stage allows to improve front-end processing delay and temporal resolution behavior as well as to increase impact position calculation resolution. Depth of interaction (DOI) is calculated from the width of the scintillation light distribution, which is related to the sum of voltages in resistor network input nodes. This operation is done by means of a high-speed current mode scheme

Trends in the design of front-end systems for room temperature solid state detectors

International Nuclear Information System (INIS)

Manfredi, Pier F.; Re, Valerio

2003-01-01

The paper discusses the present trends in the design of low-noise front-end systems for room temperature semiconductor detectors. The technological advancement provided by submicron CMOS and BiCMOS processes is examined from several points of view. The noise performances are a fundamental issue in most detector applications and suitable attention is devoted to them for the purpose of judging whether or not the present processes supersede the solutions featuring a field-effect transistor as a front-end element. However, other considerations are also important in judging how well a monolithic technology suits the front-end design. Among them, the way a technology lends itself to the realization of additional functions, for instance, the charge reset in a charge-sensitive loop or the time-variant filters featuring the special weighting functions that may be requested in some applications of CdTe or CZT detectors

Front-end and back-end electrochemistry of molten salt in accelerator-driven transmutation systems

International Nuclear Information System (INIS)

Williamson, M.A.; Venneri, F.

1995-01-01

The objective of this work is to develop preparation and clean-up processes for the fuel and carrier salt in the Los Alamos Accelerator-Driven Transmutation Technology molten salt nuclear system. The front-end or fuel preparation process focuses on the removal of fission products, uranium, and zirconium from spent nuclear fuel by utilizing electrochemical methods (i.e., electrowinning). The same method provides the separation of the so-called noble metal fission products at the back-end of the fuel cycle. Both implementations would have important diversion safeguards. The proposed separation processes and a thermodynamic analysis of the electrochemical separation method are presented

Underwater fiber-wireless communication with a passive front end

Science.gov (United States)

Xu, Jing; Sun, Bin; Lyu, Weichao; Kong, Meiwei; Sarwar, Rohail; Han, Jun; Zhang, Wei; Deng, Ning

2017-11-01

We propose and experimentally demonstrate a novel concept on underwater fiber-wireless (Fi-Wi) communication system with a fully passive wireless front end. A low-cost step-index (SI) plastic optical fiber (POF) together with a passive collimating lens at the front end composes the underwater Fi-Wi architecture. We have achieved a 1.71-Gb/s transmission at a mean BER of 4.97 × 10-3 (1.30 × 10-3 when using power loading) over a 50-m SI-POF and 2-m underwater wireless channel using orthogonal frequency division multiplexing (OFDM). Although the wireless part is very short, it actually plays a crucial role in practical underwater implementation, especially in deep sea. Compared with the wired solution (e.g. using a 52-m POF cable without the UWOC part), the proposed underwater Fi-Wi scheme can save optical wet-mate connectors that are sophisticated, very expensive and difficult to install in deep ocean. By combining high-capacity robust POF with the mobility and ubiquity of underwater wireless optical communication (UWOC), the proposed underwater Fi-Wi technology will find wide application in ocean exploration.

Radiation Protection Aspects of the Linac Coherent Light Source Front End Enclosure

Energy Technology Data Exchange (ETDEWEB)

Vollaire, J.; Fasso, A.; Liu, J.C.; Mao, X.S.; Prinz, A.; Rokni, S.H.; Leitner, M.Santana; /SLAC

2010-08-26

The Front End Enclosure (FEE) of the Linac Coherent Light Source (LCLS) is a shielding housing located between the electron dump area and the first experimental hutch. The upstream part of the FEE hosts the commissioning diagnostics for the FEL beam. In the downstream part of the FEE, two sets of grazing incidence mirror and several collimators are used to direct the beam to one of the experimental stations and reduce the bremsstrahlung background and the hard component of the spontaneous radiation spectrum. This paper addresses the beam loss assumptions and radiation sources entering the FEE used for the design of the FEE shielding using the Monte-Carlo code FLUKA. The beam containment system prevents abnormal levels of radiations inside the FEE and ensures that the beam remains in its intended path is also described.

A wideband high-linearity RF receiver front-end in CMOS

NARCIS (Netherlands)

Arkesteijn, V.J.; Klumperink, Eric A.M.; Nauta, Bram

This paper presents a wideband high-linearity RF receiver-front-end, implemented in standard 0.18 μm CMOS technology. The design employs a noise-canceling LNA in combination with two passive mixers, followed by lowpass-filtering and amplification at IF. The achieved bandwidth is >2 GHz, with a noise

Instrument Front-Ends at Fermilab During Run II

Energy Technology Data Exchange (ETDEWEB)

Meyer, Thomas; Slimmer, David; Voy, Duane; /Fermilab

2011-07-13

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Instrument front-ends at Fermilab during Run II

International Nuclear Information System (INIS)

Meyer, T; Slimmer, D; Voy, D

2011-01-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Instrument Front-Ends at Fermilab During Run II

International Nuclear Information System (INIS)

Meyer, Thomas; Slimmer, David; Voy, Duane

2011-01-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor.

Artificial Neural Network based DC-link Capacitance Estimation in a Diode-bridge Front-end Inverter System

DEFF Research Database (Denmark)

Soliman, Hammam Abdelaal Hammam; Abdelsalam, Ibrahim; Wang, Huai

2017-01-01

, a proposed software condition monitoring methodology based on Artificial Neural Network (ANN) algorithm is presented. Matlab software is used to train and generate the proposed ANN. The proposed methodology estimates the capacitance of the DC-link capacitor in a three phase front-end diode bridge AC......In modern design of power electronic converters, reliability of DC-link capacitors is an essential aspect to be considered. The industrial field have been attracted to the monitoring of their health condition and the estimation of their ageing process status. The existing condition monitoring...

Front-end data processing using the bit-sliced microprocessor

International Nuclear Information System (INIS)

Machen, D.R.

1979-01-01

A state-of-the-art computing device, based upon the high-speed bit-sliced microprocessor, was developed into hardware for front-end data processing in both control and experiment applications at the Los Alamos Scientific Laboratory. The CAMAC Instrumentation Standard provides the framework for the high-speed hardware, allowing data acquisition and processing to take place at the data source in a CAMAC crate. 5 figures

The upgraded Tevatron front end

International Nuclear Information System (INIS)

Glass, M.; Zagel, J.; Smith, P.; Marsh, W.; Smolucha, J.

1990-01-01

We are replacing the computers which support the CAMAC crates in the Fermilab accelerator control system. We want a significant performance increase, but we still want to be able to service scores of different varieties of CAMAC cards in a manner essentially transparent to console applications software. Our new architecture is based on symmetric multiprocessing. Several processors on the same bus, each running identical software, work simultaneously at satisfying different pieces of a console's request for data. We dynamically adjust the load between the processors. We can obtain more processing power by simply plugging in more processor cards and rebooting. We describe in this paper what we believe to be the interesting architectural features of the new front-end computers. We also note how we use some of the advanced features of the Multibus TM II bus and the Intel 80386 processor design to achieve reliability and expandability of both hardware and software. (orig.)

Analog circuit design : low voltage low power; short range wireless front-ends; power management and DC-DC

NARCIS (Netherlands)

Steyaert, M.; Roermund, van A.H.M.; Baschirotto, A.

2012-01-01

The book contains the contribution of 18 tutorials of the 20th workshop on Advances in Analog Circuit Design. Each part discusses a specific to-date topic on new and valuable design ideas in the area of analog circuit design. Each part is presented by six experts in that field and state of the art

The Phase-I Trigger Readout Electronics Upgrade of the ATLAS Liquid Argon Calorimeters

CERN Document Server

Yang, Yi-lin; The ATLAS collaboration

2018-01-01

The Super Cell has been proposed in the Phase-I LAr upgrade to replace the existing trigger system "Trigger Tower" due to higher luminosity environments in Run 3 at LHC. The higher granularity of the Super Cell trigger systems requires higher data transmission and processing rate. The new system is also needed to be compatible with the existing trigger system. To fulfill these requirements, the new electronics including frond end and back end are developed. In the front-end part, the new LSB sums the LAr cell signals into Super Cell signals. The new baseplane distributes analog signals among FEBs, LTDB and TBB. The LTDB sums Super Cell signals to Trigger Tower signals and redirected the signals to TBB. The Analog signals are also digitized in LTDB and then sent to back end electronics. In the back-end part, the architecture is based on ATCA. The LAr carrier is used for monitoring and controlling. The LATOMEs inserted into the LAr carrier provide energy calculation from the digitized signals. So far, the demon...

Design of ultralow power receiver front-ends for 2.4 GHz wireless sensor network applications

International Nuclear Information System (INIS)

Zhang Meng; Li Zhiqun; Wang Zengqi; Wu Chenjian; Chen Liang

2014-01-01

This paper presents the design of an ultralow power receiver front-end designed for a wireless sensor network (WSN) in a 0.18 μm CMOS process. The author designs two front-ends working in the saturation region and the subthreshold region respectively. The front-ends contain a two-stage cross-coupling cascaded common-gate (CG) LNA and a quadrature Gilbert IQ mixer. The measured conversion gain is variable with high gain at 24 dB and low gain at 7 dB for the saturation one, and high gain at 22 dB and low gain at 5 dB for the subthreshold one. The noise figure (NF) at high gain mode is 5.1 dB and 6.3 dB for each. The input 1 dB compression point (IP1dB) at low gain mode is about −6 dBm and −3 dBm for each. The front-ends consume about 2.1 mA current from 1.8 V power supply for the saturation one and 1.3 mA current for the subthreshold one. The measured results show that, comparing with the power consumption saving, it is worth making sacrifices on the performance for using the subthreshold technology. (semiconductor integrated circuits)

An analog front-end bipolar-transistor integrated circuit for the SDC silicon tracker

International Nuclear Information System (INIS)

Kipnis, I.; Spieler, H.; Collins, T.

1994-01-01

Since 1989 the Solenoidal Detector Collaboration (SDC) has been developing a general purpose detector to be operated at the Superconducting Super Collider (SSC). A low-noise, low-power, high-bandwidth, radiation hard, silicon bipolar-transistor full-custom integrated circuit (IC) containing 64 channels of analog signal processing has been developed for the SDS silicon tracker. The IC was designed and tested at LBL and was fabricated using AT and T's CBIC-U2, 4 GHz f T complementary bipolar technology. Each channel contains the following functions: low-noise preamplification, pulse shaping and threshold discrimination. This is the first iteration of the production analog IC for the SDC silicon tracker. The IC is laid out to directly match the 50 μm pitch double-sided silicon strip detector. The chip measures 6.8 mm x 3.1 mm and contains 3,600 transistors. Three stages of amplification provide 180 mV/fC of gain with a 35 nsec peaking time at the comparator input. For a 14 pF detector capacitance, the equivalent noise charge is 1300 el. rms at a power consumption of 1 mW/channel from a single 3.5 V supply. With the discriminator threshold set to 4 times the noise level, a 16nsec time-walk for 1.25 to 10 fC signals is achieved using a time-walk compensation network. Irradiation tests at TRIUMF to a φ = 10 14 protons/cm 2 have been performed on the JC, demonstrating the radiation hardness of the complementary bipolar process

Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

CERN Document Server

Tang, F; The ATLAS collaboration

2014-01-01

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and de...

The PHENIX Drift Chamber Front End Electroncs

Science.gov (United States)

Pancake, C.; Velkovska, J.; Pantuev, V.; Fong, D.; Hemmick, T.

1998-04-01

The PHENIX Drift Chamber (DC) is designed to operate in the high particle flux environment of the Relativistic Heavy Ion Collider and provide high resolution track measurements. It is segmented into 80 keystones with 160 readout channels each. The Front End Electronics (FEE) developed to meet the demanding operating conditions and the large number of readout channels of the DC will be discussed. It is based on two application specific integrated circuits: the ASD8 and the TMC-PHX1. The ASD8 chip contains 8 channels of bipolar amplifier-shaper-discriminator with 6 ns shaping time and ≈ 20 ns pulse width, which satisfies the two track resolution requirements. The TMC-PHX1 chip is a high-resolution multi-hit Time-to-Digital Converter. The outputs from the ASD8 are digitized in the Time Memory Cell (TMC) every (clock period)/32 or 0.78 ns (at 40 MHz), which gives the intrinsic time resolution of the system. A 256 words deep dual port memory keeps 6.4 μs time history of data at 40 MHz clock. Each DC keystone is supplied with 4 ASD8/TMC boards and one FEM board, which performs the readout of the TMC-PHX1's, buffers and formats the data to be transmitted over the Glink. The slow speed control communication between the FEM and the system is carried out over ARCNET. The full readout chain and the data aquisition system are being tested.

The ICARUS Front-end Preamplifier Working at Liquid Argon Temperature

CERN Document Server

Baibussinov, B; Casagrande, F; Cennini, P; Centro, S; Curioni, A; Meng, G; Picchi, P; Pietropaolo, F; Rubbia, C; Sergiampietri, F; Ventura, S

2011-01-01

We describe characteristics and performance of the low-noise front-end preamplifier used in the ICARUS 50-litre liquid Argon Time Projection Chamber installed in the CERN West Area Neutrino Facility during the 1997-98 neutrino runs. The preamplifiers were designed to work immersed in ultra-pure liquid Argon at a temperature of 87K.

Predictive Duty Cycle Control of Three-Phase Active-Front-End Rectifiers

DEFF Research Database (Denmark)

Song, Zhanfeng; Tian, Yanjun; Chen, Wei

2016-01-01

This paper proposed an on-line optimizing duty cycle control approach for three-phase active-front-end rectifiers, aiming to obtain the optimal control actions under different operating conditions. Similar to finite control set model predictive control strategy, a cost function previously...

EXPERIENCE WITH FPGA-BASED PROCESSOR CORE AS FRONT-END COMPUTER

International Nuclear Information System (INIS)

HOFF, L.T.

2005-01-01

The RHIC control system architecture follows the familiar ''standard model''. LINUX workstations are used as operator consoles. Front-end computers are distributed around the accelerator, close to equipment being controlled or monitored. These computers are generally based on VMEbus CPU modules running the VxWorks operating system. I/O is typically performed via the VMEbus, or via PMC daughter cards (via an internal PCI bus), or via on-board I/O interfaces (Ethernet or serial). Advances in FPGA size and sophistication now permit running virtual processor ''cores'' within the FPGA logic, including ''cores'' with advanced features such as memory management. Such systems offer certain advantages over traditional VMEbus Front-end computers. Advantages include tighter coupling with FPGA logic, and therefore higher I/O bandwidth, and flexibility in packaging, possibly resulting in a lower noise environment and/or lower cost. This paper presents the experience acquired while porting the RHIC control system to a PowerPC 405 core within a Xilinx FPGA for use in low-level RF control

Robust Spectrum Sensing Demonstration Using a Low-Cost Front-End Receiver

Directory of Open Access Journals (Sweden)

Daniele Borio

2015-01-01

Full Text Available Spectrum Sensing (SS is an important function in Cognitive Radio (CR to detect primary users. The design of SS algorithms is one of the most challenging tasks in CR and requires innovative hardware and software solutions to enhance detection probability and minimize low false alarm probability. Although several SS algorithms have been developed in the specialized literature, limited work has been done to practically demonstrate the feasibility of this function on platforms with significant computational and hardware constraints. In this paper, SS is demonstrated using a low cost TV tuner as agile front-end for sensing a large portion of the Ultra-High Frequency (UHF spectrum. The problems encountered and the limitations imposed by the front-end are analysed along with the solutions adopted. Finally, the spectrum sensor developed is implemented on an Android device and SS implementation is demonstrated using a smartphone.

Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

Energy Technology Data Exchange (ETDEWEB)

Nguyen, Viet Phuong; Yim, Man-Sung [Korea Advanced Institute of Science and Technology, Daejeon (Korea, Republic of)

2015-05-15

A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities.

Quantitative Analysis of the Civilian Bilateral Cooperation in Front-End of the Nuclear Fuel Cycle

International Nuclear Information System (INIS)

Nguyen, Viet Phuong; Yim, Man-Sung

2015-01-01

A substantial part of such cooperation is related to the front-end of the nuclear fuel cycle, which encompasses the processes that help manufacturing nuclear fuel, including mining and milling of natural uranium, refining and chemical conversion, enrichment (in case of fuels for Pressurized Water Reactor PWR), and fuel fabrication. Traditionally, the supply of natural uranium was dominated by Canada and Australia, whereas enrichment services have been mostly provided by companies from Western states or Russia, which are also the main customers of such services. However, Kazakhstan and African countries like Niger, Namibia, and Malawi have emerged as important suppliers in the international uranium market and recent forecasts show that China will soon become a major player in the front-end market as both consumer and service provider. In this paper, the correlation between bilateral civil nuclear cooperation in front-end of the nuclear fuel cycle and the political and economic relationship among countries was examined through a dataset of bilateral nuclear cooperation in the post-Cold War era, from 1990 to 2011. Such finding has implication on not only the nonproliferation research but also the necessary reinforcement of export control regimes like such as the Nuclear Suppliers Group. Further improvement of this dataset and the regression method are also needed in order to increase the robustness of the findings as well as to cover the whole scope of the nuclear fuel cycle, including both front-end and back-end activities

Upgraded Readout and Trigger Electronics for the ATLAS Liquid Argon Calorimeter at the LHC at the Horizons 2018-2022

CERN Document Server

Oliveira Damazio, Denis; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

Upgraded Readout and Trigger Electronics for the ATLAS Liquid-Argon Calorimeters at the LHC at the Horizons 2018-2022

CERN Document Server

Damazio, D O; The ATLAS collaboration

2013-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce a total of 182,486 signals which are digitized and processed by the front-end and back-end electronics at every triggered event. In addition, the front-end electronics is summing analog signals to provide coarsely grained energy sums, called trigger towers, to the first-level trigger system, which is optimized for nominal LHC luminosities. However, the pile-up noise expected during the High Luminosity phases of LHC will be increased by factors of 3 to 7. An improved spatial granularity of the trigger primitives is therefore proposed in order to improve the identification performance for trigger signatures, like electrons, photons, tau leptons, jets, total and missing energy, at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Board (LTDB) are being designed to receive higher granularity signals, digitize them on detector and send them via fast optical links to a new digital processing system (DPS). The DPS applies...

Scientific performances of the XAA1.2 front-end chip for silicon microstrip detectors

International Nuclear Information System (INIS)

Del Monte, Ettore; Soffitta, Paolo; Morelli, Ennio; Pacciani, Luigi; Porrovecchio, Geiland; Rubini, Alda; Uberti, Olga; Costa, Enrico; Di Persio, Giuseppe; Donnarumma, Immacolata; Evangelista, Yuri; Feroci, Marco; Lazzarotto, Francesco; Mastropietro, Marcello; Rapisarda, Massimo

2007-01-01

The XAA1.2 is a custom ASIC chip for silicon microstrip detectors adapted by Ideas for the SuperAGILE instrument on board the AGILE space mission. The chip is equipped with 128 input channels, each one containing a charge preamplifier, shaper, peak detector and stretcher. The most important features of the ASIC are the extended linearity, low noise and low power consumption. The XAA1.2 underwent extensive laboratory testing in order to study its commandability and functionality and evaluate its scientific performances. In this paper we describe the XAA1.2 features, report the laboratory measurements and discuss the results emphasizing the scientific performances in the context of the SuperAGILE front-end electronics

Front End Loader Operator. Open Pit Mining Job Training Series.

Science.gov (United States)

Savilow, Bill

This training outline for front end loader operators, one in a series of eight outlines, is designed primarily for company training foremen or supervisors and for trainers to use as an industry-wide guideline for heavy equipment operator training in open pit mining in British Columbia. Intended as a guide for preparation of lesson plans both for…

Controlling front-end electronics boards using commercial solutions

CERN Document Server

Beneyton, R; Jost, B; Schmeling, S

2002-01-01

LHCb is a dedicated B-physics experiment under construction at CERN's large hadron collider (LHC) accelerator. This paper will describe the novel approach LHCb is taking toward controlling and monitoring of electronics boards. Instead of using the bus in a crate to exercise control over the boards, we use credit-card sized personal computers (CCPCs) connected via Ethernet to cheap control PCs. The CCPCs will provide a simple parallel, I2C, and JTAG buses toward the electronics board. Each board will be equipped with a CCPC and, hence, will be completely independently controlled. The advantages of this scheme versus the traditional bus-based scheme will be described. Also, the integration of the controls of the electronics boards into a commercial supervisory control and data acquisition (SCADA) system will be shown. (5 refs).

Front end embedded microprocessors in the JET computer-based control system, past, present and future

International Nuclear Information System (INIS)

Steed, C.A.; VanderBeken, H.; Browne, M.L.; Fullard, K.; Reed, K.; Tilley, M.; Schmidt, V.

1987-01-01

A brief history of the use of Front End Microprocessors in the JET Control and Data Acquisition System (CODAS) is presented. The present expansion in their use from 2 or 3 in 1983 to 27 now, is covered along with the reasoning behind their present usage. Finally, their future planned use in the area of remote handling is discussed and the authors present views on the use of front end processing in future large distributed control systems are presented

Firmware Development and Integration for ALICE TPC and PHOS Front-end Electronics A Trigger Based Readout and Control System operating in a Radiation Environment

CERN Document Server

AUTHOR|(CDS)2068589; Rohrich, Dieter

2008-01-01

The readout electronics in PHOS and TPC - two of the major detectors of the ALICE experiment at the LHC - consist of a set of Front End Cards (FECs) that digitize, process and buffer the data from the detector sensors. The FECs are connected to a Readout Control Unit (RCU) via two sets of custom made PCB backplanes. For PHOS, 28 FECs are connected to one RCU, while for TPC the number is varying from 18 to 25 FECs depending on location. The RCU is in charge of the data readout, including reception and distribution of triggers and in moving the data from the FECs to the Data Acquisition System. In addition it does low level control tasks. The RCU consists of an RCU Motherboard that hosts a Detector Control System (DCS) board and a Source Interface Unit. The DCS board is an embedded computer running Linux that controls the readout electronics. All the mentioned devices are implemented in commercial grade SRAM based Field Programmable Gate Arrays (FPGAs). Even if these devices are not very radiation tolerant, the...

Upgrade readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

Upgraded readout and trigger electronics for the ATLAS liquid argon calorimeters for future LHC running

CERN Document Server

Yamanaka, T; The ATLAS collaboration

2014-01-01

The ATLAS Liquid Argon (LAr) calorimeters produce almost 200K signals that must be digitized and processed by the front-end and back-end electronics at every triggered event. Additionally, the front-end electronics sums analog signals to provide coarse-grained energy sums to the first-level (L1) trigger system. The current design was optimized for the nominal LHC luminosity of 10^34 cm^-2s^-1. However, in future higher-luminosity phases of LHC operation, the luminosity (and associated pile-up noise) will be 3-7 times higher. An improved spatial granularity of the trigger primitives is therefore proposed, in order to improve the trigger performance at high background rejection rates. For the first upgrade phase in 2018, new LAr Trigger Digitizer Boards are being designed to receive the higher granularity signals, digitize them on-detector and send them via fast optical links to a new digital processing system (DPS). This applies digital filtering and identifies significant energy depositions in each trigger ch...

High-Frequency Wireless Communications System: 2.45-GHz Front-End Circuit and System Integration

Science.gov (United States)

Chen, M.-H.; Huang, M.-C.; Ting, Y.-C.; Chen, H.-H.; Li, T.-L.

2010-01-01

In this article, a course on high-frequency wireless communications systems is presented. With the 145-MHz baseband subsystem available from a prerequisite course, the present course emphasizes the design and implementation of the 2.45-GHz front-end subsystem as well as system integration issues. In this curriculum, the 2.45-GHz front-end…

Status of the Warm Front End of PIP-II Injector Test

Energy Technology Data Exchange (ETDEWEB)

Shemyakin, Alexander [Fermilab; Alvarez, Matthew [Fermilab; Andrews, Richard [Fermilab; Baffes, Curtis [Fermilab; Carneiro, Jean-Paul [Fermilab; Chen, Alex [Fermilab; Derwent, Paul [Fermilab; Edelen, Jonathan [Fermilab; Frolov, Daniil [Fermilab; Hanna, Bruce [Fermilab; Prost, Lionel [Fermilab; Saewert, Gregory [Fermilab; Saini, Arun [Fermilab; Scarpine, Victor [Fermilab; Sista, V. Lalitha [Fermilab; Steimel, Jim [Fermilab; Sun, Ding [Fermilab; Warner, Arden [Fermilab

2017-05-01

The Proton Improvement Plan II (PIP-II) at Fermilab is a program of upgrades to the injection complex. At its core is the design and construction of a CW-compatible, pulsed H⁻ SRF linac. To validate the concept of the front-end of such machine, a test accelerator known as PIP-II Injector Test is under construction. It includes a 10 mA DC, 30 keV H⁻ ion source, a 2 m-long Low Energy Beam Transport (LEBT), a 2.1 MeV CW RFQ, followed by a Medium Energy Beam Transport (MEBT) that feeds the first of 2 cryomodules increasing the beam energy to about 25 MeV, and a High Energy Beam Transport section (HEBT) that takes the beam to a dump. The ion source, LEBT, RFQ, and initial version of the MEBT have been built, installed, and commissioned. This report presents the overall status of the warm front end.

Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

International Nuclear Information System (INIS)

Sorokin, Iurii

2013-01-01

The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10 14 n eq /cm 2 (n eq -neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the amplitude response on

Single event effect hardness for the front-end ASICs in the DAMPE satellite BGO calorimeter

Science.gov (United States)

Gao, Shan-Shan; Jiang, Di; Feng, Chang-Qing; Xi, Kai; Liu, Shu-Bin; An, Qi

2016-01-01

The Dark Matter Particle Explorer (DAMPE) is a Chinese scientific satellite designed for cosmic ray studies with a primary scientific goal of indirect detection of dark matter particles. As a crucial sub-detector, the BGO calorimeter measures the energy spectrum of cosmic rays in the energy range from 5 GeV to 10 TeV. In order to implement high-density front-end electronics (FEE) with the ability to measure 1848 signals from 616 photomultiplier tubes on the strictly constrained satellite platform, two kinds of 32-channel front-end ASICs, VA160 and VATA160, are customized. However, a space mission period of more than 3 years makes single event effects (SEEs) become threats to reliability. In order to evaluate SEE sensitivities of these chips and verify the effectiveness of mitigation methods, a series of laser-induced and heavy ion-induced SEE tests were performed. Benefiting from the single event latch-up (SEL) protection circuit for power supply, the triple module redundancy (TMR) technology for the configuration registers and the optimized sequential design for the data acquisition process, 52 VA160 chips and 32 VATA160 chips have been applied in the flight model of the BGO calorimeter with radiation hardness assurance. Supported by Strategic Priority Research Program on Space Science of the Chinese Academy of Sciences (XDA04040202-4) and Fundamental Research Funds for the Central Universities (WK2030040048)

Upgrade Analog Readout and Digitizing System for ATLAS TileCal Demonstrator

CERN Document Server

Tang, F; Anderson, K; Bohm, C; Hildebrand, K; Muschter, S; Oreglia, M

2015-01-01

The TileCal Demonstrator is a prototype for a future upgrade to the ATLAS hadron calorimeter when the Large Hadron Collider increases luminosity in year 2023 (HL-LHC). It will be used for functionality and performance tests. The Demonstrator has 48 channels of upgraded readout and digitizing electronics and a new digital trigger capability, but is backwards-compatible with the present detector system insofar as it also provides analog trigger signals. The Demonstrator is comprised of 4 identical mechanical mini-drawers, each equipped with up to 12 photomultipliers (PMTs). The on-detector electronics includes 45 Front-End Boards, each serving an individual PMT; 4 Main Boards, each to control and digitize up to 12 PMT signals, and 4 corresponding high-speed Daughter Boards serving as data hubs between on-detector and off-detector electronics. The Demonstrator is fully compatible with the present system, accepting ATLAS triggers, timing and slow control commands for the data acquisition, detector control, and de...

Using intuition in fuzzy front-end decision-making : a conceptual framework

NARCIS (Netherlands)

Eling, K.; Griffin, A.; Langerak, F.

2014-01-01

The goal of decision-making during the execution of the fuzzy front end (FFE) is to develop a creative new product concept. Although intuitive decision-making has been found to increase new product creativity, the theoretical knowledge base as to why and under which conditions intuition use during

Development of Radhard VLSI electronics for SSC calorimeters

International Nuclear Information System (INIS)

Dawson, J.W.; Nodulman, L.J.

1989-01-01

A new program of development of integrated electronics for liquid argon calorimeters in the SSC detector environment is being started at Argonne National Laboratory. Scientists from Brookhaven National Laboratory and Vanderbilt University together with an industrial participants are expected to collaborate in this work. Interaction rates, segmentation, and the radiation environment dictate that front-end electronics of SSC calorimeters must be implemented in the form of highly integrated, radhard, analog, low noise, VLSI custom monolithic devices. Important considerations are power dissipation, choice of functions integrated on the front-end chips, and cabling requirements. An extensive level of expertise in radhard electronics exists within the industrial community, and a primary objective of this work is to bring that expertise to bear on the problems of SSC detector design. Radiation hardness measurements and requirements as well as calorimeter design will be primarily the responsibility of Argonne scientists and our Brookhaven and Vanderbilt colleagues. Radhard VLSI design and fabrication will be primarily the industrial participant's responsibility. The rapid-cycling synchrotron at Argonne will be used for radiation damage studies involving response to neutrons and charged particles, while damage from gammas will be investigated at Brookhaven. 10 refs., 6 figs., 2 tabs

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber

KAUST Repository

Shi, Xian

2017-01-05

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber are numerically investigated using an 1-D unsteady, shock-capturing, compressible and reacting flow solver. Different combinations of reaction front propagation and end-gas combustion modes are observed, i.e., 1) deflagration without end-gas combustion, 2) deflagration to end-gas autoignition, 3) deflagration to end-gas detonation, 4) developing or developed detonation, occurring in the sequence of increasing initial temperatures. Effects of ignition location and chamber size are evaluated: the asymmetric ignition is found to promote the reactivity of unburnt mixture compared to ignitions at center/wall, due to additional heating from asymmetric pressure waves. End-gas combustion occurs earlier in smaller chambers, where end-gas temperature rise due to compression heating from the deflagration is faster. According to the ξ−ε regime diagram based on Zeldovich theory, modes of reaction front propagation are primarily determined by reactivity gradients introduced by initial ignition, while modes of end-gas combustion are influenced by the total amount of unburnt mixture at the time when autoignition occurs. A transient reactivity gradient method is provided and able to capture the occurrence of detonation.

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber

KAUST Repository

Shi, Xian; Ryu, Je Ir; Chen, Jyh-Yuan; Dibble, Robert W.

2017-01-01

Modes of reaction front propagation and end-gas combustion of hydrogen/air mixtures in a closed chamber are numerically investigated using an 1-D unsteady, shock-capturing, compressible and reacting flow solver. Different combinations of reaction front propagation and end-gas combustion modes are observed, i.e., 1) deflagration without end-gas combustion, 2) deflagration to end-gas autoignition, 3) deflagration to end-gas detonation, 4) developing or developed detonation, occurring in the sequence of increasing initial temperatures. Effects of ignition location and chamber size are evaluated: the asymmetric ignition is found to promote the reactivity of unburnt mixture compared to ignitions at center/wall, due to additional heating from asymmetric pressure waves. End-gas combustion occurs earlier in smaller chambers, where end-gas temperature rise due to compression heating from the deflagration is faster. According to the ξ−ε regime diagram based on Zeldovich theory, modes of reaction front propagation are primarily determined by reactivity gradients introduced by initial ignition, while modes of end-gas combustion are influenced by the total amount of unburnt mixture at the time when autoignition occurs. A transient reactivity gradient method is provided and able to capture the occurrence of detonation.

Microwave integrated circuit radiometer front-ends for the Push Broom Microwave Radiometer

Science.gov (United States)

Harrington, R. F.; Hearn, C. P.

1982-01-01

Microwave integrated circuit front-ends for the L-band, S-band and C-band stepped frequency null-balanced noise-injection Dicke-switched radiometer to be installed in the NASA Langley airborne prototype Push Broom Microwave Radiometer (PBMR) are described. These front-ends were developed for the fixed frequency of 1.413 GHz and the variable frequencies of 1.8-2.8 GHz and 3.8-5.8 GHz. Measurements of the noise temperature of these units were made at 55.8 C, and the results of these tests are given. While the overall performance was reasonable, improvements need to be made in circuit losses and noise temperatures, which in the case of the C-band were from 1000 to 1850 K instead of the 500 K specified. Further development of the prototypes is underway to improve performance and extend the frequency range.

Characterization of EASIROC as front-end for the readout of the SiPM at the focal plane of the Cherenkov telescope ASTRI

International Nuclear Information System (INIS)

Impiombato, D.; Giarrusso, S.; Mineo, T.; Belluso, M.; Billotta, S.; Bonanno, G.; Catalano, O.; Grillo, A.; La Rosa, G.; Marano, D.; Sottile, G.

2013-01-01

The Extended Analogue Silicon Photo-multiplier Integrated Read Out Chip, EASIROC, is a chip proposed as front-end of the camera at the focal plane of the imaging Cherenkov ASTRI SST-2M telescope prototype. This paper presents the results of the measurements performed to characterize EASIROC in order to evaluate its compliance with the ASTRI SST-2M focal plane requirements. In particular, we investigated the trigger time walk and the jitter effects as a function of the pulse amplitude. The EASIROC output signal is found to vary linearly as a function of the input pulse amplitude with very low level of electronic noise and cross-talk (<1%). Our results show that it is suitable as front-end chip for the camera prototype, although, specific modifications are necessary to adopt the device in the final version of the telescope

Design and simulation of front end power converter for a microgrid with fuel cells and solar power sources

Science.gov (United States)

Jeevargi, Chetankumar; Lodhi, Anuj; Sateeshkumar, Allu; Elangovan, D.; Arunkumar, G.

2017-11-01

The need for Renewable Energy Sources (RES) is increasing due to increased demand for the supply of power and it is also environment friendly.In the recent few years, the cost of generation of the power from the RES has been decreased. This paper aims to design the front end power converter which is required for integrating the fuel cells and solar power sources to the micro grid. The simulation of the designed front end converter is carried out in the PSIM 9.1.1 software. The results show that the designed front end power converter is sufficient for integrating the micro grid with fuel cells and solar power sources.

Design and Optimization of Multi-bit Front-end Stage and Scaled Back-end Stages of Pipelined ADCs

NARCIS (Netherlands)

Quinn, P.J.; Roermund, van A.H.M.

2005-01-01

In this paper, an error analysis is presented to aid the design of a pipeline multi-bit front-end stage. It is demonstrated and quantified how the capacitor matching requirement can be reduced in high-resolution pipeline ADCs. The paper continues by analyzing the optimal design for low power of the

ONE SIZE DOES NOT FIT ALL — UNDERSTANDING THE FRONT-END AND BACK-END OF BUSINESS MODEL INNOVATION

OpenAIRE

FRANZISKA GÜNZEL; ANNA B. HOLM

2013-01-01

Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovatio...

AiGERM: A logic programming front end for GERM

Science.gov (United States)

Hashim, Safaa H.

1990-01-01

AiGerm (Artificially Intelligent Graphical Entity Relation Modeler) is a relational data base query and programming language front end for MCC (Mission Control Center)/STP's (Space Test Program) Germ (Graphical Entity Relational Modeling) system. It is intended as an add-on component of the Germ system to be used for navigating very large networks of information. It can also function as an expert system shell for prototyping knowledge-based systems. AiGerm provides an interface between the programming language and Germ.

EBR-II Cover Gas Cleanup System upgrade distributed control and front end computer systems

International Nuclear Information System (INIS)

Carlson, R.B.

1992-01-01

The Experimental Breeder Reactor II (EBR-II) Cover Gas Cleanup System (CGCS) control system was upgraded in 1991 to improve control and provide a graphical operator interface. The upgrade consisted of a main control computer, a distributed control computer, a front end input/output computer, a main graphics interface terminal, and a remote graphics interface terminal. This paper briefly describes the Cover Gas Cleanup System and the overall control system; gives reasons behind the computer system structure; and then gives a detailed description of the distributed control computer, the front end computer, and how these computers interact with the main control computer. The descriptions cover both hardware and software

Analog Organic Electronics Building Blocks for Organic Smart Sensor Systems on Foil

CERN Document Server

Marien, Hagen; Heremans, Paul

2013-01-01

 This book provides insight into organic electronics technology and in analog circuit techniques that can be used to increase the performance of both analog and digital organic circuits. It explores the domain of organic electronics technology for analog circuit applications, specifically smart sensor systems.  It focuses on all the building blocks in the data path of an organic sensor system between the sensor and the digital processing block. Sensors, amplifiers, analog-to-digital converters and DC-DC converters are discussed in detail. Coverage includes circuit techniques, circuit implementation, design decisions and measurement results of the building blocks described. Offers readers the first book to focus on analog organic circuit design; Discusses organic electronics technology for analog circuit applications in the context of smart sensor systems; Describes all building blocks necessary for an organic sensor system between the sensor and the digital processing block; Includes circuit techniques, cir...

An Upgraded Front-End Switching Power Supply Design For the ATLAS TileCAL Detector of the LHC

CERN Document Server

Drake, Gary; The ATLAS collaboration

2011-01-01

We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

An Upgraded Front-End Switching Power Supply Design for the ATLAS TileCAL Detector of the LHC

CERN Document Server

Drake, G; The ATLAS collaboration; De Lurgio, P; Henriques, A; Minashvili, I; Nemecek, S; Price, L; Proudfoot, J; Stanek, R

2011-01-01

We present the design of an upgraded switching power supply brick for the front-end electronics of the ATLAS hadron tile calorimeter (TileCAL) at the LHC. The new design features significant improvement in noise, improved fault detection, and generally a more robust design, while retaining the compact size, water-cooling, output control, and monitoring features in this 300 KHz design. We discuss the improvements to the design, and the radiation testing that we have done to qualify the design. We also present our plans for the production of 2400 new bricks for installation on the detector in 2013.

Front end power dissipation minimization and optimal transmission rate for wireless receivers

NARCIS (Netherlands)

Heuvel, van den J.H.C.; Wu, Y.; Baltus, P.G.M.; Linnartz, J.P.M.G.; Roermund, van A.H.M.

2014-01-01

Most wireless battery-operated devices spend more energy receiving than transmitting. Hence, minimizing the power dissipation in the receiver front end, which, in many cases, is the prominent power consuming part of the receiver, is an important challenge. This paper addresses this challenge by

The Discourse on Printed and Electronic Books: Analogies, Oppositions, and Perspectives

Science.gov (United States)

Velagic, Zoran

2014-01-01

Introduction: The point of departure for this paper is the twofold analogy (analogy of content, analogy of medium) between printed and electronic books, the aim being to draw attention to the usual perception of their capacities and relationships, to provide a rather detailed analysis of the outcome and sustainability of such analogies and…

The Front-End Concentrator card for the RD51 Scalable Readout System

International Nuclear Information System (INIS)

Toledo, J; Esteve, R; Monzó, J M; Tarazona, A; Muller, H; Martoiu, S

2011-01-01

Conventional readout systems exist in many variants since the usual approach is to build readout electronics for one given type of detector. The Scalable Readout System (SRS) developed within the RD51 collaboration relaxes this situation considerably by providing a choice of frontends which are connected over a customizable interface to a common SRS DAQ architecture. This allows sharing development and production costs among a large base of users as well as support from a wide base of developers. The Front-end Concentrator card (FEC), a RD51 common project between CERN and the NEXT Collaboration, is a reconfigurable interface between the SRS online system and a wide range of frontends. This is accomplished by using application-specific adapter cards between the FEC and the frontends. The ensemble (FEC and adapter card are edge mounted) forms a 6U × 220 mm Eurocard combo that fits on a 19'' subchassis. Adapter cards exist already for the first applications and more are in development.

First test results from the Front-End Board with Cyclone V as a test high-resolution platform for the Auger-Beyond-2015 Front End Electronics

Energy Technology Data Exchange (ETDEWEB)

Szadkowski, Zbigniew [University of Lodz, Department of Physics and Applied Informatics, Faculty of High-Energy Astrophysics, 90-236 Lodz, Pomorska 149, (Poland)

2015-07-01

The paper presents the first results from the Front- End Board (FEB) with the biggest Cyclone{sup R} V E FPGA 5CEFA9F31I7N, supporting 8 channels sampled up to 250 MSps at 14-bit resolution. Considered sampling for the SD is 120 MSps, however, the FEB has been developed with external anti-aliasing filters to keep a maximal flexibility. Six channels are targeted to the SD, two the rest for other experiments like: Auger Engineering Radio Array and additional muon counters. More channels and higher sampling generate larger size of registered events. We used the standard radio channel for a radio transmission from the detectors to the Central Data Acquisition Station (CDAS) to avoid at present a significant modification of a software in both sides: the detector and the CDAS (planned in a future for a final design). Seven FEBs have been deployed in the test detectors on a dedicated Engineering Array in a hexagon. Several variants of the FPGA code were tested for 120, 160, 200 and even 240 MSps DAQ. Tests confirmed a stability and reliability of the FEB design in real pampas conditions with more than 40 deg. C daily temperature variation and a strong sun exposition with a limited power budget only from a single solar panel. (authors)

Single-chip CMUT-on-CMOS front-end system for real-time volumetric IVUS and ICE imaging.

Science.gov (United States)

Gurun, Gokce; Tekes, Coskun; Zahorian, Jaime; Xu, Toby; Satir, Sarp; Karaman, Mustafa; Hasler, Jennifer; Degertekin, F Levent

2014-02-01

Intravascular ultrasound (IVUS) and intracardiac echography (ICE) catheters with real-time volumetric ultrasound imaging capability can provide unique benefits to many interventional procedures used in the diagnosis and treatment of coronary and structural heart diseases. Integration of capacitive micromachined ultrasonic transducer (CMUT) arrays with front-end electronics in single-chip configuration allows for implementation of such catheter probes with reduced interconnect complexity, miniaturization, and high mechanical flexibility. We implemented a single-chip forward-looking (FL) ultrasound imaging system by fabricating a 1.4-mm-diameter dual-ring CMUT array using CMUT-on-CMOS technology on a front-end IC implemented in 0.35-μm CMOS process. The dual-ring array has 56 transmit elements and 48 receive elements on two separate concentric annular rings. The IC incorporates a 25-V pulser for each transmitter and a low-noise capacitive transimpedance amplifier (TIA) for each receiver, along with digital control and smart power management. The final shape of the silicon chip is a 1.5-mm-diameter donut with a 430-μm center hole for a guide wire. The overall front-end system requires only 13 external connections and provides 4 parallel RF outputs while consuming an average power of 20 mW. We measured RF A-scans from the integrated single- chip array which show full functionality at 20.1 MHz with 43% fractional bandwidth. We also tested and demonstrated the image quality of the system on a wire phantom and an ex vivo chicken heart sample. The measured axial and lateral point resolutions are 92 μm and 251 μm, respectively. We successfully acquired volumetric imaging data from the ex vivo chicken heart at 60 frames per second without any signal averaging. These demonstrative results indicate that single-chip CMUT-on-CMOS systems have the potential to produce realtime volumetric images with image quality and speed suitable for catheter-based clinical applications.

The front end electronics of the NA62 Gigatracker: challenges, design and experimental measurements

Science.gov (United States)

Noy, M.; Aglieri Rinella, G.; Ceccucci, A.; Dellacasa, G.; Fiorini, M.; Garbolino, S.; Jarron, P.; Kaplon, J.; Kluge, A.; Marchetto, F.; Martin, E.; Mazza, G.; Martoiu, S.; Morel, M.; Perktold, L.; Rivetti, A.; Tiuraniemi, S.

2011-06-01

The beam spectrometer of the NA62 experiment consists of 3 Gigatracker (GTK) stations. Each station comprises a pixel detector of 16 cm active area made of an assembly of 10 readout ASICs bump bonded to a 200 μm thick pixel silicon sensor, comprising 18000 pixels of 300 μm×300 μm. The main challenge of the NA62 pixel GTK station is the combination of an extremely high kaon/pion beam rate, where the intensity in the center of the beam reaches up to 1.5 Mhit s mm together with an extreme time resolution of 100 ps. To date, it is the first silicon tracking system with this time resolution. To face this challenge, the pixel analogue front end has been designed with a peaking time of 4 ns, with a planar silicon sensor operating up to 300 V over depletion. Moreover, the radiation level is severe, 2×10 1 MeV n cm per year of operation. Easy replacement of the GTK stations is foreseen as a design requirement. The amount of material of a single station should also be less than 0.5% X to minimize the background, which imposes strong constraints on the mechanics and the cooling system. We report upon the design and architecture of the 2 prototype demonstrator chips both designed in 130 nm CMOS technology, one with a constant fraction discriminator and the time stamp digitisation in each pixel (In-Pixel), and the other with a time-over-threshold discriminator and the processing of the time stamp located in the End of Column (EoC) region at the chip periphery. Some preliminary results are presented.

Instrument front-ends at Fermilab during Run II

Science.gov (United States)

Meyer, T.; Slimmer, D.; Voy, D.

2011-11-01

The optimization of an accelerator relies on the ability to monitor the behavior of the beam in an intelligent and timely fashion. The use of processor-driven front-ends allowed for the deployment of smart systems in the field for improved data collection and analysis during Run II. This paper describes the implementation of the two main systems used: National Instruments LabVIEW running on PCs, and WindRiver's VxWorks real-time operating system running in a VME crate processor. Work supported by Fermi Research Alliance, LLC under Contract No. DE-AC02-07CH11359 with the United States Department of Energy.

CPRF/ZTH front-end torus design and fabrication status

International Nuclear Information System (INIS)

Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

1989-01-01

Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

CPRF/ZTH front-end torus design and fabrication status

International Nuclear Information System (INIS)

Ballard, E.O.; Baker, C.; Gomez, T.; Prince, P.P.; Smith, R.L.

1989-01-01

Design of the ZTH front-end torus has been completed for a new generation Reversed Field Pinch (RFP) machine to be assembled at Los Alamos National Laboratory during FY 92. The Confinement Physics Research Facility (CPRF) houses the ZTH front-end torus. The ZTH torus consists of an Inconel 625 vacuum vessel supported by an external electrically conducting 304L stainless steel shell. Interspace support rings support the vacuum vessel to the shell and also provide accurate radial support for the interspace electrical diagnostics. The shell also supports 48 toroidal field coils that are mounted to the shell's external surface. The shell consists of an explosion bonded stainless steel-copper composite with water-cooling tube assemblies attached to the outer surface. The 0.135-in. thick copper is on the inside surface of the shell, and provides an electrically conducting path with the required electrical time constant of 50 ms. The shell plate will be formed to the required toroidal configuration, after which the poloidal and toroidal flanges will be welded to the structure and machined. The Inconel vacuum vessel consists of bellows segments, armor support rings, and diagnostic stations welded together to form the complete vacuum vessel assembly. The necessity for accurate positioning of the vacuum vessel within the shell requires that the shell and vacuum vessel be fabricated with major diameter tolerances within 0.050-in. true position of the nominal diameters of 188.0-in. and 188.820-in., respectively. 7 figs

Social Networks in the Front End: The Organizational Life of an Idea

NARCIS (Netherlands)

R.C. Kijkuit (Bob)

2007-01-01

textabstractAn effective front end (FE) of the new product development (NPD) process is important for innovative performance in companies. To date the NPD literature has mainly focused on the selection process of ideas and very little on the processes that take place before selection. This study

Front-end readout system for PHENIX RICH

International Nuclear Information System (INIS)

Tanaka, Y.; Hara, H.; Ebisu, K.; Hibino, M.; Kametani, S.; Kikuchi, J.; Wintenberg, A.L.; Walker, J.W.; Franck, S.; Moscone, C.; Jones, J.P.; Young, G.R.; Matsumoto, T.; Sakaguchi, T.; Oyama, K.; Hamagaki, H.

2000-01-01

A front-end readout system with a custom backplane and custom circuit modules has been developed for the RICH subsystem of the PHENIX experiment. The design specifications and test results of the backplane and the modules are presented in this paper. In the module design, flexibility for modification is maximized through the use of Complex Programmable Logic Devices. In the backplane design, a source-synchronous bus architecture is adopted for the data and control bus. The transfer speed of the backplane has reached 640 Mbyte/s with a 128-bit data bus. Total transaction time is estimated to be less than 30 μs per event when this system is used in the experiment. This result indicates that the performance satisfies the data-rate requirement of the PHENIX experiment

Design and Implementation of an Electronic Front-End Based on Square Wave Excitation for Ultrasonic Torsional Guided Wave Viscosity Sensor

Directory of Open Access Journals (Sweden)

Amir Rabani

2016-10-01

Full Text Available The market for process instruments generally requires low cost devices that are robust, small in size, portable, and usable in-plant. Ultrasonic torsional guided wave sensors have received much attention by researchers for measurement of viscosity and/or density of fluids in recent years. The supporting electronic systems for these sensors providing many different settings of sine-wave signals are bulky and expensive. In contrast, a system based on bursts of square waves instead of sine waves would have a considerable advantage in that respect and could be built using simple integrated circuits at a cost that is orders of magnitude lower than for a windowed sine wave device. This paper explores the possibility of using square wave bursts as the driving signal source for the ultrasonic torsional guided wave viscosity sensor. A simple design of a compact and fully automatic analogue square wave front-end for the sensor is also proposed. The successful operation of the system is demonstrated by using the sensor for measuring the viscosity in a representative fluid. This work provides the basis for design and manufacture of low cost compact standalone ultrasonic guided wave sensors and enlightens the possibility of using coded excitation techniques utilising square wave sequences in such applications.

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

International Nuclear Information System (INIS)

Erdinger, Florian

2016-01-01

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Design of front end electronics and a full scale 4k pixel readout ASIC for the DSSC X-ray detector at the European XFEL

Energy Technology Data Exchange (ETDEWEB)

Erdinger, Florian

2016-11-22

The goal of this thesis was to design a large scale readout ASIC for the 1-Mega pixel DEPFET Sensor with Signal Compression (DSSC) detector system which is being developed by an international collaboration for the European XFEL (EuXFEL). Requirements for the DSSC detector include single photon detection down to 0.5 keV combined with a large dynamic range of up to 10000 photons at frame rates of up to 4.5 MHz. The detector core concepts include full parallel readout, signal compression on the sensor or ASIC level, filtering, immediate digitization and local storage within the pixel. The DSSC is a hybrid pixel detector, each sensor pixel mates to a dedicated ASIC pixel, which includes the entire specified signal processing chain along with auxiliary circuits. One ASIC comprises 4096 pixels and a full periphery including biasing and digital control. This thesis presents the design of the ASIC, its components and integration are described in detail. Emphasis is put on the design of the analog front-end. The first full format ASIC (F1) has been fabricated within the scope of this thesis along with numerous test chips. Furthermore, the EuXFEL and the DSSC detector system are presented to create the context for the ASIC, which is the core topic of this thesis.

Laser based beam diagnostic for the RAL Front End Test Stand (FETS)

International Nuclear Information System (INIS)

Gabor, C.; Lee, D. A.; Pozimski, J. K.; Letchford, A.

2007-01-01

For the diagnostic of high power particle beams, non-destructive measurement devices provide minimum influence on the beam and avoid various problems in connection with the high power density on surfaces. An H- ion beam offers the opportunity of non destructive beam diagnostics based on the effect of photo detachment. By the interaction of light with H- ions, the additional electron can be detached and a small number of neutrals will be produced. An additional magnetic dipole field can then be used to separate the detached electrons and neutrals from the ions. Using an integral detector the spatial distribution of the beam ion density can be derived, while the use of a spatial resolving detector enables to determine the phase space distribution. To investigate the measurement principle of the latter, a test stand was set up at the IAP in Frankfurt. This system will now be adopted to the requirements of the Front End Test Stand at CCLRC/ RAL. The aim of this FETS is to demonstrate a chopped H- beam of 60mA at 3MeV and 50pps with sufficiently high beam quality. The paper will present a detailed description of the proposed set up at RAL and discuss several results of simulations and experimental data gained in Frankfurt

Characterization of silicon microstrip sensors, front-end electronics, and prototype tracking detectors for the CBM experiment at FAIR

Energy Technology Data Exchange (ETDEWEB)

Sorokin, Iurii

2013-07-01

The Compressed Baryonic Matter (CBM) experiment will explore the phase diagram of strongly interacting matter in the region of high net baryonic densities. The matter at the extreme conditions will be studied in collisions of a heavy ion beam with a fixed heavy element target. The present work is devoted to the development of the main component of the CBM experiment - the Silicon Tracking System (STS). The STS has to enable reconstruction of up to 1000 charged particle tracks per nucleus-nucleus interaction at the rate of up to 10 MHz, provide a momentum resolution Δp/p of 1 %, and withstand the radiation load of up to 10{sup 14} n{sub eq}/cm{sup 2} (n{sub eq}-neutron equivalent). The STS will be based on double-sided silicon microstrip sensors, that will be arranged in 8 planes in the aperture of the dipole magnet. Selftriggering readout electronics will be located on the periphery of the detecting planes, and connected to the sensors with low mass microcables. In the stage of R and D, as well as in the stages of pre-series and series production, characterization of the sensors, of the front-end electronics, and of the complete detector modules has to be performed. In the present work the required techniques were developed, and the performance of the latest detector prototypes was evaluated. A particular attention is paid to evaluation of the signal amplitude, as it is one of the most important detector characteristics. Techniques for measuring the passive electrical characteristics of the sensors were developed. These include: the coupling and the interstrip capacitances, the interstrip resistance, the bias resistance, the strip leakage current, the bulk capacitance, and the bulk leakage current. The techniques will be applied for the quality assurance of the sensors during the pre-series and the series production. Extensive characterization of the prototype readout chip, n-XYTER, was performed. The register settings were optimized, and the dependence of the

Influence Of Tools Input/Output Requirements On Managers Core Front End Activities In New Product Development

DEFF Research Database (Denmark)

Appio, Francesco P.; Achiche, Sofiane; Minin, Alberto Di

2011-01-01

opportunities; make this early phase of the innovation process uncertain and extremely risky. Literature suggests that the understanding, selection and use of appropriate tools/techniques to support decision making are instrumental for a less fuzzy front end of innovation. This paper considers the adoption......The object of analysis of this explorative research is the Fuzzy Front End of Innovation in Product Development, described by those activities going from the opportunity identification to the concept definition. Business scholars have shown that confusion in terms of goals and different ideas about...

Development of the control system of the ALICE Transition Radiation Detector and of a test environment for quality-assurance of its front-end electronics

CERN Document Server

Mercado Pérez, Jorge

2008-01-01

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE.

Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

International Nuclear Information System (INIS)

Mercado Perez, Jorge

2008-01-01

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

Development of the control system of the ALICE transition radiation detector and of a test environment for quality-assurance of its front-end electronics

Energy Technology Data Exchange (ETDEWEB)

Mercado Perez, Jorge

2008-11-10

Within this thesis, the detector control system (DCS) for the Transition Radiation Detector (TRD) of the ALICE experiment at the Large Hadron Collider has been developed. The TRD DCS is fully implemented as a detector oriented hierarchy of objects behaving as finite state machines. It controls and monitors over 65 thousand front-end electronics (FEE) units, a few hundred low voltage and one thousand high voltage channels, and other sub-systems such as cooling and gas. Commissioning of the TRD DCS took place during several runs with ALICE using cosmic events. Another part of this thesis describes the development of a test environment for large-scale production quality-assurance of over 4 thousand FEE read-out boards containing in total about 1.2 million read-out channels. The hardware and software components are described in detail. Additionally, a series of performance studies were carried out earlier including radiation tolerance tests of the TRAP chip which is the core component of the TRD FEE. (orig.)

Single Event Upsets in the ATLAS IBL Front End ASICs

CERN Document Server

Rozanov, Alexander; The ATLAS collaboration

2018-01-01

During operation at instantaneous luminosities of up to 2.1 10^{34} cm^{-2} s^{-1} the front end chips of the ATLAS innermost pixel layer (IBL) experienced single event upsets affecting its global registers as well as the settings for the individual pixels, causing, among other things loss of occupancy, noisy pixels, and silent pixels. A quantitative analysis of the single event upsets as well as the operational issues and mitigation techniques will be presented.

RHIC detector electronics R and D proposal (number-sign RH-8) - development of analog memories for RHIC detector front-end electronic systems

International Nuclear Information System (INIS)

Konstantinidis, A.; Ledoux, R.; Steadman, S.; Stephans, G.; Wadsworth, B.

1990-01-01

Detectors for colliding beam experiments at RHIC will provide 4pi coverage and are expected to contain from 10**5 to 10**6 channels. As the 2 to 5usec required to generate first-level triggers is long compared with RHIC's 114nsec beam crossing interval, there will be a need not only to deal with signals from a great number of channels but also to store and tag these signals over many beam crossings. The authors are concentrating their efforts on developing the switched-capacitor (SC) analog memory as the generic mechanism for storing detector signals. Switched-capacitor circuits can be implemented using metaloxide-semiconductor (MOS) technology; and, for development work, they have relatively easy access to a number of foundries running different MOS processes the choice of which would depend on the exact nature of their application. In terms of memory applications, several MOS-based designs have been reported in the literature. MOS technology is generally considered to have advantages over charge-coupled devices in terms of lower power dissipation, lower noise, better linearity, better radiation hardness, and lower cost: all desirable characteristics for a device to be used in a particle detector. However, the authors have recently learned of new developments in CCD technology at MIT's Lincoln Laboratory, and they find that the advantage of MOS technology over CCD technology, at least in terms of the parameters mentioned above, may not be as marked as once thought. Since CCD's have some interesting features which make them potentially useful for pipeline trigger applications, if not for the more general storage applications they are considering here, they intend to keep in close contact with this work

A Low Cost Bluetooth Low Energy Transceiver for Wireless Sensor Network Applications with a Front-end Receiver-Matching Network-Reusing Power Amplifier Load Inductor.

Science.gov (United States)

Liang, Zhen; Li, Bin; Huang, Mo; Zheng, Yanqi; Ye, Hui; Xu, Ken; Deng, Fangming

2017-04-19

In this work, a low cost Bluetooth Low Energy (BLE) transceiver for wireless sensor network (WSN) applications, with a receiver (RX)-matching network-reusing power amplifier (PA) load inductor, is presented. In order to decrease the die area, only two inductors were used in this work. Besides the one used in the voltage control oscillator (VCO), the PA load inductor was reused as the RX impedance matching component in the front-end. Proper controls have been applied to achieve high transmitter (TX) input impedance when the transceiver is in the receiving mode, and vice versa. This allows the TRX-switch/matching network integration without significant performance degradation. The RX adopted a low-IF structure and integrated a single-ended low noise amplifier (LNA), a current bleeding mixer, a 4th complex filter and a delta-sigma continuous time (CT) analog-to-digital converter (ADC). The TX employed a two-point PLL-based architecture with a non-linear PA. The RX achieved a sensitivity of -93 dBm and consumes 9.7 mW, while the TX achieved a 2.97% error vector magnitude (EVM) with 9.4 mW at 0 dBm output power. This design was fabricated in a 0.11 μm complementary metal oxide semiconductor (CMOS) technology and the front-end circuit only occupies 0.24 mm². The measurement results verify the effectiveness and applicability of the proposed BLE transceiver for WSN applications.

Production of the front-end boards of the LHCb muon system

CERN Document Server

Bonivento, W; Auriemma, G

2008-01-01

This note describes the production of the front end boards CARDIAC, for the 1368 MWPC, and CARDIAC-GEM, for the 12 triple-GEM chambers, of the LHCb muon system. The PCB structure and component layout and the production issues, such as component soldering, quality assurance at the company and delivery rates, are described. The performance of these boards will be the subject of a future publication.

Design and performance Assessment of an Airborne Ice Sounding Radar Front-End

DEFF Research Database (Denmark)

Hernández, Carlos Cilla; Krozer, Viktor; Vidkjær, Jens

2008-01-01

The paper describes the design and experimental performance assessment of the RF front-end of an airborne P-band ice sounding radar. The ice sounder design features newly developed components at a centre frequency of 435 MHz, such as, antenna 20% bandwidth at RL ≪ 13 dB, compact high power in...

Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

Directory of Open Access Journals (Sweden)

Umit H. Yapanel

2008-08-01

Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

Towards an Intelligent Acoustic Front End for Automatic Speech Recognition: Built-in Speaker Normalization

Directory of Open Access Journals (Sweden)

Yapanel UmitH

2008-01-01

Full Text Available A proven method for achieving effective automatic speech recognition (ASR due to speaker differences is to perform acoustic feature speaker normalization. More effective speaker normalization methods are needed which require limited computing resources for real-time performance. The most popular speaker normalization technique is vocal-tract length normalization (VTLN, despite the fact that it is computationally expensive. In this study, we propose a novel online VTLN algorithm entitled built-in speaker normalization (BISN, where normalization is performed on-the-fly within a newly proposed PMVDR acoustic front end. The novel algorithm aspect is that in conventional frontend processing with PMVDR and VTLN, two separating warping phases are needed; while in the proposed BISN method only one single speaker dependent warp is used to achieve both the PMVDR perceptual warp and VTLN warp simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces simultaneously. This improved integration unifies the nonlinear warping performed in the front end and reduces computational requirements, thereby offering advantages for real-time ASR systems. Evaluations are performed for (i an in-car extended digit recognition task, where an on-the-fly BISN implementation reduces the relative word error rate (WER by 24%, and (ii for a diverse noisy speech task (SPINE 2, where the relative WER improvement was 9%, both relative to the baseline speaker normalization method.

NECTAr: New electronics for the Cherenkov Telescope Array

International Nuclear Information System (INIS)

Vorobiov, S.; Bolmont, J.; Corona, P.; Delagnes, E.; Feinstein, F.; Gascon, D.; Glicenstein, J.-F.; Naumann, C.L.; Nayman, P.; Sanuy, A.; Toussenel, F.; Vincent, P.

2011-01-01

The European astroparticle physics community aims to design and build the next generation array of Imaging Atmospheric Cherenkov Telescopes (IACTs), that will benefit from the experience of the existing H.E.S.S. and MAGIC detectors, and further expand the very-high energy astronomy domain. In order to gain an order of magnitude in sensitivity in the 10 GeV to >100TeV range, the Cherenkov Telescope Array (CTA) will employ 50-100 mirrors of various sizes equipped with 1000-4000 channels per camera, to be compared with the 6000 channels of the final H.E.S.S. array. A 3-year program, started in 2009, aims to build and test a demonstrator module of a generic CTA camera. We present here the NECTAr design of front-end electronics for the CTA, adapted to the trigger and data acquisition of a large IACTs array, with simple production and maintenance. Cost and camera performances are optimized by maximizing integration of the front-end electronics (amplifiers, fast analog samplers, ADCs) in an ASIC, achieving several GS/s and a few μs readout dead-time. We present preliminary results and extrapolated performances from Monte Carlo simulations.

NECTAr: New electronics for the Cherenkov Telescope Array

Energy Technology Data Exchange (ETDEWEB)

Vorobiov, S., E-mail: vorobiov@lpta.in2p3.f [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Bolmont, J.; Corona, P. [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France); Delagnes, E. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Feinstein, F. [LPTA, Universite Montpellier II and IN2P3/CNRS, Montpellier (France); Gascon, D. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Glicenstein, J.-F. [IRFU/DSM/CEA, Saclay, Gif-sur-Yvette (France); Naumann, C.L.; Nayman, P. [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France); Sanuy, A. [ICC-UB, Universitat Barcelona, Barcelona (Spain); Toussenel, F.; Vincent, P. [LPNHE, Universite Paris VI and IN2P3/CNRS, Paris (France)

2011-05-21

The European astroparticle physics community aims to design and build the next generation array of Imaging Atmospheric Cherenkov Telescopes (IACTs), that will benefit from the experience of the existing H.E.S.S. and MAGIC detectors, and further expand the very-high energy astronomy domain. In order to gain an order of magnitude in sensitivity in the 10 GeV to >100TeV range, the Cherenkov Telescope Array (CTA) will employ 50-100 mirrors of various sizes equipped with 1000-4000 channels per camera, to be compared with the 6000 channels of the final H.E.S.S. array. A 3-year program, started in 2009, aims to build and test a demonstrator module of a generic CTA camera. We present here the NECTAr design of front-end electronics for the CTA, adapted to the trigger and data acquisition of a large IACTs array, with simple production and maintenance. Cost and camera performances are optimized by maximizing integration of the front-end electronics (amplifiers, fast analog samplers, ADCs) in an ASIC, achieving several GS/s and a few {mu}s readout dead-time. We present preliminary results and extrapolated performances from Monte Carlo simulations.

RF Front End Based on MEMS Components for Miniaturized Digital EVA Radio, Phase II

Data.gov (United States)

National Aeronautics and Space Administration — In this SBIR project, AlphaSense, Inc. and the Carnegie Mellon University propose to develop a RF receiver front end based on CMOS-MEMS components for miniaturized...

An Electronic Model of the ATLAS Phase-1 Upgrade Hadronic Endcap Calorimeter Front End Crate Baseplane

CERN Document Server

Porter, Ryan

This thesis presents an electrical model of two pairs of interconnects of the ATLAS Phase-1 Upgrade Hadronic Endcap Front End Crate prototype baseplane. Stripline transmission lines of the baseplane are modeled using Keysight Technologies' Electromagnetic Professional's (EMPro) 3D electromagnetic simulation (Finite Element Method) and the connectors are modeled using built-in models in Keysight Technologies' Advanced Design System (ADS). The model is compared in both the time and frequency domain to measured Time Domain Reflectometer (TDR) traces and S-parameters. The S-parameters of the model are found to be within $5\\%$ of the measured S-parameters for transmission and reflection, and range from $25\\%$ below to $100\\%$ above for forward and backward crosstalk. To make comparisons with measurements, the cables used to connect the prototype HEC baseplane to the measurement system had to be included in the model. Plots of the S-parameters of a model without these cables are presented for one pair of interconne...

Structuring front-end innovation activities throughout strategic product planning

Directory of Open Access Journals (Sweden)

Thaisa Rodrigues

Full Text Available Abstract Strategic product planning (SPP for new product development (NPD in the front-end of innovation (FEI is a great challenge for managers and practitioners. This article analyzes the structuring process of FEI activities during SPP. A research was carried out with 78 industries from both food and furniture in Brazil. Our study revealed that FEI activities are structured in an intricate network with a high level of complexity and interdependence. The large amount of activities and the complexity in structuring them denote that companies are concerned to reduce uncertainties and risks intensifying the planning phase.

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Dulucq, Frédéric; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2009-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

SPIROC (SiPM Integrated Read-Out Chip) Dedicated very front-end electronics for an ILC prototype hadronic calorimeter with SiPM read-out

CERN Document Server

Bouchel, Michel; Fleury, Julien; de La Taille, Christophe; Martin-Chassard, Gisèle; Raux, Ludovic

2007-01-01

The SPIROC chip is a dedicated very front-end electronics for an ILC prototype hadronic calorimeter with Silicon photomultiplier (or MPPC) readout. This ASIC is due to equip a 10,000-channel demonstrator in 2009. SPIROC is an evolution of FLC_SiPM used for the ILC AHCAL physics prototype [1]. SPIROC was submitted in June 2007 and will be tested in September 2007. It embeds cutting edge features that fulfil ILC final detector requirements. It has been realized in 0.35m SiGe technology. It has been developed to match the requirements of large dynamic range, low noise, low consumption, high precision and large number of readout channels needed. SPIROC is an auto-triggered, bi-gain, 36-channel ASIC which allows to measure on each channel the charge from one photoelectron to 2000 and the time with a 100ps accurate TDC. An analogue memory array with a depth of 16 for each channel is used to store the time information and the charge measurement. A 12-bit Wilkinson ADC has been embedded to digitize the analogue memor...

Session summary: Electronics, triggering and data acquisition

International Nuclear Information System (INIS)

Rescia, S.

1991-12-01

The session focused on the requirements for calorimetry at the SSC/LHC. Results on new readout techniques, calibration, radiation hard electronics and semiconductor devices, analog and digital front and electronics, and trigger strategies are presented

Confounding adjustment through front-door blocking in longitudinal studies

Directory of Open Access Journals (Sweden)

Arvid Sjölander

2013-03-01

Full Text Available A common aim of epidemiological research is to estimate the causal effect of a particular exposure on a particular outcome. Towards this end, observed associations are often ‘adjusted’ for potential confounding variables. When the potential confounders are unmeasured, explicit adjustment becomes unfeasible. It has been demonstrated that causal effects can be estimated even in the presence of umeasured confounding, utilizing a method called ‘front-door blocking’. In this paper we generalize this method to longitudinal studies. We demonstrate that the method of front-door blocking poses a number of challenging statistical problems, analogous to the famous problems associ- ated with the method of ‘back-door blocking’.

A −3 dBm RF transmitter front-end for 802.11g application

International Nuclear Information System (INIS)

Zhao Jinxin; Yan Jun; Shi Yin

2013-01-01

A 2.4 GHz, direct-conversion RF transmitter front-end with an up converter and PA driver is fabricated in a 0.13 μm CMOS process for the reliable transmission of 54 Mb/s OFDM signals. The front-end output power is −3 dBm while the corresponding EVM is −27 dB which is necessary for the 802.11g standard of EVM at −25 dB. With the adopted gain control strategy the output power changes from −14.3 to −3.7 dBm with every step 0.8 dB (20%) which covers the gain variation due to working temperature and process. A power detector indicates the output power and delivers a voltage to the baseband to control the output power. (semiconductor integrated circuits)

D-Zero muon readout electronics design

International Nuclear Information System (INIS)

Baldin, B.; Hansen, S.; Los, S.; Matveev, M.; Vaniev, V.

1996-11-01

The readout electronics designed for the D null Muon Upgrade are described. These electronics serve three detector subsystems and one trigger system. The front-ends and readout hardware are synchronized by means of timing signals broadcast from the D null Trigger Framework. The front-end electronics have continuously running digitizers and two levels of buffering resulting in nearly deadtimeless operation. The raw data is corrected and formatted by 16- bit fixed point DSP processors. These processors also perform control of the data buffering. The data transfer from the front-end electronics located on the detector platform is performed by serial links running at 160 Mbit/s. The design and test results of the subsystem readout electronics and system interface are discussed

Novel active signal compression in low-noise analog readout at future X-ray FEL facilities

Science.gov (United States)

Manghisoni, M.; Comotti, D.; Gaioni, L.; Lodola, L.; Ratti, L.; Re, V.; Traversi, G.; Vacchi, C.

2015-04-01

This work presents the design of a low-noise front-end implementing a novel active signal compression technique. This feature can be exploited in the design of analog readout channels for application to the next generation free electron laser (FEL) experiments. The readout architecture includes the low-noise charge sensitive amplifier (CSA) with dynamic signal compression, a time variant shaper used to process the signal at the preamplifier output and a 10-bit successive approximation register (SAR) analog-to-digital converter (ADC). The channel will be operated in such a way to cope with the high frame rate (exceeding 1 MHz) foreseen for future XFEL machines. The choice of a 65 nm CMOS technology has been made in order to include all the building blocks in the target pixel pitch of 100 μm. This work has been carried out in the frame of the PixFEL Project funded by the Istituto Nazionale di Fisica Nucleare (INFN), Italy.

A multichannel front end ASIC for PMT readout in LHAASO WCDA

Science.gov (United States)

Liang, Y.; Zhao, L.; Guo, Y.; Qin, J.; Yang, Y.; Cheng, B.; Liu, S.; An, Q.

2018-01-01

Time and charge measurements over a large dynamic range from 1 Photo Electron (P.E.) to 4000 P.E. are required for the Water Cherenkov Detector Array (WCDA), which is one of the key components in the Large High Altitude Air Shower Observatory (LHAASO). To simplify the circuit structure of the readout electronics, a front end ASIC was designed. Based on the charge-to-time conversion method, the output pulse width of the ASIC corresponds to the input signal charge information while time information of the input signal is picked off through a discriminator, and thus the time and charge information can be digitized simultaneously using this ASIC and a following Time-to-Digital Converter (TDC). To address the challenge of mismatch among the channels observed in the previous prototype version, this work presents approaches for analyzing the problem and optimizing the circuits. A new version of the ASIC was designed and fabricated in the GLOBALFOUNDRIES 0.35 μm CMOS technology, which integrates 6 channels (corresponding to the readout of the 3 PMTs) in each chip. The test results indicate that the mismatch between the channels is significantly reduced to less than 20% using the proposed approach. The time measurement resolution better than 300 ps is achieved, and the charge measurement resolution is better than 10% at 1 P.E., and 1% at 4000 P.E., which meets the application requirements.

Front-End Electron Transfer Dissociation Coupled to a 21 Tesla FT-ICR Mass Spectrometer for Intact Protein Sequence Analysis

Science.gov (United States)

Weisbrod, Chad R.; Kaiser, Nathan K.; Syka, John E. P.; Early, Lee; Mullen, Christopher; Dunyach, Jean-Jacques; English, A. Michelle; Anderson, Lissa C.; Blakney, Greg T.; Shabanowitz, Jeffrey; Hendrickson, Christopher L.; Marshall, Alan G.; Hunt, Donald F.

2017-09-01

High resolution mass spectrometry is a key technology for in-depth protein characterization. High-field Fourier transform ion cyclotron resonance mass spectrometry (FT-ICR MS) enables high-level interrogation of intact proteins in the most detail to date. However, an appropriate complement of fragmentation technologies must be paired with FTMS to provide comprehensive sequence coverage, as well as characterization of sequence variants, and post-translational modifications. Here we describe the integration of front-end electron transfer dissociation (FETD) with a custom-built 21 tesla FT-ICR mass spectrometer, which yields unprecedented sequence coverage for proteins ranging from 2.8 to 29 kDa, without the need for extensive spectral averaging (e.g., 60% sequence coverage for apo-myoglobin with four averaged acquisitions). The system is equipped with a multipole storage device separate from the ETD reaction device, which allows accumulation of multiple ETD fragment ion fills. Consequently, an optimally large product ion population is accumulated prior to transfer to the ICR cell for mass analysis, which improves mass spectral signal-to-noise ratio, dynamic range, and scan rate. We find a linear relationship between protein molecular weight and minimum number of ETD reaction fills to achieve optimum sequence coverage, thereby enabling more efficient use of instrument data acquisition time. Finally, real-time scaling of the number of ETD reactions fills during method-based acquisition is shown, and the implications for LC-MS/MS top-down analysis are discussed. [Figure not available: see fulltext.

R&D Studies of the ATLAS LAr Calorimeter Readout Electronics for super-LHC

CERN Document Server

Chen, H

2010-01-01

The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors, total about 180,000 signals are digitized and processed real-time on detector, to provide energy and time deposited in each detector element at every occurrence of the L1-trigger. A luminosity upgrade (x10) of the LHC will occur ~2017, the current readout electronics will have to be upgraded to sustain the higher radiation levels. A completely innovative readout scheme is being developed. The front-end readout will send out data continuously at each bunch crossing through high speed radiation resistant optical links, the data will be processed real-time with the possibility of implementing trigger algorithms. This article is an overview of the R&D activities and architectural studies the ATLAS LAr collaboration is developing: front-end analog and mixed-signal ASIC design, radiation resistance optical-links in SOS, high-speed back-end processing units based on FPGA architectures and power supply d...

The front-end electronics and slow control of large area SiPM for the SST-1M camera developed for the CTA experiment

Czech Academy of Sciences Publication Activity Database

Aguilar, J.A.; Bilnik, W.; Borkowski, J.; Mandát, Dušan; Pech, Miroslav; Schovánek, Petr

Roč. 830, Sep (2016), s. 219-232 ISSN 0168-9002 R&D Projects: GA MŠk LM2015046; GA MŠk LE13012; GA MŠk LG14019 Institutional support: RVO:68378271 Keywords : CTA * SiPM * G-APD * preamplifier * front-end * slow-control * compensation Subject RIV: BF - Elementary Particles and High Energy Physics Impact factor: 1.362, year: 2016

Readout Electronics for the ATLAS LAr Calorimeter at HL-LHC

CERN Document Server

Chen, H; The ATLAS collaboration

2011-01-01

The ATLAS experiment is one of the two general-purpose detectors designed to study proton-proton collisions (14 TeV in the center of mass) produced at the Large Hadron Collider (LHC) and to explore the full physics potential of the LHC machine at CERN. The ATLAS Liquid Argon (LAr) calorimeters are high precision, high sensitivity and high granularity detectors designed to provide precision measurements of electrons, photons, jets and missing transverse energy. ATLAS (and its LAr Calorimeters) has been operating and collecting p-p collisions at LHC since 2009. The on-detector electronics (front-end) part of the current readout electronics of the calorimeters measures the ionization current signals by means of preamplifiers, shapers and digitizers and then transfers the data to the off-detector electronics (back-end) for further elaboration, via optical links. Only the data selected by the level-1 calorimeter trigger system are transferred, achieving a bandwidth reduction to 1.6 Gbps. The analog trigger sum sig...

A CMOS Low-Power Optical Front-End for 5 Gbps Applications

Science.gov (United States)

Zohoori, Soorena; Dolatshahi, Mehdi

2018-01-01

In this paper, a new low-power optical receiver front-end is proposed in 90 nm CMOS technology for 5 Gb/s AApplications. However, to improve the gain-bandwidth trade-off, the proposed Trans-Impedance Amplifier (TIA) uses an active modified inverter-based topology followed by a common-source amplifier, which uses active inductive peaking technique to enhance the frequency bandwidth in an increased gain level for a reasonable power consumption value. The proposed TIA is analyzed and simulated in HSPICE using 90 nm CMOS technology parameters. Simulation results show a 53.5dBΩ trans-impedance gain, 3.5 GHz frequency bandwidth, 16.8pA/√Hz input referred noise, and 1.28 mW of power consumption at 1V supply voltage. The Optical receiver is completed using three stages of differential limiting amplifiers (LAs), which provide 27 dB voltage gain while consume 3.1 mW of power. Finally, the whole optical receiver front-end consumes only 5.6 mW of power at 1 V supply and amplifies the input signal by 80 dB, while providing 3.7 GHz of frequency bandwidth. Finally, the simulation results indicate that the proposed optical receiver is a proper candidate to be used in a low-power 5 Gbps optical communication system.

OLS Dialog: An open-source front end to the Ontology Lookup Service

Directory of Open Access Journals (Sweden)

Eidhammer Ingvar

2010-01-01

Full Text Available Abstract Background With the growing amount of biomedical data available in public databases it has become increasingly important to annotate data in a consistent way in order to allow easy access to this rich source of information. Annotating the data using controlled vocabulary terms and ontologies makes it much easier to compare and analyze data from different sources. However, finding the correct controlled vocabulary terms can sometimes be a difficult task for the end user annotating these data. Results In order to facilitate the location of the correct term in the correct controlled vocabulary or ontology, the Ontology Lookup Service was created. However, using the Ontology Lookup Service as a web service is not always feasible, especially for researchers without bioinformatics support. We have therefore created a Java front end to the Ontology Lookup Service, called the OLS Dialog, which can be plugged into any application requiring the annotation of data using controlled vocabulary terms, making it possible to find and use controlled vocabulary terms without requiring any additional knowledge about web services or ontology formats. Conclusions As a user-friendly open source front end to the Ontology Lookup Service, the OLS Dialog makes it straightforward to include controlled vocabulary support in third-party tools, which ultimately makes the data even more valuable to the biomedical community.

Measurement of the front-end dead-time of the LHCb muon detector and evaluation of its contribution to the muon detection inefficiency

CERN Document Server

INSPIRE-00357120; Archilli, F.; Auriemma, G.; Baldini, W.; Bencivenni, G.; Bizzeti, A.; Bocci, V.; Bondar, N.; Bonivento, W.; Bochin, B.; Bozzi, C.; Brundu, D.; Cadeddu, S.; Campana, P.; Carboni, G.; Cardini, A.; Carletti, M.; Casu, L.; Chubykin, A.; Ciambrone, P.; Dané, E.; De Simone, P.; Falabella, A.; Felici, G.; Fiore, M.; Fontana, M.; Fresch, P.; Furfaro, E.; Graziani, G.; Kashchuk, A.; Kotriakhova, S.; Lai, A.; Lanfranchi, G.; Loi, A.; Maev, O.; Manca, G.; Martellotti, G.; Neustroev, P.; Oldeman, R.G.C.; Palutan, M.; Passaleva, G.; Penso, G.; Pinci, D.; Polycarpo, E.; Saitta, B.; Santacesaria, R.; Santimaria, M.; Santovetti, E.; Saputi, A.; Sarti, A.; Satriano, C.; Satta, A.; Schmidt, B.; Schneider, T.; Sciascia, B.; Sciubba, A.; Siddi, B.G.; Tellarini, G.; Vacca, C.; Vazquez-Gomez, R.; Vecchi, S.; Veltri, M.; Vorobyev, A.

2016-04-06

A method is described which allows to deduce the dead-time of the front-end electronics of the LHCb muon detector from a series of measurements performed at different luminosities at a bunch-crossing rate of 20 MHz. The measured values of the dead-time range from 70 ns to 100 ns. These results allow to estimate the performance of the muon detector at the future bunch-crossing rate of 40 MHz and at higher luminosity.

The fuzziness of the fuzzy front end : the influence of non-technical factors

NARCIS (Netherlands)

Kiewiet, Derk Jan; van Engelen, Jo; Achterkamp, Marjolein; Chen, J; Xu, QR; Wu, XB

2007-01-01

The Fuzzy Front End (FFE) can be considered the most challenging part of the innovation process where large opportunities are to be found for an organization. Because of the inherently creative and non-routine characteristics of the FFE, only a small number of formal techniques are available to

The multichannel amplifier/discriminator CMOS ASIC for visual light photon counters

International Nuclear Information System (INIS)

Baturitsky, M.A.; Yurenya, Yu.P.Yu.P.

2002-01-01

The 18-channel CMOS custom monolithic amplifier/discriminator ASIC was designed as a front-end electronics chip for Visual Light Photon Counters which convert photons from scintillation fibre/strip detectors to electrical signals. One ASICs channel contains a charge-sensitive preamplifier, a discriminator to mark the arrival time of signals, and a charge divider to provide analog outputs for analog-to-digital conversion being performed by SVX2. The ASIC is proposed as one of the variants for possible future front-end electronics upgrading the D0 Central Fibre Tracker, Central and Forward Pre-Showers (Fermilab, Batavia, USA)

The MicroTCA acquisition and processing back-end for FERMI-Elettra diagnostics

International Nuclear Information System (INIS)

Borga, A.O.; Monte, R. de; Pavlovic, L.; Predonzani, M.; Rossi, F.; Gaio, G.; Ferianis, M.

2012-01-01

During the construction and commissioning of the FERMI-Elettra Free Electron Laser (FEL) facility, tight requirements for diagnostics readout, processing, and control electronics had been specified; together with a complete integration in the main machine control system. Among the diagnostics devices to be controlled, the Bunch Arrival Monitors (BAM) and the Cavity Beam Position Monitors (C-BPM). The back-end platform, based on the MicroTCA (or uTCA) standard, provides a robust environment for accommodating such electronics, including reliable infrastructure features for slow control and monitoring of the electronics inside the crates. Two types of Advanced Mezzanine Cards (AMC) had been conceived, developed and manufactured in order to meet the demanding requisites. The first is a fast (160 MSps) and high-resolution (16 bits) Analog to Digital and Digital to Analog (A-D-A) Convert Board, hosting two A-D and two D-A converters controlled by an FPGA. The onboard logic is also responsible for service and host interface handling. The latter board is an Analog to Digital Only (A-DO) Converter, derived from the A-D-A, with an analog front side stage made of four A-D converters. Timing synthesis and distribution from a MicroTCA Central Hub (MCH) slot can be provided by means of a custom MicroTCA Timing Central Hub (MiTiCH), specifically designed for accurate (sub ps range) timing distribution over uTCA back-planes. The overall systems' architectures, together with the AMCs and MCH concept and functionalities, are described hereafter. A summary of the achievements, for each specific use case, together with our experience in the field with the new architecture, are then summarized. (authors)

Compact Receiver Front Ends for Submillimeter-Wave Applications

Science.gov (United States)

Mehdi, Imran; Chattopadhyay, Goutam; Schlecht, Erich T.; Lin, Robert H.; Sin, Seth; Peralta, Alejandro; Lee, Choonsup; Gill, John J.; Gulkis, Samuel; Thomas, Bertrand C.

2012-01-01

The current generation of submillimeter-wave instruments is relatively mass and power-hungry. The receiver front ends (RFEs) of a submillimeter instrument form the heart of the instrument, and any mass reduction achieved in this subsystem is propagated through the instrument. In the current implementation, the RFE consists of different blocks for the mixer and LO circuits. The motivation for this work is to reduce the mass of the RFE by integrating the mixer and LO circuits in one waveguide block. The mixer and its associated LO chips will all be packaged in a single waveguide package. This will reduce the mass of the RFE and also provide a number of other advantages. By bringing the mixer and LO circuits close together, losses in the waveguide will be reduced. Moreover, the compact nature of the block will allow for better thermal control of the block, which is important in order to reduce gain fluctuations. A single waveguide block with a 600- GHz RFE functionality (based on a subharmonically pumped Schottky diode pair) has been demonstrated. The block is about 3x3x3 cubic centimeters. The block combines the mixer and multiplier chip in a single package. 3D electromagnetic simulations were carried out to design the waveguide circuit around the mixer and multiplier chip. The circuit is optimized to provide maximum output power and maximum bandwidth. An integrated submillimeter front end featuring a 520-600-GHz sub-harmonic mixer and a 260-300-GHz frequency tripler in a single cavity was tested. Both devices used GaAs MMIC membrane planar Schottky diode technology. The sub-harmonic mixer/tripler circuit has been tested using conventional metal-machined blocks. Measurement results on the metal block give best DSB (double sideband) mixer noise temperature of 2,360 K and conversion losses of 7.7 dB at 520 GHz. The LO input power required to pump the integrated tripler/sub-harmonic mixer is between 30 and 50 mW.

The CMS Tracker Readout Front End Driver

CERN Document Server

Foudas, C.; Ballard, D.; Church, I.; Corrin, E.; Coughlan, J.A.; Day, C.P.; Freeman, E.J.; Fulcher, J.; Gannon, W.J.F.; Hall, G.; Halsall, R.N.J.; Iles, G.; Jones, J.; Leaver, J.; Noy, M.; Pearson, M.; Raymond, M.; Reid, I.; Rogers, G.; Salisbury, J.; Taghavi, S.; Tomalin, I.R.; Zorba, O.

2004-01-01

The Front End Driver, FED, is a 9U 400mm VME64x card designed for reading out the Compact Muon Solenoid, CMS, silicon tracker signals transmitted by the APV25 analogue pipeline Application Specific Integrated Circuits. The FED receives the signals via 96 optical fibers at a total input rate of 3.4 GB/sec. The signals are digitized and processed by applying algorithms for pedestal and common mode noise subtraction. Algorithms that search for clusters of hits are used to further reduce the input rate. Only the cluster data along with trigger information of the event are transmitted to the CMS data acquisition system using the S-LINK64 protocol at a maximum rate of 400 MB/sec. All data processing algorithms on the FED are executed in large on-board Field Programmable Gate Arrays. Results on the design, performance, testing and quality control of the FED are presented and discussed.

Systematic Approach to Formulate PSS Development Project Proposals in the Fuzzy Front End

DEFF Research Database (Denmark)

Barquet, Ana Paula B.; Pigosso, Daniela Cristina Antelmi; Rozenfeld, Henrique

2013-01-01

be considered by companies during this definition. The systematization of PSS attributes may help increase the knowledge about different PSS projects that can emerge in the front end, thus leading to the discovery of opportunities that are not apparent in the existing business models and give rise to new ideas...

Front and backside processed thin film electronic devices

Science.gov (United States)

Yuan, Hao-Chih; Wang, Guogong; Eriksson, Mark A.; Evans, Paul G.; Lagally, Max G.; Ma, Zhenqiang

2010-10-12

This invention provides methods for fabricating thin film electronic devices with both front- and backside processing capabilities. Using these methods, high temperature processing steps may be carried out during both frontside and backside processing. The methods are well-suited for fabricating back-gate and double-gate field effect transistors, double-sided bipolar transistors and 3D integrated circuits.

One size does not fit all - understanding the front-end and back-ens of business model innovation

DEFF Research Database (Denmark)

Günzel, Franziska; Holm, Anna B.

2013-01-01

Business model innovation is becoming a central research topic in management. However, a lack of a common understanding of the nature of the business model leads to disregarding its multifaceted structure when analyzing the business model innovation process. This article proposes a more detailed...... understanding of the business model innovation process by drawing on existing knowledge from new product development literature and examining the front-end and the back-end of business model innovation of three leading Danish newspapers. We studied how changes introduced during the development of digital news...... production and delivery have affected key components of these business models, namely value creation, proposition, delivery and capture in the period 2002–2011. Our findings suggest the need to distinguish between front-end and back-end business model innovation processes, and to recognize the importance...

High-performance electronics for time-of-flight PET systems

International Nuclear Information System (INIS)

Choong, W-S; Peng, Q; Vu, C Q; Turko, B T; Moses, W W

2013-01-01

We have designed and built a high-performance readout electronics system for time-of-flight positron emission tomography (TOF PET) cameras. The electronics architecture is based on the electronics for a commercial whole-body PET camera (Siemens/CPS Cardinal electronics), modified to improve the timing performance. The fundamental contributions in the electronics that can limit the timing resolution include the constant fraction discriminator (CFD), which converts the analog electrical signal from the photo-detector to a digital signal whose leading edge is time-correlated with the input signal, and the time-to-digital converter (TDC), which provides a time stamp for the CFD output. Coincident events are identified by digitally comparing the values of the time stamps. In the Cardinal electronics, the front-end processing electronics are performed by an Analog subsection board, which has two application-specific integrated circuits (ASICs), each servicing a PET block detector module. The ASIC has a built-in CFD and TDC. We found that a significant degradation in the timing resolution comes from the ASIC's CFD and TDC. Therefore, we have designed and built an improved Analog subsection board that replaces the ASIC's CFD and TDC with a high-performance CFD (made with discrete components) and TDC (using the CERN high-performance TDC ASIC). The improved Analog subsection board is used in a custom single-ring LSO-based TOF PET camera. The electronics system achieves a timing resolution of 60 ps FWHM. Prototype TOF detector modules are read out with the electronics system and give coincidence timing resolutions of 259 ps FWHM and 156 ps FWHM for detector modules coupled to LSO and LaBr 3 crystals respectively.

Diffusive scattering of electrons by electron holes around injection fronts

Science.gov (United States)

Vasko, I. Y.; Agapitov, O. V.; Mozer, F. S.; Artemyev, A. V.; Krasnoselskikh, V. V.; Bonnell, J. W.

2017-03-01

Van Allen Probes have detected nonlinear electrostatic spikes around injection fronts in the outer radiation belt. These spikes include electron holes (EH), double layers, and more complicated solitary waves. We show that EHs can efficiently scatter electrons due to their substantial transverse electric fields. Although the electron scattering driven by EHs is diffusive, it cannot be evaluated via the standard quasi-linear theory. We derive analytical formulas describing local electron scattering by a single EH and verify them via test particle simulations. We show that the most efficiently scattered are gyroresonant electrons (crossing EH on a time scale comparable to the local electron gyroperiod). We compute bounce-averaged diffusion coefficients and demonstrate their dependence on the EH spatial distribution (latitudinal extent and spatial filling factor) and individual EH parameters (amplitude of electrostatic potential, velocity, and spatial scales). We show that EHs can drive pitch angle scattering of ≲5 keV electrons at rates 10-2-10-4 s-1 and, hence, can contribute to electron losses and conjugated diffuse aurora brightenings. The momentum and pitch angle scattering rates can be comparable, so that EHs can also provide efficient electron heating. The scattering rates driven by EHs at L shells L ˜ 5-8 are comparable to those due to chorus waves and may exceed those due to electron cyclotron harmonics.

Modulated electron bunch with amplitude front tilt in an undulator

International Nuclear Information System (INIS)

Geloni, Gianluca; Kocharyan, Vitali; Saldin, Evgeni

2015-12-01

In a previous paper we discussed the physics of a microbunched electron beam kicked by the dipole field of a corrector magnet by describing the kinematics of coherent undulator radiation after the kick. We demonstrated that the effect of aberration of light supplies the basis for understanding phenomena like the deflection of coherent undulator radiation by a dipole magnet. We illustrated this fact by examining the operation of an XFEL under the steady state assumption, that is a harmonic time dependence. We argued that in this particular case the microbunch front tilt has no objective meaning; in other words, there is no experiment that can discriminate whether an electron beam is endowed with a microbunch front tilt of not. In this paper we extend our considerations to time-dependent phenomena related with a finite electron bunch duration, or SASE mode of operation. We focus our attention on the spatiotemporal distortions of an X-ray pulse. Spatiotemporal coupling arises naturally in coherent undulator radiation behind the kick, because the deflection process involves the introduction of a tilt of the bunch profile. This tilt of the bunch profile leads to radiation pulse front tilt, which is equivalent to angular dispersion of the output radiation. We remark that our exact results can potentially be useful to developers of new generation XFEL codes for cross-checking their results.

Efficient scattering of electrons below few keV by Time Domain Structures around injection fronts

Science.gov (United States)

Vasko, I.; Agapitov, O. V.; Mozer, F.; Artemyev, A.; Krasnoselskikh, V.

2016-12-01

Van Allen Probes observations show an abundance of non-linear large-amplitude electrostatic spikes around injection fronts in the outer radiation belt. These spikes referred to as Time Domain Structures (TDS) include electron holes, double layers and more complicated solitary waves. The electron scattering driven by TDS may not be evaluated via the standard quasi-linear theory, since TDS are in principle non-linear plasma modes. In this paper we analyze the scattering of electrons by three-dimensional TDS (with non-negligible perpendicular electric field) around injection fronts. We derive the analytical formulas describing the local scattering by single TDS and show that the most efficiently scattered electrons are those in the first cyclotron resonance (electrons crossing TDS on a time scale comparable with their gyroperiod). The analytical formulas are verified via the test-particle simulation. We compute the bounce-averaged diffusion coefficients and demonstrate their dependence on the TDS spatial distribution, individual TDS parameters and L shell. We show that TDS are able to provide the pitch-angle scattering of <5 keV electrons at rate 10-2-10-4 s-1 and, thus, can be responsible for driving loss of electrons out of injections fronts on a time scale from few minutes to few hours. TDS can be, thus, responsible for driving diffuse aurora precipitations conjugated to injection fronts. We show that the pitch-angle scattering rates driven by TDS are comparable with those due to chorus waves and exceed those due to electron cyclotron harmonics. For injections fronts with no significant wave activity in the frequency range corresponding to chorus waves, TDS can be even dominant mechanism for losses of below few keV electrons.

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas on the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

Modules and Front-End Electronics Developments for the ATLAS ITk Strips Upgrade

CERN Document Server

Garcia-Argos, Carlos; The ATLAS collaboration

2017-01-01

The ATLAS experiment is currently preparing for an upgrade of the tracking system in the course of the High Luminosity LHC, scheduled for 2024. The existing Inner Detector will be replaced by an all-silicon Inner Tracker (ITk) with a pixel detector surrounded by a strip detector. The ITk strip detector consists of a four layer barrel and a forward region composed of six discs on each side of the barrel. The basic unit of the detector is the silicon-strip module, consisting of a sensor and one or more hybrid circuits that hold the read-out electronics. The geometries of the barrel and end-cap modules take into account the regions that they have to cover. In the central region, the detectors are rectangular with straight strips, whereas in the forward region the modules require wedge shaped sensors with varying strip length and pitch. The current prototyping phase has resulted in the ITk Strip Detector Technical Design Report (TDR), which kicks-off the pre-production readiness phase at the involved institutes. ...

High resolution tomography using analog coding

International Nuclear Information System (INIS)

Brownell, G.L.; Burnham, C.A.; Chesler, D.A.

1985-01-01

As part of a 30-year program in the development of positron instrumentation, the authors have developed a high resolution bismuth germanate (BGO) ring tomography (PCR) employing 360 detectors and 90 photomultiplier tubes for one plane. The detectors are shaped as trapezoid and are 4 mm wide at the front end. When assembled, they form an essentially continuous cylindrical detector. Light from a scintillation in the detector is viewed through a cylindrical light pipe by the photomultiplier tubes. By use of an analog coding scheme, the detector emitting light is identified from the phototube signals. In effect, each phototube can identify four crystals. PCR is designed as a static device and does not use interpolative motion. This results in considerable advantage when performing dynamic studies. PCR is the positron tomography analog of the γ-camera widely used in nuclear medicine

2 MV injector as the Elise front-end and as an experimental facility

International Nuclear Information System (INIS)

Yu, S.S.; Eylon, S.; Henestroza, E.; Peters, C.; Reginato, L.; Tauschwitz, A.; Grote, D.; Deadrick, F.

1996-01-01

We report on progress in the preparation of the 2 MV injector at LBNL as the front end of Elise and as a multipurpose experimental facility for heavy ion fusion beam dynamics studies. Recent advances in the performance and understanding of the injector are described, and some of the ongoing experimental activities are summarized. (orig.)

Graphene-on-semiconductor substrates for analog electronics

Science.gov (United States)

Lagally, Max G.; Cavallo, Francesca; Rojas-Delgado, Richard

2016-04-26

Electrically conductive material structures, analog electronic devices incorporating the structures and methods for making the structures are provided. The structures include a layer of graphene on a semiconductor substrate. The graphene layer and the substrate are separated by an interfacial region that promotes transfer of charge carriers from the surface of the substrate to the graphene.

A configurable electronics system for the ESS-Bilbao beam position monitors

Science.gov (United States)

Muguira, L.; Belver, D.; Etxebarria, V.; Varnasseri, S.; Arredondo, I.; del Campo, M.; Echevarria, P.; Garmendia, N.; Feuchtwanger, J.; Jugo, J.; Portilla, J.

2013-09-01

A versatile and configurable system has been developed in order to monitorize the beam position and to meet all the requirements of the future ESS-Bilbao Linac. At the same time the design has been conceived to be open and configurable so that it could eventually be used in different kinds of accelerators, independent of the charged particle, with minimal change. The design of the Beam Position Monitors (BPMs) system includes a test bench both for button-type pick-ups (PU) and striplines (SL), the electronic units and the control system. The electronic units consist of two main parts. The first part is an Analog Front-End (AFE) unit where the RF signals are filtered, conditioned and converted to base-band. The second part is a Digital Front-End (DFE) unit which is based on an FPGA board where the base-band signals are sampled in order to calculate the beam position, the amplitude and the phase. To manage the system a Multipurpose Controller (MC) developed at ESSB has been used. It includes the FPGA management, the EPICS integration and Archiver Instances. A description of the system and a comparison between the performance of both PU and SL BPM designs measured with this electronics system are fully described and discussed.

A 24 GHz integrated SiGe BiCMOS vital signs detection radar front-end

DEFF Research Database (Denmark)

Jensen, Brian Sveistrup; Johansen, Tom K.; Zhurbenko, Vitaliy

2013-01-01

In this paper a 24 GHz integrated front-end transceiver for vital signs detection (VSD) radars is described. The heterodyne radar transceiver integrates LO buffering and quadrature splitting circuits, up- and down-conversion SSB mixers and two cascaded receiver LNA's. The chip has been manufactured...

Stand-alone front-end system for high- frequency, high-frame-rate coded excitation ultrasonic imaging.

Science.gov (United States)

Park, Jinhyoung; Hu, Changhong; Shung, K Kirk

2011-12-01

A stand-alone front-end system for high-frequency coded excitation imaging was implemented to achieve a wider dynamic range. The system included an arbitrary waveform amplifier, an arbitrary waveform generator, an analog receiver, a motor position interpreter, a motor controller and power supplies. The digitized arbitrary waveforms at a sampling rate of 150 MHz could be programmed and converted to an analog signal. The pulse was subsequently amplified to excite an ultrasound transducer, and the maximum output voltage level achieved was 120 V(pp). The bandwidth of the arbitrary waveform amplifier was from 1 to 70 MHz. The noise figure of the preamplifier was less than 7.7 dB and the bandwidth was 95 MHz. Phantoms and biological tissues were imaged at a frame rate as high as 68 frames per second (fps) to evaluate the performance of the system. During the measurement, 40-MHz lithium niobate (LiNbO(3)) single-element lightweight (<;0.28 g) transducers were utilized. The wire target measure- ment showed that the -6-dB axial resolution of a chirp-coded excitation was 50 μm and lateral resolution was 120 μm. The echo signal-to-noise ratios were found to be 54 and 65 dB for the short burst and coded excitation, respectively. The contrast resolution in a sphere phantom study was estimated to be 24 dB for the chirp-coded excitation and 15 dB for the short burst modes. In an in vivo study, zebrafish and mouse hearts were imaged. Boundaries of the zebrafish heart in the image could be differentiated because of the low-noise operation of the implemented system. In mouse heart images, valves and chambers could be readily visualized with the coded excitation.

Optical Parametric Chirped-Pulse Amplifier as the Front End for the OMEGA EP Laser Chain

International Nuclear Information System (INIS)

Bagnoud, V.; Begishev, I.A.; Guardalben, M.J.; Keegan, J.; Puth, J.; Waxer, L.J.; Zuegel, J.D.

2004-01-01

A 145-mJ optical parametric amplifier has been developed as a front-end source prototype for the OEMGA EP laser chain. The system definition is presented together with experimental results that show 30% conversion efficiency

Cryogenic receiver front-end with sharp skirt characteristics

Energy Technology Data Exchange (ETDEWEB)

Narahashi, S [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Satoh, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Kawai, K [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Koizumi, D [RF Technology Laboratory, Wireless Laboratories, NTT DoCoMo, Inc, Yokosuka, Kanagawa 239-8536 (Japan); Nojima, T [Graduate School of Information Science and Technology, Hokkaido University, Sapporo, Hokkaido 060-0808 (Japan)

2006-05-15

This paper presents an experimental cryogenic receiver front-end (CRFE) with sharp skirt characteristics for mobile base stations. The CRFE comprises a high-temperature superconducting filter, a cryogenic low-noise amplifier, and a highly reliable cryostat that is very compact. The major characteristics of the proposed CRFE measured at 70 K are a centre frequency of 1.95 GHz, passband width of 20 MHz, sharp selectivity of 20 dB/100 kHz, 1.4 dB ripple, 31.3 dB average passband gain, and average passband equivalent noise temperature of 47.9 K. The CRFE weighs 19 kg and occupies 35 l. Random failure of the cryostat is also evaluated by a continuous operation test using four identical ones simultaneously. The cryostat used in the CRFE has a high reliability level of over five years of continuous maintenance-free operation.

Completion of the first TRT End-cap

CERN Multimedia

Catinaccio, A; Rohne, O

On July 1, the first end-cap of the ATLAS Transition Radiation Tracker (TRT) was successfully completed in terms of the integration of the wheels assembled in Russia with their front-end electronics. The two groups of the detector, fully assembled and equipped with front-end electronics, were rotated from their horizontal position during stacking to their nominal vertical position, in which they will be integrated with the corresponding end-cap silicon-strip (SCT) detector towards the end of 2005, before installation into ATLAS in spring 2006. After starting the assembly in the SR building one year ago, the TRT team reached this important milestone, which marks the final realization and validation of the engineering concept developed by the CERN DT1 (ex-TA1) and ATT teams. A TRT end-cap consists of two sets of identical and independent wheels. The first type of wheels (type A, 12 wheels, positioned closest to the primary interaction point) contains 6144 radial straws positioned in eight successive layers s...

Foucault's Pendulum, Analog for an Electron Spin State

Science.gov (United States)

Linck, Rebecca

2012-11-01

The classical Lagrangian that describes the coupled oscillations of Foucault's pendulum presents an interesting analog to an electron's spin state in an external magnetic field. With a simple modification, this classical Lagrangian yields equations of motion that directly map onto the Schrodinger-Pauli Equation. This analog goes well beyond the geometric phase, reproducing a broad range of behavior from Zeeman-like frequency splitting to precession of the spin state. By demonstrating that unmeasured spin states can be fully described in classical terms, this research opens the door to using the tools of classical physics to examine an inherently quantum phenomenon.

Structure and thermal analysis of the water cooling mask at NSRL front end

International Nuclear Information System (INIS)

Zhao Feiyun; Xu Chaoyin; Wang Qiuping; Wang Naxiu

2003-01-01

A water cooling mask is an important part of the front end, usually used for absorbing high power density synchrotron radiation to protect the apparatus from being destroyed by heat load. This paper presents the structure of the water cooling mask and the thermal analysis results of the mask block at NSRL using Program ANSYS5.5

Electronics for a prototype variable field of view PET camera using the PMT-quadrant-sharing detector array

Science.gov (United States)

Li, H.; Wong, Wai-Hoi; Zhang, N.; Wang, J.; Uribe, J.; Baghaei, H.; Yokoyama, S.

1999-06-01

Electronics for a prototype high-resolution PET camera with eight position-sensitive detector modules has been developed. Each module has 16 BGO (Bi/sub 4/Ge/sub 3/O/sub 12/) blocks (each block is composed of 49 crystals). The design goals are component and space reduction. The electronics is composed of five parts: front-end analog processing, digital position decoding, fast timing, coincidence processing and master data acquisition. The front-end analog circuit is a zone-based structure (each zone has 3/spl times/3 PMTs). Nine ADCs digitize integration signals of an active zone identified by eight trigger clusters; each cluster is composed of six photomultiplier tubes (PMTs). A trigger corresponding to a gamma ray is sent to a fast timing board to obtain a time-mark, and the nine digitized signals are passed to the position decoding board, where a real block (four PMTs) can be picked out from the zone for position decoding. Lookup tables are used for energy discrimination and to identify the gamma-hit crystal location. The coincidence board opens a 70-ns initial timing window, followed by two 20-ns true/accidental time-mark lookup table windows. The data output from the coincidence board can be acquired either in sinogram mode or in list mode with a Motorola/IRONICS VME-based system.

The Role of Devices in Staging Front End Innovation

DEFF Research Database (Denmark)

Clausen, Christian; Yoshinaka, Yutaka

2009-01-01

and parcel of the innovative process. The paper is grounded empirically in insight derived from industry practices and compares practices to current literature on the manage-ment of innovation, which portray Front End In-novation as a mere process of search and selection of product ideas. The paper examines...... into realisations. Inputs from different knowledge domains must be grappled with, both in terms of needing to be elucidated as well as synthesized, in the engineering design process. The paper argues that the existing research may be seen as a response to perceived difficulties in dealing with uncertain conditions...... or market and technological opportunities in the innovative process. In this respect, models are not neutral but offer certain framings, contribute translations and act as sensemaking devices....

Measurements of the performance of a beam condition monitor prototype in a 5 GeV electron beam

Energy Technology Data Exchange (ETDEWEB)

Hempel, M., E-mail: maria.hempel@desy.de [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Afanaciev, K. [NCPHEP, Minsk 220040 (Belarus); Burtowy, P.; Dabrowski, A. [CERN, Geneva 1211 (Switzerland); Henschel, H. [DESY, Zeuthen 15738 (Germany); Idzik, M. [AGH University of Science and Technology, Cracow 30-059 (Poland); Karacheban, O. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); Lange, W.; Leonard, J. [DESY, Zeuthen 15738 (Germany); Levy, I. [Tel Aviv University, Tel Aviv 6997801 (Israel); Lohmann, W. [Brandenburg University of Technology Cottbus-Senftenberg, Cottbus 03013 (Germany); DESY, Zeuthen 15738 (Germany); Pollak, B. [Northwestern University, Evanston, IL 60208 (United States); Przyborowski, D. [AGH University of Science and Technology, Cracow 30-059 (Poland); Ryjov, V. [CERN, Geneva 1211 (Switzerland); Schuwalow, S. [DESY, Zeuthen 15738 (Germany); Stickland, D. [Princeton University, Princeton, NJ 08544 (United States); Walsh, R. [DESY, Zeuthen 15738 (Germany); Zagozdzinska, A. [CERN, Geneva 1211 (Switzerland)

2016-08-01

The Fast Beam Conditions Monitor, BCM1F, in the Compact Muon Solenoid, CMS, experiment was operated since 2008 and delivered invaluable information on the machine induced background in the inner part of the CMS detector supporting a safe operation of the inner tracker and high quality data. Due to the shortening of the time between two bunch crossings from 50 ns to 25 ns and higher expected luminosity at the Large Hadron Collider, LHC, in 2015, BCM1F needed an upgrade to higher bandwidth. In addition, BCM1F is used as an on-line luminometer operated independently of CMS. To match these requirements, the number of single crystal diamond sensors was enhanced from 8 to 24. Each sensor is subdivided into two pads, leading to 48 readout channels. Dedicated fast front-end ASICs were developed in 130 nm technology, and the back-end electronics is completely upgraded. An assembled prototype BCM1F detector comprising sensors, a fast front-end ASIC and optical analog readout was studied in a 5 GeV electron beam at the DESY-II accelerator. Results on the performance are given.

Putting the use of intuition for fuzzy front end decision making on the research agenda

NARCIS (Netherlands)

Eling, K.; Langerak, F.

2011-01-01

Decision making literature suggests that intuitive decision making is more appropriate than the established rational decision making approaches to handle the specific information processing needs of the fuzzy front end (FFE) of new product development. However, these earlier studies cannot be

FTU bolometer electronic system upgrade

Energy Technology Data Exchange (ETDEWEB)

Pollastrone, Fabio, E-mail: fabio.pollastrone@enea.it [Associazione EURATOM-ENEA sulla Fusione, Via Enrico Fermi 45, 00044 Frascati, Rome (Italy); Neri, Carlo; Florean, Marco; Ciccone, Giovanni [Associazione EURATOM-ENEA sulla Fusione, Via Enrico Fermi 45, 00044 Frascati, Rome (Italy)

2013-10-15

Highlights: ► Design and realization of a new bolometer electronic system. ► Many improvements over the actual commercial system. ► Architecture based on digital electronic hardware with minimal analog front end. ► Auto off-set correction, real time visualization features and small system size. ► Test results for the electronic system. -- Abstract: The FTU (Frascati Tokamak Upgrade) requires a bolometer diagnostic in order to measure the total plasma radiation. The current diagnostic architecture is based on a full analog multichannel AC bolometer system, which uses a carrier frequency amplifier with a synchronous demodulation. Taking into account the technological upgrades in the field of electronics, it was decided to realize an upgrade for the bolometric electronic system by using a hybrid analog/digital implementation. The new system developed at the ENEA Frascati laboratories has many improvements, and mainly a massive system volume reduction, a good measurement linearity and a simplified use. The new hardware system consists of two subsystems: the Bolometer Digital Control and the Bolometer Analog System. The Bolometer Digital Control can control 16 bolometer bridges through the Bolometer Analog System. The Bolometer Digital Control, based on the FPGA architecture, is connected via Ethernet with a PC; therefore, it can receive commands settings from the PC and send the stream of bolometric measurements in real time to the PC. In order to solve the cross-talk between the bridges and the cables, each of the four bridges in the bolometer head receives a different synthesized excitation frequency. Since the system is fully controlled by a PC GUI (Graphic User Interface), it is very user friendly. Moreover, some useful features have been developed, such as: auto off-set correction, bridge amplitude regulation, software gain setting, real time visualization, frequency excitation selection and noise spectrum analyzer embedded function. In this paper, the

APPLICATION OF OBJECT ORIENTED PROGRAMMING TECHNIQUES IN FRONT END COMPUTERS

International Nuclear Information System (INIS)

SKELLY, J.F.

1997-01-01

The Front End Computer (FEC) environment imposes special demands on software, beyond real time performance and robustness. FEC software must manage a diverse inventory of devices with individualistic timing requirements and hardware interfaces. It must implement network services which export device access to the control system at large, interpreting a uniform network communications protocol into the specific control requirements of the individual devices. Object oriented languages provide programming techniques which neatly address these challenges, and also offer benefits in terms of maintainability and flexibility. Applications are discussed which exhibit the use of inheritance, multiple inheritance and inheritance trees, and polymorphism to address the needs of FEC software

A new design for SLAM front-end based on recursive SOM

Science.gov (United States)

Yang, Xuesi; Xia, Shengping

2015-12-01

Aiming at the graph optimization-based monocular SLAM, a novel design for the front-end in single camera SLAM is proposed, based on the recursive SOM. Pixel intensities are directly used to achieve image registration and motion estimation, which can save time compared with the current appearance-based frameworks, usually including feature extraction and matching. Once a key-frame is identified, a recursive SOM is used to actualize loop-closure detecting, resulting a more precise location. The experiment on a public dataset validates our method on a computer with a quicker and effective result.

Analog integrated circuits design for processing physiological signals.

Science.gov (United States)

Li, Yan; Poon, Carmen C Y; Zhang, Yuan-Ting

2010-01-01

Analog integrated circuits (ICs) designed for processing physiological signals are important building blocks of wearable and implantable medical devices used for health monitoring or restoring lost body functions. Due to the nature of physiological signals and the corresponding application scenarios, the ICs designed for these applications should have low power consumption, low cutoff frequency, and low input-referred noise. In this paper, techniques for designing the analog front-end circuits with these three characteristics will be reviewed, including subthreshold circuits, bulk-driven MOSFETs, floating gate MOSFETs, and log-domain circuits to reduce power consumption; methods for designing fully integrated low cutoff frequency circuits; as well as chopper stabilization (CHS) and other techniques that can be used to achieve a high signal-to-noise performance. Novel applications using these techniques will also be discussed.

An inductorless multi-mode RF front end for GNSS receiver in 55 nm CMOS

Science.gov (United States)

Yanbin, Luo; Chengyan, Ma; Yebing, Gan; Min, Qian; Tianchun, Ye

2015-10-01

An inductorless multi-mode RF front end for a global navigation satellite system (GNSS) receiver is presented. Unlike the traditional topology of a low noise amplifier (LNA), the inductorless current-mode noise-canceling LNA is applied in this design. The high-impedance-input radio frequency amplifier (RFA) further amplifies the GNSS signals and changes the single-end signal path into fully differential. The passive mixer down-converts the signals to the intermediate frequency (IF) band and conveys the signals to the analogue blocks. The local oscillator (LO) buffer divides the output frequency of the voltage controlled oscillator (VCO) and generates 25%-duty-cycle quadrature square waves to drive the mixer. Our measurement results display that the implemented RF front end achieves good overall performance while consuming only 6.7 mA from 1.2 V supply. The input return loss is better than -26 dB and the ultra low noise figure of 1.43 dB leads to high sensitivity of the GNSS receiver. The input 1 dB compression point is -43 dBm at the high gain of 48 dB. The designed circuit is fabricated in 55 nm CMOS technology and the die area, which is much smaller than traditional circuit, is around 220 × 280 μm2.

The nuclear fuel cycle desperately in need of front end alignment

International Nuclear Information System (INIS)

White, G.; Reaves, J.

1983-01-01

The front end of the nuclear fuel cycle which includes uranium supply, conversion of U308 to UF6 and enrichment of UF6, is characterized by excess capacity, excess production, growing inventories and price weakness. Excess capacity resulted from uncritical acceptance by suppliers of overly optimistic utility plans for nuclear growth. Cancellation and deferrals of nuclear plans led to reductions in forecast demand just as the new production capacity was coming on line to meet the high levels of demand forecast earlier. The unique and conservative nature of the utilities as business entities and the unique, sole-end-use character of uranium and its related fuel cycle services suggest that the markets for these materials and services will differ from those of other fuels. An international market is foreseen, marked by continuing boom-bust cycles

The first photon shutter development for APS insertion device beamline front ends

International Nuclear Information System (INIS)

Shu, Deming; Nian, H.L.T.; Wang, Zhibi; Collins, J.T.; Ryding, D.G.; Kuzay, T.M.

1992-01-01

One of the most critical components on the Advanced Photon Source (APS) insertion device (ID) beamline front ends is the first photon shutter. It operates in two modes to fully intercept the high total power and high-heat flux ID photon beam in seconds (normal mode) or in less than 100 ms (emergency fast mode). It is designed to operate in ultra high vacuum (UHV). The design incorporates a multi-channel rectangular bar, bent in a ''hockey stick'' configuration, with two-point suspension. The flanged end is an articulated bellows with rolling hinges. The actuation end is a spring-assisted, pneumatic fail-safe flexural pivot type. The coolant (water) channels incorporate brazed copper foam to enhance the heat transfer, a tube technology particular to the APS. The design development, and material aspects, as well as the extensive thermal and vibrational analyses in support of the design, are presented in this paper

Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

Energy Technology Data Exchange (ETDEWEB)

Sahin, Mehmet Oezguer

2017-04-15

previous searches with the 8 TeV center-of-mass energy in the single lepton final states is extended to m{sub t} = 675 GeV and m{sub χ{sup 0}} = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.

Search for supersymmetric top-quark partners using support vector machines and upgrade of the hadron calorimeter front-end readout control system at CMS

International Nuclear Information System (INIS)

Sahin, Mehmet Oezguer

2017-04-01

the 8 TeV center-of-mass energy in the single lepton final states is extended to m_t = 675 GeV and m_χ_"0 = 225 GeV. The results of the present analysis once again verified the necessity to reach higher center-of-mass energies and luminosities at the LHC. Such an upgrade will increase the radiation exposure of the readout electronics. A reliable operation of the detector electronics under these harsh conditions is absolutely crucial. Therefore, a new front-end readout control system has been integrated to the upgraded electronics infrastructure of the CMS HCAL, which simultaneously sets up and controls all front-end modules. Furthermore, it recovers diagnostic information and responses immediately in case of unexpected events. A firmware for the next-generation Front-End-Control module helping to accomplish these tasks has been developed. Consistency and reliability of the control system is successfully tested in the test-stands and irradiation beam tests.