WorldWideScience

Sample records for advanced stack hardware

  1. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  2. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  3. Implementation of Embedded Ethernet Based on Hardware Protocol Stack in Substation Automation System

    Institute of Scientific and Technical Information of China (English)

    MA Qiang; ZHAO Jianguo; LIU Bingxu

    2008-01-01

    Embedded Ethernet technology has been utilized increasingly widely as the communication mode in the substation automation system (SAS). This paper introduces the current applying situation about embedded Ethernet in SAS First. After analyzing the protocol levels used in SAS based on embedded Ethernet and the differences between the TCP and UDP, UDP/IP is selected as the communication protocol between the station-level and bay-level devices for its real-time characteristic. Then a new kind of implementation of the embedded Ethernet is presented based on hardware protocol stack. The designed scheme can be implemented easily, reduce cost significantly and shorten developing cycle.

  4. Recent Advances in MR Hardware and Software.

    Science.gov (United States)

    Kierans, Andrea; Parikh, Nainesh; Chandarana, Hersh

    2015-05-01

    Tremendous advances have been made in abdominopelvic MR imaging, which continue to improve image quality, and make acquisitions faster and robust. We briefly discuss the role of non-Cartesian acquisition schemes as well as dual parallel radiofrequency (RF) transmit systems in the article to further improve image quality of the abdominal MR imaging. Furthermore, the use of hybrid PET/MR systems has the potential to synergistically combine MR imaging with PET acquisition, and the evolving role of hybrid PET/MR imaging is discussed.

  5. Advances in neuromorphic hardware exploiting emerging nanoscale devices

    CERN Document Server

    2017-01-01

    This book covers all major aspects of cutting-edge research in the field of neuromorphic hardware engineering involving emerging nanoscale devices. Special emphasis is given to leading works in hybrid low-power CMOS-Nanodevice design. The book offers readers a bidirectional (top-down and bottom-up) perspective on designing efficient bio-inspired hardware. At the nanodevice level, it focuses on various flavors of emerging resistive memory (RRAM) technology. At the algorithm level, it addresses optimized implementations of supervised and stochastic learning paradigms such as: spike-time-dependent plasticity (STDP), long-term potentiation (LTP), long-term depression (LTD), extreme learning machines (ELM) and early adoptions of restricted Boltzmann machines (RBM) to name a few. The contributions discuss system-level power/energy/parasitic trade-offs, and complex real-world applications. The book is suited for both advanced researchers and students interested in the field.

  6. Advanced Technology Development: Solid-Liquid Interface Characterization Hardware

    Science.gov (United States)

    2003-01-01

    Characterizing the solid-liquid interface during directional solidification is key to understanding and improving material properties. The goal of this Advanced Technology Development (ATD) has been to develop hardware, which will enable real-time characterization of practical materials, such as aluminum (Al) alloys, to unprecedented levels. Required measurements include furnace and sample temperature gradients, undercooling at the growing interface, interface shape, or morphology, and furnace translation and sample growth rates (related). These and other parameters are correlated with each other and time. A major challenge was to design and develop all of the necessary hardware to measure the characteristics, nearly simultaneously, in a smaller integral furnace compatible with existing X-ray Transmission Microscopes, XTMs. Most of the desired goals have been accomplished through three generations of Seebeck furnace brassboards, several varieties of film thermocouple arrays, heaters, thermal modeling of the furnaces, and data acquisition and control (DAC) software. Presentations and publications have resulted from these activities, and proposals to use this hardware for further materials studies have been submitted as sequels to this last year of the ATD.

  7. Advanced Programming Platform for efficient use of Data Parallel Hardware

    CERN Document Server

    Cabellos, Luis

    2012-01-01

    Graphics processing units (GPU) had evolved from a specialized hardware capable to render high quality graphics in games to a commodity hardware for effective processing blocks of data in a parallel schema. This evolution is particularly interesting for scientific groups, which traditionally use mainly CPU as a work horse, and now can profit of the arrival of GPU hardware to HPC clusters. This new GPU hardware promises a boost in peak performance, but it is not trivial to use. In this article a programming platform designed to promote a direct use of this specialized hardware is presented. This platform includes a visual editor of parallel data flows and it is oriented to the execution in distributed clusters with GPUs. Examples of application in two characteristic problems, Fast Fourier Transform and Image Compression, are also shown.

  8. Fly-by-Light Advanced Systems Hardware (FLASH) program

    Science.gov (United States)

    Bedoya, Carlos A.

    1995-05-01

    hundreds of MHz are available. Applications of fiber optic buses would then result in the reduction of wires and connections because of reduction in the number of buses needed for information transfer due to the fact that a large number of different signals can be sent across one fiber by multiplexing each signal. The Advanced Research Projects Agency (ARPA) Technology Reinvestment Project (TRP) Fly-by-Light Advanced Systems Hardware (FLASH) program addresses the development of Fly-by-Light Technology in order to apply the benefits of fiber optics to military and commercial aircraft.

  9. Advanced Manufacturing Techniques Demonstrated for Fabricating Developmental Hardware

    Science.gov (United States)

    Redding, Chip

    2004-01-01

    NASA Glenn Research Center's Engineering Development Division has been working in support of innovative gas turbine engine systems under development by Glenn's Combustion Branch. These one-of-a-kind components require operation under extreme conditions. High-temperature ceramics were chosen for fabrication was because of the hostile operating environment. During the designing process, it became apparent that traditional machining techniques would not be adequate to produce the small, intricate features for the conceptual design, which was to be produced by stacking over a dozen thin layers with many small features that would then be aligned and bonded together into a one-piece unit. Instead of using traditional machining, we produced computer models in Pro/ENGINEER (Parametric Technology Corporation (PTC), Needham, MA) to the specifications of the research engineer. The computer models were exported in stereolithography standard (STL) format and used to produce full-size rapid prototype polymer models. These semi-opaque plastic models were used for visualization and design verification. The computer models also were exported in International Graphics Exchange Specification (IGES) format and sent to Glenn's Thermal/Fluids Design & Analysis Branch and Applied Structural Mechanics Branch for profiling heat transfer and mechanical strength analysis.

  10. Solid-Liquid Interface Characterization Hardware: Advanced Technology Development (ATD)

    Science.gov (United States)

    Peters, Palmer N.; Sisk, R. C.; Sen, S.; Kaukler, W. F.; Curreri, Peter A.; Wang, F. C.; Rose, M. Franklin (Technical Monitor)

    2000-01-01

    This ATD has the goal of enabling the integration of three separate measurement techniques to characterize the solid-liquid interface of directionally solidified materials in real-time. Arrays of film-based metal thermocouple elements are under development along with compact Seebeck furnaces suitable for interfacing with separately developed X-ray Transmission Microscopes. Results of applying film arrays to furnace profiling are shown, demonstrating their ability to identify a previously undetected hardware flaw in the development of a second-generation compact furnace. Results of real-time furnace profiling also confirmed that the compact furnace design effectively isolates the temperature profiles in two halves of the furnace, a necessary feature. This isolation had only been inferred previously from the characteristics of Seebeck data reported. Results from a 24-thermocouple array successfully monitoring heating and isothermal cooling of a tin sample are shown. The importance of non-intrusion by the arrays, as well as furnace design, on the profiling of temperature gradients is illustrated with example measurements. Further developments underway for effectively combining all three measurements are assessed in terms of improved x-ray transmission, increased magnification, integral arrays with minimum intrusion, integral scales for velocity measurements and other features being incorporated into the third generation Seebeck furnace under construction.

  11. Engineering aspects and hardware verification of a volume producable solid oxide fuel cell stack design for diesel auxiliary power units

    Science.gov (United States)

    Stelter, Michael; Reinert, Andreas; Mai, Björn Erik; Kuznecov, Mihail

    A solid oxide fuel cell (SOFC) stack module is presented that is designed for operation on diesel reformate in an auxiliary power unit (APU). The stack was designed using a top-down approach, based on a specification of an APU system that is installed on board of vehicles. The stack design is planar, modular and scalable with stamped sheet metal interconnectors. It features thin membrane electrode assemblies (MEAs), such as electrolyte supported cells (ESC) and operates at elevated temperatures around 800 °C. The stack has a low pressure drop in both the anode and the cathode to facilitate a simple system layout. An overview of the technical targets met so far is given. A stack power density of 0.2 kW l -1 has been demonstrated in a fully integrated, thermally self-sustaining APU prototype running with diesel and without an external water supply.

  12. RECENT ADVANCES IN HIGH TEMPERATURE ELECTROLYSIS AT IDAHO NATIONAL LABORATORY: STACK TESTS

    Energy Technology Data Exchange (ETDEWEB)

    X, Zhang; J. E. O' Brien; R. C. O' Brien; J. J. Hartvigsen; G. Tao; N. Petigny

    2012-07-01

    High temperature steam electrolysis is a promising technology for efficient sustainable large-scale hydrogen production. Solid oxide electrolysis cells (SOECs) are able to utilize high temperature heat and electric power from advanced high-temperature nuclear reactors or renewable sources to generate carbon-free hydrogen at large scale. However, long term durability of SOECs needs to be improved significantly before commercialization of this technology. A degradation rate of 1%/khr or lower is proposed as a threshold value for commercialization of this technology. Solid oxide electrolysis stack tests have been conducted at Idaho National Laboratory to demonstrate recent improvements in long-term durability of SOECs. Electrolytesupported and electrode-supported SOEC stacks were provided by Ceramatec Inc., Materials and Systems Research Inc. (MSRI), and Saint Gobain Advanced Materials (St. Gobain), respectively for these tests. Long-term durability tests were generally operated for a duration of 1000 hours or more. Stack tests based on technology developed at Ceramatec and MSRI have shown significant improvement in durability in the electrolysis mode. Long-term degradation rates of 3.2%/khr and 4.6%/khr were observed for MSRI and Ceramatec stacks, respectively. One recent Ceramatec stack even showed negative degradation (performance improvement) over 1900 hours of operation. A three-cell short stack provided by St. Gobain, however, showed rapid degradation in the electrolysis mode. Improvements on electrode materials, interconnect coatings, and electrolyteelectrode interface microstructures contribute to better durability of SOEC stacks.

  13. Advances in the development of a hydrogen/oxygen PEM fuel cell stack

    Energy Technology Data Exchange (ETDEWEB)

    Tori, C.; Garaventta, G.; Visintin, A.; Triaca, W.E. [Instituto de Investigaciones Fisicoquimicas Teoricas y Aplicadas (INIFTA), Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC 16, Suc. 4 (1900) La Plata (Argentina); Baleztena, M.; Peralta, C.; Calzada, R.; Jorge, E. [Grupo de Investigacion en Energias Sustentables y Eficiencia Energetica (GIESEE), Departamento de Electrotecnia, Universidad Tecnologica Nacional, Facultad Regional La Plata, Av. 60 esq. 124 (1900) La Plata (Argentina); Barsellini, D. [Instituto de Investigaciones Fisicoquimicas Teoricas y Aplicadas (INIFTA), Facultad de Ciencias Exactas, Universidad Nacional de La Plata, CC 16, Suc. 4 (1900) La Plata (Argentina); Grupo de Investigacion en Energias Sustentables y Eficiencia Energetica (GIESEE), Departamento de Electrotecnia, Universidad Tecnologica Nacional, Facultad Regional La Plata, Av. 60 esq. 124 (1900) La Plata (Argentina)

    2008-07-15

    Recent advances in the design and construction of a hydrogen/oxygen PEM fuel cell stack are presented. A test bench including measurement and control devices to monitor the fuel cell operating parameters was mounted. The influence of the characteristics of the membrane electrode assembly, bipolar plates, etc., on the performance of the fuel cell stack was studied. The behavior of the fuel cell stack with a different number of cells in series was evaluated. In order to identify and minimize the energy losses a critical analysis of the results was done. (author)

  14. AN APPROACH TO DESIGN ADVANCED STANDARD ENCRYPTION ALGORITHM USING HARDWARE / SOFTWARE CO-DESIGN METHODOLOGY

    Directory of Open Access Journals (Sweden)

    MEGHANA A. HASAMNIS

    2012-05-01

    Full Text Available An Advanced Standard Encryption Algorithm (AES is widely used in modern consumer electronicproducts for security. The IEEE 802.15.4 Low-Rate wireless sensor networks also use AES algorithm wherelow power consumption is the priority. To reduce the time taken for encryption of huge data, the algorithm hasto be implemented in hardware. To meet the requirement for low area the algorithm has to be implemented insoftware. Hence, a balance has to be achieved between hardware and software implementations in terms of areaand speed, so as to improve the overall performance of the system. Also with the co-design methodology totalthermal power dissipation is reduced. In this paper, 128 bit AES algorithm is implemented with hardware incombination with software using Altera NIOS II Processor platform. Altera’s Quartus II environment is used fordesign of the system. Cyclone II FPGA is used as a development platform. Software program is written in C language. NIOS II ntegrated Development Environment (IDE is used to integrate hardware and software together. By adopting hardware / software co-design methodology for implementation of AES, results show that a onsiderable improvement in speed can be achieved as compared to software only approach. Further, the significant reduction in area is achieved as compared to hardware only approach. By the approach of co-design an optimized design in terms of speed and area is achieved and also the thermal power dissipation is reduced

  15. Advances in Single-Photon Emission Computed Tomography Hardware and Software.

    Science.gov (United States)

    Piccinelli, Marina; Garcia, Ernest V

    2016-02-01

    Nuclear imaging techniques remain today's most reliable modality for the assessment and quantification of myocardial perfusion. In recent years, the field has experienced tremendous progress both in terms of dedicated cameras for cardiac applications and software techniques for image reconstruction. The most recent advances in single-photon emission computed tomography hardware and software are reviewed, focusing on how these improvements have resulted in an even more powerful diagnostic tool with reduced injected radiation dose and acquisition time.

  16. Building an advanced climate model: Program plan for the CHAMMP (Computer Hardware, Advanced Mathematics, and Model Physics) Climate Modeling Program

    Energy Technology Data Exchange (ETDEWEB)

    1990-12-01

    The issue of global warming and related climatic changes from increasing concentrations of greenhouse gases in the atmosphere has received prominent attention during the past few years. The Computer Hardware, Advanced Mathematics, and Model Physics (CHAMMP) Climate Modeling Program is designed to contribute directly to this rapid improvement. The goal of the CHAMMP Climate Modeling Program is to develop, verify, and apply a new generation of climate models within a coordinated framework that incorporates the best available scientific and numerical approaches to represent physical, biogeochemical, and ecological processes, that fully utilizes the hardware and software capabilities of new computer architectures, that probes the limits of climate predictability, and finally that can be used to address the challenging problem of understanding the greenhouse climate issue through the ability of the models to simulate time-dependent climatic changes over extended times and with regional resolution.

  17. Interim Service ISDN Satellite (ISIS) hardware experiment development for advanced ISDN satellite designs and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Service Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Development for Advanced Satellite Designs describes the development of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into Time Division Multiple Access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the RS-499 interface for satellite uplink. The same ISTA converts in the opposite direction the RS-499 to U-interface data with a simple switch setting.

  18. Interim Service ISDN Satellite (ISIS) hardware experiment design for advanced ISDN satellite design and experiments

    Science.gov (United States)

    Pepin, Gerard R.

    1992-01-01

    The Interim Service Integrated Services Digital Network (ISDN) Satellite (ISIS) Hardware Experiment Design for Advanced Satellite Designs describes the design of the ISDN Satellite Terminal Adapter (ISTA) capable of translating ISDN protocol traffic into time division multiple access (TDMA) signals for use by a communications satellite. The ISTA connects the Type 1 Network Termination (NT1) via the U-interface on the line termination side of the CPE to the V.35 interface for satellite uplink. The same ISTA converts in the opposite direction the V.35 to U-interface data with a simple switch setting.

  19. Software control of the Advanced Technology Solar Telescope enclosure PLC hardware using COTS software

    Science.gov (United States)

    Borrowman, Alastair J.; de Bilbao, Lander; Ariño, Javier; Murga, Gaizka; Goodrich, Bret; Hubbard, John R.; Greer, Alan; Mayer, Chris; Taylor, Philip

    2012-09-01

    As PLCs evolve from simple logic controllers into more capable Programmable Automation Controllers (PACs), observatories are increasingly using such devices to control complex mechanisms1, 2. This paper describes use of COTS software to control such hardware using the Advanced Technology Solar Telescope (ATST) Common Services Framework (CSF). We present the Enclosure Control System (ECS) under development in Spain and the UK. The paper details selection of the commercial PLC communication library PLCIO. Implemented in C and delivered with source code, the library separates the programmer from communication details through a simple API. Capable of communicating with many types of PLCs (including Allen-Bradley and Siemens) the API remains the same irrespective of PLC in use. The ECS is implemented in Java using the observatory's framework that provides common services for software components. We present a design following a connection-based approach where all components access the PLC through a single connection class. The link between Java and PLCIO C library is provided by a thin Java Native Interface (JNI) layer. Also presented is a software simulator of the PLC based upon the PLCIO Virtual PLC. This creates a simulator operating below the library's API and thus requires no change to ECS software. It also provides enhanced software testing capabilities prior to hardware becoming available. Results are presented in the form of communication timing test data, showing that the use of CSF, JNI and PLCIO provide a control system capable of controlling enclosure tracking mechanisms, that would be equally valid for telescope mount control.

  20. Advanced Cardiac Life Support (ACLS) utilizing Man-Tended Capability (MTC) hardware onboard Space Station Freedom

    Science.gov (United States)

    Smith, M.; Barratt, M.; Lloyd, C.

    1992-01-01

    Because of the time and distance involved in returning a patient from space to a definitive medical care facility, the capability for Advanced Cardiac Life Support (ACLS) exists onboard Space Station Freedom. Methods: In order to evaluate the effectiveness of terrestrial ACLS protocols in microgravity, a medical team conducted simulations during parabolic flights onboard the KC-135 aircraft. The hardware planned for use during the MTC phase of the space station was utilized to increase the fidelity of the scenario and to evaluate the prototype equipment. Based on initial KC-135 testing of CPR and ACLS, changes were made to the ventricular fibrillation algorithm in order to accommodate the space environment. Other constraints to delivery of ACLS onboard the space station include crew size, minimum training, crew deconditioning, and limited supplies and equipment. Results: The delivery of ACLS in microgravity is hindered by the environment, but should be adequate. Factors specific to microgravity were identified for inclusion in the protocol including immediate restraint of the patient and early intubation to insure airway. External cardiac compressions of adequate force and frequency were administered using various methods. The more significant limiting factors appear to be crew training, crew size, and limited supplies. Conclusions: Although ACLS is possible in the microgravity environment, future evaluations are necessary to further refine the protocols. Proper patient and medical officer restraint is crucial prior to advanced procedures. Also emphasis should be placed on early intubation for airway management and drug administration. Preliminary results and further testing will be utilized in the design of medical hardware, determination of crew training, and medical operations for space station and beyond.

  1. Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

    2015-08-15

    Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

  2. Hybrid Modeling for Scenario-Based Evaluation of Failure Effects in Advanced Hardware-Software Designs

    Science.gov (United States)

    Malin, Jane T.; Fleming, Land; Throop, David

    2001-01-01

    This paper describes an incremental scenario-based simulation approach to evaluation of intelligent software for control and management of hardware systems. A hybrid continuous/discrete event simulation of the hardware dynamically interacts with the intelligent software in operations scenarios. Embedded anomalous conditions and failures in simulated hardware can lead to emergent software behavior and identification of missing or faulty software or hardware requirements. An approach is described for extending simulation-based automated incremental failure modes and effects analysis, to support concurrent evaluation of intelligent software and the hardware controlled by the software

  3. System-Level Testing of the Advanced Stirling Radioisotope Generator Engineering Hardware

    Science.gov (United States)

    Chan, Jack; Wiser, Jack; Brown, Greg; Florin, Dominic; Oriti, Salvatore M.

    2014-01-01

    To support future NASA deep space missions, a radioisotope power system utilizing Stirling power conversion technology was under development. This development effort was performed under the joint sponsorship of the Department of Energy and NASA, until its termination at the end of 2013 due to budget constraints. The higher conversion efficiency of the Stirling cycle compared with that of the Radioisotope Thermoelectric Generators (RTGs) used in previous missions (Viking, Pioneer, Voyager, Galileo, Ulysses, Cassini, Pluto New Horizons and Mars Science Laboratory) offers the advantage of a four-fold reduction in Pu-238 fuel, thereby extending its limited domestic supply. As part of closeout activities, system-level testing of flight-like Advanced Stirling Convertors (ASCs) with a flight-like ASC Controller Unit (ACU) was performed in February 2014. This hardware is the most representative of the flight design tested to date. The test fully demonstrates the following ACU and system functionality: system startup; ASC control and operation at nominal and worst-case operating conditions; power rectification; DC output power management throughout nominal and out-of-range host voltage levels; ACU fault management, and system command / telemetry via MIL-STD 1553 bus. This testing shows the viability of such a system for future deep space missions and bolsters confidence in the maturity of the flight design.

  4. Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementarymetal-oxide-semiconductor devices

    Institute of Scientific and Technical Information of China (English)

    Li Yongliang; Xu Qiuxia

    2011-01-01

    A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor (CMOS) devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl3-based plasmas are applied to etch the TaN metal gate and find that BC13/Cl2/O2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that C12 almost has no selectivity to Si substrate,BCl3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl3/Cl2/O2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.

  5. Recent advancements in information extraction methodology and hardware for earth resources survey systems

    Science.gov (United States)

    Erickson, J. D.; Thomson, F. J.

    1974-01-01

    The present work discusses some recent developments in preprocessing and extractive processing techniques and hardware and in user applications model development for earth resources survey systems. The Multivariate Interactive Digital Analysis System (MIDAS) is currently being developed, and is an attempt to solve the problem of real time multispectral data processing in an operational system. The main features and design philosophy of this system are described. Examples of wetlands mapping and land resource inventory are presented. A user model developed for predicting the yearly production of mallard ducks from remote sensing and ancillary data is described.

  6. Advanced Photovoltaic Inverter Functionality using 500 kW Power Hardware-in-Loop Complete System Laboratory Testing: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Mather, B. A.; Kromer, M. A.; Casey, L.

    2013-01-01

    With the increasing penetration of distribution connected photovoltaic (PV) systems, more and more PV developers and utilities are interested in easing future PV interconnection concerns by mitigating some of the impacts of PV integration using advanced PV inverter controls and functions. This paper describes the testing of a 500 kW PV inverter using Power Hardware-in-Loop (PHIL) testing techniques. The test setup is described and the results from testing the inverter in advanced functionality modes, not commonly used in currently interconnected PV systems, are presented. PV inverter operation under PHIL evaluation that emulated both the DC PV array connection and the AC distribution level grid connection are shown for constant power factor (PF) and constant reactive power (VAr) control modes. The evaluation of these modes was completed under varying degrees of modeled PV variability.

  7. Hardware Implementation of AES

    Directory of Open Access Journals (Sweden)

    Aakrati Chaturvedi

    2014-01-01

    Full Text Available The Advanced Encryption Standard algorithm can be efficiently programmed in software and implemented in hardware. Field Programmable Gate Array (FPGA devices are considered as efficient and cost effective solution for hardware. This research is in context to efficient hardware implementation of AES algorithm with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. This research is in context to efficient hardware implementation of AES algorithm with 128-192-256 key all in one module with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. The software part has been created, processed and simulated through Xilinx ISE 9.2. A compact design approach has been chosen to implement the algorithm with minimal hardware. As for hardware, Spartan 3AN family device (XC3S700A device is used

  8. 基于硬件协议栈的以太网远程数据传输系统%Remote Ethernet Data Transmission System Based on Hardware Protocol Stack

    Institute of Scientific and Technical Information of China (English)

    张群; 赵亮; 梁若冰

    2013-01-01

    本文介绍了一款单片网络接口芯片W5100,该芯片内部集成了TCP/IP硬件协议栈,支持多种网络协议.给出了基于STM32处理器的硬件电路连接图和软件程序设计.目前,该系统已成功应用在多个建筑能耗监测项目中,运行结果表明该系统通信稳定可靠,能够满足项目对远程数据传输的需求.%The monolithic network interface chip W5100 is introduced in the paper. The chip integrates TCP / IP hardware protocol stack to support a variety of network protocols. The hardware circuit connection diagram and software program design are given based on the STM32 processor. At present, the system has been successfully applied in many building energy consumption monitoring projects. Results show that the system is reliable and stability, and it can meet the needs of the project on remote data transmission.

  9. Parabolic Flight Investigation for Advanced Exercise Concept Hardware Hybrid Ultimate Lifting Kit (HULK)

    Science.gov (United States)

    Weaver, A. S.; Funk, J. H.; Funk, N. W.; Sheehan, C. C.; Humphreys, B. T.; Perusek, G. P.

    2015-01-01

    Long-duration space flight poses many hazards to the health of the crew. Among those hazards is the physiological deconditioning of the musculoskeletal and cardiovascular systems due to prolonged exposure to microgravity. To combat this erosion of physical condition space flight may take on the crew, the Human Research Program (HRP) is charged with developing Advanced Exercise Concepts to maintain astronaut health and fitness during long-term missions, while keeping device mass, power, and volume to a minimum. The goal of this effort is to preserve the physical capability of the crew to perform mission critical tasks in transit and during planetary surface operations. The HULK is a pneumatic-based exercise system, which provides both resistive and aerobic modes to protect against human deconditioning in microgravity. Its design targeted the International Space Station (ISS) Advanced Resistive Exercise Device (ARED) high level performance characteristics and provides up to 600 foot pounds resitive loading with the capability to allow for eccentric to concentric (E:C) ratios of higher than 1:1 through a DC motor assist component. The device's rowing mode allows for high cadence aerobic activity. The HULK parabolic flight campaign, conducted through the NASA Flight Opportunities Program at Ellington Field, resulted in the creation of device specific data sets including low fidelity motion capture, accelerometry and both inline and ground reaction forces. These data provide a critical link in understanding how to vibration isolate the device in both ISS and space transit applications. Secondarily, the study of human exercise and associated body kinematics in microgravity allows for more complete understanding of human to machine interface designs to allow for maximum functionality of the device in microgravity.

  10. Challenges in Atomic-Scale Characterization of High-k Dielectrics and Metal Gate Electrodes for Advanced CMOS Gate Stacks

    Institute of Scientific and Technical Information of China (English)

    Xinhua Zhu; Jianmin Zhu; Aidong Li; Zhiguo Liu; Naiben Ming

    2009-01-01

    The decreasing feature sizes in complementary metal-oxide semiconductor (CMOS) transistor technology will require the replacement of SiO2 with gate dielectrics that have a high dielectric constant (high-k) because as the SiO2 gate thickness is reduced below 1.4 nm, electron tunnelling effects and high leakage currents occur in SiO2, which present serious obstacles to future device reliability.In recent years significant progress has been made on the screening and selection of high-k gate dielectrics, understanding their physical properties, and their integration into CMOS technology.Now the family of hafnium oxide-based materials has emerged as the leading candidate for high-k gate dielectrics due to their excellent physical properties.It is also realized that the high-k oxides must be implemented in conjunction with metal gate electrodes to get sufficient potential for CMOS continue scaling.In the advanced nanoscale Si-based CMOS devices, the composition and thickness of interfacial layers in the gate stacks determine the critical performance of devices.Therefore, detailed atomicscale understandings of the microstructures and interfacial structures built in the advanced CMOS gate stacks,are highly required.In this paper, several high-resolution electron, ion, and photon-based techniques currently used to characterize the high-k gate dielectrics and interfaces at atomic-scale, are reviewed.Particularly, we critically review the research progress on the characterization of interface behavior and structural evolution in the high-k gate dielectrics by high-resolution transmission electron microscopy (HRTEM) and the related techniques based on scanning transmission electron microscopy (STEM), including high-angle annular darkfield (HAADF) imaging (also known as Z-contrast imaging), electron energy-loss spectroscopy (EELS), and energy dispersive X-ray spectroscopy (EDS), due to that HRTEM and STEM have become essential metrology tools for characterizing the dielectric

  11. Advancing interconnect density for spiking neural network hardware implementations using traffic-aware adaptive network-on-chip routers.

    Science.gov (United States)

    Carrillo, Snaider; Harkin, Jim; McDaid, Liam; Pande, Sandeep; Cawley, Seamus; McGinley, Brian; Morgan, Fearghal

    2012-09-01

    The brain is highly efficient in how it processes information and tolerates faults. Arguably, the basic processing units are neurons and synapses that are interconnected in a complex pattern. Computer scientists and engineers aim to harness this efficiency and build artificial neural systems that can emulate the key information processing principles of the brain. However, existing approaches cannot provide the dense interconnect for the billions of neurons and synapses that are required. Recently a reconfigurable and biologically inspired paradigm based on network-on-chip (NoC) and spiking neural networks (SNNs) has been proposed as a new method of realising an efficient, robust computing platform. However, the use of the NoC as an interconnection fabric for large-scale SNNs demands a good trade-off between scalability, throughput, neuron/synapse ratio and power consumption. This paper presents a novel traffic-aware, adaptive NoC router, which forms part of a proposed embedded mixed-signal SNN architecture called EMBRACE (EMulating Biologically-inspiRed ArChitectures in hardwarE). The proposed adaptive NoC router provides the inter-neuron connectivity for EMBRACE, maintaining router communication and avoiding dropped router packets by adapting to router traffic congestion. Results are presented on throughput, power and area performance analysis of the adaptive router using a 90 nm CMOS technology which outperforms existing NoCs in this domain. The adaptive behaviour of the router is also verified on a Stratix II FPGA implementation of a 4 × 2 router array with real-time traffic congestion. The presented results demonstrate the feasibility of using the proposed adaptive NoC router within the EMBRACE architecture to realise large-scale SNNs on embedded hardware.

  12. Algebraic Stacks

    Indian Academy of Sciences (India)

    Tomás L Gómez

    2001-02-01

    This is an expository article on the theory of algebraic stacks. After introducing the general theory, we concentrate in the example of the moduli stack of vector bundles, giving a detailed comparison with the moduli scheme obtained via geometric invariant theory.

  13. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop (Poster)

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.

    2013-02-01

    This poster describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1TM. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  14. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  15. Removal of broken hardware.

    Science.gov (United States)

    Hak, David J; McElvany, Matthew

    2008-02-01

    Despite advances in metallurgy, fatigue failure of hardware is common when a fracture fails to heal. Revision procedures can be difficult, usually requiring removal of intact or broken hardware. Several different methods may need to be attempted to successfully remove intact or broken hardware. Broken intramedullary nail cross-locking screws may be advanced out by impacting with a Steinmann pin. Broken open-section (Küntscher type) intramedullary nails may be removed using a hook. Closed-section cannulated intramedullary nails require additional techniques, such as the use of guidewires or commercially available extraction tools. Removal of broken solid nails requires use of a commercial ratchet grip extractor or a bone window to directly impact the broken segment. Screw extractors, trephines, and extraction bolts are useful for removing stripped or broken screws. Cold-welded screws and plates can complicate removal of locked implants and require the use of carbide drills or high-speed metal cutting tools. Hardware removal can be a time-consuming process, and no single technique is uniformly successful.

  16. An Advanced Hardware Realization of Motion Estimation%一种先进运动估计算法的硬件实现

    Institute of Scientific and Technical Information of China (English)

    江飞; 杨奕; 杨兵

    2012-01-01

    文中介绍了一种先进运动估计处理(MEP)的算法实现。所介绍的MEP用于图像间的运动估计,它计算参考图像在搜索图像区域中不同位移时,两幅图像对应像素点亮度信息的差值之和,并选取最小值作为运动向量。而其硬件实现则采用较先进的处理单元阵列,外挂DSP处理器和外置SRAM存储器,所以算法处理速度可以迅速加快,相反硬件实现的面积也较小。%An advanced hardware realization technique of motion estimation between two images,materially is realized by choosing a better motion vector, which is the smallest one of all the sums between two relative piels belonging to two images separately while computing the motion vector of referencing image in searching image field.So its compute speeds up and realization area is relative small by adopting advanced processor element arrays and external dsp and sram.

  17. A Time-predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation...... of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures....

  18. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.

    Science.gov (United States)

    Rigante, Sara; Scarbolo, Paolo; Wipf, Mathias; Stoop, Ralph L; Bedner, Kristine; Buitrago, Elizabeth; Bazigos, Antonios; Bouvet, Didier; Calame, Michel; Schönenberger, Christian; Ionescu, Adrian M

    2015-05-26

    Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization.

  19. Capping stack: An industry in the making

    Institute of Scientific and Technical Information of China (English)

    Jack Chen; Li Xunke; Xie Wenhui; Kang Yongtian

    2013-01-01

    This paper gives an overview of recent development of the marine well containment system (MWCS)after BP Macondo subsea well blowout occurred on April 20,2010 in the Gulf of Mexico.Capping stack,a hardware utilized to contain blowout well at or near the wellhead is the center piece of MWCS.Accessibility to the dedicated capping stacks is gradually becoming a pre-requirement to obtain the permit for offshore drilling/workover,and the industry for manufacturing,maintenance,transportation and operation of the capping stack is in the making.

  20. A Time-predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspour, Sahar; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less...... precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation...... of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures....

  1. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors.

    Science.gov (United States)

    Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

    2017-02-22

    Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  2. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Directory of Open Access Journals (Sweden)

    Seung-Ho Ok

    2017-02-01

    Full Text Available Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV, three-dimensional (3D stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs.

  3. The Impact of 3D Stacking and Technology Scaling on the Power and Area of Stereo Matching Processors

    Science.gov (United States)

    Ok, Seung-Ho; Lee, Yong-Hwan; Shim, Jae Hoon; Lim, Sung Kyu; Moon, Byungin

    2017-01-01

    Recently, stereo matching processors have been adopted in real-time embedded systems such as intelligent robots and autonomous vehicles, which require minimal hardware resources and low power consumption. Meanwhile, thanks to the through-silicon via (TSV), three-dimensional (3D) stacking technology has emerged as a practical solution to achieving the desired requirements of a high-performance circuit. In this paper, we present the benefits of 3D stacking and process technology scaling on stereo matching processors. We implemented 2-tier 3D-stacked stereo matching processors with GlobalFoundries 130-nm and Nangate 45-nm process design kits and compare them with their two-dimensional (2D) counterparts to identify comprehensive design benefits. In addition, we examine the findings from various analyses to identify the power benefits of 3D-stacked integrated circuit (IC) and device technology advancements. From experiments, we observe that the proposed 3D-stacked ICs, compared to their 2D IC counterparts, obtain 43% area, 13% power, and 14% wire length reductions. In addition, we present a logic partitioning method suitable for a pipeline-based hardware architecture that minimizes the use of TSVs. PMID:28241437

  4. Proceedings of the Twenty-First Water Reactor Safety Information Meeting: Volume 1, Plenary session; Advanced reactor research; advanced control system technology; advanced instrumentation and control hardware; human factors research; probabilistic risk assessment topics; thermal hydraulics; thermal hydraulic research for advanced passive LWRs

    Energy Technology Data Exchange (ETDEWEB)

    Monteleone, S. [Brookhaven National Lab., Upton, NY (United States)] [comp.

    1994-04-01

    This three-volume report contains 90 papers out of the 102 that were presented at the Twenty-First Water Reactor Safety Information Meeting held at the Bethesda Marriott Hotel, Bethesda, Maryland, during the week of October 25--27, 1993. The papers are printed in the order of their presentation in each session and describe progress and results of programs in nuclear safety research conducted in this country and abroad. Foreign participation in the meeting included papers presented by researchers from France, Germany, Japan, Russia, Switzerland, Taiwan, and United Kingdom. The titles of the papers and the names of the authors have been updated and may differ from those that appeared in the final program of the meeting. Individual papers have been cataloged separately. This document, Volume 1 covers the following topics: Advanced Reactor Research; Advanced Instrumentation and Control Hardware; Advanced Control System Technology; Human Factors Research; Probabilistic Risk Assessment Topics; Thermal Hydraulics; and Thermal Hydraulic Research for Advanced Passive Light Water Reactors.

  5. Electrochemical cell stack assembly

    Science.gov (United States)

    Jacobson, Craig P.; Visco, Steven J.; De Jonghe, Lutgard C.

    2010-06-22

    Multiple stacks of tubular electrochemical cells having a dense electrolyte disposed between an anode and a cathode preferably deposited as thin films arranged in parallel on stamped conductive interconnect sheets or ferrules. The stack allows one or more electrochemical cell to malfunction without disabling the entire stack. Stack efficiency is enhanced through simplified gas manifolding, gas recycling, reduced operating temperature and improved heat distribution.

  6. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  7. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

    Directory of Open Access Journals (Sweden)

    Christopher Bailey

    2014-01-01

    Full Text Available Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA. We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

  8. Flight Avionics Hardware Roadmap

    Science.gov (United States)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  9. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III -- Grid Interconnection System Evaluator: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper, presented at the IEEE Green Technologies Conference 2013, describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1 (TM). The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  10. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III - Grid Interconnection System Evaluator

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  11. Dynamic Stability of Cylindrical Shells under Moving Loads by Applying Advanced Controlling Techniques—Part II: Using Piezo-Stack Control

    Directory of Open Access Journals (Sweden)

    Khaled M. Saadeldin Eldalil

    2009-01-01

    Full Text Available The load acting on the actively controlled cylindrical shell under a transient pressure pulse propelling a moving mass (gun case has been experimentally studied. The concept of using piezoelectric stack and stiffener combination is utilized for damping the tube wall radial and circumferential deforming vibrations, in the correct meeting location timing of the moving mass. The experiment was carried out by using the same stiffened shell tube of the experimental 14 mm gun tube facility which is used in part 1. Using single and double stacks is tried at two pressure levels of low-speed modes, which have response frequencies adapted with the used piezoelectric stacks characteristics. The maximum active damping ratio is occurred at high-pressure level. The radial circumferential strains are measured by using high-frequency strain gage system in phase with laser beam detection system similar to which used in part 1. Time resolved strain measurements of the wall response were obtained, and both precursor and transverse hoop strains have been resolved. A complete comparison had been made between the effect of active controlled and stepped structure cases, which indicate a significant attenuation ratio especially at higher operating pressures.

  12. Exascale Hardware Architectures Working Group

    Energy Technology Data Exchange (ETDEWEB)

    Hemmert, S; Ang, J; Chiang, P; Carnes, B; Doerfler, D; Leininger, M; Dosanjh, S; Fields, P; Koch, K; Laros, J; Noe, J; Quinn, T; Torrellas, J; Vetter, J; Wampler, C; White, A

    2011-03-15

    The ASC Exascale Hardware Architecture working group is challenged to provide input on the following areas impacting the future use and usability of potential exascale computer systems: processor, memory, and interconnect architectures, as well as the power and resilience of these systems. Going forward, there are many challenging issues that will need to be addressed. First, power constraints in processor technologies will lead to steady increases in parallelism within a socket. Additionally, all cores may not be fully independent nor fully general purpose. Second, there is a clear trend toward less balanced machines, in terms of compute capability compared to memory and interconnect performance. In order to mitigate the memory issues, memory technologies will introduce 3D stacking, eventually moving on-socket and likely on-die, providing greatly increased bandwidth but unfortunately also likely providing smaller memory capacity per core. Off-socket memory, possibly in the form of non-volatile memory, will create a complex memory hierarchy. Third, communication energy will dominate the energy required to compute, such that interconnect power and bandwidth will have a significant impact. All of the above changes are driven by the need for greatly increased energy efficiency, as current technology will prove unsuitable for exascale, due to unsustainable power requirements of such a system. These changes will have the most significant impact on programming models and algorithms, but they will be felt across all layers of the machine. There is clear need to engage all ASC working groups in planning for how to deal with technological changes of this magnitude. The primary function of the Hardware Architecture Working Group is to facilitate codesign with hardware vendors to ensure future exascale platforms are capable of efficiently supporting the ASC applications, which in turn need to meet the mission needs of the NNSA Stockpile Stewardship Program. This issue is

  13. Hardware Accelerated Power Estimation

    CERN Document Server

    Coburn, Joel; Raghunathan, Anand

    2011-01-01

    In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with "power estimation hardware", map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools.

  14. Hardware protection through obfuscation

    CERN Document Server

    Bhunia, Swarup; Tehranipoor, Mark

    2017-01-01

    This book introduces readers to various threats faced during design and fabrication by today’s integrated circuits (ICs) and systems. The authors discuss key issues, including illegal manufacturing of ICs or “IC Overproduction,” insertion of malicious circuits, referred as “Hardware Trojans”, which cause in-field chip/system malfunction, and reverse engineering and piracy of hardware intellectual property (IP). The authors provide a timely discussion of these threats, along with techniques for IC protection based on hardware obfuscation, which makes reverse-engineering an IC design infeasible for adversaries and untrusted parties with any reasonable amount of resources. This exhaustive study includes a review of the hardware obfuscation methods developed at each level of abstraction (RTL, gate, and layout) for conventional IC manufacturing, new forms of obfuscation for emerging integration strategies (split manufacturing, 2.5D ICs, and 3D ICs), and on-chip infrastructure needed for secure exchange o...

  15. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  16. Characterization of crystallite size, dislocation characteristics and stacking faults in nanostructured mechanically alloyed Cu–Fe system using an advanced X-ray diffraction analysis method

    Energy Technology Data Exchange (ETDEWEB)

    Soleimanian, V., E-mail: vishtasb@iust.ac.ir [Department of Physics, Faculty of Sciences, Shahrekord University, P.O. Box 115, Shahrekord (Iran, Islamic Republic of); Nanotechnology Research Center, Shahrekord University, 8818634141 Shahrekord (Iran, Islamic Republic of); Mojtahedi, M.; Goodarzi, M.; Aboutalebi, M.R. [School of Materials Science and Engineering, Iran University of Science and Technology, Farjam Street, Narmak Tehran 16846-13114 (Iran, Islamic Republic of)

    2014-03-25

    Highlights: • Various microstructural features of mechanically alloyed Cu–Fe are investigated simultaneously. • The crystallite size and size distribution are calculated via refinement of XRD profiles. • Using the eCMWP method, characteristics of dislocations are studied as a function of milling time and composition. • The probability of stacking faults are calculated. -- Abstract: Developments in the synthesis of nanostructured materials have expanded the need for appropriate characterization methods. The aim of this work is to apply new X-ray diffraction analysis methods for simultaneous investigation of various microstructural characteristics. For this purpose, the structure of mechanically alloyed Cu–Fe system with three compositions of 30 wt%, 50% and 70% of iron was studied. By applying the modified Williamson-Hall method, the type of dislocations in the FCC phase is distinguished. Afterwards by modification of previous XRD analysis methods, the proportion of edge/screw dislocations was characterized. Moreover, the outer cut-off radius, the density and energy of dislocations were calculated as a function of the composition and the milling time. On the other hand, using the extended convolutional multiple whole profile fitting procedure, the variations in the crystallite size and size distribution of FCC and BCC phases were studied. Finally, the stacking fault probability was calculated in different milled samples. It is revealed that smaller steady state crystallite size of samples with higher Fe content, is relevant to reduction of the outer cut-off radius of dislocation. On the other hand, the density of dislocations and stacking faults increased continuously up to 96 h of milling.

  17. Deploying OpenStack

    CERN Document Server

    Pepple, Ken

    2011-01-01

    OpenStack was created with the audacious goal of being the ubiquitous software choice for building public and private cloud infrastructures. In just over a year, it's become the most talked-about project in open source. This concise book introduces OpenStack's general design and primary software components in detail, and shows you how to start using it to build cloud infrastructures. If you're a developer, technologist, or system administrator familiar with cloud offerings such as Rackspace Cloud or Amazon Web Services, Deploying OpenStack shows you how to obtain and deploy OpenStack softwar

  18. Hardware Objects for Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan

    2008-01-01

    Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

  19. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  20. Routes to a commercially viable PEM fuel cell stack

    Energy Technology Data Exchange (ETDEWEB)

    Newton, J.; Foster, S.E.; Hodgson, D.; Marrett, A.

    2002-07-01

    This report describes the results of a project to design and build a 10 kW{sub e} proton exchange membrane fuel cell (PEMFC) stack, including membrane electrode assemblies (MEAs), bipolar plates and stack hardware. The aim was to prove the design concept and to demonstrate functionality by operating the stack at >1 kW{sub e}/L and 500 W/kg for 200 hours operation. The project was extended to include the assembly and testing of two additional 1 kW{sub e} PEMFC stacks based on coated metal components. Low equivalent weight perfluorinated ionomer ion exchange membranes were prepared and were found to give a superior electrochemical performance to commercial materials. A technique to etch various stainless steel grades and control processes was successfully developed and optimised. Coatings for stainless steel and titanium were successfully developed and met the required performance criteria. All PEMFC stack components were selected and designed to enable subsequent commercial manufacture.

  1. Mastering OpenStack

    CERN Document Server

    Khedher, Omar

    2015-01-01

    This book is intended for system administrators, cloud engineers, and system architects who want to deploy a cloud based on OpenStack in a mid- to large-sized IT infrastructure. If you have a fundamental understanding of cloud computing and OpenStack and want to expand your knowledge, then this book is an excellent checkpoint to move forward.

  2. OpenStack essentials

    CERN Document Server

    Radez, Dan

    2015-01-01

    If you need to get started with OpenStack or want to learn more, then this book is your perfect companion. If you're comfortable with the Linux command line, you'll gain confidence in using OpenStack.

  3. Stacking with stochastic cooling

    Energy Technology Data Exchange (ETDEWEB)

    Caspers, Fritz E-mail: Fritz.Caspers@cern.ch; Moehl, Dieter

    2004-10-11

    Accumulation of large stacks of antiprotons or ions with the aid of stochastic cooling is more delicate than cooling a constant intensity beam. Basically the difficulty stems from the fact that the optimized gain and the cooling rate are inversely proportional to the number of particles 'seen' by the cooling system. Therefore, to maintain fast stacking, the newly injected batch has to be strongly 'protected' from the Schottky noise of the stack. Vice versa the stack has to be efficiently 'shielded' against the high gain cooling system for the injected beam. In the antiproton accumulators with stacking ratios up to 10{sup 5} the problem is solved by radial separation of the injection and the stack orbits in a region of large dispersion. An array of several tapered cooling systems with a matched gain profile provides a continuous particle flux towards the high-density stack core. Shielding of the different systems from each other is obtained both through the spatial separation and via the revolution frequencies (filters). In the 'old AA', where the antiproton collection and stacking was done in one single ring, the injected beam was further shielded during cooling by means of a movable shutter. The complexity of these systems is very high. For more modest stacking ratios, one might use azimuthal rather than radial separation of stack and injected beam. Schematically half of the circumference would be used to accept and cool new beam and the remainder to house the stack. Fast gating is then required between the high gain cooling of the injected beam and the low gain stack cooling. RF-gymnastics are used to merge the pre-cooled batch with the stack, to re-create free space for the next injection, and to capture the new batch. This scheme is less demanding for the storage ring lattice, but at the expense of some reduction in stacking rate. The talk reviews the 'radial' separation schemes and also gives some

  4. Hardware bitstream sequence recognizer

    OpenAIRE

    Karpin, Oleksandr; Sokil, Volodymyr

    2009-01-01

    This paper describes how to implement in hardware a bistream sequence recognizer using the PSoC Pseudo Random Sequence Generator (PRS) User Module. The PRS can be used in digital communication systems with the serial data interface for automatic preamble detection and extraction, control words selection, etc.

  5. Structural and electrical characteristics of ALD-HfO2/n-Si gate stack with SiON interfacial layer for advanced CMOS technology

    Science.gov (United States)

    Gupta, Richa; Rajput, Renu; Prasher, Rakesh; Vaid, Rakesh

    2016-09-01

    We report the fabrication of an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL) for n-Si/ALD-HfO2 gate stack with reduced leakage current. The XRD, AFM, FTIR, FESEM and EDAX characterizations have been performed for structural and morphological studies. Electrical parameters such as dielectric constant (K), interface trap density (Dit), leakage current density (J), effective oxide charge (Qeff), barrier height (Φbo), ideality factor (ƞ), breakdown-voltage (Vbr) and series resistance (Rs) were extracted through C-V, G-V and I-V measurements. The determined values of K, Dit, J, Qeff, Φbo, ƞ, Vbr and Rs are 14.4, 0.5 × 10 11 eV-1 cm-2, 2.2 × 10-9 A/cm2, 0.3 × 1013 cm-2, 0.42, 2.1, -0.33 and 14.5 MΩ respectively. SiON growth prior to HfO2 deposition has curtailed the problem of high leakage current density and interfacial traps due to sufficient amount of N2 incorporated at the interface.

  6. Stacking with Stochastic Cooling

    CERN Document Server

    Caspers, Friedhelm

    2004-01-01

    Accumulation of large stacks of antiprotons or ions with the aid of stochastic cooling is more delicate than cooling a constant intensity beam. Basically the difficulty stems from the fact that the optimized gain and the cooling rate are inversely proportional to the number of particles seen by the cooling system. Therefore, to maintain fast stacking, the newly injected batch has to be strongly protected from the Schottky noise of the stack. Vice versa the stack has to be efficiently shielded against the high gain cooling system for the injected beam. In the antiproton accumulators with stacking ratios up to 105, the problem is solved by radial separation of the injection and the stack orbits in a region of large dispersion. An array of several tapered cooling systems with a matched gain profile provides a continuous particle flux towards the high-density stack core. Shielding of the different systems from each other is obtained both through the spatial separation and via the revolution frequencies (filters)....

  7. EmuStack: An OpenStack-Based DTN Network Emulation Platform (Extended Version

    Directory of Open Access Journals (Sweden)

    Haifeng Li

    2016-01-01

    Full Text Available With the advancement of computing and network virtualization technology, the networking research community shows great interest in network emulation. Compared with network simulation, network emulation can provide more relevant and comprehensive details. In this paper, EmuStack, a large-scale real-time emulation platform for Delay Tolerant Network (DTN, is proposed. EmuStack aims at empowering network emulation to become as simple as network simulation. Based on OpenStack, distributed synchronous emulation modules are developed to enable EmuStack to implement synchronous and dynamic, precise, and real-time network emulation. Meanwhile, the lightweight approach of using Docker container technology and network namespaces allows EmuStack to support a (up to hundreds of nodes large-scale topology with only several physical nodes. In addition, EmuStack integrates the Linux Traffic Control (TC tools with OpenStack for managing and emulating the virtual link characteristics which include variable bandwidth, delay, loss, jitter, reordering, and duplication. Finally, experiences with our initial implementation suggest the ability to run and debug experimental network protocol in real time. EmuStack environment would bring qualitative change in network research works.

  8. Hardware Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  9. DCSP hardware maintenance system

    Energy Technology Data Exchange (ETDEWEB)

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  10. Fuel Cell Stack Testing and Durability in Support of Ion Tiger UAV

    Science.gov (United States)

    2010-06-02

    This report covers efforts by the Hawaii Natural Energy Institute (HNEI) of the University of Hawaii under the ONR-funded Ion Tiger UAV award that included testing of Ion Tiger fuel cell stacks in HNEI’s Hawaii Fuel Cell Test Facility located in Honolulu, Hawaii. Work was focused on steady-state stack characteristics of Protonex fuel cell stacks under various operating conditions. In addition, Hardware-in-the-Loop testing was performed to characterize dynamic

  11. Exploring coordinated software and hardware support for hardware resource allocation

    OpenAIRE

    Figueiredo Boneti, Carlos Santieri de

    2009-01-01

    Multithreaded processors are now common in the industry as they offer high performance at a low cost. Traditionally, in such processors, the assignation of hardware resources between the multiple threads is done implicitly, by the hardware policies. However, a new class of multithreaded hardware allows the explicit allocation of resources to be controlled or biased by the software. Currently, there is little or no coordination between the allocation of resources done by the hardware and the p...

  12. Metallorganic chemical vapor deposition and atomic layer deposition approaches for the growth of hafnium-based thin films from dialkylamide precursors for advanced CMOS gate stack applications

    Science.gov (United States)

    Consiglio, Steven P.

    the properties of conductive HfN grown via plasma-assisted atomic layer deposition (PA-ALD) using tetrakis(ethylmethylamido)hafnium on a modified commercially available wafer processing tool. Key properties of these materials for use as gate stack replacement materials are addressed and future directions for further characterization and novel material investigations are proposed.

  13. Measuring Structural Parameters Through Stacking Galaxy Images

    Science.gov (United States)

    Li, Yubin; Zheng, Xian Zhong; Gu, Qiu-Sheng; Wang, Yi-Peng; Wen, Zhang Zheng; Guo, Kexin; An, Fang Xia

    2016-12-01

    It remains challenging to detect the low surface brightness structures of faint high-z galaxies, which are key to understanding the structural evolution of galaxies. The technique of image stacking allows us to measure the averaged light profile beneath the detection limit and probe the extended structure of a group of galaxies. We carry out simulations to examine the recovery of the averaged surface brightness profile through stacking model Hubble Space Telescope/Advanced Camera for Surveys images of a set of galaxies as functions of the Sérsic index (n), effective radius (R e) and axis ratio (AR). The Sérsic profile best fitting the radial profile of the stacked image is taken as the recovered profile, in comparison with the intrinsic mean profile of the model galaxies. Our results show that, in general, the structural parameters of the mean profile can be properly determined through stacking, though systematic biases need to be corrected when spreads of R e and AR are counted. We find that the Sérsic index is slightly overestimated and R e is underestimated at {AR}\\lt 0.5 because the stacked image appears to be more compact due to the presence of inclined galaxies; the spread of R e biases the stacked profile to have a higher Sérsic index. We stress that the measurements of structural parameters through stacking should take these biases into account. We estimate the biases in the recovered structural parameters from stacks of galaxies when the samples have distributions of {R}{{e}}, AR and n seen in local galaxies.

  14. Ball Bearing Stacking Automation System

    Directory of Open Access Journals (Sweden)

    Shafeequerrahman S . Ahmed

    2013-01-01

    Full Text Available This document is an effort to introduce the concept of automation in small scale industries and or small workshops that are involved in the manufacturing of small objects such as nuts, bolts and ball bearing in this case. This an electromechanical system which includes certain mechanical parts that involves one base stand on which one vertical metallic frame is mounted and hinged to this vertical stand is an in humanized effort seems inadequate in this era making necessary the use of Electronics, Computer in the manufacturing processes leading to the concept of Automated Manufacturing System (AMS.The ball bearing stack automation is an effort in this regard. In our project we go for stack automation for any object for example a ball bearing, be that is still a manual system there. It will be microcontroller based project control system equipped with microcontroller 89C51 from any manufacturer like Atmel or Philips. This could have been easily implemented if a PLC could be used for manufacturing the staking unit but I adopted the microcontroller based system so that some more modification in the system can be effected at will as to use the same hardware .Although a very small object i.e. ball bearig or small nut and fixture will be tried to be stacked, the system with more precision and more power handling capacity could be built for various requirements of the industry. For increasing more control capacity, we can use another module of this series. When the bearing is ready, it will be sent for packing. This is sensed by an inductive sensor. The output will be proceeds by PLC and microcontroller card which will be driving the assembly in order to put it into pads or flaps. This project will also count the total number of bearings to be packed and will display it on a LCD for real time reference and a provision is made using a higher level language using hyper terminal of the computer

  15. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  16. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  17. Foundations of hardware IP protection

    CERN Document Server

    Torres, Lionel

    2017-01-01

    This book provides a comprehensive and up-to-date guide to the design of security-hardened, hardware intellectual property (IP). Readers will learn how IP can be threatened, as well as protected, by using means such as hardware obfuscation/camouflaging, watermarking, fingerprinting (PUF), functional locking, remote activation, hidden transmission of data, hardware Trojan detection, protection against hardware Trojan, use of secure element, ultra-lightweight cryptography, and digital rights management. This book serves as a single-source reference to design space exploration of hardware security and IP protection. · Provides readers with a comprehensive overview of hardware intellectual property (IP) security, describing threat models and presenting means of protection, from integrated circuit layout to digital rights management of IP; · Enables readers to transpose techniques fundamental to digital rights management (DRM) to the realm of hardware IP security; · Introduce designers to the concept of salutar...

  18. Stacked antiaromatic porphyrins

    Science.gov (United States)

    Nozawa, Ryo; Tanaka, Hiroko; Cha, Won-Young; Hong, Yongseok; Hisaki, Ichiro; Shimizu, Soji; Shin, Ji-Young; Kowalczyk, Tim; Irle, Stephan; Kim, Dongho; Shinokubo, Hiroshi

    2016-11-01

    Aromaticity is a key concept in organic chemistry. Even though this concept has already been theoretically extrapolated to three dimensions, it usually still remains restricted to planar molecules in organic chemistry textbooks. Stacking of antiaromatic π-systems has been proposed to induce three-dimensional aromaticity as a result of strong frontier orbital interactions. However, experimental evidence to support this prediction still remains elusive so far. Here we report that close stacking of antiaromatic porphyrins diminishes their inherent antiaromaticity in the solid state as well as in solution. The antiaromatic stacking furthermore allows a delocalization of the π-electrons, which enhances the two-photon absorption cross-section values of the antiaromatic porphyrins. This feature enables the dynamic switching of the non-linear optical properties by controlling the arrangement of antiaromatic π-systems on the basis of intermolecular orbital interactions.

  19. Stack filter classifiers

    Energy Technology Data Exchange (ETDEWEB)

    Porter, Reid B [Los Alamos National Laboratory; Hush, Don [Los Alamos National Laboratory

    2009-01-01

    Just as linear models generalize the sample mean and weighted average, weighted order statistic models generalize the sample median and weighted median. This analogy can be continued informally to generalized additive modeels in the case of the mean, and Stack Filters in the case of the median. Both of these model classes have been extensively studied for signal and image processing but it is surprising to find that for pattern classification, their treatment has been significantly one sided. Generalized additive models are now a major tool in pattern classification and many different learning algorithms have been developed to fit model parameters to finite data. However Stack Filters remain largely confined to signal and image processing and learning algorithms for classification are yet to be seen. This paper is a step towards Stack Filter Classifiers and it shows that the approach is interesting from both a theoretical and a practical perspective.

  20. ATA50 TELESCOPE: HARDWARE

    Directory of Open Access Journals (Sweden)

    C. Yesilyaprak

    2014-01-01

    Full Text Available El telescopio ATA50 es un nuevo telescopio de 50cm de di ́amet ro con ́optica RC. Fue apoyado por el Proyecto de Investigaci ́on Cient ́ıfica de la Universidad de Atat ̈urk (2 010 y establecido a 2000 m.s.n.m. en Erzurum, Turqu ́ıa en 2012. Las observaciones empezaron en 2013 bajo la direcci ́on y control de el centro de aplicaciones e investi- gaci ́ones astrof ́ısicas de la Universidad de Atat ̈urk (ATA SAM. Las propiedades t ́ecnicas e infraestructuras del Telescopio ATA50 son presentadas y al igual que el trabajo en la automatizaci ́on rob ́otica del telescopio tanto en hardware como software para ser un candidato disponible par a redes de telescopios nacionales e internacionales.

  1. Detailed Electrochemical Characterisation of Large SOFC Stacks

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, R.

    2012-01-01

    application of advanced methods for detailed electrochemical characterisation during operation. An operating stack is subject to steep compositional gradients in the gaseous reactant streams, and significant temperature gradients across each cell and across the stack, which makes it a complex system...... Fuel Cell A/S was characterised in detail using electrochemical impedance spectroscopy. An investigation of the optimal geometrical placement of the current probes and voltage probes was carried out in order to minimise measurement errors caused by stray impedances. Unwanted stray impedances...... are particularly problematic at high frequencies. Stray impedances may be caused by mutual inductance and stray capacitance in the geometrical set-up and do not describe the fuel cell. Three different stack geometries were investigated by electrochemical impedance spectroscopy. Impedance measurements were carried...

  2. Progress of MCFC stack technology at Toshiba

    Energy Technology Data Exchange (ETDEWEB)

    Hori, M.; Hayashi, T.; Shimizu, Y. [Toshiba Corp., Tokyo (Japan)

    1996-12-31

    Toshiba is working on the development of MCFC stack technology; improvement of cell characteristics, and establishment of separator technology. For the cell technology, Toshiba has concentrated on both the restraints of NiO cathode dissolution and electrolyte loss from cells, which are the critical issues to extend cell life in MCFC, and great progress has been made. On the other hand, recognizing that the separator is one of key elements in accomplishing reliable and cost-competitive MCFC stacks, Toshiba has been accelerating the technology establishment and verification of an advanced type separator. A sub-scale stack with such a separator was provided for an electric generating test, and has been operated for more than 10,000 hours. This paper presents several topics obtained through the technical activities in the MCFC field at Toshiba.

  3. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  4. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  5. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  6. Stacked Sequential Learning

    Science.gov (United States)

    2005-07-01

    a constant factor of K + 2. (To see this, note sequential stacking requires training K+2 classifiers: the classifiers f1, . . . , fK used in cross...on the non- sequential learners (ME and VP) but improves per- formance of the sequential learners (CRFs and VPH - MMs) less consistently. This pattern

  7. po_stack_movie

    DEFF Research Database (Denmark)

    2009-01-01

    po_stack® er et reolsystem, hvis enkle elementer giver stor flexibilitet, variation og skulpturel virkning. Elementerne stables og forskydes frit, så reolens rum kan vendes til begge sider, være åbne eller lukkede og farvekombineres ubegrænset. Reolen kan let ombygges, udvides eller opdeles, når ...

  8. Learning SaltStack

    CERN Document Server

    Myers, Colton

    2015-01-01

    If you are a system administrator who manages multiple servers, then you know how difficult it is to keep your infrastructure in line. If you've been searching for an easier way, this book is for you. No prior experience with SaltStack is required.

  9. Transistor Level Circuit Experiments using Evolvable Hardware

    Science.gov (United States)

    Stoica, A.; Zebulum, R. S.; Keymeulen, D.; Ferguson, M. I.; Daud, Taher; Thakoor, A.

    2005-01-01

    The Jet Propulsion Laboratory (JPL) performs research in fault tolerant, long life, and space survivable electronics for the National Aeronautics and Space Administration (NASA). With that focus, JPL has been involved in Evolvable Hardware (EHW) technology research for the past several years. We have advanced the technology not only by simulation and evolution experiments, but also by designing, fabricating, and evolving a variety of transistor-based analog and digital circuits at the chip level. EHW refers to self-configuration of electronic hardware by evolutionary/genetic search mechanisms, thereby maintaining existing functionality in the presence of degradations due to aging, temperature, and radiation. In addition, EHW has the capability to reconfigure itself for new functionality when required for mission changes or encountered opportunities. Evolution experiments are performed using a genetic algorithm running on a DSP as the reconfiguration mechanism and controlling the evolvable hardware mounted on a self-contained circuit board. Rapid reconfiguration allows convergence to circuit solutions in the order of seconds. The paper illustrates hardware evolution results of electronic circuits and their ability to perform under 230 C temperature as well as radiations of up to 250 kRad.

  10. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  11. Life Sciences Division Spaceflight Hardware

    Science.gov (United States)

    Yost, B.

    1999-01-01

    The Ames Research Center (ARC) is responsible for the development, integration, and operation of non-human life sciences payloads in support of NASA's Gravitational Biology and Ecology (GB&E) program. To help stimulate discussion and interest in the development and application of novel technologies for incorporation within non-human life sciences experiment systems, three hardware system models will be displayed with associated graphics/text explanations. First, an Animal Enclosure Model (AEM) will be shown to communicate the nature and types of constraints physiological researchers must deal with during manned space flight experiments using rodent specimens. Second, a model of the Modular Cultivation System (MCS) under development by ESA will be presented to highlight technologies that may benefit cell-based research, including advanced imaging technologies. Finally, subsystems of the Cell Culture Unit (CCU) in development by ARC will also be shown. A discussion will be provided on candidate technology requirements in the areas of specimen environmental control, biotelemetry, telescience and telerobotics, and in situ analytical techniques and imaging. In addition, an overview of the Center for Gravitational Biology Research facilities will be provided.

  12. Open Source Hardware for DIY Environmental Sensing

    Science.gov (United States)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  13. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  14. Hardware Removal in Craniomaxillofacial Trauma

    Science.gov (United States)

    Cahill, Thomas J.; Gandhi, Rikesh; Allori, Alexander C.; Marcus, Jeffrey R.; Powers, David; Erdmann, Detlev; Hollenbeck, Scott T.; Levinson, Howard

    2015-01-01

    Background Craniomaxillofacial (CMF) fractures are typically treated with open reduction and internal fixation. Open reduction and internal fixation can be complicated by hardware exposure or infection. The literature often does not differentiate between these 2 entities; so for this study, we have considered all hardware exposures as hardware infections. Approximately 5% of adults with CMF trauma are thought to develop hardware infections. Management consists of either removing the hardware versus leaving it in situ. The optimal approach has not been investigated. Thus, a systematic review of the literature was undertaken and a resultant evidence-based approach to the treatment and management of CMF hardware infections was devised. Materials and Methods A comprehensive search of journal articles was performed in parallel using MEDLINE, Web of Science, and ScienceDirect electronic databases. Keywords and phrases used were maxillofacial injuries; facial bones; wounds and injuries; fracture fixation, internal; wound infection; and infection. Our search yielded 529 articles. To focus on CMF fractures with hardware infections, the full text of English-language articles was reviewed to identify articles focusing on the evaluation and management of infected hardware in CMF trauma. Each article’s reference list was manually reviewed and citation analysis performed to identify articles missed by the search strategy. There were 259 articles that met the full inclusion criteria and form the basis of this systematic review. The articles were rated based on the level of evidence. There were 81 grade II articles included in the meta-analysis. Result Our meta-analysis revealed that 7503 patients were treated with hardware for CMF fractures in the 81 grade II articles. Hardware infection occurred in 510 (6.8%) of these patients. Of those infections, hardware removal occurred in 264 (51.8%) patients; hardware was left in place in 166 (32.6%) patients; and in 80 (15.6%) cases

  15. OpenStack cloud security

    CERN Document Server

    Locati, Fabio Alessandro

    2015-01-01

    If you are an OpenStack administrator or developer, or wish to build solutions to protect your OpenStack environment, then this book is for you. Experience of Linux administration and familiarity with different OpenStack components is assumed.

  16. Fuel Cell Stacks

    Science.gov (United States)

    1975-04-01

    AD-A009 587 FUEL CELL STACKS Bernard S. Baker Energy Research Corporation Prepared for: Army Mobility Equipment Research and Development Center April... Mobility Equipment Research and Development Center Unclassified For- Belvoir, Virginia 22060 [15. DE.CLASSIFICATION/L.TWNOGRADING SCREOUJLE 16...the majority of effort has been directed at translating technoilogy for small comn- ponent manufacture on a laboratory scale into large size components

  17. Secure coupling of hardware components

    NARCIS (Netherlands)

    Knobbe, J.W.; Hoepman, J.H.; Joosten, H.J.M.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and, f

  18. Assuring Quality and Reliability in Complex Avionics Systems hardware & Software

    Directory of Open Access Journals (Sweden)

    V. Haridas

    1997-01-01

    Full Text Available It is conventional wisdom in defence systems that electronic brains are where much of the present and future weapons system capability is developed. Electronic hardware advances, particularly in microprocessor, allow highly complex and sophisticated software to provide high degree of system autonomy and customisation to mission at hand. Since modern military systems are so much dependent on the proper functioning of electronics, the quality and reliability of electronic hardware and software have a profound impact on defensive capability and readiness. At the hardware level, due to the advances in microelectronics, functional capabilities of today's systems have increased. The advances in the hardware field have an impact on software also. Now a days, it is possible to incorporate more and more system functions through software, rather than going for a pure hardware solution. On the other hand complexities the systems are increasing, working energy levels of the systems are decreasing and the areas of reliability and quality assurance are becoming more and more wide. This paper covers major failure modes in microelectronic devices. The various techniques used to improve component and system reliability are described. The recent trends in expanding the scope of traditional quality assurance techniques are also discussed, considering both hardware and software.

  19. Advanced Simulation Center

    Data.gov (United States)

    Federal Laboratory Consortium — The Advanced Simulation Center consists of 10 individual facilities which provide missile and submunition hardware-in-the-loop simulation capabilities. The following...

  20. Consolidity: Stack-based systems change pathway theory elaborated

    Directory of Open Access Journals (Sweden)

    Hassen Taher Dorrah

    2014-06-01

    , programming and hardware representations of each stack layering type to serve in reducing tremendously any repetitive research efforts in future handling of similar or analogous problems of real life systems. Finally, a new global inter-related stack-based configuration in multi-stacking networks is proposed incorporating conceptually the mutual stack-based changes balancing process through assumed ideal case of lossless bi-directional transfer piping systems.

  1. Stack Caching Using Split Data Caches

    DEFF Research Database (Denmark)

    Nielsen, Carsten; Schoeberl, Martin

    2015-01-01

    In most embedded and general purpose architectures, stack data and non-stack data is cached together, meaning that writing to or loading from the stack may expel non-stack data from the data cache. Manipulation of the stack has a different memory access pattern than that of non-stack data, showin...

  2. Die-stacking architecture

    CERN Document Server

    Xie, Yuan

    2015-01-01

    The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the ""memory wall"" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to design

  3. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  4. Hardware Evolution of Control Electronics

    Science.gov (United States)

    Gwaltney, David; Steincamp, Jim; Corder, Eric; King, Ken; Ferguson, M. I.; Dutton, Ken

    2003-01-01

    The evolution of closed-loop motor speed controllers implemented on the JPL FPTA2 is presented. The response of evolved controller to sinusoidal commands, controller reconfiguration for fault tolerance,and hardware evolution are described.

  5. Alignment of Memory Transfers of a Time-Predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian

    2014-01-01

    different approaches to handle the alignment problem in the stack cache: (1) unaligned transfers, (2) alignment through compiler-generated padding, (3) a novel hardware extension ensuring the alignment of all transfers. Simulation results show that our hardware extension offers a good compromise between...... of complex cache states. Instead, only the occupancy level of the cache has to be determined. The memory transfers generated by the standard stack cache are not generally aligned. These unaligned accesses risk to introduce complexity to the otherwise simple WCET analysis. In this work, we investigate three...

  6. Asymmetric Flexible Supercapacitor Stack

    Directory of Open Access Journals (Sweden)

    Leela Mohana Reddy A

    2008-01-01

    Full Text Available AbstractElectrical double layer supercapacitor is very significant in the field of electrical energy storage which can be the solution for the current revolution in the electronic devices like mobile phones, camera flashes which needs flexible and miniaturized energy storage device with all non-aqueous components. The multiwalled carbon nanotubes (MWNTs have been synthesized by catalytic chemical vapor deposition technique over hydrogen decrepitated Mischmetal (Mm based AB3alloy hydride. The polymer dispersed MWNTs have been obtained by insitu polymerization and the metal oxide/MWNTs were synthesized by sol-gel method. Morphological characterizations of polymer dispersed MWNTs have been carried out using scanning electron microscopy (SEM, transmission electron microscopy (TEM and HRTEM. An assymetric double supercapacitor stack has been fabricated using polymer/MWNTs and metal oxide/MWNTs coated over flexible carbon fabric as electrodes and nafion®membrane as a solid electrolyte. Electrochemical performance of the supercapacitor stack has been investigated using cyclic voltammetry, galvanostatic charge-discharge, and electrochemical impedance spectroscopy.

  7. Stacked Extreme Learning Machines.

    Science.gov (United States)

    Zhou, Hongming; Huang, Guang-Bin; Lin, Zhiping; Wang, Han; Soh, Yeng Chai

    2015-09-01

    Extreme learning machine (ELM) has recently attracted many researchers' interest due to its very fast learning speed, good generalization ability, and ease of implementation. It provides a unified solution that can be used directly to solve regression, binary, and multiclass classification problems. In this paper, we propose a stacked ELMs (S-ELMs) that is specially designed for solving large and complex data problems. The S-ELMs divides a single large ELM network into multiple stacked small ELMs which are serially connected. The S-ELMs can approximate a very large ELM network with small memory requirement. To further improve the testing accuracy on big data problems, the ELM autoencoder can be implemented during each iteration of the S-ELMs algorithm. The simulation results show that the S-ELMs even with random hidden nodes can achieve similar testing accuracy to support vector machine (SVM) while having low memory requirements. With the help of ELM autoencoder, the S-ELMs can achieve much better testing accuracy than SVM and slightly better accuracy than deep belief network (DBN) with much faster training speed.

  8. Scientific Computing Using Consumer Video-Gaming Hardware Devices

    CERN Document Server

    Volkema, Glenn

    2016-01-01

    Commodity video-gaming hardware (consoles, graphics cards, tablets, etc.) performance has been advancing at a rapid pace owing to strong consumer demand and stiff market competition. Gaming hardware devices are currently amongst the most powerful and cost-effective computational technologies available in quantity. In this article, we evaluate a sample of current generation video-gaming hardware devices for scientific computing and compare their performance with specialized supercomputing general purpose graphics processing units (GPGPUs). We use the OpenCL SHOC benchmark suite, which is a measure of the performance of compute hardware on various different scientific application kernels, and also a popular public distributed computing application, Einstein@Home in the field of gravitational physics for the purposes of this evaluation.

  9. Instant BlueStacks

    CERN Document Server

    Judge, Gary

    2013-01-01

    Get to grips with a new technology, understand what it is and what it can do for you, and then get to work with the most important features and tasks. A fast-paced, example-based approach guide for learning BlueStacks.This book is for anyone with a Mac or PC who wants to run Android apps on their computer. Whether you want to play games that are freely available for Android but not your computer, or you want to try apps before you install them on a physical device or use it as a development tool, this book will show you how. No previous experience is needed as this is written in plain English

  10. ATLAS software stack on ARM64

    CERN Document Server

    Smith, Joshua Wyatt; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment explores new hardware and software platforms that, in the future, may be more suited to its data intensive workloads. One such alternative hardware platform is the ARM architecture, which is designed to be extremely power efficient and is found in most smartphones and tablets. CERN openlab recently installed a small cluster of ARM 64-bit evaluation prototype servers. Each server is based on a single-socket ARM 64-bit system on a chip, with 32 Cortex-A57 cores. In total, each server has 128 GB RAM connected with four fast memory channels. This paper reports on the port of the ATLAS software stack onto these new prototype ARM64 servers. This included building the "external" packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adj...

  11. Hardware cleanliness methodology and certification

    Science.gov (United States)

    Harvey, Gale A.; Lash, Thomas J.; Rawls, J. Richard

    1995-01-01

    Inadequacy of mass loss cleanliness criteria for selection of materials for contamination sensitive uses, and processing of flight hardware for contamination sensitive instruments is discussed. Materials selection for flight hardware is usually based on mass loss (ASTM E-595). However, flight hardware cleanliness (MIL 1246A) is a surface cleanliness assessment. It is possible for materials (e.g. Sil-Pad 2000) to pass ASTM E-595 and fail MIL 1246A class A by orders of magnitude. Conversely, it is possible for small amounts of nonconforming material (Huma-Seal conformal coating) to not present significant cleanliness problems to an optical flight instrument. Effective cleaning (precleaning, precision cleaning, and ultra cleaning) and cleanliness verification are essential for contamination sensitive flight instruments. Polish cleaning of hardware, e.g. vacuum baking for vacuum applications, and storage of clean hardware, e.g. laser optics, is discussed. Silicone materials present special concerns for use in space because of the rapid conversion of the outgassed residues to glass by solar ultraviolet radiation and/or atomic oxygen. Non ozone depleting solvent cleaning and institutional support for cleaning and certification are also discussed.

  12. Assessing Elementary Algebra with STACK

    Science.gov (United States)

    Sangwin, Christopher J.

    2007-01-01

    This paper concerns computer aided assessment (CAA) of mathematics in which a computer algebra system (CAS) is used to help assess students' responses to elementary algebra questions. Using a methodology of documentary analysis, we examine what is taught in elementary algebra. The STACK CAA system, http://www.stack.bham.ac.uk/, which uses the CAS…

  13. Stacking disorder in ice I.

    Science.gov (United States)

    Malkin, Tamsin L; Murray, Benjamin J; Salzmann, Christoph G; Molinero, Valeria; Pickering, Steven J; Whale, Thomas F

    2015-01-07

    Traditionally, ice I was considered to exist in two well-defined crystalline forms at ambient pressure: stable hexagonal ice (ice Ih) and metastable cubic ice (ice Ic). However, it is becoming increasingly evident that what has been called cubic ice in the past does not have a structure consistent with the cubic crystal system. Instead, it is a stacking-disordered material containing cubic sequences interlaced with hexagonal sequences, which is termed stacking-disordered ice (ice Isd). In this article, we summarise previous work on ice with stacking disorder including ice that was called cubic ice in the past. We also present new experimental data which shows that ice which crystallises after heterogeneous nucleation in water droplets containing solid inclusions also contains stacking disorder even at freezing temperatures of around -15 °C. This supports the results from molecular simulations, that the structure of ice that crystallises initially from supercooled water is always stacking-disordered and that this metastable ice can transform to the stable hexagonal phase subject to the kinetics of recrystallization. We also show that stacking disorder in ice which forms from water droplets is quantitatively distinct from ice made via other routes. The emerging picture of ice I is that of a very complex material which frequently contains stacking disorder and this stacking disorder can vary in complexity depending on the route of formation and thermal history.

  14. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  15. Foundations of digital signal processing theory, algorithms and hardware design

    CERN Document Server

    Gaydecki, Patrick

    2005-01-01

    An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.

  16. LWH & ACH Helmet Hardware Study

    Science.gov (United States)

    2015-11-30

    testing included dimensional measurements, Rockwell hardness and Vicker’s microhardness measurements, metallographic examination of the grain... microhardness measurements (ASTM E384 Standard Test Method for Microindentation Hardness of Materials) were made on the exterior surfaces of screws...hardware as reference values. However, we do not recommend use of surface Vicker’s microhardness testing for characterizing the nuts, because, as

  17. Combining high productivity with high performance on commodity hardware

    DEFF Research Database (Denmark)

    Skovhede, Kenneth

    The current advances in the natural sciences are increasingly dependent on the available in computer power. At the same time, the increase in computer power is no longer based on faster cores, but on multiple cores and specialized hardware. As most scientific software is written for sequential...... to a particular hardware platform, is a risky investment. To make this problem worse, the scientists that have the required field expertise to write the algorithms are not formally trained programmers. This usually leads to scientists writing buggy, inefficient and hard to maintain programs. Occasionally...

  18. Perspectives in Simulation Hardware and Software Architecture

    Directory of Open Access Journals (Sweden)

    W.O. Grierson

    1985-10-01

    Full Text Available Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more complex models and the demand for greater simulation accuracy. The decision was to design an all-digital system to satisfy these growing requirements (see Gilbert and Howe, (1978. This all-digital approach was called the SYSTEM 10. The SYSTEM 10 has been effective in solving time-critical simulation problems and in replacing the previous approach of utilizing hybrid computers. Recent advances in 100 K emitter coupled logic (ECL now make it possible to support a new generation of equipment that expands modeling capabilities to serve simulation needs. The hardware and software concepts of this system, called the SYSTEM 100, are the subject of this paper.

  19. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  20. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...... language, where each cell is adapted to communicate with one or more other cells in the system, and where the system further comprises a converter program adapted to convert keywords from the DNA language to a binary DNA code; where the self-organisation comprises that the DNA code is transmitted to one...... or more of the cells, and each of the one or more cells is adapted to determine its function in the system; where if a fault occurs in a first cell and the first cell ceases to perform its function, self-maintenance is performed by that the system transmits information to the cells that the first cell has...

  1. The principles of computer hardware

    CERN Document Server

    Clements, Alan

    2000-01-01

    Principles of Computer Hardware, now in its third edition, provides a first course in computer architecture or computer organization for undergraduates. The book covers the core topics of such a course, including Boolean algebra and logic design; number bases and binary arithmetic; the CPU; assembly language; memory systems; and input/output methods and devices. It then goes on to cover the related topics of computer peripherals such as printers; the hardware aspects of the operating system; and data communications, and hence provides a broader overview of the subject. Its readable, tutorial-based approach makes it an accessible introduction to the subject. The book has extensive in-depth coverage of two microprocessors, one of which (the 68000) is widely used in education. All chapters in the new edition have been updated. Major updates include: powerful software simulations of digital systems to accompany the chapters on digital design; a tutorial-based introduction to assembly language, including many exam...

  2. Hardware-Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  3. Hardware Support for Dynamic Languages

    DEFF Research Database (Denmark)

    Schleuniger, Pascal; Karlsson, Sven; Probst, Christian W.

    2011-01-01

    In recent years, dynamic programming languages have enjoyed increasing popularity. For example, JavaScript has become one of the most popular programming languages on the web. As the complexity of web applications is growing, compute-intensive workloads are increasingly handed off to the client s...... on FPGA. We composed a scalable multicore configuration where we study how hardware support for software speculation can be used to increase the performance of dynamic languages....

  4. Hardware Support for Software Debugging

    Science.gov (United States)

    2011-05-01

    Architecture • Concurrency Debugging - ReEnact • Conclusions Cost of Software Defects • Financial Costs • In a study by NIST in 2002 it was found that... ReEnact • Leverages modified Thread-Level Speculation (TLS) hardware • Create partial orderings of threads in a multithreaded program using...logical vector clocks • Using these orderings, ReEnact is able to detect and often repair data race conditions in a multithreaded program • Experiments

  5. IRST system: hardware implementation issues

    Science.gov (United States)

    Deshpande, Suyog D.; Chan, Philip; Ser, W.; Venkateswarlu, Ronda

    1999-07-01

    Generally, Infrared Search and Track systems use linear focal-plane-arrays with time-delay and integration, because of their high sensitivity. However, the readout is a cumbersome process and needs special effort. This paper describes signal processing and hardware (HW) implementation issues related to front-end electronics, non-uniformity compensation, signal formatting, target detection, tracking and display system. This paper proposes parallel pipeline architecture with dedicated HW for computationally intensive algorithms and SW intensive DSP HW for reconfigurable architecture.

  6. Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Marcus Bednara

    2003-05-01

    Full Text Available The implementation of large linear control systems requires a high amount of digital signal processing. Here, we show that reconfigurable hardware allows the design of fast yet flexible control systems. After discussing the basic concepts for the design and implementation of digital controllers for mechatronic systems, a new general and automated design flow starting from a system of differential equations to application-specific hardware implementation is presented. The advances of reconfigurable hardware as a target technology for linear controllers is discussed. In a case study, we compare the new hardware approach for implementing linear controllers with a software implementation.

  7. Nova como sistema operativo embebido para hardware cubano Nova as embedded operating system for cuban hardware

    Directory of Open Access Journals (Sweden)

    José Ernesto Torres Sánchez

    2012-05-01

    Full Text Available Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented.

  8. Nova as embedded operating system for cuban hardware Nova como sistema operativo embebido para hardware cubano

    Directory of Open Access Journals (Sweden)

    Mijail Hurtado Fedorovich

    2012-05-01

    Full Text Available This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented. Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.

  9. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  10. Hardware and software reliability estimation using simulations

    Science.gov (United States)

    Swern, Frederic L.

    1994-01-01

    The simulation technique is used to explore the validation of both hardware and software. It was concluded that simulation is a viable means for validating both hardware and software and associating a reliability number with each. This is useful in determining the overall probability of system failure of an embedded processor unit, and improving both the code and the hardware where necessary to meet reliability requirements. The methodologies were proved using some simple programs, and simple hardware models.

  11. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Wilson, M.S.; Moeller-Holst, S.; Webb, D.M.; Zawodzinski, C.; Gottesfeld, S. [Los Alamos National Lab., NM (United States). Materials Science and Technology Div.

    1998-08-01

    The objective is to develop and demonstrate a 4 kW, hydrogen-fueled polymer electrolyte fuel cell (PEFC) stack, based on non-machined stainless steel hardware and on membrane/electrode assemblies (MEAs) of low catalyst loadings. The stack is designed to operate at ambient pressure on the air-side and can accommodate operation at higher fuel pressures, if so required. This is to be accomplished by working jointly with a fuel cell stack manufacturer, based on a CRADA. The performance goals are 57% energy conversion efficiency hydrogen-to-electricity (DC) at a power density of 0.9 kW/liter for a stack operating at ambient inlet pressures. The cost goal is $600/kW, based on present materials costs.

  12. 16 CFR 1508.6 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the...

  13. 16 CFR 1509.7 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall...

  14. Solid-Liquid Interface Characterization Hardware

    Science.gov (United States)

    Peters, Palmer N.

    2000-01-01

    The objective is to develop enabling technology to characterize the solid-liquid interface during directional solidification to unprecedented levels with real-time measurement hardware. Existing x-ray imaging hardware is combined with compact Seebeck furnaces and thermal profiling hardware, under development, to accomplish the measurements. Furnace thermal profiles are continuously measured in addition to the sample characteristics.

  15. Laser photography system: hardware configuration

    Science.gov (United States)

    Piszczek, Marek; Rutyna, Krzysztof; Kowalski, Marcin; Zyczkowski, Marek

    2012-06-01

    Solution presented in this article is a system using image acquisition time gating method. The time-spatial framing method developed by authors was used to build Laser Photography System (LPS). An active vision system for open space monitoring and terrorist threats detection is being built as an effect of recent work lead in the Institute of Optoelectronics, MUT. The device is destined to prevent and recognize possible terrorist threats in important land and marine areas. The aim of this article is to discuss the properties and hardware configuration of the Laser Photography System.

  16. Feature-Weighted Linear Stacking

    CERN Document Server

    Sill, Joseph; Mackey, Lester; Lin, David

    2009-01-01

    Ensemble methods, such as stacking, are designed to boost predictive accuracy by blending the predictions of multiple machine learning models. Recent work has shown that the use of meta-features, additional inputs describing each example in a dataset, can boost the performance of ensemble methods, but the greatest reported gains have come from nonlinear procedures requiring significant tuning and training time. Here, we present a linear technique, Feature-Weighted Linear Stacking (FWLS), that incorporates meta-features for improved accuracy while retaining the well-known virtues of linear regression regarding speed, stability, and interpretability. FWLS combines model predictions linearly using coefficients that are themselves linear functions of meta-features. This technique was a key facet of the solution of the second place team in the recently concluded Netflix Prize competition. Significant increases in accuracy over standard linear stacking is demonstrated on the Netflix Prize collaborative filtering da...

  17. Glassy carbon based supercapacitor stacks

    Energy Technology Data Exchange (ETDEWEB)

    Baertsch, M.; Braun, A.; Koetz, R.; Haas, O. [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1997-06-01

    Considerable effort is being made to develop electrochemical double layer capacitors (EDLC) that store relatively large quantities of electrical energy and possess at the same time a high power density. Our previous work has shown that glassy carbon is suitable as a material for capacitor electrodes concerning low resistance and high capacity requirements. We present the development of bipolar electrochemical glassy carbon capacitor stacks of up to 3 V. Bipolar stacks are an efficient way to meet the high voltage and high power density requirements for traction applications. Impedance and cyclic voltammogram measurements are reported here and show the frequency response of a 1, 2, and 3 V stack. (author) 3 figs., 1 ref..

  18. High-Performance Message Passing over generic Ethernet Hardware with Open-MX

    OpenAIRE

    Goglin, Brice

    2011-01-01

    International audience; In the last decade, cluster computing has become the most popular high-performance computing architecture. Although numerous technological innovations have been proposed to improve the interconnection of nodes, many clusters still rely on commodity Ethernet hardware to implement message passing within parallel applications. We present Open-MX, an open-source message passing stack over generic Ethernet. It offers the same abilities as the specialized Myrinet Express sta...

  19. Hardware complications in scoliosis surgery

    Energy Technology Data Exchange (ETDEWEB)

    Bagchi, Kaushik; Mohaideen, Ahamed [Department of Orthopaedic Surgery and Musculoskeletal Services, Maimonides Medical Center, Brooklyn, NY (United States); Thomson, Jeffrey D. [Connecticut Children' s Medical Center, Department of Orthopaedics, Hartford, CT (United States); Foley, Christopher L. [Department of Radiology, Connecticut Children' s Medical Center, Hartford, Connecticut (United States)

    2002-07-01

    Background: Scoliosis surgery has undergone a dramatic evolution over the past 20 years with the advent of new surgical techniques and sophisticated instrumentation. Surgeons have realized scoliosis is a complex multiplanar deformity that requires thorough knowledge of spinal anatomy and pathophysiology in order to manage patients afflicted by it. Nonoperative modalities such as bracing and casting still play roles in the treatment of scoliosis; however, it is the operative treatment that has revolutionized the treatment of this deformity that affects millions worldwide. As part of the evolution of scoliosis surgery, newer implants have resulted in improved outcomes with respect to deformity correction, reliability of fixation, and paucity of complications. Each technique and implant has its own set of unique complications, and the surgeon must appreciate these when planning surgery. Materials and methods: Various surgical techniques and types of instrumentation typically used in scoliosis surgery are briefly discussed. Though scoliosis surgery is associated with a wide variety of complications, only those that directly involve the hardware are discussed. The current literature is reviewed and several illustrative cases of patients treated for scoliosis at the Connecticut Children's Medical Center and the Newington Children's Hospital in Connecticut are briefly presented. Conclusion: Spine surgeons and radiologists should be familiar with the different types of instrumentation in the treatment of scoliosis. Furthermore, they should recognize the clinical and roentgenographic signs of hardware failure as part of prompt and effective treatment of such complications. (orig.)

  20. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  1. Simulating Small-Scale Object Stacking Using Stack Stability

    DEFF Research Database (Denmark)

    Kronborg Thomsen, Kasper; Kraus, Martin

    2015-01-01

    This paper presents an extension system to a closed-source, real-time physics engine for improving structured stacking behavior with small-scale objects such as wooden toy bricks. The proposed system was implemented and evaluated. The tests showed that the system is able to simulate several common...

  2. Electronic processing and control system with programmable hardware

    Science.gov (United States)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  3. Pressurized electrolysis stack with thermal expansion capability

    Science.gov (United States)

    Bourgeois, Richard Scott

    2015-07-14

    The present techniques provide systems and methods for mounting an electrolyzer stack in an outer shell so as to allow for differential thermal expansion of the electrolyzer stack and shell. Generally, an electrolyzer stack may be formed from a material with a high coefficient of thermal expansion, while the shell may be formed from a material having a lower coefficient of thermal expansion. The differences between the coefficients of thermal expansion may lead to damage to the electrolyzer stack as the shell may restrain the thermal expansion of the electrolyzer stack. To allow for the differences in thermal expansion, the electrolyzer stack may be mounted within the shell leaving a space between the electrolyzer stack and shell. The space between the electrolyzer stack and the shell may be filled with a non-conductive fluid to further equalize pressure inside and outside of the electrolyzer stack.

  4. Future manufacturing techniques for stacked MCM interconnections

    Science.gov (United States)

    Carson, R. F.; Seigal, P. K.; Craft, D. C.; Lovejoy, M. L.

    1994-06-01

    As multichip modules (MCMs) grow in chip count and complexity, increasingly large numbers of input/output (I/O) channels will be required for connection to other MCMs or printed wiring boards. In applications such as digital signal processing, large increases in processing density (number of operations in a given volume) can be obtained in stacked MCM arrangements. The potential pin counts and required I/O densities in these stacked architectures will push beyond the limits of present interlevel coupling techniques. This problem is particularly acute if easy separation of layers is needed to meet MCM testing and yield requirements. Solutions to this problem include the use of laser-drilled, metal-filled electrical vias in the MCM substrate and also optoelectronic data channels that operate in large arrays. These arrays will emit and detect signals traveling perpendicular to the surface of the MCM. All of these approaches will require packaging and alignment that makes use of advanced MCM manufacturing techniques.

  5. Tuple spaces in hardware for accelerated implicit routing

    Energy Technology Data Exchange (ETDEWEB)

    Baker, Zachary Kent [Los Alamos National Laboratory; Tripp, Justin [Los Alamos National Laboratory

    2010-12-01

    Organizing and optimizing data objects on networks with support for data migration and failing nodes is a complicated problem to handle as systems grow. The goal of this work is to demonstrate that high levels of speedup can be achieved by moving responsibility for finding, fetching, and staging data into an FPGA-based network card. We present a system for implicit routing of data via FPGA-based network cards. In this system, data structures are requested by name, and the network of FPGAs finds the data within the network and relays the structure to the requester. This is acheived through successive examination of hardware hash tables implemented in the FPGA. By avoiding software stacks between nodes, the data is quickly fetched entirely through FPGA-FPGA interaction. The performance of this system is orders of magnitude faster than software implementations due to the improved speed of the hash tables and lowered latency between the network nodes.

  6. Multibeam collimator uses prism stack

    Science.gov (United States)

    Minott, P. O.

    1981-01-01

    Optical instrument creates many divergent light beams for surveying and machine element alignment applications. Angles and refractive indices of stack of prisms are selected to divert incoming laser beam by small increments, different for each prism. Angles of emerging beams thus differ by small, precisely-controlled amounts. Instrument is nearly immune to vibration, changes in gravitational force, temperature variations, and mechanical distortion.

  7. Transgene Stacking in Cotton Improvement

    Institute of Scientific and Technical Information of China (English)

    YANG Ye-hua; WANG Xue-kui; YAO Ming-jing; FAN Yu-peng; GAO Da-yu

    2008-01-01

    @@ To date,more and more transgenic varieties of upland cotton (Gossypium hirsuturn L.) generated with transgenes,which derived from varies of alien species,are playing important role in agricultural production.Stacking of multi-transgenes has a potential for combining all the merits of distinct transgenic lines in a cultivar and possibly makes a significant contribution to cultivar improvement.

  8. Adding large EM stack support

    KAUST Repository

    Holst, Glendon

    2016-12-01

    Serial section electron microscopy (SSEM) image stacks generated using high throughput microscopy techniques are an integral tool for investigating brain connectivity and cell morphology. FIB or 3View scanning electron microscopes easily generate gigabytes of data. In order to produce analyzable 3D dataset from the imaged volumes, efficient and reliable image segmentation is crucial. Classical manual approaches to segmentation are time consuming and labour intensive. Semiautomatic seeded watershed segmentation algorithms, such as those implemented by ilastik image processing software, are a very powerful alternative, substantially speeding up segmentation times. We have used ilastik effectively for small EM stacks – on a laptop, no less; however, ilastik was unable to carve the large EM stacks we needed to segment because its memory requirements grew too large – even for the biggest workstations we had available. For this reason, we refactored the carving module of ilastik to scale it up to large EM stacks on large workstations, and tested its efficiency. We modified the carving module, building on existing blockwise processing functionality to process data in manageable chunks that can fit within RAM (main memory). We review this refactoring work, highlighting the software architecture, design choices, modifications, and issues encountered.

  9. Multilayer Piezoelectric Stack Actuator Characterization

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher M.; Aldrich, Jack B.; Blodget, Chad; Bao, Xioaqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to use actuators for precision positioning to accuracies of the order of fractions of a nanometer. For this purpose, multilayer piezoelectric stacks are being considered as actuators for driving these precision mechanisms. In this study, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and extreme temperatures and voltages. AC signal testing included impedance, capacitance and dielectric loss factor of each actuator as a function of the small-signal driving sinusoidal frequency, and the ambient temperature. DC signal testing includes leakage current and displacement as a function of the applied DC voltage. The applied DC voltage was increased to over eight times the manufacturers' specifications to investigate the correlation between leakage current and breakdown voltage. Resonance characterization as a function of temperature was done over a temperature range of -180C to +200C which generally exceeded the manufacturers' specifications. In order to study the lifetime performance of these stacks, five actuators from one manufacturer were driven by a 60volt, 2 kHz sine-wave for ten billion cycles. The tests were performed using a Lab-View controlled automated data acquisition system that monitored the waveform of the stack electrical current and voltage. The measurements included the displacement, impedance, capacitance and leakage current and the analysis of the experimental results will be presented.

  10. Transgene Stacking in Cotton Improvement

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    To date,more and more transgenic varieties of upland cotton(Gossypium hirsutum L.) generated with transgenes,which derived from varies of alien species,are playing important role in agricultural production.Stacking of multi-transgenes has a potential for combining all the merits of distinct

  11. Mechanically stacked concentrator tandem solar cells

    Science.gov (United States)

    Andreev, V. M.; Rumyantsev, V. D.; Karlina, L. B.; Kazantsev, A. B.; Khvostikov, V. P.; Shvarts, M. Z.; Sorokina, S. V.

    1995-01-01

    Four-terminal mechanically stacked solar cells were developed for advanced space arrays with line-focus reflective concentrators. The top cells are based on AlGaAs/GaAs multilayer heterostructures prepared by low temperature liquid phase epitaxy. The bottom cells are based on heteroepitaxial InP/InGaAs liquid phase epitaxy or on homo-junction GaSb, Zn-diffused structures. The sum of the highest reached efficiencies of the top and bottom cells is 29.4 percent. The best four-terminal tandems have an efficiency of 27 to 28 percent. Solar cells were irradiated with 1 MeV electrons and their performances were determined as a function of fluence up to 10(exp 16) cm(exp-2). It was shown that the radiation resistance of developed tandem cells is similar to the most radiative stable AlGaAs/GaAs cells with a thin p-GaAs photoactive layer.

  12. On-Chip Reconfigurable Hardware Accelerators for Popcount Computations

    Directory of Open Access Journals (Sweden)

    Valery Sklyarov

    2016-01-01

    Full Text Available Popcount computations are widely used in such areas as combinatorial search, data processing, statistical analysis, and bio- and chemical informatics. In many practical problems the size of initial data is very large and increase in throughput is important. The paper suggests two types of hardware accelerators that are (1 designed in FPGAs and (2 implemented in Zynq-7000 all programmable systems-on-chip with partitioning of algorithms that use popcounts between software of ARM Cortex-A9 processing system and advanced programmable logic. A three-level system architecture that includes a general-purpose computer, the problem-specific ARM, and reconfigurable hardware is then proposed. The results of experiments and comparisons with existing benchmarks demonstrate that although throughput of popcount computations is increased in FPGA-based designs interacting with general-purpose computers, communication overheads (in experiments with PCI express are significant and actual advantages can be gained if not only popcount but also other types of relevant computations are implemented in hardware. The comparison of software/hardware designs for Zynq-7000 all programmable systems-on-chip with pure software implementations in the same Zynq-7000 devices demonstrates increase in performance by a factor ranging from 5 to 19 (taking into account all the involved communication overheads between the programmable logic and the processing systems.

  13. Hardware Implementation of Singular Value Decomposition

    Science.gov (United States)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  14. Identification of Hardware Trojans triggering signals

    OpenAIRE

    Dupuis, Sophie; Di Natale, Giorgio; Flottes, Marie-Lise; Rouzeyre, Bruno

    2013-01-01

    International audience; Hardware Trojans are malicious alterations to a circuit. These modifications can be inserted either during the design phase or during the fabrication process. Due to the diversity of Hardware Trojans (HTs), detecting and/or locating them are challenging tasks. Numerous approaches have been proposed to address this problem. Methods based on logic testing consist in trying to activate potential Hardware Trojans in order to detect erroneous outputs during simulation. Howe...

  15. Hardware/software partitioning in Verilog.

    OpenAIRE

    2002-01-01

    We propose in this paper an algebraic approach to hardware/software partitioning in Verilog HDL. We explore a collection of algebraic laws for Verilog programs, from which we design a set of syntax-based algebraic rules to conduct hardware/software partitioning. The co-specification language and the target hardware and software description languages are specific subsets of Verilog, which brings forth our successful verification for the correctness of the partitioning process by algebra of Ver...

  16. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search....

  17. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Madsen, Jan; Knudsen, Peter Voigt

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search...

  18. An Algebraic Hardware/Software Partitioning Algorithm

    Institute of Scientific and Technical Information of China (English)

    秦胜潮; 何积丰; 裘宗燕; 张乃孝

    2002-01-01

    Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components. A critical phase of the co-design process is to decompose a program into hardware and software. This paper proposes an algebraic partitioning algorithm whose correctness is verified in program algebra. The authors introduce a program analysis phase before program partitioning and develop a collection of syntax-based splitting rules. The former provides the information for moving operations from software to hardware and reducing the interaction between components, and the latter supports a compositional approach to program partitioning.

  19. Thermal Hardware for the Thermal Analyst

    Science.gov (United States)

    Steinfeld, David

    2015-01-01

    The presentation will be given at the 26th Annual Thermal Fluids Analysis Workshop (TFAWS 2015) hosted by the Goddard Space Flight Center (GSFC) Thermal Engineering Branch (Code 545). NCTS 21070-1. Most Thermal analysts do not have a good background into the hardware which thermally controls the spacecraft they design. SINDA and Thermal Desktop models are nice, but knowing how this applies to the actual thermal hardware (heaters, thermostats, thermistors, MLI blanketing, optical coatings, etc...) is just as important. The course will delve into the thermal hardware and their application techniques on actual spacecraft. Knowledge of how thermal hardware is used and applied will make a thermal analyst a better engineer.

  20. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  1. Categorical properties of topological and differentiable stacks

    NARCIS (Netherlands)

    Carchedi, D.J.

    2011-01-01

    The focus of this PhD research is on the theory of topological and differentiable stacks. There are two main themes of this research. The first, is the creation of the theory of compactly generated stacks, which solve many categorical shortcomings of the theory of classical topological stacks. In pa

  2. Time-predictable Stack Caching

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar

    complicated and less imprecise. Time-predictable computer architectures provide solutions to this problem. As accesses to the data in caches are one source of timing unpredictability, devising methods for improving the timepredictability of caches are important. Stack data, with statically analyzable......Embedded systems are computing systems for controlling and interacting with physical environments. Embedded systems with special timing constraints where the system needs to meet deadlines are referred to as real-time systems. In hard real-time systems, missing a deadline causes the system to fail...... addresses, provides an opportunity to predict and tighten the WCET of accesses to data in caches. In this thesis, we introduce the time-predictable stack cache design and implementation within a time-predictable processor. We introduce several optimizations to our design for tightening the WCET while...

  3. Manipulation hardware for microgravity research

    Energy Technology Data Exchange (ETDEWEB)

    Herndon, J.N.; Glassell, R.L.; Butler, P.L.; Williams, D.M. (Oak Ridge National Lab., TN (USA)); Rohn, D.A. (National Aeronautics and Space Administration, Cleveland, OH (USA). Lewis Research Center); Miller, J.H. (Sverdrup Technology, Inc., Brook Park, OH (USA))

    1990-01-01

    The establishment of permanent low earth orbit occupation on the Space Station Freedom will present new opportunities for the introduction of productive flexible automation systems into the microgravity environment of space. The need for robust and reliable robotic systems to support experimental activities normally intended by astronauts will assume great importance. Many experimental modules on the space station are expected to require robotic systems for ongoing experimental operations. When implementing these systems, care must be taken not to introduce deleterious effects on the experiments or on the space station itself. It is important to minimize the acceleration effects on the experimental items being handled while also minimizing manipulator base reaction effects on adjacent experiments and on the space station structure. NASA Lewis Research Center has been performing research on these manipulator applications, focusing on improving the basic manipulator hardware, as well as developing improved manipulator control algorithms. By utilizing the modular manipulator concepts developed during the Laboratory Telerobotic Manipulator program, Oak Ridge National Laboratory has developed an experimental testbed system called the Microgravity Manipulator, incorporating two pitch-yaw modular positioners to provide a 4 dof experimental manipulator arm. A key feature in the design for microgravity manipulation research was the use of traction drives for torque transmission in the modular pitch-yaw differentials.

  4. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Zawodzinski, C.; Wilson, M.; Gottesfeld, S. [Los Alamos National Lab., NM (United States)

    1996-10-01

    The fuel cell is the most efficient device for the conversion of hydrogen fuel to electric power. As such, the fuel cell represents a key element in efforts to demonstrate and implement hydrogen fuel utilization for electric power generation. A central objective of a LANL/Industry collaborative effort supported by the Hydrogen Program is to integrate PEM fuel cell and novel stack designs at LANL with stack technology of H-Power Corporation (H-Power) in order to develop a manufacturable, low-cost/high-performance hydrogen/air fuel cell stack for stationary generation of electric power. A LANL/H-Power CRADA includes Tasks ranging from exchange, testing and optimization of membrane-electrode assemblies of large areas, development and demonstration of manufacturable flow field, backing and bipolar plate components, and testing of stacks at the 3-5 cell level and, finally, at the 4-5 kW level. The stack should demonstrate the basic features of manufacturability, overall low cost and high energy conversion efficiency. Plans for future work are to continue the CRADA work along the time line defined in a two-year program, to continue the LANL activities of developing and testing stainless steel hardware for longer term stability including testing in a stack, and to further enhance air cathode performance to achieve higher energy conversion efficiencies as required for stationary power application.

  5. Integrated Hardware and Software for No-Loss Computing

    Science.gov (United States)

    James, Mark

    2007-01-01

    When an algorithm is distributed across multiple threads executing on many distinct processors, a loss of one of those threads or processors can potentially result in the total loss of all the incremental results up to that point. When implementation is massively hardware distributed, then the probability of a hardware failure during the course of a long execution is potentially high. Traditionally, this problem has been addressed by establishing checkpoints where the current state of some or part of the execution is saved. Then in the event of a failure, this state information can be used to recompute that point in the execution and resume the computation from that point. A serious problem arises when one distributes a problem across multiple threads and physical processors is that one increases the likelihood of the algorithm failing due to no fault of the scientist but as a result of hardware faults coupled with operating system problems. With good reason, scientists expect their computing tools to serve them and not the other way around. What is novel here is a unique combination of hardware and software that reformulates an application into monolithic structure that can be monitored in real-time and dynamically reconfigured in the event of a failure. This unique reformulation of hardware and software will provide advanced aeronautical technologies to meet the challenges of next-generation systems in aviation, for civilian and scientific purposes, in our atmosphere and in atmospheres of other worlds. In particular, with respect to NASA s manned flight to Mars, this technology addresses the critical requirements for improving safety and increasing reliability of manned spacecraft.

  6. Solid Oxide Fuel Cell Stack Diagnostics

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Barfod, Rasmus Gottrup

    . An operating stack is subject to compositional gradients in the gaseous reactant streams, and temperature gradients across each cell and across the stack, which complicates detailed analysis. Several experimental stacks from Topsoe Fuel Cell A/S were characterized using Electrochemical Impedance Spectroscopy...... and discussed in the following. Parallel acquisition using electrochemical impedance spectroscopy can be used to detect possible minor differences in the supply of gas to the individual cells, which is important when going to high fuel utilizations. The fuel flow distribution was determined and provides...... carried out on an experimental 14-cell SOFC stack at varying frequencies and fuel utilizations. The results illustrated that THD can be used to detect increasing non-linearities in the current-voltage characteristics of the stack when the stack suffers from fuel starvation by monitoring the stack sum...

  7. Applying a Genetic Algorithm to Reconfigurable Hardware

    Science.gov (United States)

    Wells, B. Earl; Weir, John; Trevino, Luis; Patrick, Clint; Steincamp, Jim

    2004-01-01

    This paper investigates the feasibility of applying genetic algorithms to solve optimization problems that are implemented entirely in reconfgurable hardware. The paper highlights the pe$ormance/design space trade-offs that must be understood to effectively implement a standard genetic algorithm within a modem Field Programmable Gate Array, FPGA, reconfgurable hardware environment and presents a case-study where this stochastic search technique is applied to standard test-case problems taken from the technical literature. In this research, the targeted FPGA-based platform and high-level design environment was the Starbridge Hypercomputing platform, which incorporates multiple Xilinx Virtex II FPGAs, and the Viva TM graphical hardware description language.

  8. Space shuttle main engine hardware simulation

    Science.gov (United States)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  9. Precision cosmography with stacked voids

    CERN Document Server

    Lavaux, Guilhem

    2011-01-01

    We present a purely geometrical method for probing the expansion history of the Universe from the observation of the shape of stacked voids in spectroscopic re dshift surveys. Our method is an Alcock-Pasczinsky test based on the average sphericity of voids posited on the local isotropy of the Universe. It works by comparing the temporal extent of cosmic voids along the line of sight with their angular, spatial extent. We describe the algorithm that we use to detect and stack voids in redshift shells on the light cone and test it on mock light cones produced from N-body simulations. We establish a robust statistical model for estimating the average stretching of voids in redshift space and quantify the contamination by peculiar velocities. Finally, we assess the capability of this approach to constrain dark energy parameters in terms of the figure of merit (FoM) of the dark energy task force and in particular of the proposed Euclid mission which is particularly suited for this technique since it is a spectrosc...

  10. Air-Cooled Stack Freeze Tolerance Freeze Failure Modes and Freeze Tolerance Strategies for GenDriveTM Material Handling Application Systems and Stacks Final Scientific Report

    Energy Technology Data Exchange (ETDEWEB)

    Hancock, David, W.

    2012-02-14

    Air-cooled stack technology offers the potential for a simpler system architecture (versus liquid-cooled) for applications below 4 kilowatts. The combined cooling and cathode air allows for a reduction in part count and hence a lower cost solution. However, efficient heat rejection challenges escalate as power and ambient temperature increase. For applications in ambient temperatures below freezing, the air-cooled approach has additional challenges associated with not overcooling the fuel cell stack. The focus of this project was freeze tolerance while maintaining all other stack and system requirements. Through this project, Plug Power advanced the state of the art in technology for air-cooled PEM fuel cell stacks and related GenDrive material handling application fuel cell systems. This was accomplished through a collaborative work plan to improve freeze tolerance and mitigate freeze-thaw effect failure modes within innovative material handling equipment fuel cell systems designed for use in freezer forklift applications. Freeze tolerance remains an area where additional research and understanding can help fuel cells to become commercially viable. This project evaluated both stack level and system level solutions to improve fuel cell stack freeze tolerance. At this time, the most cost effective solutions are at the system level. The freeze mitigation strategies developed over the course of this project could be used to drive fuel cell commercialization. The fuel cell system studied in this project was Plug Power's commercially available GenDrive platform providing battery replacement for equipment in the material handling industry. The fuel cell stacks were Ballard's commercially available FCvelocity 9SSL (9SSL) liquid-cooled PEM fuel cell stack and FCvelocity 1020ACS (Mk1020) air-cooled PEM fuel cell stack.

  11. Gate stack technology for nanoscale devices

    Directory of Open Access Journals (Sweden)

    Byoung Hun Lee

    2006-06-01

    Full Text Available Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS field-effect transistors (FETs of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

  12. Demagnetizing effects in stacked rectangular prisms

    DEFF Research Database (Denmark)

    Christensen, Dennis; Nielsen, Kaspar Kirstein; Bahl, Christian Robert Haffenden;

    2011-01-01

    A numerical, magnetostatic model of the internal magnetic field of a rectangular prism is extended to the case of a stack of rectangular prisms. The model enables the calculation of the spatially resolved, three-dimensional internal field in such a stack given any magnetic state function, stack...... configuration, temperature distribution and applied magnetic field. In this paper the model is applied to the case of a stack of parallel, ferromagnetic rectangular prisms and the resulting internal field is found as a function of the orientation of the applied field, the number of prisms in the stack...... a direct impact on the design of, e.g., active magnetic regenerators made of stacked rectangular prisms in terms of optimizing the internal field....

  13. Ultra-dark graphene stack metamaterials

    Science.gov (United States)

    Chugh, Sunny; Man, Mengren; Chen, Zhihong; Webb, Kevin J.

    2015-02-01

    We present a fabrication method to achieve a graphene stack metamaterial, a periodic array of unit cells composed of graphene and a thin insulating spacer, that allows accumulation of the strong absorption from individual graphene sheets and low reflectivity from the stack. The complex sheet conductivity of graphene from experimental data models the measured power transmitted as a function of wavelength and number of periods in the stack. Simulated results based on the extracted graphene complex sheet conductivity for thicker stacks suggest that the graphene stack reflectivity and the per-unit-length absorption can be controlled to exceed the performance of competing light absorbers. Furthermore, the electrical properties of graphene coupled with the stack absorption characteristics provide for applications in optoelectronic devices.

  14. Resolution-independent surface rendering using programmable graphics hardware

    Science.gov (United States)

    Loop, Charles T.; Blinn, James Frederick

    2008-12-16

    Surfaces defined by a Bezier tetrahedron, and in particular quadric surfaces, are rendered on programmable graphics hardware. Pixels are rendered through triangular sides of the tetrahedra and locations on the shapes, as well as surface normals for lighting evaluations, are computed using pixel shader computations. Additionally, vertex shaders are used to aid interpolation over a small number of values as input to the pixel shaders. Through this, rendering of the surfaces is performed independently of viewing resolution, allowing for advanced level-of-detail management. By individually rendering tetrahedrally-defined surfaces which together form complex shapes, the complex shapes can be rendered in their entirety.

  15. Hardware-in-the-Loop Testing

    Data.gov (United States)

    Federal Laboratory Consortium — RTC has a suite of Hardware-in-the Loop facilities that include three operational facilities that provide performance assessment and production acceptance testing of...

  16. Hardware device binding and mutual authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  17. Reliability of NFV Using COTS Hardware

    Institute of Scientific and Technical Information of China (English)

    Li Mo

    2014-01-01

    This paper describes a study on the feasibility of using com-mercial off -the -shelf (COTS) hardware for telecom equip-ment. The study outlines the conditions under which COTS hardware can be utilized in a network function virtualization environment. The concept of silent -error probability is intro-duced to account for software errors and/or undetectable hard-ware failures, and is included in both the theoretical work and simulations. Silent failures are critical to overall system availability. Site -related issues are created by combined site maintenance and site failure. Site maintenance does not no-ticeably limit system availability unless there are also site fail-ures. Because the theory becomes extremely involved when site failure is introduced, simulation is used to determine the impact of those facts that constitutes the undesirable features of using COTS hardware.

  18. Efficient Hardware Design and Implementation of AES Cryptosystem

    Directory of Open Access Journals (Sweden)

    Pravin B. Ghewari

    2010-03-01

    Full Text Available We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES-Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology(NIST of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL. Optimized and Synthesizable VHDL code is developed for theimplementation of both 128- bit data encryption and decryption process. Xilinx ISE 8.1 software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The throughput reaches the value of 352 Mbit/sec for both encryption and decryption process with Device XCV600 of Xilinx Virtex Family.

  19. Stacking technology for a space constrained microsystem

    DEFF Research Database (Denmark)

    Heschel, Matthias; Kuhmann, Jochen Friedrich; Bouwstra, Siebe;

    1998-01-01

    In this paper we present a stacking technology for an integrated packaging of an intelligent transducer which is formed by a micromachined silicon transducer and an integrated circuit chip. Transducer and circuitry are stacked on top of each other with an intermediate chip in between. The bonding...... of the transducer and the intermediate chip is done by flip chip solder bump bonding. The bonding between the above two-layer stack and the circuit chip is done by conductive adhesive bonding combined with gold studs. We demonstrate the stacking technologies on passive test chips rather than real devices and report...... on technological details...

  20. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  1. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  2. Interactive histology of large-scale biomedical image stacks.

    Science.gov (United States)

    Jeong, Won-Ki; Schneider, Jens; Turney, Stephen G; Faulkner-Jones, Beverly E; Meyer, Dominik; Westermann, Rüdiger; Reid, R Clay; Lichtman, Jeff; Pfister, Hanspeter

    2010-01-01

    Histology is the study of the structure of biological tissue using microscopy techniques. As digital imaging technology advances, high resolution microscopy of large tissue volumes is becoming feasible; however, new interactive tools are needed to explore and analyze the enormous datasets. In this paper we present a visualization framework that specifically targets interactive examination of arbitrarily large image stacks. Our framework is built upon two core techniques: display-aware processing and GPU-accelerated texture compression. With display-aware processing, only the currently visible image tiles are fetched and aligned on-the-fly, reducing memory bandwidth and minimizing the need for time-consuming global pre-processing. Our novel texture compression scheme for GPUs is tailored for quick browsing of image stacks. We evaluate the usability of our viewer for two histology applications: digital pathology and visualization of neural structure at nanoscale-resolution in serial electron micrographs.

  3. Software for Managing Inventory of Flight Hardware

    Science.gov (United States)

    Salisbury, John; Savage, Scott; Thomas, Shirman

    2003-01-01

    The Flight Hardware Support Request System (FHSRS) is a computer program that relieves engineers at Marshall Space Flight Center (MSFC) of most of the non-engineering administrative burden of managing an inventory of flight hardware. The FHSRS can also be adapted to perform similar functions for other organizations. The FHSRS affords a combination of capabilities, including those formerly provided by three separate programs in purchasing, inventorying, and inspecting hardware. The FHSRS provides a Web-based interface with a server computer that supports a relational database of inventory; electronic routing of requests and approvals; and electronic documentation from initial request through implementation of quality criteria, acquisition, receipt, inspection, storage, and final issue of flight materials and components. The database lists both hardware acquired for current projects and residual hardware from previous projects. The increased visibility of residual flight components provided by the FHSRS has dramatically improved the re-utilization of materials in lieu of new procurements, resulting in a cost savings of over $1.7 million. The FHSRS includes subprograms for manipulating the data in the database, informing of the status of a request or an item of hardware, and searching the database on any physical or other technical characteristic of a component or material. The software structure forces normalization of the data to facilitate inquiries and searches for which users have entered mixed or inconsistent values.

  4. Stacks of SPS Dipole Magnets

    CERN Multimedia

    1974-01-01

    Stacks of SPS Dipole Magnets ready for installation in the tunnel. The SPS uses a separated function lattice with dipoles for bending and quadrupoles for focusing. The 6.2 m long normal conducting dipoles are of H-type with coils that are bent-up at the ends. There are two types, B1 (total of 360) and B2 (384). Both are for a maximum field of 1.8 Tesla and have the same outer dimensions (450x800 mm2 vxh) but with different gaps (B1: 39x129 mm2, B2: 52x92 mm2) tailored to the beam size. The yoke, made of 1.5 mm thick laminations, consists of an upper and a lower half joined together in the median plane once the coils have been inserted.

  5. Hardware-Based Simulation of a Fuel Cell Turbine Hybrid Response to Imposed Fuel Cell Load Transients

    Energy Technology Data Exchange (ETDEWEB)

    Smith, T.P. (Georgia Inst. of Technology); Tucker, D.A.; Haynes, C.L. (Georgia Inst. of Technology); Liese, E.A.; Wepfer, W.J. (Georgia Inst. of Technology)

    2006-11-01

    Electrical load transients imposed on the cell stack of a solid oxide fuel cell/gas turbine hybrid power system are studied using the Hybrid Performance (HyPer) project. The hardware simulation facility is located at the U.S. Department of Energy, National Energy Technology Laboratory (NETL). A computational fuel cell model capable of operating in real time is integrated with operating gas turbine hardware. The thermal output of a modeled 350 kW solid oxide fuel cell stack is replicated in the facility by a natural gas fired burner in a direct fired hybrid configuration. Pressure vessels are used to represent a fuel cell stack's cathode flow and post combustion volume and flow impedance. This hardware is used to simulate the fuel cell stack and is incorporated with a modified turbine, compressor, and 120 kW generator on a single shaft. For this study, a simulation was started with a simulated current demand of 307 A on the fuel cell at approximately 0.75 V and an actual 45 kW electrical load on the gas turbine. An open loop response, allowing the turbine rotational speed to respond to thermal transients, was successfully evaluated for a 5% current reduction on the fuel cell followed by a 5% current increase. The impact of the fuel cell load change on system process variables is presented. The test results demonstrate the capabilities of the hardware-in-the-loop simulation approach in evaluating hybrid fuel cell turbine dynamics and performance.

  6. Introduction to co-simulation of software and hardware in embedded processor systems

    Energy Technology Data Exchange (ETDEWEB)

    Dreike, P.L.; McCoy, J.A.

    1996-09-01

    From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

  7. Fast concurrent array-based stacks, queues and deques using fetch-and-increment-bounded, fetch-and-decrement-bounded and store-on-twin synchronization primitives

    Science.gov (United States)

    Chen, Dong; Gara, Alana; Heidelberger, Philip; Kumar, Sameer; Ohmacht, Martin; Steinmacher-Burow, Burkhard; Wisniewski, Robert

    2014-09-16

    Implementation primitives for concurrent array-based stacks, queues, double-ended queues (deques) and wrapped deques are provided. In one aspect, each element of the stack, queue, deque or wrapped deque data structure has its own ticket lock, allowing multiple threads to concurrently use multiple elements of the data structure and thus achieving high performance. In another aspect, new synchronization primitives FetchAndIncrementBounded (Counter, Bound) and FetchAndDecrementBounded (Counter, Bound) are implemented. These primitives can be implemented in hardware and thus promise a very fast throughput for queues, stacks and double-ended queues.

  8. A Novel Hardware Logic Encryption Technique for thwarting Illegal Overproduction and Hardware Trojans

    OpenAIRE

    Dupuis, Sophie; Ba, Papa-Sidi; Ba, Papa-Sidy; Di Natale, Giorgio; Flottes, Marie-Lise; Rouzeyre, Bruno

    2014-01-01

    International audience; Hardware piracy is a threat that is becoming more and more serious these last years. The different types of threats include mask theft, illegal overproduction, as well as the insertion of malicious alterations to a circuit, referred to as Hardware Trojans. To protect circuits from overproduction, circuits can be encrypted so that only authorized users can use the circuits. In this paper, we propose an encryption technique that also helps thwarting Hardware Trojan inser...

  9. Implementation of AES as a Custom Hardware using NIOS II Processor

    Directory of Open Access Journals (Sweden)

    Meghana Hasamnis

    2012-08-01

    Full Text Available In this paper Advanced Encryption Standard (AES algorithm has been designed and implemented as custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input / Output Port. AES implemented using data size of 128 bits, while the length of the key used is of 128 bits. The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and serves as an accelerator and hence improves the performance of the system.

  10. Evolvable Hardware Based Software-Hardware Co-Designing Platform ECDP

    Institute of Scientific and Technical Information of China (English)

    TU Hang; WU Tao-jun; LI Yuan-xiang

    2005-01-01

    Based on the theories of EA (Evolutionary Algorithm) and EHW (Evolvable Hardware), we devise an EHW-based software-hardware co-designing platform ECDP, on which we provided standards for hardware system encoding and evolving operation designing, as well as circuit emulating tools. The major features of this system are: two-layer-encoding of circuit structure, off-line evolving with software emulation and the evolving of genetic program designing. With this system, we implemented the auto-designing of some software-hardware systems, like the random number generator.

  11. Symptomatic Hardware Removal After First Tarsometatarsal Arthrodesis.

    Science.gov (United States)

    Peterson, Kyle S; McAlister, Jeffrey E; Hyer, Christopher F; Thompson, John

    2016-01-01

    Severe hallux valgus deformity with proximal instability creates pain and deformity in the forefoot. First tarsometatarsal joint arthrodesis is performed to reduce the intermetatarsal angle and stabilize the joint. Dorsomedial locking plate fixation with adjunctive lag screw fixation is used because of its superior construct strength and healing rate. Despite this, questions remain regarding whether this hardware is more prominent and more likely to need removal. The purpose of the present study was to determine the incidence of symptomatic hardware at the first tarsometatarsal joint and to determine the incidence of hardware removal resulting from prominence and/or discomfort. A review of 165 medical records of consecutive patients who had undergone first tarsometatarsal joint arthrodesis with plate fixation was conducted. The outcome of interest was the incidence of symptomatic hardware removal in patients with clinical union. The mean age was 55 (range 18.4 to 78.8) years. The mean follow-up duration was 65.9 ± 34.0 (range 7.0 to 369.0) weeks. In our cohort, 25 patients (15.2%) had undergone hardware removed because of pain and irritation. Of these patients, 18 (72.0%) had a locking plate and lag screw removed, and 7 (28.0%) had crossing lag screws removed. The fixation of a first tarsometatarsal joint fusion poses a difficult situation owing to minimal soft tissue coverage and the inherent need for robust fixation to promote fusion. Hardware can become prominent postoperatively and can become painful and/or induce cutaneous compromise. The results of the present observational investigation imply that surgeons can reasonably inform patients that the incidence of symptomatic hardware removal after first tarsometatarsal arthrodesis is approximately 15% within a median duration of 9.0 months after surgery.

  12. 40 CFR 61.44 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.44 Section 61.44 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... Firing § 61.44 Stack sampling. (a) Sources subject to § 61.42(b) shall be continuously sampled,...

  13. Learning OpenStack networking (Neutron)

    CERN Document Server

    Denton, James

    2014-01-01

    If you are an OpenStack-based cloud operator with experience in OpenStack Compute and nova-network but are new to Neutron networking, then this book is for you. Some networking experience is recommended, and a physical network infrastructure is required to provide connectivity to instances and other network resources configured in the book.

  14. Vector Fields and Flows on Differentiable Stacks

    DEFF Research Database (Denmark)

    A. Hepworth, Richard

    2009-01-01

    This paper introduces the notions of vector field and flow on a general differentiable stack. Our main theorem states that the flow of a vector field on a compact proper differentiable stack exists and is unique up to a uniquely determined 2-cell. This extends the usual result on the existence...... of vector fields....

  15. Status of MCFC stack technology at IHI

    Energy Technology Data Exchange (ETDEWEB)

    Hosaka, M.; Morita, T.; Matsuyama, T.; Otsubo, M. [Ishikawajima-Harima Heavy Industries Co., Ltd., Tokyo (Japan)

    1996-12-31

    The molten carbonate fuel cell (MCFC) is a promising option for highly efficient power generation possible to enlarge. IHI has been studying parallel flow MCFC stacks with internal manifolds that have a large electrode area of 1m{sup 2}. IHI will make two 250 kW stacks for MW plant, and has begun to make cell components for the plant. To improve the stability of stack, soft corrugated plate used in the separator has been developed, and a way of gathering current from stacks has been studied. The DC output potential of the plant being very high, the design of electric insulation will be very important. A 20 kW short stack test was conducted in 1995 FY to certificate some of the improvements and components of the MW plant. These activities are presented below.

  16. Demonstration Advanced Avionics System (DAAS), Phase 1

    Science.gov (United States)

    Bailey, A. J.; Bailey, D. G.; Gaabo, R. J.; Lahn, T. G.; Larson, J. C.; Peterson, E. M.; Schuck, J. W.; Rodgers, D. L.; Wroblewski, K. A.

    1981-01-01

    Demonstration advanced anionics system (DAAS) function description, hardware description, operational evaluation, and failure mode and effects analysis (FMEA) are provided. Projected advanced avionics system (PAAS) description, reliability analysis, cost analysis, maintainability analysis, and modularity analysis are discussed.

  17. Stacking fault probability and stacking fault energy in CoNi alloys

    Institute of Scientific and Technical Information of China (English)

    周伟敏; 江伯鸿; 刘岩; 漆王睿

    2001-01-01

    The stacking fault probability of CoNi alloys with different contents of Ni was measured by X-ray diffraction methods. The results show that the stacking fault decreases with increasing Ni content and with increasing temperature. The thermodynamical calculation has found an equation that can express the stacking fault energy γ of CoNi at temperature T. The phase equilibrium temperature depends on the composition of the certain alloy. The relationship between stacking fault energy γ and stacking fault probability Psf is determined.

  18. Bipolarly stacked electrolyser for energy and space efficient fabrication of supercapacitor electrodes

    Science.gov (United States)

    Liu, Xiaojuan; Wu, Tao; Dai, Zengxin; Tao, Keran; Shi, Yong; Peng, Chuang; Zhou, Xiaohang; Chen, George Z.

    2016-03-01

    Stacked electrolysers with titanium bipolar plates are constructed for electrodeposition of polypyrrole electrodes for supercapacitors. The cathode side of the bipolar Ti plates are pre-coated with activated carbon. In this new design, half electrolysis occurs which significantly lowers the deposition voltage. The deposited electrodes are tested in a symmetrical unit cell supercapacitor and an asymmetrical supercapacitor stack. Both devices show excellent energy storage performances and the capacitance values are very close to the design value, suggesting a very high current efficiency during the electrodeposition. The electrolyser stack offers multi-fold benefits for preparation of conducting polymer electrodes, i.e. low energy consumption, facile control of the electrode capacitance and simultaneous preparation of a number of identical electrodes. Therefore, the stacked bipolar electrolyser is a technology advance that offers an engineering solution for mass production of electrodeposited conducting polymer electrodes for supercapacitors.

  19. Stacks: building and genotyping Loci de novo from short-read sequences.

    Science.gov (United States)

    Catchen, Julian M; Amores, Angel; Hohenlohe, Paul; Cresko, William; Postlethwait, John H

    2011-08-01

    Advances in sequencing technology provide special opportunities for genotyping individuals with speed and thrift, but the lack of software to automate the calling of tens of thousands of genotypes over hundreds of individuals has hindered progress. Stacks is a software system that uses short-read sequence data to identify and genotype loci in a set of individuals either de novo or by comparison to a reference genome. From reduced representation Illumina sequence data, such as RAD-tags, Stacks can recover thousands of single nucleotide polymorphism (SNP) markers useful for the genetic analysis of crosses or populations. Stacks can generate markers for ultra-dense genetic linkage maps, facilitate the examination of population phylogeography, and help in reference genome assembly. We report here the algorithms implemented in Stacks and demonstrate their efficacy by constructing loci from simulated RAD-tags taken from the stickleback reference genome and by recapitulating and improving a genetic map of the zebrafish, Danio rerio.

  20. Probing Temperature Inside Planar SOFC Short Stack, Modules, and Stack Series

    Science.gov (United States)

    Yu, Rong; Guan, Wanbing; Zhou, Xiao-Dong

    2016-11-01

    Probing temperature inside a solid oxide fuel cell (SOFC) stack lies at the heart of the development of high-performance and stable SOFC systems. In this article, we report our recent work on the direct measurements of the temperature in three types of SOFC systems: a 5-cell short stack, a 30-cell stack module, and a stack series consisting of two 30-cell stack modules. The dependence of temperature on the gas flow rate and current density was studied under a current sweep or steady-state operation. During the current sweep, the temperature inside the 5-cell stack decreased with increasing current, while it increased significantly at the bottom and top of the 30-cell stack. During a steady-state operation, the temperature of the 5-cell stack was stable while it was increased in the 30-cell stack. In the stack series, the maximum temperature gradient reached 190°C when the gas was not preheated. If the gas was preheated and the temperature gradient was reduced to 23°C in the stack series with the presence of a preheating gas and segmented temperature control, this resulted in a low degradation rate.

  1. Robot navigation system using intrinsic evolvable hardware

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Recently there has been great interest in the idea that evolvable system based on the principle of ar tifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduc tion of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to a dapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA)and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behav iours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the tra ditional hardware systems.

  2. Memory Stacking in Hierarchical Networks.

    Science.gov (United States)

    Westö, Johan; May, Patrick J C; Tiitinen, Hannu

    2016-02-01

    Robust representations of sounds with a complex spectrotemporal structure are thought to emerge in hierarchically organized auditory cortex, but the computational advantage of this hierarchy remains unknown. Here, we used computational models to study how such hierarchical structures affect temporal binding in neural networks. We equipped individual units in different types of feedforward networks with local memory mechanisms storing recent inputs and observed how this affected the ability of the networks to process stimuli context dependently. Our findings illustrate that these local memories stack up in hierarchical structures and hence allow network units to exhibit selectivity to spectral sequences longer than the time spans of the local memories. We also illustrate that short-term synaptic plasticity is a potential local memory mechanism within the auditory cortex, and we show that it can bring robustness to context dependence against variation in the temporal rate of stimuli, while introducing nonlinearities to response profiles that are not well captured by standard linear spectrotemporal receptive field models. The results therefore indicate that short-term synaptic plasticity might provide hierarchically structured auditory cortex with computational capabilities important for robust representations of spectrotemporal patterns.

  3. Economic impact of syndesmosis hardware removal.

    Science.gov (United States)

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system.

  4. Detailed experimental characterization of a reformate fuelled PEM stack

    DEFF Research Database (Denmark)

    Korsgaard, Anders; Nielsen, Mads Pagh; Kær, Søren Knudsen

    2006-01-01

    Increasing attention is given to fuel cells for micro combined heat and power systems for local households. Currently, mainly three different types of fuel cells are commercially competitive: SOFC, low- and high-temperature PEM fuel cells. In the present paper the Low Temperature PEM technology...... performance and process input variations need to be carefully accounted for. Such data will additionally provide valuable input for system modeling and optimization. The paper presents an advanced experimental test facility capable of performing static as well as dynamic tests on fuel cell stacks...

  5. Language of CTO interventions - Focus on hardware.

    Science.gov (United States)

    Mishra, Sundeep

    2016-01-01

    The knowledge of variety of chronic total occlusion (CTO) hardware and the ability to use them represents the key to success of any CTO interventions. However, the multiplicity of CTO hardware and their physical character and the terminology used by experts create confusion in the mind of an average interventional cardiologist, particularly a beginner in this field. This knowledge is available but is scattered. We aim to classify and compare the currently used devices based on their properties focusing on how physical character of each device can be utilized in a specific situation, thus clarifying and simplifying the technical discourse.

  6. Magnetic Field Apparatus (MFA) Hardware Test

    Science.gov (United States)

    Anderson, Ken; Boody, April; Reed, Dave; Wang, Chung; Stuckey, Bob; Cox, Dave

    1999-01-01

    The objectives of this study are threefold: (1) Provide insight into water delivery in microgravity and determine optimal germination paper wetting for subsequent seed germination in microgravity; (2) Observe the behavior of water exposed to a strong localized magnetic field in microgravity; and (3) Simulate the flow of fixative (using water) through the hardware. The Magnetic Field Apparatus (MFA) is a new piece of hardware slated to fly on the Space Shuttle in early 2001. MFA is designed to expose plant tissue to magnets in a microgravity environment, deliver water to the plant tissue, record photographic images of plant tissue, and deliver fixative to the plant tissue.

  7. Hardware Trojan by Hot Carrier Injection

    CERN Document Server

    Shiyanovskii, Y; Papachristou, C; Weyer, D; Clay, W

    2009-01-01

    This paper discusses how hot carrier injection (HCI) can be exploited to create a trojan that will cause hardware failures. The trojan is produced not via additional logic circuitry but by controlled scenarios that maximize and accelerate the HCI effect in transistors. These scenarios range from manipulating the manufacturing process to varying the internal voltage distribution. This new type of trojan is difficult to test due to its gradual hardware degradation mechanism. This paper describes the HCI effect, detection techniques and discusses the possibility for maliciously induced HCI trojans.

  8. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  9. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  10. Butterflies I: morphisms of 2-group stacks

    CERN Document Server

    Aldrovandi, Ettore

    2008-01-01

    Weak morphisms of non-abelian complexes of length 2, or crossed modules, are morphisms of the associated 2-group stacks, or gr-stacks. We present a full description of the weak morphisms in terms of diagrams we call butterflies. We give a complete description of the resulting bicategory of crossed modules, which we show is fibered and biequivalent to the 2-stack of 2-group stacks. As a consequence we obtain a complete characterization of the non-abelian derived category of complexes of length 2. Deligne's analogous theorem in the case of Picard stacks and abelian sheaves becomes an immediate corollary. Commutativity laws on 2-group stacks are also analyzed in terms of butterflies, yielding new characterizations of braided, symmetric, and Picard 2-group stacks. Furthermore, the description of a weak morphism in terms of the corresponding butterfly diagram allows us to obtain a long exact sequence in non-abelian cohomology, removing a preexisting fibration condition on the coefficients short exact sequence.

  11. On flow maldistribution in PEMFC stacks

    Energy Technology Data Exchange (ETDEWEB)

    Wang, J. [Xi' an Jiaotong Univ., Xi' an (China). State Key Laboratory of Multiphase Flow in Power Engineering; Lund Univ., Lund (Sweden). Dept. of Energy Sciences, Heat Transfer Div.; Yan, J. [Xi' an Jiaotong Univ., Xi' an (China). State Key Laboratory of Multiphase Flow in Power Engineering; Yuan, J.; Sunden, B. [Lund Univ., Lund (Sweden). Dept. of Energy Sciences, Heat Transfer Div.

    2010-07-01

    Fuel cell devices have technical and environmental advantages over thermal power systems. The advantages include high performance characteristics, reliability, durability and low emissions. In order to increase the voltage in a single PEMFC for practical operations, many single cells are serially connected to fabricate a fuel cell stack. This study focused on the flow maldistribution at stack level. The flow maldistribution in unit cells may significantly influence the fuel cell stack performance, including the uniformity of current density and the voltage. Of the few studies on flow maldistribution in PEMFC stacks, the results are unsystematic, scattered, and even contradictory. As such, it is necessary to review and summarize previous studies to gain insight into methods to reduce the flow maldistribution in PEMFC stacks. This paper therefore reviewed existing literature concerning flow maldistributions in PEMFC stacks and discussed the effects of the arrangement of flow configurations, design parameters and operating conditions on the flow maldistribution. Some suggestions were outlined to reduce the flow maldistribution in PEMFC stacks. 34 refs., 1 tab., 13 figs.

  12. Density of oxidation-induced stacking faults in damaged silicon

    NARCIS (Netherlands)

    Kuper, F.G.; Hosson, J.Th.M. De; Verwey, J.F.

    1986-01-01

    A model for the relation between density and length of oxidation-induced stacking faults on damaged silicon surfaces is proposed, based on interactions of stacking faults with dislocations and neighboring stacking faults. The model agrees with experiments.

  13. Development of a driver information and warning system with vehicle hardware-in-the-loop simulations

    NARCIS (Netherlands)

    Gietelink, O.J.; Ploeg, J.; Schutter, B. de; Verhaegen, M.

    2009-01-01

    This paper presents a new method for the design and validation of advanced driver assistance systems (ADASs). With vehicle hardware-in-the-loop (VeHIL) simulations the development process, and more specifically the validation phase, of intelligent vehicles is carried out safer, cheaper, and more man

  14. Dynamical Stability of Slip-stacking Particles

    CERN Document Server

    Eldred, Jeffrey

    2014-01-01

    We study the stability of particles in slip-stacking configuration, used to nearly double proton beam intensity at Fermilab. We introduce universal area factors to calculate the available phase space area for any set of beam parameters without individual simulation. We find perturbative solutions for stable particle trajectories. We establish Booster beam quality requirements to achieve 97\\% slip-stacking efficiency. We show that slip-stacking dynamics directly correspond to the driven pendulum and to the system of two standing-wave traps moving with respect to each other.

  15. Dynamical stability of slip-stacking particles

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, Jeffrey; Zwaska, Robert

    2014-09-01

    We study the stability of particles in slip-stacking configuration, used to nearly double proton beam intensity at Fermilab. We introduce universal area factors to calculate the available phase space area for any set of beam parameters without individual simulation. We find perturbative solutions for stable particle trajectories. We establish Booster beam quality requirements to achieve 97% slip-stacking efficiency. We show that slip-stacking dynamics directly correspond to the driven pendulum and to the system of two standing-wave traps moving with respect to each other.

  16. Vector Fields and Flows on Differentiable Stacks

    DEFF Research Database (Denmark)

    A. Hepworth, Richard

    2009-01-01

    This paper introduces the notions of vector field and flow on a general differentiable stack. Our main theorem states that the flow of a vector field on a compact proper differentiable stack exists and is unique up to a uniquely determined 2-cell. This extends the usual result on the existence...... and uniqueness of flows on a manifold as well as the author's existing results for orbifolds. It sets the scene for a discussion of Morse Theory on a general proper stack and also paves the way for the categorification of other key aspects of differential geometry such as the tangent bundle and the Lie algebra...

  17. Dynamical Stability of Slip-stacking Particles

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, Jeffrey [Fermilab; Zwaska, Robert [Fermilab

    2014-09-04

    We study the stability of particles in slip-stacking configuration, used to nearly double proton beam intensity at Fermilab. We introduce universal area factors to calculate the available phase space area for any set of beam parameters without individual simulation. We find perturbative solutions for stable particle trajectories. We establish Booster beam quality requirements to achieve 97% slip-stacking efficiency. We show that slip-stacking dynamics directly correspond to the driven pendulum and to the system of two standing-wave traps moving with respect to each other.

  18. Enabling Open Hardware through FOSS tools

    CERN Document Server

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  19. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  20. QCE : A Simulator for Quantum Computer Hardware

    NARCIS (Netherlands)

    Michielsen, Kristel; Raedt, Hans De

    2003-01-01

    The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms.

  1. Computer hardware for radiologists: Part I.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  2. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  3. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  4. Arbitrary Hardware Software Trade-Offs

    NARCIS (Netherlands)

    Middelhoek, Peter F.A.

    1995-01-01

    This paper discusses a novel transformation-based design methodology and its use in the design of complex programmable VLSI systems. During the life-cycle of a complex system, the optimal trade-off between partially implementing in hardware or software is changing. This is due to varying system requ

  5. A mathematical approach towards hardware design

    NARCIS (Netherlands)

    Smit, Gerard J.M.; Kuper, Jan; Baaij, Christiaan P.R.; Athanas, P.M.; Becker, J.; Teich, J.; Verbauwhede, I.

    2010-01-01

    Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of th

  6. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access ...

  7. Remote hardware-reconfigurable robotic camera

    Science.gov (United States)

    Arias-Estrada, Miguel; Torres-Huitzil, Cesar; Maya-Rueda, Selene E.

    2001-10-01

    In this work, a camera with integrated image processing capabilities is discussed. The camera is based on an imager coupled to an FPGA device (Field Programmable Gate Array) which contains an architecture for real-time computer vision low-level processing. The architecture can be reprogrammed remotely for application specific purposes. The system is intended for rapid modification and adaptation for inspection and recognition applications, with the flexibility of hardware and software reprogrammability. FPGA reconfiguration allows the same ease of upgrade in hardware as a software upgrade process. The camera is composed of a digital imager coupled to an FPGA device, two memory banks, and a microcontroller. The microcontroller is used for communication tasks and FPGA programming. The system implements a software architecture to handle multiple FPGA architectures in the device, and the possibility to download a software/hardware object from the host computer into its internal context memory. System advantages are: small size, low power consumption, and a library of hardware/software functionalities that can be exchanged during run time. The system has been validated with an edge detection and a motion processing architecture, which will be presented in the paper. Applications targeted are in robotics, mobile robotics, and vision based quality control.

  8. LWH and ACH Helmet Hardware Study

    Science.gov (United States)

    2015-11-30

    testing included dimensional measurements, Rockwell hardness and Vicker’s microhardness measurements, metallographic examination of the grain... microhardness measurements (ASTM E384 Standard Test Method for Microindentation Hardness of Materials) were made on the exterior surfaces of screws...hardware as reference values. However, we do not recommend use of surface Vicker’s microhardness testing for characterizing the nuts, because, as

  9. Hardware Model of a Shipboard Generator

    Science.gov (United States)

    2009-05-19

    13 2.3 DC Motor Characteristics...Figure 4: Motor Nameplate.............................................................................................. 14 Figure 5: DC Motor Circuit...used in the hardware model is briefly described in the first two sections of Chapter 2. Section 2.3 details the characterization of the DC motor and

  10. Associative Memory Hardware Elements for Cognitive Systems

    Science.gov (United States)

    2006-01-01

    basis for learning ............. 40 Figure 33: Historical examples of crossbar for associative memory hardware ................ 41 Figure 34: Recent...provide one and only one function such as classification, segmentation, or pattern completion, the lazy learning approach can provide all such...standard machine learning databases and shows exponential memory capacity. For example, one test with 200 patterns was learned by only 7 quantum

  11. Test Program for Stirling Radioisotope Generator Hardware at NASA Glenn Research Center

    Science.gov (United States)

    Lewandowski, Edward J.; Bolotin, Gary S.; Oriti, Salvatore M.

    2015-01-01

    Stirling-based energy conversion technology has demonstrated the potential of high efficiency and low mass power systems for future space missions. This capability is beneficial, if not essential, to making certain deep space missions possible. Significant progress was made developing the Advanced Stirling Radioisotope Generator (ASRG), a 140-W radioisotope power system. A variety of flight-like hardware, including Stirling convertors, controllers, and housings, was designed and built under the ASRG flight development project. To support future Stirling-based power system development NASA has proposals that, if funded, will allow this hardware to go on test at the NASA Glenn Research Center. While future flight hardware may not be identical to the hardware developed under the ASRG flight development project, many components will likely be similar, and system architectures may have heritage to ASRG. Thus, the importance of testing the ASRG hardware to the development of future Stirling-based power systems cannot be understated. This proposed testing will include performance testing, extended operation to establish an extensive reliability database, and characterization testing to quantify subsystem and system performance and better understand system interfaces. This paper details this proposed test program for Stirling radioisotope generator hardware at NASA Glenn. It explains the rationale behind the proposed tests and how these tests will meet the stated objectives.

  12. Contemporary sample stacking in analytical electrophoresis.

    Science.gov (United States)

    Šlampová, Andrea; Malá, Zdena; Pantůčková, Pavla; Gebauer, Petr; Boček, Petr

    2013-01-01

    Sample stacking is a term denoting a multifarious class of methods and their names that are used daily in CE for online concentration of diluted samples to enhance separation efficiency and sensitivity of analyses. The essence of these methods is that analytes present at low concentrations in a large injected sample zone are concentrated into a short and sharp zone (stack) in the separation capillary. Then the stacked analytes are separated and detected. Regardless of the diversity of the stacking electromigration methods, one can distinguish four main principles that form the bases of nearly all of them: (i) Kohlrausch adjustment of concentrations, (ii) pH step, (iii) micellar methods, and (iv) transient ITP. This contribution is a continuation of our previous reviews on the topic and brings an overview of papers published during 2010-2012 and relevant to the mentioned principles (except the last one which is covered by another review in this issue).

  13. The stack on software and sovereignty

    CERN Document Server

    Bratton, Benjamin H

    2016-01-01

    A comprehensive political and design theory of planetary-scale computation proposing that The Stack -- an accidental megastructure -- is both a technological apparatus and a model for a new geopolitical architecture.

  14. Characterization of Piezoelectric Stacks for Space Applications

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher; Aldrich, Jack; Blodget, Chad; Bao, Xiaoqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to actuate mechanisms to precision levels in the nanometer range and below. Co-fired multilayer piezoelectric stacks offer the required actuation precision that is needed for such mechanisms. To obtain performance statistics and determine reliability for extended use, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and high temperatures and voltages. In order to study the lifetime performance of these stacks, five actuators were driven sinusoidally for up to ten billion cycles. An automated data acquisition system was developed and implemented to monitor each stack's electrical current and voltage waveforms over the life of the test. As part of the monitoring tests, the displacement, impedance, capacitance and leakage current were measured to assess the operation degradation. This paper presents some of the results of this effort.

  15. Acupuncture injection for field amplified sample stacking and glass microchip-based capillary gel electrophoresis.

    Science.gov (United States)

    Ha, Ji Won; Hahn, Jong Hoon

    2017-02-01

    Acupuncture sample injection is a simple method to deliver well-defined nanoliter-scale sample plugs in PDMS microfluidic channels. This acupuncture injection method in microchip CE has several advantages, including minimization of sample consumption, the capability of serial injections of different sample solutions into the same microchannel, and the capability of injecting sample plugs into any desired position of a microchannel. Herein, we demonstrate that the simple and cost-effective acupuncture sample injection method can be used for PDMS microchip-based field amplified sample stacking in the most simplified straight channel by applying a single potential. We achieved the increase in electropherogram signals for the case of sample stacking. Furthermore, we present that microchip CGE of ΦX174 DNA-HaeⅢ digest can be performed with the acupuncture injection method on a glass microchip while minimizing sample loss and voltage control hardware.

  16. Development of an automatic subsea blowout preventer stack control system using PLC based SCADA.

    Science.gov (United States)

    Cai, Baoping; Liu, Yonghong; Liu, Zengkai; Wang, Fei; Tian, Xiaojie; Zhang, Yanzhen

    2012-01-01

    An extremely reliable remote control system for subsea blowout preventer stack is developed based on the off-the-shelf triple modular redundancy system. To meet a high reliability requirement, various redundancy techniques such as controller redundancy, bus redundancy and network redundancy are used to design the system hardware architecture. The control logic, human-machine interface graphical design and redundant databases are developed by using the off-the-shelf software. A series of experiments were performed in laboratory to test the subsea blowout preventer stack control system. The results showed that the tested subsea blowout preventer functions could be executed successfully. For the faults of programmable logic controllers, discrete input groups and analog input groups, the control system could give correct alarms in the human-machine interface.

  17. Stacking fault energy in some single crystals

    Institute of Scientific and Technical Information of China (English)

    Aditya M.Vora

    2012-01-01

    The stacking fault energy of single crystals has been reported using the peak shift method.Presently studied all single crystals are grown by using a direct vapor transport (DVT) technique in the laboratory.The structural characterizations of these crystals are made by XRD.Considerable variations are shown in deformation (α) and growth (β) probabilities in single crystals due to off-stoichiometry,which possesses the stacking fault in the single crystal.

  18. Cosmic ray test of INO RPC stack

    Energy Technology Data Exchange (ETDEWEB)

    Bhuyan, M. [Department of High Energy Physics, Tata Institute of Fundamental Research, Mumbai 400005 (India); Datar, V.M. [Nuclear Physics Division, Bhabha Atomic Research Centre, Mumbai 400085 (India); Kalmani, S.D.; Lahamge, S.M.; Mondal, N.K.; Nagaraj, P.; Pal, S.; Reddy, L.V.; Redij, A.; Samuel, D.; Saraf, M.N. [Department of High Energy Physics, Tata Institute of Fundamental Research, Mumbai 400005 (India); Satyanarayana, B., E-mail: bsn@tifr.res.in [Department of High Energy Physics, Tata Institute of Fundamental Research, Mumbai 400005 (India); Shinde, R.R.; Verma, P. [Department of High Energy Physics, Tata Institute of Fundamental Research, Mumbai 400005 (India)

    2012-01-01

    The India-based Neutrino Observatory (INO) collaboration is planning to build a 50 kt magnetised iron calorimeter (ICAL) detector using glass Resistive Plate Chambers (RPCs) as active detector elements. A stack of 12 such glass RPCs of 1 m Multiplication-Sign 1 m in area is tracking cosmic ray muons for over three years. In this paper, we will review the constructional aspects of the stack and discuss the performance of the RPCs using this cosmic ray data.

  19. Stacking interactions in PUF-RNA complexes

    Energy Technology Data Exchange (ETDEWEB)

    Yiling Koh, Yvonne; Wang, Yeming; Qiu, Chen; Opperman, Laura; Gross, Leah; Tanaka Hall, Traci M; Wickens, Marvin [NIH; (UW)

    2012-07-02

    Stacking interactions between amino acids and bases are common in RNA-protein interactions. Many proteins that regulate mRNAs interact with single-stranded RNA elements in the 3' UTR (3'-untranslated region) of their targets. PUF proteins are exemplary. Here we focus on complexes formed between a Caenorhabditis elegans PUF protein, FBF, and its cognate RNAs. Stacking interactions are particularly prominent and involve every RNA base in the recognition element. To assess the contribution of stacking interactions to formation of the RNA-protein complex, we combine in vivo selection experiments with site-directed mutagenesis, biochemistry, and structural analysis. Our results reveal that the identities of stacking amino acids in FBF affect both the affinity and specificity of the RNA-protein interaction. Substitutions in amino acid side chains can restrict or broaden RNA specificity. We conclude that the identities of stacking residues are important in achieving the natural specificities of PUF proteins. Similarly, in PUF proteins engineered to bind new RNA sequences, the identity of stacking residues may contribute to 'target' versus 'off-target' interactions, and thus be an important consideration in the design of proteins with new specificities.

  20. AN ELECTROCHEMICAL SYSTEM FOR REMOVING AND RECOVERING ELEMENTAL MERCURY FROM FLUE-STACK GASES

    Science.gov (United States)

    the impending EPA regulations on the control of mercury emissions from the flue stacks of coal-burning electric utilities has resulted in heightened interest in the development of advanced mercury control technologies such as sorbent injection and in-situ mercury oxidation. Altho...

  1. Solid Oxide Cell and Stack Testing, Safety and Quality Assurance (SOCTESQA)

    DEFF Research Database (Denmark)

    Auer, C.; Lang, M.; Couturier, K.

    2015-01-01

    The market penetration of fuel and electrolysis cell energy systems in Europe requires the development of reliable assessment, testing and prediction of performance and durability of solid oxide cells and stacks (SOC). To advance in this field the EU-project “SOCTESQA” was launched in May 2014. P...... will be confirmed by round robin tests....

  2. Hardware-software Reconfigurable Techniques for Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    C. Rajasekaran

    2014-11-01

    Full Text Available Now-a-days, the industrial based real time embedded applications are highly developed and they act as a major role in the production cost and real world safety environment. In that, one of the advanced technique is that reconfigurable techniques. This technique plays a major role with wireless sensor networks for the efficient data transmissions. In recent days, most of the industrial applications are works to minimize the size and cost of device. The foremost improvement of the reconfigurable technique is that it circumvents the unnecessary hang and deferral in the device performance. In modern biosphere, Field Programmable Gate Array (FPGA is one of the supreme operative reconfigurable devices and generally used for most of the hardware and software reconfiguration applications. In this study, the exertion pacts with whatever going to make changes in the hardware and software during runtime, it should not disturb the present successively process. This is the main impartial of the study that the changes to be done in an analogous manner at the same time concentrating the cost and power transmission problems during data trans-receiving and also the results to be seen with the help of online manner via the Ethernet cable.

  3. The Unified Floating Point Vector Coprocessor for Reconfigurable Hardware

    Science.gov (United States)

    Kathiara, Jainik

    There has been an increased interest recently in using embedded cores on FPGAs. Many of the applications that make use of these cores have floating point operations. Due to the complexity and expense of floating point hardware, these algorithms are usually converted to fixed point operations or implemented using floating-point emulation in software. As the technology advances, more and more homogeneous computational resources and fixed function embedded blocks are added to FPGAs and hence implementation of floating point hardware becomes a feasible option. In this research we have implemented a high performance, autonomous floating point vector Coprocessor (FPVC) that works independently within an embedded processor system. We have presented a unified approach to vector and scalar computation, using a single register file for both scalar operands and vector elements. The Hybrid vector/SIMD computational model of FPVC results in greater overall performance for most applications along with improved peak performance compared to other approaches. By parameterizing vector length and the number of vector lanes, we can design an application specific FPVC and take optimal advantage of the FPGA fabric. For this research we have also initiated designing a software library for various computational kernels, each of which adapts FPVC's configuration and provide maximal performance. The kernels implemented are from the area of linear algebra and include matrix multiplication and QR and Cholesky decomposition. We have demonstrated the operation of FPVC on a Xilinx Virtex 5 using the embedded PowerPC.

  4. A Self-Provisioning Mechanism in OpenStack for IoT Devices

    Directory of Open Access Journals (Sweden)

    Antonio Solano

    2016-08-01

    Full Text Available The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT device to instantiate a Software as a Service (SaaS application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device.

  5. A Self-Provisioning Mechanism in OpenStack for IoT Devices.

    Science.gov (United States)

    Solano, Antonio; Dormido, Raquel; Duro, Natividad; Sánchez, Juan Miguel

    2016-08-17

    The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT) device to instantiate a Software as a Service (SaaS) application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device.

  6. A Self-Provisioning Mechanism in OpenStack for IoT Devices

    Science.gov (United States)

    Solano, Antonio; Dormido, Raquel; Duro, Natividad; Sánchez, Juan Miguel

    2016-01-01

    The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT) device to instantiate a Software as a Service (SaaS) application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device. PMID:27548166

  7. Campus Information Network Hardware System Design%Campus Information Network Hardware System Design

    Institute of Scientific and Technical Information of China (English)

    刘正勇

    2011-01-01

    The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export

  8. A Cost-Effective Approach to Hardware-in-the-Loop Simulation

    DEFF Research Database (Denmark)

    Pedersen, Mikkel Melters; Hansen, M. R.; Ballebye, M.

    2012-01-01

    This paper presents an approach for developing cost effective hardware-in-the- loop (HIL) simulation platforms for the use in controller software test and development. The approach is aimed at the many smaller manufacturers of e.g. mobile hydraulic machinery, which often do not have very advanced...... testing facilities at their disposal. A case study is presented where a HIL simulation platform is developed for the controller of a truck mounted loader crane. The total expenses in hardware and software is less than 10.000$....

  9. An FPGA hardware/software co-design towards evolvable spiking neural networks for robotics application.

    Science.gov (United States)

    Johnston, S P; Prasad, G; Maguire, L; McGinnity, T M

    2010-12-01

    This paper presents an approach that permits the effective hardware realization of a novel Evolvable Spiking Neural Network (ESNN) paradigm on Field Programmable Gate Arrays (FPGAs). The ESNN possesses a hybrid learning algorithm that consists of a Spike Timing Dependent Plasticity (STDP) mechanism fused with a Genetic Algorithm (GA). The design and implementation direction utilizes the latest advancements in FPGA technology to provide a partitioned hardware/software co-design solution. The approach achieves the maximum FPGA flexibility obtainable for the ESNN paradigm. The algorithm was applied as an embedded intelligent system robotic controller to solve an autonomous navigation and obstacle avoidance problem.

  10. How open hardware drives digital fabrication tools such as the 3D printer

    Directory of Open Access Journals (Sweden)

    Johan Söderberg

    2013-06-01

    Full Text Available A case study of hobbyists developing a desktop 3D printer, indicative of a broader movement around open hardware development, is used to advance a theoretical apparatus drawing on social movement research. This is proposed as an alternative to how innovation by users is typically studied in innovation studies literature, namely, as discrete, isolated cases. Open hardware development projects make up a larger ecology, held together by common ideas, a shared communication infrastructure, conferences and licenses, among other things, and it therefore makes sense to look at them as part of a single movement.

  11. Application of advanced electronics to a future spacecraft computer design

    Science.gov (United States)

    Carney, P. C.

    1980-01-01

    Advancements in hardware and software technology are summarized with specific emphasis on spacecraft computer capabilities. Available state of the art technology is reviewed and candidate architectures are defined.

  12. A new method for hardware/software integration of strategic systems - Case study of the Space Shuttle

    Science.gov (United States)

    Haque, S. I.; Ionescu, T. V.; Henley, G. D.

    1981-01-01

    An advanced system integrated self-test has been developed to provide dynamic checkout of all critical subsystems and hardware/software interfaces of the Space Shuttle during pre-launch ground testing. The system modifies hardware sensor data to represent a real flight scenario. This modified data then drives the flight software. The system was sucessfully utilized for three phases of Space Shuttle testing, and will be expanded for use as a maintenance tool.

  13. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Gottesfeld, S. [Los Alamos National Lab., NM (United States)

    1995-09-01

    The fuel cell is the most efficient device for the conversion of hydrogen fuel to electric power. As such, the fuel cell represents a key element in efforts to demonstrate and implement hydrogen fuel utilization for electric power generation. The low temperature, polymer electrolyte membrane fuel cell (PEMFC) has recently been identified as an attractive option for stationary power generation, based on the relatively simple and benign materials employed, the zero-emission character of the device, and the expected high power density, high reliability and low cost. However, a PEMFC stack fueled by hydrogen with the combined properties of low cost, high performance and high reliability has not yet been demonstrated. Demonstration of such a stack will remove a significant barrier to implementation of this advanced technology for electric power generation from hydrogen. Work done in the past at LANL on the development of components and materials, particularly on advanced membrane/electrode assemblies (MEAs), has contributed significantly to the capability to demonstrate in the foreseeable future a PEMFC stack with the combined characteristics described above. A joint effort between LANL and an industrial stack manufacturer will result in the demonstration of such a fuel cell stack for stationary power generation. The stack could operate on hydrogen fuel derived from either natural gas or from renewable sources. The technical plan includes collaboration with a stack manufacturer (CRADA). It stresses the special requirements from a PEMFC in stationary power generation, particularly maximization of the energy conversion efficiency, extension of useful life to the 10 hours time scale and tolerance to impurities from the reforming of natural gas.

  14. Variable length data formats. [in hardware-software engineering

    Science.gov (United States)

    Brakefield, J. C.; Quinn, M. J.

    1978-01-01

    The purpose of this paper is to discuss a number of variable length floating point and integer formats and to give the various advantages and disadvantages of their use. Often it is known in advance that a given integer will not exceed a certain magnitude or that a particular floating point number is accurate to only 'n' places of accuracy. Faced with this, it is good engineering to choose variable length floating point and integer formats which require the least amount of hardware or the minimum amount of software or which have some other dominant advantage. The formats discussed have the advantage that length change algorithms are invariant with respect to data types (unsigned, signed, floating point, integers, and complex numbers). The STARAN associative array processor, which uses a completely variable fixed point and floating point formats, is described.

  15. Hardware and software status of QCDOC

    CERN Document Server

    Boyle, P A; Christ, N H; Clark, M; Cohen, S D; Cristian, C; Dong, Z; Gara, A; Joó, B; Jung, C; Kim, C; Levkova, L; Liao, X; Liu, G; Mawhinney, Robert D; Ohta, S; Petrov, K V; Wettig, T; Yamaguchi, A

    2003-01-01

    QCDOC is a massively parallel supercomputer whose processing nodes are based on an application-specific integrated circuit (ASIC). This ASIC was custom-designed so that crucial lattice QCD kernels achieve an overall sustained performance of 50% on machines with several 10,000 nodes. This strong scalability, together with low power consumption and a price/performance ratio of $1 per sustained MFlops, enable QCDOC to attack the most demanding lattice QCD problems. The first ASICs became available in June of 2003, and the testing performed so far has shown all systems functioning according to specification. We review the hardware and software status of QCDOC and present performance figures obtained in real hardware as well as in simulation.

  16. Hardware Acceleration of Sparse Cognitive Algorithms

    Science.gov (United States)

    2016-05-01

    AFRL-RY-WP-TR-2016-0078 HARDWARE ACCELERATION OF SPARSE COGNITIVE ALGORITHMS Paul D Franzon, Lee Baker, Sumon Dey, Weifu Li, and...COGNITIVE ALGORITHMS 5a. CONTRACT NUMBER FA8650-15-1-7518 5b. GRANT NUMBER 5c. PROGRAM ELEMENT NUMBER 61101E 6. AUTHOR(S) Paul D Franzon, Lee...accelerators were designed for both the Sparsey and Numenta HTM cortical algorithms . Two versions were designed – a programmable 65 nm SIMD version with

  17. Computer hardware for radiologists: Part I

    OpenAIRE

    Indrajit I; Alam A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware...

  18. Particle Transport Simulation on Heterogeneous Hardware

    CERN Document Server

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  19. Hardware-Independent Proofs of Numerical Programs

    Science.gov (United States)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  20. Exploiting Semiconductor Properties for Hardware Trojans

    OpenAIRE

    Shiyanovskii, Y.; Wolff, F; Papachristou, C.; D. Weyer; Clay, W.

    2009-01-01

    This paper discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-based triggers (ESD, Latchup and Softerror). This class of latent damage is difficult to tes...

  1. Hardware code generation from dataflow programs

    OpenAIRE

    Siret, Nicolas; Wipliez, Matthieu; Nezan, Jean Francois; Rhatay, Aimad

    2010-01-01

    International audience; The elaboration of new systems on embedded targets is becoming more and more complex. In particular, multimedia devices are now implemented using mixed hardware and software architecture, which improve the computational power but also increase the design complexity and the time to market. New design flows have been developed to help designers in the development of complex architecture. These design flows are often based on the use of languages with a higher level of ab...

  2. Stabilization of RNA stacking by pseudouridine.

    Science.gov (United States)

    Davis, D R

    1995-01-01

    The effect of the modified nucleoside pseudouridine (psi) on RNA structure was compared with uridine. The extent of base stacking in model RNA oligonucleotides was measured by 1H NMR, UV, and CD spectroscopy. The UV and CD results indicate that the model single-stranded oligoribonucleotides AAUA and AA psi A form stacked structures in solution and the CD results for AA psi A are consistent with a general A-form helical conformation. The AA psi A oligomer exhibits a greater degree of UV hypochromicity over the temperature range 5-55 degrees C, consistent with a better stacked, more A-form structure compared with AAUA. The extent of stacking for each nucleotide residue was inferred from the percent 3'-endo sugar conformation as indicated by the H1'-H2' NMR scalar coupling. This indirect indication of stacking was confirmed by sequential NOE experiments. NMR measurements as a function of temperature indicate that pseudouridine forms a more stable base stacking arrangement than uridine, an effect that is propagated throughout the helix to stabilize stacking of neighboring purine nucleosides. The N1-H imino proton in AA psi A exchanges slowly with solvent, suggesting a role for the extra imino proton in stabilizing the conformation of pseudouridine. These results show that the conformational stabilization is an intrinsic property of pseudouridine occurring at the nucleotide level. The characteristics of pseudouridine in these models are consistent with earlier studies on intact rRNA, indicating that pseudouridine probably performs the same stabilizing function in most structural contexts. PMID:8559660

  3. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  4. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  5. "Greenbook Algorithms and Hardware Needs Analysis"

    Energy Technology Data Exchange (ETDEWEB)

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  6. Testing Microshutter Arrays Using Commercial FPGA Hardware

    Science.gov (United States)

    Rapchun, David

    2008-01-01

    NASA is developing micro-shutter arrays for the Near Infrared Spectrometer (NIRSpec) instrument on the James Webb Space Telescope (JWST). These micro-shutter arrays allow NIRspec to do Multi Object Spectroscopy, a key part of the mission. Each array consists of 62414 individual 100 x 200 micron shutters. These shutters are magnetically opened and held electrostatically. Individual shutters are then programmatically closed using a simple row/column addressing technique. A common approach to provide these data/clock patterns is to use a Field Programmable Gate Array (FPGA). Such devices require complex VHSIC Hardware Description Language (VHDL) programming and custom electronic hardware. Due to JWST's rapid schedule on the development of the micro-shutters, rapid changes were required to the FPGA code to facilitate new approaches being discovered to optimize the array performance. Such rapid changes simply could not be made using conventional VHDL programming. Subsequently, National Instruments introduced an FPGA product that could be programmed through a Labview interface. Because Labview programming is considerably easier than VHDL programming, this method was adopted and brought success. The software/hardware allowed the rapid change the FPGA code and timely results of new micro-shutter array performance data. As a result, numerous labor hours and money to the project were conserved.

  7. Levitation characteristics of HTS tape stacks

    Energy Technology Data Exchange (ETDEWEB)

    Pokrovskiy, S. V.; Ermolaev, Y. S.; Rudnev, I. A. [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation)

    2015-03-15

    Due to the considerable development of the technology of second generation high-temperature superconductors and a significant improvement in their mechanical and transport properties in the last few years it is possible to use HTS tapes in the magnetic levitation systems. The advantages of tapes on a metal substrate as compared with bulk YBCO material primarily in the strength, and the possibility of optimizing the convenience of manufacturing elements of levitation systems. In the present report presents the results of the magnetic levitation force measurements between the stack of HTS tapes containing of tapes and NdFeB permanent magnet in the FC and ZFC regimes. It was found a non- linear dependence of the levitation force from the height of the array of stack in both modes: linear growth at small thickness gives way to flattening and constant at large number of tapes in the stack. Established that the levitation force of stacks comparable to that of bulk samples. The numerical calculations using finite element method showed that without the screening of the applied field the levitation force of the bulk superconductor and the layered superconductor stack with a critical current of tapes increased by the filling factor is exactly the same, and taking into account the screening force slightly different.

  8. Fungal melanins differ in planar stacking distances.

    Science.gov (United States)

    Casadevall, Arturo; Nakouzi, Antonio; Crippa, Pier R; Eisner, Melvin

    2012-01-01

    Melanins are notoriously difficult to study because they are amorphous, insoluble and often associated with other biological materials. Consequently, there is a dearth of structural techniques to study this enigmatic pigment. Current models of melanin structure envision the stacking of planar structures. X ray diffraction has historically been used to deduce stacking parameters. In this study we used X ray diffraction to analyze melanins derived from Cryptococcus neoformans, Aspergillus niger, Wangiella dermatitides and Coprinus comatus. Analysis of melanin in melanized C. neoformans encapsulated cells was precluded by the fortuitous finding that the capsular polysaccharide had a diffraction spectrum that was similar to that of isolated melanin. The capsular polysaccharide spectrum was dominated by a broad non-Bragg feature consistent with origin from a repeating structural motif that may arise from inter-molecular interactions and/or possibly gel organization. Hence, we isolated melanin from each fungal species and compared diffraction parameters. The results show that the inferred stacking distances of fungal melanins differ from that reported for synthetic melanin and neuromelanin, occupying intermediate position between these other melanins. These results suggest that all melanins have a fundamental diffracting unit composed of planar graphitic assemblies that can differ in stacking distance. The stacking peak appears to be a distinguishing universal feature of melanins that may be of use in characterizing these enigmatic pigments.

  9. Pre-Hardware Optimization of Spacecraft Image Processing Software Algorithms and Hardware Implementation

    Science.gov (United States)

    Kizhner, Semion; Flatley, Thomas P.; Hestnes, Phyllis; Jentoft-Nilsen, Marit; Petrick, David J.; Day, John H. (Technical Monitor)

    2001-01-01

    Spacecraft telemetry rates have steadily increased over the last decade presenting a problem for real-time processing by ground facilities. This paper proposes a solution to a related problem for the Geostationary Operational Environmental Spacecraft (GOES-8) image processing application. Although large super-computer facilities are the obvious heritage solution, they are very costly, making it imperative to seek a feasible alternative engineering solution at a fraction of the cost. The solution is based on a Personal Computer (PC) platform and synergy of optimized software algorithms and re-configurable computing hardware technologies, such as Field Programmable Gate Arrays (FPGA) and Digital Signal Processing (DSP). It has been shown in [1] and [2] that this configuration can provide superior inexpensive performance for a chosen application on the ground station or on-board a spacecraft. However, since this technology is still maturing, intensive pre-hardware steps are necessary to achieve the benefits of hardware implementation. This paper describes these steps for the GOES-8 application, a software project developed using Interactive Data Language (IDL) (Trademark of Research Systems, Inc.) on a Workstation/UNIX platform. The solution involves converting the application to a PC/Windows/RC platform, selected mainly by the availability of low cost, adaptable high-speed RC hardware. In order for the hybrid system to run, the IDL software was modified to account for platform differences. It was interesting to examine the gains and losses in performance on the new platform, as well as unexpected observations before implementing hardware. After substantial pre-hardware optimization steps, the necessity of hardware implementation for bottleneck code in the PC environment became evident and solvable beginning with the methodology described in [1], [2], and implementing a novel methodology for this specific application [6]. The PC-RC interface bandwidth problem for the

  10. Simple model of stacking-fault energies

    DEFF Research Database (Denmark)

    Stokbro, Kurt; Jacobsen, Lærke Wedel

    1993-01-01

    -density calculations of stacking-fault energies, and gives a simple way of understanding the calculated energy contributions from the different atomic layers in the stacking-fault region. The two parameters in the model describe the relative energy contributions of the s and d electrons in the noble and transition......A simple model for the energetics of stacking faults in fcc metals is constructed. The model contains third-nearest-neighbor pairwise interactions and a term involving the fourth moment of the electronic density of states. The model is in excellent agreement with recently published local...... metals, and thereby explain the pronounced differences in energetics in these two classes of metals. The model is discussed in the framework of the effective-medium theory where it is possible to find a functional form for the pair potential and relate the contribution associated with the fourth moment...

  11. High frequency model of stacked film capacitors

    Science.gov (United States)

    Talbert, T.; Joubert, C.; Daude, N.; Glaize, C.

    2001-11-01

    Polypropylene metallized capacitors are of general use in power electronics because of their reliability, their self-healing capabilities, and their low price. Though the behavior of metallized coiled capacitors has been discussed, no work has been carried out on stacked and flattened metallized capacitors. The purpose of this article is to suggest an analytical model of resonance frequency, stray inductance and impedance of stacked capacitors. We first solve the equation of propagation of the magnetic potential vector (A) in the dielectric of an homogeneous material. Then, we suggest an original method of resolution, like the one used for resonant cavities, in order to present an analytical solution of the problem. Finally, we give some experimental results proving that the physical knowledge of the parameters of the capacitor (dimension of the component, and material constants), enables us to calculate an analytical model of resonance frequency, stray inductance and impedance of stacked capacitors.

  12. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    Directory of Open Access Journals (Sweden)

    Wong Weng-Fai

    2011-01-01

    Full Text Available Abstract Advances in technology are making it possible to run three-dimensional (3D graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API, device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC accelerator using transaction-level modeling (TLM. This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  13. Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property

    Science.gov (United States)

    2015-05-22

    hardware intellectual property (PCHIP) framework, which aims to ensure the trustworthiness of third-party hardware IPs utilizing formal methods. We...published in non peer-reviewed journals: Final Report: Trusted Module Acquisition Through Proof-Carrying Hardware Intellectual Property Report Title By...borrowing ideas from the proof carrying code (PCC) in software domain, in this project we introduced the proof carrying hardware intellectual property

  14. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  15. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  16. Study of stacked microstrip phased arrays

    Science.gov (United States)

    Arts, M. J.; Smolders, A. B.

    1993-06-01

    Two theoretical methods for studying stacked-patch microstrip phased arrays are compared: (1) the element-by-element approach (finite array approach) of Pozar (1986) and Smolders (1992); and (2) the infinite approach of Pozar and Shaubert (1984) and Liu et al. (1988). Both theories were found to give almost the same results for a 7 x 7 stacked microstrip antenna, except for edge array elements and for large scan angles. Edge array elements could only be analyzed properly by using a finite array approach. Coupling measurements were made on a 7 x 7 array with a single patch layer, and the results agreed well with calculations.

  17. Geometry and kinematics of experimental antiformal stacks

    Directory of Open Access Journals (Sweden)

    CAROLINE JANETTE SOUZA GOMES

    2000-06-01

    Full Text Available Sandbox experiments with different boundary conditions demonstrate that antiformal stacks result from a forward-breaking thrust sequence. An obstacle blocks forward thrust propagation and transfers the deformation back to the hinterland in a previously formed true duplex. In the hinterland, continued shortening causes faults to merge toward the tectonic transport direction until the older thrusts override the younger thrusts. In experiments using thin sand layers or high basal friction, shortening is accommodated by a cyclic process of thrusting, back rotation of the newly formed thrust combined with strong vertical strain, and nucleation of a new thrust. Continuous deformation produces an antiformal stack through progressive convergence of branch lines.

  18. PACE: A dynamic programming algorithm for hardware/software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic...

  19. CHeCS: International Space Station Medical Hardware Catalog

    Science.gov (United States)

    2008-01-01

    The purpose of this catalog is to provide a detailed description of each piece of hardware in the Crew Health Care System (CHeCS), including subpacks associated with the hardware, and to briefly describe the interfaces between the hardware and the ISS. The primary user of this document is the Space Medicine/Medical Operations ISS Biomedical Flight Controllers (ISS BMEs).

  20. Computer hardware for radiologists: Part 2.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-11-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future.

  1. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  2. Hardware Design of a Smart Meter

    Directory of Open Access Journals (Sweden)

    Ganiyu A. Ajenikoko

    2014-09-01

    Full Text Available Smart meters are electronic measurement devices used by utilities to communicate information for billing customers and operating their electric systems. This paper presents the hardware design of a smart meter. Sensing and circuit protection circuits are included in the design of the smart meter in which resistors are naturally a fundamental part of the electronic design. Smart meters provides a route for energy savings, real-time pricing, automated data collection and eliminating human errors due to manual readings which would ultimately reduce labour costs, diagnosis and instantaneous fault detection. This allows for predictive maintenance resulting in a more efficient and reliable distribution network.

  3. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... to be general enough to be able to capture the characteristics of a wide range of communication protocols and yet to be sufficiently detailed as to allow the designer or design tool to efficiently explore tradeoffs between throughput, bus widths, burst/non-burst transfers and data packing strategies. Thus...

  4. Hardware Accelerated Point Rendering of Isosurfaces

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Christensen, Niels Jørgen

    2003-01-01

    an approximate technique for point scaling using distance attenuation which makes it possible to render points stored in display lists or vertex arrays. This enables us to render points quickly using OpenGL. Our comparisons show that point generation is significantly faster than triangle generation...... and that the advantage of rendering points as opposed to triangles increases with the size and complexity of the volumes. To gauge the visual quality of future hardware accelerated point rendering schemes, we have implemented a software based point rendering method and compare the quality to both MC and our OpenGL based...

  5. Coquet: a Coq library for verifying hardware

    CERN Document Server

    Braibant, Thomas

    2011-01-01

    We propose a new library to model and verify hardware circuits in the Coq proof assistant. This library allows one to easily build circuits by following the usual pen-and-paper diagrams. We define a deep-embedding: we use a (dependently typed) data-type that models the architecture of circuits, and a meaning function. We propose tactics that ease the reasoning about the behavior of the circuits, and we demonstrate that our approach is practicable by proving the correctness of various circuits: a text-book divide and conquer adder of parametric size, some higher-order combinators of circuits, and some sequential circuits: a buffer, and a register.

  6. Exploiting Semiconductor Properties for Hardware Trojans

    CERN Document Server

    Shiyanovskii, Y; Papachristou, C; Weyer, D; Clay, W

    2009-01-01

    This paper discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-based triggers (ESD, Latchup and Softerror). This class of latent damage is difficult to test due to its gradual degradation nature. The paper describes life-time expectancy results for various Trojan induced scenarios. Semiconductor properties, processing and design parameters critical for device reliability and Trojan creation are discussed.

  7. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  8. 从旋回的有序叠加形式到层序的识别和划分:层序地层学进展之三%From vertical stacking pattern of cycles to discerning and division of sequences: The third advance in sequence stratigraphy

    Institute of Scientific and Technical Information of China (English)

    梅冥相

    2011-01-01

    generally form a vertical stacking pattern in the third-order sequence, and this vertically stacking pattern of meter-scale cycle becomes a main marker to study the change of sedimentary trends within the third-order sequence. Importantly, studies on sedimentary cycles that are genetically related to the Milankovitch cycles are grouped into the main content of other stratigraphic discipline, i.e. the cyclostratigraphy. Therefore, if the study on inconsistence of conceptual system for the Exxon sequence stratigraphic model represents the first ad vance, while the research on the forming mechanism of those long-term sequences is the second advance in sequence stratigraphy, the study on the discerning and division on the basis of regular vertical stacking patterns of cycles can delegate the third advance in sequence stratigraphy, which is marked by the mingling of both sequence stratigraphy and cyclostratigraphy.

  9. When is Stacking Confusing?: The Impact of Confusion on Stacking in Deep HI Galaxy Surveys

    CERN Document Server

    Jones, Michael G; Giovanelli, Riccardo; Papastergis, Emmanouil

    2015-01-01

    We present an analytic model to predict the HI mass contributed by confused sources to a stacked spectrum in a generic HI survey. Based on the ALFALFA correlation function, this model is in agreement with the estimates of confusion present in stacked Parkes telescope data, and was used to predict how confusion will limit stacking in the deepest SKA-precursor HI surveys. Stacking with LADUMA and DINGO UDEEP data will only be mildly impacted by confusion if their target synthesised beam size of 10 arcsec can be achieved. Any beam size significantly above this will result in stacks that contain a mass in confused sources that is comparable to (or greater than) that which is detectable via stacking, at all redshifts. CHILES' 5 arcsec resolution is more than adequate to prevent confusion influencing stacking of its data, throughout its bandpass range. FAST will be the most impeded by confusion, with HI surveys likely becoming heavily confused much beyond z = 0.1. The largest uncertainties in our model are the reds...

  10. Stacking of SKA data: comparing uv-plane and image-plane stacking

    CERN Document Server

    Knudsen, K K; Vlemmings, W; Conway, J; Marti-Vidal, I

    2015-01-01

    Stacking as a tool for studying objects that are not individually detected is becoming popular even for radio interferometric data, and will be widely used in the SKA era. Stacking is typically done using imaged data rather than directly using the visibilities (the uv-data). We have investigated and developed a novel algorithm to do stacking using the uv-data. We have performed exten- sive simulations comparing to image-stacking, and summarize the results of these simulations. Furthermore, we disuss the implications in light of the vast data volume produced by the SKA. Having access to the uv-stacked data provides a great advantage, as it allows the possibility to properly analyse the result with respect to calibration artifacts as well as source properties such as size. For SKA the main challenge lies in archiving the uv-data. For purposes of robust stacking analysis, it would be strongly desirable to either keep the calibrated uv-data at least in an aver- age form, or implement a stacking queue where stacki...

  11. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  12. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  13. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  14. Hardware-Software Co-Simulation for SOC Functional Verification

    Institute of Scientific and Technical Information of China (English)

    YAN Ying-jian; LIU Ming-ye

    2005-01-01

    A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

  15. OpenStack Object Storage (Swift) essentials

    CERN Document Server

    Kapadia, Amar; Varma, Sreedhar

    2015-01-01

    If you are an IT administrator and you want to enter the world of cloud storage using OpenStack Swift, then this book is ideal for you. Basic knowledge of Linux and server technology is beneficial to get the most out of the book.

  16. OpenStack cloud computing cookbook

    CERN Document Server

    Jackson, Kevin

    2013-01-01

    A Cookbook full of practical and applicable recipes that will enable you to use the full capabilities of OpenStack like never before.This book is aimed at system administrators and technical architects moving from a virtualized environment to cloud environments with familiarity of cloud computing platforms. Knowledge of virtualization and managing linux environments is expected.

  17. Measuring Structural Parameters Through Stacking Galaxy Images

    CERN Document Server

    Li, Yubin; Gu, Qiu-Sheng; Wang, Yi-Peng; Wen, ZhangZheng; Guo, Kexin; An, FangXia

    2016-01-01

    It remains challenging to detect the low surface brightness structures of faint high-z galaxies, which is key to understanding the structural evolution of galaxies. The technique of image stacking allows us to measure the averaged light profile beneath the detection limit and probe the extended structure of a group of galaxies. We carry out simulations to examine the recovery of the averaged surface brightness profile through stacking model HST/ACS images of a set of galaxies as functions of Sersic index (n), effective radius (Re) and axis ratio (AR). The Sersic profile best fitting the radial profile of the stacked image is taken as the recovered profile, in comparison with the intrinsic mean profile of the model galaxies. Our results show that, in general, the structural parameters of the mean profile can be properly determined through stacking, although systematic biases need to be corrected when spreads of Re and AR are counted. We find that Sersic index is slightly overestimated and Re is underestimated ...

  18. 40 CFR 61.33 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.33 Section 61.33 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... sampling. (a) Unless a waiver of emission testing is obtained under § 61.13, each owner or...

  19. 40 CFR 61.53 - Stack sampling.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 8 2010-07-01 2010-07-01 false Stack sampling. 61.53 Section 61.53 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED) NATIONAL... sampling. (a) Mercury ore processing facility. (1) Unless a waiver of emission testing is obtained...

  20. Flux interactions on stacked Josephson junctions

    DEFF Research Database (Denmark)

    Scott, Alwyn C.; A., Petraglia

    1996-01-01

    Perturbation methods are used to study the dynamics of locked fluxon modes on stacked Josephson junctions and single crystals of certain high-T-c, superconductors. Two limiting cases are considered: (i) The nonlinear diffusion regime in which fluxon dynamics are dominated by energy exchange betwe...

  1. Average Transmission Probability of a Random Stack

    Science.gov (United States)

    Lu, Yin; Miniatura, Christian; Englert, Berthold-Georg

    2010-01-01

    The transmission through a stack of identical slabs that are separated by gaps with random widths is usually treated by calculating the average of the logarithm of the transmission probability. We show how to calculate the average of the transmission probability itself with the aid of a recurrence relation and derive analytical upper and lower…

  2. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    Directory of Open Access Journals (Sweden)

    Cancare Fabio

    2009-07-01

    Full Text Available Abstract Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs have more memory bandwidth and computational capability than Central Processing Units (CPUs and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective

  3. Movable Ground Based Recovery System for Reuseable Space Flight Hardware

    Science.gov (United States)

    Sarver, George L. (Inventor)

    2013-01-01

    A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

  4. Measurement of heat conduction through stacked screens.

    Science.gov (United States)

    Lewis, M A; Kuriyama, T; Kuriyama, F; Radebaugh, R

    1998-01-01

    This paper describes the experimental apparatus for the measurement of heat conduction through stacked screens as well as some experimental results taken with the apparatus. Screens are stacked in a fiberglass-epoxy cylinder, which is 24.4 mm in diameter and 55 mm in length. The cold end of the stacked screens is cooled by a Gifford-McMahon (GM) cryocooler at cryogenic temperature, and the hot end is maintained at room temperature. Heat conduction through the screens is determined from the temperature gradient in a calibrated heat flow sensor mounted between the cold end of the stacked screens and the GM cryocooler. The samples used for these experiments consisted of 400-mesh stainless steel screens, 400-mesh phosphor bronze screens, and two different porosities of 325-mesh stainless steel screens. The wire diameter of the 400-mesh stainless steel and phosphor bronze screens was 25.4 micrometers and the 325-mesh stainless steel screen wire diameters were 22.9 micrometers and 27.9 micrometers. Standard porosity values were used for the experimental data with additional porosity values used on selected experiments. The experimental results showed that the helium gas between each screen enhanced the heat conduction through the stacked screens by several orders of magnitude compared to that in vacuum. The conduction degradation factor is the ratio of actual heat conduction to the heat conduction where the regenerator material is assumed to be a solid rod of the same cross sectional area as the metal fraction of the screen. This factor was about 0.1 for the stainless steel and 0.022 for the phosphor bronze, and almost constant for the temperature range of 40 to 80 K at the cold end.

  5. Optimized electrode configuration for current-in-plane characterization of magnetic tunnel junction stacks

    Science.gov (United States)

    Cagliani, A.; Kjær, D.; Østerberg, F. W.; Hansen, O.; Nielsen, P. F.; Petersen, D. H.

    2017-02-01

    The current-in-plane tunneling technique (CIPT) has been a crucial tool in the development of magnetic tunnel junction stacks suitable for magnetic random access memories (MRAM) for more than a decade. The MRAM development has now reached the maturity to make the transition from the R&D phase to the pilot production phase. This will require an improvement in the repeatability of the CIPT metrology technique. Here, we present an analytical model that can be used to simulate numerically the repeatability of a CIPT measurement for an arbitrary MTJ stack prior to any CIPT measurement. The model describes mathematically the main sources of error arising when a micro multi-electrode probe is used to perform a CIPT measurement. The numerically simulated repeatability values obtained on four different MTJ stacks are verified by experimental data and the model is used to optimize the choice of electrodes on a multi-electrode probe to reach up to 36% improvement on the repeatability for the resistance area product and the tunneling magnetoresistance measurement, without any hardware modification.

  6. Pi-Stack Engineering of Semiconducting Perylene Tetracarboxylic Derivatives

    Science.gov (United States)

    Xue, Chenming

    D crystalline intra-layer order. Chapter 4, PDI pi-stacking order has been engineered in the crystalline phase. By introducing two structuring factors, a series of crystalline PDIs with finely tunable PDI pi-stacking order was obtained. The crystalline PDIs with exceptionally red-shifted lambda max were obtained. Several PDIs possess lambdamax values greater than any literature-reported ones. These materials can be excellent candidates in solar cell devices. In Chapter 5, new chiral main-chain PDI containing polymers were synthesized. These polymers can form intramolecular helical pi-stacks in diluted solutions. In Chapter 6, a novel synthetic route leading to unsymmetrical perylene tetracarboxylic derivatives has been developed. Based on this synthetic method, more perylene tetracarboxylic derivatives can be generated. In my research in this thesis, not only synthesis is an important part because it provides novel materials, but the characterization is critical as well. Infrared spectroscopy, Ultra-violet, fluorescence, differential scanning calorimetry, circular dichroism, polarized light microscopy, gel permeation chromatography, X-ray diffraction including both small angle and wide angle have been used. Additionally, molecular simulation is also very useful in design and obtaining details in molecular packing. Overall, the achievements in this research contribute a considerable advance in the field of generating semiconducting perylene tetracarboxylic derivatives which have versatile potential applications such as in solar cell devices, organic field effect transistors and light emitting diodes.

  7. Fast and dynamic generation of linear octrees for geological bodies under hardware acceleration

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    In the application of 3D Geoscience Modeling,we often need to generate the volumetric representations of geological bodies from their surface representations.Linear octree,as an efficient and easily operated volumetric model,is widely used in 3D Geoscience Modeling.This paper proposes an algorithm for fast and dynamic generation of linear octrees of geological bodies from their surface models under hardware acceleration.The Z-buffers are used to determine the attributes of octants and voxels in a fast way,and a divide-and-conquer strategy is adopted.A stack structure is exploited to record the subdivision,which allows generating linear octrees dynamically.The algorithm avoids large-scale sorting process and bypasses the compression in linear octrees generation.Experimental results indicate its high efficiency in generating linear octrees for large-scale geologic bodies.

  8. Recent advances in direct methanol fuel cells at Los Alamos National Laboratory

    Science.gov (United States)

    Ren, Xiaoming; Zelenay, Piotr; Thomas, Sharon; Davey, John; Gottesfeld, Shimshon

    This paper describes recent advances in the science and technology of direct methanol fuel cells (DMFCs) made at Los Alamos National Laboratory (LANL). The effort on DMFCs at LANL includes work devoted to portable power applications, funded by the Defense Advanced Research Project Agency (DARPA), and work devoted to potential transport applications, funded by the US DOE. We describe recent results with a new type of DMFC stack hardware that allows to lower the pitch per cell to 2 mm while allowing low air flow and air pressure drops. Such stack technology lends itself to both portable power and potential transport applications. Power densities of 300 W/l and 1 kW/l seem achievable under conditions applicable to portable power and transport applications, respectively. DMFC power system analysis based on the performance of this stack, under conditions applying to transport applications (joint effort with U.C. Davis), has shown that, in terms of overall system efficiency and system packaging requirements, a power source for a passenger vehicle based on a DMFC could compete favorably with a hydrogen-fueled fuel cell system, as well as with fuel cell systems based on fuel processing on board. As part of more fundamental studies performed, we describe optimization of anode catalyst layers in terms of PtRu catalyst nature, loading and catalyst layer composition and structure. We specifically show that, optimized content of recast ionic conductor added to the catalyst layer is a sensitive function of the nature of the catalyst. Other elements of membrane/electrode assembly (MEA) optimization efforts are also described, highlighting our ability to resolve, to a large degree, a well-documented problem of polymer electrolyte DMFCs, namely "methanol crossover". This was achieved by appropriate cell design, enabling fuel utilization as high as 90% in highly performing DMFCs.

  9. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  10. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S-H

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  11. Current conveyors variants, applications and hardware implementations

    CERN Document Server

    Senani, Raj; Singh, A K

    2015-01-01

    This book serves as a single-source reference to Current Conveyors and their use in modern Analog Circuit Design. The authors describe the various types of current conveyors discovered over the past 45 years, details of all currently available, off-the-shelf integrated circuit current conveyors, and implementations of current conveyors using other, off-the-shelf IC building blocks. Coverage includes prominent bipolar/CMOS/Bi-CMOS architectures of current conveyors, as well as all varieties of starting from third generation current conveyors to universal current conveyors, their implementations and applications. •Describes all commercially available off-the-shelf IC current conveyors, as well as hardware implementations of current conveyors using other off-the-shelf ICs; • Describes numerous variants of current conveyors evolved over the past forty five years; • Describes a number of Bipolar/CMOS/Bi-CMOS architectures of current conveyors, along with their characteristic features; • Includes a comprehe...

  12. Enabling Technologies for Improved Data Management: Hardware

    Directory of Open Access Journals (Sweden)

    Kerstin van Dam-Kleese

    2001-01-01

    Full Text Available The most valuable assets in every scientific community are the expert work force and the research results/data produced. The last decade has seen new experimental and computational techniques developing at an ever-faster pace, encouraging the production of ever-larger quantities of data in ever-shorter time spans. Concurrently the traditional scientific working environment has changed beyond recognition. Today scientists can use a wide spectrum of experimental, computational and analytical facilities, often widely distributed over the UK and Europe. In this environment new challenges are posed for the Management of Data every day, but are we ready to tackle them? Do we know exactly what the challenges are? Is the right technology available and is it applied where necessary? This part of enabling technologies investigates current hardware techniques and their functionalities and provides a comparison between various products.

  13. Extensible Hardware Architecture for Mobile Robots

    Science.gov (United States)

    Park, Eric; Kobayashi, Linda; Lee, Susan Y.

    2005-01-01

    The Intelligent Robotics Group at NASA Ames Research Center has developed a new mobile robot hardware architecture designed for extensibility and reconfigurability. Currently implemented on the k9 rover. and won to be integrated onto the K10 series of human-robot collaboration research robots, this architecture allows for rapid changes in instrumentation configuration and provides a high degree of modularity through a synergistic mix of off-the-shelf and custom designed components, allowing eased transplantation into a wide vane6 of mobile robot platforms. A component level overview of this architecture is presented along with a description of the changes required for implementation on K10 , followed by plans for future work.

  14. Rendering Falling Leaves on Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Marcos Balsa

    2008-04-01

    Full Text Available There is a growing interest in simulating natural phenomena in computer graphics applications. Animating natural scenes in real time is one of the most challenging problems due to the inherent complexity of their structure, formed by millions of geometric entities, and the interactions that happen within. An example of natural scenario that is needed for games or simulation programs are forests. Forests are difficult to render because the huge amount of geometric entities and the large amount of detail to be represented. Moreover, the interactions between the objects (grass, leaves and external forces such as wind are complex to model. In this paper we concentrate in the rendering of falling leaves at low cost. We present a technique that exploits graphics hardware in order to render thousands of leaves with different falling paths in real time and low memory requirements.

  15. Hardware implementation of stochastic spiking neural networks.

    Science.gov (United States)

    Rosselló, Josep L; Canals, Vincent; Morro, Antoni; Oliver, Antoni

    2012-08-01

    Spiking Neural Networks, the last generation of Artificial Neural Networks, are characterized by its bio-inspired nature and by a higher computational capacity with respect to other neural models. In real biological neurons, stochastic processes represent an important mechanism of neural behavior and are responsible of its special arithmetic capabilities. In this work we present a simple hardware implementation of spiking neurons that considers this probabilistic nature. The advantage of the proposed implementation is that it is fully digital and therefore can be massively implemented in Field Programmable Gate Arrays. The high computational capabilities of the proposed model are demonstrated by the study of both feed-forward and recurrent networks that are able to implement high-speed signal filtering and to solve complex systems of linear equations.

  16. Proximal migration of hardware in patients undergoing midcarpal fusion with headless compression screws.

    Science.gov (United States)

    Shifflett, Grant D; Athanasian, Edward A; Lee, Steve K; Weiland, Andrew J; Wolfe, Scott W

    2014-11-01

    Background Scaphoid excision and limited intercarpal fusion is a common surgical procedure performed for degenerative disorders of the wrist including scapholunate advanced collapse (SLAC) and scaphoid nonunion advanced collapse (SNAC) wrist deformities. Postoperative screw migration is a rare but devastating complication that can result in severe degenerative changes in the radiocarpal joint. Questions/Purposes The purpose of this study is to report on a series of patients who developed proximal migration of their hardware following limited intercarpal fusions with headless compression screws. Patients and Methods Four patients were identified between 2001 and 2012 who were indicated for and underwent scaphoid excision and midcarpal fusions with headless compression screw fixation and subsequently developed hardware migration with screw protrusion into the radiocarpal joint. Detailed chart review was performed. Results Mean age at surgery was 64 years (57-69 years). All patients had the diagnosis of SLAC wrist. Mean time to detection of failure was 6 months (4-8 months). All patients demonstrated radiographic union prior to failure based on plain films. Radiographs revealed screw backout with erosion of the radial lunate facet in all patients. Calculated carpal height ratios demonstrated a drop from an average 44.2% to 39.5% at the time of hardware migration. All four patients underwent hardware removal. One patient was not indicated for any further surgery, and two patients underwent further revision surgery. All three patients reported complete pain relief. One patient refused a salvage procedure and had subsequent persistent pain. Conclusions This study reports a serious complication of scaphoid excision and midcarpal fusion performed with headless compression screws. We advise surgeons to be aware of this potential complication and consider employing methods to reduce the risk of hardware migration. Additionally, we recommend at least 8 months of

  17. Project W-420 Stack Monitoring system upgrades conceptual design report

    Energy Technology Data Exchange (ETDEWEB)

    TUCK, J.A.

    1998-11-06

    This document describes the scope, justification, conceptual design, and performance of Project W-420 stack monitoring system upgrades on six NESHAP-designated, Hanford Tank Farms ventilation exhaust stacks.

  18. Stacking for machine learning redshifts applied to SDSS galaxies

    OpenAIRE

    Zitlau, Roman; Hoyle, Ben; Paech, Kerstin; Weller, Jochen; Rau, Markus Michael; Seitz, Stella

    2016-01-01

    We present an analysis of a general machine learning technique called 'stacking' for the estimation of photometric redshifts. Stacking techniques can feed the photometric redshift estimate, as output by a base algorithm, back into the same algorithm as an additional input feature in a subsequent learning round. We shown how all tested base algorithms benefit from at least one additional stacking round (or layer). To demonstrate the benefit of stacking, we apply the method to both unsupervised...

  19. Luminescence associated with stacking faults in GaN

    OpenAIRE

    Lähnemann, Jonas; Jahn, Uwe; Brandt, Oliver; Flissikowski, Timur; Dogan, Pinar; Grahn, Holger T.

    2014-01-01

    Basal-plane stacking faults are an important class of optically active structural defects in wurtzite semiconductors. The local deviation from the 2H stacking of the wurtzite matrix to a 3C zinc-blende stacking induces a bound state in the gap of the host crystal, resulting in the localization of excitons. Due to the two-dimensional nature of these planar defects, stacking faults act as quantum wells, giving rise to radiative transitions of excitons with characteristic energies. Luminescence ...

  20. Stacking from Tags: Clustering Bookmarks around a Theme

    OpenAIRE

    Zubiaga, Arkaitz; García-Plaza, Alberto Pérez; Fresno, Víctor; Martínez, Raquel

    2013-01-01

    Since very recently, users on the social bookmarking service Delicious can stack web pages in addition to tagging them. Stacking enables users to group web pages around specific themes with the aim of recommending to others. However, users still stack a small subset of what they tag, and thus many web pages remain unstacked. This paper presents early research towards automatically clustering web pages from tags to find stacks and extend recommendations.

  1. DEVS Models of Palletized Ground Stacking in Storeyed Grain Warehouse

    Directory of Open Access Journals (Sweden)

    Hou Shu-Yi

    2016-01-01

    Full Text Available Processed grain stored in storeyed warehouse is generally stacked on the ground without pallets. However, in order to improve the storing way, we developed a new stacking method, palletized ground stacking. Simulation should be used to present this new storing way. DEVS provides a formalized way to describe the system model. In this paper, DEVS models of palletized ground stacking in storeyed grain warehouse are given and a simulation model is developed by AutoMod.

  2. The first self-sustainable microbial fuel cell stack.

    Science.gov (United States)

    Ledezma, Pablo; Stinchcombe, Andrew; Greenman, John; Ieropoulos, Ioannis

    2013-02-21

    This study reports for the first time on the development of a self-sustainable microbial fuel cell stack capable of self-maintenance (feeding, hydration, sensing & reporting). Furthermore, the stack system is producing excess energy, which can be used for improved functionality. The self-maintenance is performed by the stack powering single and multi-channel peristaltic pumps.

  3. Dynamic Model of High Temperature PEM Fuel Cell Stack Temperature

    DEFF Research Database (Denmark)

    Andreasen, Søren Juhl; Kær, Søren Knudsen

    2007-01-01

    cathode air cooled 30 cell HTPEM fuel cell stack developed at the Institute of Energy Technology at Aalborg University. This fuel cell stack uses PEMEAS Celtec P-1000 membranes, runs on pure hydrogen in a dead end anode configuration with a purge valve. The cooling of the stack is managed by running...

  4. Spectral Analysis using Linearly Chirped Gaussian Pulse Stacking

    Institute of Scientific and Technical Information of China (English)

    ZHENG Huan; WANG An-Ting; XU Li-Xin; MING Hai

    2009-01-01

    We analyze the spectrum of a stacked pulse with the technique of linearly chirped Gaussian pulse stacking.Our results show that there are modulation structures in the spectrum of the stacked pulse. The modulation frequencies are discussed in detail. By applying spectral analysis, we find that the intensity fluctuation cannot be smoothed by introducing an optical amplitude filter.

  5. High power collimated diode laser stack

    Institute of Scientific and Technical Information of China (English)

    LIU Yuan-yuan; FANG Gao-zhan; MA Xiao-yu; LIU Su-ping; FENG Xiao-ming

    2006-01-01

    A high power collimated diode laser stack is carried out based on fast-axis collimation and stack packaging techniques.The module includes ten typical continuous wave (cw) bars and the total output power can be up to 368W at 48.6A.Using a cylindrical lens as the collimation elements,we can make the fast-axis divergence and the slow-axis divergence are 0.926 40 and 8.2060 respectively.The light emitting area is limited in a square area of 18.3 mm×11 mm.The module has the advantage of high power density and offers a wide potential applications in pumping and material processing.

  6. Fluxon dynamics in three stacked Josephson junctions

    DEFF Research Database (Denmark)

    Gorria, Carlos; Christiansen, Peter Leth; Gaididei, Yuri Borisovich;

    2002-01-01

    /sub -/, the coupling between junctions leads to a repulsion of the fluxons with the same polarity. Above this critical velocity a fluxon will induce radiation in the neighboring junctions, leading to a bunching of the fluxons in the stacked junctions. Using the Sakai-Bodin-Pedersen model, three coupled perturbed sine......The motion of fluxons of the same polarity in three vertically stacked Josephson junctions is studied. In this configuration the difference between exterior and interior junctions plays a more important role than in other configurations with several interior junctions. Below the Swihart velocity c......-Gordon equations are numerically studied for different values of coupling, damping, and bias parameters. In a narrow range of velocities bunching occurs. Outside this interval the fluxons split and new fluxons may be created. I-V characteristics are presented...

  7. Absorption spectra of AA-stacked graphite

    Energy Technology Data Exchange (ETDEWEB)

    Chiu, C W; Lee, S H; Chen, S C; Lin, M F [Department of Physics, National Cheng Kung University, Taiwan (China); Shyu, F L, E-mail: fl.shyu@msa.hinet.ne, E-mail: mflin@mail.ncku.edu.t [Department of Physics, ROC Military Academy, 830 Kaohsiung, Taiwan (China)

    2010-08-15

    AA-stacked graphite shows strong anisotropy in geometric structures and velocity matrix elements. However, the absorption spectra are isotropic for the polarization vector on the graphene plane. The spectra exhibit one prominent plateau at middle energy and one shoulder structure at lower energy. These structures directly reflect the unique geometric and band structures and provide sufficient information for experimental fitting of the intralayer and interlayer atomic interactions. On the other hand, monolayer graphene shows a sharp absorption peak but no shoulder structure; AA-stacked bilayer graphene has two absorption peaks at middle energy and abruptly vanishes at lower energy. Furthermore, the isotropic features are expected to exist in other graphene-related systems. The calculated results and the predicted atomic interactions could be verified by optical measurements.

  8. Text-Filled Stacked Area Graphs

    DEFF Research Database (Denmark)

    Kraus, Martin

    2011-01-01

    Text can add a significant amount of detail and value to an information visualization. In particular, it can integrate more of the data that a visualization is based on, and it can also integrate information that is personally relevant to readers of a visualization. This may influence readers...... to consider a visualization a detailed enrichment of their personal experience instead of an abstract representation of anonymous numbers. However, the integration of textual detail into a visualization is often very challenging. This work discusses one particular approach to this problem, namely text......-filled stacked area graphs; i.e., graphs that feature stacked areas that are filled with small-typed text. Since these graphs allow for computing the text layout automatically, it is possible to include large amounts of textual detail with very little effort. We discuss the most important challenges and some...

  9. Multistage Force Amplification of Piezoelectric Stacks

    Science.gov (United States)

    Xu, Tian-Bing (Inventor); Siochi, Emilie J. (Inventor); Zuo, Lei (Inventor); Jiang, Xiaoning (Inventor); Kang, Jin Ho (Inventor)

    2015-01-01

    Embodiments of the disclosure include an apparatus and methods for using a piezoelectric device, that includes an outer flextensional casing, a first cell and a last cell serially coupled to each other and coupled to the outer flextensional casing such that each cell having a flextensional cell structure and each cell receives an input force and provides an output force that is amplified based on the input force. The apparatus further includes a piezoelectric stack coupled to each cell such that the piezoelectric stack of each cell provides piezoelectric energy based on the output force for each cell. Further, the last cell receives an input force that is the output force from the first cell and the last cell provides an output apparatus force In addition, the piezoelectric energy harvested is based on the output apparatus force. Moreover, the apparatus provides displacement based on the output apparatus force.

  10. Process for 3D chip stacking

    Science.gov (United States)

    Malba, Vincent

    1998-01-01

    A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

  11. Industrial stacks design; Diseno de chimeneas industriales

    Energy Technology Data Exchange (ETDEWEB)

    Cacheux, Luis [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1986-12-31

    The Instituto de Investigaciones Electricas (IIE) though its Civil Works Department, develops, under contract with CFE`s Gerencia de Proyectos Termoelectricos (Management of Fossil Power Plant Projects), a series of methods for the design of stacks, which pretends to solve the a present day problem: the stack design of the fossil power plants that will go into operation during the next coming years in the country. [Espanol] El Instituto de Investigaciones Electricas (IIE), a traves del Departamento de Ingenieria Civil, desarrolla, bajo contrato con la Gerencia de Proyectos Termoelectricos, de la Comision Federal de Electricidad (CFE), un conjunto de metodos para el diseno de chimeneas, con el que se pretende resolver un problema inmediato: el diseno de las chimeneas de las centrales termoelectricas que entraran en operacion durante los proximos anos, en el pais.

  12. Development of on-site PAFC stacks

    Energy Technology Data Exchange (ETDEWEB)

    Hotta, K.; Matsumoto, Y. [Kansai Electric Power Co., Amagasaki (Japan); Horiuchi, H.; Ohtani, T. [Mitsubishi Electric Corp., Kobe (Japan)

    1996-12-31

    PAFC (Phosphoric Acid Fuel Cell) has been researched for commercial use and demonstration plants have been installed in various sites. However, PAFC don`t have a enough stability yet, so more research and development must be required in the future. Especially, cell stack needs a proper state of three phases (liquid, gas and solid) interface. It is very difficult technology to keep this condition for a long time. In the small size cell with the electrode area of 100 cm{sup 2}, gas flow and temperature distributions show uniformity. But in the large size cell with the electrode area of 4000 cm{sup 2}, the temperature distributions show non-uniformity. These distributions would cause to be shorten the cell life. Because these distributions make hot-spot and gas poverty in limited parts. So we inserted thermocouples in short-stack for measuring three-dimensional temperature distributions and observed effects of current density and gas utilization on temperature.

  13. Process for 3D chip stacking

    Science.gov (United States)

    Malba, V.

    1998-11-10

    A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: (1) holding individual chips for batch processing, (2) depositing a dielectric passivation layer on the top and sidewalls of the chips, (3) opening vias in the dielectric, (4) forming the interconnects by laser pantography, and (5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume. 3 figs.

  14. Angular resolution of stacked resistive plate chambers

    CERN Document Server

    Samuel, Deepak; Murgod, Lakshmi P

    2016-01-01

    We present here detailed derivations of mathematical expressions for the angular resolution of a set of stacked resistive plate chambers (RPCs). The expressions are validated against experimental results using data collected from the prototype detectors (without magnet) of the upcoming India-based Neutrino Observatory (INO). In principle, these expressions can be used for any other detector with an architecture similar to that of RPCs.

  15. The stack induced draft aerial cooler (SIDAC)

    Energy Technology Data Exchange (ETDEWEB)

    Hircock, N.C. [NC Hircock Process Consulting Ltd., Calgary, AB (Canada)]|[Patching Associates Acoustical Engineering Ltd. Calgary, AB (Canada)

    2007-07-01

    The oil and gas industry uses stack induced draft aerial coolers (SIDAC) for process cooling in noise sensitive areas or in areas where no electrical power is available. The technology produces zero noise, zero operating costs and zero emissions. This paper examined the use, operation and economics of fanless, noiseless aerial coolers. Although retrofitting to convert from fin-fan to SIDAC is not viable, this paper illustrated one common application where the installation of a tapered stack over a cooler could work together with variable speed fan drives to enhance the noise suppression achieved by variable speed fan drives. A stack assisted draft air cooler (SADAC) was installed over a conventional engine cooler enclosing the engine exhaust and muffler. The exhaust stack was also acoustically lined to augment the noise suppression of the engine silencer itself. The waste heat of the engine exhaust, combined with the heat from the cooler discharge, was used to create a negative pressure behind the cooler fan. Therefore, at night the fan could back off in speed. Since fan noise is proportional to speed to the exponent 5, even a 20 per cent reduction of fan speed generates a noticeable noise reduction. The noise directive of the Alberta Energy and Utilities Board is for lower noise levels at night rather than daytime. Therefore, this innovation allows plant operators to run coolers at full capacity in the day while backing off fan speed at night. It was concluded that substantial benefits can be achieved by SIDAC and SADAC technology in the areas of noise control, process improvements and emission reductions. The capital costs of using these devices are comparable with conventional systems, and operating costs are reduced.

  16. When is stacking confusing? The impact of confusion on stacking in deep H I galaxy surveys

    Science.gov (United States)

    Jones, Michael G.; Haynes, Martha P.; Giovanelli, Riccardo; Papastergis, Emmanouil

    2016-01-01

    We present an analytic model to predict the H I mass contributed by confused sources to a stacked spectrum in a generic H I survey. Based on the ALFALFA (Arecibo Legacy Fast ALFA) correlation function, this model is in agreement with the estimates of confusion present in stacked Parkes telescope data, and was used to predict how confusion will limit stacking in the deepest Square Kilometre Array precursor H I surveys. Stacking with LADUMA (Looking At the Distant Universe with MeerKAT) and DINGO UDEEP (Deep Investigation of Neutral Gas Origins - Ultra Deep) data will only be mildly impacted by confusion if their target synthesized beam size of 10 arcsec can be achieved. Any beam size significantly above this will result in stacks that contain a mass in confused sources that is comparable to (or greater than) that which is detectable via stacking, at all redshifts. CHILES (COSMOS H I Large Extragalactic Survey) 5 arcsec resolution is more than adequate to prevent confusion influencing stacking of its data, throughout its bandpass range. FAST (Five hundred metre Aperture Spherical Telescope) will be the most impeded by confusion, with H I surveys likely becoming heavily confused much beyond z = 0.1. The largest uncertainties in our model are the redshift evolution of the H I density of the Universe and the H I correlation function. However, we argue that the two idealized cases we adopt should bracket the true evolution, and the qualitative conclusions are unchanged regardless of the model choice. The profile shape of the signal due to confusion (in the absence of any detection) was also modelled, revealing that it can take the form of a double Gaussian with a narrow and wide component.

  17. Thyristor stack for pulsed inductive plasma generation.

    Science.gov (United States)

    Teske, C; Jacoby, J; Schweizer, W; Wiechula, J

    2009-03-01

    A thyristor stack for pulsed inductive plasma generation has been developed and tested. The stack design includes a free wheeling diode assembly for current reversal. Triggering of the device is achieved by a high side biased, self supplied gate driver unit using gating energy derived from a local snubber network. The structure guarantees a hard firing gate pulse for the required high dI/dt application. A single fiber optic command is needed to achieve a simultaneous turn on of the thyristors. The stack assembly is used for switching a series resonant circuit with a ringing frequency of 30 kHz. In the prototype pulsed power system described here an inductive discharge has been generated with a pulse duration of 120 micros and a pulse energy of 50 J. A maximum power transfer efficiency of 84% and a peak power of 480 kW inside the discharge were achieved. System tests were performed with a purely inductive load and an inductively generated plasma acting as a load through transformer action at a voltage level of 4.1 kV, a peak current of 5 kA, and a current switching rate of 1 kA/micros.

  18. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    Science.gov (United States)

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  19. Architectural Support for Detection and Recovery using Hardware Wrappers

    Science.gov (United States)

    2013-04-01

    SECRYPT 2011, Seville, Spain 2011. 5. A. Baumgarten, M. Steffen, M. Clausman, and J. Zambreno. "A Case Study in Hardware Trojan Design and...AFRL-OSR-VA-TR-2013-0204 Architectural Support for Detection and Recovery using Hardware Wrappers Bhagirath Narahari Rahul...Include area code) 02-26-2013 FINAL REPORT March 1, 2009 - Nov 30, 2012 Architectural Support for Detection and Recovery using Hardware Wrappers

  20. Analog Exercise Hardware to Implement a High Intensity Exercise Program During Bed Rest

    Science.gov (United States)

    Loerch, Linda; Newby, Nate; Ploutz-Snyder, Lori

    2012-01-01

    used for leg press and heel raise exercises. Minor modifications were made to the device including adding 200 lbs to the weight stack, raising the frame by 12 inches, making the footplate adjustable, and providing removable handles. Conclusion: A combination of novel and commercial exercise hardware are used to mimic the exercise hardware capabilities aboard the ISS, allowing scientific investigation of new countermeasure protocols in a space flight analog prior to flight validation

  1. 40 CFR 75.72 - Determination of NOX mass emissions for common stack and multiple stack configurations.

    Science.gov (United States)

    2010-07-01

    ... maintain a flow monitoring system and diluent monitor in the duct to the common stack from each unit; or...; (2) Monitor NOX mass emissions at the main stack using a NOX-diluent CEMS and a flow monitoring... chooses to monitor in the ducts rather than in the stack, the owner or operator shall either: (1)...

  2. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  3. Environmental Friendly Coatings and Corrosion Prevention For Flight Hardware Project

    Science.gov (United States)

    Calle, Luz

    2014-01-01

    Identify, test and develop qualification criteria for environmentally friendly corrosion protective coatings and corrosion preventative compounds (CPC's) for flight hardware an ground support equipment.

  4. Hardware/Software Co-design using Primitive Interface

    Directory of Open Access Journals (Sweden)

    Navin Chourasia

    2011-08-01

    Full Text Available Most engineering designs can be viewed as systems, i.e., as collections of several components whose combined operation provides useful services. Components can be heterogeneous in nature and their interaction may be regulated by some simple or complex means. Interface between Hardware & Software plays a very important role in co-design of the embedded system. Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design. This paper shows how hardware & software interfaces can be implemented using primitive interface design

  5. High-Density Stacked Ru Nanocrystals for Nonvolatile Memory Application

    Institute of Scientific and Technical Information of China (English)

    MAO Ping; ZHANG Zhi-Gang; PAN Li-Yang; XU Jun; CHEN Pei-Yi

    2009-01-01

    @@ Stacked ruthenium (Ru) nanocrystals (NCs) are formed by rapid thermal annealing for the whole gate stacks and embedded in memory structure, which is compatible with conventional CMOS technology. Ru NCs with high density (3×1012 cm-2 ), small size (2-4 nm) and good uniformity both in aerial distribution and morphology are formed. Attributed to the higher surface trap density, a memory window of 5.2 V is obtained with stacked Ru NCs in comparison to that of 3.5 V with single-layer samples. The stacked Ru NCs device also exhibits much better retention performance because of Coulomb blockade and vertical uniformity between stacked Ru NCs.

  6. A Fast hardware Tracker for the ATLAS Trigger system

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  7. RF control hardware design for CYCIAE-100 cyclotron

    Energy Technology Data Exchange (ETDEWEB)

    Yin, Zhiguo, E-mail: bitbearAT@hotmail.com; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-21

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  8. Fast Sparse Level Sets on Graphics Hardware.

    Science.gov (United States)

    Jalba, Andrei C; van der Laan, Wladimir J; Roerdink, Jos B T M

    2013-01-01

    The level-set method is one of the most popular techniques for capturing and tracking deformable interfaces. Although level sets have demonstrated great potential in visualization and computer graphics applications, such as surface editing and physically based modeling, their use for interactive simulations has been limited due to the high computational demands involved. In this paper, we address this computational challenge by leveraging the increased computing power of graphics processors, to achieve fast simulations based on level sets. Our efficient, sparse GPU level-set method is substantially faster than other state-of-the-art, parallel approaches on both CPU and GPU hardware. We further investigate its performance through a method for surface reconstruction, based on GPU level sets. Our novel multiresolution method for surface reconstruction from unorganized point clouds compares favorably with recent, existing techniques and other parallel implementations. Finally, we point out that both level-set computations and rendering of level-set surfaces can be performed at interactive rates, even on large volumetric grids. Therefore, many applications based on level sets can benefit from our sparse level-set method.

  9. Live HDR video streaming on commodity hardware

    Science.gov (United States)

    McNamee, Joshua; Hatchett, Jonathan; Debattista, Kurt; Chalmers, Alan

    2015-09-01

    High Dynamic Range (HDR) video provides a step change in viewing experience, for example the ability to clearly see the soccer ball when it is kicked from the shadow of the stadium into sunshine. To achieve the full potential of HDR video, so-called true HDR, it is crucial that all the dynamic range that was captured is delivered to the display device and tone mapping is confined only to the display. Furthermore, to ensure widespread uptake of HDR imaging, it should be low cost and available on commodity hardware. This paper describes an end-to-end HDR pipeline for capturing, encoding and streaming high-definition HDR video in real-time using off-the-shelf components. All the lighting that is captured by HDR-enabled consumer cameras is delivered via the pipeline to any display, including HDR displays and even mobile devices with minimum latency. The system thus provides an integrated HDR video pipeline that includes everything from capture to post-production, archival and storage, compression, transmission, and display.

  10. Hardware upgrade for A2 data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Ostrick, Michael; Gradl, Wolfgang; Otte, Peter-Bernd; Neiser, Andreas; Steffen, Oliver; Wolfes, Martin; Koerner, Tito [Institut fuer Kernphysik, Mainz (Germany); Collaboration: A2-Collaboration

    2014-07-01

    The A2 Collaboration uses an energy tagged photon beam which is produced via bremsstrahlung off the MAMI electron beam. The detector system consists of Crystal Ball and TAPS and covers almost the whole solid angle. A frozen-spin polarized target allows to perform high precision measurements of polarization observables in meson photo-production. During the last summer, a major upgrade of the data acquisition system was performed, both on the hardware and the software side. The goal of this upgrade was increased reliability of the system and an improvement in the data rate to disk. By doubling the number of readout CPUs and employing special VME crates with a split backplane, the number of bus accesses per readout cycle and crate was cut by a factor of two, giving almost a factor of two gain in the readout rate. In the course of the upgrade, we also switched most of the detector control system to using the distributed control system EPICS. For the upgraded control system, some new tools were developed to make full use of the capabilities of this decentralised slow control and monitoring system. The poster presents some of the major contributions to this project.

  11. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  12. Mechanical Design and Development of TES Bolometer Detector Arrays for the Advanced ACTPol Experiment

    Science.gov (United States)

    Ward, Jonathan T.; Austermann, Jason; Beall, James A.; Choi, Steve K.; Crowley, Kevin T.; Devlin, Mark J.; Duff, Shannon M.; Gallardo, Patricio M.; Henderson, Shawn W.; Ho, Shuay-Pwu Patty; Hilton, Gene; Hubmayr, Johannes; Khavari, Niloufar; Klein, Jeffrey; Koopman, Brian J.; Li, Dale; McMahon, Jeffrey; Mumby, Grace; Nati, Federico; Wollack, Edward J.

    2016-01-01

    The next generation Advanced ACTPol (AdvACT) experiment is currently underway and will consist of four Transition Edge Sensor (TES) bolometer arrays, with three operating together, totaling 5800 detectors on the sky. Building on experience gained with the ACTPol detector arrays, AdvACT will utilize various new technologies, including 150 mm detector wafers equipped with multichroic pixels, allowing for a more densely packed focal plane. Each set of detectors includes a feedhorn array of stacked silicon wafers which form a spline pro le leading to each pixel. This is then followed by a waveguide interface plate, detector wafer, back short cavity plate, and backshort cap. Each array is housed in a custom designed structure manufactured from high purity copper and then gold plated. In addition to the detector array assembly, the array package also encloses cryogenic readout electronics. We present the full mechanical design of the AdvACT high frequency (HF) detector array package along with a detailed look at the detector array stack assemblies. This experiment will also make use of extensive hardware and software previously developed for ACT, which will be modi ed to incorporate the new AdvACT instruments. Therefore, we discuss the integration of all AdvACT arrays with pre-existing ACTPol infrastructure.

  13. Spectroscopic Signature of Stacking Disorder in Ice I.

    Science.gov (United States)

    Carr, Thomas H G; Shephard, Jacob J; Salzmann, Christoph G

    2014-07-17

    There is a growing realization that the presence of stacking disorder in ice I strongly influences its physical and chemical properties. Using Raman spectroscopy, we gain new fundamental insights into the spectroscopic properties of ice. We show that stacking disorder can be detected and quantified by comparing the spectra of stacking disordered ice with spectra of the "ordinary" hexagonal ice Ih. The spectral signature of stacking disorder is thought to arise from a greater structural diversity on the local length scale, vibrational modes that appear due to the lower-symmetry environments, and a strengthening of the covalent bonds. Our findings are compared to results from diffraction and calorimetry, and we discuss the advantages and disadvantages of the three techniques with respect to detecting stacking disorder in ice I. Apart from characterizing stacking disordered ice in the research lab, our new method is perfectly suited for remote or telescopic applications aiming at the identification of stacking disordered ice in nature.

  14. Horizontal high speed stacking for batteries with prismatic cans

    Energy Technology Data Exchange (ETDEWEB)

    Bartos, Andrew L.; Lin, Yhu-Tin; Turner, III, Raymond D.

    2016-06-14

    A system and method for stacking battery cells or related assembled components. Generally planar, rectangular (prismatic-shaped) battery cells are moved from an as-received generally vertical stacking orientation to a generally horizontal stacking orientation without the need for robotic pick-and-place equipment. The system includes numerous conveyor belts that work in cooperation with one another to deliver, rotate and stack the cells or their affiliated assemblies. The belts are outfitted with components to facilitate the cell transport and rotation. The coordinated movement between the belts and the components promote the orderly transport and rotation of the cells from a substantially vertical stacking orientation into a substantially horizontal stacking orientation. The approach of the present invention helps keep the stacked assemblies stable so that subsequent assembly steps--such as compressing the cells or attaching electrical leads or thermal management components--may proceed with a reduced chance of error.

  15. Influence of stacking fault energy on friction of nanotwinned metals

    Science.gov (United States)

    Zhang, J. J.; Wang, Z. F.; Sun, T.; Yan, Y. D.

    2016-12-01

    The unique dislocation-twin boundary (TB) interactions that govern the extraordinary mechanical properties of nanotwinned (NT) metals have the strong intrinsic effect of material energy and the extrinsic effect of feature size. In this work, we perform molecular dynamics (MD) simulations to elucidate fundamental deformation mechanisms of two NT face-centered cubic (FCC) metals (Cu and Pd) under probe-based friction, with an emphasis on evaluating the influence of both material’s intrinsic energy barrier and extrinsic grain size on the microscopic deformation behavior and correlated macroscopic frictional results of the materials. Simulation results reveal that individual deformation modes of dislocation mechanisms, dislocation-TB interactions, TB-associated mechanisms, deformation twinning and grain boundary (GB) accommodation work in parallel in the plastic deformation of the materials, and their competition is strongly influenced by both the intrinsic energy barriers for the nucleation of stacking faults and twin faults, and the extrinsic grain size. Consequently, both the frictional response and worn surface morphology present strong anisotropic characteristics. It is also found that the deformation behavior of NT Pd under a localized multi-axis stress state is significantly different from that which occurs under a uniaxial stress state. These findings will advance the rational design and synthesis of nanostructured materials with advanced frictional properties.

  16. Ultrasound and clinical evaluation of soft-tissue versus hardware biceps tenodesis: is hardware tenodesis worth the cost?

    Science.gov (United States)

    Elkousy, Hussein; Romero, Jose A; Edwards, T Bradley; Gartsman, Gary M; O'Connor, Daniel P

    2014-02-01

    This study assesses the failure rate of soft-tissue versus hardware fixation of biceps tenodesis by ultrasound to determine if the expense of a hardware tenodesis technique is warranted. Seventy-two patients that underwent arthroscopic biceps tenodesis over a 3-year period were evaluated using postoperative ultrasonography and clinical examination. The tenodesis technique employed was either a soft-tissue technique with sutures or an interference screw technique using hardware based on surgeon preference. Patient age was 57.9 years on average with ultrasound and clinical examination done at an average of 9.3 months postoperatively. Thirty-one patients had a hardware technique and 41 a soft-tissue technique. Overall, 67.7% of biceps tenodesis done with hardware were intact, compared with 75.6% for the soft-tissue technique by ultrasound (P = .46). Clinical evaluation indicated that 80.7% of hardware techniques and 78% of soft-tissue techniques were intact. Average material cost to the hospital for the hardware technique was $514.32, compared with $32.05 for the soft-tissue technique. Biceps tenodesis success, as determined by clinical deformity and ultrasound, was not improved using hardware as compared to soft-tissue techniques. Soft-tissue techniques are equally efficacious and more cost effective than hardware techniques.

  17. Dynamic model of a micro-tubular solid oxide fuel cell stack including an integrated cooling system

    Science.gov (United States)

    Hering, Martin; Brouwer, Jacob; Winkler, Wolfgang

    2017-02-01

    A novel dynamic micro-tubular solid oxide fuel cell (MT-SOFC) and stack model including an integrated cooling system is developed using a quasi three-dimensional, spatially resolved, transient thermodynamic, physical and electrochemical model that accounts for the complex geometrical relations between the cells and cooling-tubes. The modeling approach includes a simplified tubular geometry and stack design including an integrated cooling structure, detailed pressure drop and gas property calculations, the electrical and physical constraints of the stack design that determine the current, as well as control strategies for the temperature. Moreover, an advanced heat transfer balance with detailed radiative heat transfer between the cells and the integrated cooling-tubes, convective heat transfer between the gas flows and the surrounding structures and conductive heat transfer between the solid structures inside of the stack, is included. The detailed model can be used as a design basis for the novel MT-SOFC stack assembly including an integrated cooling system, as well as for the development of a dynamic system control strategy. The evaluated best-case design achieves very high electrical efficiency between around 75 and 55% in the entire power density range between 50 and 550 mW /cm2 due to the novel stack design comprising an integrated cooling structure.

  18. FocusStack and StimServer: a new open source MATLAB toolchain for visual stimulation and analysis of two-photon calcium neuronal imaging data.

    Science.gov (United States)

    Muir, Dylan R; Kampa, Björn M

    2014-01-01

    Two-photon calcium imaging of neuronal responses is an increasingly accessible technology for probing population responses in cortex at single cell resolution, and with reasonable and improving temporal resolution. However, analysis of two-photon data is usually performed using ad-hoc solutions. To date, no publicly available software exists for straightforward analysis of stimulus-triggered two-photon imaging experiments. In addition, the increasing data rates of two-photon acquisition systems imply increasing cost of computing hardware required for in-memory analysis. Here we present a Matlab toolbox, FocusStack, for simple and efficient analysis of two-photon calcium imaging stacks on consumer-level hardware, with minimal memory footprint. We also present a Matlab toolbox, StimServer, for generation and sequencing of visual stimuli, designed to be triggered over a network link from a two-photon acquisition system. FocusStack is compatible out of the box with several existing two-photon acquisition systems, and is simple to adapt to arbitrary binary file formats. Analysis tools such as stack alignment for movement correction, automated cell detection and peri-stimulus time histograms are already provided, and further tools can be easily incorporated. Both packages are available as publicly-accessible source-code repositories.

  19. FocusStack and StimServer: A new open source MATLAB toolchain for visual stimulation and analysis of two-photon calcium neuronal imaging data

    Directory of Open Access Journals (Sweden)

    Dylan Richard Muir

    2015-01-01

    Full Text Available Two-photon calcium imaging of neuronal responses is an increasingly accessible technology for probing population responses in cortex at single cell resolution, and with reasonable and improving temporal resolution. However, analysis of two-photon data is usually performed using ad-hoc solutions. To date, no publicly available software exists for straightforward analysis of stimulus-triggered two-photon imaging experiments. In addition, the increasing data rates of two-photon acquisition systems imply increasing cost of computing hardware required for in-memory analysis. Here we present a Matlab toolbox, FocusStack, for simple and efficient analysis of two-photon calcium imaging stacks on consumer-level hardware, with minimal memory footprint. We also present a Matlab toolbox, StimServer, for generation and sequencing of visual stimuli, designed to be triggered over a network link from a two-photon acquisition system. FocusStack is compatible out of the box with several existing two-photon acquisition systems, and is simple to adapt to arbitrary binary file formats. Analysis tools such as stack alignment for movement correction, automated cell detection and peri-stimulus time histograms are already provided, and further tools can be easily incorporated. Both packages are available as publicly-accessible source-code repositories.

  20. Life sciences flight hardware development for the International Space Station

    Science.gov (United States)

    Kern, V. D.; Bhattacharya, S.; Bowman, R. N.; Donovan, F. M.; Elland, C.; Fahlen, T. F.; Girten, B.; Kirven-Brooks, M.; Lagel, K.; Meeker, G. B.; Santos, O.

    During the construction phase of the International Space Station (ISS), early flight opportunities have been identified (including designated Utilization Flights, UF) on which early science experiments may be performed. The focus of NASA's and other agencies' biological studies on the early flight opportunities is cell and molecular biology; with UF-1 scheduled to fly in fall 2001, followed by flights 8A and UF-3. Specific hardware is being developed to verify design concepts, e.g., the Avian Development Facility for incubation of small eggs and the Biomass Production System for plant cultivation. Other hardware concepts will utilize those early research opportunities onboard the ISS, e.g., an Incubator for sample cultivation, the European Modular Cultivation System for research with small plant systems, an Insect Habitat for support of insect species. Following the first Utilization Flights, additional equipment will be transported to the ISS to expand research opportunities and capabilities, e.g., a Cell Culture Unit, the Advanced Animal Habitat for rodents, an Aquatic Facility to support small fish and aquatic specimens, a Plant Research Unit for plant cultivation, and a specialized Egg Incubator for developmental biology studies. Host systems (Figure 1A, B), e.g., a 2.5 m Centrifuge Rotor (g-levels from 0.01-g to 2-g) for direct comparisons between μg and selectable g levels, the Life Sciences Glove☐ for contained manipulations, and Habitat Holding Racks (Figure 1B) will provide electrical power, communication links, and cooling to the habitats. Habitats will provide food, water, light, air and waste management as well as humidity and temperature control for a variety of research organisms. Operators on Earth and the crew on the ISS will be able to send commands to the laboratory equipment to monitor and control the environmental and experimental parameters inside specific habitats. Common laboratory equipment such as microscopes, cryo freezers, radiation

  1. Runtime task mapping based on hardware configuration reuse

    NARCIS (Netherlands)

    Sigdel, K.; Galuzzi, C.; Bertels, K.; Thompson, M.; Pimentel, A.D.; Prasanna, V.; Becker, J.; Cumplido, R.

    2010-01-01

    In this paper, we propose a new heuristic for runtime task mapping of application(s) onto reconfigurable architectures. The heuristic is based on hardware configuration reuse, which tries to avoid the reconfiguration overhead of few selected tasks, by reusing the hardware configurations already avai

  2. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  3. [Hardware and software for X-ray therapy planning].

    Science.gov (United States)

    Zhizniakov, A L; Semenov, S I; Sushkova, L T; Troitskii, D P; Chirkov, K V

    2007-01-01

    Hardware, circuitry, and software suggested in this work make it possible to use the SLS-9 X-ray simulator for classical and computer tomographic imaging. The suggested hardware and software can be used as a basis for designing special-purpose tomographic systems.

  4. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  5. Trait stacking via targeted genome editing.

    Science.gov (United States)

    Ainley, William M; Sastry-Dent, Lakshmi; Welter, Mary E; Murray, Michael G; Zeitler, Bryan; Amora, Rainier; Corbin, David R; Miles, Rebecca R; Arnold, Nicole L; Strange, Tonya L; Simpson, Matthew A; Cao, Zehui; Carroll, Carley; Pawelczak, Katherine S; Blue, Ryan; West, Kim; Rowland, Lynn M; Perkins, Douglas; Samuel, Pon; Dewes, Cristie M; Shen, Liu; Sriram, Shreedharan; Evans, Steven L; Rebar, Edward J; Zhang, Lei; Gregory, Phillip D; Urnov, Fyodor D; Webb, Steven R; Petolino, Joseph F

    2013-12-01

    Modern agriculture demands crops carrying multiple traits. The current paradigm of randomly integrating and sorting independently segregating transgenes creates severe downstream breeding challenges. A versatile, generally applicable solution is hereby provided: the combination of high-efficiency targeted genome editing driven by engineered zinc finger nucleases (ZFNs) with modular 'trait landing pads' (TLPs) that allow 'mix-and-match', on-demand transgene integration and trait stacking in crop plants. We illustrate the utility of nuclease-driven TLP technology by applying it to the stacking of herbicide resistance traits. We first integrated into the maize genome an herbicide resistance gene, pat, flanked with a TLP (ZFN target sites and sequences homologous to incoming DNA) using WHISKERS™-mediated transformation of embryogenic suspension cultures. We established a method for targeted transgene integration based on microparticle bombardment of immature embryos and used it to deliver a second trait precisely into the TLP via cotransformation with a donor DNA containing a second herbicide resistance gene, aad1, flanked by sequences homologous to the integrated TLP along with a corresponding ZFN expression construct. Remarkably, up to 5% of the embryo-derived transgenic events integrated the aad1 transgene precisely at the TLP, that is, directly adjacent to the pat transgene. Importantly and consistent with the juxtaposition achieved via nuclease-driven TLP technology, both herbicide resistance traits cosegregated in subsequent generations, thereby demonstrating linkage of the two independently transformed transgenes. Because ZFN-mediated targeted transgene integration is becoming applicable across an increasing number of crop species, this work exemplifies a simple, facile and rapid approach to trait stacking.

  6. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  7. Compliant Glass Seals for SOFC Stacks

    Energy Technology Data Exchange (ETDEWEB)

    Chou, Y. S.; Choi, Jung-Pyung; Xu, Wei; Stephens, Elizabeth V.; Koeppel, Brian J.; Stevenson, Jeffry W.; Lara-Curzio, Edgar

    2014-04-01

    This report summarizes results from experimental and modeling studies performed by participants in the Solid-State Energy Conversion Alliance (SECA) Core Technology Program, which indicate that compliant glass-based seals offer a number of potential advantages over conventional seals based on de-vitrifying glasses, including reduced stresses during stack operation and thermal cycling, and the ability to heal micro-damage induced during thermal cycling. The properties and composition of glasses developed and/or investigated in these studies are reported, along with results from long-term (up to 5,800h) evaluations of seals based on a compliant glass containing ceramic particles or ceramic fibers.

  8. Compliant Glass Seals for SOFC Stacks

    Energy Technology Data Exchange (ETDEWEB)

    Chou, Yeong -Shyung [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Choi, Jung-Pyung [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Xu, Wei [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Stephens, Elizabeth V. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Koeppel, Brian J. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Stevenson, Jeffry W. [Pacific Northwest National Lab. (PNNL), Richland, WA (United States); Lara-Curzio, Edgar [Oak Ridge National Lab. (ORNL), Oak Ridge, TN (United States)

    2014-04-30

    This report summarizes results from experimental and modeling studies performed by participants in the Solid-State Energy Conversion Alliance (SECA) Core Technology Program, which indicate that compliant glass-based seals offer a number of potential advantages over conventional seals based on de-vitrifying glasses, including reduced stresses during stack operation and thermal cycling, and the ability to heal micro-damage induced during thermal cycling. The properties and composition of glasses developed and/or investigated in these studies are reported, along with results from long-term (up to 5,800h) evaluations of seals based on a compliant glass containing ceramic particles or ceramic fibers.

  9. Defining and Enforcing Hardware Security Requirements

    Science.gov (United States)

    2011-12-01

    only VHDL , does not provide PSL abstract syntax trees, and does not implement DFA minimization [4].1 The two most advanced checker generators...PSL Simple Subset, outputs VHDL or Verilog, provides PSL abstract syntax trees, and implements full DFA min- imization, as well as some boolean...Installation and Operation Instruction Set Registers Interrupts Privilege Levels Cache Libraries Modules Logic Design VHDL , Verilog Optimization Place and

  10. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  11. Hardware efficient monitoring of input/output signals

    Science.gov (United States)

    Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

    2012-01-01

    A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

  12. Structural Analysis of Furniture Hardware Industry in Turkey

    Directory of Open Access Journals (Sweden)

    Tuncer Dilik

    2005-01-01

    Full Text Available Furniture hardware plays an important role in the appearance, comfort and function of the furniture. In this study, Turkish furniture hardware companies were examined for their technical and economical characteristics, production materials, standards and surface treating methods, legal structures as well as foreign and domestic trade policies. Altogether, 67 companies accounting for 80% of the hardware production were examined. In addition, imported hardware brands, foreign trade companies and their representatives in Turkey were listed along with their production statistics and export sales by product groups for the years 1996-2000. It is found that the Turkish furniture hardware industry lacks vision and mission. Recommendations were made for sustained industry growth and for becoming competitive in international market.

  13. Toric Stacks I: The Theory of Stacky Fans

    CERN Document Server

    Geraschenko, Anton

    2011-01-01

    The purpose of this paper and its sequel (Toric Stacks II) is to introduce and develop a theory of toric stacks which encompasses and extends the notions of toric stacks defined in [Laf02, BCS05, FMN09, Iwa09a, Sat09, Tyo10], as well as classical toric varieties. In this paper, we define a \\emph{toric stack} as a quotient of a toric variety by a subgroup of its torus (we also define a generically stacky version). Any toric stack arises from a combinatorial gadget called a \\emph{stacky fan}. We develop a dictionary between the combinatorics of stacky fans and the geometry of toric stacks, stressing stacky phenomena such as canonical stacks and good moduli space morphisms. We also show that smooth toric stacks carry a moduli interpretation extending the usual moduli interpretations of $\\PP^n$ and $[\\AA^1/\\GG_m]$. Indeed, smooth toric stacks precisely solve moduli problems specified by (generalized) effective Cartier divisors with given linear relations and given intersection relations. Smooth toric stacks there...

  14. A Power Hardware-in-the-Loop Platform with Remote Distribution Circuit Cosimulation

    Energy Technology Data Exchange (ETDEWEB)

    Palmintier, Bryan; Lundstrom, Blake; Chakraborty, Sudipta; Williams, Tess L.; Schneider, Kevin P.; Chassin, David P.

    2015-04-01

    This paper demonstrates the use of a novel cosimulation architecture that integrates hardware testing using Power Hardware-in-the-Loop (PHIL) with larger-scale electric grid models using off-the-shelf, non-PHIL software tools. This architecture enables utilities to study the impacts of emerging energy technologies on their system and manufacturers to explore the interactions of new devices with existing and emerging devices on the power system, both without the need to convert existing grid models to a new platform or to conduct in-field trials. The paper describes an implementation of this architecture for testing two residential-scale advanced solar inverters at separate points of common coupling. The same hardware setup is tested with two different distribution feeders (IEEE 123 and 8500 node test systems) modeled using GridLAB-D. In addition to simplifying testing with multiple feeders, the architecture demonstrates additional flexibility with hardware testing in one location linked via the Internet to software modeling in a remote location. In testing, inverter current, real and reactive power, and PCC voltage are well captured by the co-simulation platform. Testing of the inverter advanced control features is currently somewhat limited by the software model time step (1 sec) and tested communication latency (24 msec). Overshoot induced oscillations are observed with volt/VAR control delays of 0 and 1.5 sec, while 3.4 sec and 5.5 sec delays produced little or no oscillation. These limitations could be overcome using faster modeling and communication within the same co-simulation architecture.

  15. Hardware Development Process for Human Research Facility Applications

    Science.gov (United States)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. The source of hardware requirements is the science community and HRF program. The HRF Science Working Group, consisting of SCientists from various medical disciplines, defined a basic set of equipment with functional requirements. This established the performance requirements of the hardware. HRF program requirements focus on making the hardware safe and operational in a space environment. This includes structural, thermal, human factors, and material requirements. Science and HRF program requirements are defined in a hardware requirements document which includes verification methods. Once the hardware is fabricated, requirements are verified by inspection, test, analysis, or demonstration. All data is compiled and reviewed to certify the hardware for flight. Obviously, the basis for all hardware development activities is requirement definition. Full and complete requirement definition is ideal prior to initiating the hardware development. However, this is generally not the case, but the hardware team typically has functional inputs as a guide. The first step is for engineers to conduct market research based on the functional inputs provided by scientists. CommerCially available products are evaluated against the science requirements as

  16. PBFA-2 vacuum insulator stack failure mechanisms

    Science.gov (United States)

    Sweeney, M. A.

    The BPFA-II accelerator includes a large-radius, vertical-axis vacuum insulator stack. The possible failure of the acrylic rings in the stack from electron- or gamma-induced charge buildup is being evaluated. The induced static charges could remain for many hours, and either type of irradiation might cause dendrites to form. Aluminum grading rings sandwiched between the acrylic affect charge accumulation; the acrylic would preferentially break down to these grading rings. The charge buildup and the bremsstrahlung dose could depend critically upon the directionality and position of the electron loss. The effects of electron loss that occurs in the vicinity of the ion diode, where the electrons have energies of about 30 MeV are considered. Monte Carlo electron-photon transport calculations indicate that the bremsstrahlung dose expected in an acrylic ring once diode experiments begin in 1986 could be as much as 5 krads per shot, with roughly half of the photon energy above 5 MeV. Moreover, the calculation indicate that the charge deposition in an individual acrylic ring might exceed 2x10 to the 11 electrons/sq cm.

  17. Control of heteroepitaxial stacking by substrate miscut

    Energy Technology Data Exchange (ETDEWEB)

    Bonham, S.W.; Flynn, C.P. [Materials Research Laboratory, University of Illinois at Urbana-Champaign, 104 South Goodwin, Urbana, Illinois 61801 (United States)

    1998-10-01

    We report studies of fcc epitaxial crystals, grown on Nb(110), in which the Nb surface offers a template for selection between the two alternative stackings, {ital ABCA}{hor_ellipsis} and {ital ACBA}{hor_ellipsis} of the fcc close-packed planes. The Nb templates were grown epitaxially about 500 {Angstrom} thick on sapphire (11{bar 2}0), and the fcc material studied was Cu{sub 3}Au. From symmetry it is not possible for the perfect bcc (110) surface to cause any such selection, which is here attributed instead to vicinal miscut: the logarithm of the stacking ratio must be even in miscut along [001] and odd in miscut along [1{bar 1}0]. We find that the measured selectivity is small for miscuts less than about 0.5{degree}, but approaches a factor 10{sup 3} for miscuts along [1{bar 1}0] greater than about 1{degree}. A mechanism for the selection process is discussed in terms of fingered mesostructures that grow on Nb(110) in this regime, as observed first by Zhou, Bonham, and Flynn. {copyright} {ital 1998} {ital The American Physical Society}

  18. Control of heteroepitaxial stacking by substrate miscut

    Science.gov (United States)

    Bonham, S. W.; Flynn, C. P.

    1998-10-01

    We report studies of fcc epitaxial crystals, grown on Nb(110), in which the Nb surface offers a template for selection between the two alternative stackings, ABCA... and ACBA... of the fcc close-packed planes. The Nb templates were grown epitaxially about 500 Å thick on sapphire (112¯0), and the fcc material studied was Cu3Au. From symmetry it is not possible for the perfect bcc (110) surface to cause any such selection, which is here attributed instead to vicinal miscut: the logarithm of the stacking ratio must be even in miscut along [001] and odd in miscut along [11¯0]. We find that the measured selectivity is small for miscuts less than about 0.5°, but approaches a factor 103 for miscuts along [11¯0] greater than about 1°. A mechanism for the selection process is discussed in terms of fingered mesostructures that grow on Nb(110) in this regime, as observed first by Zhou, Bonham, and Flynn.

  19. Tolerance Stack Analysis in Francis Turbine Design

    Directory of Open Access Journals (Sweden)

    Indra Djodikusumo

    2010-05-01

    Full Text Available The tolerance stacking problem arises in the context of assemblies from interchangeable parts because of the inability to produce or to join parts exactly according to nominal dimensions. Either the relevant part’s dimension varies around some nominal values from part to part or the act of assembly that leads to variation. For example, as runner of Francis turbine is joined with turbine shaft via mechanical lock, there is not only variation in the diameter of runner and the concentricity between the runner hole and turbine shaft, but also the variation in concentricity between the outer parts of runner to runner hole. Thus, there is the possibility that the assembly of such interacting parts won’t function or won’t come together as planned. Research in this area has been conducted and 2 mini hydro Francis turbines (800 kW and 910 kW have been designed and manufactured for San Sarino and Sawi Dago 2 in Central Sulawesi. Experiences in analyzing the tolerance stacks have been documented. In this paper it will be demonstrated how the requirements of assembling performance are derived to be the designed tolerances of each interacting component, such a way that the assembling would be functioning and come together as planned.

  20. Stacking Analysis of Binary Systems with HAWC

    Science.gov (United States)

    Brisbois, Chad; HAWC Collaboration

    2017-01-01

    Detecting binary systems at TeV energies is an important problem because only a handful of such systems are currently known. The nature of such systems is typically thought to be composed of a compact object and a massive star. The TeV emission from these systems does not obviously correspond to emission in GeV or X-ray, where many binary systems have previously been found. This study focuses on a stacking method to detect TeV emission from LS 5039, a known TeV binary, to test its efficacy in HAWC data. Stacking is a widely employed method for increasing signal to noise ratio in optical astronomy, but has never been attempted previously with HAWC. HAWC is an ideal instrument to search for TeV binaries, because of its wide field of view and high uptime. Applying this method to the entire sky may allow HAWC to detect binary sources of very short or very long periods not sensitive to current analyses. NSF, DOE, Los Alamos, Michigan Tech, CONACyt, UNAM, BUAP.

  1. [Bt transgenic crops for insect-resistance and modification of Bt protein and utilization of stacking strategy].

    Science.gov (United States)

    Li, Chen; Liu, Bolin

    2015-01-01

    Insecticidal protein genes from Bacillus thuringiensis are currently the most widely used insect-resistant genes. They have been transferred to many crops for breeding and production. Among them, cotton, maize, potato and other insect-resistant crops are commercialized, creating considerable economic benefit. In this review, we summarized advances in identifying functional genes and transgenic crops for insect resistance, compared different strategies for enhancing vigor of insecticidal protein and utilizing gene stacking as well as listing valuable groups of stacked genes. In addition, the methods for multiple gene transformation was discussed.

  2. Description of gasket failure in a 7 cell PEMFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Husar, Attila; Serra, Maria [Institut de Robotica i Informatica Industrial, Parc Tecnologic de Barcelona, Edifici U, C. Llorens i Artigas, 4-6, 2a Planta, 08028 Barcelona (Spain); Kunusch, Cristian [Laboratorio de Electronica Industrial Control e Instrumentacion, Facultad de Ingenieria, UNLP (Argentina)

    2007-06-10

    This article presents the data and the description of a fuel cell stack that failed due to gasket degradation. The fuel cell under study is a 7 cell stack. The unexpected change in several variables such as temperature, pressure and voltage indicated the possible failure of the stack. The stack was monitored over a 6 h period in which data was collected and consequently analyzed to conclude that the fuel cell stack failed due to a crossover leak on the anode inlet port located on the cathode side gasket of cell 2. This stack failure analysis revealed a series of indicators that could be used by a super visional controller in order to initiate a shutdown procedure. (author)

  3. Simple Stacking Methods for Silicon Micro Fuel Cells

    Directory of Open Access Journals (Sweden)

    Gianmario Scotti

    2014-08-01

    Full Text Available We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack. We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV of 1.6 V and a power density of 63 mW·cm−2, proving the viability of the design.

  4. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  5. Quadratic forms and Clifford algebras on derived stacks

    OpenAIRE

    Vezzosi, Gabriele

    2013-01-01

    In this paper we present an approach to quadratic structures in derived algebraic geometry. We define derived n-shifted quadratic complexes, over derived affine stacks and over general derived stacks, and give several examples of those. We define the associated notion of derived Clifford algebra, in all these contexts, and compare it with its classical version, when they both apply. Finally, we prove three main existence results for derived shifted quadratic forms over derived stacks, define ...

  6. Stacked Heterogeneous Neural Networks for Time Series Forecasting

    Directory of Open Access Journals (Sweden)

    Florin Leon

    2010-01-01

    Full Text Available A hybrid model for time series forecasting is proposed. It is a stacked neural network, containing one normal multilayer perceptron with bipolar sigmoid activation functions, and the other with an exponential activation function in the output layer. As shown by the case studies, the proposed stacked hybrid neural model performs well on a variety of benchmark time series. The combination of weights of the two stack components that leads to optimal performance is also studied.

  7. Cassette less SOFC stack and method of assembly

    Science.gov (United States)

    Meinhardt, Kerry D

    2014-11-18

    A cassette less SOFC assembly and a method for creating such an assembly. The SOFC stack is characterized by an electrically isolated stack current path which allows welded interconnection between frame portions of the stack. In one embodiment electrically isolating a current path comprises the step of sealing a interconnect plate to a interconnect plate frame with an insulating seal. This enables the current path portion to be isolated from the structural frame an enables the cell frame to be welded together.

  8. Co-flow planar SOFC fuel cell stack

    Science.gov (United States)

    Chung, Brandon W.; Pham, Ai Quoc; Glass, Robert S.

    2004-11-30

    A co-flow planar solid oxide fuel cell stack with an integral, internal manifold and a casing/holder to separately seal the cell. This construction improves sealing and gas flow, and provides for easy manifolding of cell stacks. In addition, the stack construction has the potential for an improved durability and operation with an additional increase in cell efficiency. The co-flow arrangement can be effectively utilized in other electrochemical systems requiring gas-proof separation of gases.

  9. Development of the electric utility dispersed use PAFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Horiuchi, Hiroshi; Kotani, Ikuo [Mitsubishi Electric Co., Kobe (Japan); Morotomi, Isamu [Kansai Electric Power Co., Hyogo (Japan)] [and others

    1996-12-31

    Kansai Electric Power Co. and Mitsubishi Electric Co. have been developing the electric utility dispersed use PAFC stack operated under the ambient pressure. The new cell design have been developed, so that the large scale cell (1 m{sup 2} size) was adopted for the stack. To confirm the performance and the stability of the 1 m{sup 2} scale cell design, the short stack study had been performed.

  10. Electrochemical removal of NOx with porous cell stacks

    DEFF Research Database (Denmark)

    Werchmeister, Rebecka Maria Larsen; Kammer Hansen, Kent; Mogensen, Mogens Bjerg

    2010-01-01

    In this study porous cell stacks were investigated for their ability to remove NOx electrochemically. The cell stacks were made from laminated tapes of porous electrolyte Ce0.9Gd0.1O1.95 and composite electrodes of La1−xSrxMnO3 (x = 0.15, and 0.5) and ceria doped with Gd or Pr. The cell stacks were...

  11. Targeting multiple heterogeneous hardware platforms with OpenCL

    Science.gov (United States)

    Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

    2014-06-01

    The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

  12. Thermoacoustics with idealized heat exchangers and no stack.

    Science.gov (United States)

    Wakeland, Ray Scott; Keolian, Robert M

    2002-06-01

    A model is developed for thermoacoustic devices that have neither stack nor regenerator. These "no-stack" devices have heat exchangers placed close together in an acoustic standing wave of sufficient amplitude to allow individual parcels of gas to enter both exchangers. The assumption of perfect heat transfer in the exchangers facilitates the construction of a simple model similar to the "moving parcel picture" that is used as a first approach to stack-based engines and refrigerators. The model no-stack cycle is shown to have potentially greater inviscid efficiency than a comparable stack model. However, losses from flow through the heat exchangers and on the walls of the enclosure are greater than those in a stack-based device due to the increased acoustic pressure amplitude. Estimates of these losses in refrigerators are used to compare the possible efficiencies of real refrigerators made with or without a stack. The model predicts that no-stack refrigerators can exceed stack-based refrigerators in efficiency, but only for particular enclosure geometries.

  13. Interactive visualization of multiresolution image stacks in 3D.

    Science.gov (United States)

    Trotts, Issac; Mikula, Shawn; Jones, Edward G

    2007-04-15

    Conventional microscopy, electron microscopy, and imaging techniques such as MRI and PET commonly generate large stacks of images of the sectioned brain. In other domains, such as neurophysiology, variables such as space or time are also varied along a stack axis. Digital image sizes have been progressively increasing and in virtual microscopy, it is now common to work with individual image sizes that are several hundred megapixels and several gigabytes in size. The interactive visualization of these high-resolution, multiresolution images in 2D has been addressed previously [Sullivan, G., and Baker, R., 1994. Efficient quad-tree coding of images and video. IEEE Trans. Image Process. 3 (3), 327-331]. Here, we describe a method for interactive visualization of multiresolution image stacks in 3D. The method, characterized as quad-tree based multiresolution image stack interactive visualization using a texel projection based criterion, relies on accessing and projecting image tiles from multiresolution image stacks in such a way that, from the observer's perspective, image tiles all appear approximately the same size even though they are accessed from different tiers within the images comprising the stack. This method enables efficient navigation of high-resolution image stacks. We implement this method in a program called StackVis, which is a Windows-based, interactive 3D multiresolution image stack visualization system written in C++ and using OpenGL. It is freely available at http://brainmaps.org.

  14. Hardware implementation of an electrostatic MEMS-actuator linearization

    Science.gov (United States)

    Mair, F.; Egretzberger, M.; Kugi, A.

    2011-06-01

    In this paper, an electrostatic actuator linearization will be introduced, which is based on an existing hardware-efficient iterative square root algorithm. The algorithm is solely based on add and shift operations while just needing n/2 iterations for an n bit wide input signal. As a practical example, the nonlinear input transformation will be utilized for the design of the primary mode controller of a capacitive MEMS gyroscope and an implementation of the algorithm in the Verilog hardware description language will be instantiated. Finally, measurement results will validate the feasibility of the presented control concept and its hardware implementation.

  15. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  16. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  17. A researching of the process of binding software to hardware

    OpenAIRE

    Piletskaia, A. Yu.; Kobenko, Yury Viktorovich

    2016-01-01

    Information security is one of the most important sphere in Cybernetics. And for Russia this problem is state-of-the-art because of the wide-spread internet piracy and a huge number of hackers. This article explores the commonest ways to protect software using binding to hardware, with a focus on the main approaches to a collection of data from hardware and ways of data processing. As a possible method of solution it is accepted to collect data from main parts of hardware using .Net Framework...

  18. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows...... the importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

  19. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on......-the-y the speciffic processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. Results show that significant speed-up and energy efficiency can be obtained by HLL acceleration on system-on-chips where reconfigurable fabric is placed next to the CPUs....

  20. Dynamically-Loaded Hardware Libraries (HLL) Technology for Audio Applications

    DEFF Research Database (Denmark)

    Esposito, A.; Lomuscio, A.; Nunzio, L. Di

    2016-01-01

    In this work, we apply hardware acceleration to embedded systems running audio applications. We present a new framework, Dynamically-Loaded Hardware Libraries or HLL, to dynamically load hardware libraries on reconfigurable platforms (FPGAs). Provided a library of application-specific processors......, we load on-the-fly the specific processor in the FPGA, and we transfer the execution from the CPU to the FPGA-based accelerator. The proposed architecture provides excellent flexibility with respect to the different audio applications implemented, high quality audio, and an energy efficient solution....

  1. Hardware based segmentation in iris recognition and authentication systems

    Science.gov (United States)

    Ulis, Bradley J.; Broussard, Randy P.; Rakvic, Ryan N.; Ives, Robert W.; Steiner, Neil; Ngo, Hau

    2009-05-01

    Iris recognition algorithms depend on image processing techniques for proper segmentation of the iris. In the Ridge Energy Direction (RED) iris recognition algorithm, the initial step in the segmentation process searches for the pupil by thresholding and using binary morphology functions to rectify artifacts obfuscating the pupil. These functions take substantial processing time in software on the order of a few hundred million operations. Alternatively, a hardware version of the binary morphology functions is implemented to assist in the segmentation process. The hardware binary morphology functions have negligible hardware footprint and power consumption while achieving speed up of 200 times compared to the original software functions.

  2. Hardware Implementation of Serially Concatenated PPM Decoder

    Science.gov (United States)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  3. Dynamic fuel cell stack model for real-time simulation based on system identification

    Science.gov (United States)

    Meiler, M.; Schmid, O.; Schudy, M.; Hofer, E. P.

    The authors have been developing an empirical mathematical model to predict the dynamic behaviour of a polymer electrolyte membrane fuel cell (PEMFC) stack. Today there is a great number of models, describing steady-state behaviour of fuel cells by estimating the equilibrium voltage for a certain set of operating parameters, but models capable of predicting the transient process between two steady-state points are rare. However, in automotive applications round about 80% of operating situations are dynamic. To improve the reliability of fuel cell systems by model-based control for real-time simulation dynamic fuel cell stack model is needed. Physical motivated models, described by differential equations, usually are complex and need a lot of computing time. To meet the real-time capability the focus is set on empirical models. Fuel cells are highly nonlinear systems, so often used auto-regressive (AR), output-error (OE) or Box-Jenkins (BJ) models do not accomplish satisfying accuracy. Best results are achieved by splitting the behaviour into a nonlinear static and a linear dynamic subsystem, a so-called Uryson-Model. For system identification and model validation load steps with different amplitudes are applied to the fuel cell stack at various operation points and the voltage response is recorded. The presented model is implemented in MATLAB environment and has a computing time of less than 1 ms per step on a standard desktop computer with a 2.8 MHz CPU and 504 MB RAM. Lab tests are carried out at DaimlerChrysler R&D Centre with DaimlerChrysler PEMFC hardware and a good agreement is found between model simulations and lab tests.

  4. Dynamic fuel cell stack model for real-time simulation based on system identification

    Energy Technology Data Exchange (ETDEWEB)

    Meiler, M.; Schmid, O.; Schudy, M. [Department of MEA and Stack Technology, DaimlerChrysler AG, Neue Str. 95, D-73230 Kirchheim/Teck (Germany); Hofer, E.P. [Department of Measurement, Control and Microtechnology, University of Ulm, Albert-Einstein-Allee 41, D-89081 Ulm (Germany)

    2008-02-01

    The authors have been developing an empirical mathematical model to predict the dynamic behaviour of a polymer electrolyte membrane fuel cell (PEMFC) stack. Today there is a great number of models, describing steady-state behaviour of fuel cells by estimating the equilibrium voltage for a certain set of operating parameters, but models capable of predicting the transient process between two steady-state points are rare. However, in automotive applications round about 80% of operating situations are dynamic. To improve the reliability of fuel cell systems by model-based control for real-time simulation dynamic fuel cell stack model is needed. Physical motivated models, described by differential equations, usually are complex and need a lot of computing time. To meet the real-time capability the focus is set on empirical models. Fuel cells are highly nonlinear systems, so often used auto-regressive (AR), output-error (OE) or Box-Jenkins (BJ) models do not accomplish satisfying accuracy. Best results are achieved by splitting the behaviour into a nonlinear static and a linear dynamic subsystem, a so-called Uryson-Model. For system identification and model validation load steps with different amplitudes are applied to the fuel cell stack at various operation points and the voltage response is recorded. The presented model is implemented in MATLAB environment and has a computing time of less than 1 ms per step on a standard desktop computer with a 2.8 MHz CPU and 504 MB RAM. Lab tests are carried out at DaimlerChrysler R and D Centre with DaimlerChrysler PEMFC hardware and a good agreement is found between model simulations and lab tests. (author)

  5. Dynamic provisioning of local and remote compute resources with OpenStack

    Science.gov (United States)

    Giffels, M.; Hauth, T.; Polgart, F.; Quast, G.

    2015-12-01

    Modern high-energy physics experiments rely on the extensive usage of computing resources, both for the reconstruction of measured events as well as for Monte-Carlo simulation. The Institut fur Experimentelle Kernphysik (EKP) at KIT is participating in both the CMS and Belle experiments with computing and storage resources. In the upcoming years, these requirements are expected to increase due to growing amount of recorded data and the rise in complexity of the simulated events. It is therefore essential to increase the available computing capabilities by tapping into all resource pools. At the EKP institute, powerful desktop machines are available to users. Due to the multi-core nature of modern CPUs, vast amounts of CPU time are not utilized by common desktop usage patterns. Other important providers of compute capabilities are classical HPC data centers at universities or national research centers. Due to the shared nature of these installations, the standardized software stack required by HEP applications cannot be installed. A viable way to overcome this constraint and offer a standardized software environment in a transparent manner is the usage of virtualization technologies. The OpenStack project has become a widely adopted solution to virtualize hardware and offer additional services like storage and virtual machine management. This contribution will report on the incorporation of the institute's desktop machines into a private OpenStack Cloud. The additional compute resources provisioned via the virtual machines have been used for Monte-Carlo simulation and data analysis. Furthermore, a concept to integrate shared, remote HPC centers into regular HEP job workflows will be presented. In this approach, local and remote resources are merged to form a uniform, virtual compute cluster with a single point-of-entry for the user. Evaluations of the performance and stability of this setup and operational experiences will be discussed.

  6. Stacking the odds for Golgi cisternal maturation.

    Science.gov (United States)

    Mani, Somya; Thattai, Mukund

    2016-01-01

    What is the minimal set of cell-biological ingredients needed to generate a Golgi apparatus? The compositions of eukaryotic organelles arise through a process of molecular exchange via vesicle traffic. Here we statistically sample tens of thousands of homeostatic vesicle traffic networks generated by realistic molecular rules governing vesicle budding and fusion. Remarkably, the plurality of these networks contain chains of compartments that undergo creation, compositional maturation, and dissipation, coupled by molecular recycling along retrograde vesicles. This motif precisely matches the cisternal maturation model of the Golgi, which was developed to explain many observed aspects of the eukaryotic secretory pathway. In our analysis cisternal maturation is a robust consequence of vesicle traffic homeostasis, independent of the underlying details of molecular interactions or spatial stacking. This architecture may have been exapted rather than selected for its role in the secretion of large cargo.

  7. ATLAS software stack on ARM64

    CERN Document Server

    Smith, Joshua Wyatt; The ATLAS collaboration

    2017-01-01

    This paper reports on the port of the ATLAS software stack onto new prototype ARM64 servers. This included building the “external” packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adjustments. A few additional modifications were needed to account for the different operating system, Ubuntu instead of Scientific Linux 6 / CentOS7. Selected results from the validation of the physics outputs on these ARM 64-bit servers will be shown. CPU, memory and IO intensive benchmarks using ATLAS specific environment and infrastructure have been performed, with a particular emphasis on the performance vs. energy consumption.

  8. Evaluating interaction techniques for stack mode viewing.

    Science.gov (United States)

    Atkins, M Stella; Fernquist, Jennifer; Kirkpatrick, Arthur E; Forster, Bruce B

    2009-08-01

    Three interaction techniques were evaluated for scrolling stack mode displays of volumetric data. Two used a scroll-wheel mouse: one used only the wheel, while another used a "click and drag" technique for fast scrolling, leaving the wheel for fine adjustments. The third technique used a Shuttle Xpress jog wheel. In a within-subjects design, nine radiologists searched stacked images for simulated hyper-intense regions on brain, knee, and thigh MR studies. Dependent measures were speed, accuracy, navigation path, and user preference. The radiologists considered the task realistic. They had high inter-subject variability in completion times, far larger than the differences between techniques. Most radiologists (eight out of nine) preferred familiar mouse-based techniques. Most participants scanned the data in two passes, first locating anomalies, then scanning for omissions. Participants spent a mean 10.4 s/trial exploring anomalies, with only mild variation between participants. Their rates of forward navigation searching for anomalies varied much more. Interaction technique significantly affected forward navigation rate (scroll wheel 5.4 slices/s, click and drag 9.4, and jog wheel 6.9). It is not clear what constrained the slowest navigators. The fastest navigator used a unique strategy of moving quickly just beyond an anomaly, then backing up. Eight naïve students performed a similar protocol. Their times and variability were similar to the radiologists, but more (three out of eight) students preferred the jog wheel. It may be worthwhile to introduce techniques such as the jog wheel to radiologists during training, and several techniques might be provided on workstations, allowing individuals to choose their preferred method.

  9. [Abscess at the implant site following apical parodontitis. Hardware-related complications of deep brain stimulation].

    Science.gov (United States)

    Sixel-Döring, F; Trenkwalder, C; Kappus, C; Hellwig, D

    2006-08-01

    Deep brain stimulation of the subthalamic nucleus is an important treatment option for advanced stages of idiopathic Parkinson's disease, leading to significant improvement of motor symptoms in suited patients. Hardware-related complications such as technical malfunction, skin erosion, and infections however cause patient discomfort and additional expense. The patient presented here suffered a putrid infection of the impulse generator site following only local dental treatment of apical parodontitis. Therefore, prophylactic systemic antibiotic treatment is recommended for patients with implanted deep brain stimulation devices in case of operations, dental procedures, or infectious disease.

  10. Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

    CERN Document Server

    Volpi, G; The ATLAS collaboration

    2013-01-01

    The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the Level-2 trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent results on the design, technological advancements and testing of some of the core components used in the processor.

  11. IT Career JumpStart An Introduction to PC Hardware, Software, and Networking

    CERN Document Server

    Alpern, Naomi J; Muller, Randy

    2011-01-01

    A practical approach for anyone looking to enter the IT workforce Before candidates can begin to prepare for any kind of certification, they need a basic understanding of the various hardware and software components used in a computer network. Aimed at aspiring IT professionals, this invaluable book strips down a network to its bare basics, and discusses this complex topic in a clear and concise manner so that IT beginners can confidently gain an understanding of fundamental IT concepts. In addition, a base knowledge has been established so that more advanced topics and technologies can be lea

  12. Hardware device to physical structure binding and authentication

    Energy Technology Data Exchange (ETDEWEB)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  13. New Model and Algorithm for Hardware/Software Partitioning

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan; Guang-Wei Zou

    2008-01-01

    This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O(n. A) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

  14. Hardware Virtualization Support In INTEL, AMD And IBM Power Processors

    CERN Document Server

    Biswas, Kamanashis

    2009-01-01

    At present, the mostly used and developed mechanism is hardware virtualization which provides a common platform to run multiple operating systems and applications in independent partitions. More precisely, it is all about resource virtualization as the term hardware virtualization is emphasized. In this paper, the aim is to find out the advantages and limitations of current virtualization techniques, analyze their cost and performance and also depict which forthcoming hardware virtualization techniques will able to provide efficient solutions for multiprocessor operating systems. This is done by making a methodical literature survey and statistical analysis of the benchmark reports provided by SPEC (Standard Performance Evaluation Corporation) and TPC (Transaction processing Performance Council). Finally, this paper presents the current aspects of hardware virtualization which will help the IT managers of the large organizations to take effective decision while choosing server with virtualization support. Aga...

  15. Towards Software Defined Radios Using Coarse-Grained Reconfigurable Hardware

    NARCIS (Netherlands)

    Rauwerda, Gerard K.; Heysters, Paul M.; Smit, Gerard J.M.; Jha, N.K.

    2008-01-01

    Mobile wireless terminals tend to become multimode wireless communication devices. Furthermore, these devices become adaptive. Heterogeneous reconfigurable hardware provides the flexibility, performance, and efficiency to enable the implementation of these devices. The implementation of a wideband c

  16. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    Energy Technology Data Exchange (ETDEWEB)

    Kaiser, Alex; Williams, Samuel; Madduri, Kamesh; Ibrahim, Khaled; Bailey, David; Demmel, James; Strohmaier, Erich

    2010-04-01

    Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

  17. Energy-efficient and security-optimized AES hardware design for ubiquitous computing

    Institute of Scientific and Technical Information of China (English)

    Chen Yicheng; Zou Xuecheng; Liu Zhenglin; Han Yu; Zheng Zhaoxia

    2008-01-01

    Ubiquitous computing must incorporate a certain level of security.For the severely resource con-strained applications,the energy-efficient and small size cryptography algorithm implementation is a critical problem.Hardware implementations of the advanced encryption standard(AES)for authentication and encryption are presented.An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices.It proves that compact AES architectures fail to optimize the AES hardware energy,whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods.Implemen tations of different substitution box(S-Boxes)structures are presented with 0.25 μm 1.8 V CMOS(complementary metal oxide semiconductor)standard cell library.The comparisons and trade-offs among area,security,and power are explored.The experimental results show that Galois field composite S-Boxes have smaller size and higheat security but consume considerably more power,whereas decoder-switch-encoder S-Boxes have the best power characteristics with disadvantages in terms of size and security.The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes.The technique of latch-dividing data path is analyzed,and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.

  18. Memory Based Machine Intelligence Techniques in VLSI hardware

    OpenAIRE

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high ...

  19. Hardware And Software For Development Of Robot Arms

    Science.gov (United States)

    Usikov, Daniel

    1995-01-01

    System of modular, reusable hardware and software assembled for use in developing remotely controlled robotic arms. Includes (1) central computer and peripheral equipment at control and monitoring station and (2) remote mechanical platform that supports robotic arm. Central computer controls motor drives of robotic arm, but optically, platform holds on-board computer for autonomous operation. Consists mostly of commercial hardware and software. Simulated results of commands viewed in three dimensions.

  20. The aerospace energy systems laboratory: Hardware and software implementation

    Science.gov (United States)

    Glover, Richard D.; Oneil-Rood, Nora

    1989-01-01

    For many years NASA Ames Research Center, Dryden Flight Research Facility has employed automation in the servicing of flight critical aircraft batteries. Recently a major upgrade to Dryden's computerized Battery Systems Laboratory was initiated to incorporate distributed processing and a centralized database. The new facility, called the Aerospace Energy Systems Laboratory (AESL), is being mechanized with iAPX86 and iAPX286 hardware running iRMX86. The hardware configuration and software structure for the AESL are described.

  1. Security challenges and opportunities in adaptive and reconfigurable hardware

    OpenAIRE

    Costan, Victor Marius; Devadas, Srinivas

    2011-01-01

    We present a novel approach to building hardware support for providing strong security guarantees for computations running in the cloud (shared hardware in massive data centers), while maintaining the high performance and low cost that make cloud computing attractive in the first place. We propose augmenting regular cloud servers with a Trusted Computation Base (TCB) that can securely perform high-performance computations. Our TCB achieves cost savings by spreading functionality across two pa...

  2. PLC Hardware Discrimination using RF-DNA fingerprinting

    Science.gov (United States)

    2014-06-19

    PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Bradley C. Wright, Civilian, USAF AFIT-ENG-T-14-J-12 DEPARTMENT OF THE AIR FORCE AIR...protection in the United States. AFIT-ENG-T-14-J-12 PLC HARDWARE DISCRIMINATION USING RF-DNA FINGERPRINTING THESIS Presented to the Faculty Department... DISCRIMINATION USING RF-DNA FINGERPRINTING Bradley C. Wright, B.S.E.E. Civilian, USAF Approved: /signed/ Maj Samuel J. Stone, PhD (Chairman) /signed/ Michael A

  3. Memory Based Machine Intelligence Techniques in VLSI hardware

    CERN Document Server

    James, Alex Pappachen

    2012-01-01

    We briefly introduce the memory based approaches to emulate machine intelligence in VLSI hardware, describing the challenges and advantages. Implementation of artificial intelligence techniques in VLSI hardware is a practical and difficult problem. Deep architectures, hierarchical temporal memories and memory networks are some of the contemporary approaches in this area of research. The techniques attempt to emulate low level intelligence tasks and aim at providing scalable solutions to high level intelligence problems such as sparse coding and contextual processing.

  4. Memristor Crossbar-based Hardware Implementation of IDS Method

    OpenAIRE

    Merrikh-Bayat, Farnood; Bagheri-Shouraki, Saeed; Rohani, Ali

    2010-01-01

    Ink Drop Spread (IDS) is the engine of Active Learning Method (ALM), which is the methodology of soft computing. IDS, as a pattern-based processing unit, extracts useful information from a system subjected to modeling. In spite of its excellent potential in solving problems such as classification and modeling compared to other soft computing tools, finding its simple and fast hardware implementation is still a challenge. This paper describes a new hardware implementation of IDS method based o...

  5. On the use of inexact, pruned hardware in atmospheric modelling.

    Science.gov (United States)

    Düben, Peter D; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V; Palmer, T N

    2014-06-28

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.

  6. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Bauce, Matteo; Dankel, Maik; Howard, Jacob; Kama, Sami

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. These data are processed by in-house built software frameworks which have lifetimes longer than the detector itself. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to parallel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software framework called Athena. In this talk we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline reconstruction as well as their integration into a multiple process based Athena frame...

  7. Fundamentals of GPS Receivers A Hardware Approach

    CERN Document Server

    Doberstein, Dan

    2012-01-01

    While much of the current literature on GPS receivers is aimed at those intimately familiar with their workings, this volume summarizes the basic principles using as little mathematics as possible, and details the necessary specifications and circuits for constructing a GPS receiver that is accurate to within 300 meters. Dedicated sections deal with the features of the GPS signal and its data stream, the details of the receiver (using a hybrid design as exemplar), and more advanced receivers and topics including time and frequency measurements. Later segments discuss the Zarlink GPS receiver chip set, as well as providing a thorough examination of the TurboRogue receiver, one of the most accurate yet made. Guiding the reader through the concepts and circuitry, from the antenna to the solution of user position, the book’s deployment of a hybrid receiver as a basis for discussion allows for extrapolation of the core ideas to more complex, and more accurate designs. Digital methods are used, but any analogue c...

  8. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Dankel, Maik; The ATLAS collaboration; Howard, Jacob; Bauce, Matteo; Boing, Rene

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. This data is processed by in-house built software frameworks which have lifetimes longer than the detector it- self. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to paral- lel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software frame- work called Athena. In this proceedings we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline recon- struction as well as their integration into a multiple process based...

  9. Evaluation of piezoelectret foam in a multilayer stack configuration for low-level vibration energy harvesting applications

    Science.gov (United States)

    Ray, Chase A.; Anton, Steven R.

    2015-04-01

    Electronic devices are high demand commodities in today's world, and such devices will continue increasing in popularity. Currently, batteries are implemented to provide power to these devices; however, the need for battery replacement, their cost, and the waste associated with battery disposal present a need for advances in self-powered technology. Energy harvesting technology has great potential to alleviate the drawbacks of batteries. In this work, a novel piezoelectret foam material is investigated for low-level energy harvesting. Specifically, piezoelectret foam assembled in a multilayer stack configuration is explored. Modeling and experimentation of the stack behavior when excited in compression at low frequencies are performed to investigate piezoelectret foam as a multilayer energy harvester. An examination of modeling piezoelectret foam as a stack with an equivalent circuit is made following recently published work and is used in this study. A 20-layer prototype device is fabricated and experimentally tested via harmonic base excitation. Electromechanical testing is performed by compressing the foam stack to obtain output electrical energy; consequently, allowing the frequency response between input mechanical energy and output electrical energy to be developed. Modeling results are compared to the experimental measurements to assess the fidelity of the model. Lastly, energy harvesting experimentation in which the device is subject to harmonic base excitation at the natural frequency is conducted to determine the ability of the piezoelectret foam stack to successfully charge a capacitor.

  10. Simultaneous stack-gas scrubbing and waste water treatment

    Science.gov (United States)

    Poradek, J. C.; Collins, D. D.

    1980-01-01

    Simultaneous treatment of wastewater and S02-laden stack gas make both treatments more efficient and economical. According to results of preliminary tests, solution generated by stack gas scrubbing cycle reduces bacterial content of wastewater. Both processess benefit by sharing concentrations of iron.

  11. Evaluating impact of truck announcements on container stacking efficiency

    NARCIS (Netherlands)

    E. van Asperen (Eelco); B. Borgman (Bram); R. Dekker (Rommert)

    2013-01-01

    textabstractContainer stacking rules are an important factor in container terminal efficiency. We build on prior research and use a discrete-event simulation model to evaluate the impact of a truck announcement system on the performance of online container stacking rules. The information that is con

  12. A Unit Cell Laboratory Experiment: Marbles, Magnets, and Stacking Arrangements

    Science.gov (United States)

    Collins, David C.

    2011-01-01

    An undergraduate first-semester general chemistry laboratory experiment introducing face-centered, body-centered, and simple cubic unit cells is presented. Emphasis is placed on the stacking arrangement of solid spheres used to produce a particular unit cell. Marbles and spherical magnets are employed to prepare each stacking arrangement. Packing…

  13. Efficient Context Switching for the Stack Cache: Implementation and Analysis

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian; Naji, Amine

    2015-01-01

    , the analysis of the stack cache was limited to individual tasks, ignoring aspects related to multitasking. A major drawback of the original stack cache design is that, due to its simplicity, it cannot hold the data of multiple tasks at the same time. Consequently, the entire cache content needs to be saved...

  14. The multiple facets of the Golgi reassembly stacking proteins

    NARCIS (Netherlands)

    Vinke, F.P.; Grieve, A.; Rabouille, C.

    2011-01-01

    The mammalian GRASPs (Golgi reassembly stacking proteins) GRASP65 and GRASP55 were first discovered more than a decade ago as factors involved in the stacking of Golgi cisternae. Since then, orthologues have been identified in many different organisms and GRASPs have been assigned new roles that may

  15. Yield and Cost Analysis or 3D Stacked ICs

    NARCIS (Netherlands)

    Taouil, M.

    2014-01-01

    3D stacking is an emerging technology promising many benefits such as low latency between stacked dies, reduced power consumption, high bandwidth communication, improved form factor and package volume density, heterogeneous integration, and low-cost manufacturing. However, it requires modification o

  16. Calculation of AC losses in large HTS stacks and coils

    DEFF Research Database (Denmark)

    Zermeno, Victor; Abrahamsen, Asger Bech; Mijatovic, Nenad;

    2012-01-01

    In this work, we present a homogenization method to model a stack of HTS tapes under AC applied transport current or magnetic field. The idea is to find an anisotropic bulk equivalent for the stack of tapes, where the internal alternating structures of insulating, metallic, superconducting and su...

  17. Nondestructive cell evaluation techniques in SOFC stack manufacturing

    Science.gov (United States)

    Wunderlich, C.

    2016-04-01

    Independent from the specifics of the application, a cost efficient manufacturing of solid oxide fuel cells (SOFC), its electrolyte membranes and other stack components, leading to reliable long-life stacks is the key for the commercial viability of this fuel cell technology. Tensile and shear stresses are most critical for ceramic components and especially for thin electrolyte membranes as used in SOFC cells. Although stack developers try to reduce tensile stresses acting on the electrolyte by either matching CTE of interconnects and electrolytes or by putting SOFC cells under some pressure - at least during transient operation of SOFC stacks ceramic cells will experience some tensile stresses. Electrolytes are required to have a high Weibull characteristic fracture strength. Practical experiences in stack manufacturing have shown that statistical fracture strength data generated by tests of electrolyte samples give limited information on electrolyte or cell quality. In addition, the cutting process of SOFC electrolytes has a major influence on crack initiation. Typically, any single crack in one the 30 to 80 cells in series connection will lead to a premature stack failure drastically reducing stack service life. Thus, for statistical reasons only 100% defect free SOFC cells must be assembled in stacks. This underlines the need for an automated inspection. So far, only manual processes of visual or mechanical electrolyte inspection are established. Fraunhofer IKTS has qualified the method of optical coherence tomography for an automated high throughput inspection. Alternatives like laser speckle photometry and acoustical methods are still under investigation.

  18. Long Josephson Junction Stack Coupled to a Cavity

    DEFF Research Database (Denmark)

    Madsen, Søren Peder; Pedersen, Niels Falsig; Groenbech-Jensen, N.

    2007-01-01

    A stack of inductively coupled long Josephson junctions are modeled as a system of coupled sine-Gordon equations. One boundary of the stack is coupled electrically to a resonant cavity. With one fluxon in each Josephson junction, the inter-junction fluxon forces are repulsive. We look at a possible...

  19. Development of internal reforming carbonate fuel cell stack technology

    Energy Technology Data Exchange (ETDEWEB)

    Farooque, M.

    1990-10-01

    Activities under this contract focused on the development of a coal-fueled carbonate fuel cell system design and the stack technology consistent with the system design. The overall contract effort was divided into three phases. The first phase, completed in January 1988, provided carbonate fuel cell component scale-up from the 1ft{sup 2} size to the commercial 4ft{sup 2} size. The second phase of the program provided the coal-fueled carbonate fuel cell system (CGCFC) conceptual design and carried out initial research and development needs of the CGCFC system. The final phase of the program emphasized stack height scale-up and improvement of stack life. The results of the second and third phases are included in this report. Program activities under Phase 2 and 3 were designed to address several key development areas to prepare the carbonate fuel cell system, particularly the coal-fueled CFC power plant, for commercialization in late 1990's. The issues addressed include: Coal-Gas Related Considerations; Cell and Stack Technology Improvement; Carbonate Fuel Cell Stack Design Development; Stack Tests for Design Verification; Full-Size Stack Design; Test Facility Development; Carbonate Fuel Cell Stack Cost Assessment; and Coal-Fueled Carbonate Fuel Cell System Design. All the major program objectives in each of the topical areas were successfully achieved. This report is organized along the above-mentioned topical areas. Each topical area has been processed separately for inclusion on the data base.

  20. An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

    CERN Document Server

    Mücke, M; Jacobsson, R

    2007-01-01

    Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that funct...

  1. Phase dynamics of two parallel stacks of coupled Josephson junctions

    Science.gov (United States)

    Shukrinov, Yu M.; Rahmonov, I. R.; Plecenik, A.; Seidel, P.; Ilʼichev, E.; Nawrocki, W.

    2014-12-01

    Two parallel stacks of coupled Josephson junctions (JJs) are investigated to clarify the physics of transitions between the rotating and oscillating states and their effect on the IV-characteristics of the system. The detailed study of phase dynamics and bias dependence of the superconducting and diffusion currents allows one to explain all features of simulated IV-characteristics and demonstrate the correspondence in their behavior. The coupling between JJ in the stacks leads to the branching of IV-characteristics and a decrease in the hysteretic region. The crucial role of the diffusion current in the formation of the IV-characteristic of the parallel stacks of coupled JJs is demonstrated. We discuss the effect of symmetry in a number of junctions in the stacks and show a decrease of the branching in the symmetrical stacks. The observed effects might be useful for development of superconducting electronic devices based on intrinsic JJs.

  2. Proposed Cavity for Reduced Slip-Stacking Loss

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, J. [Indiana U.; Zwaska, R. [Fermilab

    2015-06-01

    This paper employs a novel dynamical mechanism to improve the performance of slip-stacking. Slip-stacking in an accumulation technique used at Fermilab since 2004 which nearly double the proton intensity. During slip-stacking, the Recycler or the Main Injector stores two particles beams that spatially overlap but have different momenta. The two particle beams are longitudinally focused by two 53 MHz 100 kV RF cavities with a small frequency difference between them. We propose an additional 106 MHz 20 kV RF cavity, with a frequency at the double the average of the upper and lower main RF frequencies. In simulation, we find the proposed RF cavity significantly enhances the stable bucket area and reduces slip-stacking losses under reasonable injection scenarios. We quantify and map the stability of the parameter space for any accelerator implementing slip-stacking with the addition of a harmonic RF cavity.

  3. Solid oxide cell stack and method for preparing same

    DEFF Research Database (Denmark)

    2012-01-01

    A method for producing and reactivating a solid oxide cell stack structure by providing a catalyst precursor in at least one of the electrode layers by impregnation and subsequent drying after the stack has been assembled and initiated. Due to a significantly improved performance and an unexpecte...... voltage improvement this solid oxide cell stack structure is particularly suitable for use in solid oxide fuel cell (SOFC) and solid oxide electrolysing cell (SOEC) applications.......A method for producing and reactivating a solid oxide cell stack structure by providing a catalyst precursor in at least one of the electrode layers by impregnation and subsequent drying after the stack has been assembled and initiated. Due to a significantly improved performance and an unexpected...

  4. Review of Maxillofacial Hardware Complications and Indications for Salvage.

    Science.gov (United States)

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L; Sanati-Mehrizy, Paymon; Factor, Stephanie H; Taub, Peter J

    2016-06-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances when hardware may be salvaged. Articles considered for inclusion were found in the PubMed and Web of Science databases in August 2014 with the keywords maxillofacial trauma AND hardware complications OR indications for hardware removal. Included studies looked at human patients with only facial trauma and miniplate fixation, and presented data on complications and/or hardware removal. Fifteen articles were included. None were clinical trials. Complication data were presented by patient, fractures, and/or plate without consistency. The data described 1,075 fractures, 2,961 patients, and 2,592 plates, nonexclusive. Complication rates varied from 6 to 8% by fracture and 6 to 13% by patient. When their data were combined, 50% of complications were treated with plate removal; this was consistent across the mandible, midface, and upper face. All complications caused by loosening, nonunion, broken hardware, and severe/prolonged pain were treated with removal. Some complications caused by exposures, deformities, and infections were treated with salvage. Exposed plates were treated with flaps, plates with deformities were treated with secondary procedures including hardware revision, and hardware infections were treated with antibiotics alone or in conjunction with soft-tissue debridement and/or tooth extraction. Well-designed clinical trials evaluating hardware removal versus salvage are lacking. Some postoperative complications caused by exposure, deformity, and/or infection may be

  5. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

    Directory of Open Access Journals (Sweden)

    Pooja Batra

    2014-05-01

    Full Text Available For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs, wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS embedded DRAM (EDRAM having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

  6. Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

    Science.gov (United States)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Blacknall, Carolyn; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

  7. Advanced Hydrogen Turbine Development

    Energy Technology Data Exchange (ETDEWEB)

    Marra, John [Siemens Energy, Inc., Orlando, FL (United States)

    2015-09-30

    Under the sponsorship of the U.S. Department of Energy (DOE) National Energy Technology Laboratories, Siemens has completed the Advanced Hydrogen Turbine Development Program to develop an advanced gas turbine for incorporation into future coal-based Integrated Gasification Combined Cycle (IGCC) plants. All the scheduled DOE Milestones were completed and significant technical progress was made in the development of new technologies and concepts. Advanced computer simulations and modeling, as well as subscale, full scale laboratory, rig and engine testing were utilized to evaluate and select concepts for further development. Program Requirements of: A 3 to 5 percentage point improvement in overall plant combined cycle efficiency when compared to the reference baseline plant; 20 to 30 percent reduction in overall plant capital cost when compared to the reference baseline plant; and NOx emissions of 2 PPM out of the stack. were all met. The program was completed on schedule and within the allotted budget

  8. Laser Light Scattering, from an Advanced Technology Development Program to Experiments in a Reduced Gravity Environment

    Science.gov (United States)

    Meyer, William V.; Tscharnuter, Walther W.; Macgregor, Andrew D.; Dautet, Henri; Deschamps, Pierre; Boucher, Francois; Zuh, Jixiang; Tin, Padetha; Rogers, Richard B.; Ansari, Rafat R.

    1994-01-01

    Recent advancements in laser light scattering hardware are described. These include intelligent single card correlators; active quench/active reset avalanche photodiodes; laser diodes; and fiber optics which were used by or developed for a NASA advanced technology development program. A space shuttle experiment which will employ aspects of these hardware developments is previewed.

  9. Identification of critical parameters for PEMFC stack performance characterization and control strategies for reliable and comparable stack benchmarking

    DEFF Research Database (Denmark)

    Mitzel, Jens; Gülzow, Erich; Kabza, Alexander;

    2016-01-01

    in an average cell voltage deviation of 21 mV. Test parameters simulating different stack applications are summarized. The stack demonstrated comparable average cell voltage of 0.63 V for stationary and portable conditions. For automotive conditions, the voltage increased to 0.69 V, mainly caused by higher...

  10. A Review on the Key Software and Hardware Technology of the Advanced Robotic Manipulator Used for Underwater Structures Repair%水下结构物修复用先进机械手软硬件关键技术综述

    Institute of Scientific and Technical Information of China (English)

    周灿丰; 孙潇; 高辉; 焦向东

    2015-01-01

    机器人进行水下结构物维修时,不仅处于非结构化环境,而且存在浮游碰撞危险,作业区域可达性差,水下环境识别困难等特殊问题,所以,进一步提升机器人智能化水平非常重要。英国GRL公司用于焊缝检验的先进海底机械手A RM系统采用先进的人机接口以及工厂用机器人的某些技术,实现了机械手的控制。以ARM的开发经验为基础,目前GRL公司正在研制更为先进的机器人控制系统Polecat ,该系统将用于ROV导航员的训练平台Rovsim以及一系列欧盟和商业项目之中,其适用场合不仅包括海洋工程,也包括核电和其他环境。%When a robot is to carry out underwater structure repair ,it works in an unstructured environment .More significantly , some special problems should be solved , such as collision hazard in floating ,bad accessibility to working areas ,and difficult registration in underwater en‐vironment ,so to improve the intelligence level of subsea robots is very important .This paper de‐scribes the development of the ARM System ,an advanced subsea manipulator for weld inspection made by GRL UK .ARM uses an advanced man‐machine interface and provides robotic control of the manipulator adopting techniques developed in factory robots . A more advanced robotic control system ,Polecat ,is currently being developed by GRL UK ,based on experience gained from ARM .Polecat will be used in an ROV pilot trainer ,Rovsim ,and a number of European Union projects and other commercial projects ,which can be used subsea or in the nuclear power field .

  11. Long Duration Balloon Charge Controller Stack Integration

    Science.gov (United States)

    Clifford, Kyle

    NASA and the Columbia Scientific Balloon Facility are interested in updating the design of the charge controller on their long duration balloon (LDB) in order to enable the charge controllers to be directly interfaced via RS232 serial communication by a ground testing computers and the balloon's flight computer without the need to have an external electronics stack. The design involves creating a board that will interface with the existing boards in the charge controller in order to receive telemetry from and send commands to those boards, and interface with a computer through serial communication. The inputs to the board are digital status inputs indicating things like whether the photovoltaic panels are connected or disconnected; and analog inputs with information such as the battery voltage and temperature. The outputs of the board are 100ms duration command pulses that will switch relays that do things like connect the photovoltaic panels. The main component of this design is a PIC microcontroller which translates the outputs of the existing charge controller into serial data when interrogated by a ground testing or flight computer. Other components involved in the design are an AD7888 12-bit analog to digital converter, a MAX3232 serial transceiver, various other ICs, capacitors, resistors, and connectors.

  12. Lithiation-induced shuffling of atomic stacks

    KAUST Repository

    Nie, Anmin

    2014-09-10

    In rechargeable lithium-ion batteries, understanding the atomic-scale mechanism of Li-induced structural evolution occurring at the host electrode materials provides essential knowledge for design of new high performance electrodes. Here, we report a new crystalline-crystalline phase transition mechanism in single-crystal Zn-Sb intermetallic nanowires upon lithiation. Using in situ transmission electron microscopy, we observed that stacks of atomic planes in an intermediate hexagonal (h-)LiZnSb phase are "shuffled" to accommodate the geometrical confinement stress arising from lamellar nanodomains intercalated by lithium ions. Such atomic rearrangement arises from the anisotropic lithium diffusion and is accompanied by appearance of partial dislocations. This transient structure mediates further phase transition from h-LiZnSb to cubic (c-)Li2ZnSb, which is associated with a nearly "zero-strain" coherent interface viewed along the [001]h/[111]c directions. This study provides new mechanistic insights into complex electrochemically driven crystalline-crystalline phase transitions in lithium-ion battery electrodes and represents a noble example of atomic-level structural and interfacial rearrangements.

  13. Stacking faults in austempered ductile iron

    Energy Technology Data Exchange (ETDEWEB)

    Hermida, J.D. [CNEA, San Martin (Argentina). Dept. de Materiales

    1996-06-01

    During last decade, Austempered Ductile Iron (ADI) has been successfully used as an acceptable replacement material for steel in many applications, due to the relatively high strength and reasonable ductility obtained. These properties are the result of the special microstructure exhibited by this material at the end of the upper bainite reaction: ferrite platelets surrounded by high carbon stabilized austenite. However, at the beginning of the austempering treatment, the existence of interdendritic low carbon austenite is revealed by its transformation to martensite when cooling the sample or during subsequent deformation. The completion of the upper bainite reaction is of decisive importance to mechanical properties because the remaining martensite reduces ductility. It was observed that the rate of the upper bainite reaction is governed by the carbon content difference between the low and high carbon austenites. The carbon content is obtained by the lattice parameter measurement, because there exists a known expression that relates both magnitudes. Several works have used X-ray diffraction to measure the lattice parameter and phase concentrations as a function of austempering time. In these works, the lattice parameters were obtained directly from the {l_brace}220{r_brace} and {l_brace}311{r_brace} peaks position. The purpose of this work is to show more precise lattice parameters measurement and, very closely related to this, the existence of stacking faults in austenite, even at times within the processing window.

  14. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  15. Higher-Level Hardware Synthesis of the KASUMI Algorithm

    Institute of Scientific and Technical Information of China (English)

    Issam W. Damaj

    2007-01-01

    Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates.At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can exploit PLD technology.In this paper, we explore the effectiveness and extend one such formal methodology in the design of massively parallel algorithms.We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications.A functional programming notation is used for specifying algorithms and for reasoning about them.The specifications are realised through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions.The off-the-shelf refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware description language).The Handel-C descriptions are directly compiled into reconfigurable hardware.The practical realisation of this methodology is evidenced by a case studying the third generation mobile communication security algorithms.The investigated algorithm is the KASUMI block cipher.In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm.The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA.Performance analysis and evaluation of these implementations are included.

  16. Stacking for machine learning redshifts applied to SDSS galaxies

    CERN Document Server

    Zitlau, Roman; Paech, Kerstin; Weller, Jochen; Rau, Markus Michael; Seitz, Stella

    2016-01-01

    We present an analysis of a general machine learning technique called 'stacking' for the estimation of photometric redshifts. Stacking techniques can feed the photometric redshift estimate, as output by a base algorithm, back into the same algorithm as an additional input feature in a subsequent learning round. We shown how all tested base algorithms benefit from at least one additional stacking round (or layer). To demonstrate the benefit of stacking, we apply the method to both unsupervised machine learning techniques based on self-organising maps (SOMs), and supervised machine learning methods based on decision trees. We explore a range of stacking architectures, such as the number of layers and the number of base learners per layer. Finally we explore the effectiveness of stacking even when using a successful algorithm such as AdaBoost. We observe a significant improvement of between 1.9% and 21% on all computed metrics when stacking is applied to weak learners (such as SOMs and decision trees). When appl...

  17. Stacking for machine learning redshifts applied to SDSS galaxies

    Science.gov (United States)

    Zitlau, Roman; Hoyle, Ben; Paech, Kerstin; Weller, Jochen; Rau, Markus Michael; Seitz, Stella

    2016-08-01

    We present an analysis of a general machine learning technique called `stacking' for the estimation of photometric redshifts. Stacking techniques can feed the photometric redshift estimate, as output by a base algorithm, back into the same algorithm as an additional input feature in a subsequent learning round. We show how all tested base algorithms benefit from at least one additional stacking round (or layer). To demonstrate the benefit of stacking, we apply the method to both unsupervised machine learning techniques based on self-organizing maps (SOMs), and supervised machine learning methods based on decision trees. We explore a range of stacking architectures, such as the number of layers and the number of base learners per layer. Finally we explore the effectiveness of stacking even when using a successful algorithm such as AdaBoost. We observe a significant improvement of between 1.9 per cent and 21 per cent on all computed metrics when stacking is applied to weak learners (such as SOMs and decision trees). When applied to strong learning algorithms (such as AdaBoost) the ratio of improvement shrinks, but still remains positive and is between 0.4 per cent and 2.5 per cent for the explored metrics and comes at almost no additional computational cost.

  18. Reliability analysis and initial requirements for FC systems and stacks

    Science.gov (United States)

    Åström, K.; Fontell, E.; Virtanen, S.

    In the year 2000 Wärtsilä Corporation started an R&D program to develop SOFC systems for CHP applications. The program aims to bring to the market highly efficient, clean and cost competitive fuel cell systems with rated power output in the range of 50-250 kW for distributed generation and marine applications. In the program Wärtsilä focuses on system integration and development. System reliability and availability are key issues determining the competitiveness of the SOFC technology. In Wärtsilä, methods have been implemented for analysing the system in respect to reliability and safety as well as for defining reliability requirements for system components. A fault tree representation is used as the basis for reliability prediction analysis. A dynamic simulation technique has been developed to allow for non-static properties in the fault tree logic modelling. Special emphasis has been placed on reliability analysis of the fuel cell stacks in the system. A method for assessing reliability and critical failure predictability requirements for fuel cell stacks in a system consisting of several stacks has been developed. The method is based on a qualitative model of the stack configuration where each stack can be in a functional, partially failed or critically failed state, each of the states having different failure rates and effects on the system behaviour. The main purpose of the method is to understand the effect of stack reliability, critical failure predictability and operating strategy on the system reliability and availability. An example configuration, consisting of 5 × 5 stacks (series of 5 sets of 5 parallel stacks) is analysed in respect to stack reliability requirements as a function of predictability of critical failures and Weibull shape factor of failure rate distributions.

  19. PENGARUH POSISI STACK TERHADAP FREKUENSI RESONANSI PADA TABUNG RESONATOR TERMOAKUSTIK

    Directory of Open Access Journals (Sweden)

    Sigit Ristanto

    2013-05-01

    Full Text Available Telah dilakukan penelitian tentang pengaruh posisi stack dalam tabung resonator termoakustik terhadap frekuensi resonansi. Posisi stack ditaruh pada jarak 10 cm, 30 cm, dan 50 cm. Data frekuensi diambil menggunakan mikrofon yang dipasang pada ujung resonator. Mikrofon tersebut dihubungkan dengan laptop yang telah terisntall software sound card oscilloscope V1.40. Hasil penelitian menunjukkan variasi posisi stack tidak berpengaruh terhadap frekuensi resonansi, tetapi berpengaruh terhadap amplitudo maksimum pada masing-masing frekuensi resonansi. Amplitudo maksimum frekuensi resonansi terendah terjadi di tengah-tengah tabung resonator sedangkan amplitudo frekuensi resonansi terbesar terjadi pada ujung terjauh dari sumber bunyi.

  20. Fabrication of high gradient insulators by stack compression

    Energy Technology Data Exchange (ETDEWEB)

    Harris, John Richardson; Sanders, Dave; Hawkins, Steven Anthony; Norona, Marcelo

    2014-04-29

    Individual layers of a high gradient insulator (HGI) are first pre-cut to their final dimensions. The pre-cut layers are then stacked to form an assembly that is subsequently pressed into an HGI unit with the desired dimension. The individual layers are stacked, and alignment is maintained, using a sacrificial alignment tube that is removed after the stack is hot pressed. The HGI's are used as high voltage vacuum insulators in energy storage and transmission structures or devices, e.g. in particle accelerators and pulsed power systems.

  1. Revisiting the Fundamentals and Capabilities of the Stack Compression Test

    DEFF Research Database (Denmark)

    Alves, L.M.; Nielsen, Chris Valentin; Martin, P.A.F.

    2011-01-01

    of understanding for the stack compression test and to evaluate its capability for constructing the flow curves of metal sheets under high strains across the useful range of material testing conditions. The presentation draws from the fundamentals of the stack compression test to the assessment of its overall...... performance by comparing the flow curves obtained from its utilisation with those determined by means of compressive testing carried out on solid cylinder specimens of the same material. Results show that mechanical testing of materials by means of the stack compression test is capable of meeting...

  2. On $k$-stellated and $k$-stacked spheres

    OpenAIRE

    Bagchi, Bhaskar; Datta, Basudeb

    2012-01-01

    We introduce the class $\\Sigma_k(d)$ of $k$-stellated (combinatorial) spheres of dimension $d$ ($0 \\leq k \\leq d + 1$) and compare and contrast it with the class ${\\cal S}_k(d)$ ($0 \\leq k \\leq d$) of $k$-stacked homology $d$-spheres. We have $\\Sigma_1(d) = {\\cal S}_1(d)$, and $\\Sigma_k(d) \\subseteq {\\cal S}_k(d)$ for $d \\geq 2k - 1$. However, for each $k \\geq 2$ there are $k$-stacked spheres which are not $k$-stellated. The existence of $k$-stellated spheres which are not $k$-stacked remains...

  3. Loop Entropy Assists Tertiary Order: Loopy Stabilization of Stacking Motifs

    Directory of Open Access Journals (Sweden)

    Daniel P. Aalberts

    2011-11-01

    Full Text Available The free energy of an RNA fold is a combination of favorable base pairing and stacking interactions competing with entropic costs of forming loops. Here we show how loop entropy, surprisingly, can promote tertiary order. A general formula for the free energy of forming multibranch and other RNA loops is derived with a polymer-physics based theory. We also derive a formula for the free energy of coaxial stacking in the context of a loop. Simulations support the analytic formulas. The effects of stacking of unpaired bases are also studied with simulations.

  4. Phase dynamics modeling of parallel stacks of Josephson junctions

    Science.gov (United States)

    Rahmonov, I. R.; Shukrinov, Yu. M.

    2014-11-01

    The phase dynamics of two parallel connected stacks of intrinsic Josephson junctions (JJs) in high temperature superconductors is numerically investigated. The calculations are based on the system of nonlinear differential equations obtained within the CCJJ + DC model, which allows one to determine the general current-voltage characteristic of the system, as well as each individual stack. The processes with increasing and decreasing base currents are studied. The features in the behavior of the current in each stack of the system due to the switching between the states with rotating and oscillating phases are analyzed.

  5. 400 W High Temperature PEM Fuel Cell Stack Test

    DEFF Research Database (Denmark)

    Andreasen, Søren Juhl; Kær, Søren Knudsen

    2006-01-01

    This work demonstrates the operation of a 30 cell high temperature PEM (HTPEM) fuel cell stack. This prototype stack has been developed at the Institute of Energy Technology, Aalborg University, as a proof-of-concept for a low pressure cathode air cooled HTPEM stack. The membranes used are Celtec P...... of the species as in a LTPEM fuel cell system. The use of the HTPEM fuel cell makes it possible to use reformed gas at high CO concentrations, still with a stable efficient performance....

  6. A Software Managed Stack Cache for Real-Time Systems

    DEFF Research Database (Denmark)

    Jordan, Alexander; Abbaspourseyedi, Sahar; Schoeberl, Martin

    2016-01-01

    to scratchpad memory regions aids predictability, it is limited to non-recursive programs and static allocation has to take different calling contexts into account. Using a stack cache that dynamically spills data to and fills data from external memory avoids these problems, while its simple design allows...... for efficiently deriving worst-case bounds through static analysis. In this paper we present the design and implementation of software managed caching of stack allocated data in a scratchpad memory. We demonstrate a compiler-aided implementation of a stack cache using the LLVM compiler framework and report on its...

  7. Full Piezoelectric Multilayer-Stacked Hybrid Actuation/Transduction Systems

    Science.gov (United States)

    Su, Ji; Jiang, Xiaoning; Zu, Tian-Bing

    2011-01-01

    The Stacked HYBATS (Hybrid Actuation/Transduction system) demonstrates significantly enhanced electromechanical performance by using the cooperative contributions of the electromechanical responses of multilayer, stacked negative strain components and positive strain components. Both experimental and theoretical studies indicate that, for Stacked HYBATS, the displacement is over three times that of a same-sized conventional flextensional actuator/transducer. The coupled resonance mode between positive strain and negative strain components of Stacked HYBATS is much stronger than the resonance of a single element actuation only when the effective lengths of the two kinds of elements match each other. Compared with the previously invented hybrid actuation system (HYBAS), the multilayer Stacked HYBATS can be designed to provide high mechanical load capability, low voltage driving, and a highly effective piezoelectric constant. The negative strain component will contract, and the positive strain component will expand in the length directions when an electric field is applied on the device. The interaction between the two elements makes an enhanced motion along the Z direction for Stacked-HYBATS. In order to dominate the dynamic length of Stacked-HYBATS by the negative strain component, the area of the cross-section for the negative strain component will be much larger than the total cross-section areas of the two positive strain components. The transverse strain is negative and longitudinal strain positive in inorganic materials, such as ceramics/single crystals. Different piezoelectric multilayer stack configurations can make a piezoelectric ceramic/single-crystal multilayer stack exhibit negative strain or positive strain at a certain direction without increasing the applied voltage. The difference of this innovation from the HYBAS is that all the elements can be made from one-of-a-kind materials. Stacked HYBATS can provide an extremely effective piezoelectric

  8. Current status and challenges in PEMFC stacks, systems and commercialization

    Institute of Scientific and Technical Information of China (English)

    任远; 曹广益; 朱新坚

    2006-01-01

    The current status of worldwide developments of polymer electrolyte membrane fuel cell (PEMFC) stacks and system,research activities in resent years to analyze the cost of PEMFC stacks and systems, the remaining research and development issues that should be resolved before the PEMFC available for commercial application were discussed. The two main problems that challenge the PEMFC commercialization were cost and fuel supply infrastructure. The ways to lower the cost, to choose the fuel and improve the efficiency and reliability were described. To research the cost target of 125 kW and stack lifetime of 40 000 ~ 100 000h, basic research in PEMFC was indispensable.

  9. Hardware/Software Co-Design for Spike Based Recognition

    CERN Document Server

    Ghani, Arfan; Maguire, Liam; Harkin, Jim

    2008-01-01

    The practical applications based on recurrent spiking neurons are limited due to their non-trivial learning algorithms. The temporal nature of spiking neurons is more favorable for hardware implementation where signals can be represented in binary form and communication can be done through the use of spikes. This work investigates the potential of recurrent spiking neurons implementations on reconfigurable platforms and their applicability in temporal based applications. A theoretical framework of reservoir computing is investigated for hardware/software implementation. In this framework, only readout neurons are trained which overcomes the burden of training at the network level. These recurrent neural networks are termed as microcircuits which are viewed as basic computational units in cortical computation. This paper investigates the potential of recurrent neural reservoirs and presents a novel hardware/software strategy for their implementation on FPGAs. The design is implemented and the functionality is ...

  10. XOR-FREE Implementation of Convolutional Encoder for Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Gaurav Purohit

    2016-01-01

    Full Text Available This paper presents a novel XOR-FREE algorithm to implement the convolutional encoder using reconfigurable hardware. The approach completely removes the XOR processing of a chosen nonsystematic, feedforward generator polynomial of larger constraint length. The hardware (HW implementation of new architecture uses Lookup Table (LUT for storing the parity bits. The design implements architectural reconfigurability by modifying the generator polynomial of the same constraint length and code rate to reduce the design complexity. The proposed architecture reduces the dynamic power up to 30% and improves the hardware cost and propagation delay up to 20% and 32%, respectively. The performance of the proposed architecture is validated in MATLAB Simulink and tested on Zynq-7 series FPGA.

  11. Scalable Digital Hardware for a Trapped Ion Quantum Computer

    CERN Document Server

    Mount, Emily; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2015-01-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for trapping and cooling the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  12. Scalable digital hardware for a trapped ion quantum computer

    Science.gov (United States)

    Mount, Emily; Gaultney, Daniel; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2016-12-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for loading, cooling, initialization, and detection of the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  13. Floating point hardware emulator for RSX-11D

    Energy Technology Data Exchange (ETDEWEB)

    Kellogg, M.; Long, M.

    1977-01-01

    An RSX-11D task was written to simulate the FP-11 floating point hardware on systems that lack this hardware. The simulation is transparent to tasks using floating point instructions. All normal features of the hardware are simulated exactly, including its action on exception conditions. The emulator is a privileged task occupying about 2.7K words of memory. When it is loaded and run, it sets up a linkage to intercept the reserved instruction trap before it reaches the executive, and route it to a service routine that can decode and simulate the floating point instruction set. The results of a benchmark timing test are given, as are notes on converting the emulator to run under RSX-11M. 1 figure, 2 tables.

  14. Modular particle filtering FPGA hardware architecture for brain machine interfaces.

    Science.gov (United States)

    Mountney, John; Obeid, Iyad; Silage, Dennis

    2011-01-01

    As the computational complexities of neural decoding algorithms for brain machine interfaces (BMI) increase, their implementation through sequential processors becomes prohibitive for real-time applications. This work presents the field programmable gate array (FPGA) as an alternative to sequential processors for BMIs. The reprogrammable hardware architecture of the FPGA provides a near optimal platform for performing parallel computations in real-time. The scalability and reconfigurability of the FPGA accommodates diverse sets of neural ensembles and a variety of decoding algorithms. Throughput is significantly increased by decomposing computations into independent parallel hardware modules on the FPGA. This increase in throughput is demonstrated through a parallel hardware implementation of the auxiliary particle filtering signal processing algorithm.

  15. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

    2015-01-01

    -efficient protocols that use such an abstraction, as well as mechanisms to optimize a communication protocol in terms of energy consumption. The problem is modeled for different feedback-based techniques, where sensors are connected to a base station, either directly or through relays. We show that for four example......The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware...... platforms, the use of relays may decrease up to 4.5 times the total energy consumption when the protocol and the hardware are carefully matched. We conclude that: 1) the energy budget for a communication protocol varies significantly on different sensor platforms; and 2) the protocols can be judiciously...

  16. Asymmetric Hardware Distortions in Receive Diversity Systems: Outage Performance Analysis

    KAUST Repository

    Javed, Sidrah

    2017-02-22

    This paper studies the impact of asymmetric hardware distortion (HWD) on the performance of receive diversity systems using linear and switched combining receivers. The asymmetric attribute of the proposed model motivates the employment of improper Gaussian signaling (IGS) scheme rather than the traditional proper Gaussian signaling (PGS) scheme. The achievable rate performance is analyzed for the ideal and non-ideal hardware scenarios using PGS and IGS transmission schemes for different combining receivers. In addition, the IGS statistical characteristics are optimized to maximize the achievable rate performance. Moreover, the outage probability performance of the receive diversity systems is analyzed yielding closed form expressions for both PGS and IGS based transmission schemes. HWD systems that employ IGS is proven to efficiently combat the self interference caused by the HWD. Furthermore, the obtained analytic expressions are validated through Monte-Carlo simulations. Eventually, non-ideal hardware transceivers degradation and IGS scheme acquired compensation are quantified through suitable numerical results.

  17. Hardware Architecture Study for NASA's Space Software Defined Radios

    Science.gov (United States)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  18. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  19. Dependence of Raman and absorption spectra of stacked bilayer MoS2 on the stacking orientation.

    Science.gov (United States)

    Park, Seki; Kim, Hyun; Kim, Min Su; Han, Gang Hee; Kim, Jeongyong

    2016-09-19

    Stacked bilayer molybdenum disulfide (MoS2) exhibits interesting physical properties depending on the stacking orientation and interlayer coupling strength. Although optical properties, such as photoluminescence, Raman, and absorption properties, are largely dependent on the interlayer coupling of stacked bilayer MoS2, the origin of variations in these properties is not clearly understood. We performed comprehensive confocal Raman and absorption mapping measurements to determine the dependence of these spectra on the stacking orientation of bilayer MoS2. The results indicated that with 532-nm laser excitation, the Raman scattering intensity gradually increased upon increasing the stacking angle from 0° to 60°, whereas 458-nm laser excitation resulted in the opposite trend of decreasing Raman intensity with increasing stacking angle. This opposite behavior of the Raman intensity dependence was explained by the varying resonance condition between the Raman excitation wavelength and C exciton absorption energy of bilayer MoS2. Our work sheds light on the intriguing effect of the subtle interlayer interaction in stacked MoS2 bilayers on the resulting optical properties.

  20. Surface moisture measurement system hardware acceptance test report

    Energy Technology Data Exchange (ETDEWEB)

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  1. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  2. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  3. Automating an EXAFS facility: hardware and software considerations

    Energy Technology Data Exchange (ETDEWEB)

    Georgopoulos, P; Sayers, D E; Bunker, B; Elam, T; Grote, W A

    1981-01-01

    The basic design considerations for computer hardware and software, applicable not only to laboratory EXAFS facilities, but also to synchrotron installations, are reviewed. Uniformity and standardization of both hardware configurations and program packages for data collection and analysis are heavily emphasized. Specific recommendations are made with respect to choice of computers, peripherals, and interfaces, and guidelines for the development of software packages are set forth. A description of two working computer-interfaced EXAFS facilities is presented which can serve as prototypes for future developments. 3 figures.

  4. Hardware locks for a real-time Java chip multiprocessor

    DEFF Research Database (Denmark)

    Strøm, Torur Biskopstø; Puffitsch, Wolfgang; Schoeberl, Martin

    2016-01-01

    A software locking mechanism commonly protects shared resources for multithreaded applications. This mechanism can, especially in chip-multiprocessor systems, result in a large synchronization overhead. For real-time systems in particular, this overhead increases the worst-case execution time...... and may void a task set's schedulability. This paper presents 2 hardware locking mechanisms to reduce the worst-case time required to acquire and release synchronization locks. These solutions are implemented for the chip-multiprocessor version of the Java Optimized Processor. The 2 hardware locking...

  5. Hardware-assisted software clock synchronization for homogeneous distributed systems

    Science.gov (United States)

    Ramanathan, P.; Kandlur, Dilip D.; Shin, Kang G.

    1990-01-01

    A clock synchronization scheme that strikes a balance between hardware and software solutions is proposed. The proposed is a software algorithm that uses minimal additional hardware to achieve reasonably tight synchronization. Unlike other software solutions, the guaranteed worst-case skews can be made insensitive to the maximum variation of message transit delay in the system. The scheme is particularly suitable for large partially connected distributed systems with topologies that support simple point-to-point broadcast algorithms. Examples of such topologies include the hypercube and the mesh interconnection structures.

  6. On Issues of Precision for Hardware-based Volume Visualization

    Energy Technology Data Exchange (ETDEWEB)

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  7. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain

    Directory of Open Access Journals (Sweden)

    Guillermo A. Jaquenod

    2014-01-01

    Full Text Available In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.

  8. Realizable Hardware-Based Method for Digital Modulation Classification

    Institute of Scientific and Technical Information of China (English)

    HAN Li; WAN Jin-bo

    2005-01-01

    A new method suited for hardware implementation is developed to classify 8 different digital modulation types with raised cosine base-band impulse without knowing the carrier frequency and symbol timing. The normalized histogram of stagnation points for instantaneous parameters is used to recognize both ideal rectangular and raised cosine base-band digital signals. Carrier frequency estimation is used to enhance the recognition rate of phase-modulated signals. In the condition of 10 dB signal noise ratio (SNR), the recognizing rate is over 80 %. The new algorithm is suited for hardware implementation.

  9. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  10. Towards Shop Floor Hardware Reconfiguration for Industrial Collaborative Robots

    DEFF Research Database (Denmark)

    Schou, Casper; Madsen, Ole

    2016-01-01

    In this paper we propose a roadmap for hardware reconfiguration of industrial collaborative robots. As a flexible resource, the collaborative robot will often need transitioning to a new task. Our goal is, that this transitioning should be done by the shop floor operators, not highly specialized...... engineers. The hard- ware reconfiguration framework adopts a modular architecture for the collabo- rative robot which dictates a clear segmentation of the robot into well-defined exchangeable modules. Four main objectives for the hardware reconfiguration framework; 1) Modular architecture, 2) Module...

  11. Identification of critical parameters for PEMFC stack performance characterization and control strategies for reliable and comparable stack benchmarking

    DEFF Research Database (Denmark)

    Mitzel, Jens; Gülzow, Erich; Kabza, Alexander;

    2016-01-01

    for the control strategy are summarized. This ensures result comparability as well as stable test conditions. E.g., the stack temperature fluctuation is minimized to about 1 °C. The experiments demonstrate that reactants pressures differ up to 12 kPa if pressure control positions are varied, resulting...... in an average cell voltage deviation of 21 mV. Test parameters simulating different stack applications are summarized. The stack demonstrated comparable average cell voltage of 0.63 V for stationary and portable conditions. For automotive conditions, the voltage increased to 0.69 V, mainly caused by higher...

  12. Standard Hardware Acquisition and Reliability Program's (SHARP's) efforts in incorporating fiber optic interconnects into standard electronic module (SEM) connectors

    Science.gov (United States)

    Riggs, William R.

    1994-05-01

    SHARP is a Navy wide logistics technology development effort aimed at reducing the acquisition costs, support costs, and risks of military electronic weapon systems while increasing the performance capability, reliability, maintainability, and readiness of these systems. Lower life cycle costs for electronic hardware are achieved through technology transition, standardization, and reliability enhancement to improve system affordability and availability as well as enhancing fleet modernization. Advanced technology is transferred into the fleet through hardware specifications for weapon system building blocks of standard electronic modules, standard power systems, and standard electronic systems. The product lines are all defined with respect to their size, weight, I/O, environmental performance, and operational performance. This method of defining the standard is very conducive to inserting new technologies into systems using the standard hardware. This is the approach taken thus far in inserting photonic technologies into SHARP hardware. All of the efforts have been related to module packaging; i.e. interconnects, component packaging, and module developments. Fiber optic interconnects are discussed in this paper.

  13. Improvement of nuclear ship engineering simulation system. Hardware renewal and interface improvement of the integral type reactor

    Energy Technology Data Exchange (ETDEWEB)

    Takahashi, Hiroki; Kyoya, Masahiko; Shimazaki, Junya [Japan Atomic Energy Research Inst., Tokai, Ibaraki (Japan). Tokai Research Establishment; Kano, Tadashi [KCS, Co., Mito, Ibaraki (Japan); Takahashi, Teruo [Energis, Co., Kobe, Hyogo (Japan)

    2001-10-01

    JAERI had carried out the design study about a lightweight and compact integral type reactor (an advanced marine reactor) with passive safety equipment as a power source for the future nuclear ships, and completed an engineering design. We have developed the simulator for the integral type reactor to confirm the design and operation performance and to utilize the study of automation of the reactor operation. The simulator can be used also for future research and development of a compact reactor. However, the improvement in a performance of hardware and a human machine interface of software of the simulator were needed for future research and development. Therefore, renewal of hardware and improvement of software have been conducted. The operability of the integral-reactor simulator has been improved. Furthermore, this improvement with the hardware and software on the market brought about better versatility, maintainability, extendibility and transfer of the system. This report mainly focuses on contents of the enhancement in a human machine interface, and describes hardware renewal and the interface improvement of the integral type reactor simulator. (author)

  14. Sport stacking activities in school children's motor skill development.

    Science.gov (United States)

    Li, Yuhua; Coleman, Diane; Ransdell, Mary; Coleman, Lyndsie; Irwin, Carol

    2011-10-01

    This study examined the impact of a 12-wk. sport stacking intervention on reaction time (RT), manual dexterity, and hand-eye coordination in elementary school-aged children. 80 Grade 2 students participated in a 15-min. sport stacking practice session every school day for 12 wk., and were tested on psychomotor performance improvement. Tests for choice RT, manual dexterity, and photoelectric rotary pursuit tracking were conducted pre- and post-intervention for both experimental group (n = 36) and the controls (n = 44) who did no sport stacking. Students who had the intervention showed a greater improvement in two-choice RT. No other group difference was found. Such sport stacking activities may facilitate children's central processing and perceptual-motor integration.

  15. Anisotropic electronic conduction in stacked two-dimensional titanium carbide

    Science.gov (United States)

    Hu, Tao; Zhang, Hui; Wang, Jiemin; Li, Zhaojin; Hu, Minmin; Tan, Jun; Hou, Pengxiang; Li, Feng; Wang, Xiaohui

    2015-11-01

    Stacked two-dimensional titanium carbide is an emerging conductive material for electrochemical energy storage which requires an understanding of the intrinsic electronic conduction. Here we report the electronic conduction properties of stacked Ti3C2T2 (T = OH, O, F) with two distinct stacking sequences (Bernal and simple hexagonal). On the basis of first-principles calculations and energy band theory analysis, both stacking sequences give rise to metallic conduction with Ti 3d electrons contributing most to the conduction. The conduction is also significantly anisotropic due to the fact that the effective masses of carriers including electrons and holes are remarkably direction-dependent. Such an anisotropic electronic conduction is evidenced by the I-V curves of an individual Ti3C2T2 particulate, which demonstrates that the in-plane electrical conduction is at least one order of magnitude higher than that vertical to the basal plane.

  16. Real-time focal stack compositing for handheld mobile cameras

    Science.gov (United States)

    Solh, Mashhour

    2013-03-01

    Extending the depth of field using a single lens camera on a mobile device can be achieved by capturing a set of images each focused at a different depth or focal stack then combine these samples of the focal stack to form a single all-in-focus image or an image refocused at a desired depth of field. Focal stack compositing in real time for a handheld mobile camera has many challenges including capturing, processing power, handshaking, rolling shutter artifacts, occlusion, and lens zoom effect. In this paper, we describe a system for a real time focal stack compositing system for handheld mobile device with an alignment and compositing algorithms. We will also show all-in-focus images captured and processed by a cell phone camera running on Android OS.

  17. SEE on Different Layers of Stacked-SRAMs

    CERN Document Server

    Gupta, V; Tsiligiannis, G; Rousselet, M; Mohammadzadeh, A; Javanainen, A; Virtanen, A; Puchner, H; Saigné, F; Wrobel, F; Dilillo, L

    2015-01-01

    This paper presents heavy-ion and proton radiation test results of a 90 nm COTS SRAM with stacked structure. Radiation tests were made using high penetration heavy-ion cocktails at the HIF (Belgium) and at RADEF (Finland) as well as low energy protons at RADEF. The heavy-ion SEU cross-section showed an unusual profile with a peak at the lowest LET (heavy-ion with the highest penetration range). The discrepancy is due to the fact that the SRAM is constituted of two vertically stacked dice. The impact of proton testing on the response of both stacked dice is presented. The results are discussed and the SEU cross-sections of the upper and lower layers are compared. The impact of the stacked structure on the proton SEE rate is investigated.

  18. Static analysis of worst-case stack cache behavior

    DEFF Research Database (Denmark)

    Jordan, Alexander; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    Utilizing a stack cache in a real-time system can aid predictability by avoiding interference that heap memory traffic causes on the data cache. While loads and stores are guaranteed cache hits, explicit operations are responsible for managing the stack cache. The behavior of these operations can...... be analyzed statically. We present algorithms that derive worst-case bounds on the latency-inducing operations of the stack cache. Their results can be used by a static WCET tool. By breaking the analysis down into subproblems that solve intra-procedural data-flow analysis and path searches on the call......-graph, the worst-case bounds can be efficiently yet precisely determined. Our evaluation using the MiBench benchmark suite shows that only 37% and 21% of potential stack cache operations actually store to and load from memory, respectively. Analysis times are modest, on average running between 0.46s and 1.30s per...

  19. TOOL PATH PLANNING USING VORONOI DIAGRAM AND THREE STACKS

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Based on the object-oriented data structure of Vor onoi diagram, the algorithm of the trimmed offset generating and the optimal too l path planning of the pocket machining for multiply connected polygonal domains are studied. The intersection state transition rule is improved in this algorit hm. The intersection is between the trimmed offsets and Voronoi polygon. On this basis, the trimmed offset generating and the optimal tool path planning are mad e with three stacks(I-stack, C-stack and P-stack)in different monotonous pouc hes of Voronoi diagram. At the same time, a merging method of Voronoi diagram an d offsets generating for multiply connected polygonal domains is also presented. The above algorithms have been implemented in NC machining successfully, and th e efficiency is fully verified.

  20. Stacks: an analysis tool set for population genomics.

    Science.gov (United States)

    Catchen, Julian; Hohenlohe, Paul A; Bassham, Susan; Amores, Angel; Cresko, William A

    2013-06-01

    Massively parallel short-read sequencing technologies, coupled with powerful software platforms, are enabling investigators to analyse tens of thousands of genetic markers. This wealth of data is rapidly expanding and allowing biological questions to be addressed with unprecedented scope and precision. The sizes of the data sets are now posing significant data processing and analysis challenges. Here we describe an extension of the Stacks software package to efficiently use genotype-by-sequencing data for studies of populations of organisms. Stacks now produces core population genomic summary statistics and SNP-by-SNP statistical tests. These statistics can be analysed across a reference genome using a smoothed sliding window. Stacks also now provides several output formats for several commonly used downstream analysis packages. The expanded population genomics functions in Stacks will make it a useful tool to harness the newest generation of massively parallel genotyping data for ecological and evolutionary genetics.