WorldWideScience

Sample records for advanced stack hardware

  1. Hardware Evaluation of the Horizontal Exercise Fixture with Weight Stack

    Science.gov (United States)

    Newby, Nate; Leach, Mark; Fincke, Renita; Sharp, Carwyn

    2009-01-01

    HEF with weight stack seems to be a very sturdy and reliable exercise device that should function well in a bed rest training setting. A few improvements should be made to both the hardware and software to improve usage efficiency, but largely, this evaluation has demonstrated HEF's robustness. The hardware offers loading to muscles, bones, and joints, potentially sufficient to mitigate the loss of muscle mass and bone mineral density during long-duration bed rest campaigns. With some minor modifications, the HEF with weight stack equipment provides the best currently available means of performing squat, heel raise, prone row, bench press, and hip flexion/extension exercise in a supine orientation.

  2. Advanced hardware design for error correcting codes

    CERN Document Server

    Coussy, Philippe

    2015-01-01

    This book provides thorough coverage of error correcting techniques. It includes essential basic concepts and the latest advances on key topics in design, implementation, and optimization of hardware/software systems for error correction. The book’s chapters are written by internationally recognized experts in this field. Topics include evolution of error correction techniques, industrial user needs, architectures, and design approaches for the most advanced error correcting codes (Polar Codes, Non-Binary LDPC, Product Codes, etc). This book provides access to recent results, and is suitable for graduate students and researchers of mathematics, computer science, and engineering. • Examines how to optimize the architecture of hardware design for error correcting codes; • Presents error correction codes from theory to optimized architecture for the current and the next generation standards; • Provides coverage of industrial user needs advanced error correcting techniques.

  3. Implementation of Embedded Ethernet Based on Hardware Protocol Stack in Substation Automation System

    Institute of Scientific and Technical Information of China (English)

    MA Qiang; ZHAO Jianguo; LIU Bingxu

    2008-01-01

    Embedded Ethernet technology has been utilized increasingly widely as the communication mode in the substation automation system (SAS). This paper introduces the current applying situation about embedded Ethernet in SAS First. After analyzing the protocol levels used in SAS based on embedded Ethernet and the differences between the TCP and UDP, UDP/IP is selected as the communication protocol between the station-level and bay-level devices for its real-time characteristic. Then a new kind of implementation of the embedded Ethernet is presented based on hardware protocol stack. The designed scheme can be implemented easily, reduce cost significantly and shorten developing cycle.

  4. Project Beehive: A Hardware/Software Co-designed Stack for Runtime and Architectural Research

    OpenAIRE

    Kotselidis, Christos; Rodchenko, Andrey; Barrett, Colin; Nisbet, Andy; Mawer, John; Toms, Will; Clarkson, James; Gorgovan, Cosmin; d'Antras, Amanieu; Cakmakci, Yaman; Stratikopoulos, Thanos; Werner, Sebastian; Garside, Jim; Navaridas, Javier; Pop, Antoniu

    2015-01-01

    The end of Dennard scaling combined with stagnation in architectural and compiler optimizations makes it challenging to achieve significant performance deltas. Solutions based solely in hardware or software are no longer sufficient to maintain the pace of improvements seen during the past few decades. In hardware, the end of single-core scaling resulted in the proliferation of multi-core system architectures, however this has forced complex parallel programming techniques into the mainstream....

  5. Advanced Programming Platform for efficient use of Data Parallel Hardware

    CERN Document Server

    Cabellos, Luis

    2012-01-01

    Graphics processing units (GPU) had evolved from a specialized hardware capable to render high quality graphics in games to a commodity hardware for effective processing blocks of data in a parallel schema. This evolution is particularly interesting for scientific groups, which traditionally use mainly CPU as a work horse, and now can profit of the arrival of GPU hardware to HPC clusters. This new GPU hardware promises a boost in peak performance, but it is not trivial to use. In this article a programming platform designed to promote a direct use of this specialized hardware is presented. This platform includes a visual editor of parallel data flows and it is oriented to the execution in distributed clusters with GPUs. Examples of application in two characteristic problems, Fast Fourier Transform and Image Compression, are also shown.

  6. Fly-by-Light Advanced Systems Hardware (FLASH) program

    Science.gov (United States)

    Bedoya, Carlos A.

    1995-05-01

    hundreds of MHz are available. Applications of fiber optic buses would then result in the reduction of wires and connections because of reduction in the number of buses needed for information transfer due to the fact that a large number of different signals can be sent across one fiber by multiplexing each signal. The Advanced Research Projects Agency (ARPA) Technology Reinvestment Project (TRP) Fly-by-Light Advanced Systems Hardware (FLASH) program addresses the development of Fly-by-Light Technology in order to apply the benefits of fiber optics to military and commercial aircraft.

  7. Advances in Metered Dose Inhaler Technology: Hardware Development

    OpenAIRE

    Stein, Stephen W.; Sheth, Poonam; Hodson, P. David; Myrdal, Paul B.

    2013-01-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering ...

  8. Advances in metered dose inhaler technology: hardware development.

    Science.gov (United States)

    Stein, Stephen W; Sheth, Poonam; Hodson, P David; Myrdal, Paul B

    2014-04-01

    Pressurized metered dose inhalers (MDIs) were first introduced in the 1950s and they are currently widely prescribed as portable systems to treat pulmonary conditions. MDIs consist of a formulation containing dissolved or suspended drug and hardware needed to contain the formulation and enable efficient and consistent dose delivery to the patient. The device hardware includes a canister that is appropriately sized to contain sufficient formulation for the required number of doses, a metering valve capable of delivering a consistent amount of drug with each dose delivered, an actuator mouthpiece that atomizes the formulation and serves as a conduit to deliver the aerosol to the patient, and often an indicating mechanism that provides information to the patient on the number of doses remaining. This review focuses on the current state-of-the-art of MDI hardware and includes discussion of enhancements made to the device's core subsystems. In addition, technologies that aid the correct use of MDIs will be discussed. These include spacers, valved holding chambers, and breath-actuated devices. Many of the improvements discussed in this article increase the ability of MDI systems to meet regulatory specifications. Innovations that enhance the functionality of MDIs continue to be balanced by the fact that a key advantage of MDI systems is their low cost per dose. The expansion of the health care market in developing countries and the increased focus on health care costs in many developed countries will ensure that MDIs remain a cost-effective crucial delivery system for treating pulmonary conditions for many years to come. PMID:24357110

  9. Advanced Manufacturing Techniques Demonstrated for Fabricating Developmental Hardware

    Science.gov (United States)

    Redding, Chip

    2004-01-01

    NASA Glenn Research Center's Engineering Development Division has been working in support of innovative gas turbine engine systems under development by Glenn's Combustion Branch. These one-of-a-kind components require operation under extreme conditions. High-temperature ceramics were chosen for fabrication was because of the hostile operating environment. During the designing process, it became apparent that traditional machining techniques would not be adequate to produce the small, intricate features for the conceptual design, which was to be produced by stacking over a dozen thin layers with many small features that would then be aligned and bonded together into a one-piece unit. Instead of using traditional machining, we produced computer models in Pro/ENGINEER (Parametric Technology Corporation (PTC), Needham, MA) to the specifications of the research engineer. The computer models were exported in stereolithography standard (STL) format and used to produce full-size rapid prototype polymer models. These semi-opaque plastic models were used for visualization and design verification. The computer models also were exported in International Graphics Exchange Specification (IGES) format and sent to Glenn's Thermal/Fluids Design & Analysis Branch and Applied Structural Mechanics Branch for profiling heat transfer and mechanical strength analysis.

  10. Engineering aspects and hardware verification of a volume producable solid oxide fuel cell stack design for diesel auxiliary power units

    Science.gov (United States)

    Stelter, Michael; Reinert, Andreas; Mai, Björn Erik; Kuznecov, Mihail

    A solid oxide fuel cell (SOFC) stack module is presented that is designed for operation on diesel reformate in an auxiliary power unit (APU). The stack was designed using a top-down approach, based on a specification of an APU system that is installed on board of vehicles. The stack design is planar, modular and scalable with stamped sheet metal interconnectors. It features thin membrane electrode assemblies (MEAs), such as electrolyte supported cells (ESC) and operates at elevated temperatures around 800 °C. The stack has a low pressure drop in both the anode and the cathode to facilitate a simple system layout. An overview of the technical targets met so far is given. A stack power density of 0.2 kW l -1 has been demonstrated in a fully integrated, thermally self-sustaining APU prototype running with diesel and without an external water supply.

  11. Development of advanced driver assistance systems with vehicle hardware-in-the-loop simulations

    NARCIS (Netherlands)

    Gietelink, O.J.; Ploeg, J.; Schutter, B.de; Verhaegen, M.

    2006-01-01

    This paper presents a new method for the design and validation of advanced driver assistance systems (ADASs). With vehicle hardware-in-the-loop (VEHIL) simulations, the development process, and more specifically the validation phase, of intelligent vehicles is carried out safer, cheaper, and is more

  12. AN APPROACH TO DESIGN ADVANCED STANDARD ENCRYPTION ALGORITHM USING HARDWARE / SOFTWARE CO-DESIGN METHODOLOGY

    Directory of Open Access Journals (Sweden)

    MEGHANA A. HASAMNIS

    2012-05-01

    Full Text Available An Advanced Standard Encryption Algorithm (AES is widely used in modern consumer electronicproducts for security. The IEEE 802.15.4 Low-Rate wireless sensor networks also use AES algorithm wherelow power consumption is the priority. To reduce the time taken for encryption of huge data, the algorithm hasto be implemented in hardware. To meet the requirement for low area the algorithm has to be implemented insoftware. Hence, a balance has to be achieved between hardware and software implementations in terms of areaand speed, so as to improve the overall performance of the system. Also with the co-design methodology totalthermal power dissipation is reduced. In this paper, 128 bit AES algorithm is implemented with hardware incombination with software using Altera NIOS II Processor platform. Altera’s Quartus II environment is used fordesign of the system. Cyclone II FPGA is used as a development platform. Software program is written in C language. NIOS II ntegrated Development Environment (IDE is used to integrate hardware and software together. By adopting hardware / software co-design methodology for implementation of AES, results show that a onsiderable improvement in speed can be achieved as compared to software only approach. Further, the significant reduction in area is achieved as compared to hardware only approach. By the approach of co-design an optimized design in terms of speed and area is achieved and also the thermal power dissipation is reduced

  13. Recent advances in stacked inverted top-emitting organic electrophosphorescent diodes (presentation video)

    Science.gov (United States)

    Kippelen, Bernard; Knauer, Keith A.; Najafabadi, Ehsan M.; Zhou, Yinhua; Fuentes-Hernandez, Canek

    2014-10-01

    In this talk, we will discuss recent advances in green and white electrophosphorescent stacked organic light-emitting diodes (OLEDs) with inverted top-emitting structures. These devices combine the advantages of having inverted electrode positions, a top-emissive design, and a stacked architecture. We will also demonstrate OLEDs that are fabricated on cellulose nanocrystal substrates and discuss how the use of such naturally-derived materials can reduce the environmental footprint of organic electronic devices such as OLEDs.

  14. Advances in Single-Photon Emission Computed Tomography Hardware and Software.

    Science.gov (United States)

    Piccinelli, Marina; Garcia, Ernest V

    2016-02-01

    Nuclear imaging techniques remain today's most reliable modality for the assessment and quantification of myocardial perfusion. In recent years, the field has experienced tremendous progress both in terms of dedicated cameras for cardiac applications and software techniques for image reconstruction. The most recent advances in single-photon emission computed tomography hardware and software are reviewed, focusing on how these improvements have resulted in an even more powerful diagnostic tool with reduced injected radiation dose and acquisition time.

  15. Building an advanced climate model: Program plan for the CHAMMP (Computer Hardware, Advanced Mathematics, and Model Physics) Climate Modeling Program

    Energy Technology Data Exchange (ETDEWEB)

    1990-12-01

    The issue of global warming and related climatic changes from increasing concentrations of greenhouse gases in the atmosphere has received prominent attention during the past few years. The Computer Hardware, Advanced Mathematics, and Model Physics (CHAMMP) Climate Modeling Program is designed to contribute directly to this rapid improvement. The goal of the CHAMMP Climate Modeling Program is to develop, verify, and apply a new generation of climate models within a coordinated framework that incorporates the best available scientific and numerical approaches to represent physical, biogeochemical, and ecological processes, that fully utilizes the hardware and software capabilities of new computer architectures, that probes the limits of climate predictability, and finally that can be used to address the challenging problem of understanding the greenhouse climate issue through the ability of the models to simulate time-dependent climatic changes over extended times and with regional resolution.

  16. Software control of the Advanced Technology Solar Telescope enclosure PLC hardware using COTS software

    Science.gov (United States)

    Borrowman, Alastair J.; de Bilbao, Lander; Ariño, Javier; Murga, Gaizka; Goodrich, Bret; Hubbard, John R.; Greer, Alan; Mayer, Chris; Taylor, Philip

    2012-09-01

    As PLCs evolve from simple logic controllers into more capable Programmable Automation Controllers (PACs), observatories are increasingly using such devices to control complex mechanisms1, 2. This paper describes use of COTS software to control such hardware using the Advanced Technology Solar Telescope (ATST) Common Services Framework (CSF). We present the Enclosure Control System (ECS) under development in Spain and the UK. The paper details selection of the commercial PLC communication library PLCIO. Implemented in C and delivered with source code, the library separates the programmer from communication details through a simple API. Capable of communicating with many types of PLCs (including Allen-Bradley and Siemens) the API remains the same irrespective of PLC in use. The ECS is implemented in Java using the observatory's framework that provides common services for software components. We present a design following a connection-based approach where all components access the PLC through a single connection class. The link between Java and PLCIO C library is provided by a thin Java Native Interface (JNI) layer. Also presented is a software simulator of the PLC based upon the PLCIO Virtual PLC. This creates a simulator operating below the library's API and thus requires no change to ECS software. It also provides enhanced software testing capabilities prior to hardware becoming available. Results are presented in the form of communication timing test data, showing that the use of CSF, JNI and PLCIO provide a control system capable of controlling enclosure tracking mechanisms, that would be equally valid for telescope mount control.

  17. Backside versus frontside advanced chemical analysis of high-k/metal gate stacks

    Energy Technology Data Exchange (ETDEWEB)

    Martinez, E., E-mail: eugenie.martinez@cea.fr [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Saidi, B. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Veillerot, M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Caubet, P. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Fabbri, J-M. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Piallat, F. [STMicroelectronics, 850 rue Jean Monnet, 38926 Rousset Cedex, Crolles (France); Gassilloud, R. [Univ Grenoble Alpes, F-38000 Grenoble (France); CEA, LETI, MINATEC Campus, F-38054 Grenoble (France); Schamm-Chardon, S. [CEMES-CNRS et Université de Toulouse, 29 rue Jeanne Marvig, 31055 Toulouse (France)

    2015-08-15

    Highlights: • The backside approach is a promising solution for advanced chemical characterization of future MOSFETs. • Frontside ToF-SIMS and Auger depth profiles are affected by cumulative mixing effects and thus not relevant for analyzing ultra-thin layers. • Higher in-depth resolution is possible in the backside approach for Auger and ToF-SIMS depth profiling. • Backside depth profiling allows revealing ultra-thin layers and elemental in-depth redistribution inside high-k/metal gate stacks. • Backside XPS allows preserving the full metal gate, thus enabling the analysis of real technological samples. - Abstract: Downscaling of transistors beyond the 14 nm technological node requires the implementation of new architectures and materials. Advanced characterization methods are needed to gain information about the chemical composition of buried layers and interfaces. An effective approach based on backside analysis is presented here. X-ray photoelectron spectroscopy, Auger depth profiling and time-of-flight secondary ions mass spectrometry are combined to investigate inter-diffusion phenomena. To highlight improvements related to the backside method, backside and frontside analyses are compared. Critical information regarding nitrogen, oxygen and aluminium redistribution inside the gate stacks is obtained only in the backside configuration.

  18. Advances in hardware, software, and automation for 193nm aerial image measurement systems

    Science.gov (United States)

    Zibold, Axel M.; Schmid, R.; Seyfarth, A.; Waechter, M.; Harnisch, W.; Doornmalen, H. v.

    2005-05-01

    A new, second generation AIMS fab 193 system has been developed which is capable of emulating lithographic imaging of any type of reticles such as binary and phase shift masks (PSM) including resolution enhancement technologies (RET) such as optical proximity correction (OPC) or scatter bars. The system emulates the imaging process by adjustment of the lithography equivalent illumination and imaging conditions of 193nm wafer steppers including circular, annular, dipole and quadrupole type illumination modes. The AIMS fab 193 allows a rapid prediction of wafer printability of critical mask features, including dense patterns and contacts, defects or repairs by acquiring through-focus image stacks by means of a CCD camera followed by quantitative image analysis. Moreover the technology can be readily applied to directly determine the process window of a given mask under stepper imaging conditions. Since data acquisition is performed electronically, AIMS in many applications replaces the need for costly and time consuming wafer prints using a wafer stepper/ scanner followed by CD SEM resist or wafer analysis. The AIMS fab 193 second generation system is designed for 193nm lithography mask printing predictability down to the 65nm node. In addition to hardware improvements a new modular AIMS software is introduced allowing for a fully automated operation mode. Multiple pre-defined points can be visited and through-focus AIMS measurements can be executed automatically in a recipe based mode. To increase the effectiveness of the automated operation mode, the throughput of the system to locate the area of interest, and to acquire the through-focus images is increased by almost a factor of two in comparison with the first generation AIMS systems. In addition a new software plug-in concept is realised for the tools. One new feature has been successfully introduced as "Global CD Map", enabling automated investigation of global mask quality based on the local determination of

  19. Advanced Research and Education in Electrical Drives by Using Digital Real-Time Hardware-in-the-Loop Simulation

    DEFF Research Database (Denmark)

    Bojoi, R.; Profumo, F.; Griva, G.;

    2002-01-01

    drive has been implemented on the Evaluation Board of TMS320F240 DSP. The experimental results validate this solution as a powerful tool to be used in research and advanced education. Thus, the students can put in practic the theory without spending too much time with details concerning the hardware...

  20. System-Level Testing of the Advanced Stirling Radioisotope Generator Engineering Hardware

    Science.gov (United States)

    Chan, Jack; Wiser, Jack; Brown, Greg; Florin, Dominic; Oriti, Salvatore M.

    2014-01-01

    To support future NASA deep space missions, a radioisotope power system utilizing Stirling power conversion technology was under development. This development effort was performed under the joint sponsorship of the Department of Energy and NASA, until its termination at the end of 2013 due to budget constraints. The higher conversion efficiency of the Stirling cycle compared with that of the Radioisotope Thermoelectric Generators (RTGs) used in previous missions (Viking, Pioneer, Voyager, Galileo, Ulysses, Cassini, Pluto New Horizons and Mars Science Laboratory) offers the advantage of a four-fold reduction in Pu-238 fuel, thereby extending its limited domestic supply. As part of closeout activities, system-level testing of flight-like Advanced Stirling Convertors (ASCs) with a flight-like ASC Controller Unit (ACU) was performed in February 2014. This hardware is the most representative of the flight design tested to date. The test fully demonstrates the following ACU and system functionality: system startup; ASC control and operation at nominal and worst-case operating conditions; power rectification; DC output power management throughout nominal and out-of-range host voltage levels; ACU fault management, and system command / telemetry via MIL-STD 1553 bus. This testing shows the viability of such a system for future deep space missions and bolsters confidence in the maturity of the flight design.

  1. Computer Hardware, Advanced Mathematics and Model Physics pilot project final report

    International Nuclear Information System (INIS)

    The Computer Hardware, Advanced Mathematics and Model Physics (CHAMMP) Program was launched in January, 1990. A principal objective of the program has been to utilize the emerging capabilities of massively parallel scientific computers in the challenge of regional scale predictions of decade-to-century climate change. CHAMMP has already demonstrated the feasibility of achieving a 10,000 fold increase in computational throughput for climate modeling in this decade. What we have also recognized, however, is the need for new algorithms and computer software to capitalize on the radically new computing architectures. This report describes the pilot CHAMMP projects at the DOE National Laboratories and the National Center for Atmospheric Research (NCAR). The pilot projects were selected to identify the principal challenges to CHAMMP and to entrain new scientific computing expertise. The success of some of these projects has aided in the definition of the CHAMMP scientific plan. Many of the papers in this report have been or will be submitted for publication in the open literature. Readers are urged to consult with the authors directly for questions or comments about their papers

  2. Recent advances in hardware and software are to improve spent fuel measurements

    International Nuclear Information System (INIS)

    Vast quantities of spent fuel are available for safeguard measurements, primarily in Commonwealth of Independent States (CIS) of the former Soviet Union. This spent fuel, much of which consists of long-cooling-time material, is going to become less unique in the world safeguards arena as reprocessing projects or permanent repositories continue to be delayed or postponed. The long cooling time of many of the spent fuel assemblies being prepared for intermediate term storage in the CIS countries promotes the possibility of increased accuracy in spent fuel assays. This improvement is made possible through the process of decay of the Curium isotopes and of fission products. An important point to consider for the future that could advance safeguards measurements for reverification and inspection would be to determine what safeguards requirements should be imposed upon this 'new' class of spent fuel, Improvements in measurement capability will obviously affect the safeguards requirements. What most significantly enables this progress in spent fuel measurements is the improvement in computer processing power and software enhancements leading to user-friendly Graphical User Interfaces (GUT's). The software used for these projects significantly reduces the IAEA inspector's time expenditure for both learning and operating computer and data acquisition systems, At the same time, by standardizing the spent fuel measurements, it is possible to increase reproducibility and reliability of the measurement data. Hardware systems will be described which take advantage of the increased computer control available to enable more complex measurement scenarios. A specific example of this is the active regulation of a spent fuel neutron coincident counter's 3He tubes high voltage, and subsequent scaling of measurement results to maintain a calibration for direct assay of the plutonium content of Fast Breeder Reactor spent fuel. The plutonium content has been successfully determined for

  3. Asynchronous Advanced Encryption Standard Hardware with Random Noise Injection for Improved Side-Channel Attack Resistance

    Directory of Open Access Journals (Sweden)

    Siva Kotipalli

    2014-01-01

    (SCA resistance. These designs are based on a delay-insensitive (DI logic paradigm known as null convention logic (NCL, which supports useful properties for resisting SCAs including dual-rail encoding, clock-free operation, and monotonic transitions. Potential benefits include reduced and more uniform switching activities and reduced signal-to-noise (SNR ratio. A novel method to further augment NCL AES hardware with random voltage scaling technique is also presented for additional security. Thereby, the proposed components leak significantly less side-channel information than conventional clocked approaches. To quantitatively verify such improvements, functional verification and WASSO (weighted average simultaneous switching output analysis have been carried out on both conventional synchronous approach and the proposed NCL based approach using Mentor Graphics ModelSim and Xilinx simulation tools. Hardware implementation has been carried out on both designs exploiting a specified side-channel attack standard evaluation FPGA board, called SASEBO-GII, and the corresponding power waveforms for both designs have been collected. Along with the results of software simulations, we have analyzed the collected waveforms to validate the claims related to benefits of the proposed cryptohardware design approach.

  4. Advanced Photovoltaic Inverter Functionality using 500 kW Power Hardware-in-Loop Complete System Laboratory Testing: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Mather, B. A.; Kromer, M. A.; Casey, L.

    2013-01-01

    With the increasing penetration of distribution connected photovoltaic (PV) systems, more and more PV developers and utilities are interested in easing future PV interconnection concerns by mitigating some of the impacts of PV integration using advanced PV inverter controls and functions. This paper describes the testing of a 500 kW PV inverter using Power Hardware-in-Loop (PHIL) testing techniques. The test setup is described and the results from testing the inverter in advanced functionality modes, not commonly used in currently interconnected PV systems, are presented. PV inverter operation under PHIL evaluation that emulated both the DC PV array connection and the AC distribution level grid connection are shown for constant power factor (PF) and constant reactive power (VAr) control modes. The evaluation of these modes was completed under varying degrees of modeled PV variability.

  5. Dry etching of poly-Si/TaN/HfSiON gate stack for advanced complementarymetal-oxide-semiconductor devices

    Institute of Scientific and Technical Information of China (English)

    Li Yongliang; Xu Qiuxia

    2011-01-01

    A novel dry etching process of a poly-Si/TaN/HfSiON gate stack for advanced complementary metal-oxide-semiconductor (CMOS) devices is investigated.Our strategy to process a poly-Si/TaN/HfSiON gate stack is that each layer of gate stack is selectively etched with a vertical profile.First,a three-step plasma etching process is developed to get a vertical poly-Si profile and a reliable etch-stop on a TaN metal gate.Then different BCl3-based plasmas are applied to etch the TaN metal gate and find that BC13/Cl2/O2/Ar plasma is a suitable choice to get a vertical TaN profile.Moreover,considering that C12 almost has no selectivity to Si substrate,BCl3/Ar plasma is applied to etch HfSiON dielectric to improve the selectivity to Si substrate after the TaN metal gate is vertically etched off by the optimized BCl3/Cl2/O2/Ar plasma.Finally,we have succeeded in etching a poly-Si/TaN/HfSiON stack with a vertical profile and almost no Si loss utilizing these new etching technologies.

  6. Hardware Implementation of AES

    Directory of Open Access Journals (Sweden)

    Aakrati Chaturvedi

    2014-01-01

    Full Text Available The Advanced Encryption Standard algorithm can be efficiently programmed in software and implemented in hardware. Field Programmable Gate Array (FPGA devices are considered as efficient and cost effective solution for hardware. This research is in context to efficient hardware implementation of AES algorithm with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. This research is in context to efficient hardware implementation of AES algorithm with 128-192-256 key all in one module with language platform as VHDL (Very High Speed Integrated Circuit Hardware Description language. The software part has been created, processed and simulated through Xilinx ISE 9.2. A compact design approach has been chosen to implement the algorithm with minimal hardware. As for hardware, Spartan 3AN family device (XC3S700A device is used

  7. Zhejiang Star Tools Co., Ltd., One Star Advanced in All Hardwares

    Institute of Scientific and Technical Information of China (English)

    Wang Gang

    2006-01-01

    @@ Zhejiang Star Tools Co., Ltd. was sponsored in 1994. Situated in Yiwu city, Zhejiang province, it is very famous of the production of chrome & vanadium-alloy steel sleeve. The company is aiming at international advanced level. In September, China's Foreign Trade interviewed Mr. Zhou Fushou, Board Chairman of Zhejiang Star Tools Co., Ltd.

  8. Energy-Efficient Hardware Architectures for the Packet Data Convergence Protocol in LTE-Advanced Mobile Terminals

    Directory of Open Access Journals (Sweden)

    Shadi Traboulsi

    2013-01-01

    Full Text Available In this paper, we present and compare efficient low-power hardware architectures for accelerating the Packet Data Convergence Protocol (PDCP in LTE and LTE-Advanced mobile terminals. Specifically, our work proposes the design of two cores: a crypto engine for the Evolved Packet System Encryption Algorithm (128-EEA2 that is based on the AES cipher and a coprocessor for the Least Significant Bit (LSB encoding mechanism of the Robust Header Compression (ROHC algorithm. With respect to the former, first we propose a reference architecture, which reflects a basic implementation of the algorithm, then we identify area and power bottle-necks in the design and finally we introduce and compare several architectures targeting the most power-consuming operations. With respect to the LSB coprocessor, we propose a novel implementation based on a one-hot encoding, thereby reducing hardware’s logic switching rate. Architectural hardware analysis is performed using Faraday’s 90 nm standard-cell library. The obtained results, when compared against the reference architecture, show that these novel architectures achieve significant improvements, namely, 25% in area and 35% in power consumption for the 128-EEA2 crypto-core, and even more important reductions are seen for the LSB coprocessor, that is, 36% in area and 50% in power consumption.

  9. Parabolic Flight Investigation for Advanced Exercise Concept Hardware Hybrid Ultimate Lifting Kit (HULK)

    Science.gov (United States)

    Weaver, A. S.; Funk, J. H.; Funk, N. W.; Sheehan, C. C.; Humphreys, B. T.; Perusek, G. P.

    2015-01-01

    Long-duration space flight poses many hazards to the health of the crew. Among those hazards is the physiological deconditioning of the musculoskeletal and cardiovascular systems due to prolonged exposure to microgravity. To combat this erosion of physical condition space flight may take on the crew, the Human Research Program (HRP) is charged with developing Advanced Exercise Concepts to maintain astronaut health and fitness during long-term missions, while keeping device mass, power, and volume to a minimum. The goal of this effort is to preserve the physical capability of the crew to perform mission critical tasks in transit and during planetary surface operations. The HULK is a pneumatic-based exercise system, which provides both resistive and aerobic modes to protect against human deconditioning in microgravity. Its design targeted the International Space Station (ISS) Advanced Resistive Exercise Device (ARED) high level performance characteristics and provides up to 600 foot pounds resitive loading with the capability to allow for eccentric to concentric (E:C) ratios of higher than 1:1 through a DC motor assist component. The device's rowing mode allows for high cadence aerobic activity. The HULK parabolic flight campaign, conducted through the NASA Flight Opportunities Program at Ellington Field, resulted in the creation of device specific data sets including low fidelity motion capture, accelerometry and both inline and ground reaction forces. These data provide a critical link in understanding how to vibration isolate the device in both ISS and space transit applications. Secondarily, the study of human exercise and associated body kinematics in microgravity allows for more complete understanding of human to machine interface designs to allow for maximum functionality of the device in microgravity.

  10. Advanced InSAR atmospheric correction: MERIS/MODIS combination and stacked water vapour models

    OpenAIRE

    Z. Li; Fielding, E.; Cross, P; R. Preusker

    2009-01-01

    A major source of error for repeat-pass Interferometric Synthetic Aperture Radar (InSAR) is the phase delay in radio signal propagation through the atmosphere (especially the part due to tropospheric water vapour). Based on experience with the Global Positioning System (GPS)/Moderate Resolution Imaging Spectroradiometer (MODIS) integrated model and the Medium Resolution Imaging Spectrometer (MERIS) correction model, two new advanced InSAR water vapour correction models are demonstrated using ...

  11. On the interest of carbon-coated plasma reactor for advanced gate stack etching processes

    International Nuclear Information System (INIS)

    In integrated circuit fabrication the most wide spread strategy to achieve acceptable wafer-to-wafer reproducibility of the gate stack etching process is to dry-clean the plasma reactor walls between each wafer processed. However, inherent exposure of the reactor walls to fluorine-based plasma leads to formation and accumulation of nonvolatile fluoride residues (such as AlFx) on reactor wall surfaces, which in turn leads to process drifts and metallic contamination of wafers. To prevent this while keeping an Al2O3 reactor wall material, a coating strategy must be used, in which the reactor is coated by a protective layer between wafers. It was shown recently that deposition of carbon-rich coating on the reactor walls allows improvements of process reproducibility and reactor wall protection. The authors show that this strategy results in a higher ion-to-neutral flux ratio to the wafer when compared to other strategies (clean or SiOClx-coated reactors) because the carbon walls load reactive radical densities while keeping the same ion current. As a result, the etching rates are generally smaller in a carbon-coated reactor, but a highly anisotropic etching profile can be achieved in silicon and metal gates, whose etching is strongly ion assisted. Furthermore, thanks to the low density of Cl atoms in the carbon-coated reactor, silicon etching can be achieved almost without sidewall passivation layers, allowing fine critical dimension control to be achieved. In addition, it is shown that although the O atom density is also smaller in the carbon-coated reactor, the selectivity toward ultrathin gate oxides is not reduced dramatically. Furthermore, during metal gate etching over high-k dielectric, the low level of parasitic oxygen in the carbon-coated reactor also allows one to minimize bulk silicon reoxidation through HfO2 high-k gate dielectric. It is then shown that the BCl3 etching process of the HfO2 high-k material is highly selective toward the substrate in the

  12. Stacking structures and electrode performances of rare earth-Mg-Ni-based alloys for advanced nickel-metal hydride battery

    International Nuclear Information System (INIS)

    Rare earth-Mg-Ni-based alloys with stacking structures consisting of AB5 unit (CaCu5-type structure) and A2B4 unit (Laves structure) have received attention as negative electrode materials for advanced nickel-metal hydride (Ni-MH) battery. These alloy materials are very attractive because of high hydrogen storage capacity, low cobalt content and moderate plateau pressure, but have some difficulty to control the phase abundance and electrode performances. In this paper, relationship among composition, phase abundance, and electrochemical properties was investigated. Structural analysis was done using synchrotron X-ray diffraction patterns. In alloys such as La0.8Mg0.2Ni3.4-x-yCo0.3(MnAl)x (0 ≤ x ≤ 0.4), phase abundance was drastically changed with increasing amount of Mn and Al. In the range of 0.1 5Co19-type (5:19H) or rhombohedral 1:4R phases were dominant. The Rietveld analysis suggested that Mg occupies La sites in A2B4 unit, and Al has tendency to occupy Ni sites between A2B4 unit and AB5 unit or between AB5 units in these types of phases. The developed alloys showed higher discharge capacity by 20% than the conventional one at a 0.2 C discharge rate

  13. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop (Poster)

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.

    2013-02-01

    This poster describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1TM. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  14. Hardware malware

    CERN Document Server

    Krieg, Christian

    2013-01-01

    In our digital world, integrated circuits are present in nearly every moment of our daily life. Even when using the coffee machine in the morning, or driving our car to work, we interact with integrated circuits. The increasing spread of information technology in virtually all areas of life in the industrialized world offers a broad range of attack vectors. So far, mainly software-based attacks have been considered and investigated, while hardware-based attacks have attracted comparatively little interest. The design and production process of integrated circuits is mostly decentralized due to

  15. Algebraic Stacks

    Indian Academy of Sciences (India)

    Tomás L Gómez

    2001-02-01

    This is an expository article on the theory of algebraic stacks. After introducing the general theory, we concentrate in the example of the moduli stack of vector bundles, giving a detailed comparison with the moduli scheme obtained via geometric invariant theory.

  16. Qualification issues associated with the use of advanced instrumentation and control systems hardware in nuclear power plants

    International Nuclear Information System (INIS)

    The instrumentation and control (I ampersand C) systems in advanced reactors will make extensive use of digital controls, microprocessors, multiplexing, and fiber-optic transmission. Elements of these advances in I ampersand C have been implemented on some current operating plants. However, the widespread use of the above technologies, as well as the use of artificial intelligence with minimum reliance on human operator control of reactors, highlights the need to develop standards for qualifying I ampersand C used in the next generation of nuclear power plants. As a first step in this direction, the protection system I ampersand C for present-day plants was compared to that proposed for advanced light water reactors (ALWRs). An evaluation template was developed by assembling a configuration of a safety channel instrument string for a generic ALWR, then comparing the impact of environmental stressors on that string to their effect on an equivalent instrument string from an existing light water reactor. The template was then used to address reliability issues for microprocessor-based protection systems. Standards (or lack thereof) for the qualification of microprocessor-based safety I ampersand C systems were also identified. This approach addresses in part issues raised in Nuclear Regulatory Commission policy document SECY-91-292, which recognizes that advanced I ampersand C systems for the nuclear industry are open-quotes being developed without consensus standards, as the technology available for design is ahead of the technology that is well understood through experience and supported by application standards.close quotes

  17. A Level-1 Tracking Trigger for the CMS upgrade using stacked silicon strip detectors and advanced pattern technologies

    Science.gov (United States)

    Boudoul, G.

    2013-01-01

    Experience at high luminosity hadrons collider experiments shows that tracking information enhances the trigger rejection capabilities while retaining high efficiency for interesting physics events. The design of a tracking based trigger for the High Luminosity LHC (HL-LHC) is an extremely challenging task, and requires the identification of high-momentum particle tracks as a part of the Level 1 Trigger. Simulation studies show that this can be achieved by correlating hits on two closely spaced silicon strip sensors, and reconstructing tracks at L1 by employing an Associative Memory approach. The progresses on the design and development of this micro-strip stacked prototype modules and the performance of few prototype detectors will be presented. Preliminary results of a simulated tracker layout equipped with stacked modules are discussed in terms of pT resolution and triggering capabilities. Finally, a discussion on the L1 architecture will be given.

  18. Advancement of Piezo-Stack DM technology at CILAS: Example of HODM for KIS Gregor Solar Telescope

    Science.gov (United States)

    Sinquin, J. C.; Bastard, A.; Cousty, R.; Guillemard, C.; Pagès, H.

    2011-09-01

    Cilas has designed, manufactured and tested the deformable mirror for use in the high order adaptive optics system in the 1.5 m Gregor solar telescope (Tenerife). In the scope of this project for Kiepenheuer-Institut für Sonnenphysik (KIS), we have reached the smallest spacing ever made with our piezo-stack technology (3.2 mm) while increasing the overall reliability of our DMs by significant design evolutions. We will present the main specifications of the DM (18x18 actuator array, > 2 μm interactuator stroke, > 20 kHz main resonance frequency) and the study results on reliability. This study is focused on electrical and opto-mechanical stability of the DM vs. time. The improved piezo-stack technology will be used for next generation of DMs for large telescopes as TMT and ESO (VLT and E-ELT)

  19. An Advanced Hardware Realization of Motion Estimation%一种先进运动估计算法的硬件实现

    Institute of Scientific and Technical Information of China (English)

    江飞; 杨奕; 杨兵

    2012-01-01

    文中介绍了一种先进运动估计处理(MEP)的算法实现。所介绍的MEP用于图像间的运动估计,它计算参考图像在搜索图像区域中不同位移时,两幅图像对应像素点亮度信息的差值之和,并选取最小值作为运动向量。而其硬件实现则采用较先进的处理单元阵列,外挂DSP处理器和外置SRAM存储器,所以算法处理速度可以迅速加快,相反硬件实现的面积也较小。%An advanced hardware realization technique of motion estimation between two images,materially is realized by choosing a better motion vector, which is the smallest one of all the sums between two relative piels belonging to two images separately while computing the motion vector of referencing image in searching image field.So its compute speeds up and realization area is relative small by adopting advanced processor element arrays and external dsp and sram.

  20. Laser-plasma acceleration with multi-color pulse stacks: Designer electron beams for advanced radiation sources

    Science.gov (United States)

    Kalmykov, Serge; Shadwick, Bradley; Ghebregziabher, Isaac; Davoine, Xavier

    2015-11-01

    Photon engineering offers new avenues to coherently control electron beam phase space on a femtosecond time scale. It enables generation of high-quality beams at a kHz-scale repetition rate. Reducing the peak pulse power (and thus the average laser power) is the key to effectively exercise such control. A stepwise negative chirp, synthesized by incoherently stacking collinear sub-Joule pulses from conventional CPA, affords a micron-scale bandwidth. It is sufficient to prevent rapid compression of the pulse into an optical shock, while delaying electron dephasing. This extends electron energy far beyond the limits suggested by accepted scalings (beyond 1 GeV in a 3 mm plasma), without compromising beam quality. In addition, acceleration with a stacked pulse in a channel favorably modifies electron beam on a femtosecond time scale, controllably producing synchronized sequences of 100 kA-scale, quasi-monoenergetic bunches. These comb-like, designer GeV electron beams are ideal drivers of polychromatic, tunable inverse Thomson γ-ray sources. The work of SYK and BAS is supported by the US DOE Grant DE-SC0008382 and NSF Grant PHY-1104683. Inverse Thomson scattering simulations were completed utilizing the Holland Computing Center of the University of Nebraska.

  1. A Time-predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation...... of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures....

  2. Sensing with Advanced Computing Technology: Fin Field-Effect Transistors with High-k Gate Stack on Bulk Silicon.

    Science.gov (United States)

    Rigante, Sara; Scarbolo, Paolo; Wipf, Mathias; Stoop, Ralph L; Bedner, Kristine; Buitrago, Elizabeth; Bazigos, Antonios; Bouvet, Didier; Calame, Michel; Schönenberger, Christian; Ionescu, Adrian M

    2015-05-26

    Field-effect transistors (FETs) form an established technology for sensing applications. However, recent advancements and use of high-performance multigate metal-oxide semiconductor FETs (double-gate, FinFET, trigate, gate-all-around) in computing technology, instead of bulk MOSFETs, raise new opportunities and questions about the most suitable device architectures for sensing integrated circuits. In this work, we propose pH and ion sensors exploiting FinFETs fabricated on bulk silicon by a fully CMOS compatible approach, as an alternative to the widely investigated silicon nanowires on silicon-on-insulator substrates. We also provide an analytical insight of the concept of sensitivity for the electronic integration of sensors. N-channel fully depleted FinFETs with critical dimensions on the order of 20 nm and HfO2 as a high-k gate insulator have been developed and characterized, showing excellent electrical properties, subthreshold swing, SS ∼ 70 mV/dec, and on-to-off current ratio, Ion/Ioff ∼ 10(6), at room temperature. The same FinFET architecture is validated as a highly sensitive, stable, and reproducible pH sensor. An intrinsic sensitivity close to the Nernst limit, S = 57 mV/pH, is achieved. The pH response in terms of output current reaches Sout = 60%. Long-term measurements have been performed over 4.5 days with a resulting drift in time δVth/δt = 0.10 mV/h. Finally, we show the capability to reproduce experimental data with an extended three-dimensional commercial finite element analysis simulator, in both dry and wet environments, which is useful for future advanced sensor design and optimization.

  3. Capping stack: An industry in the making

    Institute of Scientific and Technical Information of China (English)

    Jack Chen; Li Xunke; Xie Wenhui; Kang Yongtian

    2013-01-01

    This paper gives an overview of recent development of the marine well containment system (MWCS)after BP Macondo subsea well blowout occurred on April 20,2010 in the Gulf of Mexico.Capping stack,a hardware utilized to contain blowout well at or near the wellhead is the center piece of MWCS.Accessibility to the dedicated capping stacks is gradually becoming a pre-requirement to obtain the permit for offshore drilling/workover,and the industry for manufacturing,maintenance,transportation and operation of the capping stack is in the making.

  4. A Time-predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspour, Sahar; Brandner, Florian; Schoeberl, Martin

    2013-01-01

    Real-time systems need time-predictable architectures to support static worst-case execution time (WCET) analysis. One architectural feature, the data cache, is hard to analyze when different data areas (e.g., heap allocated and stack allocated data) share the same cache. This sharing leads to less...... precise results of the cache analysis part of the WCET analysis. Splitting the data cache for different data areas enables composable data cache analysis. The WCET analysis tool can analyze the accesses to these different data areas independently. In this paper we present the design and implementation...... of a cache for stack allocated data. Our port of the LLVM C++ compiler supports the management of the stack cache. The combination of stack cache instructions and the hardware implementation of the stack cache is a further step towards timepredictable architectures....

  5. Introduction to Hardware Security

    Directory of Open Access Journals (Sweden)

    Yier Jin

    2015-10-01

    Full Text Available Hardware security has become a hot topic recently with more and more researchers from related research domains joining this area. However, the understanding of hardware security is often mixed with cybersecurity and cryptography, especially cryptographic hardware. For the same reason, the research scope of hardware security has never been clearly defined. To help researchers who have recently joined in this area better understand the challenges and tasks within the hardware security domain and to help both academia and industry investigate countermeasures and solutions to solve hardware security problems, we will introduce the key concepts of hardware security as well as its relations to related research topics in this survey paper. Emerging hardware security topics will also be clearly depicted through which the future trend will be elaborated, making this survey paper a good reference for the continuing research efforts in this area.

  6. Hardware removal - extremity

    Science.gov (United States)

    ... this page: //medlineplus.gov/ency/article/007644.htm Hardware removal - extremity To use the sharing features on this page, please enable JavaScript. Surgeons use hardware such as pins, plates, or screws to help ...

  7. Computer Center: 2 HyperCard Stacks for Biology.

    Science.gov (United States)

    Duhrkopf, Richard, Ed.

    1989-01-01

    Two Hypercard stacks are reviewed including "Amino Acids," created to help students associate amino acid names with their structures, and "DNA Teacher," a tutorial on the structure and function of DNA. Availability, functions, hardware requirements, and general comments on these stacks are provided. (CW)

  8. Proceedings of the Twenty-First Water Reactor Safety Information Meeting: Volume 1, Plenary session; Advanced reactor research; advanced control system technology; advanced instrumentation and control hardware; human factors research; probabilistic risk assessment topics; thermal hydraulics; thermal hydraulic research for advanced passive LWRs

    International Nuclear Information System (INIS)

    This three-volume report contains 90 papers out of the 102 that were presented at the Twenty-First Water Reactor Safety Information Meeting held at the Bethesda Marriott Hotel, Bethesda, Maryland, during the week of October 25--27, 1993. The papers are printed in the order of their presentation in each session and describe progress and results of programs in nuclear safety research conducted in this country and abroad. Foreign participation in the meeting included papers presented by researchers from France, Germany, Japan, Russia, Switzerland, Taiwan, and United Kingdom. The titles of the papers and the names of the authors have been updated and may differ from those that appeared in the final program of the meeting. Individual papers have been cataloged separately. This document, Volume 1 covers the following topics: Advanced Reactor Research; Advanced Instrumentation and Control Hardware; Advanced Control System Technology; Human Factors Research; Probabilistic Risk Assessment Topics; Thermal Hydraulics; and Thermal Hydraulic Research for Advanced Passive Light Water Reactors

  9. Proceedings of the Twenty-First Water Reactor Safety Information Meeting: Volume 1, Plenary session; Advanced reactor research; advanced control system technology; advanced instrumentation and control hardware; human factors research; probabilistic risk assessment topics; thermal hydraulics; thermal hydraulic research for advanced passive LWRs

    Energy Technology Data Exchange (ETDEWEB)

    Monteleone, S. [Brookhaven National Lab., Upton, NY (United States)] [comp.

    1994-04-01

    This three-volume report contains 90 papers out of the 102 that were presented at the Twenty-First Water Reactor Safety Information Meeting held at the Bethesda Marriott Hotel, Bethesda, Maryland, during the week of October 25--27, 1993. The papers are printed in the order of their presentation in each session and describe progress and results of programs in nuclear safety research conducted in this country and abroad. Foreign participation in the meeting included papers presented by researchers from France, Germany, Japan, Russia, Switzerland, Taiwan, and United Kingdom. The titles of the papers and the names of the authors have been updated and may differ from those that appeared in the final program of the meeting. Individual papers have been cataloged separately. This document, Volume 1 covers the following topics: Advanced Reactor Research; Advanced Instrumentation and Control Hardware; Advanced Control System Technology; Human Factors Research; Probabilistic Risk Assessment Topics; Thermal Hydraulics; and Thermal Hydraulic Research for Advanced Passive Light Water Reactors.

  10. Evaluating IP security on lightweight hardware

    OpenAIRE

    Khurri, Andrey

    2011-01-01

    TCP/IP communications stack is being increasingly used to interconnect mobile phones, PDAs, sensor motes and other wireless embedded devices. Although the core functionality of communications protocols has been successfully adopted to lightweight hardware from the traditional Internet and desktop computers, suitability of strong security mechanisms on such devices remains questionable. Insufficient processor, memory and battery resources, as well as constraints of wireless communications limi...

  11. Time-predictable Stack Caching

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar

    completely. Thus, in systems with hard deadlines the worst-case execution time (WCET) of the real-time software running on them needs to be bounded. Modern architectures use features such as pipelining and caches for improving the average performance. These features, however, make the WCET analysis more...... keeping the timepredictability of the design intact. Moreover, we provide a solution for reducing the cost of context switching in a system using the stack cache. In design of these caches, we use custom hardware and compiler support for delivering time-predictable stack data accesses. Furthermore......Embedded systems are computing systems for controlling and interacting with physical environments. Embedded systems with special timing constraints where the system needs to meet deadlines are referred to as real-time systems. In hard real-time systems, missing a deadline causes the system to fail...

  12. GENI: Grid Hardware and Software

    Energy Technology Data Exchange (ETDEWEB)

    None

    2012-01-09

    GENI Project: The 15 projects in ARPA-E’s GENI program, short for “Green Electricity Network Integration,” aim to modernize the way electricity is transmitted in the U.S. through advances in hardware and software for the electric grid. These advances will improve the efficiency and reliability of electricity transmission, increase the amount of renewable energy the grid can utilize, and provide energy suppliers and consumers with greater control over their power flows in order to better manage peak power demand and cost.

  13. Open Hardware Business Models

    OpenAIRE

    Edy Ferreira

    2008-01-01

    In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  14. Open Hardware Business Models

    Directory of Open Access Journals (Sweden)

    Edy Ferreira

    2008-04-01

    Full Text Available In the September issue of the Open Source Business Resource, Patrick McNamara, president of the Open Hardware Foundation, gave a comprehensive introduction to the concept of open hardware, including some insights about the potential benefits for both companies and users. In this article, we present the topic from a different perspective, providing a classification of market offers from companies that are making money with open hardware.

  15. Electrochemical cell stack assembly

    Science.gov (United States)

    Jacobson, Craig P.; Visco, Steven J.; De Jonghe, Lutgard C.

    2010-06-22

    Multiple stacks of tubular electrochemical cells having a dense electrolyte disposed between an anode and a cathode preferably deposited as thin films arranged in parallel on stamped conductive interconnect sheets or ferrules. The stack allows one or more electrochemical cell to malfunction without disabling the entire stack. Stack efficiency is enhanced through simplified gas manifolding, gas recycling, reduced operating temperature and improved heat distribution.

  16. Flight Avionics Hardware Roadmap

    Science.gov (United States)

    Some, Raphael; Goforth, Monte; Chen, Yuan; Powell, Wes; Paulick, Paul; Vitalpur, Sharada; Buscher, Deborah; Wade, Ray; West, John; Redifer, Matt; Partridge, Harry; Sherman, Aaron; McCabe, Mary

    2014-01-01

    The Avionics Technology Roadmap takes an 80% approach to technology investment in spacecraft avionics. It delineates a suite of technologies covering foundational, component, and subsystem-levels, which directly support 80% of future NASA space mission needs. The roadmap eschews high cost, limited utility technologies in favor of lower cost, and broadly applicable technologies with high return on investment. The roadmap is also phased to support future NASA mission needs and desires, with a view towards creating an optimized investment portfolio that matures specific, high impact technologies on a schedule that matches optimum insertion points of these technologies into NASA missions. The roadmap looks out over 15+ years and covers some 114 technologies, 58 of which are targeted for TRL6 within 5 years, with 23 additional technologies to be at TRL6 by 2020. Of that number, only a few are recommended for near term investment: 1. Rad Hard High Performance Computing 2. Extreme temperature capable electronics and packaging 3. RFID/SAW-based spacecraft sensors and instruments 4. Lightweight, low power 2D displays suitable for crewed missions 5. Radiation tolerant Graphics Processing Unit to drive crew displays 6. Distributed/reconfigurable, extreme temperature and radiation tolerant, spacecraft sensor controller and sensor modules 7. Spacecraft to spacecraft, long link data communication protocols 8. High performance and extreme temperature capable C&DH subsystem In addition, the roadmap team recommends several other activities that it believes are necessary to advance avionics technology across NASA: center dot Engage the OCT roadmap teams to coordinate avionics technology advances and infusion into these roadmaps and their mission set center dot Charter a team to develop a set of use cases for future avionics capabilities in order to decouple this roadmap from specific missions center dot Partner with the Software Steering Committee to coordinate computing hardware

  17. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III - Grid Interconnection System Evaluator

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1. The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  18. Advanced Platform for Development and Evaluation of Grid Interconnection Systems Using Hardware-in-the-Loop: Part III -- Grid Interconnection System Evaluator: Preprint

    Energy Technology Data Exchange (ETDEWEB)

    Lundstrom, B.; Shirazi, M.; Coddington, M.; Kroposki, B.

    2013-01-01

    This paper, presented at the IEEE Green Technologies Conference 2013, describes a Grid Interconnection System Evaluator (GISE) that leverages hardware-in-the-loop (HIL) simulation techniques to rapidly evaluate the grid interconnection standard conformance of an ICS according to the procedures in IEEE Std 1547.1 (TM). The architecture and test sequencing of this evaluation tool, along with a set of representative ICS test results from three different photovoltaic (PV) inverters, are presented. The GISE adds to the National Renewable Energy Laboratory's (NREL) evaluation platform that now allows for rapid development of ICS control algorithms using controller HIL (CHIL) techniques, the ability to test the dc input characteristics of PV-based ICSs through the use of a PV simulator capable of simulating real-world dynamics using power HIL (PHIL), and evaluation of ICS grid interconnection conformance.

  19. Investigation of a Superscalar Operand Stack Using FO4 and ASIC Wire-Delay Metrics

    Directory of Open Access Journals (Sweden)

    Christopher Bailey

    2014-01-01

    Full Text Available Complexity in processor microarchitecture and the related issues of power density, hot spots and wire delay, are seen to be a major concern for design migration into low nanometer technologies of the future. This paper evaluates the hardware cost of an alternative to register-file organization, the superscalar stack issue array (SSIA. We believe this is the first such reported study using discrete stack elements. Several possible implementations are evaluated, using a 90 nm standard cell library as a reference model, yielding delay data and FO4 metrics. The evaluation, including reference to ASIC layout, RC extraction, and timing simulation, suggests a 4-wide issue rate of at least four Giga-ops/sec at 90 nm and opportunities for twofold future improvement by using more advanced design approaches.

  20. Hardware Accelerated Power Estimation

    CERN Document Server

    Coburn, Joel; Raghunathan, Anand

    2011-01-01

    In this paper, we present power emulation, a novel design paradigm that utilizes hardware acceleration for the purpose of fast power estimation. Power emulation is based on the observation that the functions necessary for power estimation (power model evaluation, aggregation, etc.) can be implemented as hardware circuits. Therefore, we can enhance any given design with "power estimation hardware", map it to a prototyping platform, and exercise it with any given test stimuli to obtain power consumption estimates. Our empirical studies with industrial designs reveal that power emulation can achieve significant speedups (10X to 500X) over state-of-the-art commercial register-transfer level (RTL) power estimation tools.

  1. Open Hardware at CERN

    CERN Multimedia

    CERN Knowledge Transfer Group

    2015-01-01

    CERN is actively making its knowledge and technology available for the benefit of society and does so through a variety of different mechanisms. Open hardware has in recent years established itself as a very effective way for CERN to make electronics designs and in particular printed circuit board layouts, accessible to anyone, while also facilitating collaboration and design re-use. It is creating an impact on many levels, from companies producing and selling products based on hardware designed at CERN, to new projects being released under the CERN Open Hardware Licence. Today the open hardware community includes large research institutes, universities, individual enthusiasts and companies. Many of the companies are actively involved in the entire process from design to production, delivering services and consultancy and even making their own products available under open licences.

  2. Hardware description languages

    Science.gov (United States)

    Tucker, Jerry H.

    1994-01-01

    Hardware description languages are special purpose programming languages. They are primarily used to specify the behavior of digital systems and are rapidly replacing traditional digital system design techniques. This is because they allow the designer to concentrate on how the system should operate rather than on implementation details. Hardware description languages allow a digital system to be described with a wide range of abstraction, and they support top down design techniques. A key feature of any hardware description language environment is its ability to simulate the modeled system. The two most important hardware description languages are Verilog and VHDL. Verilog has been the dominant language for the design of application specific integrated circuits (ASIC's). However, VHDL is rapidly gaining in popularity.

  3. SOM Hardware-Accelerator

    OpenAIRE

    Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich

    1997-01-01

    Many applications of Selforganizing Feature Maps (SOMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOMs , a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by ...

  4. Dynamic Stability of Cylindrical Shells under Moving Loads by Applying Advanced Controlling Techniques—Part II: Using Piezo-Stack Control

    Directory of Open Access Journals (Sweden)

    Khaled M. Saadeldin Eldalil

    2009-01-01

    Full Text Available The load acting on the actively controlled cylindrical shell under a transient pressure pulse propelling a moving mass (gun case has been experimentally studied. The concept of using piezoelectric stack and stiffener combination is utilized for damping the tube wall radial and circumferential deforming vibrations, in the correct meeting location timing of the moving mass. The experiment was carried out by using the same stiffened shell tube of the experimental 14 mm gun tube facility which is used in part 1. Using single and double stacks is tried at two pressure levels of low-speed modes, which have response frequencies adapted with the used piezoelectric stacks characteristics. The maximum active damping ratio is occurred at high-pressure level. The radial circumferential strains are measured by using high-frequency strain gage system in phase with laser beam detection system similar to which used in part 1. Time resolved strain measurements of the wall response were obtained, and both precursor and transverse hoop strains have been resolved. A complete comparison had been made between the effect of active controlled and stepped structure cases, which indicate a significant attenuation ratio especially at higher operating pressures.

  5. Hardware Objects for Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Thalinger, Christian; Korsholm, Stephan;

    2008-01-01

    Java, as a safe and platform independent language, avoids access to low-level I/O devices or direct memory access. In standard Java, low-level I/O it not a concern; it is handled by the operating system. However, in the embedded domain resources are scarce and a Java virtual machine (JVM) without...... an underlying middleware is an attractive architecture. When running the JVM on bare metal, we need access to I/O devices from Java; therefore we investigate a safe and efficient mechanism to represent I/O devices as first class Java objects, where device registers are represented by object fields. Access...... to those registers is safe as Java’s type system regulates it. The access is also fast as it is directly performed by the bytecodes getfield and putfield. Hardware objects thus provide an object-oriented abstraction of low-level hardware devices. As a proof of concept, we have implemented hardware objects...

  6. Computer hardware fault administration

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-09-14

    Computer hardware fault administration carried out in a parallel computer, where the parallel computer includes a plurality of compute nodes. The compute nodes are coupled for data communications by at least two independent data communications networks, where each data communications network includes data communications links connected to the compute nodes. Typical embodiments carry out hardware fault administration by identifying a location of a defective link in the first data communications network of the parallel computer and routing communications data around the defective link through the second data communications network of the parallel computer.

  7. RRFC hardware operation manual

    International Nuclear Information System (INIS)

    The Research Reactor Fuel Counter (RRFC) system was developed to assay the 235U content in spent Material Test Reactor (MTR) type fuel elements underwater in a spent fuel pool. RRFC assays the 235U content using active neutron coincidence counting and also incorporates an ion chamber for gross gamma-ray measurements. This manual describes RRFC hardware, including detectors, electronics, and performance characteristics

  8. Deploying OpenStack

    CERN Document Server

    Pepple, Ken

    2011-01-01

    OpenStack was created with the audacious goal of being the ubiquitous software choice for building public and private cloud infrastructures. In just over a year, it's become the most talked-about project in open source. This concise book introduces OpenStack's general design and primary software components in detail, and shows you how to start using it to build cloud infrastructures. If you're a developer, technologist, or system administrator familiar with cloud offerings such as Rackspace Cloud or Amazon Web Services, Deploying OpenStack shows you how to obtain and deploy OpenStack softwar

  9. Sterilization of space hardware.

    Science.gov (United States)

    Pflug, I. J.

    1971-01-01

    Discussion of various techniques of sterilization of space flight hardware using either destructive heating or the action of chemicals. Factors considered in the dry-heat destruction of microorganisms include the effects of microbial water content, temperature, the physicochemical properties of the microorganism and adjacent support, and nature of the surrounding gas atmosphere. Dry-heat destruction rates of microorganisms on the surface, between mated surface areas, or buried in the solid material of space vehicle hardware are reviewed, along with alternative dry-heat sterilization cycles, thermodynamic considerations, and considerations of final sterilization-process design. Discussed sterilization chemicals include ethylene oxide, formaldehyde, methyl bromide, dimethyl sulfoxide, peracetic acid, and beta-propiolactone.

  10. Hardware Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-04-12

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32 bit floating point texture capabilities to obtain validated solutions to the radiative transport equation for X-rays. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedra that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester. We show that the hardware accelerated solution is faster than the current technique used by scientists.

  11. DCSP hardware maintenance system

    Energy Technology Data Exchange (ETDEWEB)

    Pazmino, M.

    1995-11-01

    This paper discusses the necessary changes to be implemented on the hardware side of the DCSP database. DCSP is currently tracking hardware maintenance costs in six separate databases. The goal is to develop a system that combines all data and works off a single database. Some of the tasks that will be discussed in this paper include adding the capability for report generation, creating a help package and preparing a users guide, testing the executable file, and populating the new database with data taken from the old database. A brief description of the basic process used in developing the system will also be discussed. Conclusions about the future of the database and the delivery of the final product are then addressed, based on research and the desired use of the system.

  12. Spent fuel assembly hardware

    International Nuclear Information System (INIS)

    When spent nuclear fuel is disposed of in a repository, the waste package will include the spent fuel assembly hardware, the structural portion of the fuel assembly, and the fuel pins. The spent fuel assembly hardware is the subject of this paper. The basic constituent parts of the fuel assembly will be described with particular attention on the materials used in their construction. The results of laboratory analyses performed to determine radionuclide inventories and trace impurities also will be described. Much of this work has been incorporated into a US Department of Energy (DOE) database maintained by Oak Ridge National Laboratory (ORNL). This database is documented in DOE/RW-0184 and can be obtained from Karl Notz at ORNL. The database provides a single source for information regarding wastes that may be sent to the repository

  13. Mastering OpenStack

    CERN Document Server

    Khedher, Omar

    2015-01-01

    This book is intended for system administrators, cloud engineers, and system architects who want to deploy a cloud based on OpenStack in a mid- to large-sized IT infrastructure. If you have a fundamental understanding of cloud computing and OpenStack and want to expand your knowledge, then this book is an excellent checkpoint to move forward.

  14. OpenStack essentials

    CERN Document Server

    Radez, Dan

    2015-01-01

    If you need to get started with OpenStack or want to learn more, then this book is your perfect companion. If you're comfortable with the Linux command line, you'll gain confidence in using OpenStack.

  15. Structural and electrical characteristics of ALD-HfO2/n-Si gate stack with SiON interfacial layer for advanced CMOS technology

    Science.gov (United States)

    Gupta, Richa; Rajput, Renu; Prasher, Rakesh; Vaid, Rakesh

    2016-09-01

    We report the fabrication of an ultra-thin silicon oxynitride (SiON) as an interfacial layer (IL) for n-Si/ALD-HfO2 gate stack with reduced leakage current. The XRD, AFM, FTIR, FESEM and EDAX characterizations have been performed for structural and morphological studies. Electrical parameters such as dielectric constant (K), interface trap density (Dit), leakage current density (J), effective oxide charge (Qeff), barrier height (Φbo), ideality factor (ƞ), breakdown-voltage (Vbr) and series resistance (Rs) were extracted through C-V, G-V and I-V measurements. The determined values of K, Dit, J, Qeff, Φbo, ƞ, Vbr and Rs are 14.4, 0.5 × 10 11 eV-1 cm-2, 2.2 × 10-9 A/cm2, 0.3 × 1013 cm-2, 0.42, 2.1, -0.33 and 14.5 MΩ respectively. SiON growth prior to HfO2 deposition has curtailed the problem of high leakage current density and interfacial traps due to sufficient amount of N2 incorporated at the interface.

  16. Efficient Context Switching for the Stack Cache: Implementation and Analysis

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian; Naji, Amine;

    2015-01-01

    The design of tailored hardware has proven a successful strategy to reduce the timing analysis overhead for (hard) real-time systems. The stack cache is an example of such a design that has been proven to provide good average-case performance, while being easy to analyze. So far, however, the ana...

  17. COMPUTER HARDWARE MARKING

    CERN Multimedia

    Groupe de protection des biens

    2000-01-01

    As part of the campaign to protect CERN property and for insurance reasons, all computer hardware belonging to the Organization must be marked with the words 'PROPRIETE CERN'.IT Division has recently introduced a new marking system that is both economical and easy to use. From now on all desktop hardware (PCs, Macintoshes, printers) issued by IT Division with a value equal to or exceeding 500 CHF will be marked using this new system.For equipment that is already installed but not yet marked, including UNIX workstations and X terminals, IT Division's Desktop Support Service offers the following services free of charge:Equipment-marking wherever the Service is called out to perform other work (please submit all work requests to the IT Helpdesk on 78888 or helpdesk@cern.ch; for unavoidable operational reasons, the Desktop Support Service will only respond to marking requests when these coincide with requests for other work such as repairs, system upgrades, etc.);Training of personnel designated by Division Leade...

  18. Radiation-Tolerant Intelligent Memory Stack - RTIMS

    Science.gov (United States)

    Ng, Tak-kwong; Herath, Jeffrey A.

    2011-01-01

    This innovation provides reconfigurable circuitry and 2-Gb of error-corrected or 1-Gb of triple-redundant digital memory in a small package. RTIMS uses circuit stacking of heterogeneous components and radiation shielding technologies. A reprogrammable field-programmable gate array (FPGA), six synchronous dynamic random access memories, linear regulator, and the radiation mitigation circuits are stacked into a module of 42.7 42.7 13 mm. Triple module redundancy, current limiting, configuration scrubbing, and single- event function interrupt detection are employed to mitigate radiation effects. The novel self-scrubbing and single event functional interrupt (SEFI) detection allows a relatively soft FPGA to become radiation tolerant without external scrubbing and monitoring hardware

  19. Decoding Stacked Denoising Autoencoders

    OpenAIRE

    Sonoda, Sho; Murata, Noboru

    2016-01-01

    Data representation in a stacked denoising autoencoder is investigated. Decoding is a simple technique for translating a stacked denoising autoencoder into a composition of denoising autoencoders in the ground space. In the infinitesimal limit, a composition of denoising autoencoders is reduced to a continuous denoising autoencoder, which is rich in analytic properties and geometric interpretation. For example, the continuous denoising autoencoder solves the backward heat equation and transpo...

  20. Open hardware for open science

    CERN Multimedia

    CERN Bulletin

    2011-01-01

    Inspired by the open source software movement, the Open Hardware Repository was created to enable hardware developers to share the results of their R&D activities. The recently published CERN Open Hardware Licence offers the legal framework to support this knowledge and technology exchange.   Two years ago, a group of electronics designers led by Javier Serrano, a CERN engineer, working in experimental physics laboratories created the Open Hardware Repository (OHR). This project was initiated in order to facilitate the exchange of hardware designs across the community in line with the ideals of “open science”. The main objectives include avoiding duplication of effort by sharing results across different teams that might be working on the same need. “For hardware developers, the advantages of open hardware are numerous. For example, it is a great learning tool for technologies some developers would not otherwise master, and it avoids unnecessary work if someone ha...

  1. Ball Bearing Stacking Automation System

    Directory of Open Access Journals (Sweden)

    Shafeequerrahman S . Ahmed

    2013-01-01

    Full Text Available This document is an effort to introduce the concept of automation in small scale industries and or small workshops that are involved in the manufacturing of small objects such as nuts, bolts and ball bearing in this case. This an electromechanical system which includes certain mechanical parts that involves one base stand on which one vertical metallic frame is mounted and hinged to this vertical stand is an in humanized effort seems inadequate in this era making necessary the use of Electronics, Computer in the manufacturing processes leading to the concept of Automated Manufacturing System (AMS.The ball bearing stack automation is an effort in this regard. In our project we go for stack automation for any object for example a ball bearing, be that is still a manual system there. It will be microcontroller based project control system equipped with microcontroller 89C51 from any manufacturer like Atmel or Philips. This could have been easily implemented if a PLC could be used for manufacturing the staking unit but I adopted the microcontroller based system so that some more modification in the system can be effected at will as to use the same hardware .Although a very small object i.e. ball bearig or small nut and fixture will be tried to be stacked, the system with more precision and more power handling capacity could be built for various requirements of the industry. For increasing more control capacity, we can use another module of this series. When the bearing is ready, it will be sent for packing. This is sensed by an inductive sensor. The output will be proceeds by PLC and microcontroller card which will be driving the assembly in order to put it into pads or flaps. This project will also count the total number of bearings to be packed and will display it on a LCD for real time reference and a provision is made using a higher level language using hyper terminal of the computer

  2. Hardware Middleware for Person Tracking on Embedded Distributed Smart Cameras

    Directory of Open Access Journals (Sweden)

    Ali Akbar Zarezadeh

    2012-01-01

    Full Text Available Tracking individuals is a prominent application in such domains like surveillance or smart environments. This paper provides a development of a multiple camera setup with jointed view that observes moving persons in a site. It focuses on a geometry-based approach to establish correspondence among different views. The expensive computational parts of the tracker are hardware accelerated via a novel system-on-chip (SoC design. In conjunction with this vision application, a hardware object request broker (ORB middleware is presented as the underlying communication system. The hardware ORB provides a hardware/software architecture to achieve real-time intercommunication among multiple smart cameras. Via a probing mechanism, a performance analysis is performed to measure network latencies, that is, time traversing the TCP/IP stack, in both software and hardware ORB approaches on the same smart camera platform. The empirical results show that using the proposed hardware ORB as client and server in separate smart camera nodes will considerably reduce the network latency up to 100 times compared to the software ORB.

  3. DAQ hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed read-out hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  4. DAQ Hardware and software development for the ATLAS Pixel Detector

    CERN Document Server

    Stramaglia, Maria Elena; The ATLAS collaboration

    2015-01-01

    In 2014, the Pixel Detector of the ATLAS experiment was extended by about 12 million pixels with the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented by employing newly designed read-out hardware, which supports the full detector bandwidth even for calibration. The hardware is supported by an embedded software stack running on the read-out boards. The same boards will be used to upgrade the read-out bandwidth for the two outermost layers of the ATLAS Pixel Barrel (54 million pixels). We present the IBL read-out hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  5. DAQ hardware and software development for the ATLAS Pixel Detector

    Science.gov (United States)

    Stramaglia, Maria Elena

    2016-07-01

    In 2014, the Pixel Detector of the ATLAS experiment has been extended by about 12 million pixels thanks to the installation of the Insertable B-Layer (IBL). Data-taking and tuning procedures have been implemented along with newly designed readout hardware to support high bandwidth for data readout and calibration. The hardware is supported by an embedded software stack running on the readout boards. The same boards will be used to upgrade the readout bandwidth for the two outermost barrel layers of the ATLAS Pixel Detector. We present the IBL readout hardware and the supporting software architecture used to calibrate and operate the 4-layer ATLAS Pixel Detector. We discuss the technical implementations and status for data taking, validation of the DAQ system in recent cosmic ray data taking, in-situ calibrations, and results from additional tests in preparation for Run 2 at the LHC.

  6. Hardware Support for Embedded Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin

    2012-01-01

    The general Java runtime environment is resource hungry and unfriendly for real-time systems. To reduce the resource consumption of Java in embedded systems, direct hardware support of the language is a valuable option. Furthermore, an implementation of the Java virtual machine in hardware enables...... worst-case execution time analysis of Java programs. This chapter gives an overview of current approaches to hardware support for embedded and real-time Java....

  7. Hardware assisted hypervisor introspection.

    Science.gov (United States)

    Shi, Jiangyong; Yang, Yuexiang; Tang, Chuan

    2016-01-01

    In this paper, we introduce hypervisor introspection, an out-of-box way to monitor the execution of hypervisors. Similar to virtual machine introspection which has been proposed to protect virtual machines in an out-of-box way over the past decade, hypervisor introspection can be used to protect hypervisors which are the basis of cloud security. Virtual machine introspection tools are usually deployed either in hypervisor or in privileged virtual machines, which might also be compromised. By utilizing hardware support including nested virtualization, EPT protection and #BP, we are able to monitor all hypercalls belongs to the virtual machines of one hypervisor, include that of privileged virtual machine and even when the hypervisor is compromised. What's more, hypercall injection method is used to simulate hypercall-based attacks and evaluate the performance of our method. Experiment results show that our method can effectively detect hypercall-based attacks with some performance cost. Lastly, we discuss our furture approaches of reducing the performance cost and preventing the compromised hypervisor from detecting the existence of our introspector, in addition with some new scenarios to apply our hypervisor introspection system. PMID:27330913

  8. Hardware multiplier processor

    Science.gov (United States)

    Pierce, Paul E.

    1986-01-01

    A hardware processor is disclosed which in the described embodiment is a memory mapped multiplier processor that can operate in parallel with a 16 bit microcomputer. The multiplier processor decodes the address bus to receive specific instructions so that in one access it can write and automatically perform single or double precision multiplication involving a number written to it with or without addition or subtraction with a previously stored number. It can also, on a single read command automatically round and scale a previously stored number. The multiplier processor includes two concatenated 16 bit multiplier registers, two 16 bit concatenated 16 bit multipliers, and four 16 bit product registers connected to an internal 16 bit data bus. A high level address decoder determines when the multiplier processor is being addressed and first and second low level address decoders generate control signals. In addition, certain low order address lines are used to carry uncoded control signals. First and second control circuits coupled to the decoders generate further control signals and generate a plurality of clocking pulse trains in response to the decoded and address control signals.

  9. Hardware for soft computing and soft computing for hardware

    CERN Document Server

    Nedjah, Nadia

    2014-01-01

    Single and Multi-Objective Evolutionary Computation (MOEA),  Genetic Algorithms (GAs), Artificial Neural Networks (ANNs), Fuzzy Controllers (FCs), Particle Swarm Optimization (PSO) and Ant colony Optimization (ACO) are becoming omnipresent in almost every intelligent system design. Unfortunately, the application of the majority of these techniques is complex and so requires a huge computational effort to yield useful and practical results. Therefore, dedicated hardware for evolutionary, neural and fuzzy computation is a key issue for designers. With the spread of reconfigurable hardware such as FPGAs, digital as well as analog hardware implementations of such computation become cost-effective. The idea behind this book is to offer a variety of hardware designs for soft computing techniques that can be embedded in any final product. Also, to introduce the successful application of soft computing technique to solve many hard problem encountered during the design of embedded hardware designs. Reconfigurable em...

  10. Hardware Virtualization towards a Proficient Computing Environment

    Directory of Open Access Journals (Sweden)

    Shweta Agrawal

    2013-06-01

    Full Text Available In the recent few years Server Virtualization and Green Information Technology have become very popular and are fast becoming the norm in organizations of all disciplines and sizes. Today, different methods of energy savings are in use and in great demand. One of the newest methods in the IT to control the pollution of the environment and the greenhouse effect is Green IT that is directly connected with the Virtualization of Hardware Resources.Virtualization is the presentation of an environment to one layer in an information technology stack that abstracts or represents a lower layer. It makes it possible for the IT professional to run a number of machines on a single physical machine.In this study we elicit the concept of Hardware Virtualization. We illustrate the procedure of Hardware Virtualization using a real-world example and then we emulate a virtualized infrastructure to contrast against the physical infrastructure on the basis of CPU utilization. We have used the VMware Workstation 7.1.0 as a software tool for virtualization and AVG PC Tune Up 2011 to present the difference in CPU utilization before and after virtualization.This paper helps to identify the main reasons for the growing need for data centre virtualization. The results in this paper show that a virtualized infrastructure can potentially increase the CPU utilization by a significant margin, thereby suggesting an efficient and faster way of resource utilization, saving processing time, reducing the cost incurred in building separate physical servers and furthermore reducing the power consumption.

  11. Open Source Hardware for DIY Environmental Sensing

    Science.gov (United States)

    Aufdenkampe, A. K.; Hicks, S. D.; Damiano, S. G.; Montgomery, D. S.

    2014-12-01

    The Arduino open source electronics platform has been very popular within the DIY (Do It Yourself) community for several years, and it is now providing environmental science researchers with an inexpensive alternative to commercial data logging and transmission hardware. Here we present the designs for our latest series of custom Arduino-based dataloggers, which include wireless communication options like self-meshing radio networks and cellular phone modules. The main Arduino board uses a custom interface board to connect to various research-grade sensors to take readings of turbidity, dissolved oxygen, water depth and conductivity, soil moisture, solar radiation, and other parameters. Sensors with SDI-12 communications can be directly interfaced to the logger using our open Arduino-SDI-12 software library (https://github.com/StroudCenter/Arduino-SDI-12). Different deployment options are shown, like rugged enclosures to house the loggers and rigs for mounting the sensors in both fresh water and marine environments. After the data has been collected and transmitted by the logger, the data is received by a mySQL-PHP stack running on a web server that can be accessed from anywhere in the world. Once there, the data can be visualized on web pages or served though REST requests and Water One Flow (WOF) services. Since one of the main benefits of using open source hardware is the easy collaboration between users, we are introducing a new web platform for discussion and sharing of ideas and plans for hardware and software designs used with DIY environmental sensors and data loggers.

  12. Progress of MCFC stack technology at Toshiba

    Energy Technology Data Exchange (ETDEWEB)

    Hori, M.; Hayashi, T.; Shimizu, Y. [Toshiba Corp., Tokyo (Japan)

    1996-12-31

    Toshiba is working on the development of MCFC stack technology; improvement of cell characteristics, and establishment of separator technology. For the cell technology, Toshiba has concentrated on both the restraints of NiO cathode dissolution and electrolyte loss from cells, which are the critical issues to extend cell life in MCFC, and great progress has been made. On the other hand, recognizing that the separator is one of key elements in accomplishing reliable and cost-competitive MCFC stacks, Toshiba has been accelerating the technology establishment and verification of an advanced type separator. A sub-scale stack with such a separator was provided for an electric generating test, and has been operated for more than 10,000 hours. This paper presents several topics obtained through the technical activities in the MCFC field at Toshiba.

  13. Detailed Electrochemical Characterisation of Large SOFC Stacks

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, R.;

    2012-01-01

    application of advanced methods for detailed electrochemical characterisation during operation. An operating stack is subject to steep compositional gradients in the gaseous reactant streams, and significant temperature gradients across each cell and across the stack, which makes it a complex system...... Fuel Cell A/S was characterised in detail using electrochemical impedance spectroscopy. An investigation of the optimal geometrical placement of the current probes and voltage probes was carried out in order to minimise measurement errors caused by stray impedances. Unwanted stray impedances...... are particularly problematic at high frequencies. Stray impedances may be caused by mutual inductance and stray capacitance in the geometrical set-up and do not describe the fuel cell. Three different stack geometries were investigated by electrochemical impedance spectroscopy. Impedance measurements were carried...

  14. Wolfram technology stack

    CERN Multimedia

    2013-01-01

    Stephen Wolfram gives a personal account of his vision for the "Wolfram technology stack" and how it developed, starting with his work in particle physics. The talk was presented at the 2013 ROOT Users' Meeting and followed a talk, earlier in the day, on "Mathematica with ROOT".

  15. Learning SaltStack

    CERN Document Server

    Myers, Colton

    2015-01-01

    If you are a system administrator who manages multiple servers, then you know how difficult it is to keep your infrastructure in line. If you've been searching for an easier way, this book is for you. No prior experience with SaltStack is required.

  16. Secure coupling of hardware components

    NARCIS (Netherlands)

    Knobbe, J.W.; Hoepman, J.H.; Joosten, H.J.M.

    2011-01-01

    A method and a system for securing communication between at least a first and a second hardware components of a mobile device is described. The method includes establishing a first shared secret between the first and the second hardware components during an initialization of the mobile device and, f

  17. BIOLOGICALLY INSPIRED HARDWARE CELL ARCHITECTURE

    DEFF Research Database (Denmark)

    2010-01-01

    Disclosed is a system comprising: - a reconfigurable hardware platform; - a plurality of hardware units defined as cells adapted to be programmed to provide self-organization and self-maintenance of the system by means of implementing a program expressed in a programming language defined as DNA...

  18. Flight Avionics Hardware Roadmap

    Science.gov (United States)

    Hodson, Robert; McCabe, Mary; Paulick, Paul; Ruffner, Tim; Some, Rafi; Chen, Yuan; Vitalpur, Sharada; Hughes, Mark; Ling, Kuok; Redifer, Matt; Wallace, Shawn

    2013-01-01

    As part of NASA's Avionics Steering Committee's stated goal to advance the avionics discipline ahead of program and project needs, the committee initiated a multi-Center technology roadmapping activity to create a comprehensive avionics roadmap. The roadmap is intended to strategically guide avionics technology development to effectively meet future NASA missions needs. The scope of the roadmap aligns with the twelve avionics elements defined in the ASC charter, but is subdivided into the following five areas: Foundational Technology (including devices and components), Command and Data Handling, Spaceflight Instrumentation, Communication and Tracking, and Human Interfaces.

  19. Assuring Quality and Reliability in Complex Avionics Systems hardware & Software

    Directory of Open Access Journals (Sweden)

    V. Haridas

    1997-01-01

    Full Text Available It is conventional wisdom in defence systems that electronic brains are where much of the present and future weapons system capability is developed. Electronic hardware advances, particularly in microprocessor, allow highly complex and sophisticated software to provide high degree of system autonomy and customisation to mission at hand. Since modern military systems are so much dependent on the proper functioning of electronics, the quality and reliability of electronic hardware and software have a profound impact on defensive capability and readiness. At the hardware level, due to the advances in microelectronics, functional capabilities of today's systems have increased. The advances in the hardware field have an impact on software also. Now a days, it is possible to incorporate more and more system functions through software, rather than going for a pure hardware solution. On the other hand complexities the systems are increasing, working energy levels of the systems are decreasing and the areas of reliability and quality assurance are becoming more and more wide. This paper covers major failure modes in microelectronic devices. The various techniques used to improve component and system reliability are described. The recent trends in expanding the scope of traditional quality assurance techniques are also discussed, considering both hardware and software.

  20. OpenStack cloud security

    CERN Document Server

    Locati, Fabio Alessandro

    2015-01-01

    If you are an OpenStack administrator or developer, or wish to build solutions to protect your OpenStack environment, then this book is for you. Experience of Linux administration and familiarity with different OpenStack components is assumed.

  1. Energy Expenditure of Sport Stacking

    Science.gov (United States)

    Murray, Steven R.; Udermann, Brian E.; Reineke, David M.; Battista, Rebecca A.

    2009-01-01

    Sport stacking is an activity taught in many physical education programs. The activity, although very popular, has been studied minimally, and the energy expenditure for sport stacking is unknown. Therefore, the purposes of this study were to determine the energy expenditure of sport stacking in elementary school children and to compare that value…

  2. Analytic stacks and hyperbolicity

    OpenAIRE

    Borghesi, Simone; Tomassini, Giuseppe

    2012-01-01

    The classical Brody's theorem asserts the equivalence between two notions of hyperbolicity for compact complex spaces, one named after Kobayashi and one expressed in terms of lack of non constant holomorphic entire functions (compactness is only used to prove the harder implication). We extend this theorem to Deligne-Mumford analytic stacks, by first providing definitions of what we think of Kobayashi and Brody hyperbolicity for such objects and then proving the equivalence of these concepts ...

  3. Toric Stacks II: Intrinsic Characterization of Toric Stacks

    CERN Document Server

    Geraschenko, Anton

    2011-01-01

    The purpose of this paper and its prequel (Toric Stacks I) is to introduce and develop a theory of toric stacks which encompasses and extends the notions of toric stacks defined in [Laf02, BCS05, FMN09, Iwa09, Sat09, Tyo10], as well as classical toric varieties. While the focus of the prequel is on how to work with toric stacks, the focus of this paper is how to show a stack is toric. For toric varieties, a classical result says that any normal variety with an action of a dense open torus arises from a fan. In [FMN09, Theorem 7.24], it is shown that a smooth separated DM stack with an action of a dense open stacky torus arises from a stacky fan. In the same spirit, the main result of this paper is that any Artin stack with an action of a dense open torus arises from a stacky fan under reasonable hypotheses.

  4. Hardware Evolution of Control Electronics

    Science.gov (United States)

    Gwaltney, David; Steincamp, Jim; Corder, Eric; King, Ken; Ferguson, M. I.; Dutton, Ken

    2003-01-01

    The evolution of closed-loop motor speed controllers implemented on the JPL FPTA2 is presented. The response of evolved controller to sinusoidal commands, controller reconfiguration for fault tolerance,and hardware evolution are described.

  5. NDAS Hardware Translation Layer Development

    Science.gov (United States)

    Nazaretian, Ryan N.; Holladay, Wendy T.

    2011-01-01

    The NASA Data Acquisition System (NDAS) project is aimed to replace all DAS software for NASA s Rocket Testing Facilities. There must be a software-hardware translation layer so the software can properly talk to the hardware. Since the hardware from each test stand varies, drivers for each stand have to be made. These drivers will act more like plugins for the software. If the software is being used in E3, then the software should point to the E3 driver package. If the software is being used at B2, then the software should point to the B2 driver package. The driver packages should also be filled with hardware drivers that are universal to the DAS system. For example, since A1, A2, and B2 all use the Preston 8300AU signal conditioners, then the driver for those three stands should be the same and updated collectively.

  6. Stack Caching Using Split Data Caches

    DEFF Research Database (Denmark)

    Nielsen, Carsten; Schoeberl, Martin

    2015-01-01

    In most embedded and general purpose architectures, stack data and non-stack data is cached together, meaning that writing to or loading from the stack may expel non-stack data from the data cache. Manipulation of the stack has a different memory access pattern than that of non-stack data, showin...

  7. Die-stacking architecture

    CERN Document Server

    Xie, Yuan

    2015-01-01

    The emerging three-dimensional (3D) chip architectures, with their intrinsic capability of reducing the wire length, promise attractive solutions to reduce the delay of interconnects in future microprocessors. 3D memory stacking enables much higher memory bandwidth for future chip-multiprocessor design, mitigating the ""memory wall"" problem. In addition, heterogenous integration enabled by 3D technology can also result in innovative designs for future microprocessors. This book first provides a brief introduction to this emerging technology, and then presents a variety of approaches to design

  8. Scientific Computing Using Consumer Video-Gaming Hardware Devices

    CERN Document Server

    Volkema, Glenn

    2016-01-01

    Commodity video-gaming hardware (consoles, graphics cards, tablets, etc.) performance has been advancing at a rapid pace owing to strong consumer demand and stiff market competition. Gaming hardware devices are currently amongst the most powerful and cost-effective computational technologies available in quantity. In this article, we evaluate a sample of current generation video-gaming hardware devices for scientific computing and compare their performance with specialized supercomputing general purpose graphics processing units (GPGPUs). We use the OpenCL SHOC benchmark suite, which is a measure of the performance of compute hardware on various different scientific application kernels, and also a popular public distributed computing application, Einstein@Home in the field of gravitational physics for the purposes of this evaluation.

  9. Technology stacks and frameworks for full-stack application development

    OpenAIRE

    Ušaj, Erik

    2016-01-01

    This work aims providing a comprehensive overview and analysis of current JavaScript (JS) technology stacks and frameworks for full-stack application development: from web clients, mobile and desktop applications to server applications and cloud-connected services. Analysis shall focus on MEAN technology stack and frameworks such as Meteor which also tries to leverage mobile app development using Apache Cordova framework. We will include an overview of available JS build tools for desktop app...

  10. Alignment of Memory Transfers of a Time-Predictable Stack Cache

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Brandner, Florian

    2014-01-01

    of complex cache states. Instead, only the occupancy level of the cache has to be determined. The memory transfers generated by the standard stack cache are not generally aligned. These unaligned accesses risk to introduce complexity to the otherwise simple WCET analysis. In this work, we investigate three...... different approaches to handle the alignment problem in the stack cache: (1) unaligned transfers, (2) alignment through compiler-generated padding, (3) a novel hardware extension ensuring the alignment of all transfers. Simulation results show that our hardware extension offers a good compromise between...

  11. Stacked Extreme Learning Machines.

    Science.gov (United States)

    Zhou, Hongming; Huang, Guang-Bin; Lin, Zhiping; Wang, Han; Soh, Yeng Chai

    2015-09-01

    Extreme learning machine (ELM) has recently attracted many researchers' interest due to its very fast learning speed, good generalization ability, and ease of implementation. It provides a unified solution that can be used directly to solve regression, binary, and multiclass classification problems. In this paper, we propose a stacked ELMs (S-ELMs) that is specially designed for solving large and complex data problems. The S-ELMs divides a single large ELM network into multiple stacked small ELMs which are serially connected. The S-ELMs can approximate a very large ELM network with small memory requirement. To further improve the testing accuracy on big data problems, the ELM autoencoder can be implemented during each iteration of the S-ELMs algorithm. The simulation results show that the S-ELMs even with random hidden nodes can achieve similar testing accuracy to support vector machine (SVM) while having low memory requirements. With the help of ELM autoencoder, the S-ELMs can achieve much better testing accuracy than SVM and slightly better accuracy than deep belief network (DBN) with much faster training speed. PMID:25361517

  12. Asymmetric Flexible Supercapacitor Stack

    Directory of Open Access Journals (Sweden)

    Leela Mohana Reddy A

    2008-01-01

    Full Text Available AbstractElectrical double layer supercapacitor is very significant in the field of electrical energy storage which can be the solution for the current revolution in the electronic devices like mobile phones, camera flashes which needs flexible and miniaturized energy storage device with all non-aqueous components. The multiwalled carbon nanotubes (MWNTs have been synthesized by catalytic chemical vapor deposition technique over hydrogen decrepitated Mischmetal (Mm based AB3alloy hydride. The polymer dispersed MWNTs have been obtained by insitu polymerization and the metal oxide/MWNTs were synthesized by sol-gel method. Morphological characterizations of polymer dispersed MWNTs have been carried out using scanning electron microscopy (SEM, transmission electron microscopy (TEM and HRTEM. An assymetric double supercapacitor stack has been fabricated using polymer/MWNTs and metal oxide/MWNTs coated over flexible carbon fabric as electrodes and nafion®membrane as a solid electrolyte. Electrochemical performance of the supercapacitor stack has been investigated using cyclic voltammetry, galvanostatic charge-discharge, and electrochemical impedance spectroscopy.

  13. The Art of Space Flight Exercise Hardware: Design and Implementation

    Science.gov (United States)

    Beyene, Nahom M.

    2004-01-01

    while it is deployed and conduct all sanitization, calibration, and maintenance for the devices. Thus, hardware designs must account for these issues with a goal of minimizing crew time on orbit required to complete these tasks. In the future, humans will venture to Mars and exercise countermeasures will play a critical role in allowing us to continue in our spirit of exploration. NASA will benefit from further experimentation on Earth, through the International Space Station, and with advanced biomechanical models to quantify how each device counteracts specific symptoms of weightlessness. With the continued support of international space agencies and the academic research community, we will usher the next frontier in human space exploration.

  14. Raspberry Pi hardware projects 1

    CERN Document Server

    Robinson, Andrew

    2013-01-01

    Learn how to take full advantage of all of Raspberry Pi's amazing features and functions-and have a blast doing it! Congratulations on becoming a proud owner of a Raspberry Pi, the credit-card-sized computer! If you're ready to dive in and start finding out what this amazing little gizmo is really capable of, this ebook is for you. Taken from the forthcoming Raspberry Pi Projects, Raspberry Pi Hardware Projects 1 contains three cool hardware projects that let you have fun with the Raspberry Pi while developing your Raspberry Pi skills. The authors - PiFace inventor, Andrew Robinson and Rasp

  15. ATLAS software stack on ARM64

    CERN Document Server

    Smith, Joshua Wyatt; The ATLAS collaboration

    2016-01-01

    The ATLAS experiment explores new hardware and software platforms that, in the future, may be more suited to its data intensive workloads. One such alternative hardware platform is the ARM architecture, which is designed to be extremely power efficient and is found in most smartphones and tablets. CERN openlab recently installed a small cluster of ARM 64-bit evaluation prototype servers. Each server is based on a single-socket ARM 64-bit system on a chip, with 32 Cortex-A57 cores. In total, each server has 128 GB RAM connected with four fast memory channels. This paper reports on the port of the ATLAS software stack onto these new prototype ARM64 servers. This included building the "external" packages that the ATLAS software relies on. Patches were needed to introduce this new architecture into the build as well as patches that correct for platform specific code that caused failures on non-x86 architectures. These patches were applied such that porting to further platforms will need no or only very little adj...

  16. Instant BlueStacks

    CERN Document Server

    Judge, Gary

    2013-01-01

    Get to grips with a new technology, understand what it is and what it can do for you, and then get to work with the most important features and tasks. A fast-paced, example-based approach guide for learning BlueStacks.This book is for anyone with a Mac or PC who wants to run Android apps on their computer. Whether you want to play games that are freely available for Android but not your computer, or you want to try apps before you install them on a physical device or use it as a development tool, this book will show you how. No previous experience is needed as this is written in plain English

  17. Lazy Spilling for a Time-Predictable Stack Cache: Implementation and Analysis

    DEFF Research Database (Denmark)

    Abbaspourseyedi, Sahar; Jordan, Alexander; Brandner, Florian

    2014-01-01

    The growing complexity of modern computer architectures increasingly complicates the prediction of the run-time behavior of software. For real-time systems, where a safe estimation of the program's worst-case execution time is needed, time-predictable computer architectures promise to resolve...... this problem. A stack cache, for instance, allows the compiler to efficiently cache a program's stack, while static analysis of its behavior remains easy. Likewise, its implementation requires little hardware overhead. This work introduces an optimization of the standard stack cache to avoid redundant spilling...

  18. Foundations of digital signal processing theory, algorithms and hardware design

    CERN Document Server

    Gaydecki, Patrick

    2005-01-01

    An excellent introductory text, this book covers the basic theoretical, algorithmic and real-time aspects of digital signal processing (DSP). Detailed information is provided on off-line, real-time and DSP programming and the reader is effortlessly guided through advanced topics such as DSP hardware design, FIR and IIR filter design and difference equation manipulation.

  19. Commodity hardware and software summary

    Energy Technology Data Exchange (ETDEWEB)

    Wolbers, S.

    1997-04-01

    A review is given of the talks and papers presented in the Commodity Hardware and Software Session at the CHEP97 conference. An examination of the trends leading to the consideration of PC`s for HEP is given, and a status of the work that is being done at various HEP labs and Universities is given.

  20. Multiple Segmentation of Image Stacks

    DEFF Research Database (Denmark)

    Smets, Jonathan; Jaeger, Manfred

    2014-01-01

    segmentations that capture different structural elements of the image. We also apply the method to collections of images with identical pixel dimensions, which we call image stacks. Here it turns out that the method is able to both identify groups of similar images in the stack, and to provide segmentations...

  1. Stacking disorder in ice I.

    Science.gov (United States)

    Malkin, Tamsin L; Murray, Benjamin J; Salzmann, Christoph G; Molinero, Valeria; Pickering, Steven J; Whale, Thomas F

    2015-01-01

    Traditionally, ice I was considered to exist in two well-defined crystalline forms at ambient pressure: stable hexagonal ice (ice Ih) and metastable cubic ice (ice Ic). However, it is becoming increasingly evident that what has been called cubic ice in the past does not have a structure consistent with the cubic crystal system. Instead, it is a stacking-disordered material containing cubic sequences interlaced with hexagonal sequences, which is termed stacking-disordered ice (ice Isd). In this article, we summarise previous work on ice with stacking disorder including ice that was called cubic ice in the past. We also present new experimental data which shows that ice which crystallises after heterogeneous nucleation in water droplets containing solid inclusions also contains stacking disorder even at freezing temperatures of around -15 °C. This supports the results from molecular simulations, that the structure of ice that crystallises initially from supercooled water is always stacking-disordered and that this metastable ice can transform to the stable hexagonal phase subject to the kinetics of recrystallization. We also show that stacking disorder in ice which forms from water droplets is quantitatively distinct from ice made via other routes. The emerging picture of ice I is that of a very complex material which frequently contains stacking disorder and this stacking disorder can vary in complexity depending on the route of formation and thermal history. PMID:25380218

  2. Modular hardware synthesis using an HDL. [Hardware Description Language

    Science.gov (United States)

    Covington, J. A.; Shiva, S. G.

    1981-01-01

    Although hardware description languages (HDL) are becoming more and more necessary to automated design systems, their application is complicated due to the difficulty in translating the HDL description into an implementable format, nonfamiliarity of hardware designers with high-level language programming, nonuniform design methodologies and the time and costs involved in transfering HDL design software. Digital design language (DDL) suffers from all of the above problems and in addition can only by synthesized on a complete system and not on its subparts, making it unsuitable for synthesis using standard modules or prefabricated chips such as those required in LSI or VLSI circuits. The present paper presents a method by which the DDL translator can be made to generate modular equations that will allow the system to be synthesized as an interconnection of lower-level modules. The method involves the introduction of a new language construct called a Module which provides for the separate translation of all equations bounded by it.

  3. Fuel flow distribution in SOFC stacks revealed by impedance spectroscopy

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, Rasmus;

    2014-01-01

    As SOFC technology is moving closer to a commercial break through, methods to measure the “state-of-health” of operating stacks are becoming of increasing interest. This requires application of advanced methods for detailed electrical and electrochemical characterization during operation. An oper......As SOFC technology is moving closer to a commercial break through, methods to measure the “state-of-health” of operating stacks are becoming of increasing interest. This requires application of advanced methods for detailed electrical and electrochemical characterization during operation....... An operating stack is subject to compositional gradients in the gaseous reactant streams, and temperature gradients across each cell and across the stack, which complicates detailed analysis. An experimental stack with low ohmic resistance from Topsoe Fuel Cell A/S was characterized using Electrochemical...... Impedance Spectroscopy (EIS). The stack measurement geometry was optimized for EIS by careful selection of the placement of current feeds and voltage probes in order to minimize measurement errors. It was demonstrated that with the improved placement of current feeds and voltage probes it is possible...

  4. CASIS Fact Sheet: Hardware and Facilities

    Science.gov (United States)

    Solomon, Michael R.; Romero, Vergel

    2016-01-01

    Vencore is a proven information solutions, engineering, and analytics company that helps our customers solve their most complex challenges. For more than 40 years, we have designed, developed and delivered mission-critical solutions as our customers' trusted partner. The Engineering Services Contract, or ESC, provides engineering and design services to the NASA organizations engaged in development of new technologies at the Kennedy Space Center. Vencore is the ESC prime contractor, with teammates that include Stinger Ghaffarian Technologies, Sierra Lobo, Nelson Engineering, EASi, and Craig Technologies. The Vencore team designs and develops systems and equipment to be used for the processing of space launch vehicles, spacecraft, and payloads. We perform flight systems engineering for spaceflight hardware and software; develop technologies that serve NASA's mission requirements and operations needs for the future. Our Flight Payload Support (FPS) team at Kennedy Space Center (KSC) provides engineering, development, and certification services as well as payload integration and management services to NASA and commercial customers. Our main objective is to assist principal investigators (PIs) integrate their science experiments into payload hardware for research aboard the International Space Station (ISS), commercial spacecraft, suborbital vehicles, parabolic flight aircrafts, and ground-based studies. Vencore's FPS team is AS9100 certified and a recognized implementation partner for the Center for Advancement of Science in Space (CASIS

  5. Hardware-Accelerated Simulated Radiography

    Energy Technology Data Exchange (ETDEWEB)

    Laney, D; Callahan, S; Max, N; Silva, C; Langer, S; Frank, R

    2005-08-04

    We present the application of hardware accelerated volume rendering algorithms to the simulation of radiographs as an aid to scientists designing experiments, validating simulation codes, and understanding experimental data. The techniques presented take advantage of 32-bit floating point texture capabilities to obtain solutions to the radiative transport equation for X-rays. The hardware accelerated solutions are accurate enough to enable scientists to explore the experimental design space with greater efficiency than the methods currently in use. An unsorted hexahedron projection algorithm is presented for curvilinear hexahedral meshes that produces simulated radiographs in the absorption-only regime. A sorted tetrahedral projection algorithm is presented that simulates radiographs of emissive materials. We apply the tetrahedral projection algorithm to the simulation of experimental diagnostics for inertial confinement fusion experiments on a laser at the University of Rochester.

  6. IRST system: hardware implementation issues

    Science.gov (United States)

    Deshpande, Suyog D.; Chan, Philip; Ser, W.; Venkateswarlu, Ronda

    1999-07-01

    Generally, Infrared Search and Track systems use linear focal-plane-arrays with time-delay and integration, because of their high sensitivity. However, the readout is a cumbersome process and needs special effort. This paper describes signal processing and hardware (HW) implementation issues related to front-end electronics, non-uniformity compensation, signal formatting, target detection, tracking and display system. This paper proposes parallel pipeline architecture with dedicated HW for computationally intensive algorithms and SW intensive DSP HW for reconfigurable architecture.

  7. Compressive Sensing Image Sensors-Hardware Implementation

    Directory of Open Access Journals (Sweden)

    Shahram Shirani

    2013-04-01

    Full Text Available The compressive sensing (CS paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal–oxide–semiconductor technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed.

  8. Perspectives in Simulation Hardware and Software Architecture

    Directory of Open Access Journals (Sweden)

    W.O. Grierson

    1985-10-01

    Full Text Available Historically, analog and hybrid computer systems have provided effective real-time solutions for the simulation of large dynamic systems. In the mid 1970s, ADI concluded that these systems were no longer adequate to meet the demands of larger, more complex models and the demand for greater simulation accuracy. The decision was to design an all-digital system to satisfy these growing requirements (see Gilbert and Howe, (1978. This all-digital approach was called the SYSTEM 10. The SYSTEM 10 has been effective in solving time-critical simulation problems and in replacing the previous approach of utilizing hybrid computers. Recent advances in 100 K emitter coupled logic (ECL now make it possible to support a new generation of equipment that expands modeling capabilities to serve simulation needs. The hardware and software concepts of this system, called the SYSTEM 100, are the subject of this paper.

  9. Compressive sensing image sensors-hardware implementation.

    Science.gov (United States)

    Dadkhah, Mohammadreza; Deen, M Jamal; Shirani, Shahram

    2013-01-01

    The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementations of CS encoding in optical and electrical domains is presented. Considering the recent advances in CMOS (complementary metal-oxide-semiconductor) technologies and the feasibility of performing on-chip signal processing, important practical issues in the implementation of CS in CMOS sensors are emphasized. In addition, the CS coding for video capture is discussed. PMID:23584123

  10. Seismic qualification of ventilation stack

    International Nuclear Information System (INIS)

    This paper describes the method to be used to qualify the 105 K ventilation stack at the US Department of Energy's Hanford Site, near Richland, Washington, under seismic and wind loadings. The stack stands at 175 ft (53.34 m), with a diameter tapering from 22 ft (6.71 m) at the foundation to 12.83 ft (3.91 m) at the top. Although the stack is classified as Safety Class 3 (low hazard), it is treated as a Safety Class 1 (high hazard) component, as failure could damage a Safety Class 1 facility (the irradiated fuel storage basin). The evaluation used US Department of Energy criteria specified in UCRL 15910 (1990). The seismic responses of the stack under earthquake loading were obtained from modal analyses with response spectrum input that used the ANSYS (1989) finite-element computer code. The moments and shear forces from the results of seismic analysis were used to qualify the reinforcement capacity of the stack structure by the ultimate-strength method. The wind forces acting on the stack in both along-wind and are evaluations of the soil bearing pressure, the moment, and the shear capacity of the stack foundation

  11. Hunting for hardware changes in data centres

    International Nuclear Information System (INIS)

    With many servers and server parts the environment of warehouse sized data centres is increasingly complex. Server life-cycle management and hardware failures are responsible for frequent changes that need to be managed. To manage these changes better a project codenamed “hardware hound” focusing on hardware failure trending and hardware inventory has been started at CERN. By creating and using a hardware oriented data set - the inventory - with detailed information on servers and their parts as well as tracking changes to this inventory, the project aims at, for example, being able to discover trends in hardware failure rates.

  12. Combining high productivity with high performance on commodity hardware

    DEFF Research Database (Denmark)

    Skovhede, Kenneth

    The current advances in the natural sciences are increasingly dependent on the available in computer power. At the same time, the increase in computer power is no longer based on faster cores, but on multiple cores and specialized hardware. As most scientific software is written for sequential...... processing, the increase in hardware performance cannot be utilized. Most existing scientific software is written in low-level languages such as C or FORTRAN, making it difficult to rewrite these to work in parallel. As the brief CELL-BE processor history showed, writing solutions that are tied...... to a particular hardware platform, is a risky investment. To make this problem worse, the scientists that have the required field expertise to write the algorithms are not formally trained programmers. This usually leads to scientists writing buggy, inefficient and hard to maintain programs. Occasionally...

  13. Bringing the power of dynamic languages to hardware control systems

    CERN Document Server

    Caicedo, J M; Neufeld, N

    2009-01-01

    Hardware control systems are normally programmed using high-performance languages like C or C++ and increasingly also Java. All these languages are strongly typed and compiled which brings usually good performance but at the cost of a longer development and testing cycle and the need for more programming expertise. Dynamic languages which were long thought to be too slow and not powerful enough for control purposes are, thanks to modern powerful computers and advanced implementation techniques, fast enough for many of these tasks. We present examples from the LHCb Experiment Control System (ECS), which is based on a commercial SCADA software. We have successfully used Python to integrate hardware devices into the ECS. We present the necessary lightweight middle-ware we have developed, including examples for controlling hardware and software devices. We also discuss the development cycle, tools used and compare the effort to traditional solutions.

  14. Nova as embedded operating system for cuban hardware Nova como sistema operativo embebido para hardware cubano

    Directory of Open Access Journals (Sweden)

    Mijail Hurtado Fedorovich

    2012-05-01

    Full Text Available This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented. Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.

  15. Nova como sistema operativo embebido para hardware cubano Nova as embedded operating system for cuban hardware

    Directory of Open Access Journals (Sweden)

    José Ernesto Torres Sánchez

    2012-05-01

    Full Text Available Este trabajo expone los resultados de construir un sistema operativo embebido basado en Nova, el cual brinda las funcionalidades necesarias para crear el Cliente Ligero Cubano, utilizando como componente de hardware, la Computadora en una Tarjeta CID 300/9 diseñada por el Instituto Central de Investigación Digital. Obteniéndose la primera versión de Nova para la arquitectura de computadora Advanced RISC Machine y el primer sistema operativo base, estable y de propósito general para la CID 300/9. Se expone un estado del arte de los sistemas operativos embebidos más utilizados actualmente; la estructura de la solución, los métodos y herramientas empleados para obtenerla.This paper presents the results of the construction a an embedded operating system based on Nova, which provides the needed features to create the Cuban Thin Client, using as hardware component the Computer on a CID 300/9 Board designed by the Central Institute for Digital Research, obtaining the first version of Nova for the Advance RISC Machine  computer architecture and the first base operating system, stable and for general purposes for the CID 300/9. A state of the art of the currently most used embedded operating systems, the solution's structure, the methods and tools used for its development are presented.

  16. Design and Implementation of Digital Linear Control Systems on Reconfigurable Hardware

    Directory of Open Access Journals (Sweden)

    Marcus Bednara

    2003-05-01

    Full Text Available The implementation of large linear control systems requires a high amount of digital signal processing. Here, we show that reconfigurable hardware allows the design of fast yet flexible control systems. After discussing the basic concepts for the design and implementation of digital controllers for mechatronic systems, a new general and automated design flow starting from a system of differential equations to application-specific hardware implementation is presented. The advances of reconfigurable hardware as a target technology for linear controllers is discussed. In a case study, we compare the new hardware approach for implementing linear controllers with a software implementation.

  17. GOSH! A roadmap for open-source science hardware

    CERN Multimedia

    Stefania Pandolfi

    2016-01-01

    The goal of the Gathering for Open Science Hardware (GOSH! 2016), held from 2 to 5 March 2016 at IdeaSquare, was to lay the foundations of the open-source hardware for science movement.   The participants in the GOSH! 2016 meeting gathered in IdeaSquare. (Image: GOSH Community) “Despite advances in technology, many scientific innovations are held back because of a lack of affordable and customisable hardware,” says François Grey, a professor at the University of Geneva and coordinator of Citizen Cyberlab – a partnership between CERN, the UN Institute for Training and Research and the University of Geneva – which co-organised the GOSH! 2016 workshop. “This scarcity of accessible science hardware is particularly obstructive for citizen science groups and humanitarian organisations that don’t have the same economic means as a well-funded institution.” Instead, open sourcing science hardware co...

  18. Laser photography system: hardware configuration

    Science.gov (United States)

    Piszczek, Marek; Rutyna, Krzysztof; Kowalski, Marcin; Zyczkowski, Marek

    2012-06-01

    Solution presented in this article is a system using image acquisition time gating method. The time-spatial framing method developed by authors was used to build Laser Photography System (LPS). An active vision system for open space monitoring and terrorist threats detection is being built as an effect of recent work lead in the Institute of Optoelectronics, MUT. The device is destined to prevent and recognize possible terrorist threats in important land and marine areas. The aim of this article is to discuss the properties and hardware configuration of the Laser Photography System.

  19. 16 CFR 1508.6 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1508.6 Section 1508.6 Commercial... FULL-SIZE BABY CRIBS § 1508.6 Hardware. (a) A crib shall be designed and constructed in a manner that eliminates from any hardware accessible to a child within the crib the possibility of the...

  20. 16 CFR 1509.7 - Hardware.

    Science.gov (United States)

    2010-01-01

    ... 16 Commercial Practices 2 2010-01-01 2010-01-01 false Hardware. 1509.7 Section 1509.7 Commercial Practices CONSUMER PRODUCT SAFETY COMMISSION FEDERAL HAZARDOUS SUBSTANCES ACT REGULATIONS REQUIREMENTS FOR NON-FULL-SIZE BABY CRIBS § 1509.7 Hardware. (a) The hardware in a non-full-size baby crib shall...

  1. High exposure hardware removal activity readiness evaluation

    International Nuclear Information System (INIS)

    This document comprises the Readiness Evaluation Plan for the High Exposure Rate Hardware (HERH) Removal Activity planned for the N Basin area at the Hanford Reservation in Richland Washington. This activity will consist of collecting hardware, depositing hardware in stainless-steel fuel element storage baskets, placing baskets in specially fabricated steel grout pipe, and encasing the contents in a high-slump grout

  2. Hardware complications in scoliosis surgery

    Energy Technology Data Exchange (ETDEWEB)

    Bagchi, Kaushik; Mohaideen, Ahamed [Department of Orthopaedic Surgery and Musculoskeletal Services, Maimonides Medical Center, Brooklyn, NY (United States); Thomson, Jeffrey D. [Connecticut Children' s Medical Center, Department of Orthopaedics, Hartford, CT (United States); Foley, Christopher L. [Department of Radiology, Connecticut Children' s Medical Center, Hartford, Connecticut (United States)

    2002-07-01

    Background: Scoliosis surgery has undergone a dramatic evolution over the past 20 years with the advent of new surgical techniques and sophisticated instrumentation. Surgeons have realized scoliosis is a complex multiplanar deformity that requires thorough knowledge of spinal anatomy and pathophysiology in order to manage patients afflicted by it. Nonoperative modalities such as bracing and casting still play roles in the treatment of scoliosis; however, it is the operative treatment that has revolutionized the treatment of this deformity that affects millions worldwide. As part of the evolution of scoliosis surgery, newer implants have resulted in improved outcomes with respect to deformity correction, reliability of fixation, and paucity of complications. Each technique and implant has its own set of unique complications, and the surgeon must appreciate these when planning surgery. Materials and methods: Various surgical techniques and types of instrumentation typically used in scoliosis surgery are briefly discussed. Though scoliosis surgery is associated with a wide variety of complications, only those that directly involve the hardware are discussed. The current literature is reviewed and several illustrative cases of patients treated for scoliosis at the Connecticut Children's Medical Center and the Newington Children's Hospital in Connecticut are briefly presented. Conclusion: Spine surgeons and radiologists should be familiar with the different types of instrumentation in the treatment of scoliosis. Furthermore, they should recognize the clinical and roentgenographic signs of hardware failure as part of prompt and effective treatment of such complications. (orig.)

  3. Travel Software using GPU Hardware

    CERN Document Server

    Szalwinski, Chris M; Dimov, Veliko Atanasov; CERN. Geneva. ATS Department

    2015-01-01

    Travel is the main multi-particle tracking code being used at CERN for the beam dynamics calculations through hadron and ion linear accelerators. It uses two routines for the calculation of space charge forces, namely, rings of charges and point-to-point. This report presents the studies to improve the performance of Travel using GPU hardware. The studies showed that the performance of Travel with the point-to-point simulations of space-charge effects can be speeded up at least 72 times using current GPU hardware. Simple recompilation of the source code using an Intel compiler can improve performance at least 4 times without GPU support. The limited memory of the GPU is the bottleneck. Two algorithms were investigated on this point: repeated computation and tiling. The repeating computation algorithm is simpler and is the currently recommended solution. The tiling algorithm was more complicated and degraded performance. Both build and test instructions for the parallelized version of the software are inclu...

  4. Electronic processing and control system with programmable hardware

    Science.gov (United States)

    Alkalaj, Leon (Inventor); Fang, Wai-Chi (Inventor); Newell, Michael A. (Inventor)

    1998-01-01

    A computer system with reprogrammable hardware allowing dynamically allocating hardware resources for different functions and adaptability for different processors and different operating platforms. All hardware resources are physically partitioned into system-user hardware and application-user hardware depending on the specific operation requirements. A reprogrammable interface preferably interconnects the system-user hardware and application-user hardware.

  5. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Wilson, M.S.; Moeller-Holst, S.; Webb, D.M.; Zawodzinski, C.; Gottesfeld, S. [Los Alamos National Lab., NM (United States). Materials Science and Technology Div.

    1998-08-01

    The objective is to develop and demonstrate a 4 kW, hydrogen-fueled polymer electrolyte fuel cell (PEFC) stack, based on non-machined stainless steel hardware and on membrane/electrode assemblies (MEAs) of low catalyst loadings. The stack is designed to operate at ambient pressure on the air-side and can accommodate operation at higher fuel pressures, if so required. This is to be accomplished by working jointly with a fuel cell stack manufacturer, based on a CRADA. The performance goals are 57% energy conversion efficiency hydrogen-to-electricity (DC) at a power density of 0.9 kW/liter for a stack operating at ambient inlet pressures. The cost goal is $600/kW, based on present materials costs.

  6. Tuple spaces in hardware for accelerated implicit routing

    Energy Technology Data Exchange (ETDEWEB)

    Baker, Zachary Kent [Los Alamos National Laboratory; Tripp, Justin [Los Alamos National Laboratory

    2010-12-01

    Organizing and optimizing data objects on networks with support for data migration and failing nodes is a complicated problem to handle as systems grow. The goal of this work is to demonstrate that high levels of speedup can be achieved by moving responsibility for finding, fetching, and staging data into an FPGA-based network card. We present a system for implicit routing of data via FPGA-based network cards. In this system, data structures are requested by name, and the network of FPGAs finds the data within the network and relays the structure to the requester. This is acheived through successive examination of hardware hash tables implemented in the FPGA. By avoiding software stacks between nodes, the data is quickly fetched entirely through FPGA-FPGA interaction. The performance of this system is orders of magnitude faster than software implementations due to the improved speed of the hash tables and lowered latency between the network nodes.

  7. Feature-Weighted Linear Stacking

    CERN Document Server

    Sill, Joseph; Mackey, Lester; Lin, David

    2009-01-01

    Ensemble methods, such as stacking, are designed to boost predictive accuracy by blending the predictions of multiple machine learning models. Recent work has shown that the use of meta-features, additional inputs describing each example in a dataset, can boost the performance of ensemble methods, but the greatest reported gains have come from nonlinear procedures requiring significant tuning and training time. Here, we present a linear technique, Feature-Weighted Linear Stacking (FWLS), that incorporates meta-features for improved accuracy while retaining the well-known virtues of linear regression regarding speed, stability, and interpretability. FWLS combines model predictions linearly using coefficients that are themselves linear functions of meta-features. This technique was a key facet of the solution of the second place team in the recently concluded Netflix Prize competition. Significant increases in accuracy over standard linear stacking is demonstrated on the Netflix Prize collaborative filtering da...

  8. Glassy carbon based supercapacitor stacks

    Energy Technology Data Exchange (ETDEWEB)

    Baertsch, M.; Braun, A.; Koetz, R.; Haas, O. [Paul Scherrer Inst. (PSI), Villigen (Switzerland)

    1997-06-01

    Considerable effort is being made to develop electrochemical double layer capacitors (EDLC) that store relatively large quantities of electrical energy and possess at the same time a high power density. Our previous work has shown that glassy carbon is suitable as a material for capacitor electrodes concerning low resistance and high capacity requirements. We present the development of bipolar electrochemical glassy carbon capacitor stacks of up to 3 V. Bipolar stacks are an efficient way to meet the high voltage and high power density requirements for traction applications. Impedance and cyclic voltammogram measurements are reported here and show the frequency response of a 1, 2, and 3 V stack. (author) 3 figs., 1 ref..

  9. Simulating Small-Scale Object Stacking Using Stack Stability

    DEFF Research Database (Denmark)

    Kronborg Thomsen, Kasper; Kraus, Martin

    2015-01-01

    This paper presents an extension system to a closed-source, real-time physics engine for improving structured stacking behavior with small-scale objects such as wooden toy bricks. The proposed system was implemented and evaluated. The tests showed that the system is able to simulate several common...

  10. Neural Network Adaptations to Hardware Implementations

    OpenAIRE

    Moerland, Perry,; Fiesler,Emile

    1997-01-01

    In order to take advantage of the massive parallelism offered by artificial neural networks, hardware implementations are essential.However, most standard neural network models are not very suitable for implementation in hardware and adaptations are needed. In this section an overview is given of the various issues that are encountered when mapping an ideal neural network model onto a compact and reliable neural network hardware implementation, like quantization, handling nonuniformities and ...

  11. Neural Network Adaptations to Hardware Implementations

    OpenAIRE

    Moerland, Perry,; Fiesler,Emile; Beale, R

    1997-01-01

    In order to take advantage of the massive parallelism offered by artificial neural networks, hardware implementations are essential. However, most standard neural network models are not very suitable for implementation in hardware and adaptations are needed. In this section an overview is given of the various issues that are encountered when mapping an ideal neural network model onto a compact and reliable neural network hardware implementation, like quantization, handling nonuniformities and...

  12. Hardware Implementation of Singular Value Decomposition

    Science.gov (United States)

    Majumder, Swanirbhar; Shaw, Anil Kumar; Sarkar, Subir Kumar

    2016-06-01

    Singular value decomposition (SVD) is a useful decomposition technique which has important role in various engineering fields such as image compression, watermarking, signal processing, and numerous others. SVD does not involve convolution operation, which make it more suitable for hardware implementation, unlike the most popular transforms. This paper reviews the various methods of hardware implementation for SVD computation. This paper also studies the time complexity and hardware complexity in various methods of SVD computation.

  13. Electronic hardware implementations of neutral networks

    Science.gov (United States)

    Thakoor, A. P.; Moopenn, A.; Lambe, John; Khanna, S. K.

    1987-01-01

    This paper examines some of the present work on the development of electronic neural network hardware. In particular, the investigations currently under way at JPL on neural network hardware implementations based on custom VLSI technology, novel thin film materials, and an analog-digital hybrid architecture are reviewed. The availability of such hardware will greatly benefit and enhance the present intense research effort on the potential computational capabilities of highly parallel systems based on neural network models.

  14. Hardware Trojan Horses in Cryptographic IP Cores

    OpenAIRE

    Bhasin, Shivam; Danger, Jean-Luc; Guilley, Sylvain; Ngo, Xuan Thuy; Sauvage, Laurent

    2013-01-01

    International audience Detecting hardware trojans is a difficult task in general. In this article we study hardware trojan horses insertion and detection in cryptographic intellectual property (IP) blocks. The context is that of a fabless design house that sells IP blocks as GDSII hard macros, and wants to check that final products have not been infected by trojans during the foundry stage. First, we show the efficiency of a medium cost hardware trojans detection method if the placement or...

  15. Transgene Stacking in Cotton Improvement

    Institute of Scientific and Technical Information of China (English)

    2008-01-01

    To date,more and more transgenic varieties of upland cotton(Gossypium hirsutum L.) generated with transgenes,which derived from varies of alien species,are playing important role in agricultural production.Stacking of multi-transgenes has a potential for combining all the merits of distinct

  16. Multibeam collimator uses prism stack

    Science.gov (United States)

    Minott, P. O.

    1981-01-01

    Optical instrument creates many divergent light beams for surveying and machine element alignment applications. Angles and refractive indices of stack of prisms are selected to divert incoming laser beam by small increments, different for each prism. Angles of emerging beams thus differ by small, precisely-controlled amounts. Instrument is nearly immune to vibration, changes in gravitational force, temperature variations, and mechanical distortion.

  17. Multilayer Piezoelectric Stack Actuator Characterization

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher M.; Aldrich, Jack B.; Blodget, Chad; Bao, Xioaqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to use actuators for precision positioning to accuracies of the order of fractions of a nanometer. For this purpose, multilayer piezoelectric stacks are being considered as actuators for driving these precision mechanisms. In this study, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and extreme temperatures and voltages. AC signal testing included impedance, capacitance and dielectric loss factor of each actuator as a function of the small-signal driving sinusoidal frequency, and the ambient temperature. DC signal testing includes leakage current and displacement as a function of the applied DC voltage. The applied DC voltage was increased to over eight times the manufacturers' specifications to investigate the correlation between leakage current and breakdown voltage. Resonance characterization as a function of temperature was done over a temperature range of -180C to +200C which generally exceeded the manufacturers' specifications. In order to study the lifetime performance of these stacks, five actuators from one manufacturer were driven by a 60volt, 2 kHz sine-wave for ten billion cycles. The tests were performed using a Lab-View controlled automated data acquisition system that monitored the waveform of the stack electrical current and voltage. The measurements included the displacement, impedance, capacitance and leakage current and the analysis of the experimental results will be presented.

  18. Transgene Stacking in Cotton Improvement

    Institute of Scientific and Technical Information of China (English)

    YANG Ye-hua; WANG Xue-kui; YAO Ming-jing; FAN Yu-peng; GAO Da-yu

    2008-01-01

    @@ To date,more and more transgenic varieties of upland cotton (Gossypium hirsuturn L.) generated with transgenes,which derived from varies of alien species,are playing important role in agricultural production.Stacking of multi-transgenes has a potential for combining all the merits of distinct transgenic lines in a cultivar and possibly makes a significant contribution to cultivar improvement.

  19. Implementation of Hardware Accelerators on Zynq

    DEFF Research Database (Denmark)

    Toft, Jakob Kenn

    processors, which has made hardware accelerators an essential part of several datacentres and the worlds fastest super-computers. In this work, two different hardware accelerators were implemented on a Xilinx Zynq SoC platform mounted on the ZedBoard platform. The two accelerators are based on two different...... of the ARM Cortex-9 processor featured on the Zynq SoC, with regard to execution time, power dissipation and energy consumption. The implementation of the hardware accelerators were successful. Use of the Monte Carlo processor resulted in a significant increase in performance. The Telco hardware accelerator...

  20. An Algebraic Hardware/Software Partitioning Algorithm

    Institute of Scientific and Technical Information of China (English)

    秦胜潮; 何积丰; 裘宗燕; 张乃孝

    2002-01-01

    Hardware and software co-design is a design technique which delivers computer systems comprising hardware and software components. A critical phase of the co-design process is to decompose a program into hardware and software. This paper proposes an algebraic partitioning algorithm whose correctness is verified in program algebra. The authors introduce a program analysis phase before program partitioning and develop a collection of syntax-based splitting rules. The former provides the information for moving operations from software to hardware and reducing the interaction between components, and the latter supports a compositional approach to program partitioning.

  1. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Madsen, Jan; Knudsen, Peter Voigt

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search...

  2. Hardware Resource Allocation for Hardware/Software Partitioning in the LYCOS System

    DEFF Research Database (Denmark)

    Grode, Jesper Nicolai Riis; Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a novel hardware resource allocation technique for hardware/software partitioning. It allocates hardware resources to the hardware data-path using information such as data-dependencies between operations in the application, and profiling information. The algorithm is useful...... as a designer's/design tool's aid to generate good hardware allocations for use in hardware/software partitioning. The algorithm has been implemented in a tool under the LYCOS system. The results show that the allocations produced by the algorithm come close to the best allocations obtained by exhaustive search....

  3. Solid Oxide Fuel Cell Stack Diagnostics

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Barfod, Rasmus Gottrup

    repeating units are reported and discussed. The performance and degradation of a 14-cell co-flow stack was monitored for more than 667 hours at steady operating conditions using the sequential impedance measurement setup. The stack was tested galvanostatically (at constant current) with 50% steam...... carried out on an experimental 14-cell SOFC stack at varying frequencies and fuel utilizations. The results illustrated that THD can be used to detect increasing non-linearities in the current-voltage characteristics of the stack when the stack suffers from fuel starvation by monitoring the stack sum...

  4. Nanorobot Hardware Architecture for Medical Defense

    Directory of Open Access Journals (Sweden)

    Luiz C. Kretly

    2008-05-01

    Full Text Available This work presents a new approach with details on the integrated platform and hardware architecture for nanorobots application in epidemic control, which should enable real time in vivo prognosis of biohazard infection. The recent developments in the field of nanoelectronics, with transducers progressively shrinking down to smaller sizes through nanotechnology and carbon nanotubes, are expected to result in innovative biomedical instrumentation possibilities, with new therapies and efficient diagnosis methodologies. The use of integrated systems, smart biosensors, and programmable nanodevices are advancing nanoelectronics, enabling the progressive research and development of molecular machines. It should provide high precision pervasive biomedical monitoring with real time data transmission. The use of nanobioelectronics as embedded systems is the natural pathway towards manufacturing methodology to achieve nanorobot applications out of laboratories sooner as possible. To demonstrate the practical application of medical nanorobotics, a 3D simulation based on clinical data addresses how to integrate communication with nanorobots using RFID, mobile phones, and satellites, applied to long distance ubiquitous surveillance and health monitoring for troops in conflict zones. Therefore, the current model can also be used to prevent and save a population against the case of some targeted epidemic disease.

  5. HSX hardware, control and diagnostics

    International Nuclear Information System (INIS)

    The HSX Helically Symmetric Stellarator has been operational for the last year, making plasmas at 0.5T using 28 GHz ECH. During this phase of operation, hardware, machine diagnostics, and plasma diagnostics have been continually implemented to improve machine operation and control, and plasma diagnostic capabilities. This paper will provide and overview of the basic machine control concepts, some details of the He glow discharge cleaning methods used to provide density control under plasma operation, and some details of the LabViewR (National Instruments) and SLC interfaced machine control, timing and diagnostics. Low-level machine operation (coil deflection, ground currents, vacuum base pressures and contaminants, etc.), motor generator, Gyrotron, coil cooling and temperature monitoring is also performed using the LabView/SLC combination; more of which is planned for the ensuing months. Diagnostic implementation, from 288 GHz microwave interferometer, diamagnetic loop signals, optical and x-ray diagnostics, probes, etc., are primarily interfaced using LabView A/D, digital and analog I/O, and timing cards controlled by PC computers: all of which save the data to a PC based data storage site. A ten-chord fir Thomson Scattering system and a multichannel ECE system are under construction for operation in the near future, again with primary control and data interface planned for incorporation into the PC based system. A SQL database is currently under implementation to improve overall data searching capabilities and accessibility, and to facilitate data backup and protection. Both MatLabR and IDLR are currently used for data analysis and presentation, which will be maintained through the database implementation. Copyright (2002) Australian National University- Research School of Physical Sciences and Engineering

  6. Tinker's Toys: Lessons from Bank Street: Hardware.

    Science.gov (United States)

    Tinker, Robert

    1985-01-01

    Bank Street Laboratory (a set of hardware/software tools for measuring temperature, light, and sound) consists of a board that plugs into Apple microcomputers, cabling, software, and six probes. Discusses the laboratory's hardware, including the analog-to-digital converter, multiplier chip, and modular connectors. Circuit diagrams of components…

  7. Relational algebra as formalism for hardware design

    NARCIS (Netherlands)

    Berg, ten A.J.W.M.; Huijs, C.; Krol, Th.

    1993-01-01

    This paper introduces relational algebra as an elegant formalism to describe hardware behaviour. Hardware behaviour is modelled by functions that are represented by sets of tables. Relational algebra, developed for designing large and consistent databases is capable to operate on sets of tables and

  8. Computer hardware description languages - A tutorial

    Science.gov (United States)

    Shiva, S. G.

    1979-01-01

    The paper introduces hardware description languages (HDL) as useful tools for hardware design and documentation. The capabilities and limitations of HDLs are discussed along with the guidelines needed in selecting an appropriate HDL. The directions for future work are provided and attention is given to the implementation of HDLs in microcomputers.

  9. Returned Solar Max hardware degradation study results

    International Nuclear Information System (INIS)

    The Solar Maximum Repair Mission returned with the replaced hardware that had been in low Earth orbit for over four years. The materials of this returned hardware gave the aerospace community an opportunity to study the realtime effects of atomic oxygen, solar radiation, impact particles, charged particle radiation, and molecular contamination. The results of these studies are summarized

  10. Federation of OpenStack clouds

    OpenAIRE

    Tartarini, Luca; Denis, Marek

    2014-01-01

    Project Specification Rackspace and CERN are implementing federated identity of OpenStack clouds within the OpenStack cloud project. The project is to enhance the client tools in OpenStack to support Thefederated identity functionalities, work with the open source community to incorporate these changes into the product and adapt the documentation and testing. The student will learn about the internals of OpenStack, federated identity techniques such as SAML and working with open sour...

  11. Hardware Software co-simulation for Image Processing Applications

    Directory of Open Access Journals (Sweden)

    A.C.Suthar

    2012-03-01

    Full Text Available We proposed the concept of hardware software co-simulation for image processing using Xilinx system generator. Recent advances in synthesis tools for SIMULINK suggest a feasible high-level approach to algorithm implementation for embedded DSP systems. An efficient FPGA based hardware design for enhancement of color and grey scale images in image and video processing. The top model - based visual development process of SIMULINK facilitates host side simulation and validation, as well as synthesis of target specific code, furthermore, legacy code written in MATLAB or ANCI C can be reuse in custom blocks. However, the code generated for DSP platforms is often not very efficient. We are implemented the Image processing applications on FPGA it can be easily design

  12. Treatment, packaging, and storage of bundle scrap hardware

    International Nuclear Information System (INIS)

    A study was performed to identify and evaluate the various technical options for treatment, packaging and storing the bundle scrap hardware that results from rod consolidation. The three general scenarios addressed were keeping the treated scrap in the pool, moving it to on-site dry storage, or immediate disposal. The study concluded that practical alternatives existed for all three cases. Use of novel scrap packaging techniques achieved an overall net consolidation ratio of two. The most economical concept was found to be using advanced technology in the pool storage scenario with dry storage schemes a close second. The project also provides information on scrap characterization and provides tools to assist in classifying the scrap hardware

  13. Docker on OpenStack

    OpenAIRE

    Agarwal, Nitin; Moreira, Belmiro

    2014-01-01

    Project Specification CERN is establishing a large scale private cloud based on OpenStack as part of the expansion of the computing infrastructure for storing the data coming out of the Large Hadron Collider (LHC) experiments. As the data coming out of the detectors is increasing continuously that needs to be stored in the data center, we need more physical resources (more money) and since Virtual machines takes lot of CPU and memory overhead and minutes for creating the images, booting u...

  14. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Zawodzinski, C.; Wilson, M.; Gottesfeld, S. [Los Alamos National Lab., NM (United States)

    1996-10-01

    The fuel cell is the most efficient device for the conversion of hydrogen fuel to electric power. As such, the fuel cell represents a key element in efforts to demonstrate and implement hydrogen fuel utilization for electric power generation. A central objective of a LANL/Industry collaborative effort supported by the Hydrogen Program is to integrate PEM fuel cell and novel stack designs at LANL with stack technology of H-Power Corporation (H-Power) in order to develop a manufacturable, low-cost/high-performance hydrogen/air fuel cell stack for stationary generation of electric power. A LANL/H-Power CRADA includes Tasks ranging from exchange, testing and optimization of membrane-electrode assemblies of large areas, development and demonstration of manufacturable flow field, backing and bipolar plate components, and testing of stacks at the 3-5 cell level and, finally, at the 4-5 kW level. The stack should demonstrate the basic features of manufacturability, overall low cost and high energy conversion efficiency. Plans for future work are to continue the CRADA work along the time line defined in a two-year program, to continue the LANL activities of developing and testing stainless steel hardware for longer term stability including testing in a stack, and to further enhance air cathode performance to achieve higher energy conversion efficiencies as required for stationary power application.

  15. Space shuttle main engine hardware simulation

    Science.gov (United States)

    Vick, H. G.; Hampton, P. W.

    1985-01-01

    The Huntsville Simulation Laboratory (HSL) provides a simulation facility to test and verify the space shuttle main engine (SSME) avionics and software system using a maximum complement of flight type hardware. The HSL permits evaluations and analyses of the SSME avionics hardware, software, control system, and mathematical models. The laboratory has performed a wide spectrum of tests and verified operational procedures to ensure system component compatibility under all operating conditions. It is a test bed for integration of hardware/software/hydraulics. The HSL is and has been an invaluable tool in the design and development of the SSME.

  16. Hardware device binding and mutual authentication

    Science.gov (United States)

    Hamlet, Jason R; Pierson, Lyndon G

    2014-03-04

    Detection and deterrence of device tampering and subversion by substitution may be achieved by including a cryptographic unit within a computing device for binding multiple hardware devices and mutually authenticating the devices. The cryptographic unit includes a physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generates a binding PUF value. The cryptographic unit uses the binding PUF value during an enrollment phase and subsequent authentication phases. During a subsequent authentication phase, the cryptographic unit uses the binding PUF values of the multiple hardware devices to generate a challenge to send to the other device, and to verify a challenge received from the other device to mutually authenticate the hardware devices.

  17. Programmable hardware for reconfigurable computing systems

    Science.gov (United States)

    Smith, Stephen

    1996-10-01

    In 1945 the work of J. von Neumann and H. Goldstein created the principal architecture for electronic computation that has now lasted fifty years. Nevertheless alternative architectures have been created that have computational capability, for special tasks, far beyond that feasible with von Neumann machines. The emergence of high capacity programmable logic devices has made the realization of these architectures practical. The original ENIAC and EDVAC machines were conceived to solve special mathematical problems that were far from today's concept of 'killer applications.' In a similar vein programmable hardware computation is being used today to solve unique mathematical problems. Our programmable hardware activity is focused on the research and development of novel computational systems based upon the reconfigurability of our programmable logic devices. We explore our programmable logic architectures and their implications for programmable hardware. One programmable hardware board implementation is detailed.

  18. Resolution-independent surface rendering using programmable graphics hardware

    Science.gov (United States)

    Loop, Charles T.; Blinn, James Frederick

    2008-12-16

    Surfaces defined by a Bezier tetrahedron, and in particular quadric surfaces, are rendered on programmable graphics hardware. Pixels are rendered through triangular sides of the tetrahedra and locations on the shapes, as well as surface normals for lighting evaluations, are computed using pixel shader computations. Additionally, vertex shaders are used to aid interpolation over a small number of values as input to the pixel shaders. Through this, rendering of the surfaces is performed independently of viewing resolution, allowing for advanced level-of-detail management. By individually rendering tetrahedrally-defined surfaces which together form complex shapes, the complex shapes can be rendered in their entirety.

  19. IDD Archival Hardware Architecture and Workflow

    Energy Technology Data Exchange (ETDEWEB)

    Mendonsa, D; Nekoogar, F; Martz, H

    2008-10-09

    This document describes the functionality of every component in the DHS/IDD archival and storage hardware system shown in Fig. 1. The document describes steps by step process of image data being received at LLNL then being processed and made available to authorized personnel and collaborators. Throughout this document references will be made to one of two figures, Fig. 1 describing the elements of the architecture and the Fig. 2 describing the workflow and how the project utilizes the available hardware.

  20. A High Performance SOFM Hardware-System

    OpenAIRE

    Rüping, Stefan; Porrmann, Mario; Rückert, Ulrich

    1997-01-01

    Many applications of Selforganizing Feature Maps (SOFMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOFMs, a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by...

  1. ASIC life extension through hardware patch interfaces

    OpenAIRE

    Bryksin, Vladyslav Sergeevich

    2009-01-01

    Specialized processor designs and ASICs offer lower power consumption and greater efficiency compared to general purpose processors. However, the drawback of specialized hardware designs is the reduction in the generality of workloads that they are able to handle. An important characteristic of specialized hardware designs is the inability to manage changes in the underlying applications. This thesis describes and analyzes the concept of ASIC patching in the Arsenal design: a mechanism to mit...

  2. Cooperative communications hardware, channel and PHY

    CERN Document Server

    Dohler, Mischa

    2010-01-01

    Facilitating Cooperation for Wireless Systems Cooperative Communications: Hardware, Channel & PHY focuses on issues pertaining to the PHY layer of wireless communication networks, offering a rigorous taxonomy of this dispersed field, along with a range of application scenarios for cooperative and distributed schemes, demonstrating how these techniques can be employed. The authors discuss hardware, complexity and power consumption issues, which are vital for understanding what can be realized at the PHY layer, showing how wireless channel models differ from more traditional

  3. Efficient Hardware Design and Implementation of AES Cryptosystem

    Directory of Open Access Journals (Sweden)

    Pravin B. Ghewari

    2010-03-01

    Full Text Available We propose an efficient hardware architecture design & implementation of Advanced Encryption Standard (AES-Rijndael cryptosystem. The AES algorithm defined by the National Institute of Standard and Technology(NIST of United States has been widely accepted. The cryptographic algorithms can be implemented with software or built with pure hardware. However Field Programmable Gate Arrays (FPGA implementation offers quicker solution and can be easily upgraded to incorporate any protocol changes. This contribution investigates the AES encryption and decryption cryptosystem with regard to FPGA and Very High Speed Integrated Circuit Hardware Description language (VHDL. Optimized and Synthesizable VHDL code is developed for theimplementation of both 128- bit data encryption and decryption process. Xilinx ISE 8.1 software is used for simulation. Each program is tested with some of the sample vectors provided by NIST and output results are perfect with minimal delay. The throughput reaches the value of 352 Mbit/sec for both encryption and decryption process with Device XCV600 of Xilinx Virtex Family.

  4. Self-Adjusting Stack Machines

    CERN Document Server

    Hammer, Matthew A; Chen, Yan; Acar, Umut A

    2011-01-01

    Self-adjusting computation offers a language-based approach to writing programs that automatically respond to dynamically changing data. Recent work made significant progress in developing sound semantics and associated implementations of self-adjusting computation for high-level, functional languages. These techniques, however, do not address issues that arise for low-level languages, i.e., stack-based imperative languages that lack strong type systems and automatic memory management. In this paper, we describe techniques for self-adjusting computation which are suitable for low-level languages. Necessarily, we take a different approach than previous work: instead of starting with a high-level language with additional primitives to support self-adjusting computation, we start with a low-level intermediate language, whose semantics is given by a stack-based abstract machine. We prove that this semantics is sound: it always updates computations in a way that is consistent with full reevaluation. We give a comp...

  5. Introduction to co-simulation of software and hardware in embedded processor systems

    Energy Technology Data Exchange (ETDEWEB)

    Dreike, P.L.; McCoy, J.A.

    1996-09-01

    From the dawn of the first use of microprocessors and microcontrollers in embedded systems, the software has been blamed for products being late to market, This is due to software being developed after hardware is fabricated. During the past few years, the use of Hardware Description (or Design) Languages (HDLs) and digital simulation have advanced to a point where the concurrent development of software and hardware can be contemplated using simulation environments. This offers the potential of 50% or greater reductions in time-to-market for embedded systems. This paper is a tutorial on the technical issues that underlie software-hardware (swhw) co-simulation, and the current state of the art. We review the traditional sequential hardware-software design paradigm, and suggest a paradigm for concurrent design, which is supported by co-simulation of software and hardware. This is followed by sections on HDLs modeling and simulation;hardware assisted approaches to simulation; microprocessor modeling methods; brief descriptions of four commercial products for sw-hw co-simulation and a description of our own experiments to develop a co-simulation environment.

  6. Air-Cooled Stack Freeze Tolerance Freeze Failure Modes and Freeze Tolerance Strategies for GenDriveTM Material Handling Application Systems and Stacks Final Scientific Report

    Energy Technology Data Exchange (ETDEWEB)

    Hancock, David, W.

    2012-02-14

    Air-cooled stack technology offers the potential for a simpler system architecture (versus liquid-cooled) for applications below 4 kilowatts. The combined cooling and cathode air allows for a reduction in part count and hence a lower cost solution. However, efficient heat rejection challenges escalate as power and ambient temperature increase. For applications in ambient temperatures below freezing, the air-cooled approach has additional challenges associated with not overcooling the fuel cell stack. The focus of this project was freeze tolerance while maintaining all other stack and system requirements. Through this project, Plug Power advanced the state of the art in technology for air-cooled PEM fuel cell stacks and related GenDrive material handling application fuel cell systems. This was accomplished through a collaborative work plan to improve freeze tolerance and mitigate freeze-thaw effect failure modes within innovative material handling equipment fuel cell systems designed for use in freezer forklift applications. Freeze tolerance remains an area where additional research and understanding can help fuel cells to become commercially viable. This project evaluated both stack level and system level solutions to improve fuel cell stack freeze tolerance. At this time, the most cost effective solutions are at the system level. The freeze mitigation strategies developed over the course of this project could be used to drive fuel cell commercialization. The fuel cell system studied in this project was Plug Power's commercially available GenDrive platform providing battery replacement for equipment in the material handling industry. The fuel cell stacks were Ballard's commercially available FCvelocity 9SSL (9SSL) liquid-cooled PEM fuel cell stack and FCvelocity 1020ACS (Mk1020) air-cooled PEM fuel cell stack.

  7. Gate stack technology for nanoscale devices

    Directory of Open Access Journals (Sweden)

    Byoung Hun Lee

    2006-06-01

    Full Text Available Scaling of the gate stack has been a key to enhancing the performance of complementary metal-oxide-semiconductor (CMOS field-effect transistors (FETs of past technology generations. Because the rate of gate stack scaling has diminished in recent years, the motivation for alternative gate stacks or novel device structures has increased considerably. Intense research during the last decade has led to the development of high dielectric constant (k gate stacks that match the performance of conventional SiO2-based gate dielectrics. However, many challenges remain before alternative gate stacks can be introduced into mainstream technology. We review the current status of and challenges in gate stack research for planar CMOS devices and alternative device technologies to provide insights for future research.

  8. Evolvable Hardware Based Software-Hardware Co-Designing Platform ECDP

    Institute of Scientific and Technical Information of China (English)

    TU Hang; WU Tao-jun; LI Yuan-xiang

    2005-01-01

    Based on the theories of EA (Evolutionary Algorithm) and EHW (Evolvable Hardware), we devise an EHW-based software-hardware co-designing platform ECDP, on which we provided standards for hardware system encoding and evolving operation designing, as well as circuit emulating tools. The major features of this system are: two-layer-encoding of circuit structure, off-line evolving with software emulation and the evolving of genetic program designing. With this system, we implemented the auto-designing of some software-hardware systems, like the random number generator.

  9. Hardware-Based Simulation of a Fuel Cell Turbine Hybrid Response to Imposed Fuel Cell Load Transients

    Energy Technology Data Exchange (ETDEWEB)

    Smith, T.P. (Georgia Inst. of Technology); Tucker, D.A.; Haynes, C.L. (Georgia Inst. of Technology); Liese, E.A.; Wepfer, W.J. (Georgia Inst. of Technology)

    2006-11-01

    Electrical load transients imposed on the cell stack of a solid oxide fuel cell/gas turbine hybrid power system are studied using the Hybrid Performance (HyPer) project. The hardware simulation facility is located at the U.S. Department of Energy, National Energy Technology Laboratory (NETL). A computational fuel cell model capable of operating in real time is integrated with operating gas turbine hardware. The thermal output of a modeled 350 kW solid oxide fuel cell stack is replicated in the facility by a natural gas fired burner in a direct fired hybrid configuration. Pressure vessels are used to represent a fuel cell stack's cathode flow and post combustion volume and flow impedance. This hardware is used to simulate the fuel cell stack and is incorporated with a modified turbine, compressor, and 120 kW generator on a single shaft. For this study, a simulation was started with a simulated current demand of 307 A on the fuel cell at approximately 0.75 V and an actual 45 kW electrical load on the gas turbine. An open loop response, allowing the turbine rotational speed to respond to thermal transients, was successfully evaluated for a 5% current reduction on the fuel cell followed by a 5% current increase. The impact of the fuel cell load change on system process variables is presented. The test results demonstrate the capabilities of the hardware-in-the-loop simulation approach in evaluating hybrid fuel cell turbine dynamics and performance.

  10. Symptomatic Hardware Removal After First Tarsometatarsal Arthrodesis.

    Science.gov (United States)

    Peterson, Kyle S; McAlister, Jeffrey E; Hyer, Christopher F; Thompson, John

    2016-01-01

    Severe hallux valgus deformity with proximal instability creates pain and deformity in the forefoot. First tarsometatarsal joint arthrodesis is performed to reduce the intermetatarsal angle and stabilize the joint. Dorsomedial locking plate fixation with adjunctive lag screw fixation is used because of its superior construct strength and healing rate. Despite this, questions remain regarding whether this hardware is more prominent and more likely to need removal. The purpose of the present study was to determine the incidence of symptomatic hardware at the first tarsometatarsal joint and to determine the incidence of hardware removal resulting from prominence and/or discomfort. A review of 165 medical records of consecutive patients who had undergone first tarsometatarsal joint arthrodesis with plate fixation was conducted. The outcome of interest was the incidence of symptomatic hardware removal in patients with clinical union. The mean age was 55 (range 18.4 to 78.8) years. The mean follow-up duration was 65.9 ± 34.0 (range 7.0 to 369.0) weeks. In our cohort, 25 patients (15.2%) had undergone hardware removed because of pain and irritation. Of these patients, 18 (72.0%) had a locking plate and lag screw removed, and 7 (28.0%) had crossing lag screws removed. The fixation of a first tarsometatarsal joint fusion poses a difficult situation owing to minimal soft tissue coverage and the inherent need for robust fixation to promote fusion. Hardware can become prominent postoperatively and can become painful and/or induce cutaneous compromise. The results of the present observational investigation imply that surgeons can reasonably inform patients that the incidence of symptomatic hardware removal after first tarsometatarsal arthrodesis is approximately 15% within a median duration of 9.0 months after surgery.

  11. The untyped stack calculus and Bohm's theorem

    OpenAIRE

    Alberto Carraro

    2013-01-01

    The stack calculus is a functional language in which is in a Curry-Howard correspondence with classical logic. It enjoys confluence but, as well as Parigot's lambda-mu, does not admit the Bohm Theorem, typical of the lambda-calculus. We present a simple extension of stack calculus which is for the stack calculus what Saurin's Lambda-mu is for lambda-mu.

  12. Implementation of AES as a Custom Hardware using NIOS II Processor

    Directory of Open Access Journals (Sweden)

    Meghana Hasamnis

    2012-08-01

    Full Text Available In this paper Advanced Encryption Standard (AES algorithm has been designed and implemented as custom hardware. The algorithm is controlled through C-code written in NIOS II IDE. AES as a custom hardware is interfaced with the system designed around NIOS II Processor using SOPC builder tool. AES is written in hardware in VHDL language and the interface is through GPIO (General Purpose Input / Output Port. AES implemented using data size of 128 bits, while the length of the key used is of 128 bits. The key size of AES used is of 128 bits, as it is secure from the different attacks in existence. The FPGA used is CYCLONE II from Altera. AES as a custom hardware increases the speed of encryption and serves as an accelerator and hence improves the performance of the system.

  13. Demagnetizing effects in stacked rectangular prisms

    DEFF Research Database (Denmark)

    Christensen, Dennis; Nielsen, Kaspar Kirstein; Bahl, Christian Robert Haffenden;

    2011-01-01

    configuration, temperature distribution and applied magnetic field. In this paper the model is applied to the case of a stack of parallel, ferromagnetic rectangular prisms and the resulting internal field is found as a function of the orientation of the applied field, the number of prisms in the stack, the...... spacing between the prisms and the packing density of the stack. The results show that the resulting internal field is far from being equal to the applied field and that the various stack configurations investigated affect the resulting internal field significantly and non-linearly. The results have a...

  14. Non-fuel bearing hardware melting technology

    International Nuclear Information System (INIS)

    Battelle has developed a portable hardware melter concept that would allow spent fuel rod consolidation operations at commercial nuclear power plants to provide significantly more storage space for other spent fuel assemblies in existing pool racks at lower cost. Using low pressure compaction, the non-fuel bearing hardware (NFBH) left over from the removal of spent fuel rods from the stainless steel end fittings and the Zircaloy guide tubes and grid spacers still occupies 1/3 to 2/5 of the volume of the consolidated fuel rod assemblies. Melting the non-fuel bearing hardware reduces its volume by a factor 4 from that achievable with low-pressure compaction. This paper describes: (1) the configuration and design features of Battelle's hardware melter system that permit its portability, (2) the system's throughput capacity, (3) the bases for capital and operating estimates, and (4) the status of NFBH melter demonstration to reduce technical risks for implementation of the concept. Since all NFBH handling and processing operations would be conducted at the reactor site, costs for shipping radioactive hardware to and from a stationary processing facility for volume reduction are avoided. Initial licensing, testing, and installation in the field would follow the successful pattern achieved with rod consolidation technology

  15. Dense Depth Map Reconstruction Using Special Purpose Hardware

    Science.gov (United States)

    Distante, A.; Mugnuolo, R.; Stella, E.; Attolico, G.

    1989-02-01

    The advancements in machine vision technology have been substantial in recent years with the introduction of faster processors and the improvements in sensor technology. A depth map can be obtained with both direct and indirect methods. The first ones recover depth directly from ranging devices. The second ones recover 3-D information by means of shape from xxx and stereopsis. Our idea consists of integration of information from two different source: local shading analysis and stereo vision. At present this alternate method has been tested with satisfactory results on conventional hardware but it's impracticable for computing time. The use of advanced parallel hardware is surely suitable to achieve the real time response, but it is not justified for some application fields (where response time is not very critical) because of its cost. An alternate choice can fall on low-cost and simple architectures that allow a configuration to achieve the required speed/cost ratio for a particular vision application by using a combination of standard modules. In this paper our method for depth recover is analyzed in order to enhance the critical steps for computing time. They are expressed in terms of computation suitable for standard and special purpose modules.

  16. Interactive histology of large-scale biomedical image stacks.

    Science.gov (United States)

    Jeong, Won-Ki; Schneider, Jens; Turney, Stephen G; Faulkner-Jones, Beverly E; Meyer, Dominik; Westermann, Rüdiger; Reid, R Clay; Lichtman, Jeff; Pfister, Hanspeter

    2010-01-01

    Histology is the study of the structure of biological tissue using microscopy techniques. As digital imaging technology advances, high resolution microscopy of large tissue volumes is becoming feasible; however, new interactive tools are needed to explore and analyze the enormous datasets. In this paper we present a visualization framework that specifically targets interactive examination of arbitrarily large image stacks. Our framework is built upon two core techniques: display-aware processing and GPU-accelerated texture compression. With display-aware processing, only the currently visible image tiles are fetched and aligned on-the-fly, reducing memory bandwidth and minimizing the need for time-consuming global pre-processing. Our novel texture compression scheme for GPUs is tailored for quick browsing of image stacks. We evaluate the usability of our viewer for two histology applications: digital pathology and visualization of neural structure at nanoscale-resolution in serial electron micrographs.

  17. Stacks of SPS Dipole Magnets

    CERN Multimedia

    1974-01-01

    Stacks of SPS Dipole Magnets ready for installation in the tunnel. The SPS uses a separated function lattice with dipoles for bending and quadrupoles for focusing. The 6.2 m long normal conducting dipoles are of H-type with coils that are bent-up at the ends. There are two types, B1 (total of 360) and B2 (384). Both are for a maximum field of 1.8 Tesla and have the same outer dimensions (450x800 mm2 vxh) but with different gaps (B1: 39x129 mm2, B2: 52x92 mm2) tailored to the beam size. The yoke, made of 1.5 mm thick laminations, consists of an upper and a lower half joined together in the median plane once the coils have been inserted.

  18. Communication Estimation for Hardware/Software Codesign

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1998-01-01

    This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended to be ge......This paper presents a general high level estimation model of communication throughput for the implementation of a given communication protocol. The model, which is part of a larger model that includes component price, software driver object code size and hardware driver area, is intended...... it provides a basis for decision making with respect to communication protocols/components and communication driver design in the initial design space exploration phase of a co-synthesis process where a large number of possibilities must be examined and where fast estimators are therefore necessary. The fill...... model allows for additional (money) cost, software code size and hardware area tradeoffs to be examined...

  19. A Hardware Abstraction Layer in Java

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Korsholm, Stephan; Kalibera, Tomas;

    2011-01-01

    Embedded systems use specialized hardware devices to interact with their environment, and since they have to be dependable, it is attractive to use a modern, type-safe programming language like Java to develop programs for them. Standard Java, as a platform-independent language, delegates access...... to devices, direct memory access, and interrupt handling to some underlying operating system or kernel, but in the embedded systems domain resources are scarce and a Java Virtual Machine (JVM) without an underlying middleware is an attractive architecture. The contribution of this article is a proposal...... for Java packages with hardware objects and interrupt handlers that interface to such a JVM. We provide implementations of the proposal directly in hardware, as extensions of standard interpreters, and finally with an operating system middleware. The latter solution is mainly seen as a migration path...

  20. Hardware Accelerators for Elliptic Curve Cryptography

    Directory of Open Access Journals (Sweden)

    C. Puttmann

    2008-05-01

    Full Text Available In this paper we explore different hardware accelerators for cryptography based on elliptic curves. Furthermore, we present a hierarchical multiprocessor system-on-chip (MPSoC platform that can be used for fast integration and evaluation of novel hardware accelerators. In respect of two application scenarios the hardware accelerators are coupled at different hierarchy levels of the MPSoC platform. The whole system is implemented in a state of the art 65 nm standard cell technology. Moreover, an FPGA-based rapid prototyping system for fast system verification is presented. Finally, a metric to analyze the resource efficiency by means of chip area, execution time and energy consumption is introduced.

  1. MFTF supervisory control and diagnostics system hardware

    International Nuclear Information System (INIS)

    The Supervisory Control and Diagnostics System (SCDS) for the Mirror Fusion Test Facility (MFTF) is a multiprocessor minicomputer system designed so that for most single-point failures, the hardware may be quickly reconfigured to provide continued operation of the experiment. The system is made up of nine Perkin-Elmer computers - a mixture of 8/32's and 7/32's. Each computer has ports on a shared memory system consisting of two independent shared memory modules. Each processor can signal other processors through hardware external to the shared memory. The system communicates with the Local Control and Instrumentation System, which consists of approximately 65 microprocessors. Each of the six system processors has facilities for communicating with a group of microprocessors; the groups consist of from four to 24 microprocessors. There are hardware switches so that if an SCDS processor communicating with a group of microprocessors fails, another SCDS processor takes over the communication

  2. Robot navigation system using intrinsic evolvable hardware

    Institute of Scientific and Technical Information of China (English)

    2001-01-01

    Recently there has been great interest in the idea that evolvable system based on the principle of ar tifcial intelligence can be used to continuously and autonomously adapt the behaviour of physically embedded systems such as autonomous mobile robots and intelligent home devices. Meanwhile, we have seen the introduc tion of evolvable hardware(EHW): new integrated electronic circuits that are able to continuously evolve to a dapt the chages in the environment implemented by evolutionary algorithms such as genetic algorithm(GA)and reinforcement learning. This paper concentrates on developing a robotic navigation system whose basic behav iours are obstacle avoidance and light source navigation. The results demonstrate that the intrinsic evolvable hardware system is able to create the stable robotiiuc behaviours as required in the real world instead of the tra ditional hardware systems.

  3. Quantitative hardware prediction modeling for hardware/software co-design

    NARCIS (Netherlands)

    Meeuws, R.J.

    2012-01-01

    Hardware estimation is an important factor in Hardware/Software Co-design. In this dissertation, we present the Quipu Modeling Approach, a high-level quantitative prediction model for HW/SW Partitioning using statistical methods. Our approach uses linear regression between software complexity metric

  4. Economic impact of syndesmosis hardware removal.

    Science.gov (United States)

    Lalli, Trapper A J; Matthews, Leslie J; Hanselman, Andrew E; Hubbard, David F; Bramer, Michelle A; Santrock, Robert D

    2015-09-01

    Ankle syndesmosis injuries are commonly seen with 5-10% of sprains and 10% of ankle fractures involving injury to the ankle syndesmosis. Anatomic reduction has been shown to be the most important predictor of clinical outcomes. Optimal surgical management has been a subject of debate in the literature. The method of fixation, number of screws, screw size, and number of cortices are all controversial. Postoperative hardware removal has also been widely debated in the literature. Some surgeons advocate for elective hardware removal prior to resuming full weightbearing. Returning to the operating room for elective hardware removal results in increased cost to the patient, potential for infection or complication(s), and missed work days for the patient. Suture button devices and bioabsorbable screw fixation present other options, but cortical screw fixation remains the gold standard. This retrospective review was designed to evaluate the economic impact of a second operative procedure for elective removal of 3.5mm cortical syndesmosis screws. Two hundred and two patients with ICD-9 code for "open treatment of distal tibiofibular joint (syndesmosis) disruption" were identified. The medical records were reviewed for those who underwent elective syndesmosis hardware removal. The primary outcome measurements included total hospital billing charges and total hospital billing collection. Secondary outcome measurements included average individual patient operative costs and average operating room time. Fifty-six patients were included in the study. Our institution billed a total of $188,271 (USD) and collected $106,284 (55%). The average individual patient operating room cost was $3579. The average operating room time was 67.9 min. To the best of our knowledge, no study has previously provided cost associated with syndesmosis hardware removal. Our study shows elective syndesmosis hardware removal places substantial economic burden on both the patient and the healthcare system.

  5. Human Centered Hardware Modeling and Collaboration

    Science.gov (United States)

    Stambolian Damon; Lawrence, Brad; Stelges, Katrine; Henderson, Gena

    2013-01-01

    In order to collaborate engineering designs among NASA Centers and customers, to in clude hardware and human activities from multiple remote locations, live human-centered modeling and collaboration across several sites has been successfully facilitated by Kennedy Space Center. The focus of this paper includes innovative a pproaches to engineering design analyses and training, along with research being conducted to apply new technologies for tracking, immersing, and evaluating humans as well as rocket, vehic le, component, or faci lity hardware utilizing high resolution cameras, motion tracking, ergonomic analysis, biomedical monitoring, wor k instruction integration, head-mounted displays, and other innovative human-system integration modeling, simulation, and collaboration applications.

  6. Hardware Accelerated Sequence Alignment with Traceback

    Directory of Open Access Journals (Sweden)

    Scott Lloyd

    2009-01-01

    in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is presented that accelerates the forward scan and traceback in hardware without memory and I/O limitations. With 256 processing elements in FPGA technology, a performance gain over 300 times that of a desktop computer is demonstrated on sequence lengths of 16000. For greater performance, the architecture is scalable to more processing elements.

  7. Language of CTO interventions - Focus on hardware.

    Science.gov (United States)

    Mishra, Sundeep

    2016-01-01

    The knowledge of variety of chronic total occlusion (CTO) hardware and the ability to use them represents the key to success of any CTO interventions. However, the multiplicity of CTO hardware and their physical character and the terminology used by experts create confusion in the mind of an average interventional cardiologist, particularly a beginner in this field. This knowledge is available but is scattered. We aim to classify and compare the currently used devices based on their properties focusing on how physical character of each device can be utilized in a specific situation, thus clarifying and simplifying the technical discourse.

  8. Do Stack Traces Help Developers Fix Bugs?

    NARCIS (Netherlands)

    Schröter, A.; Bettenburg, N.; Premraj, R.

    2010-01-01

    A widely shared belief in the software engineering community is that stack traces are much sought after by developers to support them in debugging. But limited empirical evidence is available to confirm the value of stack traces to developers. In this paper, we seek to provide such evidence by condu

  9. 49 CFR 178.815 - Stacking test.

    Science.gov (United States)

    2010-10-01

    ... qualification of all IBC design types intended to be stacked. (b) Special preparation for the stacking test. (1) All IBCs except flexible IBC design types must be loaded to their maximum permissible gross mass. (2) The flexible IBC must be filled to not less than 95 percent of its capacity and to its maximum...

  10. Excitation transfer in stacked quantum dot chains

    International Nuclear Information System (INIS)

    Stacked InAs quantum dot chains (QDCs) on InGaAs/GaAs cross-hatch pattern (CHP) templates yield a rich emission spectrum with an unusual carrier transfer characteristic compared to conventional quantum dot (QD) stacks. The photoluminescent spectra of the controlled, single QDC layer comprise multiple peaks from the orthogonal QDCs, the free-standing QDs, the CHP, the wetting layers and the GaAs substrate. When the QDC layers are stacked, employing a 10 nm GaAs spacer between adjacent QDC layers, the PL spectra are dominated by the top-most stack, indicating that the QDC layers are nominally uncoupled. Under high excitation power densities when the high-energy peaks of the top stack are saturated, however, low-energy PL peaks from the bottom stacks emerge as a result of carrier transfers across the GaAs spacers. These unique PL signatures contrast with the state-filling effects in conventional, coupled QD stacks and serve as a means to quickly assess the presence of electronic coupling in stacks of dissimilar-sized nanostructures. (paper)

  11. Learning OpenStack networking (Neutron)

    CERN Document Server

    Denton, James

    2014-01-01

    If you are an OpenStack-based cloud operator with experience in OpenStack Compute and nova-network but are new to Neutron networking, then this book is for you. Some networking experience is recommended, and a physical network infrastructure is required to provide connectivity to instances and other network resources configured in the book.

  12. Demagnetizing effects in stacked rectangular prisms

    International Nuclear Information System (INIS)

    A numerical, magnetostatic model of the internal magnetic field of a rectangular prism is extended to the case of a stack of rectangular prisms. The model enables the calculation of the spatially resolved, three-dimensional internal field in such a stack given any magnetic state function, stack configuration, temperature distribution and applied magnetic field. In this paper the model is applied to the case of a stack of parallel, ferromagnetic rectangular prisms and the resulting internal field is found as a function of the orientation of the applied field, the number of prisms in the stack, the spacing between the prisms and the packing density of the stack. The results show that the resulting internal field is far from being equal to the applied field and that the various stack configurations investigated affect the resulting internal field significantly and non-linearly. The results have a direct impact on the design of, e.g., active magnetic regenerators made of stacked rectangular prisms in terms of optimizing the internal field.

  13. Stacking technology for a space constrained microsystem

    DEFF Research Database (Denmark)

    Heschel, Matthias; Kuhmann, Jochen Friedrich; Bouwstra, Siebe;

    1998-01-01

    In this paper we present a stacking technology for an integrated packaging of an intelligent transducer which is formed by a micromachined silicon transducer and an integrated circuit chip. Transducer and circuitry are stacked on top of each other with an intermediate chip in between. The bonding...

  14. Modular fuel-cell stack assembly

    Science.gov (United States)

    Patel, Pinakin

    2010-07-13

    A fuel cell assembly having a plurality of fuel cells arranged in a stack. An end plate assembly abuts the fuel cell at an end of said stack. The end plate assembly has an inlet area adapted to receive an exhaust gas from the stack, an outlet area and a passage connecting the inlet area and outlet area and adapted to carry the exhaust gas received at the inlet area from the inlet area to the outlet area. A further end plate assembly abuts the fuel cell at a further opposing end of the stack. The further end plate assembly has a further inlet area adapted to receive a further exhaust gas from the stack, a further outlet area and a further passage connecting the further inlet area and further outlet area and adapted to carry the further exhaust gas received at the further inlet area from the further inlet area to the further outlet area.

  15. Status of MCFC stack technology at IHI

    Energy Technology Data Exchange (ETDEWEB)

    Hosaka, M.; Morita, T.; Matsuyama, T.; Otsubo, M. [Ishikawajima-Harima Heavy Industries Co., Ltd., Tokyo (Japan)

    1996-12-31

    The molten carbonate fuel cell (MCFC) is a promising option for highly efficient power generation possible to enlarge. IHI has been studying parallel flow MCFC stacks with internal manifolds that have a large electrode area of 1m{sup 2}. IHI will make two 250 kW stacks for MW plant, and has begun to make cell components for the plant. To improve the stability of stack, soft corrugated plate used in the separator has been developed, and a way of gathering current from stacks has been studied. The DC output potential of the plant being very high, the design of electric insulation will be very important. A 20 kW short stack test was conducted in 1995 FY to certificate some of the improvements and components of the MW plant. These activities are presented below.

  16. Electrochemical Characterization and Degradation Analysis of Large SOFC Stacks by Impedance Spectroscopy

    DEFF Research Database (Denmark)

    Mosbæk, Rasmus Rode; Hjelm, Johan; Barfod, R.;

    2013-01-01

    As solid oxide fuel cell (SOFC) technology is moving closer to a commercial break through, lifetime limiting factors, and methods to measure the “state-of-health” of operating cells and stacks are becoming of increasing interest. This requires application of advanced methods for detailed electroc......As solid oxide fuel cell (SOFC) technology is moving closer to a commercial break through, lifetime limiting factors, and methods to measure the “state-of-health” of operating cells and stacks are becoming of increasing interest. This requires application of advanced methods for detailed...

  17. Stacking fault probability and stacking fault energy in CoNi alloys

    Institute of Scientific and Technical Information of China (English)

    周伟敏; 江伯鸿; 刘岩; 漆王睿

    2001-01-01

    The stacking fault probability of CoNi alloys with different contents of Ni was measured by X-ray diffraction methods. The results show that the stacking fault decreases with increasing Ni content and with increasing temperature. The thermodynamical calculation has found an equation that can express the stacking fault energy γ of CoNi at temperature T. The phase equilibrium temperature depends on the composition of the certain alloy. The relationship between stacking fault energy γ and stacking fault probability Psf is determined.

  18. Development of a driver information and warning system with vehicle hardware-in-the-loop simulations

    NARCIS (Netherlands)

    Gietelink, O.J.; Ploeg, J.; Schutter, B. de; Verhaegen, M.

    2009-01-01

    This paper presents a new method for the design and validation of advanced driver assistance systems (ADASs). With vehicle hardware-in-the-loop (VeHIL) simulations the development process, and more specifically the validation phase, of intelligent vehicles is carried out safer, cheaper, and more man

  19. A Cost-Effective Approach to Hardware-in-the-Loop Simulation

    DEFF Research Database (Denmark)

    Pedersen, Mikkel Melters; Hansen, M. R.; Ballebye, M.

    2012-01-01

    This paper presents an approach for developing cost effective hardware-in-the- loop (HIL) simulation platforms for the use in controller software test and development. The approach is aimed at the many smaller manufacturers of e.g. mobile hydraulic machinery, which often do not have very advanced...

  20. Image Interpolation With Dedicated Digital Hardware

    Science.gov (United States)

    Hartenstein, R.; Wagner, G.; Simons, D.; Coulson, J.

    1986-01-01

    Algorithm for interpolating two-dimensional image data to change picture-element spacing implemented in dedicated digital hardware for high-speed execution. System interpolates 100 times as fast as generalpurpose computer. Image resampling occurs first along one image axis and then along other, using two interpolation devices implemented in series.

  1. The fast Amsterdam multiprocessor (FAMP) system hardware

    CERN Document Server

    Hertzberger, L O; Kieft, G; Kisielewski, B; Van Koningsveld, L; Wiggers, L W

    1981-01-01

    The architecture of a multiprocessor system is described that will be used for online filter and second stage trigger applications. The system is based on the MC68000 microprocessor from Motorola. Emphasis is paid to hardware aspects, in particular the modularity, processor communication and interfacing. (8 refs).

  2. Computer hardware for radiologists: Part I.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration. PMID:21042437

  3. Computer hardware for radiologists: Part I

    International Nuclear Information System (INIS)

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called “buses”. The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute “programs”. A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration

  4. QCE : A Simulator for Quantum Computer Hardware

    NARCIS (Netherlands)

    Michielsen, Kristel; Raedt, Hans De

    2003-01-01

    The Quantum Computer Emulator (QCE) described in this paper consists of a simulator of a generic, general purpose quantum computer and a graphical user interface. The latter is used to control the simulator, to define the hardware of the quantum computer and to debug and execute quantum algorithms.

  5. Enabling Open Hardware through FOSS tools

    CERN Document Server

    CERN. Geneva

    2016-01-01

    Software developers often take open file formats and tools for granted. When you publish code on github, you do not ask yourself if somebody will be able to open it and modify it. We need the same freedom in the open hardware world, to make it truly accessible for everyone.

  6. Digital Hardware Design Teaching: An Alternative Approach

    Science.gov (United States)

    Benkrid, Khaled; Clayton, Thomas

    2012-01-01

    This article presents the design and implementation of a complete review of undergraduate digital hardware design teaching in the School of Engineering at the University of Edinburgh. Four guiding principles have been used in this exercise: learning-outcome driven teaching, deep learning, affordability, and flexibility. This has identified…

  7. Hardware Accelerated Point Rendering of Isosurfaces

    DEFF Research Database (Denmark)

    Bærentzen, Jakob Andreas; Christensen, Niels Jørgen

    2003-01-01

    and that the advantage of rendering points as opposed to triangles increases with the size and complexity of the volumes. To gauge the visual quality of future hardware accelerated point rendering schemes, we have implemented a software based point rendering method and compare the quality to both MC and our OpenGL based...

  8. Computer hardware for radiologists: Part I

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM, Picture Archiving and Communication System (PACS, Radiology information system (RIS technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU, the chipset, the random access memory (RAM, the memory modules, bus, storage drives, and ports. The personnel computer (PC has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs. The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium® 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  9. Arbitrary Hardware Software Trade-Offs

    NARCIS (Netherlands)

    Middelhoek, Peter F.A.

    1995-01-01

    This paper discusses a novel transformation-based design methodology and its use in the design of complex programmable VLSI systems. During the life-cycle of a complex system, the optimal trade-off between partially implementing in hardware or software is changing. This is due to varying system requ

  10. Microprocessor Design Using Hardware Description Language

    Science.gov (United States)

    Mita, Rosario; Palumbo, Gaetano

    2008-01-01

    The following paper has been conceived to deal with the contents of some lectures aimed at enhancing courses on digital electronic, microelectronic or VLSI systems. Those lectures show how to use a hardware description language (HDL), such as the VHDL, to specify, design and verify a custom microprocessor. The general goal of this work is to teach…

  11. Computer hardware for radiologists: Part I.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-08-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware relevant to radiology practice is presented here. The key hardware components in a computer are the motherboard, central processor unit (CPU), the chipset, the random access memory (RAM), the memory modules, bus, storage drives, and ports. The personnel computer (PC) has a rectangular case that contains important components called hardware, many of which are integrated circuits (ICs). The fiberglass motherboard is the main printed circuit board and has a variety of important hardware mounted on it, which are connected by electrical pathways called "buses". The CPU is the largest IC on the motherboard and contains millions of transistors. Its principal function is to execute "programs". A Pentium(®) 4 CPU has transistors that execute a billion instructions per second. The chipset is completely different from the CPU in design and function; it controls data and interaction of buses between the motherboard and the CPU. Memory (RAM) is fundamentally semiconductor chips storing data and instructions for access by a CPU. RAM is classified by storage capacity, access speed, data rate, and configuration.

  12. A mathematical approach towards hardware design

    NARCIS (Netherlands)

    Smit, Gerard J.M.; Kuper, Jan; Baaij, Christiaan P.R.; Athanas, P.M.; Becker, J.; Teich, J.; Verbauwhede, I.

    2010-01-01

    Today the hardware for embedded systems is often specified in VHDL. However, VHDL describes the system at a rather low level, which is cumbersome and may lead to design faults in large real life applications. There is a need of higher level abstraction mechanisms. In the embedded systems group of th

  13. CAMAC high energy physics electronics hardware

    International Nuclear Information System (INIS)

    CAMAC hardware for high energy physics large spectrometers and control systems is reviewed as is the development of CAMAC modules at the High Energy Laboratory, JINR (Dubna). The total number of crates used at the Laboratory is 179. The number of CAMAC modules of 120 different types exceeds 1700. The principles of organization and the structure of developed CAMAC systems are described. (author)

  14. Postflight hardware evaluation (RSRM-29, STS-54)

    Science.gov (United States)

    1993-09-01

    This document is the final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-29 flight set. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64221), represents a summary of the RSRM-29 hardware evaluation. Disassembly evaluation photograph numbers are logged in TWA-1990. The RSRM-29 flight set disassembly evaluations described in this document were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on September 9, 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  15. Bipolarly stacked electrolyser for energy and space efficient fabrication of supercapacitor electrodes

    Science.gov (United States)

    Liu, Xiaojuan; Wu, Tao; Dai, Zengxin; Tao, Keran; Shi, Yong; Peng, Chuang; Zhou, Xiaohang; Chen, George Z.

    2016-03-01

    Stacked electrolysers with titanium bipolar plates are constructed for electrodeposition of polypyrrole electrodes for supercapacitors. The cathode side of the bipolar Ti plates are pre-coated with activated carbon. In this new design, half electrolysis occurs which significantly lowers the deposition voltage. The deposited electrodes are tested in a symmetrical unit cell supercapacitor and an asymmetrical supercapacitor stack. Both devices show excellent energy storage performances and the capacitance values are very close to the design value, suggesting a very high current efficiency during the electrodeposition. The electrolyser stack offers multi-fold benefits for preparation of conducting polymer electrodes, i.e. low energy consumption, facile control of the electrode capacitance and simultaneous preparation of a number of identical electrodes. Therefore, the stacked bipolar electrolyser is a technology advance that offers an engineering solution for mass production of electrodeposited conducting polymer electrodes for supercapacitors.

  16. Density of oxidation-induced stacking faults in damaged silicon

    NARCIS (Netherlands)

    Kuper, F.G.; Hosson, J.Th.M. De; Verwey, J.F.

    1986-01-01

    A model for the relation between density and length of oxidation-induced stacking faults on damaged silicon surfaces is proposed, based on interactions of stacking faults with dislocations and neighboring stacking faults. The model agrees with experiments.

  17. Vector Fields and Flows on Differentiable Stacks

    DEFF Research Database (Denmark)

    A. Hepworth, Richard

    2009-01-01

    and uniqueness of flows on a manifold as well as the author's existing results for orbifolds. It sets the scene for a discussion of Morse Theory on a general proper stack and also paves the way for the categorification of other key aspects of differential geometry such as the tangent bundle and the Lie algebra......This paper introduces the notions of vector field and flow on a general differentiable stack. Our main theorem states that the flow of a vector field on a compact proper differentiable stack exists and is unique up to a uniquely determined 2-cell. This extends the usual result on the existence...

  18. Do Stack Traces Help Developers Fix Bugs?

    OpenAIRE

    Schröter, A; Bettenburg, N.; Premraj, R

    2010-01-01

    A widely shared belief in the software engineering community is that stack traces are much sought after by developers to support them in debugging. But limited empirical evidence is available to confirm the value of stack traces to developers. In this paper, we seek to provide such evidence by conducting an empirical study on the usage of stack traces by developers from the ECLIPSE project. Our results provide strong evidence to this effect and also throws light on some of the patterns in bug...

  19. Dynamical Stability of Slip-stacking Particles

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, Jeffrey [Fermilab; Zwaska, Robert [Fermilab

    2014-09-04

    We study the stability of particles in slip-stacking configuration, used to nearly double proton beam intensity at Fermilab. We introduce universal area factors to calculate the available phase space area for any set of beam parameters without individual simulation. We find perturbative solutions for stable particle trajectories. We establish Booster beam quality requirements to achieve 97% slip-stacking efficiency. We show that slip-stacking dynamics directly correspond to the driven pendulum and to the system of two standing-wave traps moving with respect to each other.

  20. Parallel transport on principal bundles over stacks

    Science.gov (United States)

    Collier, Brian; Lerman, Eugene; Wolbert, Seth

    2016-09-01

    In this paper we introduce a notion of parallel transport for principal bundles with connections over differentiable stacks. We show that principal bundles with connections over stacks can be recovered from their parallel transport thereby extending the results of Barrett, Caetano and Picken, and Schreiber and Waldorf from manifolds to stacks. In the process of proving our main result we simplify Schreiber and Waldorf's original definition of a transport functor for principal bundles with connections over manifolds and provide a more direct proof of the correspondence between principal bundles with connections and transport functors.

  1. Hardware-software Reconfigurable Techniques for Wireless Sensor Network

    Directory of Open Access Journals (Sweden)

    C. Rajasekaran

    2014-11-01

    Full Text Available Now-a-days, the industrial based real time embedded applications are highly developed and they act as a major role in the production cost and real world safety environment. In that, one of the advanced technique is that reconfigurable techniques. This technique plays a major role with wireless sensor networks for the efficient data transmissions. In recent days, most of the industrial applications are works to minimize the size and cost of device. The foremost improvement of the reconfigurable technique is that it circumvents the unnecessary hang and deferral in the device performance. In modern biosphere, Field Programmable Gate Array (FPGA is one of the supreme operative reconfigurable devices and generally used for most of the hardware and software reconfiguration applications. In this study, the exertion pacts with whatever going to make changes in the hardware and software during runtime, it should not disturb the present successively process. This is the main impartial of the study that the changes to be done in an analogous manner at the same time concentrating the cost and power transmission problems during data trans-receiving and also the results to be seen with the help of online manner via the Ethernet cable.

  2. Campus Information Network Hardware System Design%Campus Information Network Hardware System Design

    Institute of Scientific and Technical Information of China (English)

    刘正勇

    2011-01-01

    The emphasis of constructing and developing the campus information network is how to design and optimize the network hardware system. This paper mainly studies the network system structure design, the server system structure design and the network export

  3. Separated Control and Data Stacks to Mitigate Buffer Overflow Exploits

    OpenAIRE

    Christopher Kugler; Tilo Müller

    2015-01-01

    Despite the fact that protection mechanisms like StackGuard, ASLR and NX are widespread, the development on new defense strategies against stack-based buffer overflows has not yet come to an end. In this article, we present a novel compiler-level protection called SCADS: Separated Control and Data Stacks that protects return addresses and saved frame pointers on a separate stack, called the control stack. In common computer programs, a single user mode stack is used to store control informati...

  4. Reconfigurable hardware for an augmented reality application

    Science.gov (United States)

    Toledo Moreo, F. Javier; Martinez Alvarez, J. Javier; Garrigos Guerrero, F. Javier; Ferrandez Vicente, J. Manuel

    2005-06-01

    An FPGA-based approach is proposed to build an augmented reality system in order to aid people affected by a visual disorder known as tunnel vision. The aim is to increase the user's knowledge of his environment by superimposing on his own view useful information obtained with image processing. Two different alternatives have been explored to perform the required image processing: a specific purpose algorithm to extract edge detection information, and a cellular neural network with the suitable template. Their implementations in reconfigurable hardware pursue to take advantage of the performance and flexibility that show modern FPGAs. This paper describes the hardware implementation of both the Canny algorithm and the cellular neural network, and the overall system architecture. Results of the implementations and examples of the system functionality are presented.

  5. Autonomous distributed self-organizing and self-healing hardware architecture - The eDNA concept

    DEFF Research Database (Denmark)

    Boesen, Michael Reibel; Madsen, Jan; Keymeulen, Didier

    2011-01-01

    This paper presents the current state of the autonomous distributed self-organizing and self-healing electronic DNA (eDNA) hardware architecture (patent pending). In its current prototype state, the eDNA architecture is capable of responding to multiple injected faults by autonomously reconfiguring...... itself to accommodate the fault and keep the application running. This paper will also disclose advanced features currently available in the simulation model only. These features are future work and will soon be implemented in hardware. Finally we will describe step-by-step how an application...

  6. AVR microcontroller simulator for software implemented hardware fault tolerance algorithms research

    Science.gov (United States)

    Piotrowski, Adam; Tarnowski, Szymon; Napieralski, Andrzej

    2008-01-01

    Reliability of new, advanced electronic systems becomes a serious problem especially in places like accelerators and synchrotrons, where sophisticated digital devices operate closely to radiation sources. One of the possible solutions to harden the microprocessor-based system is a strict programming approach known as the Software Implemented Hardware Fault Tolerance. Unfortunately, in real environments it is not possible to perform precise and accurate tests of the new algorithms due to hardware limitation. This paper highlights the AVR-family microcontroller simulator project equipped with an appropriate monitoring and the SEU injection systems.

  7. Computer hardware for radiologists: Part I

    OpenAIRE

    Indrajit I; Alam A

    2010-01-01

    Computers are an integral part of modern radiology practice. They are used in different radiology modalities to acquire, process, and postprocess imaging data. They have had a dramatic influence on contemporary radiology practice. Their impact has extended further with the emergence of Digital Imaging and Communications in Medicine (DICOM), Picture Archiving and Communication System (PACS), Radiology information system (RIS) technology, and Teleradiology. A basic overview of computer hardware...

  8. Hardware Virtualization towards a Proficient Computing Environment

    OpenAIRE

    Shweta Agrawal

    2013-01-01

    In the recent few years Server Virtualization and Green Information Technology have become very popular and are fast becoming the norm in organizations of all disciplines and sizes. Today, different methods of energy savings are in use and in great demand. One of the newest methods in the IT to control the pollution of the environment and the greenhouse effect is Green IT that is directly connected with the Virtualization of Hardware Resources.Virtualization is the presentation of an environm...

  9. Hardware-Independent Proofs of Numerical Programs

    Science.gov (United States)

    Boldo, Sylvie; Nguyen, Thi Minh Tuyen

    2010-01-01

    On recent architectures, a numerical program may give different answers depending on the execution hardware and the compilation. Our goal is to formally prove properties about numerical programs that are true for multiple architectures and compilers. We propose an approach that states the rounding error of each floating-point computation whatever the environment. This approach is implemented in the Frama-C platform for static analysis of C code. Small case studies using this approach are entirely and automatically proved

  10. Compressive Sensing Image Sensors-Hardware Implementation

    OpenAIRE

    Shahram Shirani; M. Jamal Deen; Mohammadreza Dadkhah

    2013-01-01

    The compressive sensing (CS) paradigm uses simultaneous sensing and compression to provide an efficient image acquisition technique. The main advantages of the CS method include high resolution imaging using low resolution sensor arrays and faster image acquisition. Since the imaging philosophy in CS imagers is different from conventional imaging systems, new physical structures have been developed for cameras that use the CS technique. In this paper, a review of different hardware implementa...

  11. Particle Transport Simulation on Heterogeneous Hardware

    CERN Document Server

    CERN. Geneva

    2014-01-01

    CPUs and GPGPUs. About the speaker Vladimir Koylazov is CTO and founder of Chaos Software and one of the original developers of the V-Ray raytracing software. Passionate about 3D graphics and programming, Vlado is the driving force behind Chaos Group's software solutions. He participated in the implementation of algorithms for accurate light simulations and support for different hardware platforms, including CPU and GPGPU, as well as distributed calculat...

  12. Hardware Accelerated Sequence Alignment with Traceback

    OpenAIRE

    Scott Lloyd; Snell, Quinn O

    2009-01-01

    Biological sequence alignment is an essential tool used in molecular biology and biomedical applications. The growing volume of genetic data and the complexity of sequence alignment present a challenge in obtaining alignment results in a timely manner. Known methods to accelerate alignment on reconfigurable hardware only address sequence comparison, limit the sequence length, or exhibit memory and I/O bottlenecks. A space-efficient, global sequence alignment algorithm and architecture is pres...

  13. PERFORMANCE ANALYSIS OF HARDWARE TROJAN DETECTION METHODS

    OpenAIRE

    Ehsan, Sharifi; Kamal, Mohammadiasl; Mehrdad, Havasi; Amir, Yazdani

    2015-01-01

    Due to the increasing use of information and communication technologies in most aspects of life, security of the information has drawn the attention of governments and industry as well as the researchers. In this regard, structural attacks on the functions of a chip are called hardware Trojans, and are capable of rendering ineffective the security protecting our systems and data. This method represents a big challenge for cyber-security as it is nearly impossible to detect with any currently ...

  14. Acceleration of Astrophysical Simulations with Special Hardware

    OpenAIRE

    Marcus Martinez, Guillermo Anibal

    2011-01-01

    This work presents the raceSPH and raceGRAV accelerator libraries, designed to interface astrophysical simulations with special-purpose hardware. The raceSPH focuses on the acceleration of Smoothed Particle Hydrodynamics (SPH), a method for approximating force interactions in fluid dynamics. Accelerators used range from vectorizing units on the microprocessors to Field Programmable Gate Arrays (FPGAs) and Graphics Processing Units (GPUs), and speed-ups range from 1.2x to 28x when measured in ...

  15. Trends in computer hardware and software.

    Science.gov (United States)

    Frankenfeld, F M

    1993-04-01

    Previously identified and current trends in the development of computer systems and in the use of computers for health care applications are reviewed. Trends identified in a 1982 article were increasing miniaturization and archival ability, increasing software costs, increasing software independence, user empowerment through new software technologies, shorter computer-system life cycles, and more rapid development and support of pharmaceutical services. Most of these trends continue today. Current trends in hardware and software include the increasing use of reduced instruction-set computing, migration to the UNIX operating system, the development of large software libraries, microprocessor-based smart terminals that allow remote validation of data, speech synthesis and recognition, application generators, fourth-generation languages, computer-aided software engineering, object-oriented technologies, and artificial intelligence. Current trends specific to pharmacy and hospitals are the withdrawal of vendors of hospital information systems from the pharmacy market, improved linkage of information systems within hospitals, and increased regulation by government. The computer industry and its products continue to undergo dynamic change. Software development continues to lag behind hardware, and its high cost is offsetting the savings provided by hardware. PMID:8470690

  16. A Hardware Lab Anywhere At Any Time

    Directory of Open Access Journals (Sweden)

    Tobias Schubert

    2004-12-01

    Full Text Available Scientific technical courses are an important component in any student's education. These courses are usually characterised by the fact that the students execute experiments in special laboratories. This leads to extremely high costs and a reduction in the maximum number of possible participants. From this traditional point of view, it doesn't seem possible to realise the concepts of a Virtual University in the context of sophisticated technical courses since the students must be "on the spot". In this paper we introduce the so-called Mobile Hardware Lab which makes student participation possible at any time and from any place. This lab nevertheless transfers a feeling of being present in a laboratory. This is accomplished with a special Learning Management System in combination with hardware components which correspond to a fully equipped laboratory workstation that are lent out to the students for the duration of the lab. The experiments are performed and solved at home, then handed in electronically. Judging and marking are also both performed electronically. Since 2003 the Mobile Hardware Lab is now offered in a completely web based form.

  17. "Greenbook Algorithms and Hardware Needs Analysis"

    Energy Technology Data Exchange (ETDEWEB)

    De Jong, Wibe A.; Oehmen, Chris S.; Baxter, Douglas J.

    2007-01-09

    "This document describes the algorithms, and hardware balance requirements needed to enable the solution of real scientific problems in the DOE core mission areas of environmental and subsurface chemistry, computational and systems biology, and climate science. The MSCF scientific drivers have been outlined in the Greenbook, which is available online at http://mscf.emsl.pnl.gov/docs/greenbook_for_web.pdf . Historically, the primary science driver has been the chemical and the molecular dynamics of the biological science area, whereas the remaining applications in the biological and environmental systems science areas have been occupying a smaller segment of the available hardware resources. To go from science drivers to hardware balance requirements, the major applications were identified. Major applications on the MSCF resources are low- to high-accuracy electronic structure methods, molecular dynamics, regional climate modeling, subsurface transport, and computational biology. The algorithms of these applications were analyzed to identify the computational kernels in both sequential and parallel execution. This analysis shows that a balanced architecture is needed with respect to processor speed, peak flop rate, peak integer operation rate, and memory hierarchy, interprocessor communication, and disk access and storage. A single architecture can satisfy the needs of all of the science areas, although some areas may take greater advantage of certain aspects of the architecture. "

  18. The stack on software and sovereignty

    CERN Document Server

    Bratton, Benjamin H

    2016-01-01

    A comprehensive political and design theory of planetary-scale computation proposing that The Stack -- an accidental megastructure -- is both a technological apparatus and a model for a new geopolitical architecture.

  19. Stacking for Cosmic Magnetism with SKA Surveys

    CERN Document Server

    Stil, J M

    2015-01-01

    Stacking polarized radio emission in SKA surveys provides statistical information on large samples that is not accessible otherwise due to limitations in sensitivity, source statistics in small fields, and averaging over frequency (including Faraday synthesis). Polarization is a special case because one obvious source of stacking targets is the Stokes I source catalog, possibly in combination with external catalogs, for example an SKA HI survey or a non-radio survey. We point out the significance of stacking sub-samples selected by additional observable parameters to investigate relations that reveal more about the physics of the source. Applications of stacking polarization include, but are not limited to, obtaining in a statistical sense polarization information to the detection limit in total intensity, depolarization as a function of cosmic time at consistent source-frame wavelengths, magnetic field properties in objects with a low radio luminosity such as dwarf and low-surface-brightness galaxies, and in...

  20. Characterization of Piezoelectric Stacks for Space Applications

    Science.gov (United States)

    Sherrit, Stewart; Jones, Christopher; Aldrich, Jack; Blodget, Chad; Bao, Xiaoqi; Badescu, Mircea; Bar-Cohen, Yoseph

    2008-01-01

    Future NASA missions are increasingly seeking to actuate mechanisms to precision levels in the nanometer range and below. Co-fired multilayer piezoelectric stacks offer the required actuation precision that is needed for such mechanisms. To obtain performance statistics and determine reliability for extended use, sets of commercial PZT stacks were tested in various AC and DC conditions at both nominal and high temperatures and voltages. In order to study the lifetime performance of these stacks, five actuators were driven sinusoidally for up to ten billion cycles. An automated data acquisition system was developed and implemented to monitor each stack's electrical current and voltage waveforms over the life of the test. As part of the monitoring tests, the displacement, impedance, capacitance and leakage current were measured to assess the operation degradation. This paper presents some of the results of this effort.

  1. Turing Impossibility Properties for Stack Machine Programming

    NARCIS (Netherlands)

    J.A. Bergstra; C.A. Middelburg

    2012-01-01

    The strong, intermediate, and weak Turing impossibility properties are introduced. Some facts concerning Turing impossibility for stack machine programming are trivially adapted from previous work. Several intriguing questions are raised about the Turing impossibility properties concerning different

  2. Development of an automatic subsea blowout preventer stack control system using PLC based SCADA.

    Science.gov (United States)

    Cai, Baoping; Liu, Yonghong; Liu, Zengkai; Wang, Fei; Tian, Xiaojie; Zhang, Yanzhen

    2012-01-01

    An extremely reliable remote control system for subsea blowout preventer stack is developed based on the off-the-shelf triple modular redundancy system. To meet a high reliability requirement, various redundancy techniques such as controller redundancy, bus redundancy and network redundancy are used to design the system hardware architecture. The control logic, human-machine interface graphical design and redundant databases are developed by using the off-the-shelf software. A series of experiments were performed in laboratory to test the subsea blowout preventer stack control system. The results showed that the tested subsea blowout preventer functions could be executed successfully. For the faults of programmable logic controllers, discrete input groups and analog input groups, the control system could give correct alarms in the human-machine interface. PMID:21889767

  3. Technology leadership: a road map to commercially viable PEMFC stack technology. Paper no. IGEC-1-008

    International Nuclear Information System (INIS)

    'Full text:' In February 2005, Ballard announced its most recent advances in PEMFC stack technology. This technology development exhibited, we believe, for the first time the capability of a single PEMFC stack design to demonstrate combined excellence in cost reduction, freeze start capability from -20 C and durability under an automotive OEM defined dynamic operating cycle, comparable to that experienced by a fuel cell stack in an actual vehicle. One month later, building on the above technology leadership demonstration, Ballard announced a technology 'oad map' that defined a path to commercially viability for a PEMFC stack by 2010. The key target parameters for cost reduction, durability, freeze start and stack power density are described in detail along with demonstrated historical capability and a clear path as to how Ballard will achieve the required targets. (author)

  4. A hardware implementation of neural network with modified HANNIBAL architecture

    Energy Technology Data Exchange (ETDEWEB)

    Lee, Bum youb; Chung, Duck Jin [Inha University, Inchon (Korea, Republic of)

    1996-03-01

    A digital hardware architecture for artificial neural network with learning capability is described in this paper. It is a modified hardware architecture known as HANNIBAL(Hardware Architecture for Neural Networks Implementing Back propagation Algorithm Learning). For implementing an efficient neural network hardware, we analyzed various type of multiplier which is major function block of neuro-processor cell. With this result, we design a efficient digital neural network hardware using serial/parallel multiplier, and test the operation. We also analyze the hardware efficiency with logic level simulation. (author). 14 refs., 10 figs., 3 tabs.

  5. Exploring online evolution of network stacks

    OpenAIRE

    Imai, Pierre

    2013-01-01

    Network stacks today follow a one-size-fits-all philosophy. They are mostly kept unmodified due to often prohibitive costs of engineering, deploying and administrating customisation of the networking software, with the Internet stack architecture still largely being based on designs and assumptions made for the ARPANET 40 years ago. We venture that heterogeneous and rapidly changing networks of the future require, in order to be successful, run-time self-adaptation mechanisms at different tim...

  6. Stacking fault energy in some single crystals

    Institute of Scientific and Technical Information of China (English)

    Aditya M.Vora

    2012-01-01

    The stacking fault energy of single crystals has been reported using the peak shift method.Presently studied all single crystals are grown by using a direct vapor transport (DVT) technique in the laboratory.The structural characterizations of these crystals are made by XRD.Considerable variations are shown in deformation (α) and growth (β) probabilities in single crystals due to off-stoichiometry,which possesses the stacking fault in the single crystal.

  7. Stacking interactions in PUF-RNA complexes

    Energy Technology Data Exchange (ETDEWEB)

    Yiling Koh, Yvonne; Wang, Yeming; Qiu, Chen; Opperman, Laura; Gross, Leah; Tanaka Hall, Traci M; Wickens, Marvin [NIH; (UW)

    2012-07-02

    Stacking interactions between amino acids and bases are common in RNA-protein interactions. Many proteins that regulate mRNAs interact with single-stranded RNA elements in the 3' UTR (3'-untranslated region) of their targets. PUF proteins are exemplary. Here we focus on complexes formed between a Caenorhabditis elegans PUF protein, FBF, and its cognate RNAs. Stacking interactions are particularly prominent and involve every RNA base in the recognition element. To assess the contribution of stacking interactions to formation of the RNA-protein complex, we combine in vivo selection experiments with site-directed mutagenesis, biochemistry, and structural analysis. Our results reveal that the identities of stacking amino acids in FBF affect both the affinity and specificity of the RNA-protein interaction. Substitutions in amino acid side chains can restrict or broaden RNA specificity. We conclude that the identities of stacking residues are important in achieving the natural specificities of PUF proteins. Similarly, in PUF proteins engineered to bind new RNA sequences, the identity of stacking residues may contribute to 'target' versus 'off-target' interactions, and thus be an important consideration in the design of proteins with new specificities.

  8. AN ELECTROCHEMICAL SYSTEM FOR REMOVING AND RECOVERING ELEMENTAL MERCURY FROM FLUE-STACK GASES

    Science.gov (United States)

    the impending EPA regulations on the control of mercury emissions from the flue stacks of coal-burning electric utilities has resulted in heightened interest in the development of advanced mercury control technologies such as sorbent injection and in-situ mercury oxidation. Altho...

  9. A Self-Provisioning Mechanism in OpenStack for IoT Devices

    Science.gov (United States)

    Solano, Antonio; Dormido, Raquel; Duro, Natividad; Sánchez, Juan Miguel

    2016-01-01

    The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT) device to instantiate a Software as a Service (SaaS) application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device. PMID:27548166

  10. A Self-Provisioning Mechanism in OpenStack for IoT Devices.

    Science.gov (United States)

    Solano, Antonio; Dormido, Raquel; Duro, Natividad; Sánchez, Juan Miguel

    2016-01-01

    The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT) device to instantiate a Software as a Service (SaaS) application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device. PMID:27548166

  11. A Self-Provisioning Mechanism in OpenStack for IoT Devices

    Directory of Open Access Journals (Sweden)

    Antonio Solano

    2016-08-01

    Full Text Available The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT device to instantiate a Software as a Service (SaaS application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device.

  12. A Self-Provisioning Mechanism in OpenStack for IoT Devices.

    Science.gov (United States)

    Solano, Antonio; Dormido, Raquel; Duro, Natividad; Sánchez, Juan Miguel

    2016-08-17

    The aim of this paper is to introduce a plug-and-play mechanism for an Internet of Things (IoT) device to instantiate a Software as a Service (SaaS) application in a private cloud, built up with OpenStack. The SaaS application is the digital avatar of a physical object connected to Internet. As a proof of concept, a Vending Machine is retrofitted and connected to Internet with and Arduino Open Hardware device. Once the self-configuration mechanism is completed, it is possible to order a product from a mobile communication device.

  13. Real-Time Hardware-in-the-Loop Simulation of Ares I Launch Vehicle

    Science.gov (United States)

    Tobbe, Patrick; Matras, Alex; Walker, David; Wilson, Heath; Fulton, Chris; Alday, Nathan; Betts, Kevin; Hughes, Ryan; Turbe, Michael

    2009-01-01

    The Ares Real-Time Environment for Modeling, Integration, and Simulation (ARTEMIS) has been developed for use by the Ares I launch vehicle System Integration Laboratory at the Marshall Space Flight Center. The primary purpose of the Ares System Integration Laboratory is to test the vehicle avionics hardware and software in a hardware - in-the-loop environment to certify that the integrated system is prepared for flight. ARTEMIS has been designed to be the real-time simulation backbone to stimulate all required Ares components for verification testing. ARTE_VIIS provides high -fidelity dynamics, actuator, and sensor models to simulate an accurate flight trajectory in order to ensure realistic test conditions. ARTEMIS has been designed to take advantage of the advances in underlying computational power now available to support hardware-in-the-loop testing to achieve real-time simulation with unprecedented model fidelity. A modular realtime design relying on a fully distributed computing architecture has been implemented.

  14. Stacked subwavelength gratings for imaging polarimetry

    Science.gov (United States)

    Deguzman, Panfilo Castro

    The stacking of subwavelength gratings (SWG) in an integrated structure is presented for an application in imaging polarimetry. Imaging polarimetry extends the capability of conventional imaging by providing polarization information about a scene, in addition to variations in intensity. In this dissertation, a novel approach is introduced to develop a real-time imaging polarimeter. Subwavelength gratings are implemented as linear and circular polarization filters that are directly mounted onto the focal plane array of an infrared (IR) camera. Wire grid polarizers are used as linear polarization filters. The stacked structure, consisting of a wire grid polarizer and a form birefringent quarter-wave plate (QWP), implements the circular polarization filter and is the focus of this dissertation. Initial investigations of the development of the individual SWG components and their integration are presented. Rigorous Coupled Wave Analysis (RCWA) was used to design the SWG structures. A broadband form birefringent quarter-wave plate for the 3.5 to 5 μm wavelength range was designed as a grating structure patterned directly into the substrate. Two fabrication methods for the wire grid polarizer were investigated. A 0.5 μm period polarizer was patterned by interference lithography. A 1 μm period polarizer was patterned by contact printing. The stacking of the subwavelength grating structures was analyzed using the Jones Matrix calculus and a new RCWA method (developed by fellow graduate student Jianhua Jiang). Stacked SWG's were fabricated as large area (1.3 cm x 1.3 cm) filters and as a 256 x 256 array of small aperture (15 μm x 15 μm) pixels. Two stack designs were investigated, referred to as Stack I and Stack II. Stack I consisted of the 0.5 μm period polarizer and the form birefringent QWP. Stack II consisted of the I μm grid period polarizer and the form birefringent QWP. Simulation and measured results are presented to compare the cases of samples with and

  15. A polymer electrolyte fuel cell stack for stationary power generation from hydrogen fuel

    Energy Technology Data Exchange (ETDEWEB)

    Gottesfeld, S. [Los Alamos National Lab., NM (United States)

    1995-09-01

    The fuel cell is the most efficient device for the conversion of hydrogen fuel to electric power. As such, the fuel cell represents a key element in efforts to demonstrate and implement hydrogen fuel utilization for electric power generation. The low temperature, polymer electrolyte membrane fuel cell (PEMFC) has recently been identified as an attractive option for stationary power generation, based on the relatively simple and benign materials employed, the zero-emission character of the device, and the expected high power density, high reliability and low cost. However, a PEMFC stack fueled by hydrogen with the combined properties of low cost, high performance and high reliability has not yet been demonstrated. Demonstration of such a stack will remove a significant barrier to implementation of this advanced technology for electric power generation from hydrogen. Work done in the past at LANL on the development of components and materials, particularly on advanced membrane/electrode assemblies (MEAs), has contributed significantly to the capability to demonstrate in the foreseeable future a PEMFC stack with the combined characteristics described above. A joint effort between LANL and an industrial stack manufacturer will result in the demonstration of such a fuel cell stack for stationary power generation. The stack could operate on hydrogen fuel derived from either natural gas or from renewable sources. The technical plan includes collaboration with a stack manufacturer (CRADA). It stresses the special requirements from a PEMFC in stationary power generation, particularly maximization of the energy conversion efficiency, extension of useful life to the 10 hours time scale and tolerance to impurities from the reforming of natural gas.

  16. A Comparative Study on Hardware Platforms for Wireless Sensor Networks

    Directory of Open Access Journals (Sweden)

    Thang Vu Chien

    2012-01-01

    Full Text Available Recently, Wireless Sensor Networks (WSNs attract a great deal of research attention, and are envisioned to support a variety of applications, including building monitoring, environment control, wild-life habitat monitoring, forest fire detection, industry automation, military, security, and health-care. Over the years, we have seen a variety of hardware platforms for WSNs to facilitate developing WSN applications. In this paper, we provide a comprehensive review of existing hardware platforms for WSNs. We first present the hardware architecture of a wireless sensor node. We then survey the major hardware platforms for WSNs and present a comparison of these hardware platforms. Finally we present some recommendations from the perspectives of hardware platform developers and hardware platform users. The authors hope that making information about existing hardware platforms will assist researchers working in this area to appreciate the diversity of platforms available to them and to help them select the most appropriate platform for their purposes.

  17. The Impact of Flight Hardware Scavenging on Space Logistics

    Science.gov (United States)

    Oeftering, Richard C.

    2011-01-01

    For a given fixed launch vehicle capacity the logistics payload delivered to the moon may be only roughly 20 percent of the payload delivered to the International Space Station (ISS). This is compounded by the much lower flight frequency to the moon and thus low availability of spares for maintenance. This implies that lunar hardware is much more scarce and more costly per kilogram than ISS and thus there is much more incentive to preserve hardware. The Constellation Lunar Surface System (LSS) program is considering ways of utilizing hardware scavenged from vehicles including the Altair lunar lander. In general, the hardware will have only had a matter of hours of operation yet there may be years of operational life remaining. By scavenging this hardware the program, in effect, is treating vehicle hardware as part of the payload. Flight hardware may provide logistics spares for system maintenance and reduce the overall logistics footprint. This hardware has a wide array of potential applications including expanding the power infrastructure, and exploiting in-situ resources. Scavenging can also be seen as a way of recovering the value of, literally, billions of dollars worth of hardware that would normally be discarded. Scavenging flight hardware adds operational complexity and steps must be taken to augment the crew s capability with robotics, capabilities embedded in flight hardware itself, and external processes. New embedded technologies are needed to make hardware more serviceable and scavengable. Process technologies are needed to extract hardware, evaluate hardware, reconfigure or repair hardware, and reintegrate it into new applications. This paper also illustrates how scavenging can be used to drive down the cost of the overall program by exploiting the intrinsic value of otherwise discarded flight hardware.

  18. Inner Loop Optimizations in Mapping Single Threaded Programs to Hardware

    OpenAIRE

    Desai, Madhav

    2014-01-01

    In the context of mapping high-level algorithms to hardware, we consider the basic problem of generating an efficient hardware implementation of a single threaded program, in particular, that of an inner loop. We describe a control-flow mechanism which provides dynamic loop-pipelining capability in hardware, so that multiple iterations of an arbitrary inner loop can be made simultaneously active in the generated hardware, We study the impact of this loop-pipelining scheme in conjunction with ...

  19. Computer hardware for radiologists: Part 2

    Directory of Open Access Journals (Sweden)

    Indrajit I

    2010-01-01

    Full Text Available Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU, chipset, random access memory (RAM, and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ′ever increasing′ digital future.

  20. Computer hardware for radiologists: Part 2

    International Nuclear Information System (INIS)

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. “Storage drive” is a term describing a “memory” hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. “Drive interfaces” connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular “input/output devices” used commonly with computers are the printer, monitor, mouse, and keyboard. The “bus” is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. “Ports” are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the ‘ever increasing’ digital future

  1. Computer hardware for radiologists: Part 2.

    Science.gov (United States)

    Indrajit, Ik; Alam, A

    2010-11-01

    Computers are an integral part of modern radiology equipment. In the first half of this two-part article, we dwelt upon some fundamental concepts regarding computer hardware, covering components like motherboard, central processing unit (CPU), chipset, random access memory (RAM), and memory modules. In this article, we describe the remaining computer hardware components that are of relevance to radiology. "Storage drive" is a term describing a "memory" hardware used to store data for later retrieval. Commonly used storage drives are hard drives, floppy drives, optical drives, flash drives, and network drives. The capacity of a hard drive is dependent on many factors, including the number of disk sides, number of tracks per side, number of sectors on each track, and the amount of data that can be stored in each sector. "Drive interfaces" connect hard drives and optical drives to a computer. The connections of such drives require both a power cable and a data cable. The four most popular "input/output devices" used commonly with computers are the printer, monitor, mouse, and keyboard. The "bus" is a built-in electronic signal pathway in the motherboard to permit efficient and uninterrupted data transfer. A motherboard can have several buses, including the system bus, the PCI express bus, the PCI bus, the AGP bus, and the (outdated) ISA bus. "Ports" are the location at which external devices are connected to a computer motherboard. All commonly used peripheral devices, such as printers, scanners, and portable drives, need ports. A working knowledge of computers is necessary for the radiologist if the workflow is to realize its full potential and, besides, this knowledge will prepare the radiologist for the coming innovations in the 'ever increasing' digital future. PMID:21423895

  2. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    Directory of Open Access Journals (Sweden)

    Wong Weng-Fai

    2011-01-01

    Full Text Available Abstract Advances in technology are making it possible to run three-dimensional (3D graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API, device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC accelerator using transaction-level modeling (TLM. This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  3. Internet-based hardware/software co-design framework for embedded 3D graphics applications

    Science.gov (United States)

    Yeh, Chi-Tsai; Wang, Chun-Hao; Huang, Ing-Jer; Wong, Weng-Fai

    2011-12-01

    Advances in technology are making it possible to run three-dimensional (3D) graphics applications on embedded and handheld devices. In this article, we propose a hardware/software co-design environment for 3D graphics application development that includes the 3D graphics software, OpenGL ES application programming interface (API), device driver, and 3D graphics hardware simulators. We developed a 3D graphics system-on-a-chip (SoC) accelerator using transaction-level modeling (TLM). This gives software designers early access to the hardware even before it is ready. On the other hand, hardware designers also stand to gain from the more complex test benches made available in the software for verification. A unique aspect of our framework is that it allows hardware and software designers from geographically dispersed areas to cooperate and work on the same framework. Designs can be entered and executed from anywhere in the world without full access to the entire framework, which may include proprietary components. This results in controlled and secure transparency and reproducibility, granting leveled access to users of various roles.

  4. Improving web server efficiency on commodity hardware

    OpenAIRE

    Beltrán Querol, Vicenç

    2008-01-01

    El ràpid creixement de la Web requereix una gran quantitat de recursos computacionals que han de ser utilitzats eficientment. Avui en dia, els servidors basats en hardware estendard son les plataformes preferides per executar els servidors web, ja que són les plataformes amb millor relació rendiment/cost. El treball presentat en aquesta tesi esta dirigit a millorar la eficàcia en la gestió de recursos dels servidors web actuals. Per assolir els objectius d'aquesta tesis s'ha caracteritzat e...

  5. INTEGRATED MONITORING HARDWARE DEVELOPMENTS AT LOS ALAMOS

    International Nuclear Information System (INIS)

    The hardware of the integrated monitoring system supports a family of instruments having a common internal architecture and firmware. Instruments can be easily configured from application-specific personality boards combined with common master-processor and high- and low-voltage power supply boards, and basic operating firmware. The instruments are designed to function autonomously to survive power and communication outages and to adapt to changing conditions. The personality boards allow measurement of gross gammas and neutrons, neutron coincidence and multiplicity, and gamma spectra. In addition, the Intelligent Local Node (ILON) provides a moderate-bandwidth network to tie together instruments, sensors, and computers

  6. Hardware Design of a Smart Meter

    Directory of Open Access Journals (Sweden)

    Ganiyu A. Ajenikoko

    2014-09-01

    Full Text Available Smart meters are electronic measurement devices used by utilities to communicate information for billing customers and operating their electric systems. This paper presents the hardware design of a smart meter. Sensing and circuit protection circuits are included in the design of the smart meter in which resistors are naturally a fundamental part of the electronic design. Smart meters provides a route for energy savings, real-time pricing, automated data collection and eliminating human errors due to manual readings which would ultimately reduce labour costs, diagnosis and instantaneous fault detection. This allows for predictive maintenance resulting in a more efficient and reliable distribution network.

  7. A building block for hardware belief networks.

    Science.gov (United States)

    Behin-Aein, Behtash; Diep, Vinh; Datta, Supriyo

    2016-01-01

    Belief networks represent a powerful approach to problems involving probabilistic inference, but much of the work in this area is software based utilizing standard deterministic hardware based on the transistor which provides the gain and directionality needed to interconnect billions of them into useful networks. This paper proposes a transistor like device that could provide an analogous building block for probabilistic networks. We present two proof-of-concept examples of belief networks, one reciprocal and one non-reciprocal, implemented using the proposed device which is simulated using experimentally benchmarked models. PMID:27443521

  8. Fast Gridding on Commodity Graphics Hardware

    DEFF Research Database (Denmark)

    Sørensen, Thomas Sangild; Schaeffter, Tobias; Noe, Karsten Østergaard;

    2007-01-01

    The most commonly used algorithm for non-cartesian MRI reconstruction is the gridding algorithm [1]. It consists of three steps:                    1) convolution with a gridding kernel and resampling on a cartesian grid, 2) inverse FFT, and 3) deapodization. On the CPU the convolution step is th...... implemented on graphics hardware giving a significant speedup compared to CPU based alternatives. We present a novel GPU implementation of the convolution step that overcomes the problems of memory bandwidth that has limited the speed of previous GPU gridding algorithms [2]....

  9. Exploiting Semiconductor Properties for Hardware Trojans

    CERN Document Server

    Shiyanovskii, Y; Papachristou, C; Weyer, D; Clay, W

    2009-01-01

    This paper discusses the possible introduction of hidden reliability defects during CMOS foundry fabrication processes that may lead to accelerated wearout of the devices. These hidden defects or hardware Trojans can be created by deviation from foundry design rules and processing parameters. The Trojans are produced by exploiting time-based wearing mechanisms (HCI, NBTI, TDDB and EM) and/or condition-based triggers (ESD, Latchup and Softerror). This class of latent damage is difficult to test due to its gradual degradation nature. The paper describes life-time expectancy results for various Trojan induced scenarios. Semiconductor properties, processing and design parameters critical for device reliability and Trojan creation are discussed.

  10. Management of cladding hulls and fuel hardware

    International Nuclear Information System (INIS)

    The reprocessing of spent fuel from power reactors based on chop-leach technology produces a solid waste product of cladding hulls and other metallic residues. This report describes the current situation in the management of fuel cladding hulls and hardware. Information is presented on the material composition of such waste together with the heating effects due to neutron-induced activation products and fuel contamination. As no country has established a final disposal route and the corresponding repository, this report also discusses possible disposal routes and various disposal options under consideration at present

  11. SuperCDMS Cold Hardware Design

    International Nuclear Information System (INIS)

    We discuss the current design of the cold hardware and cold electronics to be used in the upcoming SuperCDMS Soudan deployment. Engineering challenges associated with such concerns as thermal isolation, microphonics, radiopurity, and power dissipation are discussed, along with identifying the design changes necessary for SuperCDMS SNOLAB. The Cryogenic Dark Matter Search (CDMS) employs ultrapure 1-inch thick, 3-inch diameter germanium crystals operating below 50 mK in a dilution cryostat. These detectors give an ionization and phonon signal, which gives us rejection capabilities regarding background events versus dark matter signals.

  12. The Cryptographic Strength of Tamper-Proof Hardware

    OpenAIRE

    Nilges, Tobias

    2015-01-01

    Tamper-proof hardware has found its way into our everyday life in various forms, be it SIM cards, credit cards or passports. Usually, a cryptographic key is embedded in these hardware tokens that allows the execution of simple cryptographic operations, such as encryption or digital signing. The inherent security guarantees of tamper-proof hardware, however, allow more complex and diverse applications.

  13. A Short Historical Survey of Functional Hardware Languages

    OpenAIRE

    Gang Chen

    2012-01-01

    Functional programming languages offer a high degree of abstractions and clean semantics, which are desirable for hardware descriptions. This short historical survey is about functional languages specifically created for hardware design and verification. It also includes those hardware languages or formalisms which are strongly influenced by functional programming style.

  14. Safe to Fly: Certifying COTS Hardware for Spaceflight

    Science.gov (United States)

    Fichuk, Jessica L.

    2011-01-01

    Providing hardware for the astronauts to use on board the Space Shuttle or International Space Station (ISS) involves a certification process that entails evaluating hardware safety, weighing risks, providing mitigation, and verifying requirements. Upon completion of this certification process, the hardware is deemed safe to fly. This process from start to finish can be completed as quickly as 1 week or can take several years in length depending on the complexity of the hardware and whether the item is a unique custom design. One area of cost and schedule savings that NASA implements is buying Commercial Off the Shelf (COTS) hardware and certifying it for human spaceflight as safe to fly. By utilizing commercial hardware, NASA saves time not having to develop, design and build the hardware from scratch, as well as a timesaving in the certification process. By utilizing COTS hardware, the current detailed certification process can be simplified which results in schedule savings. Cost savings is another important benefit of flying COTS hardware. Procuring COTS hardware for space use can be more economical than custom building the hardware. This paper will investigate the cost savings associated with certifying COTS hardware to NASA s standards rather than performing a custom build.

  15. FPGA Acceleration by Dynamically-Loaded Hardware Libraries

    DEFF Research Database (Denmark)

    Lomuscio, Andrea; Nannarelli, Alberto; Re, Marco

    Hardware acceleration is a viable solution to obtain energy efficiency in data intensive computation. In this work, we present a hardware framework to dynamically load hardware libraries, HLL, on reconfigurable platforms (FPGAs). Provided a library of application-specific processors, we load on...

  16. PACE: A dynamic programming algorithm for hardware/software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    with a hardware area constraint and the problem of minimizing hardware area with a system execution time constraint. The target architecture consists of a single microprocessor and a single hardware chip (ASIC, FPGA, etc.) which are connected by a communication channel. The algorithm incorporates a realistic...

  17. Unifying Approach to Software and Hardware Design for Scientific Calculations

    OpenAIRE

    Litvinov, G. L.; Maslov, V. P.; Rodionov, A. Ya.

    1999-01-01

    A unifying approach to software and hardware design generated by ideas of Idempotent Mathematics is discussed. The so-called idempotent correspondence principle for algorithms, programs and hardware units is described. A software project based on this approach is presented. Key words: universal algorithms, idempotent calculus, software design, hardware design, object oriented programming

  18. Space Telecommunications Radio Systems (STRS) Hardware Architecture Standard: Release 1.0 Hardware Section

    Science.gov (United States)

    Reinhart, Richard C.; Kacpura, Thomas J.; Smith, Carl R.; Liebetreu, John; Hill, Gary; Mortensen, Dale J.; Andro, Monty; Scardelletti, Maximilian C.; Farrington, Allen

    2008-01-01

    This report defines a hardware architecture approach for software-defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general-purpose processors, digital signal processors, field programmable gate arrays, and application-specific integrated circuits (ASICs) in addition to flexible and tunable radiofrequency front ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and interfaces. The modules are a logical division of common radio functions that compose a typical communication radio. This report describes the architecture details, the module definitions, the typical functions on each module, and the module interfaces. Tradeoffs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify a physical implementation internally on each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  19. Fungal melanins differ in planar stacking distances.

    Directory of Open Access Journals (Sweden)

    Arturo Casadevall

    Full Text Available Melanins are notoriously difficult to study because they are amorphous, insoluble and often associated with other biological materials. Consequently, there is a dearth of structural techniques to study this enigmatic pigment. Current models of melanin structure envision the stacking of planar structures. X ray diffraction has historically been used to deduce stacking parameters. In this study we used X ray diffraction to analyze melanins derived from Cryptococcus neoformans, Aspergillus niger, Wangiella dermatitides and Coprinus comatus. Analysis of melanin in melanized C. neoformans encapsulated cells was precluded by the fortuitous finding that the capsular polysaccharide had a diffraction spectrum that was similar to that of isolated melanin. The capsular polysaccharide spectrum was dominated by a broad non-Bragg feature consistent with origin from a repeating structural motif that may arise from inter-molecular interactions and/or possibly gel organization. Hence, we isolated melanin from each fungal species and compared diffraction parameters. The results show that the inferred stacking distances of fungal melanins differ from that reported for synthetic melanin and neuromelanin, occupying intermediate position between these other melanins. These results suggest that all melanins have a fundamental diffracting unit composed of planar graphitic assemblies that can differ in stacking distance. The stacking peak appears to be a distinguishing universal feature of melanins that may be of use in characterizing these enigmatic pigments.

  20. Levitation characteristics of HTS tape stacks

    Energy Technology Data Exchange (ETDEWEB)

    Pokrovskiy, S. V.; Ermolaev, Y. S.; Rudnev, I. A. [National Research Nuclear University MEPhI (Moscow Engineering Physics Institute), Moscow (Russian Federation)

    2015-03-15

    Due to the considerable development of the technology of second generation high-temperature superconductors and a significant improvement in their mechanical and transport properties in the last few years it is possible to use HTS tapes in the magnetic levitation systems. The advantages of tapes on a metal substrate as compared with bulk YBCO material primarily in the strength, and the possibility of optimizing the convenience of manufacturing elements of levitation systems. In the present report presents the results of the magnetic levitation force measurements between the stack of HTS tapes containing of tapes and NdFeB permanent magnet in the FC and ZFC regimes. It was found a non- linear dependence of the levitation force from the height of the array of stack in both modes: linear growth at small thickness gives way to flattening and constant at large number of tapes in the stack. Established that the levitation force of stacks comparable to that of bulk samples. The numerical calculations using finite element method showed that without the screening of the applied field the levitation force of the bulk superconductor and the layered superconductor stack with a critical current of tapes increased by the filling factor is exactly the same, and taking into account the screening force slightly different.

  1. A Late Pleistocene sea level stack

    Directory of Open Access Journals (Sweden)

    R. M. Spratt

    2015-08-01

    Full Text Available Late Pleistocene sea level has been reconstructed from ocean sediment core data using a wide variety of proxies and models. However, the accuracy of individual reconstructions is limited by measurement error, local variations in salinity and temperature, and assumptions particular to each technique. Here we present a sea level stack (average which increases the signal-to-noise ratio of individual reconstructions. Specifically, we perform principal component analysis (PCA on seven records from 0–430 ka and five records from 0–798 ka. The first principal component, which we use as the stack, describes ~80 % of the variance in the data and is similar using either five or seven records. After scaling the stack based on Holocene and Last Glacial Maximum (LGM sea level estimates, the stack agrees to within 5 m with isostatically adjusted coral sea level estimates for Marine Isotope Stages 5e and 11 (125 and 400 ka, respectively. When we compare the sea level stack with the δ18O of benthic foraminifera, we find that sea level change accounts for about ~40 % of the total orbital-band variance in benthic δ18O, compared to a 65 % contribution during the LGM-to-Holocene transition. Additionally, the second and third principal components of our analyses reflect differences between proxy records associated with spatial variations in the δ18O of seawater.

  2. 硬件协议栈芯片W3100A%Hardware Protocol Stack Chip W3100A

    Institute of Scientific and Technical Information of China (English)

    谢冲; 梅大成

    2005-01-01

    W3100是WIZnet公司专门为以太网互联和嵌入式设备推出的硬件TCP/IP协议栈芯片,其硬件TCP/IP协议栈包含了TCP、UDP、IP、ARP和ICMP协议.文中介绍了W3100A的主要特点、引脚功能和基本结构,分析了W3100的软硬件设计应用方法.

  3. ISS Logistics Hardware Disposition and Metrics Validation

    Science.gov (United States)

    Rogers, Toneka R.

    2010-01-01

    I was assigned to the Logistics Division of the International Space Station (ISS)/Spacecraft Processing Directorate. The Division consists of eight NASA engineers and specialists that oversee the logistics portion of the Checkout, Assembly, and Payload Processing Services (CAPPS) contract. Boeing, their sub-contractors and the Boeing Prime contract out of Johnson Space Center, provide the Integrated Logistics Support for the ISS activities at Kennedy Space Center. Essentially they ensure that spares are available to support flight hardware processing and the associated ground support equipment (GSE). Boeing maintains a Depot for electrical, mechanical and structural modifications and/or repair capability as required. My assigned task was to learn project management techniques utilized by NASA and its' contractors to provide an efficient and effective logistics support infrastructure to the ISS program. Within the Space Station Processing Facility (SSPF) I was exposed to Logistics support components, such as, the NASA Spacecraft Services Depot (NSSD) capabilities, Mission Processing tools, techniques and Warehouse support issues, required for integrating Space Station elements at the Kennedy Space Center. I also supported the identification of near-term ISS Hardware and Ground Support Equipment (GSE) candidates for excessing/disposition prior to October 2010; and the validation of several Logistics Metrics used by the contractor to measure logistics support effectiveness.

  4. Introduction to Hardware Security and Trust

    CERN Document Server

    Wang, Cliff

    2012-01-01

    The emergence of a globalized, horizontal semiconductor business model raises a set of concerns involving the security and trust of the information systems on which modern society is increasingly reliant for mission-critical functionality. Hardware-oriented security and trust issues span a broad range including threats related to the malicious insertion of Trojan circuits designed, e.g.,to act as a ‘kill switch’ to disable a chip, to integrated circuit (IC) piracy,and to attacks designed to extract encryption keys and IP from a chip. This book provides the foundations for understanding hardware security and trust, which have become major concerns for national security over the past decade.  Coverage includes security and trust issues in all types of electronic devices and systems such as ASICs, COTS, FPGAs, microprocessors/DSPs, and embedded systems.  This serves as an invaluable reference to the state-of-the-art research that is of critical significance to the security of,and trust in, modern society�...

  5. ARM assembly language with hardware experiments

    CERN Document Server

    Elahi, Ata

    2015-01-01

    This book provides a hands-on approach to learning ARM assembly language with the use of a TI microcontroller. The book starts with an introduction to computer architecture and then discusses number systems and digital logic. The text covers ARM Assembly Language, ARM Cortex Architecture and its components, and Hardware Experiments using TILM3S1968. Written for those interested in learning embedded programming using an ARM Microcontroller. ·         Introduces number systems and signal transmission methods   ·         Reviews logic gates, registers, multiplexers, decoders and memory   ·         Provides an overview and examples of ARM instruction set   ·         Uses using Keil development tools for writing and debugging ARM assembly language Programs   ·         Hardware experiments using a Mbed NXP LPC1768 microcontroller; including General Purpose Input/Output (GPIO) configuration, real time clock configuration, binary input to 7-segment display, creating ...

  6. Optimizing imaging hardware for estimation tasks

    Science.gov (United States)

    Kupinski, Matthew A.; Clarkson, Eric; Gross, Kevin; Hoppin, John W.

    2003-05-01

    Medical imaging is often performed for the purpose of estimating a clinically relevant parameter. For example, cardiologists are interested in the cardiac ejection fraction, the fraction of blood pumped out of the left ventricle at the end of each heart cycle. Even when the primary task of the imaging system is tumor detection, physicians frequently want to estimate parameters of the tumor, e.g. size and location. For signal-detection tasks, we advocate that the performance of an ideal observer be employed as the figure of merit for optimizing medical imaging hardware. We have examined the use of the minimum variance of the ideal, unbiased estimator as a figure of merit for hardware optimization. The minimum variance of the ideal, unbiased estimator can be calculated using the Fisher information matrix. To account for both image noise and object variability, we used a statistical method known as Markov-chain Monte Carlo. We employed a lumpy object model and simulated imaging systems to compute our figures of merit. We have demonstrated the use of this method in comparing imaging systems for estimation tasks.

  7. Hardware development process for Human Research facility applications

    Science.gov (United States)

    Bauer, Liz

    2000-01-01

    The simple goal of the Human Research Facility (HRF) is to conduct human research experiments on the International Space Station (ISS) astronauts during long-duration missions. This is accomplished by providing integration and operation of the necessary hardware and software capabilities. A typical hardware development flow consists of five stages: functional inputs and requirements definition, market research, design life cycle through hardware delivery, crew training, and mission support. The purpose of this presentation is to guide the audience through the early hardware development process: requirement definition through selecting a development path. Specific HRF equipment is used to illustrate the hardware development paths. .

  8. Hardware-Software Co-Simulation for SOC Functional Verification

    Institute of Scientific and Technical Information of China (English)

    YAN Ying-jian; LIU Ming-ye

    2005-01-01

    A hardware-software co-simulation method for system on chip (SOC) design is discussed. It is based on an instruction set simulator (ISS) and an event-driven hardware simulator, and a bus interface model that is described in C language provides the interface between the two. The bus interface model and the ISS are linked into a singleton program the software simulator, which communicate with the hardware simulator through Windows sockets. The implementation of the bus interface model and the synchronization between hardware and software simulator are discussed in detail. Co-simulation control of the hardware simulator is also discussed.

  9. Advanced Plant Habitat (APH)

    Science.gov (United States)

    Richards, Stephanie E. (Compiler); Levine, Howard G.; Reed, David W.

    2016-01-01

    The Advanced Plant Habitat (APH) hardware will be a large growth volume plant habitat, capable of hosting multigenerational studies, in which environmental variables (e.g., temperature, relative humidity, carbon dioxide level light intensity and spectral quality) can be tracked and controlled in support of whole plant physiological testing and Bio-regenerative Life Support System investigations.

  10. Simple model of stacking-fault energies

    DEFF Research Database (Denmark)

    Stokbro, Kurt; Jacobsen, Lærke Wedel

    1993-01-01

    -density calculations of stacking-fault energies, and gives a simple way of understanding the calculated energy contributions from the different atomic layers in the stacking-fault region. The two parameters in the model describe the relative energy contributions of the s and d electrons in the noble and transition......A simple model for the energetics of stacking faults in fcc metals is constructed. The model contains third-nearest-neighbor pairwise interactions and a term involving the fourth moment of the electronic density of states. The model is in excellent agreement with recently published local...... metals, and thereby explain the pronounced differences in energetics in these two classes of metals. The model is discussed in the framework of the effective-medium theory where it is possible to find a functional form for the pair potential and relate the contribution associated with the fourth moment...

  11. Accelerating epistasis analysis in human genetics with consumer graphics hardware

    Directory of Open Access Journals (Sweden)

    Cancare Fabio

    2009-07-01

    Full Text Available Abstract Background Human geneticists are now capable of measuring more than one million DNA sequence variations from across the human genome. The new challenge is to develop computationally feasible methods capable of analyzing these data for associations with common human disease, particularly in the context of epistasis. Epistasis describes the situation where multiple genes interact in a complex non-linear manner to determine an individual's disease risk and is thought to be ubiquitous for common diseases. Multifactor Dimensionality Reduction (MDR is an algorithm capable of detecting epistasis. An exhaustive analysis with MDR is often computationally expensive, particularly for high order interactions. This challenge has previously been met with parallel computation and expensive hardware. The option we examine here exploits commodity hardware designed for computer graphics. In modern computers Graphics Processing Units (GPUs have more memory bandwidth and computational capability than Central Processing Units (CPUs and are well suited to this problem. Advances in the video game industry have led to an economy of scale creating a situation where these powerful components are readily available at very low cost. Here we implement and evaluate the performance of the MDR algorithm on GPUs. Of primary interest are the time required for an epistasis analysis and the price to performance ratio of available solutions. Findings We found that using MDR on GPUs consistently increased performance per machine over both a feature rich Java software package and a C++ cluster implementation. The performance of a GPU workstation running a GPU implementation reduces computation time by a factor of 160 compared to an 8-core workstation running the Java implementation on CPUs. This GPU workstation performs similarly to 150 cores running an optimized C++ implementation on a Beowulf cluster. Furthermore this GPU system provides extremely cost effective

  12. Movable Ground Based Recovery System for Reuseable Space Flight Hardware

    Science.gov (United States)

    Sarver, George L. (Inventor)

    2013-01-01

    A reusable space flight launch system is configured to eliminate complex descent and landing systems from the space flight hardware and move them to maneuverable ground based systems. Precision landing of the reusable space flight hardware is enabled using a simple, light weight aerodynamic device on board the flight hardware such as a parachute, and one or more translating ground based vehicles such as a hovercraft that include active speed, orientation and directional control. The ground based vehicle maneuvers itself into position beneath the descending flight hardware, matching its speed and direction and captures the flight hardware. The ground based vehicle will contain propulsion, command and GN&C functionality as well as space flight hardware landing cushioning and retaining hardware. The ground based vehicle propulsion system enables longitudinal and transverse maneuverability independent of its physical heading.

  13. Three wafer stacking for 3D integration.

    Energy Technology Data Exchange (ETDEWEB)

    Greth, K. Douglas; Ford, Christine L.; Lantz, Jeffrey W.; Shinde, Subhash L.; Timon, Robert P.; Bauer, Todd M.; Hetherington, Dale Laird; Sanchez, Carlos Anthony

    2011-11-01

    Vertical wafer stacking will enable a wide variety of new system architectures by enabling the integration of dissimilar technologies in one small form factor package. With this LDRD, we explored the combination of processes and integration techniques required to achieve stacking of three or more layers. The specific topics that we investigated include design and layout of a reticle set for use as a process development vehicle, through silicon via formation, bonding media, wafer thinning, dielectric deposition for via isolation on the wafer backside, and pad formation.

  14. Geometry and kinematics of experimental antiformal stacks

    Directory of Open Access Journals (Sweden)

    CAROLINE JANETTE SOUZA GOMES

    2000-06-01

    Full Text Available Sandbox experiments with different boundary conditions demonstrate that antiformal stacks result from a forward-breaking thrust sequence. An obstacle blocks forward thrust propagation and transfers the deformation back to the hinterland in a previously formed true duplex. In the hinterland, continued shortening causes faults to merge toward the tectonic transport direction until the older thrusts override the younger thrusts. In experiments using thin sand layers or high basal friction, shortening is accommodated by a cyclic process of thrusting, back rotation of the newly formed thrust combined with strong vertical strain, and nucleation of a new thrust. Continuous deformation produces an antiformal stack through progressive convergence of branch lines.

  15. Protein similarity search with subset seeds on a dedicated reconfigurable hardware

    OpenAIRE

    Peterlongo, Pierre; Noé, Laurent; Lavenier, Dominique; Georges, Gilles; Jacques, Julien; Kucherov, Gregory; Giraud, Mathieu

    2007-01-01

    Genome sequencing of numerous species raises the need of complete genome comparison with precise and fast similarity searches. Today, advanced seed-based techniques (spaced seeds, multiple seeds, subset seeds) provide better sensitivity/specificity ratios. We present an implementation of such a seed-based technique onto parallel specialized hardware embedding reconfigurable architecture (FPGA), where the FPGA is tightly connected to large capacity Flash memories. This parallel system allows l...

  16. Stacking of SKA data: comparing uv-plane and image-plane stacking

    CERN Document Server

    Knudsen, K K; Vlemmings, W; Conway, J; Marti-Vidal, I

    2015-01-01

    Stacking as a tool for studying objects that are not individually detected is becoming popular even for radio interferometric data, and will be widely used in the SKA era. Stacking is typically done using imaged data rather than directly using the visibilities (the uv-data). We have investigated and developed a novel algorithm to do stacking using the uv-data. We have performed exten- sive simulations comparing to image-stacking, and summarize the results of these simulations. Furthermore, we disuss the implications in light of the vast data volume produced by the SKA. Having access to the uv-stacked data provides a great advantage, as it allows the possibility to properly analyse the result with respect to calibration artifacts as well as source properties such as size. For SKA the main challenge lies in archiving the uv-data. For purposes of robust stacking analysis, it would be strongly desirable to either keep the calibrated uv-data at least in an aver- age form, or implement a stacking queue where stacki...

  17. When is Stacking Confusing?: The Impact of Confusion on Stacking in Deep HI Galaxy Surveys

    CERN Document Server

    Jones, Michael G; Giovanelli, Riccardo; Papastergis, Emmanouil

    2015-01-01

    We present an analytic model to predict the HI mass contributed by confused sources to a stacked spectrum in a generic HI survey. Based on the ALFALFA correlation function, this model is in agreement with the estimates of confusion present in stacked Parkes telescope data, and was used to predict how confusion will limit stacking in the deepest SKA-precursor HI surveys. Stacking with LADUMA and DINGO UDEEP data will only be mildly impacted by confusion if their target synthesised beam size of 10 arcsec can be achieved. Any beam size significantly above this will result in stacks that contain a mass in confused sources that is comparable to (or greater than) that which is detectable via stacking, at all redshifts. CHILES' 5 arcsec resolution is more than adequate to prevent confusion influencing stacking of its data, throughout its bandpass range. FAST will be the most impeded by confusion, with HI surveys likely becoming heavily confused much beyond z = 0.1. The largest uncertainties in our model are the reds...

  18. Locating hardware faults in a parallel computer

    Science.gov (United States)

    Archer, Charles J.; Megerian, Mark G.; Ratterman, Joseph D.; Smith, Brian E.

    2010-04-13

    Locating hardware faults in a parallel computer, including defining within a tree network of the parallel computer two or more sets of non-overlapping test levels of compute nodes of the network that together include all the data communications links of the network, each non-overlapping test level comprising two or more adjacent tiers of the tree; defining test cells within each non-overlapping test level, each test cell comprising a subtree of the tree including a subtree root compute node and all descendant compute nodes of the subtree root compute node within a non-overlapping test level; performing, separately on each set of non-overlapping test levels, an uplink test on all test cells in a set of non-overlapping test levels; and performing, separately from the uplink tests and separately on each set of non-overlapping test levels, a downlink test on all test cells in a set of non-overlapping test levels.

  19. Current conveyors variants, applications and hardware implementations

    CERN Document Server

    Senani, Raj; Singh, A K

    2015-01-01

    This book serves as a single-source reference to Current Conveyors and their use in modern Analog Circuit Design. The authors describe the various types of current conveyors discovered over the past 45 years, details of all currently available, off-the-shelf integrated circuit current conveyors, and implementations of current conveyors using other, off-the-shelf IC building blocks. Coverage includes prominent bipolar/CMOS/Bi-CMOS architectures of current conveyors, as well as all varieties of starting from third generation current conveyors to universal current conveyors, their implementations and applications. •Describes all commercially available off-the-shelf IC current conveyors, as well as hardware implementations of current conveyors using other off-the-shelf ICs; • Describes numerous variants of current conveyors evolved over the past forty five years; • Describes a number of Bipolar/CMOS/Bi-CMOS architectures of current conveyors, along with their characteristic features; • Includes a comprehe...

  20. Rendering Falling Leaves on Graphics Hardware

    Directory of Open Access Journals (Sweden)

    Marcos Balsa

    2008-04-01

    Full Text Available There is a growing interest in simulating natural phenomena in computer graphics applications. Animating natural scenes in real time is one of the most challenging problems due to the inherent complexity of their structure, formed by millions of geometric entities, and the interactions that happen within. An example of natural scenario that is needed for games or simulation programs are forests. Forests are difficult to render because the huge amount of geometric entities and the large amount of detail to be represented. Moreover, the interactions between the objects (grass, leaves and external forces such as wind are complex to model. In this paper we concentrate in the rendering of falling leaves at low cost. We present a technique that exploits graphics hardware in order to render thousands of leaves with different falling paths in real time and low memory requirements.

  1. Protection of Accelerator Hardware: RF systems

    CERN Document Server

    Kim, S-H

    2016-01-01

    The radio-frequency (RF) system is the key element that generates electric fields for beam acceleration. To keep the system reliable, a highly sophisticated protection scheme is required, which also should be designed to ensure a good balance between beam availability and machine safety. Since RF systems are complex, incorporating high-voltage and high-power equipment, a good portion of machine downtime typically comes from RF systems. Equipment and component damage in RF systems results in long and expensive repairs. Protection of RF system hardware is one of the oldest machine protection concepts, dealing with the protection of individual high-power RF equipment from breakdowns. As beam power increases in modern accelerators, the protection of accelerating structures from beam-induced faults also becomes a critical aspect of protection schemes. In this article, an overview of the RF system is given, and selected topics of failure mechanisms and examples of protection requirements are introduced.

  2. EPICS: Allen-Bradley hardware reference manual

    International Nuclear Information System (INIS)

    This manual covers the following hardware: Allen-Bradley 6008 -- SV VMEbus I/O scanner; Allen-Bradley universal I/O chassis 1771-A1B, -A2B, -A3B, and -A4B; Allen-Bradley power supply module 1771-P4S; Allen-Bradley 1771-ASB remote I/O adapter module; Allen-Bradley 1771-IFE analog input module; Allen-Bradley 1771-OFE analog output module; Allen-Bradley 1771-IG(D) TTL input module; Allen-Bradley 1771-OG(d) TTL output; Allen-Bradley 1771-IQ DC selectable input module; Allen-Bradley 1771-OW contact output module; Allen-Bradley 1771-IBD DC (10--30V) input module; Allen-Bradley 1771-OBD DC (10--60V) output module; Allen-Bradley 1771-IXE thermocouple/millivolt input module; and the Allen-Bradley 2705 RediPANEL push button module

  3. Fast and dynamic generation of linear octrees for geological bodies under hardware acceleration

    Institute of Scientific and Technical Information of China (English)

    2010-01-01

    In the application of 3D Geoscience Modeling,we often need to generate the volumetric representations of geological bodies from their surface representations.Linear octree,as an efficient and easily operated volumetric model,is widely used in 3D Geoscience Modeling.This paper proposes an algorithm for fast and dynamic generation of linear octrees of geological bodies from their surface models under hardware acceleration.The Z-buffers are used to determine the attributes of octants and voxels in a fast way,and a divide-and-conquer strategy is adopted.A stack structure is exploited to record the subdivision,which allows generating linear octrees dynamically.The algorithm avoids large-scale sorting process and bypasses the compression in linear octrees generation.Experimental results indicate its high efficiency in generating linear octrees for large-scale geologic bodies.

  4. Measuring Structural Parameters Through Stacking Galaxy Images

    CERN Document Server

    Li, Yubin; Gu, Qiu-Sheng; Wang, Yi-Peng; Wen, ZhangZheng; Guo, Kexin; An, FangXia

    2016-01-01

    It remains challenging to detect the low surface brightness structures of faint high-z galaxies, which is key to understanding the structural evolution of galaxies. The technique of image stacking allows us to measure the averaged light profile beneath the detection limit and probe the extended structure of a group of galaxies. We carry out simulations to examine the recovery of the averaged surface brightness profile through stacking model HST/ACS images of a set of galaxies as functions of Sersic index (n), effective radius (Re) and axis ratio (AR). The Sersic profile best fitting the radial profile of the stacked image is taken as the recovered profile, in comparison with the intrinsic mean profile of the model galaxies. Our results show that, in general, the structural parameters of the mean profile can be properly determined through stacking, although systematic biases need to be corrected when spreads of Re and AR are counted. We find that Sersic index is slightly overestimated and Re is underestimated ...

  5. Scaling the CERN OpenStack cloud

    Science.gov (United States)

    Bell, T.; Bompastor, B.; Bukowiec, S.; Castro Leon, J.; Denis, M. K.; van Eldik, J.; Fermin Lobo, M.; Fernandez Alvarez, L.; Fernandez Rodriguez, D.; Marino, A.; Moreira, B.; Noel, B.; Oulevey, T.; Takase, W.; Wiebalck, A.; Zilli, S.

    2015-12-01

    CERN has been running a production OpenStack cloud since July 2013 to support physics computing and infrastructure services for the site. In the past year, CERN Cloud Infrastructure has seen a constant increase in nodes, virtual machines, users and projects. This paper will present what has been done in order to make the CERN cloud infrastructure scale out.

  6. OpenStack Object Storage (Swift) essentials

    CERN Document Server

    Kapadia, Amar; Varma, Sreedhar

    2015-01-01

    If you are an IT administrator and you want to enter the world of cloud storage using OpenStack Swift, then this book is ideal for you. Basic knowledge of Linux and server technology is beneficial to get the most out of the book.

  7. Average Transmission Probability of a Random Stack

    Science.gov (United States)

    Lu, Yin; Miniatura, Christian; Englert, Berthold-Georg

    2010-01-01

    The transmission through a stack of identical slabs that are separated by gaps with random widths is usually treated by calculating the average of the logarithm of the transmission probability. We show how to calculate the average of the transmission probability itself with the aid of a recurrence relation and derive analytical upper and lower…

  8. Photoswitchable Intramolecular H-Stacking of Perylenebisimide

    NARCIS (Netherlands)

    Wang, Jiaobing; Kulago, Artem; Browne, Wesley R.; Feringa, Ben L.

    2010-01-01

    Dynamic control over the formation of H- or J-type aggregates of chromophores is of fundamental importance for developing responsive organic optoelectronic materials. In this study, the first example of photoswitching between a nonstacked and an intramolecularly H-stacked arrangement of perylenebisi

  9. SRS reactor stack plume marking tests

    Energy Technology Data Exchange (ETDEWEB)

    Petry, S.F.

    1992-03-01

    Tests performed in 105-K in 1987 and 1988 demonstrated that the stack plume can successfully be made visible (i.e., marked) by introducing smoke into the stack breech. The ultimate objective of these tests is to provide a means during an emergency evacuation so that an evacuee can readily identify the stack plume and evacuate in the opposite direction, thus minimizing the potential of severe radiation exposure. The EPA has also requested DOE to arrange for more tests to settle a technical question involving the correct calculation of stack downwash. New test canisters were received in 1988 designed to produce more smoke per unit time; however, these canisters have not been evaluated, because normal ventilation conditions have not been reestablished in K Area. Meanwhile, both the authorization and procedure to conduct the tests have expired. The tests can be performed during normal reactor operation. It is recommended that appropriate authorization and procedure approval be obtained to resume testing after K Area restart.

  10. OpenStack cloud computing cookbook

    CERN Document Server

    Jackson, Kevin

    2013-01-01

    A Cookbook full of practical and applicable recipes that will enable you to use the full capabilities of OpenStack like never before.This book is aimed at system administrators and technical architects moving from a virtualized environment to cloud environments with familiarity of cloud computing platforms. Knowledge of virtualization and managing linux environments is expected.

  11. Proximal migration of hardware in patients undergoing midcarpal fusion with headless compression screws.

    Science.gov (United States)

    Shifflett, Grant D; Athanasian, Edward A; Lee, Steve K; Weiland, Andrew J; Wolfe, Scott W

    2014-11-01

    Background Scaphoid excision and limited intercarpal fusion is a common surgical procedure performed for degenerative disorders of the wrist including scapholunate advanced collapse (SLAC) and scaphoid nonunion advanced collapse (SNAC) wrist deformities. Postoperative screw migration is a rare but devastating complication that can result in severe degenerative changes in the radiocarpal joint. Questions/Purposes The purpose of this study is to report on a series of patients who developed proximal migration of their hardware following limited intercarpal fusions with headless compression screws. Patients and Methods Four patients were identified between 2001 and 2012 who were indicated for and underwent scaphoid excision and midcarpal fusions with headless compression screw fixation and subsequently developed hardware migration with screw protrusion into the radiocarpal joint. Detailed chart review was performed. Results Mean age at surgery was 64 years (57-69 years). All patients had the diagnosis of SLAC wrist. Mean time to detection of failure was 6 months (4-8 months). All patients demonstrated radiographic union prior to failure based on plain films. Radiographs revealed screw backout with erosion of the radial lunate facet in all patients. Calculated carpal height ratios demonstrated a drop from an average 44.2% to 39.5% at the time of hardware migration. All four patients underwent hardware removal. One patient was not indicated for any further surgery, and two patients underwent further revision surgery. All three patients reported complete pain relief. One patient refused a salvage procedure and had subsequent persistent pain. Conclusions This study reports a serious complication of scaphoid excision and midcarpal fusion performed with headless compression screws. We advise surgeons to be aware of this potential complication and consider employing methods to reduce the risk of hardware migration. Additionally, we recommend at least 8 months of

  12. Measurement of heat conduction through stacked screens.

    Science.gov (United States)

    Lewis, M A; Kuriyama, T; Kuriyama, F; Radebaugh, R

    1998-01-01

    This paper describes the experimental apparatus for the measurement of heat conduction through stacked screens as well as some experimental results taken with the apparatus. Screens are stacked in a fiberglass-epoxy cylinder, which is 24.4 mm in diameter and 55 mm in length. The cold end of the stacked screens is cooled by a Gifford-McMahon (GM) cryocooler at cryogenic temperature, and the hot end is maintained at room temperature. Heat conduction through the screens is determined from the temperature gradient in a calibrated heat flow sensor mounted between the cold end of the stacked screens and the GM cryocooler. The samples used for these experiments consisted of 400-mesh stainless steel screens, 400-mesh phosphor bronze screens, and two different porosities of 325-mesh stainless steel screens. The wire diameter of the 400-mesh stainless steel and phosphor bronze screens was 25.4 micrometers and the 325-mesh stainless steel screen wire diameters were 22.9 micrometers and 27.9 micrometers. Standard porosity values were used for the experimental data with additional porosity values used on selected experiments. The experimental results showed that the helium gas between each screen enhanced the heat conduction through the stacked screens by several orders of magnitude compared to that in vacuum. The conduction degradation factor is the ratio of actual heat conduction to the heat conduction where the regenerator material is assumed to be a solid rod of the same cross sectional area as the metal fraction of the screen. This factor was about 0.1 for the stainless steel and 0.022 for the phosphor bronze, and almost constant for the temperature range of 40 to 80 K at the cold end.

  13. Expert System analysis of non-fuel assembly hardware and spent fuel disassembly hardware: Its generation and recommended disposal

    International Nuclear Information System (INIS)

    Almost all of the effort being expended on radioactive waste disposal in the United States is being focused on the disposal of spent Nuclear Fuel, with little consideration for other areas that will have to be disposed of in the same facilities. one area of radioactive waste that has not been addressed adequately because it is considered a secondary part of the waste issue is the disposal of the various Non-Fuel Bearing Components of the reactor core. These hardware components fall somewhat arbitrarily into two categories: Non-Fuel Assembly (NFA) hardware and Spent Fuel Disassembly (SFD) hardware. This work provides a detailed examination of the generation and disposal of NFA hardware and SFD hardware by the nuclear utilities of the United States as it relates to the Civilian Radioactive Waste Management Program. All available sources of data on NFA and SFD hardware are analyzed with particular emphasis given to the Characteristics Data Base developed by Oak Ridge National Laboratory and the characterization work performed by Pacific Northwest Laboratories and Rochester Gas ampersand Electric. An Expert System developed as a portion of this work is used to assist in the prediction of quantities of NFA hardware and SFD hardware that will be generated by the United States' utilities. Finally, the hardware waste management practices of the United Kingdom, France, Germany, Sweden, and Japan are studied for possible application to the disposal of domestic hardware wastes. As a result of this work, a general classification scheme for NFA and SFD hardware was developed. Only NFA and SFD hardware constructed of zircaloy and experiencing a burnup of less than 70,000 MWD/MTIHM and PWR control rods constructed of stainless steel are considered Low-Level Waste. All other hardware is classified as Greater-ThanClass-C waste

  14. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    Science.gov (United States)

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  15. Resource Optimized Stereo Matching in Reconfigurable Hardware for Autonomous Systems

    OpenAIRE

    Ekstrand, Fredrik

    2011-01-01

    There is a need for compact, high-speed, and low-power vision systems for enabling real-time mobile autonomous applications. The best approach to achieve this is to implement the bulk of the application in hardware. Reconfigurable hardware meet these requirements without the limitation of fixed functionality that accompanies application-specific circuits. Resource constraints of reconfigurable hardware calls for optimized implementations i terms of resource usage with maintained performance. ...

  16. Exercise Countermeasure Hardware Evolution on ISS: The First Decade.

    Science.gov (United States)

    Korth, Deborah W

    2015-12-01

    The hardware systems necessary to support exercise countermeasures to the deconditioning associated with microgravity exposure have evolved and improved significantly during the first decade of the International Space Station (ISS), resulting in both new types of hardware and enhanced performance capabilities for initial hardware items. The original suite of countermeasure hardware supported the first crews to arrive on the ISS and the improved countermeasure system delivered in later missions continues to serve the astronauts today with increased efficacy. Due to aggressive hardware development schedules and constrained budgets, the initial approach was to identify existing spaceflight-certified exercise countermeasure equipment, when available, and modify it for use on the ISS. Program management encouraged the use of commercial-off-the-shelf (COTS) hardware, or hardware previously developed (heritage hardware) for the Space Shuttle Program. However, in many cases the resultant hardware did not meet the additional requirements necessary to support crew health maintenance during long-duration missions (3 to 12 mo) and anticipated future utilization activities in support of biomedical research. Hardware development was further complicated by performance requirements that were not fully defined at the outset and tended to evolve over the course of design and fabrication. Modifications, ranging from simple to extensive, were necessary to meet these evolving requirements in each case where heritage hardware was proposed. Heritage hardware was anticipated to be inherently reliable without the need for extensive ground testing, due to its prior positive history during operational spaceflight utilization. As a result, developmental budgets were typically insufficient and schedules were too constrained to permit long-term evaluation of dedicated ground-test units ("fleet leader" type testing) to identify reliability issues when applied to long-duration use. In most cases

  17. Downlink MIMO HCNs with Residual Transceiver Hardware Impairments

    OpenAIRE

    Papazafeiropoulos, Anastasios; Ratnarajah, Tharm

    2016-01-01

    A major limitation of heterogeneous cellular networks (HCNs) is the neglect of the additive residual transceiver hardware impairments (ARTHIs). The assumption of perfect hardware is quite strong and results in misleading conclusions. This paper models a general multiple-input multiple-output (MIMO) HCN with cell association by incorporating the RTHIs. We derive the coverage probability and shed light on the impact of the ARTHIs, when various transmission methods are applied. As the hardware q...

  18. GSTAMIDS ground-penetrating radar: hardware description

    Science.gov (United States)

    Sower, Gary D.; Eberly, John; Christy, Ed

    2001-10-01

    The Ground Standoff Mine Detection System (GSTAMIDS) is now in the Engineering, Manufacturing and Development (EMD) Block 0 phase for USA CECOM. The Mine Detection Subsystem (MDS) presently utilizes three different sensor technologies to detect buried anti-tank (AT) land mines; Ground Penetrating Radar (GPR), Pulsed Magnetic Induction (PMI), and passive infrared (IR). The GSTAMIDS hardware and software architectures are designed so that other technologies can readily be incorporated when and if they prove viable. Each sensor suite is designed to detect the buried mines and to discriminate against various clutter and background objects. Sensor data fusion of the outputs of the individual sensor suites then enhances the detection probability while reducing the false alarm rate from clutter objects. The metal detector is an essential tool for buried mine detection, as metal land mines still account for a large percentage of land mines. Technologies such as nuclear quadrupole resonance (NQR or QR) are presently being developed to detect or confirm the presence of explosive material in buried land mines, particularly the so-called plastic mines; unfortunately, the radio frequency signals required cannot penetrate into a metal land mine. The limitation of the metal detector is not in detection of the metal mines, but in the additional detection of metal clutter. A metal detector has been developed using singular value decomposition (SVD) extraction techniques to discriminate the mines from the clutter, thereby greatly reducing false alarm rates. This mine detector is designed to characterize the impulse response function of the metal objects, based on a parametric three-pole model of the response, and to use pattern recognition to determine the match of the responses to known mines. In addition to discrimination against clutter, the system can also generally tell one mine type from another. This paper describes the PMI sensor suite hardware and its physical incorporation

  19. Reliable software for unreliable hardware a cross layer perspective

    CERN Document Server

    Rehman, Semeen; Henkel, Jörg

    2016-01-01

    This book describes novel software concepts to increase reliability under user-defined constraints. The authors’ approach bridges, for the first time, the reliability gap between hardware and software. Readers will learn how to achieve increased soft error resilience on unreliable hardware, while exploiting the inherent error masking characteristics and error (stemming from soft errors, aging, and process variations) mitigations potential at different software layers. · Provides a comprehensive overview of reliability modeling and optimization techniques at different hardware and software levels; · Describes novel optimization techniques for software cross-layer reliability, targeting unreliable hardware.

  20. Hardware/Software Co-design using Primitive Interface

    Directory of Open Access Journals (Sweden)

    Navin Chourasia

    2011-08-01

    Full Text Available Most engineering designs can be viewed as systems, i.e., as collections of several components whose combined operation provides useful services. Components can be heterogeneous in nature and their interaction may be regulated by some simple or complex means. Interface between Hardware & Software plays a very important role in co-design of the embedded system. Hardware/software co-design means meeting system-level objectives by exploiting the synergism of hardware and software through their concurrent design. This paper shows how hardware & software interfaces can be implemented using primitive interface design

  1. Project W-420 Stack Monitoring system upgrades conceptual design report

    Energy Technology Data Exchange (ETDEWEB)

    TUCK, J.A.

    1998-11-06

    This document describes the scope, justification, conceptual design, and performance of Project W-420 stack monitoring system upgrades on six NESHAP-designated, Hanford Tank Farms ventilation exhaust stacks.

  2. Analog Exercise Hardware to Implement a High Intensity Exercise Program During Bed Rest

    Science.gov (United States)

    Loerch, Linda; Newby, Nate; Ploutz-Snyder, Lori

    2012-01-01

    used for leg press and heel raise exercises. Minor modifications were made to the device including adding 200 lbs to the weight stack, raising the frame by 12 inches, making the footplate adjustable, and providing removable handles. Conclusion: A combination of novel and commercial exercise hardware are used to mimic the exercise hardware capabilities aboard the ISS, allowing scientific investigation of new countermeasure protocols in a space flight analog prior to flight validation

  3. A Fast hardware tracker for the ATLAS Trigger

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. To achieve high background rejection while maintaining good efficiency for interesting physics signals, sophisticated algorithms are needed which require extensive use of tracking information. The Fast TracKer (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform track-finding at 100 kHz and based on a mixture of advanced technologies. Modern, powerful Field Programmable Gate Arrays (FPGA) form an important part of the system architecture, and the combinatorial problem of pattern recognition is solved by ~8000 standard-cell ASICs named Associative Memories. The availability of the tracking and subsequent vertex information within a short latency ensures robust selections and allows improved trigger performance for the most difficult sign...

  4. RF control hardware design for CYCIAE-100 cyclotron

    Science.gov (United States)

    Yin, Zhiguo; Fu, Xiaoliang; Ji, Bin; Zhao, Zhenlu; Zhang, Tianjue; Li, Pengzhan; Wei, Junyi; Xing, Jiansheng; Wang, Chuan

    2015-11-01

    The Beijing Radioactive Ion-beam Facility project is being constructed by BRIF division of China Institute of Atomic Energy. In this project, a 100 MeV high intensity compact proton cyclotron is built for multiple applications. The first successful beam extraction of CYCIAE-100 cyclotron was done in the middle of 2014. The extracted proton beam energy is 100 MeV and the beam current is more than 20 μA. The RF system of the CYCIAE-100 cyclotron includes two half-wavelength cavities, two 100 kW tetrode amplifiers and power transmission line systems (all above are independent from each other) and two sets of Low Level RF control crates. Each set of LLRF control includes an amplitude control unit, a tuning control unit, a phase control unit, a local Digital Signal Process control unit and an Advanced RISC Machines based EPICS IOC unit. These two identical LLRF control crates share one common reference clock and take advantages of modern digital technologies (e.g. DSP and Direct Digital Synthesizer) to achieve closed loop voltage and phase regulations of the dee-voltage. In the beam commission, the measured dee-voltage stability of RF system is better than 0.1% and phase stability is better than 0.03°. The hardware design of the LLRF system will be reviewed in this paper.

  5. A Fast hardware Tracker for the ATLAS Trigger system

    CERN Document Server

    Pandini, Carlo Enrico; The ATLAS collaboration

    2015-01-01

    The trigger system at the ATLAS experiment is designed to lower the event rate occurring from the nominal bunch crossing at 40 MHz to about 1 kHz for a designed LHC luminosity of 10$^{34}$ cm$^{-2}$ s$^{-1}$. After a very successful data taking run the LHC is expected to run starting in 2015 with much higher instantaneous luminosities and this will increase the load on the High Level Trigger system. More sophisticated algorithms will be needed to achieve higher background rejection while maintaining good efficiency for interesting physics signals, which requires a more extensive use of tracking information. The Fast Tracker (FTK) trigger system, part of the ATLAS trigger upgrade program, is a highly parallel hardware device designed to perform full-scan track-finding at the event rate of 100 kHz. FTK is a dedicated processor based on a mixture of advanced technologies. Modern, powerful, Field Programmable Gate Arrays form an important part of the system architecture, and the combinatorial problem of pattern r...

  6. Extracting high fidelity quantum computer hardware from random systems

    International Nuclear Information System (INIS)

    An overview of current status and prospects of the development of quantum computer hardware based on inorganic crystals doped with rare-earth ions are presented. Major parts of the experimental work in this area have been done in two places, Canberra, Australia and Lund, Sweden, and the present description follows more closely the Lund work. Techniques will be described that include optimal filtering of the initially inhomogeneously broadened profile down to well separated and narrow ensembles, as well as the use of advanced pulse-shaping in order to achieve robust arbitrary single-qubit operations with fidelities above 90%, as characterized by quantum state tomography. It is expected that full scalability of these systems will require the ability to determine the state of single rare-earth ions. It has been proposed that this can be done using special readout ions doped into the crystal and an update is given on the work to find and characterize such ions. Finally, a few aspects on possibilities for remote entanglement of ions in separate rare-earth-ion-doped crystals are considered.

  7. Magnetic qubits as hardware for quantum computers

    International Nuclear Information System (INIS)

    We propose two potential realisations for quantum bits based on nanometre scale magnetic particles of large spin S and high anisotropy molecular clusters. In case (1) the bit-value basis states vertical bar-0> and vertical bar-1> are the ground and first excited spin states Sz = S and S-1, separated by an energy gap given by the ferromagnetic resonance (FMR) frequency. In case (2), when there is significant tunnelling through the anisotropy barrier, the qubit states correspond to the symmetric, vertical bar-0>, and antisymmetric, vertical bar-1>, combinations of the two-fold degenerate ground state Sz = ± S. In each case the temperature of operation must be low compared to the energy gap, Δ, between the states vertical bar-0> and vertical bar-1>. The gap Δ in case (2) can be controlled with an external magnetic field perpendicular to the easy axis of the molecular cluster. The states of different molecular clusters and magnetic particles may be entangled by connecting them by superconducting lines with Josephson switches, leading to the potential for quantum computing hardware. (author)

  8. Hardware upgrade for A2 data acquisition

    Energy Technology Data Exchange (ETDEWEB)

    Ostrick, Michael; Gradl, Wolfgang; Otte, Peter-Bernd; Neiser, Andreas; Steffen, Oliver; Wolfes, Martin; Koerner, Tito [Institut fuer Kernphysik, Mainz (Germany); Collaboration: A2-Collaboration

    2014-07-01

    The A2 Collaboration uses an energy tagged photon beam which is produced via bremsstrahlung off the MAMI electron beam. The detector system consists of Crystal Ball and TAPS and covers almost the whole solid angle. A frozen-spin polarized target allows to perform high precision measurements of polarization observables in meson photo-production. During the last summer, a major upgrade of the data acquisition system was performed, both on the hardware and the software side. The goal of this upgrade was increased reliability of the system and an improvement in the data rate to disk. By doubling the number of readout CPUs and employing special VME crates with a split backplane, the number of bus accesses per readout cycle and crate was cut by a factor of two, giving almost a factor of two gain in the readout rate. In the course of the upgrade, we also switched most of the detector control system to using the distributed control system EPICS. For the upgraded control system, some new tools were developed to make full use of the capabilities of this decentralised slow control and monitoring system. The poster presents some of the major contributions to this project.

  9. Live HDR video streaming on commodity hardware

    Science.gov (United States)

    McNamee, Joshua; Hatchett, Jonathan; Debattista, Kurt; Chalmers, Alan

    2015-09-01

    High Dynamic Range (HDR) video provides a step change in viewing experience, for example the ability to clearly see the soccer ball when it is kicked from the shadow of the stadium into sunshine. To achieve the full potential of HDR video, so-called true HDR, it is crucial that all the dynamic range that was captured is delivered to the display device and tone mapping is confined only to the display. Furthermore, to ensure widespread uptake of HDR imaging, it should be low cost and available on commodity hardware. This paper describes an end-to-end HDR pipeline for capturing, encoding and streaming high-definition HDR video in real-time using off-the-shelf components. All the lighting that is captured by HDR-enabled consumer cameras is delivered via the pipeline to any display, including HDR displays and even mobile devices with minimum latency. The system thus provides an integrated HDR video pipeline that includes everything from capture to post-production, archival and storage, compression, transmission, and display.

  10. Implementation of a veto processing hardware

    International Nuclear Information System (INIS)

    This paper describes the implementation of a piece of general purpose events veto processing hardware, in the form of a custom integrated circuit and a minimum of additional components, for use with pixel-type detectors, in particular those requiring the technique of time-walk correction and multi-trigger association. This work was carried out as a part of the design study for a gamma-ray imager experiment such as the one proposed for the integral spacecraft mission. The design can handle up to 3072 detector elements, grouped into 24 separate detector modules (consisting of up to 128 detector elements each) in addition to a veto shield detector module. The system will be capable of handling a maximum average detector trigger rate of 10 000 triggers/s and veto shield trigger rate of 70 000 triggers/s without saturating the system. Analysis of an operational model of the gamma-ray imager under study results in 1400 valid events s where on average there are 1.75 triggers per event. This will result in data reduction factor of 4. The IC can also perform triggers to events associations thus, further reducing the workload on the rest of the experiment's central data processing system. This study shows that a single ASIC solution is viable using for example a XILINX IC, three 8 k x 8 SRAMs and a single 512 k x 1 bit serial ROM. (orig.)

  11. Open Hardware For CERN's Accelerator Control Systems

    CERN Document Server

    van der Bij, E; Ayass, M; Boccardi, A; Cattin, M; Gil Soriano, C; Gousiou, E; Iglesias Gonsálvez, S; Penacoba Fernandez, G; Serrano, J; Voumard, N; Wlostowski, T

    2011-01-01

    The accelerator control systems at CERN will be renovated and many electronics modules will be redesigned as the modules they will replace cannot be bought anymore or use obsolete components. The modules used in the control systems are diverse: analog and digital I/O, level converters and repeaters, serial links and timing modules. Overall around 120 modules are supported that are used in systems such as beam instrumentation, cryogenics and power converters. Only a small percentage of the currently used modules are commercially available, while most of them had been specifically designed at CERN. The new developments are based on VITA and PCI-SIG standards such as FMC (FPGA Mezzanine Card), PCI Express and VME64x using transition modules. As system-on-chip interconnect, the public domain Wishbone specification is used. For the renovation, it is considered imperative to have for each board access to the full hardware design and its firmware so that problems could quickly be resolved by CERN engineers or its ...

  12. Absorption spectra of AA-stacked graphite

    Energy Technology Data Exchange (ETDEWEB)

    Chiu, C W; Lee, S H; Chen, S C; Lin, M F [Department of Physics, National Cheng Kung University, Taiwan (China); Shyu, F L, E-mail: fl.shyu@msa.hinet.ne, E-mail: mflin@mail.ncku.edu.t [Department of Physics, ROC Military Academy, 830 Kaohsiung, Taiwan (China)

    2010-08-15

    AA-stacked graphite shows strong anisotropy in geometric structures and velocity matrix elements. However, the absorption spectra are isotropic for the polarization vector on the graphene plane. The spectra exhibit one prominent plateau at middle energy and one shoulder structure at lower energy. These structures directly reflect the unique geometric and band structures and provide sufficient information for experimental fitting of the intralayer and interlayer atomic interactions. On the other hand, monolayer graphene shows a sharp absorption peak but no shoulder structure; AA-stacked bilayer graphene has two absorption peaks at middle energy and abruptly vanishes at lower energy. Furthermore, the isotropic features are expected to exist in other graphene-related systems. The calculated results and the predicted atomic interactions could be verified by optical measurements.

  13. High power collimated diode laser stack

    Institute of Scientific and Technical Information of China (English)

    LIU Yuan-yuan; FANG Gao-zhan; MA Xiao-yu; LIU Su-ping; FENG Xiao-ming

    2006-01-01

    A high power collimated diode laser stack is carried out based on fast-axis collimation and stack packaging techniques.The module includes ten typical continuous wave (cw) bars and the total output power can be up to 368W at 48.6A.Using a cylindrical lens as the collimation elements,we can make the fast-axis divergence and the slow-axis divergence are 0.926 40 and 8.2060 respectively.The light emitting area is limited in a square area of 18.3 mm×11 mm.The module has the advantage of high power density and offers a wide potential applications in pumping and material processing.

  14. Process for 3D chip stacking

    Science.gov (United States)

    Malba, Vincent

    1998-01-01

    A manufacturable process for fabricating electrical interconnects which extend from a top surface of an integrated circuit chip to a sidewall of the chip using laser pantography to pattern three dimensional interconnects. The electrical interconnects may be of an L-connect or L-shaped type. The process implements three dimensional (3D) stacking by moving the conventional bond or interface pads on a chip to the sidewall of the chip. Implementation of the process includes: 1) holding individual chips for batch processing, 2) depositing a dielectric passivation layer on the top and sidewalls of the chips, 3) opening vias in the dielectric, 4) forming the interconnects by laser pantography, and 5) removing the chips from the holding means. The process enables low cost manufacturing of chips with bond pads on the sidewalls, which enables stacking for increased performance, reduced space, and higher functional per unit volume.

  15. Industrial stacks design; Diseno de chimeneas industriales

    Energy Technology Data Exchange (ETDEWEB)

    Cacheux, Luis [Instituto de Investigaciones Electricas, Cuernavaca (Mexico)

    1986-12-31

    The Instituto de Investigaciones Electricas (IIE) though its Civil Works Department, develops, under contract with CFE`s Gerencia de Proyectos Termoelectricos (Management of Fossil Power Plant Projects), a series of methods for the design of stacks, which pretends to solve the a present day problem: the stack design of the fossil power plants that will go into operation during the next coming years in the country. [Espanol] El Instituto de Investigaciones Electricas (IIE), a traves del Departamento de Ingenieria Civil, desarrolla, bajo contrato con la Gerencia de Proyectos Termoelectricos, de la Comision Federal de Electricidad (CFE), un conjunto de metodos para el diseno de chimeneas, con el que se pretende resolver un problema inmediato: el diseno de las chimeneas de las centrales termoelectricas que entraran en operacion durante los proximos anos, en el pais.

  16. Development of on-site PAFC stacks

    Energy Technology Data Exchange (ETDEWEB)

    Hotta, K.; Matsumoto, Y. [Kansai Electric Power Co., Amagasaki (Japan); Horiuchi, H.; Ohtani, T. [Mitsubishi Electric Corp., Kobe (Japan)

    1996-12-31

    PAFC (Phosphoric Acid Fuel Cell) has been researched for commercial use and demonstration plants have been installed in various sites. However, PAFC don`t have a enough stability yet, so more research and development must be required in the future. Especially, cell stack needs a proper state of three phases (liquid, gas and solid) interface. It is very difficult technology to keep this condition for a long time. In the small size cell with the electrode area of 100 cm{sup 2}, gas flow and temperature distributions show uniformity. But in the large size cell with the electrode area of 4000 cm{sup 2}, the temperature distributions show non-uniformity. These distributions would cause to be shorten the cell life. Because these distributions make hot-spot and gas poverty in limited parts. So we inserted thermocouples in short-stack for measuring three-dimensional temperature distributions and observed effects of current density and gas utilization on temperature.

  17. System for inspection of stacked cargo containers

    Science.gov (United States)

    Derenzo, Stephen

    2011-08-16

    The present invention relates to a system for inspection of stacked cargo containers. One embodiment of the invention generally comprises a plurality of stacked cargo containers arranged in rows or tiers, each container having a top, a bottom a first side, a second side, a front end, and a back end; a plurality of spacers arranged in rows or tiers; one or more mobile inspection devices for inspecting the cargo containers, wherein the one or more inspection devices are removeably disposed within the spacers, the inspection means configured to move through the spacers to detect radiation within the containers. The invented system can also be configured to inspect the cargo containers for a variety of other potentially hazardous materials including but not limited to explosive and chemical threats.

  18. Fluxon dynamics in three stacked Josephson junctions

    DEFF Research Database (Denmark)

    Gorria, Carlos; Christiansen, Peter Leth; Gaididei, Yuri Borisovich;

    2002-01-01

    /sub -/, the coupling between junctions leads to a repulsion of the fluxons with the same polarity. Above this critical velocity a fluxon will induce radiation in the neighboring junctions, leading to a bunching of the fluxons in the stacked junctions. Using the Sakai-Bodin-Pedersen model, three coupled perturbed sine......The motion of fluxons of the same polarity in three vertically stacked Josephson junctions is studied. In this configuration the difference between exterior and interior junctions plays a more important role than in other configurations with several interior junctions. Below the Swihart velocity c......-Gordon equations are numerically studied for different values of coupling, damping, and bias parameters. In a narrow range of velocities bunching occurs. Outside this interval the fluxons split and new fluxons may be created. I-V characteristics are presented...

  19. Spectral analysis using linearly chirped Gaussian pulse stacking

    International Nuclear Information System (INIS)

    We analyze the spectrum of a stacked pulse with the technique of linearly chirped Gaussian pulse stacking. Our results show that there are modulation structures in the spectrum of the stacked pulse. The modulation frequencies are discussed in detail. By applying spectral analysis, we find that the intensity fluctuation cannot be smoothed by introducing an optical amplitude filter. (authors)

  20. Spectral Analysis using Linearly Chirped Gaussian Pulse Stacking

    Institute of Scientific and Technical Information of China (English)

    ZHENG Huan; WANG An-Ting; XU Li-Xin; MING Hai

    2009-01-01

    We analyze the spectrum of a stacked pulse with the technique of linearly chirped Gaussian pulse stacking.Our results show that there are modulation structures in the spectrum of the stacked pulse. The modulation frequencies are discussed in detail. By applying spectral analysis, we find that the intensity fluctuation cannot be smoothed by introducing an optical amplitude filter.

  1. Ultrasound and clinical evaluation of soft-tissue versus hardware biceps tenodesis: is hardware tenodesis worth the cost?

    Science.gov (United States)

    Elkousy, Hussein; Romero, Jose A; Edwards, T Bradley; Gartsman, Gary M; O'Connor, Daniel P

    2014-02-01

    This study assesses the failure rate of soft-tissue versus hardware fixation of biceps tenodesis by ultrasound to determine if the expense of a hardware tenodesis technique is warranted. Seventy-two patients that underwent arthroscopic biceps tenodesis over a 3-year period were evaluated using postoperative ultrasonography and clinical examination. The tenodesis technique employed was either a soft-tissue technique with sutures or an interference screw technique using hardware based on surgeon preference. Patient age was 57.9 years on average with ultrasound and clinical examination done at an average of 9.3 months postoperatively. Thirty-one patients had a hardware technique and 41 a soft-tissue technique. Overall, 67.7% of biceps tenodesis done with hardware were intact, compared with 75.6% for the soft-tissue technique by ultrasound (P = .46). Clinical evaluation indicated that 80.7% of hardware techniques and 78% of soft-tissue techniques were intact. Average material cost to the hospital for the hardware technique was $514.32, compared with $32.05 for the soft-tissue technique. Biceps tenodesis success, as determined by clinical deformity and ultrasound, was not improved using hardware as compared to soft-tissue techniques. Soft-tissue techniques are equally efficacious and more cost effective than hardware techniques.

  2. Angular resolution of stacked resistive plate chambers

    CERN Document Server

    Samuel, Deepak; Murgod, Lakshmi P

    2016-01-01

    We present here detailed derivations of mathematical expressions for the angular resolution of a set of stacked resistive plate chambers (RPCs). The expressions are validated against experimental results using data collected from the prototype detectors (without magnet) of the upcoming India-based Neutrino Observatory (INO). In principle, these expressions can be used for any other detector with an architecture similar to that of RPCs.

  3. When is stacking confusing? The impact of confusion on stacking in deep H I galaxy surveys

    Science.gov (United States)

    Jones, Michael G.; Haynes, Martha P.; Giovanelli, Riccardo; Papastergis, Emmanouil

    2016-01-01

    We present an analytic model to predict the H I mass contributed by confused sources to a stacked spectrum in a generic H I survey. Based on the ALFALFA (Arecibo Legacy Fast ALFA) correlation function, this model is in agreement with the estimates of confusion present in stacked Parkes telescope data, and was used to predict how confusion will limit stacking in the deepest Square Kilometre Array precursor H I surveys. Stacking with LADUMA (Looking At the Distant Universe with MeerKAT) and DINGO UDEEP (Deep Investigation of Neutral Gas Origins - Ultra Deep) data will only be mildly impacted by confusion if their target synthesized beam size of 10 arcsec can be achieved. Any beam size significantly above this will result in stacks that contain a mass in confused sources that is comparable to (or greater than) that which is detectable via stacking, at all redshifts. CHILES (COSMOS H I Large Extragalactic Survey) 5 arcsec resolution is more than adequate to prevent confusion influencing stacking of its data, throughout its bandpass range. FAST (Five hundred metre Aperture Spherical Telescope) will be the most impeded by confusion, with H I surveys likely becoming heavily confused much beyond z = 0.1. The largest uncertainties in our model are the redshift evolution of the H I density of the Universe and the H I correlation function. However, we argue that the two idealized cases we adopt should bracket the true evolution, and the qualitative conclusions are unchanged regardless of the model choice. The profile shape of the signal due to confusion (in the absence of any detection) was also modelled, revealing that it can take the form of a double Gaussian with a narrow and wide component.

  4. HTS twisted stacked-tape cable conductor

    International Nuclear Information System (INIS)

    The feasibility of high field magnet applications of the twisted stacked-tape cabling method with 2G YBCO tapes has been investigated. An analysis of torsional twist strains of a thin HTS tape has been carried out taking into account the internal shortening compressive strains accompanied with the lengthening tensile strains due to the torsional twist. The model is benchmarked against experimental tests using YBCO tapes. The critical current degradation and current distribution of a four-tape conductor was evaluated by taking account of the twist strain, the self-field and the termination resistances. The critical current degradation for the tested YBCO cables can be explained by the perpendicular self-field effect. It is shown that the critical current of a twisted stacked-tape conductor with a four-tape cable does not degrade with a twist pitch length as short as 120 mm. Current distribution among tapes and hysteresis losses are also investigated. A compact joint termination method for a 2G YBCO tape cable has been developed. The twisted stacked-tape conductor method may be an attractive means for the fabrication of highly compact, high current cables from multiple flat HTS tapes.

  5. Thyristor stack for pulsed inductive plasma generation.

    Science.gov (United States)

    Teske, C; Jacoby, J; Schweizer, W; Wiechula, J

    2009-03-01

    A thyristor stack for pulsed inductive plasma generation has been developed and tested. The stack design includes a free wheeling diode assembly for current reversal. Triggering of the device is achieved by a high side biased, self supplied gate driver unit using gating energy derived from a local snubber network. The structure guarantees a hard firing gate pulse for the required high dI/dt application. A single fiber optic command is needed to achieve a simultaneous turn on of the thyristors. The stack assembly is used for switching a series resonant circuit with a ringing frequency of 30 kHz. In the prototype pulsed power system described here an inductive discharge has been generated with a pulse duration of 120 micros and a pulse energy of 50 J. A maximum power transfer efficiency of 84% and a peak power of 480 kW inside the discharge were achieved. System tests were performed with a purely inductive load and an inductively generated plasma acting as a load through transformer action at a voltage level of 4.1 kV, a peak current of 5 kA, and a current switching rate of 1 kA/micros. PMID:19334940

  6. Thyristor stack for pulsed inductive plasma generation.

    Science.gov (United States)

    Teske, C; Jacoby, J; Schweizer, W; Wiechula, J

    2009-03-01

    A thyristor stack for pulsed inductive plasma generation has been developed and tested. The stack design includes a free wheeling diode assembly for current reversal. Triggering of the device is achieved by a high side biased, self supplied gate driver unit using gating energy derived from a local snubber network. The structure guarantees a hard firing gate pulse for the required high dI/dt application. A single fiber optic command is needed to achieve a simultaneous turn on of the thyristors. The stack assembly is used for switching a series resonant circuit with a ringing frequency of 30 kHz. In the prototype pulsed power system described here an inductive discharge has been generated with a pulse duration of 120 micros and a pulse energy of 50 J. A maximum power transfer efficiency of 84% and a peak power of 480 kW inside the discharge were achieved. System tests were performed with a purely inductive load and an inductively generated plasma acting as a load through transformer action at a voltage level of 4.1 kV, a peak current of 5 kA, and a current switching rate of 1 kA/micros.

  7. Monitoring Particulate Matter with Commodity Hardware

    Science.gov (United States)

    Holstius, David

    Health effects attributed to outdoor fine particulate matter (PM 2.5) rank it among the risk factors with the highest health burdens in the world, annually accounting for over 3.2 million premature deaths and over 76 million lost disability-adjusted life years. Existing PM2.5 monitoring infrastructure cannot, however, be used to resolve variations in ambient PM2.5 concentrations with adequate spatial and temporal density, or with adequate coverage of human time-activity patterns, such that the needs of modern exposure science and control can be met. Small, inexpensive, and portable devices, relying on newly available off-the-shelf sensors, may facilitate the creation of PM2.5 datasets with improved resolution and coverage, especially if many such devices can be deployed concurrently with low system cost. Datasets generated with such technology could be used to overcome many important problems associated with exposure misclassification in air pollution epidemiology. Chapter 2 presents an epidemiological study of PM2.5 that used data from ambient monitoring stations in the Los Angeles basin to observe a decrease of 6.1 g (95% CI: 3.5, 8.7) in population mean birthweight following in utero exposure to the Southern California wildfires of 2003, but was otherwise limited by the sparsity of the empirical basis for exposure assessment. Chapter 3 demonstrates technical potential for remedying PM2.5 monitoring deficiencies, beginning with the generation of low-cost yet useful estimates of hourly and daily PM2.5 concentrations at a regulatory monitoring site. The context (an urban neighborhood proximate to a major goods-movement corridor) and the method (an off-the-shelf sensor costing approximately USD $10, combined with other low-cost, open-source, readily available hardware) were selected to have special significance among researchers and practitioners affiliated with contemporary communities of practice in public health and citizen science. As operationalized by

  8. Hardware replacements and software tools for digital control computers

    International Nuclear Information System (INIS)

    Technological obsolescence is an on-going challenge for all computer use. By design, and to some extent good fortune, AECL has had a good track record with respect to the march of obsolescence in CANDU digital control computer technology. Recognizing obsolescence as a fact of life, AECL has undertaken a program of supporting the digital control technology of existing CANDU plants. Other AECL groups are developing complete replacement systems for the digital control computers, and more advanced systems for the digital control computers of the future CANDU reactors. This paper presents the results of the efforts of AECL's DCC service support group to replace obsolete digital control computer and related components and to provide friendlier software technology related to the maintenance and use of digital control computers in CANDU. These efforts are expected to extend the current lifespan of existing digital control computers through their mandated life. This group applied two simple rules; the product, whether new or replacement should have a generic basis, and the products should be applicable to both existing CANDU plants and to 'repeat' plant designs built using current design guidelines. While some exceptions do apply, the rules have been met. The generic requirement dictates that the product should not be dependent on any brand technology, and should back-fit to and interface with any such technology which remains in the control design. The application requirement dictates that the product should have universal use and be user friendly to the greatest extent possible. Furthermore, both requirements were designed to anticipate user involvement, modifications and alternate user defined applications. The replacements for hardware components such as paper tape reader/punch, moving arm disk, contact scanner and Ramtek are discussed. The development of these hardware replacements coincide with the development of a gateway system for selected CANDU digital control

  9. Life sciences flight hardware development for the International Space Station

    Science.gov (United States)

    Kern, V. D.; Bhattacharya, S.; Bowman, R. N.; Donovan, F. M.; Elland, C.; Fahlen, T. F.; Girten, B.; Kirven-Brooks, M.; Lagel, K.; Meeker, G. B.; Santos, O.

    During the construction phase of the International Space Station (ISS), early flight opportunities have been identified (including designated Utilization Flights, UF) on which early science experiments may be performed. The focus of NASA's and other agencies' biological studies on the early flight opportunities is cell and molecular biology; with UF-1 scheduled to fly in fall 2001, followed by flights 8A and UF-3. Specific hardware is being developed to verify design concepts, e.g., the Avian Development Facility for incubation of small eggs and the Biomass Production System for plant cultivation. Other hardware concepts will utilize those early research opportunities onboard the ISS, e.g., an Incubator for sample cultivation, the European Modular Cultivation System for research with small plant systems, an Insect Habitat for support of insect species. Following the first Utilization Flights, additional equipment will be transported to the ISS to expand research opportunities and capabilities, e.g., a Cell Culture Unit, the Advanced Animal Habitat for rodents, an Aquatic Facility to support small fish and aquatic specimens, a Plant Research Unit for plant cultivation, and a specialized Egg Incubator for developmental biology studies. Host systems (Figure 1A, B), e.g., a 2.5 m Centrifuge Rotor (g-levels from 0.01-g to 2-g) for direct comparisons between μg and selectable g levels, the Life Sciences Glove☐ for contained manipulations, and Habitat Holding Racks (Figure 1B) will provide electrical power, communication links, and cooling to the habitats. Habitats will provide food, water, light, air and waste management as well as humidity and temperature control for a variety of research organisms. Operators on Earth and the crew on the ISS will be able to send commands to the laboratory equipment to monitor and control the environmental and experimental parameters inside specific habitats. Common laboratory equipment such as microscopes, cryo freezers, radiation

  10. FPGA BASED HARDWARE KEY FOR TEMPORAL ENCRYPTION

    Directory of Open Access Journals (Sweden)

    B. Lakshmi

    2010-09-01

    Full Text Available In this paper, a novel encryption scheme with time based key technique on an FPGA is presented. Time based key technique ensures right key to be entered at right time and hence, vulnerability of encryption through brute force attack is eliminated. Presently available encryption systems, suffer from Brute force attack and in such a case, the time taken for breaking a code depends on the system used for cryptanalysis. The proposed scheme provides an effective method in which the time is taken as the second dimension of the key so that the same system can defend against brute force attack more vigorously. In the proposed scheme, the key is rotated continuously and four bits are drawn from the key with their concatenated value representing the delay the system has to wait. This forms the time based key concept. Also the key based function selection from a pool of functions enhances the confusion and diffusion to defend against linear and differential attacks while the time factor inclusion makes the brute force attack nearly impossible. In the proposed scheme, the key scheduler is implemented on FPGA that generates the right key at right time intervals which is then connected to a NIOS – II processor (a virtual microcontroller which is brought out from Altera FPGA that communicates with the keys to the personal computer through JTAG (Joint Test Action Group communication and the computer is used to perform encryption (or decryption. In this case the FPGA serves as hardware key (dongle for data encryption (or decryption.

  11. The use of additive manufacture for metallic bipolar plates in polymer electrolyte fuel cell stacks

    OpenAIRE

    Dawson, Richard; Patel, Anant; Rennie, Allan; White, Simon

    2014-01-01

    The bipolar plate is of critical importance to the efficient and long lasting operation of a polymer electrolyte fuel cell (PEMFC) stack. With advances in membrane electrode assembly (MEA) design greater attention has been focused on the bipolar plate and the important role it plays in performance and durability. Although carbon composite plates are a likely candidate for the mass introduction of fuel cells, it is metallic plates made from thin strip materials (typically 0.2 mm thick stainles...

  12. Hardware packet pacing using a DMA in a parallel computer

    Science.gov (United States)

    Chen, Dong; Heidelberger, Phillip; Vranas, Pavlos

    2013-08-13

    Method and system for hardware packet pacing using a direct memory access controller in a parallel computer which, in one aspect, keeps track of a total number of bytes put on the network as a result of a remote get operation, using a hardware token counter.

  13. Developing a Decision Support System: The Software and Hardware Tools.

    Science.gov (United States)

    Clark, Phillip M.

    1989-01-01

    Describes some of the available software and hardware tools that can be used to develop a decision support system implemented on microcomputers. Activities that should be supported by software are discussed, including data entry, data coding, finding and combining data, and data compatibility. Hardware considerations include speed, storage…

  14. The hardware and software support for the MRSP.

    Science.gov (United States)

    Teuber, D.

    The Muenster Redshift Project (MRSP) described by Horstmann (1988) and Schuecker (1988) relies on an arrangement of hardware and software which is referred to as the Astronomical Data Analysis System. In this paper the hardware is briefly introduced and the support software GAME is discussed.

  15. Teaching Robotics Software with the Open Hardware Mobile Manipulator

    Science.gov (United States)

    Vona, M.; Shekar, N. H.

    2013-01-01

    The "open hardware mobile manipulator" (OHMM) is a new open platform with a unique combination of features for teaching robotics software and algorithms. On-board low- and high-level processors support real-time embedded programming and motor control, as well as higher-level coding with contemporary libraries. Full hardware designs and…

  16. A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding

    Directory of Open Access Journals (Sweden)

    Li-Hsun Chen

    2007-01-01

    Full Text Available Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 μm CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45 mm2, and yields a throughput rate of 20 M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.

  17. A Hardware-Efficient Programmable FIR Processor Using Input-Data and Tap Folding

    Directory of Open Access Journals (Sweden)

    Chen Oscal T-C

    2007-01-01

    Full Text Available Advances in nanoelectronic fabrication have enabled integrated circuits to operate at a high frequency. The finite impulse response (FIR filter needs only to meet real-time demand. Accordingly, increasing the FIR architecture's folding number can compensate the high-frequency operation and reduce the hardware complexity, while continuing to allow applications to operate in real time. In this work, the folding scheme with integrating input-data and tap folding is proposed to develop a hardware-efficient programmable FIR architecture. With the use of the radix-4 Booth algorithm, the 2-bit input subdata approach replaces the conventional 3-bit input subdata approach to reduce the number of latches required to store input subdata in the proposed FIR architecture. Additionally, the tree accumulation approach with simplified carry-in bit processing is developed to minimize the hardware complexity of the accumulation path. With folding in input data and taps, and reduction in hardware complexity of the input subdata latches and accumulation path, the proposed FIR architecture is demonstrated to have a low hardware complexity. By using the TSMC 0.18 m CMOS technology, the proposed FIR processor with 10-bit input data and filter coefficient enables a 128-tap FIR filter to be performed, which takes an area of 0.45 , and yields a throughput rate of 20 M samples per second at 200 MHz. As compared to the conventional FIR processors, the proposed programmable FIR processor not only meets the throughput-rate demand but also has the lowest area occupied per tap.

  18. A Practical Introduction to HardwareSoftware Codesign

    CERN Document Server

    Schaumont, Patrick R

    2013-01-01

    This textbook provides an introduction to embedded systems design, with emphasis on integration of custom hardware components with software. The key problem addressed in the book is the following: how can an embedded systems designer strike a balance between flexibility and efficiency? The book describes how combining hardware design with software design leads to a solution to this important computer engineering problem. The book covers four topics in hardware/software codesign: fundamentals, the design space of custom architectures, the hardware/software interface and application examples. The book comes with an associated design environment that helps the reader to perform experiments in hardware/software codesign. Each chapter also includes exercises and further reading suggestions. Improvements in this second edition include labs and examples using modern FPGA environments from Xilinx and Altera, which make the material applicable to a greater number of courses where these tools are already in use.  Mo...

  19. Hardware efficient monitoring of input/output signals

    Science.gov (United States)

    Driscoll, Kevin R. (Inventor); Hall, Brendan (Inventor); Paulitsch, Michael (Inventor)

    2012-01-01

    A communication device comprises first and second circuits to implement a plurality of ports via which the communicative device is operable to communicate over a plurality of communication channels. For each of the plurality of ports, the communication device comprises: command hardware that includes a first transmitter to transmit data over a respective one of the plurality of channels and a first receiver to receive data from the respective one of the plurality of channels; and monitor hardware that includes a second receiver coupled to the first transmitter and a third receiver coupled to the respective one of the plurality of channels. The first circuit comprises the command hardware for a first subset of the plurality of ports. The second circuit comprises the monitor hardware for the first subset of the plurality of ports and the command hardware for a second subset of the plurality of ports.

  20. Design of hardware platform of digital adjustor for HIRFL-CSR power supply

    International Nuclear Information System (INIS)

    The hardware platform of digital adjustor for HIRFL-CSR power system has been developed. It is based on Cyclone III FPGA, which is of 1 mm BGA package. The platform can run digital adjustor algorithm and satisfy specific technical requirements. ARM (Advanced RISC Machines) EP9315 microprocessor is used as the core of the control system to deal with the task of multi-threaded. And there are 1 G SFP connecting with FPGA to transmit data processed by DSP on other board, hence a great improvement of the system's real-time performance. The hardware platform can realize a stable, reliable, real-time control for the HIRFL-CSR power supply system. (authors)

  1. Re-configurable ATCA Hardware for Plasma Control and Data Acquisition

    International Nuclear Information System (INIS)

    ATCA platform is gaining interest in the physics community because of its main assets: -) advanced communication bus architecture (serial giga-bit replacing parallel buses), -) very high data throughput options and its suitability for real-time applications, -) high levels of modularity and adaptability, -) the ability to host large pools of DSPs, NPs, processors and storage, -) high security and regulatory conformance, -) reliable, full redundancy support, -) system high availability to 99.999%, and -) hardware management interface (IPMI). The ATCA standard presents a promising technology platform to develop complex, reliable, adaptable and scalable control and data acquisition system. Already appearing on Fusion Devices: JET, COMPASS, ISTTOK. The applications to JET γ-ray spectroscopy and to JET vertical stabilization controller are detailed. Modular Hardware Design and adaptable devices (FPGA) enables re-use in a wide range of control and data acquisition applications. This document is composed of the slides of the presentation

  2. Mechanical Design and Development of TES Bolometer Detector Arrays for the Advanced ACTPol Experiment

    Science.gov (United States)

    Ward, Jonathan T.; Austermann, Jason; Beall, James A.; Choi, Steve K.; Crowley, Kevin T.; Devlin, Mark J.; Duff, Shannon M.; Gallardo, Patricio M.; Henderson, Shawn W.; Ho, Shuay-Pwu Patty; Hilton, Gene; Hubmayr, Johannes; Khavari, Niloufar; Klein, Jeffrey; Koopman, Brian J.; Li, Dale; McMahon, Jeffrey; Mumby, Grace; Nati, Federico; Wollack, Edward J.

    2016-01-01

    The next generation Advanced ACTPol (AdvACT) experiment is currently underway and will consist of four Transition Edge Sensor (TES) bolometer arrays, with three operating together, totaling 5800 detectors on the sky. Building on experience gained with the ACTPol detector arrays, AdvACT will utilize various new technologies, including 150 mm detector wafers equipped with multichroic pixels, allowing for a more densely packed focal plane. Each set of detectors includes a feedhorn array of stacked silicon wafers which form a spline pro le leading to each pixel. This is then followed by a waveguide interface plate, detector wafer, back short cavity plate, and backshort cap. Each array is housed in a custom designed structure manufactured from high purity copper and then gold plated. In addition to the detector array assembly, the array package also encloses cryogenic readout electronics. We present the full mechanical design of the AdvACT high frequency (HF) detector array package along with a detailed look at the detector array stack assemblies. This experiment will also make use of extensive hardware and software previously developed for ACT, which will be modi ed to incorporate the new AdvACT instruments. Therefore, we discuss the integration of all AdvACT arrays with pre-existing ACTPol infrastructure.

  3. A Stack Cache for Real-Time Systems

    DEFF Research Database (Denmark)

    Schoeberl, Martin; Nielsen, Carsten

    2016-01-01

    Real-time systems need time-predictable computing platforms to allowfor static analysis of the worst-case execution time. Caches are important for good performance, but data caches arehard to analyze for the worst-case execution time. Stack allocated data has different properties related...... to locality, lifetime, and static analyzability of access addresses comparedto static or heap allocated data. Therefore, caching of stack allocateddata benefits from having its own cache. In this paper we present a cache architecture optimized for stack allocateddata. This cache is additional to the normal...... data cache. As stack allocated datahas a high locality, even a small stack cache gives a high hit rate. A stack cache added to a write-through data cache considerablyimproves the performance, while a stack cache compared tothe harder to analyze write-back cache has about the sameaverage case...

  4. Spectroscopic Signature of Stacking Disorder in Ice I.

    Science.gov (United States)

    Carr, Thomas H G; Shephard, Jacob J; Salzmann, Christoph G

    2014-07-17

    There is a growing realization that the presence of stacking disorder in ice I strongly influences its physical and chemical properties. Using Raman spectroscopy, we gain new fundamental insights into the spectroscopic properties of ice. We show that stacking disorder can be detected and quantified by comparing the spectra of stacking disordered ice with spectra of the "ordinary" hexagonal ice Ih. The spectral signature of stacking disorder is thought to arise from a greater structural diversity on the local length scale, vibrational modes that appear due to the lower-symmetry environments, and a strengthening of the covalent bonds. Our findings are compared to results from diffraction and calorimetry, and we discuss the advantages and disadvantages of the three techniques with respect to detecting stacking disorder in ice I. Apart from characterizing stacking disordered ice in the research lab, our new method is perfectly suited for remote or telescopic applications aiming at the identification of stacking disordered ice in nature.

  5. Horizontal high speed stacking for batteries with prismatic cans

    Energy Technology Data Exchange (ETDEWEB)

    Bartos, Andrew L.; Lin, Yhu-Tin; Turner, III, Raymond D.

    2016-06-14

    A system and method for stacking battery cells or related assembled components. Generally planar, rectangular (prismatic-shaped) battery cells are moved from an as-received generally vertical stacking orientation to a generally horizontal stacking orientation without the need for robotic pick-and-place equipment. The system includes numerous conveyor belts that work in cooperation with one another to deliver, rotate and stack the cells or their affiliated assemblies. The belts are outfitted with components to facilitate the cell transport and rotation. The coordinated movement between the belts and the components promote the orderly transport and rotation of the cells from a substantially vertical stacking orientation into a substantially horizontal stacking orientation. The approach of the present invention helps keep the stacked assemblies stable so that subsequent assembly steps--such as compressing the cells or attaching electrical leads or thermal management components--may proceed with a reduced chance of error.

  6. LONG-TERM PERFORMANCE OF SOLID OXIDE STACKS WITH ELECTRODE-SUPPORTED CELLS OPERATING IN THE STEAM ELECTROLYSIS MODE

    Energy Technology Data Exchange (ETDEWEB)

    J. E. O' Brien; R. C. O' Brien; X. Zhang; G. Tao; B. J. Butler

    2011-11-01

    Performance characterization and durability testing have been completed on two five-cell high-temperature electrolysis stacks constructed with advanced cell and stack technologies. The solid oxide cells incorporate a negative-electrode-supported multi-layer design with nickel-zirconia cermet negative electrodes, thin-film yttria-stabilized zirconia electrolytes, and multi-layer lanthanum ferrite-based positive electrodes. The per-cell active area is 100 cm2. The stack is internally manifolded with compliant mica-glass seals. Treated metallic interconnects with integral flow channels separate the cells. Stack compression is accomplished by means of a custom spring-loaded test fixture. Initial stack performance characterization was determined through a series of DC potential sweeps in both fuel cell and electrolysis modes of operation. Results of these sweeps indicated very good initial performance, with area-specific resistance values less than 0.5 ?.cm2. Long-term durability testing was performed with A test duration of 1000 hours. Overall performance degradation was less than 10% over the 1000-hour period. Final stack performance characterization was again determined by a series of DC potential sweeps at the same flow conditions as the initial sweeps in both electrolysis and fuel cell modes of operation. A final sweep in the fuel cell mode indicated a power density of 0.356 W/cm2, with average per-cell voltage of 0.71 V at a current of 50 A.

  7. FocusStack and StimServer: A new open source MATLAB toolchain for visual stimulation and analysis of two-photon calcium neuronal imaging data

    Directory of Open Access Journals (Sweden)

    Dylan Richard Muir

    2015-01-01

    Full Text Available Two-photon calcium imaging of neuronal responses is an increasingly accessible technology for probing population responses in cortex at single cell resolution, and with reasonable and improving temporal resolution. However, analysis of two-photon data is usually performed using ad-hoc solutions. To date, no publicly available software exists for straightforward analysis of stimulus-triggered two-photon imaging experiments. In addition, the increasing data rates of two-photon acquisition systems imply increasing cost of computing hardware required for in-memory analysis. Here we present a Matlab toolbox, FocusStack, for simple and efficient analysis of two-photon calcium imaging stacks on consumer-level hardware, with minimal memory footprint. We also present a Matlab toolbox, StimServer, for generation and sequencing of visual stimuli, designed to be triggered over a network link from a two-photon acquisition system. FocusStack is compatible out of the box with several existing two-photon acquisition systems, and is simple to adapt to arbitrary binary file formats. Analysis tools such as stack alignment for movement correction, automated cell detection and peri-stimulus time histograms are already provided, and further tools can be easily incorporated. Both packages are available as publicly-accessible source-code repositories.

  8. FocusStack and StimServer: a new open source MATLAB toolchain for visual stimulation and analysis of two-photon calcium neuronal imaging data.

    Science.gov (United States)

    Muir, Dylan R; Kampa, Björn M

    2014-01-01

    Two-photon calcium imaging of neuronal responses is an increasingly accessible technology for probing population responses in cortex at single cell resolution, and with reasonable and improving temporal resolution. However, analysis of two-photon data is usually performed using ad-hoc solutions. To date, no publicly available software exists for straightforward analysis of stimulus-triggered two-photon imaging experiments. In addition, the increasing data rates of two-photon acquisition systems imply increasing cost of computing hardware required for in-memory analysis. Here we present a Matlab toolbox, FocusStack, for simple and efficient analysis of two-photon calcium imaging stacks on consumer-level hardware, with minimal memory footprint. We also present a Matlab toolbox, StimServer, for generation and sequencing of visual stimuli, designed to be triggered over a network link from a two-photon acquisition system. FocusStack is compatible out of the box with several existing two-photon acquisition systems, and is simple to adapt to arbitrary binary file formats. Analysis tools such as stack alignment for movement correction, automated cell detection and peri-stimulus time histograms are already provided, and further tools can be easily incorporated. Both packages are available as publicly-accessible source-code repositories.

  9. PBG Based High Gain Microstrip Stacked Antenna

    Directory of Open Access Journals (Sweden)

    Babulal Chaudhary

    2013-03-01

    Full Text Available In this paper, authors have proposed the analysis of a rectangular stacked patch antenna operates at the frequency of 2.4 GHz with a photonic band-gap structure (PBG and compared its performances with a conventional patch antenna. Due to the presence of the PBG structure in the dielectric substrate, proposed antenna shows a significant reduction in surface wave levels than a conventional patch antenna. As a result, the gain of the proposed antenna is found to be improved by 3.2 dB

  10. Compliant Glass Seals for SOFC Stacks

    Energy Technology Data Exchange (ETDEWEB)

    Chou, Y. S.; Choi, Jung-Pyung; Xu, Wei; Stephens, Elizabeth V.; Koeppel, Brian J.; Stevenson, Jeffry W.; Lara-Curzio, Edgar

    2014-04-01

    This report summarizes results from experimental and modeling studies performed by participants in the Solid-State Energy Conversion Alliance (SECA) Core Technology Program, which indicate that compliant glass-based seals offer a number of potential advantages over conventional seals based on de-vitrifying glasses, including reduced stresses during stack operation and thermal cycling, and the ability to heal micro-damage induced during thermal cycling. The properties and composition of glasses developed and/or investigated in these studies are reported, along with results from long-term (up to 5,800h) evaluations of seals based on a compliant glass containing ceramic particles or ceramic fibers.

  11. Targeting multiple heterogeneous hardware platforms with OpenCL

    Science.gov (United States)

    Fox, Paul A.; Kozacik, Stephen T.; Humphrey, John R.; Paolini, Aaron; Kuller, Aryeh; Kelmelis, Eric J.

    2014-06-01

    The OpenCL API allows for the abstract expression of parallel, heterogeneous computing, but hardware implementations have substantial implementation differences. The abstractions provided by the OpenCL API are often insufficiently high-level to conceal differences in hardware architecture. Additionally, implementations often do not take advantage of potential performance gains from certain features due to hardware limitations and other factors. These factors make it challenging to produce code that is portable in practice, resulting in much OpenCL code being duplicated for each hardware platform being targeted. This duplication of effort offsets the principal advantage of OpenCL: portability. The use of certain coding practices can mitigate this problem, allowing a common code base to be adapted to perform well across a wide range of hardware platforms. To this end, we explore some general practices for producing performant code that are effective across platforms. Additionally, we explore some ways of modularizing code to enable optional optimizations that take advantage of hardware-specific characteristics. The minimum requirement for portability implies avoiding the use of OpenCL features that are optional, not widely implemented, poorly implemented, or missing in major implementations. Exposing multiple levels of parallelism allows hardware to take advantage of the types of parallelism it supports, from the task level down to explicit vector operations. Static optimizations and branch elimination in device code help the platform compiler to effectively optimize programs. Modularization of some code is important to allow operations to be chosen for performance on target hardware. Optional subroutines exploiting explicit memory locality allow for different memory hierarchies to be exploited for maximum performance. The C preprocessor and JIT compilation using the OpenCL runtime can be used to enable some of these techniques, as well as to factor in hardware

  12. Hardware Realization of Chaos Based Symmetric Image Encryption

    KAUST Repository

    Barakat, Mohamed L.

    2012-06-01

    This thesis presents a novel work on hardware realization of symmetric image encryption utilizing chaos based continuous systems as pseudo random number generators. Digital implementation of chaotic systems results in serious degradations in the dynamics of the system. Such defects are illuminated through a new technique of generalized post proceeding with very low hardware cost. The thesis further discusses two encryption algorithms designed and implemented as a block cipher and a stream cipher. The security of both systems is thoroughly analyzed and the performance is compared with other reported systems showing a superior results. Both systems are realized on Xilinx Vetrix-4 FPGA with a hardware and throughput performance surpassing known encryption systems.

  13. Aspects of system modelling in Hardware/Software partitioning

    DEFF Research Database (Denmark)

    Knudsen, Peter Voigt; Madsen, Jan

    1996-01-01

    This paper addresses fundamental aspects of system modelling and partitioning algorithms in the area of Hardware/Software Codesign. Three basic system models for partitioning are presented and the consequences of partitioning according to each of these are analyzed. The analysis shows the...... importance of making a clear distinction between the model used for partitioning and the model used for evaluation It also illustrates the importance of having a realistic hardware model such that hardware sharing can be taken into account. Finally, the importance of integrating scheduling and allocation...

  14. Hardware Synchronization for Embedded Multi-Core Processors

    DEFF Research Database (Denmark)

    Stoif, Christian; Schoeberl, Martin; Liccardi, Benito;

    2011-01-01

    , establishing coherence and consistency for different types of shared memory by hardware means. Also support for point-to-point synchronization between the processor cores is realized implementing different hardware barriers. The practical examinations focus on the logical first step from single- to dual......-core systems, using an FPGA-development board with two hard PowerPC processor cores. Best- and worst-case results, together with intensive benchmarking of all synchronization primitives implemented, show the expected superiority of the hardware solutions. It is also shown that dual-ported memory outperforms...

  15. Hardware support for collecting performance counters directly to memory

    Science.gov (United States)

    Gara, Alan; Salapura, Valentina; Wisniewski, Robert W.

    2012-09-25

    Hardware support for collecting performance counters directly to memory, in one aspect, may include a plurality of performance counters operable to collect one or more counts of one or more selected activities. A first storage element may be operable to store an address of a memory location. A second storage element may be operable to store a value indicating whether the hardware should begin copying. A state machine may be operable to detect the value in the second storage element and trigger hardware copying of data in selected one or more of the plurality of performance counters to the memory location whose address is stored in the first storage element.

  16. Hardware Implementation of Serially Concatenated PPM Decoder

    Science.gov (United States)

    Moision, Bruce; Hamkins, Jon; Barsoum, Maged; Cheng, Michael; Nakashima, Michael

    2009-01-01

    A prototype decoder for a serially concatenated pulse position modulation (SCPPM) code has been implemented in a field-programmable gate array (FPGA). At the time of this reporting, this is the first known hardware SCPPM decoder. The SCPPM coding scheme, conceived for free-space optical communications with both deep-space and terrestrial applications in mind, is an improvement of several dB over the conventional Reed-Solomon PPM scheme. The design of the FPGA SCPPM decoder is based on a turbo decoding algorithm that requires relatively low computational complexity while delivering error-rate performance within approximately 1 dB of channel capacity. The SCPPM encoder consists of an outer convolutional encoder, an interleaver, an accumulator, and an inner modulation encoder (more precisely, a mapping of bits to PPM symbols). Each code is describable by a trellis (a finite directed graph). The SCPPM decoder consists of an inner soft-in-soft-out (SISO) module, a de-interleaver, an outer SISO module, and an interleaver connected in a loop (see figure). Each SISO module applies the Bahl-Cocke-Jelinek-Raviv (BCJR) algorithm to compute a-posteriori bit log-likelihood ratios (LLRs) from apriori LLRs by traversing the code trellis in forward and backward directions. The SISO modules iteratively refine the LLRs by passing the estimates between one another much like the working of a turbine engine. Extrinsic information (the difference between the a-posteriori and a-priori LLRs) is exchanged rather than the a-posteriori LLRs to minimize undesired feedback. All computations are performed in the logarithmic domain, wherein multiplications are translated into additions, thereby reducing complexity and sensitivity to fixed-point implementation roundoff errors. To lower the required memory for storing channel likelihood data and the amounts of data transfer between the decoder and the receiver, one can discard the majority of channel likelihoods, using only the remainder in

  17. Hardware Implementation of a Bilateral Subtraction Filter

    Science.gov (United States)

    Huertas, Andres; Watson, Robert; Villalpando, Carlos; Goldberg, Steven

    2009-01-01

    A bilateral subtraction filter has been implemented as a hardware module in the form of a field-programmable gate array (FPGA). In general, a bilateral subtraction filter is a key subsystem of a high-quality stereoscopic machine vision system that utilizes images that are large and/or dense. Bilateral subtraction filters have been implemented in software on general-purpose computers, but the processing speeds attainable in this way even on computers containing the fastest processors are insufficient for real-time applications. The present FPGA bilateral subtraction filter is intended to accelerate processing to real-time speed and to be a prototype of a link in a stereoscopic-machine- vision processing chain, now under development, that would process large and/or dense images in real time and would be implemented in an FPGA. In terms that are necessarily oversimplified for the sake of brevity, a bilateral subtraction filter is a smoothing, edge-preserving filter for suppressing low-frequency noise. The filter operation amounts to replacing the value for each pixel with a weighted average of the values of that pixel and the neighboring pixels in a predefined neighborhood or window (e.g., a 9 9 window). The filter weights depend partly on pixel values and partly on the window size. The present FPGA implementation of a bilateral subtraction filter utilizes a 9 9 window. This implementation was designed to take advantage of the ability to do many of the component computations in parallel pipelines to enable processing of image data at the rate at which they are generated. The filter can be considered to be divided into the following parts (see figure): a) An image pixel pipeline with a 9 9- pixel window generator, b) An array of processing elements; c) An adder tree; d) A smoothing-and-delaying unit; and e) A subtraction unit. After each 9 9 window is created, the affected pixel data are fed to the processing elements. Each processing element is fed the pixel value for

  18. Tolerance Stack Analysis in Francis Turbine Design

    Directory of Open Access Journals (Sweden)

    Indra Djodikusumo

    2010-05-01

    Full Text Available The tolerance stacking problem arises in the context of assemblies from interchangeable parts because of the inability to produce or to join parts exactly according to nominal dimensions. Either the relevant part’s dimension varies around some nominal values from part to part or the act of assembly that leads to variation. For example, as runner of Francis turbine is joined with turbine shaft via mechanical lock, there is not only variation in the diameter of runner and the concentricity between the runner hole and turbine shaft, but also the variation in concentricity between the outer parts of runner to runner hole. Thus, there is the possibility that the assembly of such interacting parts won’t function or won’t come together as planned. Research in this area has been conducted and 2 mini hydro Francis turbines (800 kW and 910 kW have been designed and manufactured for San Sarino and Sawi Dago 2 in Central Sulawesi. Experiences in analyzing the tolerance stacks have been documented. In this paper it will be demonstrated how the requirements of assembling performance are derived to be the designed tolerances of each interacting component, such a way that the assembling would be functioning and come together as planned.

  19. PBFA-2 vacuum insulator stack failure mechanisms

    Science.gov (United States)

    Sweeney, M. A.

    The BPFA-II accelerator includes a large-radius, vertical-axis vacuum insulator stack. The possible failure of the acrylic rings in the stack from electron- or gamma-induced charge buildup is being evaluated. The induced static charges could remain for many hours, and either type of irradiation might cause dendrites to form. Aluminum grading rings sandwiched between the acrylic affect charge accumulation; the acrylic would preferentially break down to these grading rings. The charge buildup and the bremsstrahlung dose could depend critically upon the directionality and position of the electron loss. The effects of electron loss that occurs in the vicinity of the ion diode, where the electrons have energies of about 30 MeV are considered. Monte Carlo electron-photon transport calculations indicate that the bremsstrahlung dose expected in an acrylic ring once diode experiments begin in 1986 could be as much as 5 krads per shot, with roughly half of the photon energy above 5 MeV. Moreover, the calculation indicate that the charge deposition in an individual acrylic ring might exceed 2x10 to the 11 electrons/sq cm.

  20. Stacking interactions and the twist of DNA

    DEFF Research Database (Denmark)

    Cooper, V.R.; Thonhauser, T.; Puzder, A.;

    2008-01-01

    The importance of stacking interactions for the Twist and stability of DNA is investigated using the fully ab initio van der Waals density functional (vdW-DF).(1,2) Our results highlight the role that binary interactions between adjacent sets of base pairs play in defining the sequence-dependent ......The importance of stacking interactions for the Twist and stability of DNA is investigated using the fully ab initio van der Waals density functional (vdW-DF).(1,2) Our results highlight the role that binary interactions between adjacent sets of base pairs play in defining the sequence......-dependent Twists observed in high-resolution experiments. Furthermore, they demonstrate that additional stability gained by the presence of thymine is due to methyl interactions with neighboring bases, thus adding to our understanding of the mechanisms that contribute to the relative stability of DNA and RNA. Our...... mapping of the energy required to twist each of the 10 unique base pair steps should provide valuable information for future studies of nucleic acid stability and dynamics. The method introduced will enable the nonempirical theoretical study of significantly larger pieces of DNA or DNA/amino acid...

  1. High performance zinc air fuel cell stack

    Science.gov (United States)

    Pei, Pucheng; Ma, Ze; Wang, Keliang; Wang, Xizhong; Song, Mancun; Xu, Huachi

    2014-03-01

    A zinc air fuel cell (ZAFC) stack with inexpensive manganese dioxide (MnO2) as the catalyst is designed, in which the circulation flowing potassium hydroxide (KOH) electrolyte carries the reaction product away and acts as a coolant. Experiments are carried out to investigate the characteristics of polarization, constant current discharge and dynamic response, as well as the factors affecting the performance and uniformity of individual cells in the stack. The results reveal that the peak power density can be as high as 435 mW cm-2 according to the area of the air cathode sheet, and the influence factors on cell performance and uniformity are cell locations, filled state of zinc pellets, contact resistance, flow rates of electrolyte and air. It is also shown that the time needed for voltages to reach steady state and that for current step-up or current step-down are both in milliseconds, indicating the ZAFC can be excellently applied to vehicles with rapid dynamic response demands.

  2. OpenMM: A Hardware Independent Framework for Molecular Simulations

    OpenAIRE

    Eastman, Peter; Pande, Vijay S.

    2010-01-01

    The wide diversity of computer architectures today requires a new approach to software development. OpenMM is a framework for molecular mechanics simulations, allowing a single program to run efficiently on a variety of hardware platforms.

  3. Hardware problems encountered in solar heating and cooling systems

    Science.gov (United States)

    Cash, M.

    1978-01-01

    Numerous problems in the design, production, installation, and operation of solar energy systems are discussed. Described are hardware problems, which range from simple to obscure and complex, and their resolution.

  4. Hardware Transactional Memory Optimization Guidelines, Applied to Ordered Maps

    DEFF Research Database (Denmark)

    Bonnichsen, Lars Frydendal; Probst, Christian W.; Karlsson, Sven

    2015-01-01

    synchronization method scales well. Recently, hardware transactional memory was introduced, which allows threads to use transactions instead of locks. So far, applying hardware transactional memory has shown mixed results. We believe this is because transactions are different from locks, and using them...... efficiently requires reasoning about those differences. In this paper we present 5 guidelines for applying hardware transactional memory efficiently, and apply the guidelines to BT-trees, a concurrent ordered map. Evaluating BT-trees on standard benchmarks shows that they are up to 5.3 times faster than...... traditional maps using hardware transactional memory, and up to 3.9 times faster than state of the art concurrent ordered maps....

  5. Hardware device to physical structure binding and authentication

    Science.gov (United States)

    Hamlet, Jason R.; Stein, David J.; Bauer, Todd M.

    2013-08-20

    Detection and deterrence of device tampering and subversion may be achieved by including a cryptographic fingerprint unit within a hardware device for authenticating a binding of the hardware device and a physical structure. The cryptographic fingerprint unit includes an internal physically unclonable function ("PUF") circuit disposed in or on the hardware device, which generate an internal PUF value. Binding logic is coupled to receive the internal PUF value, as well as an external PUF value associated with the physical structure, and generates a binding PUF value, which represents the binding of the hardware device and the physical structure. The cryptographic fingerprint unit also includes a cryptographic unit that uses the binding PUF value to allow a challenger to authenticate the binding.

  6. Hardware Abstraction and Protocol Optimization for Coded Sensor Networks

    DEFF Research Database (Denmark)

    Nistor, Maricica; Roetter, Daniel Enrique Lucani; Barros, João

    2015-01-01

    The design of the communication protocols in wireless sensor networks (WSNs) often neglects several key characteristics of the sensor's hardware, while assuming that the number of transmitted bits is the dominating factor behind the system's energy consumption. A closer look at the hardware...... specifications of common sensors reveals, however, that other equally important culprits exist, such as the reception and processing energy. Hence, there is a need for a more complete hardware abstraction of a sensor node to reduce effectively the total energy consumption of the network by designing energy...... platforms, the use of relays may decrease up to 4.5 times the total energy consumption when the protocol and the hardware are carefully matched. We conclude that: 1) the energy budget for a communication protocol varies significantly on different sensor platforms; and 2) the protocols can be judiciously...

  7. Hardware Virtualization Support In INTEL, AMD And IBM Power Processors

    CERN Document Server

    Biswas, Kamanashis

    2009-01-01

    At present, the mostly used and developed mechanism is hardware virtualization which provides a common platform to run multiple operating systems and applications in independent partitions. More precisely, it is all about resource virtualization as the term hardware virtualization is emphasized. In this paper, the aim is to find out the advantages and limitations of current virtualization techniques, analyze their cost and performance and also depict which forthcoming hardware virtualization techniques will able to provide efficient solutions for multiprocessor operating systems. This is done by making a methodical literature survey and statistical analysis of the benchmark reports provided by SPEC (Standard Performance Evaluation Corporation) and TPC (Transaction processing Performance Council). Finally, this paper presents the current aspects of hardware virtualization which will help the IT managers of the large organizations to take effective decision while choosing server with virtualization support. Aga...

  8. New Model and Algorithm for Hardware/Software Partitioning

    Institute of Scientific and Technical Information of China (English)

    Ji-Gang Wu; Thambipillai Srikanthan; Guang-Wei Zou

    2008-01-01

    This paper focuses on the algorithmic aspects for the hardware/software (HW/SW) partitioning which searches a reasonable composition of hardware and software components which not only satisfies the constraint of hardware area but also optimizes the execution time. The computational model is extended so that all possible types of communications can be taken into account for the HW/SW partitioning. Also, a new dynamic programming algorithm is proposed on the basis of the computational model, in which source data, rather than speedup in previous work, of basic scheduling blocks are directly utilized to calculate the optimal solution. The proposed algorithm runs in O(n. A) for n code fragments and the available hardware area A. Simulation results show that the proposed algorithm solves the HW/SW partitioning without increase in running time, compared with the algorithm cited in the literature.

  9. Hardware Implementation Of Line Clipping A lgorithm By Using FPGA

    Directory of Open Access Journals (Sweden)

    Amar Dawod

    2013-04-01

    Full Text Available The computer graphics system performance is increasing faster than any other computing application. Algorithms for line clipping against convex polygons and lines have been studied for a long time and many research papers have been published so far. In spite of the latest graphical hardware development and significant increase of performance the clipping is still a bottleneck of any graphical system. So its implementation in hardware is essential for real time applications. In this paper clipping operation is discussed and a hardware implementation of the line clipping algorithm is presented and finally formulated and tested using Field Programmable Gate Arrays (FPGA. The designed hardware unit consists of two parts : the first is positional code generator unit and the second is the clipping unit. Finally it is worth mentioning that the  designed unit is capable of clipping (232524 line segments per second.       

  10. IT Career JumpStart An Introduction to PC Hardware, Software, and Networking

    CERN Document Server

    Alpern, Naomi J; Muller, Randy

    2011-01-01

    A practical approach for anyone looking to enter the IT workforce Before candidates can begin to prepare for any kind of certification, they need a basic understanding of the various hardware and software components used in a computer network. Aimed at aspiring IT professionals, this invaluable book strips down a network to its bare basics, and discusses this complex topic in a clear and concise manner so that IT beginners can confidently gain an understanding of fundamental IT concepts. In addition, a base knowledge has been established so that more advanced topics and technologies can be lea

  11. Design of a Hardware Track Finder (Fast Tracker) for the ATLAS Trigger

    CERN Document Server

    Volpi, G; The ATLAS collaboration

    2013-01-01

    The ATLAS Fast TracKer is a custom electronics system that will operate at the full Level-1 accept rate, 100 kHz, to provide high quality tracks as input to the Level-2 trigger. The event reconstruction is performed in hardware, thanks to the massive parallelism of associative memories (AM) and FPGAs. We present the advantages for the physics goals of the ATLAS experiment and the recent results on the design, technological advancements and testing of some of the core components used in the processor.

  12. Simple Stacking Methods for Silicon Micro Fuel Cells

    Directory of Open Access Journals (Sweden)

    Gianmario Scotti

    2014-08-01

    Full Text Available We present two simple methods, with parallel and serial gas flows, for the stacking of microfabricated silicon fuel cells with integrated current collectors, flow fields and gas diffusion layers. The gas diffusion layer is implemented using black silicon. In the two stacking methods proposed in this work, the fluidic apertures and gas flow topology are rotationally symmetric and enable us to stack fuel cells without an increase in the number of electrical or fluidic ports or interconnects. Thanks to this simplicity and the structural compactness of each cell, the obtained stacks are very thin (~1.6 mm for a two-cell stack. We have fabricated two-cell stacks with two different gas flow topologies and obtained an open-circuit voltage (OCV of 1.6 V and a power density of 63 mW·cm−2, proving the viability of the design.

  13. Description of gasket failure in a 7 cell PEMFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Husar, Attila; Serra, Maria [Institut de Robotica i Informatica Industrial, Parc Tecnologic de Barcelona, Edifici U, C. Llorens i Artigas, 4-6, 2a Planta, 08028 Barcelona (Spain); Kunusch, Cristian [Laboratorio de Electronica Industrial Control e Instrumentacion, Facultad de Ingenieria, UNLP (Argentina)

    2007-06-10

    This article presents the data and the description of a fuel cell stack that failed due to gasket degradation. The fuel cell under study is a 7 cell stack. The unexpected change in several variables such as temperature, pressure and voltage indicated the possible failure of the stack. The stack was monitored over a 6 h period in which data was collected and consequently analyzed to conclude that the fuel cell stack failed due to a crossover leak on the anode inlet port located on the cathode side gasket of cell 2. This stack failure analysis revealed a series of indicators that could be used by a super visional controller in order to initiate a shutdown procedure. (author)

  14. Cloud Computing with Open Source Tool :OpenStack

    Directory of Open Access Journals (Sweden)

    Dr. Urmila R. Pol

    2014-09-01

    Full Text Available OpenStack is a especially scalable open source cloud operating system that is a global alliance of developers and cloud computing technologists producing the ubiquitous open source cloud computing platform for public and private clouds. OpenStack provides series of interrelated projects delivering various components for a cloud infrastructure solution as well as controls large pools of storage, compute and networking resources throughout a datacenter that all managed through a Dashboard(Horizon that gives administrators control while empowering their users to provision resources through a web interface.In this paper, we present a overview of Cloud Computing Platform such as, Openstack, Eucalyptus ,CloudStack and Opennebula which is open source software, cloud computing layered model, components of OpenStack, architecture of OpenStack. The aim of this paper is to show mainly importance of OpenStack as a Cloud provider and its installation.

  15. Top Down Approach: SIMULINK Mixed Hardware / Software Design

    Directory of Open Access Journals (Sweden)

    Youssef Atat

    2012-05-01

    Full Text Available System-level design methodologies have been introduced as a solution to handle the design complexity of mixed Hardware / Software systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: System Simulink model, Transaction Simulink model, Macro architecture, and micro architecture. We used the MP3 CodeC application, to validate our approach and methodology.

  16. Using software and hardware neural networks in a Higgs search

    International Nuclear Information System (INIS)

    The present investigation uses information from computer simulations to train neural networks to identify decays of heavy Higgs particles (mH>>mZ). Results are presented both for software and hardware analog neural networks. The hardware tests include the Intel ETANN and the CLNN32/CLNS64 (experimental, research prototype developed at Bellcore) chip-set implemented in VME-modules. The processing and learning times for the networks are discussed. ((orig.))

  17. Mitigating Hardware Cyber-Security Risks in Error Correcting Decoders

    OpenAIRE

    Hemati, Saied

    2015-01-01

    This paper investigates hardware cyber-security risks associated with channel decoders, which are commonly acquired as a black box in semiconductor industry. It is shown that channel decoders are potentially attractive targets for hardware cyber-security attacks and can be easily embedded with malicious blocks. Several attack scenarios are considered in this work and suitable methods for mitigating the risks are proposed. These methods are based on randomizing the inputs of the channel decode...

  18. Computer generated holography using parallel commodity graphics hardware

    OpenAIRE

    Ahrenberg, Lukas; Benzie, Philip; Magnor, Marcus; Watson, John

    2006-01-01

    This paper presents a novel method for using programmable graphics hardware to generate fringe patterns for SLM-based holographic displays. The algorithm is designed to take the programming constraints imposed by the graphics hardware pipeline model into consideration, and scales linearly with the number of object points. In contrast to previous methods we do not have to use the Fresnel approximation. The technique can also be used on several graphics processors in p...

  19. Hardware Evolution of Closed-Loop Controller Designs

    Science.gov (United States)

    Gwaltney, David; Ferguson, Ian

    2002-01-01

    Poster presentation will outline on-going efforts at NASA, MSFC to employ various Evolvable Hardware experimental platforms in the evolution of digital and analog circuitry for application to automatic control. Included will be information concerning the application of commercially available hardware and software along with the use of the JPL developed FPTA2 integrated circuit and supporting JPL developed software. Results to date will be presented.

  20. SNL/NM weapon hardware characterization process development report

    Energy Technology Data Exchange (ETDEWEB)

    Graff, E.W.; Chambers, W.B.

    1995-01-01

    This report describes the process used by Sandia National Laboratories, New Mexico to characterize weapon hardware for disposition. The report describes the following basic steps: (1) the drawing search process and primary hazard identification; (2) the development of Disassembly Procedures (DPs), including demilitarization and sanitization requirements; (3) the generation of a ``disposal tree``; (4) generating RCRA waste disposal information; and (5) documenting the information. Additional data gathered during the characterization process supporting hardware grouping and recycle efforts is also discussed.

  1. Smartphone’s Hardware Architectures and Their Issues

    OpenAIRE

    Rohit Kumar; Lokesh Pawar

    2014-01-01

    Smart phones provides us the capability of a typical computer with absolute mobility and small form factor. But the hardware architecture of smart phone is significantly different from the conventional hardware architectures. The feature and architecture of the processors is totally different the traditional processor as these processors are developed to cope-up with fewer energy availability with smart phones or any other ultra portable devices.

  2. Top Down Approach: SIMULINK Mixed Hardware / Software Design

    OpenAIRE

    Youssef Atat; Mostafa Rizk

    2012-01-01

    System-level design methodologies have been introduced as a solution to handle the design complexity of mixed Hardware / Software systems. In this paper we describe a system-level design flow starting from Simulink specification, focusing on concurrent hardware and software design and verification at four different abstraction levels: System Simulink model, Transaction Simulink model, Macro architecture, and micro architecture. We used the MP3 CodeC application, to validate our approach and m...

  3. A Programmable Hardware Cellular Automaton: Example of Data Flow Transformation

    OpenAIRE

    Samuel Charbouillot; Annie Pérez; Daniele Fronte

    2008-01-01

    We present an IP-core called PHCA which stands for programmable hardware cellular automaton. PHCA is a hardware implementation of a general purpose cellular automaton (CA) entirely programmable. The heart of this structure is a PE array with reconfigurable side links allowing the implementation of a 2D CA or a 1D CA. As an illustration of a PHCA program, we present the implementation of a symmetric cryptography algorithm called ISEA for Ising spin encryption algorithm. Indeed ISEA is based on...

  4. Energy-efficient and security-optimized AES hardware design for ubiquitous computing

    Institute of Scientific and Technical Information of China (English)

    Chen Yicheng; Zou Xuecheng; Liu Zhenglin; Han Yu; Zheng Zhaoxia

    2008-01-01

    Ubiquitous computing must incorporate a certain level of security.For the severely resource con-strained applications,the energy-efficient and small size cryptography algorithm implementation is a critical problem.Hardware implementations of the advanced encryption standard(AES)for authentication and encryption are presented.An energy consumption variable is derived to evaluate low-power design strategies for battery-powered devices.It proves that compact AES architectures fail to optimize the AES hardware energy,whereas reducing invalid switching activities and implementing power-optimized sub-modules are the reasonable methods.Implemen tations of different substitution box(S-Boxes)structures are presented with 0.25 μm 1.8 V CMOS(complementary metal oxide semiconductor)standard cell library.The comparisons and trade-offs among area,security,and power are explored.The experimental results show that Galois field composite S-Boxes have smaller size and higheat security but consume considerably more power,whereas decoder-switch-encoder S-Boxes have the best power characteristics with disadvantages in terms of size and security.The combination of these two type S-Boxes instead of homogeneous S-Boxes in AES circuit will lead to optimal schemes.The technique of latch-dividing data path is analyzed,and the quantitative simulation results demonstrate that this approach diminishes the glitches effectively at a very low hardware cost.

  5. A Principled Kernel Testbed for Hardware/Software Co-Design Research

    Energy Technology Data Exchange (ETDEWEB)

    Kaiser, Alex; Williams, Samuel; Madduri, Kamesh; Ibrahim, Khaled; Bailey, David; Demmel, James; Strohmaier, Erich

    2010-04-01

    Recently, advances in processor architecture have become the driving force for new programming models in the computing industry, as ever newer multicore processor designs with increasing number of cores are introduced on schedules regimented by marketing demands. As a result, collaborative parallel (rather than simply concurrent) implementations of important applications, programming languages, models, and even algorithms have been forced to adapt to these architectures to exploit the available raw performance. We believe that this optimization regime is flawed. In this paper, we present an alternate approach that, rather than starting with an existing hardware/software solution laced with hidden assumptions, defines the computational problems of interest and invites architects, researchers and programmers to implement novel hardware/software co-designed solutions. Our work builds on the previous ideas of computational dwarfs, motifs, and parallel patterns by selecting a representative set of essential problems for which we provide: An algorithmic description; scalable problem definition; illustrative reference implementations; verification schemes. This testbed will enable comparative research in areas such as parallel programming models, languages, auto-tuning, and hardware/software codesign. For simplicity, we focus initially on the computational problems of interest to the scientific computing community but proclaim the methodology (and perhaps a subset of the problems) as applicable to other communities. We intend to broaden the coverage of this problem space through stronger community involvement.

  6. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Bauce, Matteo; Dankel, Maik; Howard, Jacob; Kama, Sami

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. These data are processed by in-house built software frameworks which have lifetimes longer than the detector itself. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to parallel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software framework called Athena. In this talk we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline reconstruction as well as their integration into a multiple process based Athena frame...

  7. Use of hardware accelerators for ATLAS computing

    CERN Document Server

    Dankel, Maik; The ATLAS collaboration; Howard, Jacob; Bauce, Matteo; Boing, Rene

    2015-01-01

    Modern HEP experiments produce tremendous amounts of data. This data is processed by in-house built software frameworks which have lifetimes longer than the detector it- self. Such frameworks were traditionally based on serial code and relied on advances in CPU technologies, mainly clock frequency, to cope with increasing data volumes. With the advent of many-core architectures and GPGPUs this paradigm has to shift to paral- lel processing and has to include the use of co-processors. However, since the design of most existing frameworks is based on the assumption of frequency scaling and predate co-processors, parallelisation and integration of co-processors are not an easy task. The ATLAS experiment is an example of such a big experiment with a big software frame- work called Athena. In this proceedings we will present the studies on parallelisation and co-processor (GPGPU) use in data preparation and tracking for trigger and offline recon- struction as well as their integration into a multiple process based...

  8. Fundamentals of GPS Receivers A Hardware Approach

    CERN Document Server

    Doberstein, Dan

    2012-01-01

    While much of the current literature on GPS receivers is aimed at those intimately familiar with their workings, this volume summarizes the basic principles using as little mathematics as possible, and details the necessary specifications and circuits for constructing a GPS receiver that is accurate to within 300 meters. Dedicated sections deal with the features of the GPS signal and its data stream, the details of the receiver (using a hybrid design as exemplar), and more advanced receivers and topics including time and frequency measurements. Later segments discuss the Zarlink GPS receiver chip set, as well as providing a thorough examination of the TurboRogue receiver, one of the most accurate yet made. Guiding the reader through the concepts and circuitry, from the antenna to the solution of user position, the book’s deployment of a hybrid receiver as a basis for discussion allows for extrapolation of the core ideas to more complex, and more accurate designs. Digital methods are used, but any analogue c...

  9. Compact bipolar plate-free direct methanol fuel cell stacks.

    Science.gov (United States)

    Dong, Xue; Takahashi, Motohiro; Nagao, Masahiro; Hibino, Takashi

    2011-05-14

    Fuel cells with a PtAu/C anode and a Pr-doped Mn(2)O(3)/C cathode were stacked without using a bipolar plate, and their discharge properties were investigated in a methanol aqueous solution bubbled with air. A three-cell stack exhibited a stack voltage of 2330 mV and a power output of 21 mW. PMID:21451850

  10. Solid oxide cell stack and method for preparing same

    DEFF Research Database (Denmark)

    2012-01-01

    A method for producing and reactivating a solid oxide cell stack structure by providing a catalyst precursor in at least one of the electrode layers by impregnation and subsequent drying after the stack has been assembled and initiated. Due to a significantly improved performance and an unexpecte...... voltage improvement this solid oxide cell stack structure is particularly suitable for use in solid oxide fuel cell (SOFC) and solid oxide electrolysing cell (SOEC) applications....

  11. Development of the electric utility dispersed use PAFC stack

    Energy Technology Data Exchange (ETDEWEB)

    Horiuchi, Hiroshi; Kotani, Ikuo [Mitsubishi Electric Co., Kobe (Japan); Morotomi, Isamu [Kansai Electric Power Co., Hyogo (Japan)] [and others

    1996-12-31

    Kansai Electric Power Co. and Mitsubishi Electric Co. have been developing the electric utility dispersed use PAFC stack operated under the ambient pressure. The new cell design have been developed, so that the large scale cell (1 m{sup 2} size) was adopted for the stack. To confirm the performance and the stability of the 1 m{sup 2} scale cell design, the short stack study had been performed.

  12. Stacked Heterogeneous Neural Networks for Time Series Forecasting

    Directory of Open Access Journals (Sweden)

    Florin Leon

    2010-01-01

    Full Text Available A hybrid model for time series forecasting is proposed. It is a stacked neural network, containing one normal multilayer perceptron with bipolar sigmoid activation functions, and the other with an exponential activation function in the output layer. As shown by the case studies, the proposed stacked hybrid neural model performs well on a variety of benchmark time series. The combination of weights of the two stack components that leads to optimal performance is also studied.

  13. On the use of inexact, pruned hardware in atmospheric modelling.

    Science.gov (United States)

    Düben, Peter D; Joven, Jaume; Lingamneni, Avinash; McNamara, Hugh; De Micheli, Giovanni; Palem, Krishna V; Palmer, T N

    2014-06-28

    Inexact hardware design, which advocates trading the accuracy of computations in exchange for significant savings in area, power and/or performance of computing hardware, has received increasing prominence in several error-tolerant application domains, particularly those involving perceptual or statistical end-users. In this paper, we evaluate inexact hardware for its applicability in weather and climate modelling. We expand previous studies on inexact techniques, in particular probabilistic pruning, to floating point arithmetic units and derive several simulated set-ups of pruned hardware with reasonable levels of error for applications in atmospheric modelling. The set-up is tested on the Lorenz '96 model, a toy model for atmospheric dynamics, using software emulation for the proposed hardware. The results show that large parts of the computation tolerate the use of pruned hardware blocks without major changes in the quality of short- and long-time diagnostics, such as forecast errors and probability density functions. This could open the door to significant savings in computational cost and to higher resolution simulations with weather and climate models.

  14. Complexity of the FIFO Stack-Up Problem

    OpenAIRE

    Gurski, Frank; Rethmann, Jochen; Wanke, Egon

    2013-01-01

    We study the combinatorial FIFO stack-up problem. In delivery industry, bins have to be stacked-up from conveyor belts onto pallets with respect to customer orders. Given k sequences q_1, ..., q_k of labeled bins and a positive integer p, the aim is to stack-up the bins by iteratively removing the first bin of one of the k sequences and put it onto an initially empty pallet of unbounded capacity located at one of p stack-up places. Bins with different pallet labels have to be placed on differ...

  15. An Enhanced Hardware Description Language Implementation for Improved Design-Space Exploration in High-Energy Physics Hardware Design

    CERN Document Server

    Mücke, M; Jacobsson, R

    2007-01-01

    Detectors in High-Energy Physics (HEP) have increased tremendously in accuracy, speed and integration. Consequently HEP experiments are confronted with an immense amount of data to be read out, processed and stored. Originally low-level processing has been accomplished in hardware, while more elaborate algorithms have been executed on large computing farms. Field-Programmable Gate Arrays (FPGAs) meet HEP's need for ever higher real-time processing performance by providing programmable yet fast digital logic resources. With the fast move from HEP Digital Signal Processing (DSPing) applications into the domain of FPGAs, related design tools are crucial to realise the potential performance gains. This work reviews Hardware Description Languages (HDLs) in respect to the special needs present in the HEP digital hardware design process. It is especially concerned with the question, how features outside the scope of mainstream digital hardware design can be implemented efficiently into HDLs. It will argue that funct...

  16. Dynamic provisioning of local and remote compute resources with OpenStack

    Science.gov (United States)

    Giffels, M.; Hauth, T.; Polgart, F.; Quast, G.

    2015-12-01

    Modern high-energy physics experiments rely on the extensive usage of computing resources, both for the reconstruction of measured events as well as for Monte-Carlo simulation. The Institut fur Experimentelle Kernphysik (EKP) at KIT is participating in both the CMS and Belle experiments with computing and storage resources. In the upcoming years, these requirements are expected to increase due to growing amount of recorded data and the rise in complexity of the simulated events. It is therefore essential to increase the available computing capabilities by tapping into all resource pools. At the EKP institute, powerful desktop machines are available to users. Due to the multi-core nature of modern CPUs, vast amounts of CPU time are not utilized by common desktop usage patterns. Other important providers of compute capabilities are classical HPC data centers at universities or national research centers. Due to the shared nature of these installations, the standardized software stack required by HEP applications cannot be installed. A viable way to overcome this constraint and offer a standardized software environment in a transparent manner is the usage of virtualization technologies. The OpenStack project has become a widely adopted solution to virtualize hardware and offer additional services like storage and virtual machine management. This contribution will report on the incorporation of the institute's desktop machines into a private OpenStack Cloud. The additional compute resources provisioned via the virtual machines have been used for Monte-Carlo simulation and data analysis. Furthermore, a concept to integrate shared, remote HPC centers into regular HEP job workflows will be presented. In this approach, local and remote resources are merged to form a uniform, virtual compute cluster with a single point-of-entry for the user. Evaluations of the performance and stability of this setup and operational experiences will be discussed.

  17. Review of Maxillofacial Hardware Complications and Indications for Salvage.

    Science.gov (United States)

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L; Sanati-Mehrizy, Paymon; Factor, Stephanie H; Taub, Peter J

    2016-06-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances when hardware may be salvaged. Articles considered for inclusion were found in the PubMed and Web of Science databases in August 2014 with the keywords maxillofacial trauma AND hardware complications OR indications for hardware removal. Included studies looked at human patients with only facial trauma and miniplate fixation, and presented data on complications and/or hardware removal. Fifteen articles were included. None were clinical trials. Complication data were presented by patient, fractures, and/or plate without consistency. The data described 1,075 fractures, 2,961 patients, and 2,592 plates, nonexclusive. Complication rates varied from 6 to 8% by fracture and 6 to 13% by patient. When their data were combined, 50% of complications were treated with plate removal; this was consistent across the mandible, midface, and upper face. All complications caused by loosening, nonunion, broken hardware, and severe/prolonged pain were treated with removal. Some complications caused by exposures, deformities, and infections were treated with salvage. Exposed plates were treated with flaps, plates with deformities were treated with secondary procedures including hardware revision, and hardware infections were treated with antibiotics alone or in conjunction with soft-tissue debridement and/or tooth extraction. Well-designed clinical trials evaluating hardware removal versus salvage are lacking. Some postoperative complications caused by exposure, deformity, and/or infection may be

  18. Review of Maxillofacial Hardware Complications and Indications for Salvage.

    Science.gov (United States)

    Hernandez Rosa, Jonatan; Villanueva, Nathaniel L; Sanati-Mehrizy, Paymon; Factor, Stephanie H; Taub, Peter J

    2016-06-01

    From 2002 to 2006, more than 117,000 facial fractures were recorded in the U.S. National Trauma Database. These fractures are commonly treated with open reduction and internal fixation. While in place, the hardware facilitates successful bony union. However, when postoperative complications occur, the plates may require removal before bony union. Indications for salvage versus removal of the maxillofacial hardware are not well defined. A literature review was performed to identify instances when hardware may be salvaged. Articles considered for inclusion were found in the PubMed and Web of Science databases in August 2014 with the keywords maxillofacial trauma AND hardware complications OR indications for hardware removal. Included studies looked at human patients with only facial trauma and miniplate fixation, and presented data on complications and/or hardware removal. Fifteen articles were included. None were clinical trials. Complication data were presented by patient, fractures, and/or plate without consistency. The data described 1,075 fractures, 2,961 patients, and 2,592 plates, nonexclusive. Complication rates varied from 6 to 8% by fracture and 6 to 13% by patient. When their data were combined, 50% of complications were treated with plate removal; this was consistent across the mandible, midface, and upper face. All complications caused by loosening, nonunion, broken hardware, and severe/prolonged pain were treated with removal. Some complications caused by exposures, deformities, and infections were treated with salvage. Exposed plates were treated with flaps, plates with deformities were treated with secondary procedures including hardware revision, and hardware infections were treated with antibiotics alone or in conjunction with soft-tissue debridement and/or tooth extraction. Well-designed clinical trials evaluating hardware removal versus salvage are lacking. Some postoperative complications caused by exposure, deformity, and/or infection may be

  19. Rapid Feature Learning with Stacked Linear Denoisers

    CERN Document Server

    Xu, Zhixiang Eddie; Sha, Fei

    2011-01-01

    We investigate unsupervised pre-training of deep architectures as feature generators for "shallow" classifiers. Stacked Denoising Autoencoders (SdA), when used as feature pre-processing tools for SVM classification, can lead to significant improvements in accuracy - however, at the price of a substantial increase in computational cost. In this paper we create a simple algorithm which mimics the layer by layer training of SdAs. However, in contrast to SdAs, our algorithm requires no training through gradient descent as the parameters can be computed in closed-form. It can be implemented in less than 20 lines of MATLABTMand reduces the computation time from several hours to mere seconds. We show that our feature transformation reliably improves the results of SVM classification significantly on all our data sets - often outperforming SdAs and even deep neural networks in three out of four deep learning benchmarks.

  20. GRB neutrino detection via time profile stacking

    CERN Document Server

    van Eijndhoven, Nick

    2007-01-01

    A method is presented for the identification of high-energy neutrinos from gamma ray bursts by means of a large-scale neutrino telescope. The procedure makes use of a time profile stacking technique of observed neutrino induced signals in correlation with satellite observations. By selecting a rather wide time window, a possible difference between the arrival times of the gamma and neutrino signals may also be identified. This might provide insight in the particle production processes at the source. By means of a toy model it will be demonstrated that a statistically significant signal can be obtained with a km$^{3}$-scale neutrino telescope on a sample of 500 gamma ray bursts for a signal rate as low as 1 detectable neutrino for 3% of the bursts.

  1. Stacking the odds for Golgi cisternal maturation.

    Science.gov (United States)

    Mani, Somya; Thattai, Mukund

    2016-01-01

    What is the minimal set of cell-biological ingredients needed to generate a Golgi apparatus? The compositions of eukaryotic organelles arise through a process of molecular exchange via vesicle traffic. Here we statistically sample tens of thousands of homeostatic vesicle traffic networks generated by realistic molecular rules governing vesicle budding and fusion. Remarkably, the plurality of these networks contain chains of compartments that undergo creation, compositional maturation, and dissipation, coupled by molecular recycling along retrograde vesicles. This motif precisely matches the cisternal maturation model of the Golgi, which was developed to explain many observed aspects of the eukaryotic secretory pathway. In our analysis cisternal maturation is a robust consequence of vesicle traffic homeostasis, independent of the underlying details of molecular interactions or spatial stacking. This architecture may have been exapted rather than selected for its role in the secretion of large cargo. PMID:27542195

  2. Stacking the odds for Golgi cisternal maturation.

    Science.gov (United States)

    Mani, Somya; Thattai, Mukund

    2016-01-01

    What is the minimal set of cell-biological ingredients needed to generate a Golgi apparatus? The compositions of eukaryotic organelles arise through a process of molecular exchange via vesicle traffic. Here we statistically sample tens of thousands of homeostatic vesicle traffic networks generated by realistic molecular rules governing vesicle budding and fusion. Remarkably, the plurality of these networks contain chains of compartments that undergo creation, compositional maturation, and dissipation, coupled by molecular recycling along retrograde vesicles. This motif precisely matches the cisternal maturation model of the Golgi, which was developed to explain many observed aspects of the eukaryotic secretory pathway. In our analysis cisternal maturation is a robust consequence of vesicle traffic homeostasis, independent of the underlying details of molecular interactions or spatial stacking. This architecture may have been exapted rather than selected for its role in the secretion of large cargo.

  3. Stacking catalog sources in WMAP data

    CERN Document Server

    Schultz, Kasey W

    2011-01-01

    We stack WMAP 7-year temperature data around extragalactic point sources, showing that the profiles are consistent with WMAP's beam models, in disagreement with the findings of Sawangwit & Shanks (2010). These results require that the source sample's selection is not biased by CMB fluctuations. We compare profiles from sources in the standard WMAP catalog, the WMAP catalog selected from a CMB-free combination of data, and the NVSS catalog, and quantify the agreement with fits to simple parametric beam models. We estimate the biases in source profiles due to alignments with positive CMB fluctuations, finding them roughly consistent with those biases found with the WMAP standard catalog. Addressing those biases, we find source spectral indices significantly steeper than those used by WMAP, with strong evidence for spectral steepening above 61 GHz. Such changes modify the power spectrum correction required for unresolved point sources, and tend to weaken somewhat the evidence for deviation from a Harrison-Ze...

  4. Space biology initiative program definition review. Trade study 5: Modification of existing hardware (COTS) versus new hardware build cost analysis

    Science.gov (United States)

    Jackson, L. Neal; Crenshaw, John, Sr.; Davidson, William L.; Blacknall, Carolyn; Bilodeau, James W.; Stoval, J. Michael; Sutton, Terry

    1989-01-01

    The JSC Life Sciences Project Division has been directly supporting NASA Headquarters, Life Sciences Division, in the preparation of data from JSC and ARC to assist in defining the Space Biology Initiative (SBI). GE Government Services and Horizon Aerospace have provided contract support for the development and integration of review data, reports, presentations, and detailed supporting data. An SBI Definition (Non-Advocate) Review at NASA Headquarters, Code B, has been scheduled for the June-July 1989 time period. In a previous NASA Headquarters review, NASA determined that additional supporting data would be beneficial to determine the potential advantages in modifying commercial off-the-shelf (COTS) hardware for some SBI hardware items. In order to meet the demands of program implementation planning with the definition review in late spring of 1989, the definition trade study analysis must be adjusted in scope and schedule to be complete for the SBI Definition (Non-Advocate) Review. The relative costs of modifying existing commercial off-the-shelf (COTS) hardware is compared to fabricating new hardware. An historical basis for new build versus modifying COTS to meet current NMI specifications for manned space flight hardware is surveyed and identified. Selected SBI hardware are identified as potential candidates for off-the-shelf modification and statistical estimates on the relative cost of modifying COTS versus new build are provided.

  5. Stacking of silicon pore optics for IXO

    Science.gov (United States)

    Collon, Maximilien J.; Guenther, Ramses; Ackermann, Marcelo; Partapsing, Rakesh; Kelly, Chris; Beijersbergen, Marco W.; Bavdaz, Marcos; Wallace, Kotska; Olde Riekerink, Mark; Mueller, Peter; Krumrey, Michael

    2009-08-01

    Silicon pore optics is a technology developed to enable future large area X-ray telescopes, such as the International Xray Observatory (IXO), a candidate mission in the ESA Space Science Programme 'Cosmic Visions 2015-2025'. IXO uses nested mirrors in Wolter-I configuration to focus grazing incidence X-ray photons on a detector plane. The IXO mirrors will have to meet stringent performance requirements including an effective area of ~3 m2 at 1.25 keV and ~1 m2 at 6 keV and angular resolution better than 5 arc seconds. To achieve the collecting area requires a total polished mirror surface area of ~1300 m2 with a surface roughness better than 0.5 nm rms. By using commercial high-quality 12" silicon wafers which are diced, structured, wedged, coated, bent and stacked the stringent performance requirements of IXO can be attained without any costly polishing steps. Two of these stacks are then assembled into a co-aligned mirror module, which is a complete X-ray imaging system. Included in the mirror module are the isostatic mounting points, providing a reliable interface to the telescope. Hundreds of such mirror modules are finally integrated into petals, and mounted onto the spacecraft to form an X-ray optic of four meters in diameter. In this paper we will present the silicon pore optics assembly process and latest X-ray results. The required metrology is described in detail and experimental methods are shown, which allow to assess the quality of the HPOs during production and to predict the performance when measured in synchrotron radiation facilities.

  6. Dielectric elastomer generators that stack up

    International Nuclear Information System (INIS)

    This paper reports the design, fabrication, and testing of a soft dielectric elastomer power generator with a volume of less than 1 cm3. The generator is well suited to harvest energy from ambient and from human body motion as it can harvest from low frequency (sub-Hz) motions, and is compact and lightweight. Dielectric elastomers are highly stretchable variable capacitors. Electrical energy is produced when the deformation of a stretched, charged dielectric elastomer is relaxed; like-charges are compressed together and opposite-charges are pushed apart, resulting in an increased voltage. This technology provides an opportunity to produce soft, high energy density generators with unparalleled robustness. Two major issues block this goal: current configurations require rigid frames that maintain the dielectric elastomer in a prestretched state, and high energy densities have come at the expense of short lifetime. This paper presents a self-supporting stacked generator configuration which does not require rigid frames. The generator consists of 48 generator films stacked on top of each other, resulting in a structure that fits within an 11 mm diameter footprint while containing enough active material to produce useful power. To ensure sustainable power production, we also present a mathematical model for designing the electronic control of the generator which optimizes energy production while limiting the electrical stress on the generator below failure limits. When cyclically compressed at 1.6 Hz, our generator produced 1.8 mW of power, which is sufficient for many low-power wireless sensor nodes. This performance compares favorably with similarly scaled electromagnetic, piezoelectric, and electrostatic generators. The generator’s small form factor and ability to harvest useful energy from low frequency motions such as tree swaying or shoe impact provides an opportunity to deliver power to remote wireless sensor nodes or to distributed points in the human body

  7. Evaluating interaction techniques for stack mode viewing.

    Science.gov (United States)

    Atkins, M Stella; Fernquist, Jennifer; Kirkpatrick, Arthur E; Forster, Bruce B

    2009-08-01

    Three interaction techniques were evaluated for scrolling stack mode displays of volumetric data. Two used a scroll-wheel mouse: one used only the wheel, while another used a "click and drag" technique for fast scrolling, leaving the wheel for fine adjustments. The third technique used a Shuttle Xpress jog wheel. In a within-subjects design, nine radiologists searched stacked images for simulated hyper-intense regions on brain, knee, and thigh MR studies. Dependent measures were speed, accuracy, navigation path, and user preference. The radiologists considered the task realistic. They had high inter-subject variability in completion times, far larger than the differences between techniques. Most radiologists (eight out of nine) preferred familiar mouse-based techniques. Most participants scanned the data in two passes, first locating anomalies, then scanning for omissions. Participants spent a mean 10.4 s/trial exploring anomalies, with only mild variation between participants. Their rates of forward navigation searching for anomalies varied much more. Interaction technique significantly affected forward navigation rate (scroll wheel 5.4 slices/s, click and drag 9.4, and jog wheel 6.9). It is not clear what constrained the slowest navigators. The fastest navigator used a unique strategy of moving quickly just beyond an anomaly, then backing up. Eight naïve students performed a similar protocol. Their times and variability were similar to the radiologists, but more (three out of eight) students preferred the jog wheel. It may be worthwhile to introduce techniques such as the jog wheel to radiologists during training, and several techniques might be provided on workstations, allowing individuals to choose their preferred method.

  8. Dielectric elastomer generators that stack up

    Science.gov (United States)

    McKay, T. G.; Rosset, S.; Anderson, I. A.; Shea, H.

    2015-01-01

    This paper reports the design, fabrication, and testing of a soft dielectric elastomer power generator with a volume of less than 1 cm3. The generator is well suited to harvest energy from ambient and from human body motion as it can harvest from low frequency (sub-Hz) motions, and is compact and lightweight. Dielectric elastomers are highly stretchable variable capacitors. Electrical energy is produced when the deformation of a stretched, charged dielectric elastomer is relaxed; like-charges are compressed together and opposite-charges are pushed apart, resulting in an increased voltage. This technology provides an opportunity to produce soft, high energy density generators with unparalleled robustness. Two major issues block this goal: current configurations require rigid frames that maintain the dielectric elastomer in a prestretched state, and high energy densities have come at the expense of short lifetime. This paper presents a self-supporting stacked generator configuration which does not require rigid frames. The generator consists of 48 generator films stacked on top of each other, resulting in a structure that fits within an 11 mm diameter footprint while containing enough active material to produce useful power. To ensure sustainable power production, we also present a mathematical model for designing the electronic control of the generator which optimizes energy production while limiting the electrical stress on the generator below failure limits. When cyclically compressed at 1.6 Hz, our generator produced 1.8 mW of power, which is sufficient for many low-power wireless sensor nodes. This performance compares favorably with similarly scaled electromagnetic, piezoelectric, and electrostatic generators. The generator’s small form factor and ability to harvest useful energy from low frequency motions such as tree swaying or shoe impact provides an opportunity to deliver power to remote wireless sensor nodes or to distributed points in the human body

  9. Forward and adjoint spectral-element simulations of seismic wave propagation using hardware accelerators

    Science.gov (United States)

    Peter, Daniel; Videau, Brice; Pouget, Kevin; Komatitsch, Dimitri

    2015-04-01

    Improving the resolution of tomographic images is crucial to answer important questions on the nature of Earth's subsurface structure and internal processes. Seismic tomography is the most prominent approach where seismic signals from ground-motion records are used to infer physical properties of internal structures such as compressional- and shear-wave speeds, anisotropy and attenuation. Recent advances in regional- and global-scale seismic inversions move towards full-waveform inversions which require accurate simulations of seismic wave propagation in complex 3D media, providing access to the full 3D seismic wavefields. However, these numerical simulations are computationally very expensive and need high-performance computing (HPC) facilities for further improving the current state of knowledge. During recent years, many-core architectures such as graphics processing units (GPUs) have been added to available large HPC systems. Such GPU-accelerated computing together with advances in multi-core central processing units (CPUs) can greatly accelerate scientific applications. There are mainly two possible choices of language support for GPU cards, the CUDA programming environment and OpenCL language standard. CUDA software development targets NVIDIA graphic cards while OpenCL was adopted mainly by AMD graphic cards. In order to employ such hardware accelerators for seismic wave propagation simulations, we incorporated a code generation tool BOAST into an existing spectral-element code package SPECFEM3D_GLOBE. This allows us to use meta-programming of computational kernels and generate optimized source code for both CUDA and OpenCL languages, running simulations on either CUDA or OpenCL hardware accelerators. We show here applications of forward and adjoint seismic wave propagation on CUDA/OpenCL GPUs, validating results and comparing performances for different simulations and hardware usages.

  10. Hardware additions to microprocessor architecture aid software development

    Science.gov (United States)

    Sievers, M. W.

    1976-01-01

    An address trap (breakpoint) mechanism and last-in-first-out (LIFO) address stack are suggested as two additions to the basic microprocessor architecture whose functions are solely to aid the programmer. These devices provide the programmer with the ability to specify address breakpoints and to trace program execution back through N instructions, where N is the depth of the stack. Both devices, plus interface logic and buffering, have been designed for an INTEL 8080-based system using approximately 25 integrated-circuit packages.

  11. Evaluation of piezoelectret foam in a multilayer stack configuration for low-level vibration energy harvesting applications

    Science.gov (United States)

    Ray, Chase A.; Anton, Steven R.

    2015-04-01

    Electronic devices are high demand commodities in today's world, and such devices will continue increasing in popularity. Currently, batteries are implemented to provide power to these devices; however, the need for battery replacement, their cost, and the waste associated with battery disposal present a need for advances in self-powered technology. Energy harvesting technology has great potential to alleviate the drawbacks of batteries. In this work, a novel piezoelectret foam material is investigated for low-level energy harvesting. Specifically, piezoelectret foam assembled in a multilayer stack configuration is explored. Modeling and experimentation of the stack behavior when excited in compression at low frequencies are performed to investigate piezoelectret foam as a multilayer energy harvester. An examination of modeling piezoelectret foam as a stack with an equivalent circuit is made following recently published work and is used in this study. A 20-layer prototype device is fabricated and experimentally tested via harmonic base excitation. Electromechanical testing is performed by compressing the foam stack to obtain output electrical energy; consequently, allowing the frequency response between input mechanical energy and output electrical energy to be developed. Modeling results are compared to the experimental measurements to assess the fidelity of the model. Lastly, energy harvesting experimentation in which the device is subject to harmonic base excitation at the natural frequency is conducted to determine the ability of the piezoelectret foam stack to successfully charge a capacitor.

  12. Color science demonstration kit from open source hardware and software

    Science.gov (United States)

    Zollers, Michael W.

    2014-09-01

    Color science is perhaps the most universally tangible discipline within the optical sciences for people of all ages. Excepting a small and relatively well-understood minority, we can see that the world around us consists of a multitude of colors; yet, describing the "what", "why", and "how" of these colors is not an easy task, especially without some sort of equally colorful visual aids. While static displays (e.g., poster boards, etc.) serve their purpose, there is a growing trend, aided by the recent permeation of small interactive devices into our society, for interactive and immersive learning. However, for the uninitiated, designing software and hardware for this purpose may not be within the purview of all optical scientists and engineers. Enter open source. Open source "anything" are those tools and designs -- hardware or software -- that are available and free to use, often without any restrictive licensing. Open source software may be familiar to some, but the open source hardware movement is relatively new. These are electronic circuit board designs that are provided for free and can be implemented in physical hardware by anyone. This movement has led to the availability of some relatively inexpensive, but quite capable, computing power for the creation of small devices. This paper will showcase the design and implementation of the software and hardware that was used to create an interactive demonstration kit for color. Its purpose is to introduce and demonstrate the concepts of color spectra, additive color, color rendering, and metamers.

  13. OS friendly microprocessor architecture: Hardware level computer security

    Science.gov (United States)

    Jungwirth, Patrick; La Fratta, Patrick

    2016-05-01

    We present an introduction to the patented OS Friendly Microprocessor Architecture (OSFA) and hardware level computer security. Conventional microprocessors have not tried to balance hardware performance and OS performance at the same time. Conventional microprocessors have depended on the Operating System for computer security and information assurance. The goal of the OS Friendly Architecture is to provide a high performance and secure microprocessor and OS system. We are interested in cyber security, information technology (IT), and SCADA control professionals reviewing the hardware level security features. The OS Friendly Architecture is a switched set of cache memory banks in a pipeline configuration. For light-weight threads, the memory pipeline configuration provides near instantaneous context switching times. The pipelining and parallelism provided by the cache memory pipeline provides for background cache read and write operations while the microprocessor's execution pipeline is running instructions. The cache bank selection controllers provide arbitration to prevent the memory pipeline and microprocessor's execution pipeline from accessing the same cache bank at the same time. This separation allows the cache memory pages to transfer to and from level 1 (L1) caching while the microprocessor pipeline is executing instructions. Computer security operations are implemented in hardware. By extending Unix file permissions bits to each cache memory bank and memory address, the OSFA provides hardware level computer security.

  14. Higher-Level Hardware Synthesis of the KASUMI Algorithm

    Institute of Scientific and Technical Information of China (English)

    Issam W. Damaj

    2007-01-01

    Programmable Logic Devices (PLDs) continue to grow in size and currently contain several millions of gates.At the same time, research effort is going into higher-level hardware synthesis methodologies for reconfigurable computing that can exploit PLD technology.In this paper, we explore the effectiveness and extend one such formal methodology in the design of massively parallel algorithms.We take a step-wise refinement approach to the development of correct reconfigurable hardware circuits from formal specifications.A functional programming notation is used for specifying algorithms and for reasoning about them.The specifications are realised through the use of a combination of function decomposition strategies, data refinement techniques, and off-the-shelf refinements based upon higher-order functions.The off-the-shelf refinements are inspired by the operators of Communicating Sequential Processes (CSP) and map easily to programs in Handel-C (a hardware description language).The Handel-C descriptions are directly compiled into reconfigurable hardware.The practical realisation of this methodology is evidenced by a case studying the third generation mobile communication security algorithms.The investigated algorithm is the KASUMI block cipher.In this paper, we obtain several hardware implementations with different performance characteristics by applying different refinements to the algorithm.The developed designs are compiled and tested under Celoxica's RC-1000 reconfigurable computer with its 2 million gates Virtex-E FPGA.Performance analysis and evaluation of these implementations are included.

  15. Postflight hardware evaluation 360T025 (RSRM-25, STS-46)

    Science.gov (United States)

    Morgan, Ferral

    1993-03-01

    The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the 360T025 (STS-46) Redesign Solid Rocket Motor (RSRM) flight set is presented. All observed hardware conditions were documented on PFOR's and are included in Appendices A through C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. Along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-60687), a summary of the 360T025 hardware evaluation is provided. The as-flown hardware configuration is documented in TWR-60470. Disassembly evaluation photograph numbers are logged in TWA-1986. The 360T025 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on 16 Mar. 1993. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  16. Final postflight hardware evaluation report RSRM-28 (STS-53)

    Science.gov (United States)

    Starrett, William David, Jr.

    1993-11-01

    The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the RSRM-28 (STS-53) RSRM flight set is presented. All observed hardware conditions were documented on PFOR's and are included in Appendices A through C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64215), represents a summary of the RSRM-28 hardware evaluation. The as-flown hardware configuration is documented in TWR-63638. Disassembly evaluation photograph numbers are logged in TWA-1989. The RSRM-28 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on July 15, 1993. Additional time was required to perform the evaluation of the stiffener rings per special issue 4.1.5.2 because of the washout schedule. The release of this report was after completion of all special issues per program management direction. Detailed evaluations were performed in accordance with the Clearfield PEEP, TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable team and tracked through the PFAR system.

  17. Postflight hardware evaluation 360T026 (RSRM-26, STS-47)

    Science.gov (United States)

    Nielson, Greg

    1993-05-01

    The final report for the Clearfield disassembly evaluation and a continuation of the KSC postflight assessment for the 360T026 (STS-47) Redesigned Solid Rocket Motor (RSRM) flight set is provided. All observed hardware conditions were documented on PFOR's and are included in Appendices A, B, and C. Appendices D and E contain the measurements and safety factor data for the nozzle and insulation components. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report (TWR-64203), represents a summary of the 360T026 hardware evaluation. The as-flown hardware configuration is documented in TWR-60472. Disassembly evaluation photograph numbers are logged in TWA-1987. The 360T026 flight set disassembly evaluations described were performed at the RSRM Refurbishment Facility in Clearfield, Utah. The final factory joint demate occurred on 12 April 1993. Detailed evaluations were performed in accordance with the Clearfield Postflight Engineering Evaluation Plan (PEEP), TWR-50051, Revision A. All observations were compared against limits that are also defined in the PEEP. These limits outline the criteria for categorizing the observations as acceptable, reportable, or critical. Hardware conditions that were unexpected and/or determined to be reportable or critical were evaluated by the applicable CPT and tracked through the PFAR system.

  18. Calculation of AC losses in large HTS stacks and coils

    DEFF Research Database (Denmark)

    Zermeno, Victor; Abrahamsen, Asger Bech; Mijatovic, Nenad;

    2012-01-01

    In this work, we present a homogenization method to model a stack of HTS tapes under AC applied transport current or magnetic field. The idea is to find an anisotropic bulk equivalent for the stack of tapes, where the internal alternating structures of insulating, metallic, superconducting...

  19. Development of internal reforming carbonate fuel cell stack technology

    Energy Technology Data Exchange (ETDEWEB)

    Farooque, M.

    1990-10-01

    Activities under this contract focused on the development of a coal-fueled carbonate fuel cell system design and the stack technology consistent with the system design. The overall contract effort was divided into three phases. The first phase, completed in January 1988, provided carbonate fuel cell component scale-up from the 1ft{sup 2} size to the commercial 4ft{sup 2} size. The second phase of the program provided the coal-fueled carbonate fuel cell system (CGCFC) conceptual design and carried out initial research and development needs of the CGCFC system. The final phase of the program emphasized stack height scale-up and improvement of stack life. The results of the second and third phases are included in this report. Program activities under Phase 2 and 3 were designed to address several key development areas to prepare the carbonate fuel cell system, particularly the coal-fueled CFC power plant, for commercialization in late 1990's. The issues addressed include: Coal-Gas Related Considerations; Cell and Stack Technology Improvement; Carbonate Fuel Cell Stack Design Development; Stack Tests for Design Verification; Full-Size Stack Design; Test Facility Development; Carbonate Fuel Cell Stack Cost Assessment; and Coal-Fueled Carbonate Fuel Cell System Design. All the major program objectives in each of the topical areas were successfully achieved. This report is organized along the above-mentioned topical areas. Each topical area has been processed separately for inclusion on the data base.

  20. Yield and Cost Analysis or 3D Stacked ICs

    NARCIS (Netherlands)

    Taouil, M.

    2014-01-01

    3D stacking is an emerging technology promising many benefits such as low latency between stacked dies, reduced power consumption, high bandwidth communication, improved form factor and package volume density, heterogeneous integration, and low-cost manufacturing. However, it requires modification o

  1. Simultaneous stack-gas scrubbing and waste water treatment

    Science.gov (United States)

    Poradek, J. C.; Collins, D. D.

    1980-01-01

    Simultaneous treatment of wastewater and S02-laden stack gas make both treatments more efficient and economical. According to results of preliminary tests, solution generated by stack gas scrubbing cycle reduces bacterial content of wastewater. Both processess benefit by sharing concentrations of iron.

  2. 29 CFR 1917.14 - Stacking of cargo and pallets.

    Science.gov (United States)

    2010-07-01

    ... 29 Labor 7 2010-07-01 2010-07-01 false Stacking of cargo and pallets. 1917.14 Section 1917.14 Labor Regulations Relating to Labor (Continued) OCCUPATIONAL SAFETY AND HEALTH ADMINISTRATION... pallets. Cargo, pallets and other material stored in tiers shall be stacked in such a manner as to...

  3. Nondestructive cell evaluation techniques in SOFC stack manufacturing

    Science.gov (United States)

    Wunderlich, C.

    2016-04-01

    Independent from the specifics of the application, a cost efficient manufacturing of solid oxide fuel cells (SOFC), its electrolyte membranes and other stack components, leading to reliable long-life stacks is the key for the commercial viability of this fuel cell technology. Tensile and shear stresses are most critical for ceramic components and especially for thin electrolyte membranes as used in SOFC cells. Although stack developers try to reduce tensile stresses acting on the electrolyte by either matching CTE of interconnects and electrolytes or by putting SOFC cells under some pressure - at least during transient operation of SOFC stacks ceramic cells will experience some tensile stresses. Electrolytes are required to have a high Weibull characteristic fracture strength. Practical experiences in stack manufacturing have shown that statistical fracture strength data generated by tests of electrolyte samples give limited information on electrolyte or cell quality. In addition, the cutting process of SOFC electrolytes has a major influence on crack initiation. Typically, any single crack in one the 30 to 80 cells in series connection will lead to a premature stack failure drastically reducing stack service life. Thus, for statistical reasons only 100% defect free SOFC cells must be assembled in stacks. This underlines the need for an automated inspection. So far, only manual processes of visual or mechanical electrolyte inspection are established. Fraunhofer IKTS has qualified the method of optical coherence tomography for an automated high throughput inspection. Alternatives like laser speckle photometry and acoustical methods are still under investigation.

  4. Assessment of mean stack rises for cold sources

    International Nuclear Information System (INIS)

    A stack rise for cold sources depends on the exit conditions, namely the exit velocity, the stack diameter, the stack height, and the heat emission and, for calculating a mean rise, on the weather statistics employed. For routine assessments, in most cases the Holland-Stuemke formula is used. It supplies values for the stack rise, and so for the diffusion factor, which are in the medium range of those calculated by means of equations available for cold sources. The Moses-Carson formula supplies the lowest rise values. The Bryant-Davidson formula produces results up to mean exit impulses which are similar to those of the Holland-Stuemke formula, but for very high exit impulses it deviates positively to an increasing extent. Downwash occurs only at low exit velocities in connection with high wind speed. The decision as to whether a mean stack rise should be taken into account for long-term diffusion calculations can only be taken after assessing this quantity by means of one of the described formulas. The stack height is also important in this context. With lower stacks a certain rise has stronger effects than with high stacks. (orig./HP)

  5. 40 CFR 52.383 - Stack height review.

    Science.gov (United States)

    2010-07-01

    ... 40 Protection of Environment 3 2010-07-01 2010-07-01 false Stack height review. 52.383 Section 52.383 Protection of Environment ENVIRONMENTAL PROTECTION AGENCY (CONTINUED) AIR PROGRAMS (CONTINUED... by stack height credits greater than good engineering practice or any other prohibited...

  6. Phase dynamics of two parallel stacks of coupled Josephson junctions

    Science.gov (United States)

    Shukrinov, Yu M.; Rahmonov, I. R.; Plecenik, A.; Seidel, P.; Ilʼichev, E.; Nawrocki, W.

    2014-12-01

    Two parallel stacks of coupled Josephson junctions (JJs) are investigated to clarify the physics of transitions between the rotating and oscillating states and their effect on the IV-characteristics of the system. The detailed study of phase dynamics and bias dependence of the superconducting and diffusion currents allows one to explain all features of simulated IV-characteristics and demonstrate the correspondence in their behavior. The coupling between JJ in the stacks leads to the branching of IV-characteristics and a decrease in the hysteretic region. The crucial role of the diffusion current in the formation of the IV-characteristic of the parallel stacks of coupled JJs is demonstrated. We discuss the effect of symmetry in a number of junctions in the stacks and show a decrease of the branching in the symmetrical stacks. The observed effects might be useful for development of superconducting electronic devices based on intrinsic JJs.

  7. Dynamic Model of High Temperature PEM Fuel Cell Stack Temperature

    DEFF Research Database (Denmark)

    Andreasen, Søren Juhl; Kær, Søren Knudsen

    2007-01-01

    the stack at a high stoichiometric air flow. This is possible because of the PBI fuel cell membranes used, and the very low pressure drop in the stack. The model consists of a discrete thermal model dividing the stack into three parts: inlet, middle and end and predicting the temperatures in these three...... parts, where also the temperatures are measured. The heat balance of the system involves a fuel cell model to describe the heat added by the fuel cells when a current is drawn. Furthermore the model also predicts the temperatures, when heating the stack with external heating elements for start-up, heat......The present work involves the development of a model for predicting the dynamic temperature of a high temperature PEM (HTPEM) fuel cell stack. The model is developed to test different thermal control strategies before implementing them in the actual system. The test system consists of a prototype...

  8. Proposed Cavity for Reduced Slip-Stacking Loss

    Energy Technology Data Exchange (ETDEWEB)

    Eldred, J. [Indiana U.; Zwaska, R. [Fermilab

    2015-06-01

    This paper employs a novel dynamical mechanism to improve the performance of slip-stacking. Slip-stacking in an accumulation technique used at Fermilab since 2004 which nearly double the proton intensity. During slip-stacking, the Recycler or the Main Injector stores two particles beams that spatially overlap but have different momenta. The two particle beams are longitudinally focused by two 53 MHz 100 kV RF cavities with a small frequency difference between them. We propose an additional 106 MHz 20 kV RF cavity, with a frequency at the double the average of the upper and lower main RF frequencies. In simulation, we find the proposed RF cavity significantly enhances the stable bucket area and reduces slip-stacking losses under reasonable injection scenarios. We quantify and map the stability of the parameter space for any accelerator implementing slip-stacking with the addition of a harmonic RF cavity.

  9. Three-Dimensional Wafer Stacking Using Cu TSV Integrated with 45 nm High Performance SOI-CMOS Embedded DRAM Technology

    Directory of Open Access Journals (Sweden)

    Pooja Batra

    2014-05-01

    Full Text Available For high-volume production of 3D-stacked chips with through-silicon-vias (TSVs, wafer-scale bonding offers lower production cost compared with bump bond technology and is promising for interconnect pitches smaller than 5 µ using available tooling. Prior work has presented wafer-scale integration with tungsten TSV for low-power applications. This paper reports the first use of low-temperature oxide bonding and copper TSV to stack high performance cache cores manufactured in 45 nm Silicon On Insulator-Complementary Metal Oxide Semiconductor (SOI-CMOS embedded DRAM (EDRAM having 12 to 13 copper wiring levels per strata and upto 11000 TSVs at 13 µm pitch for power and signal delivery. The wafers are thinned to 13 µm using grind polish and etch. TSVs are defined post bonding and thinning using conventional alignment techniques. Up to four additional metal levels are formed post bonding and TSV definition. A key feature of this process is its compatibility with the existing high performance POWER7™ EDRAM core requiring neither modification of the existing CMOS fabrication process nor re-design since the TSV RC characteristic is similar to typical 100–200 µm length wiring load enabling 3D macro-to-macro signaling without additional buffering Hardware measurements show no significant impact on device drive and off-current. Functional test at wafer level confirms 2.1 GHz 3D stacked EDRAM operation.

  10. Laser Light Scattering, from an Advanced Technology Development Program to Experiments in a Reduced Gravity Environment

    Science.gov (United States)

    Meyer, William V.; Tscharnuter, Walther W.; Macgregor, Andrew D.; Dautet, Henri; Deschamps, Pierre; Boucher, Francois; Zuh, Jixiang; Tin, Padetha; Rogers, Richard B.; Ansari, Rafat R.

    1994-01-01

    Recent advancements in laser light scattering hardware are described. These include intelligent single card correlators; active quench/active reset avalanche photodiodes; laser diodes; and fiber optics which were used by or developed for a NASA advanced technology development program. A space shuttle experiment which will employ aspects of these hardware developments is previewed.

  11. ADVANCED HYDROGEN TURBINE DEVELOPMENT

    Energy Technology Data Exchange (ETDEWEB)

    Marra, John

    2015-06-30

    Under the sponsorship of the U.S. Department of Energy (DOE) National Energy Technology Laboratories, Siemens has completed the Advanced Hydrogen Turbine Development Program to develop an advanced gas turbine for incorporation into future coal-based Integrated Gasification Combined Cycle (IGCC) plants. All the scheduled DOE Milestones were completed and significant technical progress was made in the development of new technologies and concepts. Advanced computer simulations and modeling, as well as subscale, full scale laboratory, rig and engine testing were utilized to evaluate and select concepts for further development. Program Requirements of: ⟂ A 3 to 5 percentage point improvement in overall plant combined cycle efficiency when compared to the reference baseline plant. ⟂ 20 to 30 percent reduction in overall plant capital cost when compared to the reference baseline plant. ₜ NOx emissions of 2 PPM out of the stack. were all met. The program was completed on schedule and within the allotted budget

  12. Advanced Hydrogen Turbine Development

    Energy Technology Data Exchange (ETDEWEB)

    Marra, John [Siemens Energy, Inc., Orlando, FL (United States)

    2015-09-30

    Under the sponsorship of the U.S. Department of Energy (DOE) National Energy Technology Laboratories, Siemens has completed the Advanced Hydrogen Turbine Development Program to develop an advanced gas turbine for incorporation into future coal-based Integrated Gasification Combined Cycle (IGCC) plants. All the scheduled DOE Milestones were completed and significant technical progress was made in the development of new technologies and concepts. Advanced computer simulations and modeling, as well as subscale, full scale laboratory, rig and engine testing were utilized to evaluate and select concepts for further development. Program Requirements of: A 3 to 5 percentage point improvement in overall plant combined cycle efficiency when compared to the reference baseline plant; 20 to 30 percent reduction in overall plant capital cost when compared to the reference baseline plant; and NOx emissions of 2 PPM out of the stack. were all met. The program was completed on schedule and within the allotted budget

  13. Plutonium Protection System (PPS). Volume 2. Hardware description. Final report

    Energy Technology Data Exchange (ETDEWEB)

    Miyoshi, D.S.

    1979-05-01

    The Plutonium Protection System (PPS) is an integrated safeguards system developed by Sandia Laboratories for the Department of Energy, Office of Safeguards and Security. The system is designed to demonstrate and test concepts for the improved safeguarding of plutonium. Volume 2 of the PPS final report describes the hardware elements of the system. The major areas containing hardware elements are the vault, where plutonium is stored, the packaging room, where plutonium is packaged into Container Modules, the Security Operations Center, which controls movement of personnel, the Material Accountability Center, which maintains the system data base, and the Material Operations Center, which monitors the operating procedures in the system. References are made to documents in which details of the hardware items can be found.

  14. Hardware Accelerated Compression of LIDAR Data Using FPGA Devices

    Directory of Open Access Journals (Sweden)

    Franc Novak

    2013-05-01

    Full Text Available Airborne Light Detection and Ranging (LIDAR has become a mainstream technology for terrain data acquisition and mapping. High sampling density of LIDAR enables the acquisition of high details of the terrain, but on the other hand, it results in a vast amount of gathered data, which requires huge storage space as well as substantial processing effort. The data are usually stored in the LAS format which has become the de facto standard for LIDAR data storage and exchange. In the paper, a hardware accelerated compression of LIDAR data is presented. The compression and decompression of LIDAR data is performed by a dedicated FPGA-based circuit and interfaced to the computer via a PCI-E general bus. The hardware compressor consists of three modules: LIDAR data predictor, variable length coder, and arithmetic coder. Hardware compression is considerably faster than software compression, while it also alleviates the processor load.

  15. Scalable Digital Hardware for a Trapped Ion Quantum Computer

    CERN Document Server

    Mount, Emily; Vrijsen, Geert; Adams, Michael; Baek, So-Young; Hudek, Kai; Isabella, Louis; Crain, Stephen; van Rynbach, Andre; Maunz, Peter; Kim, Jungsang

    2015-01-01

    Many of the challenges of scaling quantum computer hardware lie at the interface between the qubits and the classical control signals used to manipulate them. Modular ion trap quantum computer architectures address scalability by constructing individual quantum processors interconnected via a network of quantum communication channels. Successful operation of such quantum hardware requires a fully programmable classical control system capable of frequency stabilizing the continuous wave lasers necessary for trapping and cooling the ion qubits, stabilizing the optical frequency combs used to drive logic gate operations on the ion qubits, providing a large number of analog voltage sources to drive the trap electrodes, and a scheme for maintaining phase coherence among all the controllers that manipulate the qubits. In this work, we describe scalable solutions to these hardware development challenges.

  16. Hardware Realization of Chaos-based Symmetric Video Encryption

    KAUST Repository

    Ibrahim, Mohamad A.

    2013-05-01

    This thesis reports original work on hardware realization of symmetric video encryption using chaos-based continuous systems as pseudo-random number generators. The thesis also presents some of the serious degradations caused by digitally implementing chaotic systems. Subsequently, some techniques to eliminate such defects, including the ultimately adopted scheme are listed and explained in detail. Moreover, the thesis describes original work on the design of an encryption system to encrypt MPEG-2 video streams. Information about the MPEG-2 standard that fits this design context is presented. Then, the security of the proposed system is exhaustively analyzed and the performance is compared with other reported systems, showing superiority in performance and security. The thesis focuses more on the hardware and the circuit aspect of the system’s design. The system is realized on Xilinx Vetrix-4 FPGA with hardware parameters and throughput performance surpassing conventional encryption systems.

  17. Hardware/Software Co-Design for Spike Based Recognition

    CERN Document Server

    Ghani, Arfan; Maguire, Liam; Harkin, Jim

    2008-01-01

    The practical applications based on recurrent spiking neurons are limited due to their non-trivial learning algorithms. The temporal nature of spiking neurons is more favorable for hardware implementation where signals can be represented in binary form and communication can be done through the use of spikes. This work investigates the potential of recurrent spiking neurons implementations on reconfigurable platforms and their applicability in temporal based applications. A theoretical framework of reservoir computing is investigated for hardware/software implementation. In this framework, only readout neurons are trained which overcomes the burden of training at the network level. These recurrent neural networks are termed as microcircuits which are viewed as basic computational units in cortical computation. This paper investigates the potential of recurrent neural reservoirs and presents a novel hardware/software strategy for their implementation on FPGAs. The design is implemented and the functionality is ...

  18. Mapping of topological quantum circuits to physical hardware.

    Science.gov (United States)

    Paler, Alexandru; Devitt, Simon J; Nemoto, Kae; Polian, Ilia

    2014-01-01

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit. PMID:24722360

  19. Mapping of Topological Quantum Circuits to Physical Hardware

    Science.gov (United States)

    Paler, Alexandru; Devitt, Simon J.; Nemoto, Kae; Polian, Ilia

    2014-04-01

    Topological quantum computation is a promising technique to achieve large-scale, error-corrected computation. Quantum hardware is used to create a large, 3-dimensional lattice of entangled qubits while performing computation requires strategic measurement in accordance with a topological circuit specification. The specification is a geometric structure that defines encoded information and fault-tolerant operations. The compilation of a topological circuit is one important aspect of programming a quantum computer, another is the mapping of the topological circuit into the operations performed by the hardware. Each qubit has to be controlled, and measurement results are needed to propagate encoded quantum information from input to output. In this work, we introduce an algorithm for mapping an topological circuit to the operations needed by the physical hardware. We determine the control commands for each qubit in the computer and the relevant measurements that are needed to track information as it moves through the circuit.

  20. Hardware Architecture Study for NASA's Space Software Defined Radios

    Science.gov (United States)

    Reinhart, Richard C.; Scardelletti, Maximilian C.; Mortensen, Dale J.; Kacpura, Thomas J.; Andro, Monty; Smith, Carl; Liebetreu, John

    2008-01-01

    This study defines a hardware architecture approach for software defined radios to enable commonality among NASA space missions. The architecture accommodates a range of reconfigurable processing technologies including general purpose processors, digital signal processors, field programmable gate arrays (FPGAs), and application-specific integrated circuits (ASICs) in addition to flexible and tunable radio frequency (RF) front-ends to satisfy varying mission requirements. The hardware architecture consists of modules, radio functions, and and interfaces. The modules are a logical division of common radio functions that comprise a typical communication radio. This paper describes the architecture details, module definitions, and the typical functions on each module as well as the module interfaces. Trade-offs between component-based, custom architecture and a functional-based, open architecture are described. The architecture does not specify the internal physical implementation within each module, nor does the architecture mandate the standards or ratings of the hardware used to construct the radios.

  1. Final postflight hardware evaluation report RSRM-32 (STS-57)

    Science.gov (United States)

    Nielson, Greg

    1993-11-01

    This document is the final report for the postflight assessment of the RSRM-32 (STS-57) flight set. This report presents the disassembly evaluations performed at the Thiokol facilities in Utah and is a continuation of the evaluations performed at KSC (TWR-64239). The PEEP for this assessment is outlined in TWR-50051, Revision B. The PEEP defines the requirements for evaluating RSRM hardware. Special hardware issues pertaining to this flight set requiring additional or modified assessment are outlined in TWR-64237. All observed hardware conditions were documented on PFOR's which are included in Appendix A. Observations were compared against limits defined in the PEEP. Any observation that was categorized as reportable or had no defined limits was documented on a preliminary PFAR by the assessment engineers. Preliminary PFAR's were reviewed by the Thiokol SPAT Executive Board to determine if elevation to PFAR's was required.

  2. On Issues of Precision for Hardware-based Volume Visualization

    Energy Technology Data Exchange (ETDEWEB)

    LaMar, E C

    2003-04-11

    This paper discusses issues with the limited precision of hardware-based volume visualization. We will describe the compositing OVER operator and how fixed-point arithmetic affects it. We propose two techniques to improve the precision of fixed-point compositing and the accuracy of hardware-based volume visualization. The first technique is to perform dithering of color and alpha values. The second technique we call exponent-factoring, and captures significantly more numeric resolution than dithering, but can only produce monochromatic images.

  3. Efficient FPGA Hardware Reuse in a Multiplierless Decimation Chain

    Directory of Open Access Journals (Sweden)

    Guillermo A. Jaquenod

    2014-01-01

    Full Text Available In digital communications, an usual reception chain requires many stages of digital signal processing for filtering and sample rate reduction. For satellite on board applications, this need is hardly constrained by the very limited hardware resources available in space qualified FPGAs. This short paper focuses on the implementation of a dual chain of 14 stages of cascaded half band filters plus 2 : 1 decimators for complex signals (in-phase and quadrature with minimal hardware resources, using a small portion of an UT6325 Aeroflex FPGA, as a part of a receiver designed for a low data rate command and telemetry channel.

  4. Surface moisture measurement system hardware acceptance test report

    Energy Technology Data Exchange (ETDEWEB)

    Ritter, G.A., Westinghouse Hanford

    1996-05-28

    This document summarizes the results of the hardware acceptance test for the Surface Moisture Measurement System (SMMS). This test verified that the mechanical and electrical features of the SMMS functioned as designed and that the unit is ready for field service. The bulk of hardware testing was performed at the 306E Facility in the 300 Area and the Fuels and Materials Examination Facility in the 400 Area. The SMMS was developed primarily in support of Tank Waste Remediation System (TWRS) Safety Programs for moisture measurement in organic and ferrocyanide watch list tanks.

  5. Integrated circuit authentication hardware Trojans and counterfeit detection

    CERN Document Server

    Tehranipoor, Mohammad; Zhang, Xuehui

    2013-01-01

    This book describes techniques to verify the authenticity of integrated circuits (ICs). It focuses on hardware Trojan detection and prevention and counterfeit detection and prevention. The authors discuss a variety of detection schemes and design methodologies for improving Trojan detection techniques, as well as various attempts at developing hardware Trojans in IP cores and ICs. While describing existing Trojan detection methods, the authors also analyze their effectiveness in disclosing various types of Trojans, and demonstrate several architecture-level solutions. 

  6. USING SUBTHRESHOLD SRAM TO DESIGN LOW-POWER CRYPTO HARDWARE

    Directory of Open Access Journals (Sweden)

    Adnan Abdul-Aziz Gutub

    2011-01-01

    Full Text Available Cryptography and Security hardware architecture designing is in essential need for efficient power utilization which is achieved earlier by giving a range of trade- off between speed and power consumption. This paper presents the initiative of considering subthreshold SRAM memory modules to gain ultra-low-power capable systems. The paper presents improving existing crypto security architectures to reconfigurable domain-specific SRAM memory designs. It is found that reliability is still a problem not solved; however, we start this paper idea to design flexible crypto hardware to gain the performance as well as the reduced power consumption.

  7. Computer organization and design the hardware/software interface

    CERN Document Server

    Hennessy, John L

    1994-01-01

    Computer Organization and Design: The Hardware/Software Interface presents the interaction between hardware and software at a variety of levels, which offers a framework for understanding the fundamentals of computing. This book focuses on the concepts that are the basis for computers.Organized into nine chapters, this book begins with an overview of the computer revolution. This text then explains the concepts and algorithms used in modern computer arithmetic. Other chapters consider the abstractions and concepts in memory hierarchies by starting with the simplest possible cache. This book di

  8. Stretched Lens Array (SLA) Photovoltaic Concentrator Hardware Development and Testing

    Science.gov (United States)

    Piszczor, Michael; O'Neill, Mark J.; Eskenazi, Michael

    2003-01-01

    Over the past two years, the Stretched Lens Array (SLA) photovoltaic concentrator has evolved, under a NASA contract, from a concept with small component demonstrators to operational array hardware that is ready for space validation testing. A fully-functional four panel SLA solar array has been designed, built and tested. This paper will summarize the focus of the hardware development effort, discuss the results of recent testing conducted under this program and present the expected performance of a full size 7kW array designed to meet the requirements of future space missions.

  9. Electrical, electronics, and digital hardware essentials for scientists and engineers

    CERN Document Server

    Lipiansky, Ed

    2012-01-01

    A practical guide for solving real-world circuit board problems Electrical, Electronics, and Digital Hardware Essentials for Scientists and Engineers arms engineers with the tools they need to test, evaluate, and solve circuit board problems. It explores a wide range of circuit analysis topics, supplementing the material with detailed circuit examples and extensive illustrations. The pros and cons of various methods of analysis, fundamental applications of electronic hardware, and issues in logic design are also thoroughly examined. The author draws on more than tw

  10. Appcessory Economics: Enabling loosely coupled hardware / software innovation

    OpenAIRE

    Holtman, Koen

    2012-01-01

    An appcessory (app + accessory) is a smart phone accessory that is combined with a specially written app to perform a useful function. An example is a toy helicopter controlled by a smart phone app: the full value proposition involves both new hardware outside the phone and new software running inside the phone. Like the smart phone itself and like a PC, the appcessory hardware is a platform: it has the property that it becomes even more valuable if innovative new software is written for it. ...

  11. Grey Energy and Environmental Impacts of ICT Hardware

    OpenAIRE

    Hischier, Roland; Coroama, Vlad C.; Schien, Daniel; Ahmadi Achachlouei, Mohammad

    2015-01-01

    Direct energy consumption of ICT hardware is only “half the story.” In order to get the “whole story,” energy consumption during the entire life cycle has to be taken into account. This chapter is a first step toward a more comprehensive picture, showing the “grey energy” (i.e., the overall energy requirements) as well as the releases (into air, water, and soil) during the entire life cycle of exemplary ICT hardware devices by applying the life cycle assessment method. The examples calculated...

  12. Realizable Hardware-Based Method for Digital Modulation Classification

    Institute of Scientific and Technical Information of China (English)

    HAN Li; WAN Jin-bo

    2005-01-01

    A new method suited for hardware implementation is developed to classify 8 different digital modulation types with raised cosine base-band impulse without knowing the carrier frequency and symbol timing. The normalized histogram of stagnation points for instantaneous parameters is used to recognize both ideal rectangular and raised cosine base-band digital signals. Carrier frequency estimation is used to enhance the recognition rate of phase-modulated signals. In the condition of 10 dB signal noise ratio (SNR), the recognizing rate is over 80 %. The new algorithm is suited for hardware implementation.

  13. Progress on the NSTX Center Stack Upgrade

    Energy Technology Data Exchange (ETDEWEB)

    L. Dudek, J. Chrzanowski, P. Heitzenroeder, D. Mangra, C. Neumeyer, M. Smith, R. Strykowsky, P. Titus, T. Willard

    2010-09-22

    The National Spherical Torus Experiment (NSTX) will be upgraded to provide increased toroidal field, plasma current and pulse length. This involves the replacement of the so-called center stack, including the inner legs of the Toroidal Field (TF) coil, the Ohmic Heating (OH) coil, and the inner Poloidal Field (PF) coils. In addition the increased performance of the upgrade requires qualification of remaining existing components for higher loads. Initial conceptual design efforts were based on worst-case combinations of possible currents that the power supplies could deliver. This proved to be an onerous requirement and caused many of the outer coils support structures to require costly heavy reinforcement. This has led to the planned implementation of a Digital Coil Protection System (DCPS) to reduce design-basis loads to levels that are more realistic and manageable. As a minimum, all components must be qualified for the increase in normal operating loads with headroom. Design features and analysis efforts needed to meet the upgrade loading are discussed. Mission and features of the DCPS are presented.

  14. Lithiation-induced shuffling of atomic stacks

    KAUST Repository

    Nie, Anmin

    2014-09-10

    In rechargeable lithium-ion batteries, understanding the atomic-scale mechanism of Li-induced structural evolution occurring at the host electrode materials provides essential knowledge for design of new high performance electrodes. Here, we report a new crystalline-crystalline phase transition mechanism in single-crystal Zn-Sb intermetallic nanowires upon lithiation. Using in situ transmission electron microscopy, we observed that stacks of atomic planes in an intermediate hexagonal (h-)LiZnSb phase are "shuffled" to accommodate the geometrical confinement stress arising from lamellar nanodomains intercalated by lithium ions. Such atomic rearrangement arises from the anisotropic lithium diffusion and is accompanied by appearance of partial dislocations. This transient structure mediates further phase transition from h-LiZnSb to cubic (c-)Li2ZnSb, which is associated with a nearly "zero-strain" coherent interface viewed along the [001]h/[111]c directions. This study provides new mechanistic insights into complex electrochemically driven crystalline-crystalline phase transitions in lithium-ion battery electrodes and represents a noble example of atomic-level structural and interfacial rearrangements.

  15. Progress on NSTX center stack upgrade

    Energy Technology Data Exchange (ETDEWEB)

    Dudek, L., E-mail: ldudek@pppl.gov [Princeton Plasma Physics Laboratory (PPPL), Princeton, NJ 08543 (United States); Chrzanowski, J.; Heitzenroeder, P.; Mangra, D.; Neumeyer, C.; Smith, M.; Strykowsky, R.; Titus, P.; Willard, T. [Princeton Plasma Physics Laboratory (PPPL), Princeton, NJ 08543 (United States)

    2012-09-15

    The national spherical torus experiment (NSTX) will be upgraded to provide increased toroidal field, plasma current and pulse length. This involves the replacement of the so-called center stack, including the inner legs of the toroidal field (TF) coil, the Ohmic heating (OH) coil, and the inner poloidal field (PF) coils. In addition the increased performance of the upgrade requires qualification of remaining existing components for higher loads. Initial conceptual design efforts were based on worst-case combinations of possible currents that the power supplies could deliver. This proved to be an onerous requirement and caused many of the outer coils support structures to require costly heavy reinforcement. This has led to the planned implementation of a digital coil protection system (DCPS) to reduce design-basis loads to levels that are more realistic and manageable. As a minimum, all components must be qualified for the increase in normal operating loads with headroom. Design features and analysis efforts needed to meet the upgrade loading are discussed. Mission and features of the DCPS are presented.

  16. Stacking for machine learning redshifts applied to SDSS galaxies

    CERN Document Server

    Zitlau, Roman; Paech, Kerstin; Weller, Jochen; Rau, Markus Michael; Seitz, Stella

    2016-01-01

    We present an analysis of a general machine learning technique called 'stacking' for the estimation of photometric redshifts. Stacking techniques can feed the photometric redshift estimate, as output by a base algorithm, back into the same algorithm as an additional input feature in a subsequent learning round. We shown how all tested base algorithms benefit from at least one additional stacking round (or layer). To demonstrate the benefit of stacking, we apply the method to both unsupervised machine learning techniques based on self-organising maps (SOMs), and supervised machine learning methods based on decision trees. We explore a range of stacking architectures, such as the number of layers and the number of base learners per layer. Finally we explore the effectiveness of stacking even when using a successful algorithm such as AdaBoost. We observe a significant improvement of between 1.9% and 21% on all computed metrics when stacking is applied to weak learners (such as SOMs and decision trees). When appl...

  17. Stacking for machine learning redshifts applied to SDSS galaxies

    Science.gov (United States)

    Zitlau, Roman; Hoyle, Ben; Paech, Kerstin; Weller, Jochen; Rau, Markus Michael; Seitz, Stella

    2016-08-01

    We present an analysis of a general machine learning technique called `stacking' for the estimation of photometric redshifts. Stacking techniques can feed the photometric redshift estimate, as output by a base algorithm, back into the same algorithm as an additional input feature in a subsequent learning round. We show how all tested base algorithms benefit from at least one additional stacking round (or layer). To demonstrate the benefit of stacking, we apply the method to both unsupervised machine learning techniques based on self-organizing maps (SOMs), and supervised machine learning methods based on decision trees. We explore a range of stacking architectures, such as the number of layers and the number of base learners per layer. Finally we explore the effectiveness of stacking even when using a successful algorithm such as AdaBoost. We observe a significant improvement of between 1.9 per cent and 21 per cent on all computed metrics when stacking is applied to weak learners (such as SOMs and decision trees). When applied to strong learning algorithms (such as AdaBoost) the ratio of improvement shrinks, but still remains positive and is between 0.4 per cent and 2.5 per cent for the explored metrics and comes at almost no additional computational cost.

  18. Diagnosis of PEM fuel cell stack dynamic behaviors

    Science.gov (United States)

    Chen, Jixin; Zhou, Biao

    In this study, the steady-state performance and dynamic behavior of a commercial 10-cell Proton Exchange Membrane (PEM) fuel cell stack was experimentally investigated using a self-developed PEM fuel cell test stand. The start-up characteristics of the stack to different current loads and dynamic responses after current step-up to an elevated load were investigated. The stack voltage was observed to experience oscillation at air excess coefficient of 2 due to the flooding/recovery cycle of part of the cells. In order to correlate the stack voltage with the pressure drop across the cathode/anode, fast Fourier transform was performed. Dominant frequency of pressure drop signal was obtained to indicate the water behavior in cathode/anode, thereby predicting the stack voltage change. Such relationship between frequency of pressure drop and stack voltage was found and summarized. This provides an innovative approach to utilize frequency of pressure drop signal as a diagnostic tool for PEM fuel cell stack dynamic behaviors.

  19. Separated Control and Data Stacks to Mitigate Buffer Overflow Exploits

    Directory of Open Access Journals (Sweden)

    Christopher Kugler

    2015-10-01

    Full Text Available Despite the fact that protection mechanisms like StackGuard, ASLR and NX are widespread, the development on new defense strategies against stack-based buffer overflows has not yet come to an end. In this article, we present a novel compiler-level protection called SCADS: Separated Control and Data Stacks that protects return addresses and saved frame pointers on a separate stack, called the control stack. In common computer programs, a single user mode stack is used to store control information next to data buffers. By separating control information from the data stack, we can protect sensitive pointers of a program’s control flow from being overwritten by buffer overflows. To substantiate the practicability of our approach, we provide SCADS as an open source patch for the LLVM compiler infrastructure. Focusing on Linux and FreeBSD running on the AMD64 architecture, we show compatibility, security and performance results. As we make control flow information simply unreachable for buffer overflows, many exploits are stopped at an early stage of progression with only negligible performance overhead.

  20. Postflight hardware evaluation 360T021 (RSRM-21, STS-45), revision A

    Science.gov (United States)

    Maccauly, Linda E.

    1992-12-01

    The Final Postflight Hardware Evaluation Report 360T021 (RSRM-21, STS-45) is included. All observed hardware conditions were documented on Postflight Observation Reports (PFOR's) and included in Appendices A through E. This report, along with the KSC Ten-Day Postflight Hardware Evaluation Report represents a summary of the 360T021 hardware evaluation.